#include <stdio.h>
//#include <omp.h>
#include <string.h>
#include <math.h>
//#include "../common/common.h"
#include <cuda_runtime.h>

/*
 * compute string value, length should be small than strlen
 */
int compute_value(char *str, int length, int d, int q)
{
	int i = 0;
	int p0 = 0;

	for (i = 0; i < length; ++i) {
		p0 = (d * p0 + (str[i] /*- '0'*/ )) % q;
	}

	return p0;

}

int rk_matcher(char *str, char *pattern, int d, int q)
{
	int i = 0, j = 0;
	int str_length = strlen(str);
	int pattern_length = strlen(pattern);
	int p0 = 0;
	int ts[str_length];

	/* This code block prints what is inside the matrix
	   for (i=0;i<num_cores;i++)
	   {
	   for (j=0;j<el_chunk_len;j++)
	   if (tss[i][j]==0)
	   printf("%c", '0');
	   else
	   printf("%c", tss[i][j]);
	   printf("\n");
	   }
	 */

	//hash value of the pattern
	p0 = compute_value(pattern, pattern_length, d, q);

	//hash value of the first char
	ts[0] = compute_value(str, pattern_length, d, q);

	//p does not change, calculate once
	int p = pow(d, pattern_length - 1);
	for (i = 1; i < str_length - pattern_length + 1; i++) {
		ts[i] = ((str[i + pattern_length - 1]) * p
			 + (ts[i - 1] - (str[i - 1])) / d) % q;
		/*      (ts[i - 1] * d -
		   ((str[i - 1] - '0') * (int) pow(d,
		   pattern_length))) % q +
		   (str[i + pattern_length - 1]
		   - '0') % q; */
	}

/*    for (i=0;i<str_length-pattern_length+1;i++)
    {
    	printf("%d ", ts[i]);
    }*/

	for (i = 0; i <= str_length - pattern_length + 1; ++i) {
		if (ts[i] == p0) {
			for (j = 0; j < pattern_length; ++j) {
				if (pattern[j] != str[i + j]) {
					break;
				} else if (j == pattern_length - 1) {
					printf("%d\n", i);
				}
			}
		}
	}

	return 0;

}

__global__ void findHashes(char *d_css, int d_len, int *d_iss,
			   int pattern_length, int d, /*int q,*/ int p)
{
	int i = 0;
	int ind = d_len * threadIdx.x;
	d_iss += ind;
	d_css += ind;
	d_iss[0] = 0;
//      printf("%d %d %d %d %d %d", d_iss[0], d_len, pattern_length, d, q, p);
	int pw = 1;
	for (; i < pattern_length; i++) {
		d_iss[0] += pw * (d_css[i]);
		pw *= d;
	}
	//d_iss[0] %= q;
	//printf("%d ", d_iss[0]);

	for (i = 1; i < d_len - pattern_length + 1; i++) {
		d_iss[i] = ((d_css[i + pattern_length - 1]) * p
			    + (d_iss[i - 1] - (d_css[i - 1])) / d); //% q;
        //printf("%d ",d_iss[i]);
	}

}

__global__ void seekPattern(char *d_css, int d_len, int *d_iss,
                int pattern_length, char* pattern, int d, int p0) 
{
	int i = 0;
        int j=0;
	int ind = d_len * threadIdx.x;
	d_iss += ind;
	d_css += ind;

	for (i = 0; i < d_len - pattern_length + 1; i++) {
		if (d_iss[i] == p0) {
			for (j = 0; j < pattern_length; j++) {
				if (pattern[j] != d_css[i + j]) {
					break;
				} else if (j == pattern_length - 1) {

			//		printf("ThreadId: %d\n", threadIdx.x);
					printf("pos:%d\n", threadIdx.x*(d_len-pattern_length+1)+i-pattern_length+1);
				}
			}
		}
	}

}
int main(int argc, char *argv[])
{
	int i = 0;
	int j = 0;
	char str[] = "bababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaver";
	char pattern[] = "aba";
	int d = 3;
	//int q = 50000;
	int num_cores = 8;

	//CHECK(cudaDeviceReset());

	int str_length = strlen(str);
	//int nElem=str_length;
	int pattern_length = strlen(pattern);
	int chunk_len = (int)ceil((float)str_length / num_cores);
	int padding_len = chunk_len * num_cores - str_length;
	int el_chunk_len = chunk_len + pattern_length - 1;

	//matrix on host which holds the characters, each row will go to a core
	char css[num_cores][el_chunk_len];
	int iss[num_cores][el_chunk_len];
	//on the device
	char *d_css;
        char *d_pattern;
	//hashes on the device
	int *d_iss;
	int nchars = num_cores * el_chunk_len;
	cudaMalloc((char **)&d_css, nchars * sizeof(char));
	cudaMalloc((int **)&d_iss, nchars * sizeof(int));
        cudaMalloc((char **)&d_pattern, pattern_length*sizeof(char));

	//initial zeroes
	for (i = 0; i < pattern_length - 1; i++)
		css[0][i] = 0;

	//first n-1 cores' characters
	for (i = 0; i < num_cores - 1; i++)
		for (j = 0; j < chunk_len; j++)
			css[i][j + pattern_length - 1] = str[i * chunk_len + j];

	//last core's characters
	for (i = (num_cores - 1) * chunk_len, j = 0; i < str_length; i++, j++)
		css[num_cores - 1][j + pattern_length - 1] = str[i];

	//last n-1 cores' padding characters
	for (i = 1; i < num_cores; i++)
		for (j = 0; j < pattern_length - 1; j++)
			css[i][j] = css[i - 1][j + chunk_len];

	//last core's last paddings
	for (i = 0; i < padding_len; i++)
		css[num_cores - 1][el_chunk_len - i - 1] = 0;

	//transfer css to device
	cudaMemcpy(d_css, css, nchars, cudaMemcpyHostToDevice);
	cudaMemcpy(d_css, css, nchars, cudaMemcpyHostToDevice);
	cudaMemcpy(d_pattern, pattern, pattern_length, cudaMemcpyHostToDevice);

	dim3 block(num_cores);	//str_length/pattern_length
	//__global__ void findHashes(char *d_css, int d_len, int *d_iss, int pattern_length, int d, int q, int p)
	int p = pow(d, pattern_length - 1);
	findHashes <<< 1, num_cores >>> (d_css, el_chunk_len, d_iss,
					 pattern_length, d, /*q,*/ p);

        //find the hash of the pattern
        int pw = 1;
        int p0=0;
        for (i=0; i < pattern_length; i++) {
            p0 += pw * (pattern[i]);
            pw *= d;
        }
	//printf("%d\n", p0);
        
        seekPattern<<<1, num_cores>>>(d_css, el_chunk_len, d_iss,
                pattern_length, d_pattern, d, p0); 

	//printf("%d %d %d %d %d \n", el_chunk_len, pattern_length, d, q, p);

	//cudaMemcpy(iss, d_iss, nchars * sizeof(int), cudaMemcpyDeviceToHost);
	/*for (i=0;i<num_cores;i++)
	   {
	   for (j=0;j<el_chunk_len;j++)
	   	printf("%d ", iss[i][j]);
	   printf("\n");
	   } 
	*/
	cudaFree(d_iss);
	cudaFree(d_css);

	//int pos = rk_matcher(str, pattern, d, q);
	//printf("%d", pos);
	return 0;
}

	.file	"tmpxft_00271475_00000000-6_rabin.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13compute_valuePciii
	.type	_Z13compute_valuePciii, @function
_Z13compute_valuePciii:
.LFB2027:
	.cfi_startproc
	endbr64
	movq	%rdi, %r8
	movl	%edx, %r9d
	xorl	%edi, %edi
	xorl	%edx, %edx
.L3:
	cmpl	%edi, %esi
	jle	.L6
	imull	%r9d, %edx
	movsbl	(%r8,%rdi), %eax
	incq	%rdi
	addl	%edx, %eax
	cltd
	idivl	%ecx
	jmp	.L3
.L6:
	movl	%edx, %eax
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z13compute_valuePciii, .-_Z13compute_valuePciii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d\n"
	.text
	.globl	_Z10rk_matcherPcS_ii
	.type	_Z10rk_matcherPcS_ii, @function
_Z10rk_matcherPcS_ii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	movl	%edx, %r12d
	pushq	%rbx
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	subq	$56, %rsp
	movl	%ecx, -76(%rbp)
	movq	%rsi, -72(%rbp)
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	call	strlen@PLT
	movq	-72(%rbp), %rdi
	movq	%rax, %r15
	movl	%eax, -84(%rbp)
	call	strlen@PLT
	movslq	%r15d, %r15
	movq	%rsp, %rcx
	leaq	15(,%r15,4), %rdx
	movq	%rax, %r10
	movl	%eax, %r13d
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rcx
.L8:
	cmpq	%rcx, %rsp
	je	.L9
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L8
.L9:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L10
	orq	$0, -8(%rsp,%rax)
.L10:
	movl	-76(%rbp), %ecx
	movq	-72(%rbp), %rdi
	leaq	3(%rsp), %r8
	movl	%r13d, %esi
	movq	%r8, %r11
	cvtsi2sdl	%r12d, %xmm0
	andq	$-4, %r8
	movl	%r12d, %edx
	movq	%r8, %r14
	shrq	$2, %r11
	call	_Z13compute_valuePciii
	movq	%rbx, %rdi
	movl	%r12d, %edx
	movl	%eax, %r15d
	call	_Z13compute_valuePciii
	movl	%eax, 0(,%r11,4)
	leal	-1(%r10), %eax
	cvtsi2sdl	%eax, %xmm1
	movl	%eax, -80(%rbp)
	call	pow@PLT
	movl	-84(%rbp), %r9d
	movslq	%r13d, %rsi
	xorl	%ecx, %ecx
	cvttsd2sil	%xmm0, %edi
	addq	%rbx, %rsi
	subl	%r13d, %r9d
.L11:
	incq	%rcx
	cmpl	%ecx, %r9d
	jl	.L24
	movsbl	-1(%rbx,%rcx), %edx
	movl	-4(%r14,%rcx,4), %eax
	subl	%edx, %eax
	cltd
	idivl	%r12d
	movsbl	-1(%rsi,%rcx), %edx
	imull	%edi, %edx
	addl	%edx, %eax
	cltd
	idivl	-76(%rbp)
	movl	%edx, (%r14,%rcx,4)
	jmp	.L11
.L24:
	xorl	%r12d, %r12d
.L13:
	leal	1(%r9), %eax
	cmpl	%r12d, %eax
	jl	.L25
	cmpl	%r15d, (%r14,%r12,4)
	jne	.L14
	movl	%r12d, -76(%rbp)
	xorl	%r10d, %r10d
	jmp	.L15
.L26:
	cmpl	%eax, -80(%rbp)
	jne	.L16
	movl	-76(%rbp), %edx
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	movq	%r10, -96(%rbp)
	movl	$2, %edi
	movl	%r9d, -84(%rbp)
	call	__printf_chk@PLT
	movq	-96(%rbp), %r10
	movl	-84(%rbp), %r9d
.L16:
	incq	%r10
.L15:
	movl	%r10d, %eax
	cmpl	%r10d, %r13d
	jle	.L14
	movq	-72(%rbp), %rsi
	leaq	(%rbx,%r12), %rdx
	movb	(%rdx,%r10), %dil
	cmpb	%dil, (%rsi,%r10)
	je	.L26
.L14:
	incq	%r12
	jmp	.L13
.L25:
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10rk_matcherPcS_ii, .-_Z10rk_matcherPcS_ii
	.globl	_Z36__device_stub__Z10findHashesPciPiiiiPciPiiii
	.type	_Z36__device_stub__Z10findHashesPciPiiiiPciPiiii, @function
_Z36__device_stub__Z10findHashesPciPiiiiPciPiiii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z10findHashesPciPiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L27:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z36__device_stub__Z10findHashesPciPiiiiPciPiiii, .-_Z36__device_stub__Z10findHashesPciPiiiiPciPiiii
	.globl	_Z10findHashesPciPiiii
	.type	_Z10findHashesPciPiiii, @function
_Z10findHashesPciPiiii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10findHashesPciPiiiiPciPiiii
	.cfi_endproc
.LFE2055:
	.size	_Z10findHashesPciPiiii, .-_Z10findHashesPciPiiii
	.globl	_Z39__device_stub__Z11seekPatternPciPiiS_iiPciPiiS_ii
	.type	_Z39__device_stub__Z11seekPatternPciPiiS_iiPciPiiS_ii, @function
_Z39__device_stub__Z11seekPatternPciPiiS_iiPciPiiS_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z11seekPatternPciPiiS_ii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L32:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z39__device_stub__Z11seekPatternPciPiiS_iiPciPiiS_ii, .-_Z39__device_stub__Z11seekPatternPciPiiS_iiPciPiiS_ii
	.globl	_Z11seekPatternPciPiiS_ii
	.type	_Z11seekPatternPciPiiS_ii, @function
_Z11seekPatternPciPiiS_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z11seekPatternPciPiiS_iiPciPiiS_ii
	.cfi_endproc
.LFE2057:
	.size	_Z11seekPatternPciPiiS_ii, .-_Z11seekPatternPciPiiS_ii
	.section	.rodata.str1.1
.LC1:
	.string	"bababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaver"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC1(%rip), %rsi
	movl	$106, %ecx
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	leaq	-162(%rbp), %rdi
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$216, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	movl	$6382177, -166(%rbp)
	rep movsb
	leaq	-162(%rbp), %rdi
	call	strlen@PLT
	movq	%rax, %r12
	movl	%eax, -252(%rbp)
	leaq	-166(%rbp), %rax
	movq	%rax, %rdi
	movq	%rax, -248(%rbp)
	call	strlen@PLT
	cvtsi2ssl	%r12d, %xmm0
	mulss	.LC2(%rip), %xmm0
	movq	%rax, %r13
	movl	%eax, -228(%rbp)
	call	ceilf@PLT
	movq	%rsp, %rsi
	cvttss2sil	%xmm0, %ebx
	leal	0(,%rbx,8), %eax
	subl	%r12d, %eax
	leal	(%rbx,%r13), %r12d
	movl	%eax, -256(%rbp)
	leal	-1(%r12), %eax
	movslq	%eax, %r14
	movl	%eax, -232(%rbp)
	leaq	0(,%r14,8), %rax
	leaq	15(%rax), %rcx
	movq	%rax, -240(%rbp)
	movq	%rcx, %rax
	andq	$-4096, %rcx
	andq	$-16, %rax
	subq	%rcx, %rsi
.L38:
	cmpq	%rsi, %rsp
	je	.L39
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L38
.L39:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L40
	orq	$0, -8(%rsp,%rax)
.L40:
	movq	-240(%rbp), %rsi
	leaq	-216(%rbp), %rdi
	movq	%rsp, %r15
	call	cudaMalloc@PLT
	movq	%r14, %rsi
	leaq	-200(%rbp), %rdi
	salq	$5, %rsi
	call	cudaMalloc@PLT
	leaq	-208(%rbp), %rdi
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movl	-228(%rbp), %edx
	xorl	%eax, %eax
	leal	-1(%rdx), %r9d
.L41:
	cmpl	%eax, %r9d
	jle	.L66
	movb	$0, (%r15,%rax)
	incq	%rax
	jmp	.L41
.L66:
	leaq	(%r15,%r13), %r10
	xorl	%esi, %esi
	movl	$7, %edi
	leaq	-162(%rbp), %r11
.L43:
	movslq	%esi, %rcx
	xorl	%eax, %eax
	addq	%r11, %rcx
.L46:
	cmpl	%eax, %ebx
	jle	.L67
	movb	(%rcx,%rax), %dl
	movb	%dl, -1(%r10,%rax)
	incq	%rax
	jmp	.L46
.L67:
	addl	%ebx, %esi
	addq	%r14, %r10
	decl	%edi
	jne	.L43
	imulq	$7, %r14, %rsi
	imull	$7, %ebx, %eax
	leaq	0(%r13,%rsi), %rcx
	cltq
	addq	%r15, %rcx
.L47:
	incq	%rcx
	cmpl	%eax, -252(%rbp)
	jle	.L68
	movb	-162(%rbp,%rax), %dil
	incq	%rax
	movb	%dil, -2(%rcx)
	jmp	.L47
.L68:
	movslq	%ebx, %rbx
	leaq	(%r15,%r14), %rcx
	movl	$7, %edi
	subq	%r14, %rbx
.L51:
	xorl	%eax, %eax
	leaq	(%rbx,%rcx), %r10
.L53:
	cmpl	%eax, %r9d
	jle	.L69
	movb	(%r10,%rax), %r11b
	movb	%r11b, (%rcx,%rax)
	incq	%rax
	jmp	.L53
.L69:
	addq	%r14, %rcx
	decl	%edi
	jne	.L51
	movslq	%r12d, %r12
	xorl	%eax, %eax
	addq	%rsi, %r12
	addq	%r15, %r12
.L52:
	movl	-256(%rbp), %ebx
	decq	%r12
	cmpl	%ebx, %eax
	jge	.L70
	movb	$0, -1(%r12)
	incl	%eax
	jmp	.L52
.L70:
	movq	-240(%rbp), %rdx
	movq	-216(%rbp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	%r9d, -252(%rbp)
	call	cudaMemcpy@PLT
	movq	-240(%rbp), %rdx
	movl	$1, %ecx
	movq	%r15, %rsi
	movq	-216(%rbp), %rdi
	call	cudaMemcpy@PLT
	movq	-248(%rbp), %rsi
	movl	$1, %ecx
	movq	%r13, %rdx
	movq	-208(%rbp), %rdi
	call	cudaMemcpy@PLT
	movl	-252(%rbp), %r9d
	movsd	.LC3(%rip), %xmm0
	cvtsi2sdl	%r9d, %xmm1
	call	pow@PLT
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$3, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movsd	%xmm0, -240(%rbp)
	movq	%rdx, -180(%rbp)
	movl	$1, -172(%rbp)
	movq	%rdi, -192(%rbp)
	movl	$1, -184(%rbp)
	call	__cudaPushCallConfiguration@PLT
	movsd	-240(%rbp), %xmm0
	testl	%eax, %eax
	jne	.L55
	cvttsd2sil	%xmm0, %r9d
	movl	-228(%rbp), %ecx
	movq	-200(%rbp), %rdx
	movl	$3, %r8d
	movl	-232(%rbp), %esi
	movq	-216(%rbp), %rdi
	call	_Z36__device_stub__Z10findHashesPciPiiiiPciPiiii
.L55:
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	movl	$1, %edx
.L56:
	cmpl	%eax, -228(%rbp)
	jle	.L71
	movq	-248(%rbp), %rsi
	movsbl	(%rsi,%rax), %ecx
	incq	%rax
	imull	%edx, %ecx
	leal	(%rdx,%rdx,2), %edx
	addl	%ecx, %ebx
	jmp	.L56
.L71:
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$3, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, -172(%rbp)
	movq	%rdx, -180(%rbp)
	movq	%rdi, -192(%rbp)
	movl	$1, -184(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L58
	pushq	%rax
	movl	-228(%rbp), %ecx
	movl	$3, %r9d
	movq	-200(%rbp), %rdx
	movq	-208(%rbp), %r8
	pushq	%rbx
	movl	-232(%rbp), %esi
	movq	-216(%rbp), %rdi
	call	_Z39__device_stub__Z11seekPatternPciPiiS_iiPciPiiS_ii
	popq	%rdx
	popq	%rcx
.L58:
	movq	-200(%rbp), %rdi
	call	cudaFree@PLT
	movq	-216(%rbp), %rdi
	call	cudaFree@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L59
	call	__stack_chk_fail@PLT
.L59:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z11seekPatternPciPiiS_ii"
.LC6:
	.string	"_Z10findHashesPciPiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11seekPatternPciPiiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10findHashesPciPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	1040187392
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1074266112
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
//#include <omp.h>
#include <string.h>
#include <math.h>
//#include "../common/common.h"
#include <hip/hip_runtime.h>

/*
 * compute string value, length should be small than strlen
 */
int compute_value(char *str, int length, int d, int q)
{
	int i = 0;
	int p0 = 0;

	for (i = 0; i < length; ++i) {
		p0 = (d * p0 + (str[i] /*- '0'*/ )) % q;
	}

	return p0;

}

int rk_matcher(char *str, char *pattern, int d, int q)
{
	int i = 0, j = 0;
	int str_length = strlen(str);
	int pattern_length = strlen(pattern);
	int p0 = 0;
	int ts[str_length];

	/* This code block prints what is inside the matrix
	   for (i=0;i<num_cores;i++)
	   {
	   for (j=0;j<el_chunk_len;j++)
	   if (tss[i][j]==0)
	   printf("%c", '0');
	   else
	   printf("%c", tss[i][j]);
	   printf("\n");
	   }
	 */

	//hash value of the pattern
	p0 = compute_value(pattern, pattern_length, d, q);

	//hash value of the first char
	ts[0] = compute_value(str, pattern_length, d, q);

	//p does not change, calculate once
	int p = pow(d, pattern_length - 1);
	for (i = 1; i < str_length - pattern_length + 1; i++) {
		ts[i] = ((str[i + pattern_length - 1]) * p
			 + (ts[i - 1] - (str[i - 1])) / d) % q;
		/*      (ts[i - 1] * d -
		   ((str[i - 1] - '0') * (int) pow(d,
		   pattern_length))) % q +
		   (str[i + pattern_length - 1]
		   - '0') % q; */
	}

/*    for (i=0;i<str_length-pattern_length+1;i++)
    {
    	printf("%d ", ts[i]);
    }*/

	for (i = 0; i <= str_length - pattern_length + 1; ++i) {
		if (ts[i] == p0) {
			for (j = 0; j < pattern_length; ++j) {
				if (pattern[j] != str[i + j]) {
					break;
				} else if (j == pattern_length - 1) {
					printf("%d\n", i);
				}
			}
		}
	}

	return 0;

}

__global__ void findHashes(char *d_css, int d_len, int *d_iss,
			   int pattern_length, int d, /*int q,*/ int p)
{
	int i = 0;
	int ind = d_len * threadIdx.x;
	d_iss += ind;
	d_css += ind;
	d_iss[0] = 0;
//      printf("%d %d %d %d %d %d", d_iss[0], d_len, pattern_length, d, q, p);
	int pw = 1;
	for (; i < pattern_length; i++) {
		d_iss[0] += pw * (d_css[i]);
		pw *= d;
	}
	//d_iss[0] %= q;
	//printf("%d ", d_iss[0]);

	for (i = 1; i < d_len - pattern_length + 1; i++) {
		d_iss[i] = ((d_css[i + pattern_length - 1]) * p
			    + (d_iss[i - 1] - (d_css[i - 1])) / d); //% q;
        //printf("%d ",d_iss[i]);
	}

}

__global__ void seekPattern(char *d_css, int d_len, int *d_iss,
                int pattern_length, char* pattern, int d, int p0) 
{
	int i = 0;
        int j=0;
	int ind = d_len * threadIdx.x;
	d_iss += ind;
	d_css += ind;

	for (i = 0; i < d_len - pattern_length + 1; i++) {
		if (d_iss[i] == p0) {
			for (j = 0; j < pattern_length; j++) {
				if (pattern[j] != d_css[i + j]) {
					break;
				} else if (j == pattern_length - 1) {

			//		printf("ThreadId: %d\n", threadIdx.x);
					printf("pos:%d\n", threadIdx.x*(d_len-pattern_length+1)+i-pattern_length+1);
				}
			}
		}
	}

}
int main(int argc, char *argv[])
{
	int i = 0;
	int j = 0;
	char str[] = "bababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaver";
	char pattern[] = "aba";
	int d = 3;
	//int q = 50000;
	int num_cores = 8;

	//CHECK(cudaDeviceReset());

	int str_length = strlen(str);
	//int nElem=str_length;
	int pattern_length = strlen(pattern);
	int chunk_len = (int)ceil((float)str_length / num_cores);
	int padding_len = chunk_len * num_cores - str_length;
	int el_chunk_len = chunk_len + pattern_length - 1;

	//matrix on host which holds the characters, each row will go to a core
	char css[num_cores][el_chunk_len];
	int iss[num_cores][el_chunk_len];
	//on the device
	char *d_css;
        char *d_pattern;
	//hashes on the device
	int *d_iss;
	int nchars = num_cores * el_chunk_len;
	hipMalloc((char **)&d_css, nchars * sizeof(char));
	hipMalloc((int **)&d_iss, nchars * sizeof(int));
        hipMalloc((char **)&d_pattern, pattern_length*sizeof(char));

	//initial zeroes
	for (i = 0; i < pattern_length - 1; i++)
		css[0][i] = 0;

	//first n-1 cores' characters
	for (i = 0; i < num_cores - 1; i++)
		for (j = 0; j < chunk_len; j++)
			css[i][j + pattern_length - 1] = str[i * chunk_len + j];

	//last core's characters
	for (i = (num_cores - 1) * chunk_len, j = 0; i < str_length; i++, j++)
		css[num_cores - 1][j + pattern_length - 1] = str[i];

	//last n-1 cores' padding characters
	for (i = 1; i < num_cores; i++)
		for (j = 0; j < pattern_length - 1; j++)
			css[i][j] = css[i - 1][j + chunk_len];

	//last core's last paddings
	for (i = 0; i < padding_len; i++)
		css[num_cores - 1][el_chunk_len - i - 1] = 0;

	//transfer css to device
	hipMemcpy(d_css, css, nchars, hipMemcpyHostToDevice);
	hipMemcpy(d_css, css, nchars, hipMemcpyHostToDevice);
	hipMemcpy(d_pattern, pattern, pattern_length, hipMemcpyHostToDevice);

	dim3 block(num_cores);	//str_length/pattern_length
	//__global__ void findHashes(char *d_css, int d_len, int *d_iss, int pattern_length, int d, int q, int p)
	int p = pow(d, pattern_length - 1);
	findHashes <<< 1, num_cores >>> (d_css, el_chunk_len, d_iss,
					 pattern_length, d, /*q,*/ p);

        //find the hash of the pattern
        int pw = 1;
        int p0=0;
        for (i=0; i < pattern_length; i++) {
            p0 += pw * (pattern[i]);
            pw *= d;
        }
	//printf("%d\n", p0);
        
        seekPattern<<<1, num_cores>>>(d_css, el_chunk_len, d_iss,
                pattern_length, d_pattern, d, p0); 

	//printf("%d %d %d %d %d \n", el_chunk_len, pattern_length, d, q, p);

	//cudaMemcpy(iss, d_iss, nchars * sizeof(int), cudaMemcpyDeviceToHost);
	/*for (i=0;i<num_cores;i++)
	   {
	   for (j=0;j<el_chunk_len;j++)
	   	printf("%d ", iss[i][j]);
	   printf("\n");
	   } 
	*/
	hipFree(d_iss);
	hipFree(d_css);

	//int pos = rk_matcher(str, pattern, d, q);
	//printf("%d", pos);
	return 0;
}

	.text
	.file	"rabin.hip"
	.globl	_Z13compute_valuePciii          # -- Begin function _Z13compute_valuePciii
	.type	_Z13compute_valuePciii,@function
_Z13compute_valuePciii:                 # @_Z13compute_valuePciii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB0_1
# %bb.2:                                # %.lr.ph.preheader
	movl	%edx, %r8d
	movl	%esi, %esi
	xorl	%r9d, %r9d
	xorl	%edx, %edx
.LBB0_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	imull	%r8d, %edx
	movsbl	(%rdi,%r9), %eax
	addl	%edx, %eax
	cltd
	idivl	%ecx
	incq	%r9
	cmpq	%r9, %rsi
	jne	.LBB0_3
	jmp	.LBB0_4
.LBB0_1:
	xorl	%edx, %edx
.LBB0_4:                                # %._crit_edge
	movl	%edx, %eax
	retq
.Lfunc_end0:
	.size	_Z13compute_valuePciii, .Lfunc_end0-_Z13compute_valuePciii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10rk_matcherPcS_ii            # -- Begin function _Z10rk_matcherPcS_ii
	.type	_Z10rk_matcherPcS_ii,@function
_Z10rk_matcherPcS_ii:                   # @_Z10rk_matcherPcS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, -48(%rbp)                 # 4-byte Spill
	movl	%edx, %r15d
	movq	%rsi, %rbx
	movq	%rdi, %r14
	callq	strlen
	movq	%rax, -64(%rbp)                 # 8-byte Spill
	movl	%eax, %r12d
	movq	%rbx, -72(%rbp)                 # 8-byte Spill
	movq	%rbx, %rdi
	callq	strlen
	movl	%r12d, %r9d
	movq	%rax, %rbx
	movl	%r12d, %eax
	movq	%rsp, %r13
	leaq	15(,%rax,4), %rax
	andq	$-16, %rax
	subq	%rax, %r13
	movq	%r13, %rsp
	testl	%ebx, %ebx
	movq	%r13, -88(%rbp)                 # 8-byte Spill
	movl	%r12d, -80(%rbp)                # 4-byte Spill
	jle	.LBB1_1
# %bb.2:                                # %.lr.ph.preheader.i
	movl	%ebx, %ecx
	xorl	%esi, %esi
	xorl	%edx, %edx
	movq	-72(%rbp), %rdi                 # 8-byte Reload
	movl	-48(%rbp), %r8d                 # 4-byte Reload
.LBB1_3:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	imull	%r15d, %edx
	movsbl	(%rdi,%rsi), %eax
	addl	%edx, %eax
	cltd
	idivl	%r8d
	incq	%rsi
	cmpq	%rsi, %rcx
	jne	.LBB1_3
# %bb.4:                                # %.lr.ph.i51.preheader
	movl	%edx, -52(%rbp)                 # 4-byte Spill
	xorl	%esi, %esi
	xorl	%r12d, %r12d
.LBB1_5:                                # %.lr.ph.i51
                                        # =>This Inner Loop Header: Depth=1
	imull	%r15d, %r12d
	movsbl	(%r14,%rsi), %eax
	addl	%r12d, %eax
	cltd
	idivl	%r8d
	incq	%rsi
	movl	%edx, %r12d
	cmpq	%rsi, %rcx
	jne	.LBB1_5
# %bb.6:
	movq	-88(%rbp), %r13                 # 8-byte Reload
	jmp	.LBB1_7
.LBB1_1:
	movl	$0, -52(%rbp)                   # 4-byte Folded Spill
	xorl	%r12d, %r12d
.LBB1_7:                                # %_Z13compute_valuePciii.exit56
	movl	%r12d, (%r13)
	leal	-1(%rbx), %eax
	cvtsi2sd	%r15d, %xmm0
	movl	%eax, -76(%rbp)                 # 4-byte Spill
	cvtsi2sd	%eax, %xmm1
	callq	pow
	movl	-80(%rbp), %r11d                # 4-byte Reload
	subl	%ebx, %r11d
	movl	-48(%rbp), %r10d                # 4-byte Reload
	jle	.LBB1_10
# %bb.8:                                # %.lr.ph.preheader
	cvttsd2si	%xmm0, %ecx
	movslq	%ebx, %rsi
	movq	-64(%rbp), %rdi                 # 8-byte Reload
                                        # kill: def $edi killed $edi killed $rdi def $rdi
	subl	%esi, %edi
	incl	%edi
	addq	%r14, %rsi
	decq	%rdi
	xorl	%r8d, %r8d
.LBB1_9:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movsbl	(%rsi,%r8), %r9d
	imull	%ecx, %r9d
	movsbl	(%r14,%r8), %eax
	subl	%eax, %r12d
	movl	%r12d, %eax
	cltd
	idivl	%r15d
	addl	%r9d, %eax
	cltd
	idivl	%r10d
	movl	%edx, %r12d
	movl	%edx, 4(%r13,%r8,4)
	incq	%r8
	cmpq	%r8, %rdi
	jne	.LBB1_9
.LBB1_10:                               # %.preheader59
	movq	%rbx, -48(%rbp)                 # 8-byte Spill
	cmpl	$-1, %r11d
	movq	-72(%rbp), %rcx                 # 8-byte Reload
	jl	.LBB1_20
# %bb.11:                               # %.lr.ph71
	movl	-76(%rbp), %r12d                # 4-byte Reload
	movq	-64(%rbp), %r13                 # 8-byte Reload
	movq	-48(%rbp), %rax                 # 8-byte Reload
	subl	%eax, %r13d
	addl	$2, %r13d
	movq	%r13, -64(%rbp)                 # 8-byte Spill
	movl	%eax, %ebx
	xorl	%r15d, %r15d
.LBB1_12:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_15 Depth 2
	movq	-88(%rbp), %rax                 # 8-byte Reload
	movl	-52(%rbp), %edx                 # 4-byte Reload
	cmpl	%edx, (%rax,%r15,4)
	jne	.LBB1_19
# %bb.13:                               #   in Loop: Header=BB1_12 Depth=1
	cmpl	$0, -48(%rbp)                   # 4-byte Folded Reload
	jle	.LBB1_19
# %bb.14:                               # %.lr.ph66.preheader
                                        #   in Loop: Header=BB1_12 Depth=1
	xorl	%r13d, %r13d
.LBB1_15:                               # %.lr.ph66
                                        #   Parent Loop BB1_12 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movb	(%rcx,%r13), %al
	cmpb	(%r14,%r13), %al
	jne	.LBB1_19
# %bb.16:                               #   in Loop: Header=BB1_15 Depth=2
	cmpq	%r13, %r12
	jne	.LBB1_18
# %bb.17:                               #   in Loop: Header=BB1_15 Depth=2
	movl	$.L.str, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	movq	-72(%rbp), %rcx                 # 8-byte Reload
.LBB1_18:                               #   in Loop: Header=BB1_15 Depth=2
	incq	%r13
	cmpq	%r13, %rbx
	jne	.LBB1_15
.LBB1_19:                               # %.loopexit
                                        #   in Loop: Header=BB1_12 Depth=1
	incq	%r15
	incq	%r14
	cmpq	-64(%rbp), %r15                 # 8-byte Folded Reload
	jne	.LBB1_12
.LBB1_20:                               # %._crit_edge
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end1:
	.size	_Z10rk_matcherPcS_ii, .Lfunc_end1-_Z10rk_matcherPcS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__findHashesPciPiiii # -- Begin function _Z25__device_stub__findHashesPciPiiii
	.type	_Z25__device_stub__findHashesPciPiiii,@function
_Z25__device_stub__findHashesPciPiiii:  # @_Z25__device_stub__findHashesPciPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10findHashesPciPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__findHashesPciPiiii, .Lfunc_end2-_Z25__device_stub__findHashesPciPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__seekPatternPciPiiS_ii # -- Begin function _Z26__device_stub__seekPatternPciPiiS_ii
	.type	_Z26__device_stub__seekPatternPciPiiS_ii,@function
_Z26__device_stub__seekPatternPciPiiS_ii: # @_Z26__device_stub__seekPatternPciPiiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11seekPatternPciPiiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z26__device_stub__seekPatternPciPiiS_ii, .Lfunc_end3-_Z26__device_stub__seekPatternPciPiiS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x4008000000000000              # double 3
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$56, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	leaq	-52(%rbp), %rdi
	movl	$6382177, (%rdi)                # imm = 0x616261
	callq	strlen
	movq	%rax, %rbx
	movq	%rsp, -96(%rbp)                 # 8-byte Spill
	leal	13(%rax), %r14d
	movq	%rsp, %r15
	leaq	15(,%r14,8), %rax
	andq	$-16, %rax
	subq	%rax, %r15
	movq	%r15, %rsp
	leal	104(,%rbx,8), %eax
	movslq	%eax, %r12
	leaq	-48(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%r12, -64(%rbp)                 # 8-byte Spill
	leaq	(,%r12,4), %rsi
	leaq	-72(%rbp), %rdi
	callq	hipMalloc
	movslq	%ebx, %r13
	leaq	-88(%rbp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leal	-1(%r13), %eax
	movl	%eax, -76(%rbp)                 # 4-byte Spill
	movl	%eax, %r12d
	cmpl	$2, %r13d
	jl	.LBB4_2
# %bb.1:                                # %.lr.ph.preheader
	movq	%r15, %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	memset@PLT
.LBB4_2:                                # %.preheader114
	movslq	%ebx, %rcx
	leaq	(%r15,%rcx), %rax
	decq	%rax
	movq	$-98, %rdx
.LBB4_3:                                # %.preheader113
                                        # =>This Inner Loop Header: Depth=1
	movq	.L__const.main.str+104(%rdx), %rsi
	movq	%rsi, 6(%rax)
	movq	.L__const.main.str+98(%rdx), %rsi
	movq	%rsi, (%rax)
	addq	%r14, %rax
	addq	$14, %rdx
	jne	.LBB4_3
# %bb.4:                                # %.preheader112
	leaq	(,%r14,8), %rax
	subq	%r14, %rax
	leaq	(%r15,%rax), %rdx
	movl	$1919252065, 2(%rcx,%rdx)       # imm = 0x72657661
	movl	$1634886000, -1(%rcx,%rdx)      # imm = 0x61726170
	leaq	14(%r15), %rcx
	leaq	(%r15,%r14), %rdx
	movl	$1, %esi
.LBB4_5:                                # %.preheader110
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_7 Depth 2
	cmpl	$2, %ebx
	jl	.LBB4_8
# %bb.6:                                # %.lr.ph124
                                        #   in Loop: Header=BB4_5 Depth=1
	xorl	%edi, %edi
.LBB4_7:                                #   Parent Loop BB4_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movb	(%rcx,%rdi), %r8b
	movb	%r8b, (%rdx,%rdi)
	incq	%rdi
	cmpq	%rdi, %r12
	jne	.LBB4_7
.LBB4_8:                                # %._crit_edge
                                        #   in Loop: Header=BB4_5 Depth=1
	incq	%rsi
	addq	%r14, %rdx
	addq	%r14, %rcx
	cmpq	$8, %rsi
	jne	.LBB4_5
# %bb.9:                                # %.preheader
	addq	%r13, %rax
	addq	%r15, %rax
	movl	$7, %ecx
.LBB4_10:                               # =>This Inner Loop Header: Depth=1
	movb	$0, 5(%rax,%rcx)
	decq	%rcx
	jne	.LBB4_10
# %bb.11:
	movq	-48(%rbp), %rdi
	movq	%r15, %rsi
	movq	-64(%rbp), %r12                 # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	-48(%rbp), %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	-88(%rbp), %rdi
	leaq	-52(%rbp), %rsi
	movq	%r13, %rdx
	movabsq	$4294967297, %r13               # imm = 0x100000001
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2sdl	-76(%rbp), %xmm1        # 4-byte Folded Reload
	movsd	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	pow
	movsd	%xmm0, -64(%rbp)                # 8-byte Spill
	leaq	7(%r13), %r15
	xorl	%r12d, %r12d
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_13
# %bb.12:
	cvttsd2si	-64(%rbp), %r9d         # 8-byte Folded Reload
	movq	-48(%rbp), %rdi
	movq	-72(%rbp), %rdx
	movl	%r14d, %esi
	movl	%ebx, %ecx
	movl	$3, %r8d
	callq	_Z25__device_stub__findHashesPciPiiii
.LBB4_13:
	testl	%ebx, %ebx
	jle	.LBB4_16
# %bb.14:                               # %.lr.ph135.preheader
	movl	%ebx, %eax
	xorl	%ecx, %ecx
	movl	$1, %edx
	xorl	%r12d, %r12d
.LBB4_15:                               # %.lr.ph135
                                        # =>This Inner Loop Header: Depth=1
	movsbl	-52(%rbp,%rcx), %esi
	imull	%edx, %esi
	addl	%esi, %r12d
	leal	(%rdx,%rdx,2), %edx
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_15
.LBB4_16:                               # %._crit_edge136
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.17:
	movq	-48(%rbp), %rdi
	movq	-72(%rbp), %rdx
	movq	-88(%rbp), %r8
	subq	$8, %rsp
	movl	%r14d, %esi
	movl	%ebx, %ecx
	movl	$3, %r9d
	pushq	%r12
	callq	_Z26__device_stub__seekPatternPciPiiS_ii
	addq	$16, %rsp
.LBB4_18:
	movq	-72(%rbp), %rdi
	callq	hipFree
	movq	-48(%rbp), %rdi
	callq	hipFree
	movq	-96(%rbp), %rsp                 # 8-byte Reload
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10findHashesPciPiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11seekPatternPciPiiS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d\n"
	.size	.L.str, 4

	.type	_Z10findHashesPciPiiii,@object  # @_Z10findHashesPciPiiii
	.section	.rodata,"a",@progbits
	.globl	_Z10findHashesPciPiiii
	.p2align	3, 0x0
_Z10findHashesPciPiiii:
	.quad	_Z25__device_stub__findHashesPciPiiii
	.size	_Z10findHashesPciPiiii, 8

	.type	_Z11seekPatternPciPiiS_ii,@object # @_Z11seekPatternPciPiiS_ii
	.globl	_Z11seekPatternPciPiiS_ii
	.p2align	3, 0x0
_Z11seekPatternPciPiiS_ii:
	.quad	_Z26__device_stub__seekPatternPciPiiS_ii
	.size	_Z11seekPatternPciPiiS_ii, 8

	.type	.L__const.main.str,@object      # @__const.main.str
	.section	.rodata.str1.16,"aMS",@progbits,1
	.p2align	4, 0x0
.L__const.main.str:
	.asciz	"bababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaverbababanaparaver"
	.size	.L__const.main.str, 106

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10findHashesPciPiiii"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11seekPatternPciPiiS_ii"
	.size	.L__unnamed_2, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__findHashesPciPiiii
	.addrsig_sym _Z26__device_stub__seekPatternPciPiiS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10findHashesPciPiiii
	.addrsig_sym _Z11seekPatternPciPiiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10findHashesPciPiiii  ; -- Begin function _Z10findHashesPciPiiii
	.globl	_Z10findHashesPciPiiii
	.p2align	8
	.type	_Z10findHashesPciPiiii,@function
_Z10findHashesPciPiiii:                 ; @_Z10findHashesPciPiiii
; %bb.0:
	s_clause 0x3
	s_load_b32 s4, s[0:1], 0x8
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x18
	v_mov_b32_e32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s3, 1
	v_mul_lo_u32 v0, v0, s4
	s_cmp_lt_i32 s0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[2:3], v4, off
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
	s_mov_b32 s5, s0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_i8 v9, v[5:6], off
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, s3, v9, v[4:5]
	v_add_co_u32 v5, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_mul_i32 s3, s3, s1
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v4, v7
	global_store_b32 v[2:3], v7, off
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %.preheader
	s_sub_i32 s3, s4, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB0_6
; %bb.4:                                ; %.lr.ph37.preheader
	global_load_b32 v4, v[2:3], off
	s_ashr_i32 s4, s1, 31
	v_add_co_u32 v2, vcc_lo, v2, 4
	s_add_i32 s1, s1, s4
	s_add_i32 s0, s0, 1
	s_xor_b32 s5, s1, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_cvt_f32_u32_e32 v5, s5
	s_sub_i32 s1, 0, s5
	v_add_co_u32 v7, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v6, s1, v5
	s_ashr_i32 s1, s0, 31
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v6
	v_add_nc_u32_e32 v6, v5, v6
.LBB0_5:                                ; %.lr.ph37
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v9, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v11, vcc_lo, v7, s0
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v8, vcc_lo
	s_add_u32 s0, s0, 1
	s_clause 0x1
	global_load_i8 v5, v[9:10], off
	global_load_i8 v10, v[11:12], off offset:-1
	s_addc_u32 s1, s1, 0
	s_cmp_lt_i32 s0, s3
	s_waitcnt vmcnt(1)
	v_sub_nc_u32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v5
	v_xor_b32_e32 v5, s4, v5
	v_mul_hi_u32 v9, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v9, s5
	v_add_nc_u32_e32 v12, 1, v9
	v_sub_nc_u32_e32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v11, s5, v4
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	v_dual_cndmask_b32 v9, v9, v12 :: v_dual_cndmask_b32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, 1, v9
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v9, v11, vcc_lo
	v_xor_b32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v4, v5
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v10, s2, v[9:10]
	global_store_b32 v[2:3], v4, off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_cbranch_scc1 .LBB0_5
.LBB0_6:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10findHashesPciPiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 10
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10findHashesPciPiiii, .Lfunc_end0-_Z10findHashesPciPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 12
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11seekPatternPciPiiS_ii ; -- Begin function _Z11seekPatternPciPiiS_ii
	.globl	_Z11seekPatternPciPiiS_ii
	.p2align	8
	.type	_Z11seekPatternPciPiiS_ii,@function
_Z11seekPatternPciPiiS_ii:              ; @_Z11seekPatternPciPiiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x8
	s_load_b32 s22, s[0:1], 0x18
	s_mov_b32 s4, 0
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s23, s2, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s23, 0
	s_cbranch_scc1 .LBB1_181
; %bb.1:                                ; %.lr.ph63
	v_mul_lo_u32 v1, v0, s2
	s_clause 0x3
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b32 s24, s[0:1], 0x2c
	s_cmp_lt_i32 s22, 1
	v_mbcnt_lo_u32_b32 v36, -1, 0
	s_cselect_b32 s5, -1, 0
	s_add_i32 s25, s22, -1
	s_mov_b32 s10, 0
	v_ashrrev_i32_e32 v2, 31, v1
	v_mad_u64_u32 v[3:4], null, v0, s23, v[0:1]
	v_mov_b32_e32 v6, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_subrev_nc_u32_e32 v0, s22, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v31, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v32, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v33, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v34, vcc_lo, s9, v2, vcc_lo
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v35, 1, v0
	v_dual_mov_b32 v5, 2 :: v_dual_mov_b32 v0, 33
	s_add_u32 s8, s0, 48
	s_addc_u32 s9, s1, 0
	s_xor_b32 s26, s5, -1
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
                                        ;       Child Loop BB1_9 Depth 3
                                        ;       Child Loop BB1_17 Depth 3
                                        ;       Child Loop BB1_23 Depth 3
                                        ;       Child Loop BB1_32 Depth 3
                                        ;       Child Loop BB1_35 Depth 3
                                        ;         Child Loop BB1_38 Depth 4
                                        ;         Child Loop BB1_46 Depth 4
                                        ;         Child Loop BB1_54 Depth 4
                                        ;         Child Loop BB1_62 Depth 4
                                        ;         Child Loop BB1_70 Depth 4
                                        ;         Child Loop BB1_78 Depth 4
                                        ;         Child Loop BB1_86 Depth 4
                                        ;         Child Loop BB1_94 Depth 4
                                        ;         Child Loop BB1_102 Depth 4
                                        ;         Child Loop BB1_108 Depth 4
                                        ;         Child Loop BB1_117 Depth 4
                                        ;       Child Loop BB1_125 Depth 3
                                        ;       Child Loop BB1_133 Depth 3
                                        ;       Child Loop BB1_139 Depth 3
                                        ;       Child Loop BB1_148 Depth 3
                                        ;       Child Loop BB1_153 Depth 3
                                        ;       Child Loop BB1_161 Depth 3
                                        ;       Child Loop BB1_167 Depth 3
                                        ;       Child Loop BB1_176 Depth 3
	s_mov_b32 s11, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[10:11], 2
	v_add_co_u32 v3, vcc_lo, v31, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v32, vcc_lo
	global_load_b32 v1, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s24, v1
	s_and_b32 s0, vcc_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB1_180
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v1, s10, v35
	v_mov_b32_e32 v30, v2
	s_mov_b32 s27, 0
	s_mov_b32 s28, 0
                                        ; implicit-def: $sgpr29
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v29, v1
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_9 Depth 3
                                        ;       Child Loop BB1_17 Depth 3
                                        ;       Child Loop BB1_23 Depth 3
                                        ;       Child Loop BB1_32 Depth 3
                                        ;       Child Loop BB1_35 Depth 3
                                        ;         Child Loop BB1_38 Depth 4
                                        ;         Child Loop BB1_46 Depth 4
                                        ;         Child Loop BB1_54 Depth 4
                                        ;         Child Loop BB1_62 Depth 4
                                        ;         Child Loop BB1_70 Depth 4
                                        ;         Child Loop BB1_78 Depth 4
                                        ;         Child Loop BB1_86 Depth 4
                                        ;         Child Loop BB1_94 Depth 4
                                        ;         Child Loop BB1_102 Depth 4
                                        ;         Child Loop BB1_108 Depth 4
                                        ;         Child Loop BB1_117 Depth 4
                                        ;       Child Loop BB1_125 Depth 3
                                        ;       Child Loop BB1_133 Depth 3
                                        ;       Child Loop BB1_139 Depth 3
                                        ;       Child Loop BB1_148 Depth 3
                                        ;       Child Loop BB1_153 Depth 3
                                        ;       Child Loop BB1_161 Depth 3
                                        ;       Child Loop BB1_167 Depth 3
                                        ;       Child Loop BB1_176 Depth 3
	s_add_i32 s0, s28, s10
	v_mov_b32_e32 v1, s28
	v_add_co_u32 v3, vcc_lo, v33, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v34, vcc_lo
	s_or_b32 s29, s29, exec_lo
	s_mov_b32 s30, exec_lo
	global_load_u8 v1, v1, s[2:3]
	global_load_u8 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v1, v3
	s_cbranch_execz .LBB1_179
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=2
	s_cmp_lg_u32 s28, s25
	s_cbranch_scc1 .LBB1_178
; %bb.6:                                ;   in Loop: Header=BB1_4 Depth=2
	s_load_b64 s[12:13], s[8:9], 0x50
	v_mov_b32_e32 v1, v36
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_12
; %bb.7:                                ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[9:10], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[7:8], v2, s[12:13]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[9:10]
	s_cbranch_execz .LBB1_11
; %bb.8:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s6, 0
.LBB1_9:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	global_load_b64 v[11:12], v2, s[12:13]
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[9:10]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_9
; %bb.10:                               ; %Flow373
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_11:                               ; %Flow375
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_12:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[12:13] offset:40
	global_load_b128 v[7:10], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[14:15], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s17, s6, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB1_14
; %bb.13:                               ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, v2
	s_add_i32 s5, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v7, s17
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v8, vcc_lo
	global_store_b128 v[11:12], v[3:6], off offset:8
.LBB1_14:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v9, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v12, s7
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v10, s5
	v_mov_b32_e32 v11, s6
	v_mov_b32_e32 v9, s4
	s_clause 0x3
	global_store_b128 v[13:14], v[0:3], off
	global_store_b128 v[13:14], v[9:12], off offset:16
	global_store_b128 v[13:14], v[9:12], off offset:32
	global_store_b128 v[13:14], v[9:12], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_22
; %bb.15:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[12:13] offset:32 glc
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	v_mov_b32_e32 v15, s14
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v16, s15 :: v_dual_and_b32 v1, s15, v4
	v_and_b32_e32 v3, s14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v1, vcc_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB1_18
; %bb.16:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s7, 0
.LBB1_17:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, s15
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_17
.LBB1_18:                               ; %Flow371
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[3:4], v2, s[12:13] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_20
; %bb.19:                               ;   in Loop: Header=BB1_4 Depth=2
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_20:                               ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB1_22
; %bb.21:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_22:                               ; %Flow372
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v7, s17
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_23:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_25
; %bb.24:                               ;   in Loop: Header=BB1_23 Depth=3
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_25:                               ;   in Loop: Header=BB1_23 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_27
; %bb.26:                               ;   in Loop: Header=BB1_23 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_28
.LBB1_27:                               ;   in Loop: Header=BB1_23 Depth=3
	s_mov_b32 s1, -1
.LBB1_28:                               ; %Flow366
                                        ;   in Loop: Header=BB1_23 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_23
; %bb.29:                               ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[7:8], v[13:14], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_33
; %bb.30:                               ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[13:14], v2, s[12:13] offset:24 glc
	global_load_b64 v[11:12], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v1
	v_and_b32_e32 v1, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v9, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_33
; %bb.31:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
.LBB1_32:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_32
.LBB1_33:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB1_120
; %bb.34:                               ;   in Loop: Header=BB1_4 Depth=2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v10, v8 :: v_dual_and_b32 v37, 2, v7
	v_and_b32_e32 v9, -3, v7
	s_mov_b64 s[14:15], 8
.LBB1_35:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_38 Depth 4
                                        ;         Child Loop BB1_46 Depth 4
                                        ;         Child Loop BB1_54 Depth 4
                                        ;         Child Loop BB1_62 Depth 4
                                        ;         Child Loop BB1_70 Depth 4
                                        ;         Child Loop BB1_78 Depth 4
                                        ;         Child Loop BB1_86 Depth 4
                                        ;         Child Loop BB1_94 Depth 4
                                        ;         Child Loop BB1_102 Depth 4
                                        ;         Child Loop BB1_108 Depth 4
                                        ;         Child Loop BB1_117 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[14:15], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s16, s14, 56
	s_cselect_b32 s17, s15, 0
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB1_40
; %bb.36:                               ;   in Loop: Header=BB1_35 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB1_39
; %bb.37:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_lshl_b64 s[0:1], s[16:17], 3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], s[6:7]
.LBB1_38:                               ; %.preheader31.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v1, v2, s[20:21]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s0, s18
	v_or_b32_e32 v11, v3, v11
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB1_38
.LBB1_39:                               ; %Flow342
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s0, 0
	s_mov_b32 s5, 0
	s_branch .LBB1_41
.LBB1_40:                               ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr5
.LBB1_41:                               ; %Flow344
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[6:7]
	s_cbranch_vccnz .LBB1_43
; %bb.42:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[11:12], v2, s[6:7]
	s_add_i32 s5, s16, -8
	s_add_u32 s0, s6, 8
	s_addc_u32 s1, s7, 0
.LBB1_43:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB1_48
; %bb.44:                               ;   in Loop: Header=BB1_35 Depth=3
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB1_47
; %bb.45:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB1_46:                               ; %.preheader29.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s20
	s_addc_u32 s35, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[34:35]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s5, s20
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB1_46
.LBB1_47:                               ; %Flow337
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, 0
	s_mov_b32 s31, 0
	s_branch .LBB1_49
.LBB1_48:                               ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr31
.LBB1_49:                               ; %Flow339
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_51
; %bb.50:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[13:14], v2, s[0:1]
	s_add_i32 s31, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_51:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_cmp_gt_u32 s31, 7
	s_cbranch_scc1 .LBB1_56
; %bb.52:                               ;   in Loop: Header=BB1_35 Depth=3
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s31, 0
	s_cbranch_scc1 .LBB1_55
; %bb.53:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB1_54:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s20
	s_addc_u32 s35, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[34:35]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s31, s20
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB1_54
.LBB1_55:                               ; %Flow332
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, 0
	s_mov_b32 s5, 0
	s_branch .LBB1_57
.LBB1_56:                               ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr5
.LBB1_57:                               ; %Flow334
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_59
; %bb.58:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[15:16], v2, s[0:1]
	s_add_i32 s5, s31, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_59:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB1_64
; %bb.60:                               ;   in Loop: Header=BB1_35 Depth=3
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB1_63
; %bb.61:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB1_62:                               ; %.preheader25.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s20
	s_addc_u32 s35, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[34:35]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s5, s20
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB1_62
.LBB1_63:                               ; %Flow327
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, 0
	s_mov_b32 s31, 0
	s_branch .LBB1_65
.LBB1_64:                               ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr31
.LBB1_65:                               ; %Flow329
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_67
; %bb.66:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[17:18], v2, s[0:1]
	s_add_i32 s31, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_67:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_cmp_gt_u32 s31, 7
	s_cbranch_scc1 .LBB1_72
; %bb.68:                               ;   in Loop: Header=BB1_35 Depth=3
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s31, 0
	s_cbranch_scc1 .LBB1_71
; %bb.69:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB1_70:                               ; %.preheader23.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s20
	s_addc_u32 s35, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[34:35]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s31, s20
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB1_70
.LBB1_71:                               ; %Flow322
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, 0
	s_mov_b32 s5, 0
	s_branch .LBB1_73
.LBB1_72:                               ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr5
.LBB1_73:                               ; %Flow324
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_75
; %bb.74:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[19:20], v2, s[0:1]
	s_add_i32 s5, s31, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_75:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB1_80
; %bb.76:                               ;   in Loop: Header=BB1_35 Depth=3
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB1_79
; %bb.77:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB1_78:                               ; %.preheader21.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s34, s0, s20
	s_addc_u32 s35, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[34:35]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s5, s20
	v_or_b32_e32 v21, v3, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB1_78
.LBB1_79:                               ; %Flow317
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, 0
	s_mov_b32 s31, 0
	s_branch .LBB1_81
.LBB1_80:                               ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr31
.LBB1_81:                               ; %Flow319
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_83
; %bb.82:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[21:22], v2, s[0:1]
	s_add_i32 s31, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_83:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_cmp_gt_u32 s31, 7
	s_cbranch_scc1 .LBB1_88
; %bb.84:                               ;   in Loop: Header=BB1_35 Depth=3
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s31, 0
	s_cbranch_scc1 .LBB1_87
; %bb.85:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], s[0:1]
.LBB1_86:                               ; %.preheader.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v1, v2, s[20:21]
	s_add_i32 s31, s31, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s31, 0
	v_or_b32_e32 v23, v3, v23
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB1_86
.LBB1_87:                               ; %Flow312
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s5, 0
	s_branch .LBB1_89
.LBB1_88:                               ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s5, -1
.LBB1_89:                               ; %Flow314
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB1_91
; %bb.90:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[23:24], v2, s[0:1]
.LBB1_91:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	v_mov_b32_e32 v1, v36
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_97
; %bb.92:                               ;   in Loop: Header=BB1_35 Depth=3
	global_load_b64 v[27:28], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[25:26], v2, s[12:13]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v28
	v_and_b32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v38, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v38, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v25, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[27:28]
	s_cbranch_execz .LBB1_96
; %bb.93:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s18, 0
.LBB1_94:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[12:13] offset:40
	global_load_b64 v[38:39], v2, s[12:13]
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v27, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v25, 24, v[38:39]
	v_and_b32_e32 v38, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v38, 24, v[4:5]
	v_mov_b32_e32 v4, v25
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[27:28]
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB1_94
; %bb.95:                               ; %Flow307
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_or_b32 exec_lo, exec_lo, s18
.LBB1_96:                               ; %Flow309
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_97:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[38:39], v2, s[12:13] offset:40
	global_load_b128 v[25:28], v2, s[12:13]
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_mov_b32 s33, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s20, v38
	v_readfirstlane_b32 s21, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[18:19], s[20:21]
	s_mul_i32 s1, s21, 24
	s_mul_hi_u32 s5, s20, 24
	s_mul_i32 s31, s20, 24
	s_and_saveexec_b32 s34, s0
	s_cbranch_execz .LBB1_99
; %bb.98:                               ;   in Loop: Header=BB1_35 Depth=3
	v_dual_mov_b32 v3, s33 :: v_dual_mov_b32 v4, v2
	s_add_i32 s33, s5, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v38, vcc_lo, v25, s31
	v_add_co_ci_u32_e32 v39, vcc_lo, s33, v26, vcc_lo
	global_store_b128 v[38:39], v[3:6], off offset:8
.LBB1_99:                               ;   in Loop: Header=BB1_35 Depth=3
	s_or_b32 exec_lo, exec_lo, s34
	v_cmp_gt_u64_e64 vcc_lo, s[14:15], 56
	v_or_b32_e32 v3, 0, v10
	v_or_b32_e32 v4, v9, v37
	s_lshl_b64 s[20:21], s[20:21], 12
	s_lshl_b32 s33, s16, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s33, s33, 28
	v_dual_cndmask_b32 v10, v3, v10 :: v_dual_cndmask_b32 v9, v4, v9
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v27, s20
	v_add_co_ci_u32_e32 v27, vcc_lo, s21, v28, vcc_lo
	s_and_b32 s33, s33, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v9, 0xffffff1f, v9, s33
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[17:20], off offset:32
	global_store_b128 v[3:4], v[21:24], off offset:48
	s_and_saveexec_b32 s20, s0
	s_cbranch_execz .LBB1_107
; %bb.100:                              ;   in Loop: Header=BB1_35 Depth=3
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[12:13] offset:32 glc
	global_load_b64 v[9:10], v2, s[12:13] offset:40
	v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s34, v9
	v_readfirstlane_b32 s35, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[34:35], s[34:35], s[18:19]
	s_mul_i32 s21, s35, 24
	s_mul_hi_u32 s33, s34, 24
	s_mul_i32 s34, s34, 24
	s_add_i32 s33, s33, s21
	v_add_co_u32 v13, vcc_lo, v25, s34
	v_add_co_ci_u32_e32 v14, vcc_lo, s33, v26, vcc_lo
	s_mov_b32 s21, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB1_103
; %bb.101:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s33, 0
.LBB1_102:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
	s_sleep 1
	global_store_b64 v[13:14], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s33, vcc_lo, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s33
	s_cbranch_execnz .LBB1_102
.LBB1_103:                              ; %Flow305
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
	global_load_b64 v[9:10], v2, s[12:13] offset:16
	s_mov_b32 s33, exec_lo
	s_mov_b32 s21, exec_lo
	v_mbcnt_lo_u32_b32 v1, s33, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_105
; %bb.104:                              ;   in Loop: Header=BB1_35 Depth=3
	s_bcnt1_i32_b32 s33, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s33
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[1:2], off offset:8
.LBB1_105:                              ;   in Loop: Header=BB1_35 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_107
; %bb.106:                              ;   in Loop: Header=BB1_35 Depth=3
	global_load_b32 v1, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s21, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s21, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_107:                              ; %Flow306
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_or_b32 exec_lo, exec_lo, s20
	s_add_i32 s5, s5, s1
	v_add_co_u32 v1, vcc_lo, v25, s31
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB1_108:                              ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_110
; %bb.109:                              ;   in Loop: Header=BB1_108 Depth=4
	global_load_b32 v1, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_110:                              ;   in Loop: Header=BB1_108 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_112
; %bb.111:                              ;   in Loop: Header=BB1_108 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_113
.LBB1_112:                              ;   in Loop: Header=BB1_108 Depth=4
	s_mov_b32 s1, -1
.LBB1_113:                              ; %Flow300
                                        ;   in Loop: Header=BB1_108 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_108
; %bb.114:                              ;   in Loop: Header=BB1_35 Depth=3
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_118
; %bb.115:                              ;   in Loop: Header=BB1_35 Depth=3
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[15:16], v2, s[12:13] offset:24 glc
	global_load_b64 v[13:14], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s18
	v_add_co_ci_u32_e32 v12, vcc_lo, s19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v1, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v12, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_118
; %bb.116:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_mov_b32 s0, 0
.LBB1_117:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_35 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_117
.LBB1_118:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB1_35 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s14, s14, s16
	s_subb_u32 s15, s15, s17
	s_add_u32 s6, s6, s16
	s_addc_u32 s7, s7, s17
	s_cmp_lg_u64 s[14:15], 0
	s_cbranch_scc1 .LBB1_35
; %bb.119:                              ; %Flow345
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
	s_branch .LBB1_121
.LBB1_120:                              ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB1_121:                              ; %Flow360
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_150
; %bb.122:                              ;   in Loop: Header=BB1_4 Depth=2
	v_mov_b32_e32 v1, v36
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_128
; %bb.123:                              ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[11:12], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[9:10], v2, s[12:13]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v12
	v_and_b32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[11:12]
	s_cbranch_execz .LBB1_127
; %bb.124:                              ; %.preheader3.i.i.i37.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s6, 0
.LBB1_125:                              ; %.preheader3.i.i.i37
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[12:13] offset:40
	global_load_b64 v[13:14], v2, s[12:13]
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v9
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_125
; %bb.126:                              ; %Flow357
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_127:                              ; %Flow359
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_128:                              ; %.loopexit4.i.i.i32
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[12:13] offset:40
	global_load_b128 v[11:14], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[14:15], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s17, s6, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB1_130
; %bb.129:                              ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, v2
	s_add_i32 s5, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v11, s17
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
	global_store_b128 v[9:10], v[3:6], off offset:8
.LBB1_130:                              ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v14, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v7, 0xffffff1f, v7, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v16, s7
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v15, s6
	v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v13, s4
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_138
; %bb.131:                              ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[12:13] offset:32 glc
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	v_dual_mov_b32 v15, s14 :: v_dual_mov_b32 v16, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[14:15]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s18, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s18, s18, s7
	v_add_co_u32 v13, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v14, vcc_lo, s18, v12, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[15:18], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[17:18]
	s_cbranch_execz .LBB1_134
; %bb.132:                              ; %.preheader1.i.i.i35.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s7, 0
.LBB1_133:                              ; %.preheader1.i.i.i35
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
	s_sleep 1
	global_store_b64 v[13:14], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_133
.LBB1_134:                              ; %Flow355
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v2, s[12:13] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_136
; %bb.135:                              ;   in Loop: Header=BB1_4 Depth=2
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_136:                              ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB1_138
; %bb.137:                              ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_138:                              ; %Flow356
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v11, s17
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_139:                              ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_141
; %bb.140:                              ;   in Loop: Header=BB1_139 Depth=3
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_141:                              ;   in Loop: Header=BB1_139 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_143
; %bb.142:                              ;   in Loop: Header=BB1_139 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_144
.LBB1_143:                              ;   in Loop: Header=BB1_139 Depth=3
	s_mov_b32 s1, -1
.LBB1_144:                              ; %Flow350
                                        ;   in Loop: Header=BB1_139 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_139
; %bb.145:                              ;   in Loop: Header=BB1_4 Depth=2
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_149
; %bb.146:                              ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[7:8], v2, s[12:13] offset:24 glc
	global_load_b64 v[13:14], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v12, vcc_lo, s15, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v1
	v_and_b32_e32 v1, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v11, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_149
; %bb.147:                              ; %.preheader.i.i.i34.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
.LBB1_148:                              ; %.preheader.i.i.i34
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_148
.LBB1_149:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_150:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB1_4 Depth=2
	v_mov_b32_e32 v1, v36
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_156
; %bb.151:                              ;   in Loop: Header=BB1_4 Depth=2
	global_load_b64 v[13:14], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[7:8], v2, s[12:13]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v14
	v_and_b32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[13:14]
	s_cbranch_execz .LBB1_155
; %bb.152:                              ; %.preheader3.i.i.i44.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s6, 0
.LBB1_153:                              ; %.preheader3.i.i.i44
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	global_load_b64 v[11:12], v2, s[12:13]
	v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v13, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[13:14]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_153
; %bb.154:                              ; %Flow293
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_155:                              ; %Flow295
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_156:                              ; %.loopexit4.i.i.i38
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	global_load_b128 v[13:16], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[14:15], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s17, s6, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB1_158
; %bb.157:                              ;   in Loop: Header=BB1_4 Depth=2
	v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, v2
	s_add_i32 s5, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v13, s17
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v14, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB1_158:                              ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v15, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v16, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v9, 0xffffff1d, v9, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v11, v29 :: v_dual_mov_b32 v12, v30
	v_dual_mov_b32 v18, s7 :: v_dual_mov_b32 v17, s6
	v_dual_mov_b32 v16, s5 :: v_dual_mov_b32 v15, s4
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[15:18], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[15:18], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_166
; %bb.159:                              ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[12:13] offset:32 glc
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v3
	v_readfirstlane_b32 s7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[14:15]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s18, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s18, s18, s7
	v_add_co_u32 v3, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s18, v14, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[11:12]
	s_cbranch_execz .LBB1_162
; %bb.160:                              ; %.preheader1.i.i.i42.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s7, 0
.LBB1_161:                              ; %.preheader1.i.i.i42
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_161
.LBB1_162:                              ; %Flow291
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[3:4], v2, s[12:13] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_164
; %bb.163:                              ;   in Loop: Header=BB1_4 Depth=2
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_164:                              ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB1_166
; %bb.165:                              ;   in Loop: Header=BB1_4 Depth=2
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_166:                              ; %Flow292
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v13, s17
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_167:                              ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_169
; %bb.168:                              ;   in Loop: Header=BB1_167 Depth=3
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_169:                              ;   in Loop: Header=BB1_167 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_171
; %bb.170:                              ;   in Loop: Header=BB1_167 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_172
.LBB1_171:                              ;   in Loop: Header=BB1_167 Depth=3
	s_mov_b32 s1, -1
.LBB1_172:                              ; %Flow286
                                        ;   in Loop: Header=BB1_167 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_167
; %bb.173:                              ;   in Loop: Header=BB1_4 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_177
; %bb.174:                              ;   in Loop: Header=BB1_4 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[11:12], v2, s[12:13] offset:24 glc
	global_load_b64 v[9:10], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_177
; %bb.175:                              ; %.preheader.i.i.i41.preheader
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_mov_b32 s0, 0
.LBB1_176:                              ; %.preheader.i.i.i41
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_176
.LBB1_177:                              ; %Flow284
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_178:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_add_i32 s28, s28, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s28, s22
	s_cselect_b32 s0, -1, 0
	s_and_not1_b32 s1, s29, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s29, s1, s0
.LBB1_179:                              ; %Flow377
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s29
	s_or_b32 s27, s0, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB1_4
.LBB1_180:                              ; %Flow379
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_add_i32 s0, s10, 1
	s_cmp_lg_u32 s10, s23
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB1_2
.LBB1_181:                              ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11seekPatternPciPiiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11seekPatternPciPiiS_ii, .Lfunc_end1-_Z11seekPatternPciPiiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6984
; NumSgprs: 38
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"pos:%d\n"
	.size	.str, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10findHashesPciPiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z10findHashesPciPiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         128
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11seekPatternPciPiiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z11seekPatternPciPiiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
