#include <assert.h>
//#include <sys/time.h>
#include <time.h>

#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cmath>
#include <algorithm>

using std::cout;
using std::endl;
using std::cerr;

#define DECLINE_HORIZONTAL 0.1
#define DECLINE_VERTICAL   0.1
#define STEPS              1000               /* number of time steps */

/* error check on hip macro */
#define CUDA_CHECK(command) \
{ \
  cudaError_t status = command; \
  if(status != cudaSuccess) \
  { \
    cerr << "Error : Cuda reports " << cudaGetErrorString(status) << endl; \
    heatCleanExit(-6); \
  } \
}

/* Device(GPU) FUNCTIONS TO BE LAUNCHED AS KERNELS FROM HOST(CPU) */
/* This function is used to discover the local working area of each thread */
__global__ void heatDiscover(int * __restrict__ workRowS,
                             int * __restrict__ workRowE,
                             int * __restrict__ workColS,
                             int * __restrict__ workColE,
                             const int blockRows, const int blockCols,
                             const int threadsPerRow, const int threadsPerCol,
                             const int probCase,
                             const int gridRows, const int gridCols)
{
  const int thread_Id = blockIdx.x * blockDim.x + threadIdx.x;
  if(probCase == 1)//2 threads
  {
    if(thread_Id == 0)//west thread
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 2;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else//east thread
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 2;
      workColS[thread_Id] = blockCols;
      workColE[thread_Id] = gridCols - 2;
    } 
  }
  else if(probCase == 2)//6, 8, 10, ... OR 4, 16, 64 ... threads
  {
    if(thread_Id == 0)//NW corner
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 1;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else if(thread_Id == (threadsPerCol - 1))//NE corner
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 1;
      workColS[thread_Id] = gridCols - blockCols;
      workColE[thread_Id] = gridCols - 2;
    }
    else if(thread_Id == ((threadsPerRow * threadsPerCol) - threadsPerCol))//SW corner
    {
      workRowS[thread_Id] = gridRows - blockRows;
      workRowE[thread_Id] = gridRows - 2;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else if(thread_Id == ((threadsPerCol * threadsPerRow) - 1))//SE corner
    {
      workRowS[thread_Id] = gridRows - blockRows;
      workRowE[thread_Id] = gridRows - 2;
      workColS[thread_Id] = gridCols - blockCols;
      workColE[thread_Id] = gridCols - 2;
    }
    else if(thread_Id < threadsPerCol)//NN side
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 1;
      workColS[thread_Id] = thread_Id * blockCols;
      workColE[thread_Id] = workColS[thread_Id] + blockCols - 1;
    }
    else if((thread_Id > ((threadsPerCol * threadsPerRow) - threadsPerCol)) && 
            (thread_Id < ((threadsPerCol * threadsPerRow) - 1)))//SS side
    {
      workRowS[thread_Id] = gridRows - blockRows;
      workRowE[thread_Id] = gridRows - 2;
      workColS[thread_Id] = (thread_Id % threadsPerCol) * blockCols;
      workColE[thread_Id] =  workColS[thread_Id] + blockCols - 1;
    }
    else if((thread_Id % threadsPerCol) == 0)//WW side
    {
      workRowS[thread_Id] = (thread_Id / threadsPerCol) * blockRows;
      workRowE[thread_Id] = workRowS[thread_Id] + blockRows - 1;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else if((thread_Id + 1) % threadsPerCol == 0)//EE side
    {
      workRowS[thread_Id] = ((thread_Id + 1 - threadsPerCol) / threadsPerCol) *
                              blockRows;
      workRowE[thread_Id] = workRowS[thread_Id] + blockRows - 1;
      workColS[thread_Id] = gridCols - blockCols;
      workColE[thread_Id] = gridCols - 2;
    }
    else//general case middle location
    {
      int rowMarginS = threadsPerCol;
      int rowMarginE = rowMarginS + threadsPerCol - 1;
      int rowOffset = 1;
      while(1)
      {
        if((thread_Id > rowMarginS) && (thread_Id < rowMarginE))
        {
          workRowS[thread_Id] = rowOffset * blockRows;
          break;
        }
        else
        {
          rowMarginS += threadsPerCol;
          rowMarginE += threadsPerCol;
          ++rowOffset;
        }
      }
      workRowE[thread_Id] = workRowS[thread_Id] + blockRows - 1;
      workColS[thread_Id] = (thread_Id % threadsPerCol) * blockCols;
      workColE[thread_Id] = workColS[thread_Id] + blockCols - 1;
    }
  }
}

/* This function updates the grid and is invoked on serial executions */
__global__ void heatUpdateSerial(const double * __restrict__ devOldHeatGrid,
                                       double * __restrict__ devNewHeatGrid,
                                 const int gridRows, const int gridCols)
{
  for(int i = 1; i < gridRows - 1; ++i)
  {
    for(int j = 1; j < gridCols - 1; ++j)
    {
      devNewHeatGrid[i*gridCols+j] = devOldHeatGrid[i*gridCols+j] +
                                    DECLINE_HORIZONTAL *
                                    (devOldHeatGrid[(i+1)*gridCols+j] +
                                    devOldHeatGrid[(i-1)*gridCols+j] -
                                    (2 * devOldHeatGrid[i*gridCols+j])) +
                                    DECLINE_VERTICAL *
                                    (devOldHeatGrid[i*gridCols+j+1] +
                                    devOldHeatGrid[i*gridCols+j-1] -
                                    (2 * devOldHeatGrid[i*gridCols+j]));
    }
  }    
}

/* This function updates the grid and is invoked on parallel executions */
__global__ void heatUpdateParallel(const double * __restrict__ devOldHeatGrid,
                                   double       * __restrict__ devNewHeatGrid,
                                   const int    * __restrict__ workRowS,
                                   const int    * __restrict__ workRowE,
                                   const int    * __restrict__ workColS,
                                   const int    * __restrict__ workColE,
                                   const int                   gridCols)
{
  const int thread_Id = blockIdx.x * blockDim.x + threadIdx.x;
  //get the borders in registers for 1 cycle memory access
  const int wRowS = workRowS[thread_Id];
  const int wRowE = workRowE[thread_Id];
  const int wColS = workColS[thread_Id];
  const int wColE = workColE[thread_Id];

  for(int i = wRowS; i <= wRowE; ++i)
  {
    for(int j = wColS; j <= wColE; ++j)
    {
      devNewHeatGrid[i*gridCols+j] = devOldHeatGrid[i*gridCols+j] +
                                 DECLINE_HORIZONTAL *
                                 (devOldHeatGrid[(i+1)*gridCols+j] +
                                 devOldHeatGrid[(i-1)*gridCols+j] -
                                 (2*devOldHeatGrid[i*gridCols+j])) +
                                 DECLINE_VERTICAL *
                                 (devOldHeatGrid[i*gridCols+j+1] +
                                 devOldHeatGrid[i*gridCols+j-1] -
                                 (2*devOldHeatGrid[i*gridCols+j]));
    }
  }
}                                      

//declare dynamic variables
double * heatGrid = nullptr;
double * devNewHeatGrid = nullptr;
double * devOldHeatGrid = nullptr;
int * workRowS = nullptr;
int * workRowE = nullptr;
int * workColS = nullptr;
int * workColE = nullptr;
int * devWorkRowS = nullptr;
int * devWorkRowE = nullptr;
int * devWorkColS = nullptr;
int * devWorkColE = nullptr;

/* HOST(CPU) FUNCTIONS */
/* This function intialises the temperature on the given grid with higher
   temperatures at the centre, progressively lower ones until the sides 
   and 0s at the perimetre 
*/
static inline void heatInit(double * heatGrid,
                            const int gridRows, const int gridCols)
{
  for(int i = 0; i < gridRows; ++i)//avoid halo area
    for(int j = 0; j < gridCols; ++j)
      heatGrid[i*gridCols+j] = (double) (i * (gridRows - i - 1) * j * (gridCols - j - 1));
}

/* This function writes out the input grid to a .dat file in current path */
static inline int heatWrite(const double * heatGrid, const int flag,
                            const int gridRows, const int gridCols,
                            const int threadsPerBlock, const int blocksPerGrid)
{
  char filePath[70] = "";
  if(flag == 0)
  {
    sprintf(filePath, "%d_%d_cuda_%d_%d_Initial.dat", gridRows, gridCols,
            threadsPerBlock, blocksPerGrid);
  }
  else
  {
    sprintf(filePath, "%d_%d_cuda_%d_%d_Final.dat", gridRows, gridCols,
            threadsPerBlock, blocksPerGrid);
  }

  FILE * fp = fopen(filePath, "w");
  if(fp == nullptr)
    return -1;
  for(int i = 0; i < gridRows; ++i)
  {
    for(int j = 0; j < gridCols; ++j)
    {
      fprintf(fp, "%-.1lf", fabs(heatGrid[i*gridCols+j]));//some 0.0s appear as -0.0s
      if(j != (gridCols - 1))
        fprintf(fp, " ");
    }
    fprintf(fp, "\n");
  }
  fclose(fp);
  return 0;//all ok
}

/* This function swaps between the 2 grids to avoid assignmenets */
static inline void heatSwap(double ** a, double ** b)
{
  double *temp = *a;
  *a = *b;
  *b = temp;
}

/* This function cleans up memory to prevent leaks on any exit error */
static inline void heatCleanExit(const int errorCode)
{
  if(heatGrid != nullptr)
  {
    free(heatGrid);
    heatGrid = nullptr;
  }
  if(devOldHeatGrid != nullptr)
  {
    CUDA_CHECK(cudaFree(devOldHeatGrid));
    devOldHeatGrid = nullptr;
  }
  if(devNewHeatGrid != nullptr)
  {
    CUDA_CHECK(cudaFree(devNewHeatGrid));
    devNewHeatGrid = nullptr;
  }
  if(workRowS != nullptr)
  {
    free(workRowS);
    workRowS = nullptr;
  }
  if(devWorkRowS != nullptr)
  {
    CUDA_CHECK(cudaFree(devWorkRowS));
    devWorkRowS = nullptr;
  }
  if(workRowE != nullptr)
  {
    free(workRowE);
    workRowE = nullptr;
  }
  if(devWorkRowE != nullptr)
  {
    CUDA_CHECK(cudaFree(devWorkRowE));
    devWorkRowE = nullptr;
  }
  if(workColS != nullptr)
  {
    free(workColS);
    workColS = nullptr;
  }
  if(devWorkColS != nullptr)
  {
    CUDA_CHECK(cudaFree(devWorkColS));
    devWorkColS = nullptr;
  }
  if(workColE != nullptr)
  {
    free(workColE);
    workColE = nullptr;
  }
  if(devWorkColE != nullptr)
  {
    CUDA_CHECK(cudaFree(devWorkColE));
    devWorkColE = nullptr;
  }
  exit(errorCode);
}

/* Main program function */
int main(int argc, char *argv[])
{
  //get the properties
  cudaDeviceProp deviceProp;
  CUDA_CHECK(cudaGetDeviceProperties(&deviceProp, 0));
  cout << "GPU PROPERTIES\n";
  cout << "******************************************************************\n";
  cout << "Cuda Device prop succeeded" << endl;
  cout << "System minor " << deviceProp.minor << endl;
  cout << "System major " << deviceProp.major << endl;
  cout << "Agent Prop Name " << deviceProp.name << endl;
  cout << "Total Global Memory " << deviceProp.totalGlobalMem << " bytes\n";
  cout << "Shared Memory Per Block " << deviceProp.sharedMemPerBlock << " bytes\n";
  cout << "Registers per block " << deviceProp.regsPerBlock << endl;
  cout << "Warp size " << deviceProp.warpSize << endl;
  cout << "Max Threads Per Block " << deviceProp.maxThreadsPerBlock << endl;
  cout << "Max clock frequency of the multiProcessors " << deviceProp.clockRate << " kHz\n";
  cout << "Size of shared memory region " << deviceProp.totalConstMem << " bytes\n";
  cout << "Number of multi-processors (compute units) " << deviceProp.multiProcessorCount << endl;
  cout << "******************************************************************\n\n";
  //get properties to check on input data possible run scenarios
  const int devMaxThreadsPerBlock = deviceProp.maxThreadsPerBlock;
  const int devMaxConcurrentThreads = deviceProp.multiProcessorCount *
                                      deviceProp.warpSize;

  //get the command line input data and do initial checks
  if(argc != 5)
  {
    cerr << "Not enough input data, need 4\n";
    cerr << "Grid_Rows Grid_Collumns Threads_Per_Block Blocks_Per_Grid\n";
    cerr << "Aborting...\n";
    heatCleanExit(-1);
  }
  const int gridRows = atoi(argv[1]);
  const int gridCols = atoi(argv[2]);
  const int threadsPerBlock = atoi(argv[3]);
  const int blocksPerGrid = atoi(argv[4]);
  const int gridSize = gridRows * gridCols;
  const int totalThreads = threadsPerBlock * blocksPerGrid;
  if(gridRows < 0 || gridCols < 0 || threadsPerBlock < 1 || blocksPerGrid < 1)
  {
    cerr << "Invalid Input Data\n";
    cerr << "Grid Rows = " << gridRows << endl;
    cerr << "Grid Cols = " << gridCols << endl;
    cerr << "Threads Per Block = " << threadsPerBlock << endl;
    cerr << "Blocks Per Grid = " << blocksPerGrid << endl;
    cerr << "Aborting...\n";
    heatCleanExit(-1);
  }
  //do checks based on device(GPU) capabilities
  if(threadsPerBlock > devMaxThreadsPerBlock)
  {
    cerr << "Maximum threads per block exceeded for current device\n";
    cerr << "Aborting...\n";
    heatCleanExit(-2);
  }
  if(totalThreads > devMaxConcurrentThreads)
  {
    cerr << "Maximum concurrent threads exceeded for current device\n";
    cerr << "Aborting...\n";
    heatCleanExit(-2);
  }

  //allocate host(CPU) memory
  heatGrid = (double *) malloc(gridSize * sizeof(double));
  if(heatGrid == nullptr)
  {
    cerr << "Error, not enough memory...\nAborting...\n";
    heatCleanExit(1);
  }

  //initialise with 0.0s the heat grid
  for(int i = 0; i < gridRows; ++i)
    for(int j = 0; j < gridCols; ++j)
      heatGrid[i*gridCols+j] = 0.0;

  //allocate device(GPU) global memory
  CUDA_CHECK(cudaMalloc((void **)&devNewHeatGrid, gridSize * sizeof(double)));

  //transfer data from host(CPU) to device(GPU) memory
  CUDA_CHECK(cudaMemcpy(devNewHeatGrid, heatGrid, gridSize * sizeof(double),
                      cudaMemcpyHostToDevice));

  //initialise the heat grid with actual data
  heatInit(heatGrid, gridRows, gridCols);

  //allocate device(GPU) global memory
  CUDA_CHECK(cudaMalloc((void **)&devOldHeatGrid, gridSize * sizeof(double)));

  //transfer data from host(CPU) to device(GPU) memory
  CUDA_CHECK(cudaMemcpy(devOldHeatGrid, heatGrid, gridSize * sizeof(double),
                      cudaMemcpyHostToDevice));

  //write out the initial grid to the corresponding file
  // if(heatWrite(heatGrid, 0, gridRows, gridCols,
               // threadsPerBlock, blocksPerGrid) == -1)
  // {
    // cerr << "Error, could not create the initial file...\nAborting...\n";
    // heatCleanExit(2);
  // }

  //calculate the kernel dimensions (x,y,z) threads/block and blocks/grid
  dim3 cudaThreads(threadsPerBlock, 1, 1);
  dim3 cudaBlocks(blocksPerGrid, 1 ,1);

  //define the timer structs to be used
  // struct timespec start;
  // struct timespec end;
  // double totalTime = 0.0;

  if(totalThreads == 1)//serial execution
  {
    cout << "Serial execution with 1 cuda thread\n";

    //start the timer
    //clock_gettime(CLOCK_MONOTONIC, &start);
	clock_t begin = clock();

    //solve the problem
    for(int steps = 0; steps < STEPS; ++steps)
    {
      //launch the kernel
      heatUpdateSerial<<<cudaBlocks, cudaThreads>>>(devOldHeatGrid, devNewHeatGrid,
                                                    gridRows, gridCols);

      //wait for device(GPU) to finish it's work
      CUDA_CHECK(cudaDeviceSynchronize());

      //old = new
      heatSwap(&devNewHeatGrid, &devOldHeatGrid);
    }

    //stop the timer and print the result
    //clock_gettime(CLOCK_MONOTONIC, &end);
	clock_t end = clock();
	double totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
    //totalTime = ((end.tv_sec - start.tv_sec) * 1000.0) +
    //            ((end.tv_nsec - start.tv_nsec) / 1000000.0); 
    cout << "\nElapsed time was " << totalTime << " ms\n";
  }
  else//parallel execution
  {
    //initial check on number of threads
    if(totalThreads % 2 != 0)
    {
      cout << "Can't parition grid fairly with odd number of threads = "
           << totalThreads
           << "\nAborting...\n";
      heatCleanExit(4);
    }
    cout << "Parallel execution with ";
    cout << "Threads Per Block : " << threadsPerBlock << endl;
    cout << "Blocks Per Grid : " << blocksPerGrid << endl;
    cout << "Total Cuda Threads : " << totalThreads << endl;

    //allocate arrays for neighbour discovery 
    //working border rows
    workRowS = (int *) malloc(totalThreads * sizeof(int));
    if(workRowS == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    workRowE = (int *) malloc(totalThreads * sizeof(int));
    if(workRowE == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    //working border collumns
    workColS = (int *) malloc(totalThreads * sizeof(int));
    if(workColS == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    workColE = (int *) malloc(totalThreads * sizeof(int));
    if(workColE == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    
    int blockRows = 0;//total rows for each block of threads data block
    int blockCols = 0;//total cols for each block of threads data block
    int threadsPerRow = 0, threadsPerCol = 0;//vertical and horizontal distrib

    //classify problem cases based on total threads
    int cut = (int) sqrt(totalThreads);
    double cutF = sqrt(totalThreads);
    int probCase;
    if(totalThreads == 2)//case 1 : handling 2 threads
    {
      blockRows = gridRows;
      blockCols = gridCols / totalThreads;
      threadsPerRow = gridRows / blockRows;
      threadsPerCol = gridCols / blockCols;
      if((threadsPerRow * threadsPerCol) != totalThreads)
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(6);
      }
      probCase = 1;
    }
    else if(cutF > (double) cut)//case 2.1 : handling 6, 8, 10, ... threads
    {
      if(gridSize % totalThreads != 0)//can't cut it without remains
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(7);
      }
      const int localProbSize = gridSize / totalThreads;
      int spread = gridSize;
      //find the best possible partition
      for(int i = gridRows; i > 0; --i)//priority to rows
      {
        for(int j = gridCols; j > 0; --j)
        {
          if((i * j) == localProbSize)
          {
            if(gridRows % i != 0 || gridCols % j != 0)
              continue;
            if(abs(i -j) < spread)
            {
              spread = abs(i - j);
              blockRows = i;
              blockCols = j;
            }
          }
        }
      }
      threadsPerRow = gridRows / blockRows;
      threadsPerCol = gridCols / blockCols;
      if((threadsPerRow * threadsPerCol) != totalThreads)
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(7);
      }
      probCase = 2;
    }
    else//case 2.2 : handling 4, 9, 16, ... threads
    {
      threadsPerRow = cut;
      threadsPerCol = cut;
      if((gridRows % cut != 0) || (gridCols % cut != 0))//can't cut even blocks
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(8);
      }
      blockRows = gridRows / cut;
      blockCols = gridCols / cut;
      probCase = 2;
    }

    printf("Grid can be partioned without remains...\n"
             "Rows per block : %d, Columns per block : %d\n"
             "Vertical threads : %d, Horizontal threads : %d\n\n",
             blockRows, blockCols, threadsPerRow, threadsPerCol);

    //working and global discovery phase
    //allocate device(GPU) global memory
    CUDA_CHECK(cudaMalloc((void **)&devWorkRowS, totalThreads * sizeof(int)));
    CUDA_CHECK(cudaMalloc((void **)&devWorkRowE, totalThreads * sizeof(int)));
    CUDA_CHECK(cudaMalloc((void **)&devWorkColS, totalThreads * sizeof(int)));
    CUDA_CHECK(cudaMalloc((void **)&devWorkColE, totalThreads * sizeof(int)));
    //transfer data from host(CPU) to device(GPU) memory
    CUDA_CHECK(cudaMemcpy(devWorkRowS, workRowS, totalThreads * sizeof(int),
                          cudaMemcpyHostToDevice));
    CUDA_CHECK(cudaMemcpy(devWorkRowE, workRowE, totalThreads * sizeof(int),
                          cudaMemcpyHostToDevice));
    CUDA_CHECK(cudaMemcpy(devWorkColS, workColS, totalThreads * sizeof(int),
                          cudaMemcpyHostToDevice));
    CUDA_CHECK(cudaMemcpy(devWorkColE, workColE, totalThreads * sizeof(int),
                          cudaMemcpyHostToDevice));

    heatDiscover<<<cudaBlocks, cudaThreads>>>
                (devWorkRowS, devWorkRowE, devWorkColS, devWorkColE,
                 blockRows, blockCols,
                 threadsPerRow, threadsPerCol, probCase,
                 gridRows, gridCols);

    //wait for device(GPU) to finish it's work
    CUDA_CHECK(cudaDeviceSynchronize());

    //start the timer
    // clock_gettime(CLOCK_MONOTONIC, &start);
	clock_t begin = clock();

    //launch the kernel
    for(int steps = 0; steps < STEPS; ++steps)
    {
      heatUpdateParallel<<<cudaBlocks, cudaThreads>>>
                        (devOldHeatGrid, devNewHeatGrid,
                         devWorkRowS, devWorkRowE, devWorkColS, devWorkColE,
                         gridCols);

      //wait for device(GPU) to finish it's work
      CUDA_CHECK(cudaDeviceSynchronize());

      //old = new
      heatSwap(&devNewHeatGrid, &devOldHeatGrid);
    }
    
    //stop the timer and print the result
	clock_t end = clock();
	double totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
    // clock_gettime(CLOCK_MONOTONIC, &end);
    // totalTime = ((end.tv_sec - start.tv_sec) * 1000.0) +
                // ((end.tv_nsec - start.tv_nsec) / 1000000.0); 
    cout << "\nElapsed time was " << totalTime << " ms\n";
  }

  if(STEPS % 2 == 0)//get the correct version
  {
    CUDA_CHECK(cudaMemcpy(heatGrid, devOldHeatGrid, gridSize * sizeof(double),
                        cudaMemcpyDeviceToHost));
  }
  else
  {
    CUDA_CHECK(cudaMemcpy(heatGrid, devNewHeatGrid, gridSize * sizeof(double),
                        cudaMemcpyDeviceToHost));
  }
  
  //write out the final grid to the corresponding file
  // if(heatWrite(heatGrid, 1, gridRows, gridCols,
               // threadsPerBlock, blocksPerGrid) == -1)
  // {
    // cerr << "Error, could not create the initial file...\nAborting...\n";
    // heatCleanExit(3);
  // }

  //clear memory and exit
  heatCleanExit(0);
}
	.file	"tmpxft_002c77af_00000000-6_cuda_Heat2D.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3896:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3896:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4557:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4557:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Error : Cuda reports "
	.text
	.type	_ZL13heatCleanExiti, @function
_ZL13heatCleanExiti:
.LFB3892:
	.cfi_startproc
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rax
	.cfi_def_cfa_offset 32
	movq	heatGrid(%rip), %rdi
	testq	%rdi, %rdi
	je	.L4
	call	free@PLT
	xorl	%eax, %eax
	movq	%rax, heatGrid(%rip)
.L4:
	movq	devOldHeatGrid(%rip), %rdi
	testq	%rdi, %rdi
	je	.L5
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L57
	xorl	%ebx, %ebx
	movq	%rbx, devOldHeatGrid(%rip)
.L5:
	movq	devNewHeatGrid(%rip), %rdi
	testq	%rdi, %rdi
	je	.L7
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L57
	xorl	%r11d, %r11d
	movq	%r11, devNewHeatGrid(%rip)
.L7:
	movq	workRowS(%rip), %rdi
	testq	%rdi, %rdi
	je	.L9
	call	free@PLT
	xorl	%r10d, %r10d
	movq	%r10, workRowS(%rip)
.L9:
	movq	devWorkRowS(%rip), %rdi
	testq	%rdi, %rdi
	je	.L10
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L57
	xorl	%r9d, %r9d
	movq	%r9, devWorkRowS(%rip)
.L10:
	movq	workRowE(%rip), %rdi
	testq	%rdi, %rdi
	je	.L12
	call	free@PLT
	xorl	%r8d, %r8d
	movq	%r8, workRowE(%rip)
.L12:
	movq	devWorkRowE(%rip), %rdi
	testq	%rdi, %rdi
	je	.L13
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L57
	xorl	%edi, %edi
	movq	%rdi, devWorkRowE(%rip)
.L13:
	movq	workColS(%rip), %rdi
	testq	%rdi, %rdi
	je	.L15
	call	free@PLT
	xorl	%esi, %esi
	movq	%rsi, workColS(%rip)
.L15:
	movq	devWorkColS(%rip), %rdi
	testq	%rdi, %rdi
	je	.L16
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L57
	xorl	%ecx, %ecx
	movq	%rcx, devWorkColS(%rip)
.L16:
	movq	workColE(%rip), %rdi
	testq	%rdi, %rdi
	je	.L18
	call	free@PLT
	xorl	%edx, %edx
	movq	%rdx, workColE(%rip)
.L18:
	movq	devWorkColE(%rip), %rdi
	testq	%rdi, %rdi
	je	.L19
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L20
.L57:
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$-6, %edi
	call	_ZL13heatCleanExiti
.L20:
	xorl	%eax, %eax
	movq	%rax, devWorkColE(%rip)
.L19:
	movl	%ebp, %edi
	call	exit@PLT
	.cfi_endproc
.LFE3892:
	.size	_ZL13heatCleanExiti, .-_ZL13heatCleanExiti
	.globl	_Z45__device_stub__Z12heatDiscoverPiS_S_S_iiiiiiiPiS_S_S_iiiiiii
	.type	_Z45__device_stub__Z12heatDiscoverPiS_S_S_iiiiiiiPiS_S_S_iiiiiii, @function
_Z45__device_stub__Z12heatDiscoverPiS_S_S_iiiiiiiPiS_S_S_iiiiiii:
.LFB3918:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z12heatDiscoverPiS_S_S_iiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L59:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3918:
	.size	_Z45__device_stub__Z12heatDiscoverPiS_S_S_iiiiiiiPiS_S_S_iiiiiii, .-_Z45__device_stub__Z12heatDiscoverPiS_S_S_iiiiiiiPiS_S_S_iiiiiii
	.globl	_Z12heatDiscoverPiS_S_S_iiiiiii
	.type	_Z12heatDiscoverPiS_S_S_iiiiiii, @function
_Z12heatDiscoverPiS_S_S_iiiiiii:
.LFB3919:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z12heatDiscoverPiS_S_S_iiiiiiiPiS_S_S_iiiiiii
	.cfi_endproc
.LFE3919:
	.size	_Z12heatDiscoverPiS_S_S_iiiiiii, .-_Z12heatDiscoverPiS_S_S_iiiiiii
	.globl	_Z41__device_stub__Z16heatUpdateSerialPKdPdiiPKdPdii
	.type	_Z41__device_stub__Z16heatUpdateSerialPKdPdiiPKdPdii, @function
_Z41__device_stub__Z16heatUpdateSerialPKdPdiiPKdPdii:
.LFB3920:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16heatUpdateSerialPKdPdii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L64:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3920:
	.size	_Z41__device_stub__Z16heatUpdateSerialPKdPdiiPKdPdii, .-_Z41__device_stub__Z16heatUpdateSerialPKdPdiiPKdPdii
	.globl	_Z16heatUpdateSerialPKdPdii
	.type	_Z16heatUpdateSerialPKdPdii, @function
_Z16heatUpdateSerialPKdPdii:
.LFB3921:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z16heatUpdateSerialPKdPdiiPKdPdii
	.cfi_endproc
.LFE3921:
	.size	_Z16heatUpdateSerialPKdPdii, .-_Z16heatUpdateSerialPKdPdii
	.globl	_Z54__device_stub__Z18heatUpdateParallelPKdPdPKiS3_S3_S3_iPKdPdPKiS3_S3_S3_i
	.type	_Z54__device_stub__Z18heatUpdateParallelPKdPdPKiS3_S3_S3_iPKdPdPKiS3_S3_S3_i, @function
_Z54__device_stub__Z18heatUpdateParallelPKdPdPKiS3_S3_S3_iPKdPdPKiS3_S3_S3_i:
.LFB3922:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rsi, 8(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 32(%rsp)
	movq	%r9, 40(%rsp)
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L69:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L71
	call	__stack_chk_fail@PLT
.L71:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3922:
	.size	_Z54__device_stub__Z18heatUpdateParallelPKdPdPKiS3_S3_S3_iPKdPdPKiS3_S3_S3_i, .-_Z54__device_stub__Z18heatUpdateParallelPKdPdPKiS3_S3_S3_iPKdPdPKiS3_S3_S3_i
	.globl	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.type	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i, @function
_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i:
.LFB3923:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z18heatUpdateParallelPKdPdPKiS3_S3_S3_iPKdPdPKiS3_S3_S3_i
	.cfi_endproc
.LFE3923:
	.size	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i, .-_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.section	.rodata.str1.1
.LC1:
	.string	"GPU PROPERTIES\n"
.LC2:
	.string	"******************************************************************\n"
.LC3:
	.string	"Cuda Device prop succeeded"
.LC4:
	.string	"System minor "
.LC5:
	.string	"System major "
.LC6:
	.string	"Agent Prop Name "
.LC7:
	.string	"Total Global Memory "
.LC8:
	.string	" bytes\n"
.LC9:
	.string	"Shared Memory Per Block "
.LC10:
	.string	"Registers per block "
.LC11:
	.string	"Warp size "
.LC12:
	.string	"Max Threads Per Block "
.LC13:
	.string	"Max clock frequency of the multiProcessors "
.LC14:
	.string	" kHz\n"
.LC15:
	.string	"Size of shared memory region "
.LC16:
	.string	"Number of multi-processors (compute units) "
.LC17:
	.string	"******************************************************************\n\n"
.LC18:
	.string	"Not enough input data, need 4\n"
.LC19:
	.string	"Grid_Rows Grid_Collumns Threads_Per_Block Blocks_Per_Grid\n"
.LC20:
	.string	"Aborting...\n"
.LC21:
	.string	"Invalid Input Data\n"
.LC22:
	.string	"Grid Rows = "
.LC23:
	.string	"Grid Cols = "
.LC24:
	.string	"Threads Per Block = "
.LC25:
	.string	"Blocks Per Grid = "
.LC26:
	.string	"Maximum threads per block exceeded for current device\n"
.LC27:
	.string	"Maximum concurrent threads exceeded for current device\n"
.LC28:
	.string	"Error, not enough memory...\nAborting...\n"
.LC30:
	.string	"Serial execution with 1 cuda thread\n"
.LC32:
	.string	"\nElapsed time was "
.LC33:
	.string	" ms\n"
.LC34:
	.string	"Can't parition grid fairly with odd number of threads = "
.LC35:
	.string	"\nAborting...\n"
.LC36:
	.string	"Parallel execution with "
.LC37:
	.string	"Threads Per Block : "
.LC38:
	.string	"Blocks Per Grid : "
.LC39:
	.string	"Total Cuda Threads : "
.LC40:
	.string	"Grid partitioning results to remains...\nAborting...\n"
.LC41:
	.string	"Grid can be partioned without remains...\nRows per block : %d, Columns per block : %d\nVertical threads : %d, Horizontal threads : %d\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3893:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	xorl	%esi, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$1112, %rsp
	.cfi_def_cfa_offset 1168
	movq	%fs:40, %rax
	movq	%rax, 1096(%rsp)
	xorl	%eax, %eax
	leaq	64(%rsp), %rbp
	movq	%rbp, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	.L188
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	428(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC5(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	424(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	leaq	.LC8(%rip), %rbp
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	352(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	360(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC10(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	368(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC11(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	372(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC12(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	384(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC13(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	412(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC15(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	416(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC16(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	452(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC17(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	384(%rsp), %r15d
	movl	452(%rsp), %edx
	movl	372(%rsp), %r14d
	cmpl	$5, %ebx
	je	.L77
	leaq	_ZSt4cerr(%rip), %rbx
	leaq	.LC18(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC19(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC20(%rip), %rsi
	movq	%rbx, %rdi
	jmp	.L180
.L77:
	movq	8(%r12), %rdi
	movl	%edx, 8(%rsp)
	call	atoi@PLT
	movq	16(%r12), %rdi
	movl	%eax, (%rsp)
	call	atoi@PLT
	movq	24(%r12), %rdi
	movl	%eax, %ebx
	call	atoi@PLT
	movq	32(%r12), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movl	%eax, %r12d
	movl	(%rsp), %eax
	orl	%ebx, %eax
	js	.L79
	testl	%ebp, %ebp
	jle	.L79
	testl	%r12d, %r12d
	movl	8(%rsp), %edx
	jg	.L80
.L79:
	leaq	_ZSt4cerr(%rip), %r13
	leaq	.LC21(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC22(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC23(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC24(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC25(%rip), %rsi
	movq	%r13, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC20(%rip), %rsi
	movq	%r13, %rdi
.L180:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L179
	orl	$-1, %edi
	jmp	.L178
.L80:
	leaq	.LC26(%rip), %rsi
	cmpl	%ebp, %r15d
	jl	.L181
	movl	%ebp, %r15d
	imull	%r14d, %edx
	imull	%r12d, %r15d
	cmpl	%r15d, %edx
	jge	.L85
	leaq	.LC27(%rip), %rsi
.L181:
	leaq	_ZSt4cerr(%rip), %rbx
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbx, %rdi
	leaq	.LC20(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$-2, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L85:
	movl	(%rsp), %r14d
	imull	%ebx, %r14d
	movslq	%r14d, %rax
	salq	$3, %rax
	movq	%rax, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	xorl	%ecx, %ecx
	movq	%rax, heatGrid(%rip)
	testq	%rax, %rax
	jne	.L88
	leaq	_ZSt4cerr(%rip), %rdi
	leaq	.LC28(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L189:
	incl	%ecx
	addl	%ebx, %r13d
.L88:
	movl	(%rsp), %edx
	cmpl	%edx, %ecx
	jge	.L91
	movslq	%r13d, %rdx
	leaq	(%rax,%rdx,8), %rsi
	xorl	%edx, %edx
.L92:
	cmpl	%edx, %ebx
	jle	.L189
	movq	$0x000000000, (%rsi,%rdx,8)
	incq	%rdx
	jmp	.L92
.L91:
	movq	16(%rsp), %rsi
	leaq	devNewHeatGrid(%rip), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	.L188
	movq	16(%rsp), %rdx
	movq	heatGrid(%rip), %rsi
	movl	$1, %ecx
	movq	devNewHeatGrid(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	.L188
	movl	(%rsp), %eax
	movq	heatGrid(%rip), %r10
	xorl	%esi, %esi
	xorl	%edx, %edx
	leal	-1(%rax), %r11d
.L97:
	cmpl	%edx, (%rsp)
	jle	.L99
	movl	%r11d, %edi
	movslq	%esi, %rax
	xorl	%ecx, %ecx
	subl	%edx, %edi
	leaq	(%r10,%rax,8), %r9
	xorl	%eax, %eax
	imull	%edx, %edi
.L100:
	incq	%rax
	leal	-1(%rax), %r8d
	cmpl	%r8d, %ebx
	jle	.L190
	movl	%ebx, %r8d
	subl	%eax, %r8d
	imull	%ecx, %r8d
	addl	%edi, %ecx
	cvtsi2sdl	%r8d, %xmm0
	movsd	%xmm0, -8(%r9,%rax,8)
	jmp	.L100
.L190:
	incl	%edx
	addl	%ebx, %esi
	jmp	.L97
.L99:
	movq	16(%rsp), %rsi
	leaq	devOldHeatGrid(%rip), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	.L188
	movq	16(%rsp), %rdx
	movq	heatGrid(%rip), %rsi
	movl	$1, %ecx
	movq	devOldHeatGrid(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	jne	.L188
	movabsq	$4294967297, %rax
	movl	%ebp, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	%r12d, 52(%rsp)
	movq	%rax, 56(%rsp)
	cmpl	$1, %r15d
	jne	.L105
	leaq	.LC30(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movl	$1000, %r12d
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	call	clock@PLT
	movq	%rax, %rbp
.L109:
	movl	48(%rsp), %ecx
	movq	40(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L106
	movl	(%rsp), %edx
	movq	devNewHeatGrid(%rip), %rsi
	movl	%ebx, %ecx
	movq	devOldHeatGrid(%rip), %rdi
	call	_Z41__device_stub__Z16heatUpdateSerialPKdPdiiPKdPdii
.L106:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	je	.L107
.L188:
	leaq	_ZSt4cerr(%rip), %rdi
	leaq	.LC0(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %edi
	movq	%rax, %rbx
	jmp	.L183
.L107:
	movq	devNewHeatGrid(%rip), %rax
	movq	devOldHeatGrid(%rip), %rdx
	movq	%rax, devOldHeatGrid(%rip)
	movq	%rdx, devNewHeatGrid(%rip)
	decl	%r12d
	jne	.L109
	call	clock@PLT
	subq	%rbp, %rax
	jmp	.L176
.L105:
	testl	$1, %r15d
	je	.L111
	leaq	.LC34(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r15d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC35(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$4, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L111:
	leaq	.LC36(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC37(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC38(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC39(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r15d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movslq	%r15d, %rax
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%rax, workRowS(%rip)
	testq	%rax, %rax
	jne	.L113
.L115:
	leaq	_ZSt4cerr(%rip), %rdi
	leaq	.LC28(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$5, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L113:
	movq	8(%rsp), %rdi
	call	malloc@PLT
	movq	%rax, workRowE(%rip)
	testq	%rax, %rax
	je	.L115
	movq	8(%rsp), %rdi
	call	malloc@PLT
	movq	%rax, workColS(%rip)
	testq	%rax, %rax
	je	.L115
	movq	8(%rsp), %rdi
	call	malloc@PLT
	movq	%rax, workColE(%rip)
	testq	%rax, %rax
	je	.L115
	cvtsi2sdl	%r15d, %xmm2
	movaps	%xmm2, %xmm0
	movq	%xmm2, %rbp
	call	sqrt@PLT
	movq	%xmm0, %r12
	movq	%rbp, %xmm0
	call	sqrt@PLT
	cmpl	$2, %r15d
	jne	.L116
	movl	%ebx, %eax
	movl	%ebx, %ebp
	sarl	%ebp
	cltd
	idivl	%ebp
	movl	%eax, %r14d
	cmpl	$2, %eax
	je	.L159
	leaq	_ZSt4cout(%rip), %rdi
	leaq	.LC40(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$6, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L116:
	movq	%r12, %xmm3
	cvttsd2sil	%xmm3, %r12d
	cvtsi2sdl	%r12d, %xmm1
	comisd	%xmm1, %xmm0
	jbe	.L173
	movl	%r14d, %eax
	cltd
	idivl	%r15d
	movl	%edx, %r13d
	movl	%eax, %r9d
	testl	%edx, %edx
	je	.L121
.L128:
	leaq	_ZSt4cout(%rip), %rdi
	leaq	.LC40(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$7, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L121:
	movl	(%rsp), %ecx
	movl	%r14d, %r8d
	xorl	%ebp, %ebp
.L123:
	testl	%ecx, %ecx
	je	.L126
	movl	%r8d, %edi
	movl	%ebx, %esi
.L127:
	testl	%esi, %esi
	je	.L191
	cmpl	%edi, %r9d
	jne	.L124
	movl	(%rsp), %eax
	cltd
	idivl	%ecx
	testl	%edx, %edx
	jne	.L124
	movl	%ebx, %eax
	cltd
	idivl	%esi
	testl	%edx, %edx
	jne	.L124
	movl	%ecx, %edx
	subl	%esi, %edx
	movl	%edx, %eax
	negl	%eax
	cmovs	%edx, %eax
	cmpl	%r14d, %eax
	jge	.L124
	movl	%eax, %r14d
	movl	%esi, %ebp
	movl	%ecx, %r13d
.L124:
	decl	%esi
	subl	%ecx, %edi
	jmp	.L127
.L191:
	decl	%ecx
	subl	%ebx, %r8d
	jmp	.L123
.L126:
	movl	(%rsp), %eax
	cltd
	idivl	%r13d
	movl	%eax, %r12d
	movl	%ebx, %eax
	cltd
	idivl	%ebp
	movl	%eax, %r14d
	movl	%r12d, %eax
	imull	%r14d, %eax
	cmpl	%r15d, %eax
	je	.L175
	jmp	.L128
.L173:
	movl	(%rsp), %eax
	cltd
	idivl	%r12d
	movl	%eax, %r13d
	testl	%edx, %edx
	jne	.L129
	movl	%ebx, %eax
	cltd
	idivl	%r12d
	testl	%edx, %edx
	je	.L130
.L129:
	leaq	_ZSt4cout(%rip), %rdi
	leaq	.LC40(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$8, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L130:
	movl	%eax, %ebp
	movl	%r12d, %r14d
.L175:
	movl	$2, %r15d
	jmp	.L117
.L159:
	movl	(%rsp), %r13d
	movl	$1, %r15d
	movl	$1, %r12d
.L117:
	movl	%r14d, %r9d
	movl	%r12d, %r8d
	movl	%ebp, %ecx
	movl	%r13d, %edx
	leaq	.LC41(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	leaq	devWorkRowS(%rip), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	movl	%eax, 28(%rsp)
	jne	.L185
	movq	8(%rsp), %rsi
	leaq	devWorkRowE(%rip), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	movl	%eax, 28(%rsp)
	je	.L134
.L185:
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	28(%rsp), %edx
	movq	%rax, %rbx
.L184:
	movl	%edx, %edi
.L183:
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	jmp	.L182
.L134:
	movq	8(%rsp), %rsi
	leaq	devWorkColS(%rip), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	movl	%eax, 28(%rsp)
	jne	.L185
	movq	8(%rsp), %rsi
	leaq	devWorkColE(%rip), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	movl	%eax, 28(%rsp)
	jne	.L185
	movq	8(%rsp), %rdx
	movq	workRowS(%rip), %rsi
	movl	$1, %ecx
	movq	devWorkRowS(%rip), %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	movl	%eax, 28(%rsp)
	jne	.L185
	movq	8(%rsp), %rdx
	movq	workRowE(%rip), %rsi
	movl	$1, %ecx
	movq	devWorkRowE(%rip), %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	movl	%eax, 28(%rsp)
	jne	.L185
	movq	8(%rsp), %rdx
	movq	workColS(%rip), %rsi
	movl	$1, %ecx
	movq	devWorkColS(%rip), %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	movl	%eax, 28(%rsp)
	jne	.L185
	movq	8(%rsp), %rdx
	movq	workColE(%rip), %rsi
	movl	$1, %ecx
	movq	devWorkColE(%rip), %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	movl	%eax, 8(%rsp)
	je	.L146
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	8(%rsp), %edx
	movq	%rax, %rbx
	jmp	.L184
.L146:
	movl	48(%rsp), %ecx
	movq	40(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L148
	pushq	%rsi
	.cfi_def_cfa_offset 1176
	movq	devWorkColE(%rip), %rcx
	movl	%ebp, %r9d
	movl	%r13d, %r8d
	movq	devWorkColS(%rip), %rdx
	movq	devWorkRowE(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 1184
	movl	16(%rsp), %eax
	movq	devWorkRowS(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 1192
	pushq	%r15
	.cfi_def_cfa_offset 1200
	pushq	%r14
	.cfi_def_cfa_offset 1208
	pushq	%r12
	.cfi_def_cfa_offset 1216
	call	_Z45__device_stub__Z12heatDiscoverPiS_S_S_iiiiiiiPiS_S_S_iiiiiii
	addq	$48, %rsp
	.cfi_def_cfa_offset 1168
.L148:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	jne	.L187
	call	clock@PLT
	movl	$1000, %r13d
	movq	%rax, %r12
.L154:
	movl	48(%rsp), %ecx
	movq	40(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L151
	movq	devWorkRowE(%rip), %rcx
	movq	devWorkRowS(%rip), %rdx
	pushq	%rax
	.cfi_def_cfa_offset 1176
	movq	devWorkColE(%rip), %r9
	movq	devWorkColS(%rip), %r8
	pushq	%rbx
	.cfi_def_cfa_offset 1184
	movq	devNewHeatGrid(%rip), %rsi
	movq	devOldHeatGrid(%rip), %rdi
	call	_Z54__device_stub__Z18heatUpdateParallelPKdPdPKiS3_S3_S3_iPKdPdPKiS3_S3_S3_i
	popq	%rdx
	.cfi_def_cfa_offset 1176
	popq	%rcx
	.cfi_def_cfa_offset 1168
.L151:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L152
.L187:
	leaq	_ZSt4cerr(%rip), %rdi
	leaq	.LC0(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	jmp	.L183
.L152:
	movq	devNewHeatGrid(%rip), %rax
	movq	devOldHeatGrid(%rip), %rdx
	movq	%rax, devOldHeatGrid(%rip)
	movq	%rdx, devNewHeatGrid(%rip)
	decl	%r13d
	jne	.L154
	call	clock@PLT
	subq	%r12, %rax
.L176:
	leaq	.LC32(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC31(%rip), %xmm0
	movsd	%xmm0, (%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC33(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	16(%rsp), %rdx
	movl	$2, %ecx
	movq	devOldHeatGrid(%rip), %rsi
	movq	heatGrid(%rip), %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L155
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
.L182:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$-6, %edi
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	jmp	.L179
.L155:
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L157
.L179:
	call	__stack_chk_fail@PLT
.L157:
	xorl	%edi, %edi
.L178:
	call	_ZL13heatCleanExiti
	.cfi_endproc
.LFE3893:
	.size	main, .-main
	.section	.rodata.str1.1
.LC42:
	.string	"_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i"
.LC43:
	.string	"_Z16heatUpdateSerialPKdPdii"
.LC44:
	.string	"_Z12heatDiscoverPiS_S_S_iiiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3925:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC42(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC43(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16heatUpdateSerialPKdPdii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC44(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12heatDiscoverPiS_S_S_iiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3925:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	devWorkColE
	.bss
	.align 8
	.type	devWorkColE, @object
	.size	devWorkColE, 8
devWorkColE:
	.zero	8
	.globl	devWorkColS
	.align 8
	.type	devWorkColS, @object
	.size	devWorkColS, 8
devWorkColS:
	.zero	8
	.globl	devWorkRowE
	.align 8
	.type	devWorkRowE, @object
	.size	devWorkRowE, 8
devWorkRowE:
	.zero	8
	.globl	devWorkRowS
	.align 8
	.type	devWorkRowS, @object
	.size	devWorkRowS, 8
devWorkRowS:
	.zero	8
	.globl	workColE
	.align 8
	.type	workColE, @object
	.size	workColE, 8
workColE:
	.zero	8
	.globl	workColS
	.align 8
	.type	workColS, @object
	.size	workColS, 8
workColS:
	.zero	8
	.globl	workRowE
	.align 8
	.type	workRowE, @object
	.size	workRowE, 8
workRowE:
	.zero	8
	.globl	workRowS
	.align 8
	.type	workRowS, @object
	.size	workRowS, 8
workRowS:
	.zero	8
	.globl	devOldHeatGrid
	.align 8
	.type	devOldHeatGrid, @object
	.size	devOldHeatGrid, 8
devOldHeatGrid:
	.zero	8
	.globl	devNewHeatGrid
	.align 8
	.type	devNewHeatGrid, @object
	.size	devNewHeatGrid, 8
devNewHeatGrid:
	.zero	8
	.globl	heatGrid
	.align 8
	.type	heatGrid, @object
	.size	heatGrid, 8
heatGrid:
	.zero	8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC31:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <assert.h>
//#include <sys/time.h>
#include <time.h>

#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cmath>
#include <algorithm>

using std::cout;
using std::endl;
using std::cerr;

#define DECLINE_HORIZONTAL 0.1
#define DECLINE_VERTICAL   0.1
#define STEPS              1000               /* number of time steps */

/* error check on hip macro */
#define CUDA_CHECK(command) \
{ \
  hipError_t status = command; \
  if(status != hipSuccess) \
  { \
    cerr << "Error : Cuda reports " << hipGetErrorString(status) << endl; \
    heatCleanExit(-6); \
  } \
}

/* Device(GPU) FUNCTIONS TO BE LAUNCHED AS KERNELS FROM HOST(CPU) */
/* This function is used to discover the local working area of each thread */
__global__ void heatDiscover(int * __restrict__ workRowS,
                             int * __restrict__ workRowE,
                             int * __restrict__ workColS,
                             int * __restrict__ workColE,
                             const int blockRows, const int blockCols,
                             const int threadsPerRow, const int threadsPerCol,
                             const int probCase,
                             const int gridRows, const int gridCols)
{
  const int thread_Id = blockIdx.x * blockDim.x + threadIdx.x;
  if(probCase == 1)//2 threads
  {
    if(thread_Id == 0)//west thread
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 2;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else//east thread
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 2;
      workColS[thread_Id] = blockCols;
      workColE[thread_Id] = gridCols - 2;
    } 
  }
  else if(probCase == 2)//6, 8, 10, ... OR 4, 16, 64 ... threads
  {
    if(thread_Id == 0)//NW corner
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 1;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else if(thread_Id == (threadsPerCol - 1))//NE corner
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 1;
      workColS[thread_Id] = gridCols - blockCols;
      workColE[thread_Id] = gridCols - 2;
    }
    else if(thread_Id == ((threadsPerRow * threadsPerCol) - threadsPerCol))//SW corner
    {
      workRowS[thread_Id] = gridRows - blockRows;
      workRowE[thread_Id] = gridRows - 2;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else if(thread_Id == ((threadsPerCol * threadsPerRow) - 1))//SE corner
    {
      workRowS[thread_Id] = gridRows - blockRows;
      workRowE[thread_Id] = gridRows - 2;
      workColS[thread_Id] = gridCols - blockCols;
      workColE[thread_Id] = gridCols - 2;
    }
    else if(thread_Id < threadsPerCol)//NN side
    {
      workRowS[thread_Id] = 1;
      workRowE[thread_Id] = blockRows - 1;
      workColS[thread_Id] = thread_Id * blockCols;
      workColE[thread_Id] = workColS[thread_Id] + blockCols - 1;
    }
    else if((thread_Id > ((threadsPerCol * threadsPerRow) - threadsPerCol)) && 
            (thread_Id < ((threadsPerCol * threadsPerRow) - 1)))//SS side
    {
      workRowS[thread_Id] = gridRows - blockRows;
      workRowE[thread_Id] = gridRows - 2;
      workColS[thread_Id] = (thread_Id % threadsPerCol) * blockCols;
      workColE[thread_Id] =  workColS[thread_Id] + blockCols - 1;
    }
    else if((thread_Id % threadsPerCol) == 0)//WW side
    {
      workRowS[thread_Id] = (thread_Id / threadsPerCol) * blockRows;
      workRowE[thread_Id] = workRowS[thread_Id] + blockRows - 1;
      workColS[thread_Id] = 1;
      workColE[thread_Id] = blockCols - 1;
    }
    else if((thread_Id + 1) % threadsPerCol == 0)//EE side
    {
      workRowS[thread_Id] = ((thread_Id + 1 - threadsPerCol) / threadsPerCol) *
                              blockRows;
      workRowE[thread_Id] = workRowS[thread_Id] + blockRows - 1;
      workColS[thread_Id] = gridCols - blockCols;
      workColE[thread_Id] = gridCols - 2;
    }
    else//general case middle location
    {
      int rowMarginS = threadsPerCol;
      int rowMarginE = rowMarginS + threadsPerCol - 1;
      int rowOffset = 1;
      while(1)
      {
        if((thread_Id > rowMarginS) && (thread_Id < rowMarginE))
        {
          workRowS[thread_Id] = rowOffset * blockRows;
          break;
        }
        else
        {
          rowMarginS += threadsPerCol;
          rowMarginE += threadsPerCol;
          ++rowOffset;
        }
      }
      workRowE[thread_Id] = workRowS[thread_Id] + blockRows - 1;
      workColS[thread_Id] = (thread_Id % threadsPerCol) * blockCols;
      workColE[thread_Id] = workColS[thread_Id] + blockCols - 1;
    }
  }
}

/* This function updates the grid and is invoked on serial executions */
__global__ void heatUpdateSerial(const double * __restrict__ devOldHeatGrid,
                                       double * __restrict__ devNewHeatGrid,
                                 const int gridRows, const int gridCols)
{
  for(int i = 1; i < gridRows - 1; ++i)
  {
    for(int j = 1; j < gridCols - 1; ++j)
    {
      devNewHeatGrid[i*gridCols+j] = devOldHeatGrid[i*gridCols+j] +
                                    DECLINE_HORIZONTAL *
                                    (devOldHeatGrid[(i+1)*gridCols+j] +
                                    devOldHeatGrid[(i-1)*gridCols+j] -
                                    (2 * devOldHeatGrid[i*gridCols+j])) +
                                    DECLINE_VERTICAL *
                                    (devOldHeatGrid[i*gridCols+j+1] +
                                    devOldHeatGrid[i*gridCols+j-1] -
                                    (2 * devOldHeatGrid[i*gridCols+j]));
    }
  }    
}

/* This function updates the grid and is invoked on parallel executions */
__global__ void heatUpdateParallel(const double * __restrict__ devOldHeatGrid,
                                   double       * __restrict__ devNewHeatGrid,
                                   const int    * __restrict__ workRowS,
                                   const int    * __restrict__ workRowE,
                                   const int    * __restrict__ workColS,
                                   const int    * __restrict__ workColE,
                                   const int                   gridCols)
{
  const int thread_Id = blockIdx.x * blockDim.x + threadIdx.x;
  //get the borders in registers for 1 cycle memory access
  const int wRowS = workRowS[thread_Id];
  const int wRowE = workRowE[thread_Id];
  const int wColS = workColS[thread_Id];
  const int wColE = workColE[thread_Id];

  for(int i = wRowS; i <= wRowE; ++i)
  {
    for(int j = wColS; j <= wColE; ++j)
    {
      devNewHeatGrid[i*gridCols+j] = devOldHeatGrid[i*gridCols+j] +
                                 DECLINE_HORIZONTAL *
                                 (devOldHeatGrid[(i+1)*gridCols+j] +
                                 devOldHeatGrid[(i-1)*gridCols+j] -
                                 (2*devOldHeatGrid[i*gridCols+j])) +
                                 DECLINE_VERTICAL *
                                 (devOldHeatGrid[i*gridCols+j+1] +
                                 devOldHeatGrid[i*gridCols+j-1] -
                                 (2*devOldHeatGrid[i*gridCols+j]));
    }
  }
}                                      

//declare dynamic variables
double * heatGrid = nullptr;
double * devNewHeatGrid = nullptr;
double * devOldHeatGrid = nullptr;
int * workRowS = nullptr;
int * workRowE = nullptr;
int * workColS = nullptr;
int * workColE = nullptr;
int * devWorkRowS = nullptr;
int * devWorkRowE = nullptr;
int * devWorkColS = nullptr;
int * devWorkColE = nullptr;

/* HOST(CPU) FUNCTIONS */
/* This function intialises the temperature on the given grid with higher
   temperatures at the centre, progressively lower ones until the sides 
   and 0s at the perimetre 
*/
static inline void heatInit(double * heatGrid,
                            const int gridRows, const int gridCols)
{
  for(int i = 0; i < gridRows; ++i)//avoid halo area
    for(int j = 0; j < gridCols; ++j)
      heatGrid[i*gridCols+j] = (double) (i * (gridRows - i - 1) * j * (gridCols - j - 1));
}

/* This function writes out the input grid to a .dat file in current path */
static inline int heatWrite(const double * heatGrid, const int flag,
                            const int gridRows, const int gridCols,
                            const int threadsPerBlock, const int blocksPerGrid)
{
  char filePath[70] = "";
  if(flag == 0)
  {
    sprintf(filePath, "%d_%d_cuda_%d_%d_Initial.dat", gridRows, gridCols,
            threadsPerBlock, blocksPerGrid);
  }
  else
  {
    sprintf(filePath, "%d_%d_cuda_%d_%d_Final.dat", gridRows, gridCols,
            threadsPerBlock, blocksPerGrid);
  }

  FILE * fp = fopen(filePath, "w");
  if(fp == nullptr)
    return -1;
  for(int i = 0; i < gridRows; ++i)
  {
    for(int j = 0; j < gridCols; ++j)
    {
      fprintf(fp, "%-.1lf", fabs(heatGrid[i*gridCols+j]));//some 0.0s appear as -0.0s
      if(j != (gridCols - 1))
        fprintf(fp, " ");
    }
    fprintf(fp, "\n");
  }
  fclose(fp);
  return 0;//all ok
}

/* This function swaps between the 2 grids to avoid assignmenets */
static inline void heatSwap(double ** a, double ** b)
{
  double *temp = *a;
  *a = *b;
  *b = temp;
}

/* This function cleans up memory to prevent leaks on any exit error */
static inline void heatCleanExit(const int errorCode)
{
  if(heatGrid != nullptr)
  {
    free(heatGrid);
    heatGrid = nullptr;
  }
  if(devOldHeatGrid != nullptr)
  {
    CUDA_CHECK(hipFree(devOldHeatGrid));
    devOldHeatGrid = nullptr;
  }
  if(devNewHeatGrid != nullptr)
  {
    CUDA_CHECK(hipFree(devNewHeatGrid));
    devNewHeatGrid = nullptr;
  }
  if(workRowS != nullptr)
  {
    free(workRowS);
    workRowS = nullptr;
  }
  if(devWorkRowS != nullptr)
  {
    CUDA_CHECK(hipFree(devWorkRowS));
    devWorkRowS = nullptr;
  }
  if(workRowE != nullptr)
  {
    free(workRowE);
    workRowE = nullptr;
  }
  if(devWorkRowE != nullptr)
  {
    CUDA_CHECK(hipFree(devWorkRowE));
    devWorkRowE = nullptr;
  }
  if(workColS != nullptr)
  {
    free(workColS);
    workColS = nullptr;
  }
  if(devWorkColS != nullptr)
  {
    CUDA_CHECK(hipFree(devWorkColS));
    devWorkColS = nullptr;
  }
  if(workColE != nullptr)
  {
    free(workColE);
    workColE = nullptr;
  }
  if(devWorkColE != nullptr)
  {
    CUDA_CHECK(hipFree(devWorkColE));
    devWorkColE = nullptr;
  }
  exit(errorCode);
}

/* Main program function */
int main(int argc, char *argv[])
{
  //get the properties
  hipDeviceProp_t deviceProp;
  CUDA_CHECK(hipGetDeviceProperties(&deviceProp, 0));
  cout << "GPU PROPERTIES\n";
  cout << "******************************************************************\n";
  cout << "Cuda Device prop succeeded" << endl;
  cout << "System minor " << deviceProp.minor << endl;
  cout << "System major " << deviceProp.major << endl;
  cout << "Agent Prop Name " << deviceProp.name << endl;
  cout << "Total Global Memory " << deviceProp.totalGlobalMem << " bytes\n";
  cout << "Shared Memory Per Block " << deviceProp.sharedMemPerBlock << " bytes\n";
  cout << "Registers per block " << deviceProp.regsPerBlock << endl;
  cout << "Warp size " << deviceProp.warpSize << endl;
  cout << "Max Threads Per Block " << deviceProp.maxThreadsPerBlock << endl;
  cout << "Max clock frequency of the multiProcessors " << deviceProp.clockRate << " kHz\n";
  cout << "Size of shared memory region " << deviceProp.totalConstMem << " bytes\n";
  cout << "Number of multi-processors (compute units) " << deviceProp.multiProcessorCount << endl;
  cout << "******************************************************************\n\n";
  //get properties to check on input data possible run scenarios
  const int devMaxThreadsPerBlock = deviceProp.maxThreadsPerBlock;
  const int devMaxConcurrentThreads = deviceProp.multiProcessorCount *
                                      deviceProp.warpSize;

  //get the command line input data and do initial checks
  if(argc != 5)
  {
    cerr << "Not enough input data, need 4\n";
    cerr << "Grid_Rows Grid_Collumns Threads_Per_Block Blocks_Per_Grid\n";
    cerr << "Aborting...\n";
    heatCleanExit(-1);
  }
  const int gridRows = atoi(argv[1]);
  const int gridCols = atoi(argv[2]);
  const int threadsPerBlock = atoi(argv[3]);
  const int blocksPerGrid = atoi(argv[4]);
  const int gridSize = gridRows * gridCols;
  const int totalThreads = threadsPerBlock * blocksPerGrid;
  if(gridRows < 0 || gridCols < 0 || threadsPerBlock < 1 || blocksPerGrid < 1)
  {
    cerr << "Invalid Input Data\n";
    cerr << "Grid Rows = " << gridRows << endl;
    cerr << "Grid Cols = " << gridCols << endl;
    cerr << "Threads Per Block = " << threadsPerBlock << endl;
    cerr << "Blocks Per Grid = " << blocksPerGrid << endl;
    cerr << "Aborting...\n";
    heatCleanExit(-1);
  }
  //do checks based on device(GPU) capabilities
  if(threadsPerBlock > devMaxThreadsPerBlock)
  {
    cerr << "Maximum threads per block exceeded for current device\n";
    cerr << "Aborting...\n";
    heatCleanExit(-2);
  }
  if(totalThreads > devMaxConcurrentThreads)
  {
    cerr << "Maximum concurrent threads exceeded for current device\n";
    cerr << "Aborting...\n";
    heatCleanExit(-2);
  }

  //allocate host(CPU) memory
  heatGrid = (double *) malloc(gridSize * sizeof(double));
  if(heatGrid == nullptr)
  {
    cerr << "Error, not enough memory...\nAborting...\n";
    heatCleanExit(1);
  }

  //initialise with 0.0s the heat grid
  for(int i = 0; i < gridRows; ++i)
    for(int j = 0; j < gridCols; ++j)
      heatGrid[i*gridCols+j] = 0.0;

  //allocate device(GPU) global memory
  CUDA_CHECK(hipMalloc((void **)&devNewHeatGrid, gridSize * sizeof(double)));

  //transfer data from host(CPU) to device(GPU) memory
  CUDA_CHECK(hipMemcpy(devNewHeatGrid, heatGrid, gridSize * sizeof(double),
                      hipMemcpyHostToDevice));

  //initialise the heat grid with actual data
  heatInit(heatGrid, gridRows, gridCols);

  //allocate device(GPU) global memory
  CUDA_CHECK(hipMalloc((void **)&devOldHeatGrid, gridSize * sizeof(double)));

  //transfer data from host(CPU) to device(GPU) memory
  CUDA_CHECK(hipMemcpy(devOldHeatGrid, heatGrid, gridSize * sizeof(double),
                      hipMemcpyHostToDevice));

  //write out the initial grid to the corresponding file
  // if(heatWrite(heatGrid, 0, gridRows, gridCols,
               // threadsPerBlock, blocksPerGrid) == -1)
  // {
    // cerr << "Error, could not create the initial file...\nAborting...\n";
    // heatCleanExit(2);
  // }

  //calculate the kernel dimensions (x,y,z) threads/block and blocks/grid
  dim3 cudaThreads(threadsPerBlock, 1, 1);
  dim3 cudaBlocks(blocksPerGrid, 1 ,1);

  //define the timer structs to be used
  // struct timespec start;
  // struct timespec end;
  // double totalTime = 0.0;

  if(totalThreads == 1)//serial execution
  {
    cout << "Serial execution with 1 cuda thread\n";

    //start the timer
    //clock_gettime(CLOCK_MONOTONIC, &start);
	clock_t begin = clock();

    //solve the problem
    for(int steps = 0; steps < STEPS; ++steps)
    {
      //launch the kernel
      heatUpdateSerial<<<cudaBlocks, cudaThreads>>>(devOldHeatGrid, devNewHeatGrid,
                                                    gridRows, gridCols);

      //wait for device(GPU) to finish it's work
      CUDA_CHECK(hipDeviceSynchronize());

      //old = new
      heatSwap(&devNewHeatGrid, &devOldHeatGrid);
    }

    //stop the timer and print the result
    //clock_gettime(CLOCK_MONOTONIC, &end);
	clock_t end = clock();
	double totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
    //totalTime = ((end.tv_sec - start.tv_sec) * 1000.0) +
    //            ((end.tv_nsec - start.tv_nsec) / 1000000.0); 
    cout << "\nElapsed time was " << totalTime << " ms\n";
  }
  else//parallel execution
  {
    //initial check on number of threads
    if(totalThreads % 2 != 0)
    {
      cout << "Can't parition grid fairly with odd number of threads = "
           << totalThreads
           << "\nAborting...\n";
      heatCleanExit(4);
    }
    cout << "Parallel execution with ";
    cout << "Threads Per Block : " << threadsPerBlock << endl;
    cout << "Blocks Per Grid : " << blocksPerGrid << endl;
    cout << "Total Cuda Threads : " << totalThreads << endl;

    //allocate arrays for neighbour discovery 
    //working border rows
    workRowS = (int *) malloc(totalThreads * sizeof(int));
    if(workRowS == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    workRowE = (int *) malloc(totalThreads * sizeof(int));
    if(workRowE == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    //working border collumns
    workColS = (int *) malloc(totalThreads * sizeof(int));
    if(workColS == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    workColE = (int *) malloc(totalThreads * sizeof(int));
    if(workColE == nullptr)
    {
      cerr << "Error, not enough memory...\nAborting...\n";
      heatCleanExit(5);
    }
    
    int blockRows = 0;//total rows for each block of threads data block
    int blockCols = 0;//total cols for each block of threads data block
    int threadsPerRow = 0, threadsPerCol = 0;//vertical and horizontal distrib

    //classify problem cases based on total threads
    int cut = (int) sqrt(totalThreads);
    double cutF = sqrt(totalThreads);
    int probCase;
    if(totalThreads == 2)//case 1 : handling 2 threads
    {
      blockRows = gridRows;
      blockCols = gridCols / totalThreads;
      threadsPerRow = gridRows / blockRows;
      threadsPerCol = gridCols / blockCols;
      if((threadsPerRow * threadsPerCol) != totalThreads)
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(6);
      }
      probCase = 1;
    }
    else if(cutF > (double) cut)//case 2.1 : handling 6, 8, 10, ... threads
    {
      if(gridSize % totalThreads != 0)//can't cut it without remains
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(7);
      }
      const int localProbSize = gridSize / totalThreads;
      int spread = gridSize;
      //find the best possible partition
      for(int i = gridRows; i > 0; --i)//priority to rows
      {
        for(int j = gridCols; j > 0; --j)
        {
          if((i * j) == localProbSize)
          {
            if(gridRows % i != 0 || gridCols % j != 0)
              continue;
            if(abs(i -j) < spread)
            {
              spread = abs(i - j);
              blockRows = i;
              blockCols = j;
            }
          }
        }
      }
      threadsPerRow = gridRows / blockRows;
      threadsPerCol = gridCols / blockCols;
      if((threadsPerRow * threadsPerCol) != totalThreads)
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(7);
      }
      probCase = 2;
    }
    else//case 2.2 : handling 4, 9, 16, ... threads
    {
      threadsPerRow = cut;
      threadsPerCol = cut;
      if((gridRows % cut != 0) || (gridCols % cut != 0))//can't cut even blocks
      {
        cout << "Grid partitioning results to remains...\nAborting...\n";
        heatCleanExit(8);
      }
      blockRows = gridRows / cut;
      blockCols = gridCols / cut;
      probCase = 2;
    }

    printf("Grid can be partioned without remains...\n"
             "Rows per block : %d, Columns per block : %d\n"
             "Vertical threads : %d, Horizontal threads : %d\n\n",
             blockRows, blockCols, threadsPerRow, threadsPerCol);

    //working and global discovery phase
    //allocate device(GPU) global memory
    CUDA_CHECK(hipMalloc((void **)&devWorkRowS, totalThreads * sizeof(int)));
    CUDA_CHECK(hipMalloc((void **)&devWorkRowE, totalThreads * sizeof(int)));
    CUDA_CHECK(hipMalloc((void **)&devWorkColS, totalThreads * sizeof(int)));
    CUDA_CHECK(hipMalloc((void **)&devWorkColE, totalThreads * sizeof(int)));
    //transfer data from host(CPU) to device(GPU) memory
    CUDA_CHECK(hipMemcpy(devWorkRowS, workRowS, totalThreads * sizeof(int),
                          hipMemcpyHostToDevice));
    CUDA_CHECK(hipMemcpy(devWorkRowE, workRowE, totalThreads * sizeof(int),
                          hipMemcpyHostToDevice));
    CUDA_CHECK(hipMemcpy(devWorkColS, workColS, totalThreads * sizeof(int),
                          hipMemcpyHostToDevice));
    CUDA_CHECK(hipMemcpy(devWorkColE, workColE, totalThreads * sizeof(int),
                          hipMemcpyHostToDevice));

    heatDiscover<<<cudaBlocks, cudaThreads>>>
                (devWorkRowS, devWorkRowE, devWorkColS, devWorkColE,
                 blockRows, blockCols,
                 threadsPerRow, threadsPerCol, probCase,
                 gridRows, gridCols);

    //wait for device(GPU) to finish it's work
    CUDA_CHECK(hipDeviceSynchronize());

    //start the timer
    // clock_gettime(CLOCK_MONOTONIC, &start);
	clock_t begin = clock();

    //launch the kernel
    for(int steps = 0; steps < STEPS; ++steps)
    {
      heatUpdateParallel<<<cudaBlocks, cudaThreads>>>
                        (devOldHeatGrid, devNewHeatGrid,
                         devWorkRowS, devWorkRowE, devWorkColS, devWorkColE,
                         gridCols);

      //wait for device(GPU) to finish it's work
      CUDA_CHECK(hipDeviceSynchronize());

      //old = new
      heatSwap(&devNewHeatGrid, &devOldHeatGrid);
    }
    
    //stop the timer and print the result
	clock_t end = clock();
	double totalTime = (double)(end - begin) / CLOCKS_PER_SEC;
    // clock_gettime(CLOCK_MONOTONIC, &end);
    // totalTime = ((end.tv_sec - start.tv_sec) * 1000.0) +
                // ((end.tv_nsec - start.tv_nsec) / 1000000.0); 
    cout << "\nElapsed time was " << totalTime << " ms\n";
  }

  if(STEPS % 2 == 0)//get the correct version
  {
    CUDA_CHECK(hipMemcpy(heatGrid, devOldHeatGrid, gridSize * sizeof(double),
                        hipMemcpyDeviceToHost));
  }
  else
  {
    CUDA_CHECK(hipMemcpy(heatGrid, devNewHeatGrid, gridSize * sizeof(double),
                        hipMemcpyDeviceToHost));
  }
  
  //write out the final grid to the corresponding file
  // if(heatWrite(heatGrid, 1, gridRows, gridCols,
               // threadsPerBlock, blocksPerGrid) == -1)
  // {
    // cerr << "Error, could not create the initial file...\nAborting...\n";
    // heatCleanExit(3);
  // }

  //clear memory and exit
  heatCleanExit(0);
}
	.text
	.file	"cuda_Heat2D.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii # -- Begin function _Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii
	.type	_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii,@function
_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii: # @_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12heatDiscoverPiS_S_S_iiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii, .Lfunc_end0-_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__heatUpdateSerialPKdPdii # -- Begin function _Z31__device_stub__heatUpdateSerialPKdPdii
	.type	_Z31__device_stub__heatUpdateSerialPKdPdii,@function
_Z31__device_stub__heatUpdateSerialPKdPdii: # @_Z31__device_stub__heatUpdateSerialPKdPdii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16heatUpdateSerialPKdPdii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__heatUpdateSerialPKdPdii, .Lfunc_end1-_Z31__device_stub__heatUpdateSerialPKdPdii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i # -- Begin function _Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.type	_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i,@function
_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i: # @_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i, .Lfunc_end2-_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI3_1:
	.quad	0x0000000000000000              # double 0
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1528, %rsp                     # imm = 0x5F8
	.cfi_def_cfa_offset 1584
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	leaq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.6:
	movl	$_ZSt4cout, %r13d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$67, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$13, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	56(%rsp), %r15
	movl	364(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$13, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	360(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$16, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	callq	strlen
	movl	$_ZSt4cout, %edi
	movq	%r15, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.7, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	288(%r15), %rsi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movl	$.L.str.8, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$24, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	296(%r15), %rsi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movl	$.L.str.8, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.10, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	304(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.11, %esi
	movl	$10, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	308(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.12, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	320(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.13, %esi
	movl	$43, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	348(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.14, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.15, %esi
	movl	$29, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	352(%r15), %rsi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movl	$.L.str.8, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.16, %esi
	movl	$43, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	388(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.17, %esi
	movl	$68, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cmpl	$5, %ebx
	jne	.LBB3_7
# %bb.9:
	movl	364(%rsp), %r12d
	movl	376(%rsp), %r13d
	imull	444(%rsp), %r12d
	movq	8(%r14), %rdi
	callq	atoi
	movl	%eax, %r15d
	movq	16(%r14), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	24(%r14), %rdi
	callq	atoi
	movq	32(%r14), %rdi
	movl	%eax, %r14d
	callq	atoi
	movl	%eax, %ebp
	testl	%r15d, %r15d
	js	.LBB3_13
# %bb.10:
	testl	%ebx, %ebx
	js	.LBB3_13
# %bb.11:
	testl	%r14d, %r14d
	jle	.LBB3_13
# %bb.12:
	testl	%ebp, %ebp
	jle	.LBB3_13
# %bb.14:
	cmpl	%r13d, %r14d
	jle	.LBB3_17
# %bb.15:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.26, %esi
	movl	$54, %edx
	jmp	.LBB3_16
.LBB3_7:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.18, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.19, %esi
	movl	$58, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB3_8
.LBB3_13:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.21, %esi
	movl	$19, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.22, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%r15d, %esi
	callq	_ZNSolsEi
	movl	%r14d, %r15d
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.23, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.24, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%r15d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.25, %esi
	movl	$18, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB3_8:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.20, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$-1, %edi
	callq	_ZL13heatCleanExiti
.LBB3_17:
	movl	%ebp, (%rsp)                    # 4-byte Spill
	imull	%r14d, %ebp
	cmpl	%r12d, %ebp
	jle	.LBB3_19
# %bb.18:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.27, %esi
	movl	$55, %edx
.LBB3_16:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.20, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$-2, %edi
	callq	_ZL13heatCleanExiti
.LBB3_19:
	movl	%r14d, 16(%rsp)                 # 4-byte Spill
	movl	%ebx, %eax
	imull	%r15d, %eax
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	movslq	%eax, %r14
	shlq	$3, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, heatGrid(%rip)
	testq	%rax, %rax
	jne	.LBB3_20
# %bb.92:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.28, %esi
	movl	$40, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$1, %edi
	callq	_ZL13heatCleanExiti
.LBB3_20:                               # %.preheader309
	movl	%ebp, 24(%rsp)                  # 4-byte Spill
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	testl	%r15d, %r15d
	je	.LBB3_25
# %bb.21:                               # %.preheader308.lr.ph
	movq	%rax, %r12
	movl	%ebx, %r13d
	shlq	$3, %r13
	movl	%r15d, %ebp
	xorl	%r14d, %r14d
.LBB3_22:                               # %.preheader308
                                        # =>This Inner Loop Header: Depth=1
	testl	%ebx, %ebx
	je	.LBB3_24
# %bb.23:                               # %.lr.ph
                                        #   in Loop: Header=BB3_22 Depth=1
	movl	%r14d, %eax
	leaq	(%r12,%rax,8), %rdi
	xorl	%esi, %esi
	movq	%r13, %rdx
	callq	memset@PLT
.LBB3_24:                               # %._crit_edge
                                        #   in Loop: Header=BB3_22 Depth=1
	addl	%ebx, %r14d
	decq	%rbp
	jne	.LBB3_22
.LBB3_25:                               # %._crit_edge313
	movl	$devNewHeatGrid, %edi
	movq	40(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_26
# %bb.27:
	movq	devNewHeatGrid(%rip), %rdi
	movq	heatGrid(%rip), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_26
# %bb.28:
	testl	%r15d, %r15d
	je	.LBB3_34
# %bb.29:                               # %.preheader.lr.ph.i
	movq	heatGrid(%rip), %rax
	movl	%r15d, %ecx
	movl	%ebx, %edx
	shlq	$3, %rdx
	leal	-1(%rbx), %esi
	leal	-2(%r15), %edi
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB3_30:                               # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_32 Depth 2
	testl	%ebx, %ebx
	jle	.LBB3_33
# %bb.31:                               # %.lr.ph.i
                                        #   in Loop: Header=BB3_30 Depth=1
	movl	%r9d, %r11d
	leaq	(%rax,%r11,8), %r11
	xorl	%r14d, %r14d
	movl	%esi, %ebp
	xorl	%r12d, %r12d
.LBB3_32:                               #   Parent Loop BB3_30 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ebp, %r13d
	imull	%r14d, %r13d
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r13d, %xmm0
	movsd	%xmm0, (%r11,%r12)
	addq	$8, %r12
	decl	%ebp
	addl	%r8d, %r14d
	cmpq	%r12, %rdx
	jne	.LBB3_32
.LBB3_33:                               # %._crit_edge.i
                                        #   in Loop: Header=BB3_30 Depth=1
	incq	%r10
	addl	%ebx, %r9d
	addl	%edi, %r8d
	addl	$-2, %edi
	cmpq	%rcx, %r10
	jne	.LBB3_30
.LBB3_34:                               # %_ZL8heatInitPdii.exit
	movl	$devOldHeatGrid, %edi
	movq	40(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_26
# %bb.35:
	movq	devOldHeatGrid(%rip), %rdi
	movq	heatGrid(%rip), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_26
# %bb.36:
	movl	16(%rsp), %r14d                 # 4-byte Reload
	movl	%r14d, %r12d
	btsq	$32, %r12
	movl	(%rsp), %r13d                   # 4-byte Reload
	btsq	$32, %r13
	movl	24(%rsp), %ebp                  # 4-byte Reload
	movl	$_ZSt4cout, %edi
	cmpl	$1, %ebp
	jne	.LBB3_42
# %bb.37:
	movl	$.L.str.29, %esi
	movl	$36, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$1000, %r14d                    # imm = 0x3E8
	callq	clock
	movq	%rax, (%rsp)                    # 8-byte Spill
.LBB3_38:                               # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_40
# %bb.39:                               #   in Loop: Header=BB3_38 Depth=1
	movq	devOldHeatGrid(%rip), %rdi
	movq	devNewHeatGrid(%rip), %rsi
	movl	%r15d, %edx
	movl	%ebx, %ecx
	callq	_Z31__device_stub__heatUpdateSerialPKdPdii
.LBB3_40:                               #   in Loop: Header=BB3_38 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.41:                               #   in Loop: Header=BB3_38 Depth=1
	movq	devNewHeatGrid(%rip), %rax
	movq	devOldHeatGrid(%rip), %rcx
	movq	%rcx, devNewHeatGrid(%rip)
	movq	%rax, devOldHeatGrid(%rip)
	decl	%r14d
	jne	.LBB3_38
.LBB3_89:                               # %.loopexit
	callq	clock
	subq	(%rsp), %rax                    # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.30, %esi
	movl	$18, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.31, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	heatGrid(%rip), %rdi
	movq	devOldHeatGrid(%rip), %rsi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_90
# %bb.91:
	xorl	%edi, %edi
	callq	_ZL13heatCleanExiti
.LBB3_26:
	movl	%eax, %r12d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%r12d, %edi
	jmp	.LBB3_2
.LBB3_42:
	testb	$1, %bpl
	jne	.LBB3_93
# %bb.43:
	movl	$.L.str.34, %esi
	movl	$24, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.35, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbp, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbp, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.36, %esi
	movl	$18, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	(%rsp), %esi                    # 4-byte Reload
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbp, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbp, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.37, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	24(%rsp), %esi                  # 4-byte Reload
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbp, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbp, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movslq	24(%rsp), %r14                  # 4-byte Folded Reload
	shlq	$2, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, workRowS(%rip)
	testq	%rax, %rax
	je	.LBB3_94
# %bb.44:
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, workRowE(%rip)
	testq	%rax, %rax
	je	.LBB3_94
# %bb.45:
	movq	%r14, (%rsp)                    # 8-byte Spill
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, workColS(%rip)
	testq	%rax, %rax
	je	.LBB3_94
# %bb.46:
	movq	(%rsp), %rdi                    # 8-byte Reload
	callq	malloc
	movq	%rax, workColE(%rip)
	testq	%rax, %rax
	jne	.LBB3_47
.LBB3_94:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.28, %esi
	movl	$40, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$5, %edi
	callq	_ZL13heatCleanExiti
.LBB3_93:
	movl	$.L.str.32, %esi
	movl	$56, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.33, %esi
	movl	$13, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$4, %edi
	callq	_ZL13heatCleanExiti
.LBB3_90:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	jmp	.LBB3_2
.LBB3_47:
	cvtsi2sdl	24(%rsp), %xmm1         # 4-byte Folded Reload
	sqrtsd	%xmm1, %xmm0
	xorpd	%xmm2, %xmm2
	movsd	%xmm1, 16(%rsp)                 # 8-byte Spill
	ucomisd	%xmm2, %xmm1
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
	jae	.LBB3_49
# %bb.48:                               # %call.sqrt
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	sqrt
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
.LBB3_49:                               # %.split
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	ucomisd	.LCPI3_1(%rip), %xmm0
	jae	.LBB3_51
# %bb.50:                               # %call.sqrt386
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	sqrt
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
.LBB3_51:                               # %.split.split
	cmpl	$2, 24(%rsp)                    # 4-byte Folded Reload
	jne	.LBB3_55
# %bb.52:
	movl	%ebx, %ecx
	shrl	$31, %ecx
	addl	%ebx, %ecx
	sarl	%ecx
	movl	%ebx, %eax
	cltd
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	idivl	%ecx
	cmpl	$2, %eax
	jne	.LBB3_54
# %bb.53:
	movl	$2, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	$1, %eax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movl	$1, %eax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	%r15d, %ebp
.LBB3_72:
	movl	$.L.str.39, %edi
	movl	%ebp, %esi
	movl	12(%rsp), %edx                  # 4-byte Reload
	movq	32(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movq	16(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	xorl	%eax, %eax
	callq	printf
	movl	$devWorkRowS, %edi
	movq	(%rsp), %rsi                    # 8-byte Reload
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.74:
	movl	$devWorkRowE, %edi
	movq	(%rsp), %rsi                    # 8-byte Reload
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.75:
	movl	$devWorkColS, %edi
	movq	(%rsp), %rsi                    # 8-byte Reload
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.76:
	movl	$devWorkColE, %edi
	movq	(%rsp), %rsi                    # 8-byte Reload
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.77:
	movq	devWorkRowS(%rip), %rdi
	movq	workRowS(%rip), %rsi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.78:
	movq	devWorkRowE(%rip), %rdi
	movq	workRowE(%rip), %rsi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.79:
	movq	devWorkColS(%rip), %rdi
	movq	workColS(%rip), %rsi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.80:
	movq	devWorkColE(%rip), %rdi
	movq	workColE(%rip), %rsi
	movq	(%rsp), %rdx                    # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_73
# %bb.81:
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_83
# %bb.82:
	movq	devWorkRowS(%rip), %rdi
	movq	devWorkRowE(%rip), %rsi
	movq	devWorkColS(%rip), %rdx
	movq	devWorkColE(%rip), %rcx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%ebp, %r8d
	movl	20(%rsp), %r9d                  # 4-byte Reload
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB3_83:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.84:
	movl	$1000, %r15d                    # imm = 0x3E8
	callq	clock
	movq	%rax, (%rsp)                    # 8-byte Spill
.LBB3_85:                               # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_87
# %bb.86:                               #   in Loop: Header=BB3_85 Depth=1
	movq	devOldHeatGrid(%rip), %rdi
	movq	devNewHeatGrid(%rip), %rsi
	movq	devWorkRowS(%rip), %rdx
	movq	devWorkRowE(%rip), %rcx
	movq	devWorkColS(%rip), %r8
	movq	devWorkColE(%rip), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB3_87:                               #   in Loop: Header=BB3_85 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.88:                               #   in Loop: Header=BB3_85 Depth=1
	movq	devNewHeatGrid(%rip), %rax
	movq	devOldHeatGrid(%rip), %rcx
	movq	%rcx, devNewHeatGrid(%rip)
	movq	%rax, devOldHeatGrid(%rip)
	decl	%r15d
	jne	.LBB3_85
	jmp	.LBB3_89
.LBB3_1:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
.LBB3_2:
	callq	hipGetErrorString
	testq	%rax, %rax
	jne	.LBB3_4
# %bb.3:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
	jmp	.LBB3_5
.LBB3_4:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB3_5:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-6, %edi
	callq	_ZL13heatCleanExiti
.LBB3_55:
	cvttsd2si	48(%rsp), %eax          # 8-byte Folded Reload
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	movsd	32(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	ucomisd	%xmm0, %xmm1
	jbe	.LBB3_69
# %bb.56:
	movl	12(%rsp), %eax                  # 4-byte Reload
	cltd
	idivl	24(%rsp)                        # 4-byte Folded Reload
	testl	%edx, %edx
	jne	.LBB3_95
# %bb.57:
	xorl	%r14d, %r14d
	movl	$0, %ebp
	testl	%r15d, %r15d
	movl	12(%rsp), %r11d                 # 4-byte Reload
	je	.LBB3_61
# %bb.58:                               # %.preheader.lr.ph
	movl	%eax, %ecx
	movl	%ebx, %eax
	imull	%r15d, %eax
	movl	%r15d, %esi
	subl	%ebx, %esi
	subl	%eax, %ecx
	xorl	%ebp, %ebp
	xorl	%r14d, %r14d
	movl	%r15d, %edi
.LBB3_59:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_63 Depth 2
	movl	%ecx, %r8d
	movl	%esi, %r9d
	movl	%ebx, %r10d
	testl	%ebx, %ebx
	jle	.LBB3_60
.LBB3_63:                               # %.lr.ph318
                                        #   Parent Loop BB3_59 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	testl	%r8d, %r8d
	jne	.LBB3_68
# %bb.64:                               #   in Loop: Header=BB3_63 Depth=2
	movl	%r15d, %eax
	cltd
	idivl	%edi
	testl	%edx, %edx
	jne	.LBB3_68
# %bb.65:                               #   in Loop: Header=BB3_63 Depth=2
	movl	%ebx, %eax
	cltd
	idivl	%r10d
	testl	%edx, %edx
	jne	.LBB3_68
# %bb.66:                               #   in Loop: Header=BB3_63 Depth=2
	movl	%r9d, %eax
	negl	%eax
	cmovsl	%r9d, %eax
	cmpl	%r11d, %eax
	jge	.LBB3_68
# %bb.67:                               #   in Loop: Header=BB3_63 Depth=2
	movl	%eax, %r11d
	movl	%r10d, %r14d
	movl	%edi, %ebp
.LBB3_68:                               #   in Loop: Header=BB3_63 Depth=2
	leal	-1(%r10), %eax
	incl	%r9d
	addl	%edi, %r8d
	cmpl	$1, %r10d
	movl	%eax, %r10d
	jg	.LBB3_63
.LBB3_60:                               # %._crit_edge319
                                        #   in Loop: Header=BB3_59 Depth=1
	leal	-1(%rdi), %eax
	decl	%esi
	addl	%ebx, %ecx
	cmpl	$1, %edi
	movl	%eax, %edi
	jg	.LBB3_59
.LBB3_61:                               # %._crit_edge326
	movl	%r15d, %eax
	cltd
	idivl	%ebp
	movl	%eax, %esi
	movl	%ebx, %eax
	cltd
	movl	%r14d, 12(%rsp)                 # 4-byte Spill
	idivl	%r14d
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, %rcx
	movq	%rax, 16(%rsp)                  # 8-byte Spill
                                        # kill: def $eax killed $eax killed $rax
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	imull	%esi, %eax
	cmpl	24(%rsp), %eax                  # 4-byte Folded Reload
	jne	.LBB3_95
# %bb.62:
	movl	$2, %eax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	jmp	.LBB3_72
.LBB3_73:
	movl	%eax, %r14d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%r14d, %edi
	jmp	.LBB3_2
.LBB3_54:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.38, %esi
	movl	$52, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$6, %edi
	callq	_ZL13heatCleanExiti
.LBB3_69:
	movl	%r15d, %eax
	cltd
	idivl	16(%rsp)                        # 4-byte Folded Reload
	testl	%edx, %edx
	jne	.LBB3_96
# %bb.70:
	movl	%eax, %ebp
	movl	%ebx, %eax
	cltd
	idivl	16(%rsp)                        # 4-byte Folded Reload
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	testl	%edx, %edx
	jne	.LBB3_96
# %bb.71:
	movl	$2, %eax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	16(%rsp), %rax                  # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax def $rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	jmp	.LBB3_72
.LBB3_95:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.38, %esi
	movl	$52, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$7, %edi
	callq	_ZL13heatCleanExiti
.LBB3_96:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.38, %esi
	movl	$52, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$8, %edi
	callq	_ZL13heatCleanExiti
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.type	_ZL13heatCleanExiti,@function   # -- Begin function _ZL13heatCleanExiti
_ZL13heatCleanExiti:                    # @_ZL13heatCleanExiti
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebx
	movq	heatGrid(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	callq	free
	movq	$0, heatGrid(%rip)
.LBB4_2:
	movq	devOldHeatGrid(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_9
# %bb.3:
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.8:
	movq	$0, devOldHeatGrid(%rip)
.LBB4_9:
	movq	devNewHeatGrid(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_12
# %bb.10:
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.11:
	movq	$0, devNewHeatGrid(%rip)
.LBB4_12:
	movq	workRowS(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_14
# %bb.13:
	callq	free
	movq	$0, workRowS(%rip)
.LBB4_14:
	movq	devWorkRowS(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_17
# %bb.15:
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.16:
	movq	$0, devWorkRowS(%rip)
.LBB4_17:
	movq	workRowE(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_19
# %bb.18:
	callq	free
	movq	$0, workRowE(%rip)
.LBB4_19:
	movq	devWorkRowE(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_22
# %bb.20:
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.21:
	movq	$0, devWorkRowE(%rip)
.LBB4_22:
	movq	workColS(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_24
# %bb.23:
	callq	free
	movq	$0, workColS(%rip)
.LBB4_24:
	movq	devWorkColS(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_27
# %bb.25:
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.26:
	movq	$0, devWorkColS(%rip)
.LBB4_27:
	movq	workColE(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_29
# %bb.28:
	callq	free
	movq	$0, workColE(%rip)
.LBB4_29:
	movq	devWorkColE(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_32
# %bb.30:
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.31:
	movq	$0, devWorkColE(%rip)
.LBB4_32:
	movl	%ebx, %edi
	callq	exit
.LBB4_4:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	jne	.LBB4_6
# %bb.5:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
	jmp	.LBB4_7
.LBB4_6:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB4_7:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-6, %edi
	callq	_ZL13heatCleanExiti
.Lfunc_end4:
	.size	_ZL13heatCleanExiti, .Lfunc_end4-_ZL13heatCleanExiti
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12heatDiscoverPiS_S_S_iiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16heatUpdateSerialPKdPdii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12heatDiscoverPiS_S_S_iiiiiii,@object # @_Z12heatDiscoverPiS_S_S_iiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z12heatDiscoverPiS_S_S_iiiiiii
	.p2align	3, 0x0
_Z12heatDiscoverPiS_S_S_iiiiiii:
	.quad	_Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii
	.size	_Z12heatDiscoverPiS_S_S_iiiiiii, 8

	.type	_Z16heatUpdateSerialPKdPdii,@object # @_Z16heatUpdateSerialPKdPdii
	.globl	_Z16heatUpdateSerialPKdPdii
	.p2align	3, 0x0
_Z16heatUpdateSerialPKdPdii:
	.quad	_Z31__device_stub__heatUpdateSerialPKdPdii
	.size	_Z16heatUpdateSerialPKdPdii, 8

	.type	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i,@object # @_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.globl	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.p2align	3, 0x0
_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i:
	.quad	_Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.size	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i, 8

	.type	heatGrid,@object                # @heatGrid
	.bss
	.globl	heatGrid
	.p2align	3, 0x0
heatGrid:
	.quad	0
	.size	heatGrid, 8

	.type	devNewHeatGrid,@object          # @devNewHeatGrid
	.globl	devNewHeatGrid
	.p2align	3, 0x0
devNewHeatGrid:
	.quad	0
	.size	devNewHeatGrid, 8

	.type	devOldHeatGrid,@object          # @devOldHeatGrid
	.globl	devOldHeatGrid
	.p2align	3, 0x0
devOldHeatGrid:
	.quad	0
	.size	devOldHeatGrid, 8

	.type	workRowS,@object                # @workRowS
	.globl	workRowS
	.p2align	3, 0x0
workRowS:
	.quad	0
	.size	workRowS, 8

	.type	workRowE,@object                # @workRowE
	.globl	workRowE
	.p2align	3, 0x0
workRowE:
	.quad	0
	.size	workRowE, 8

	.type	workColS,@object                # @workColS
	.globl	workColS
	.p2align	3, 0x0
workColS:
	.quad	0
	.size	workColS, 8

	.type	workColE,@object                # @workColE
	.globl	workColE
	.p2align	3, 0x0
workColE:
	.quad	0
	.size	workColE, 8

	.type	devWorkRowS,@object             # @devWorkRowS
	.globl	devWorkRowS
	.p2align	3, 0x0
devWorkRowS:
	.quad	0
	.size	devWorkRowS, 8

	.type	devWorkRowE,@object             # @devWorkRowE
	.globl	devWorkRowE
	.p2align	3, 0x0
devWorkRowE:
	.quad	0
	.size	devWorkRowE, 8

	.type	devWorkColS,@object             # @devWorkColS
	.globl	devWorkColS
	.p2align	3, 0x0
devWorkColS:
	.quad	0
	.size	devWorkColS, 8

	.type	devWorkColE,@object             # @devWorkColE
	.globl	devWorkColE
	.p2align	3, 0x0
devWorkColE:
	.quad	0
	.size	devWorkColE, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error : Cuda reports "
	.size	.L.str, 22

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"GPU PROPERTIES\n"
	.size	.L.str.1, 16

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"******************************************************************\n"
	.size	.L.str.2, 68

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Cuda Device prop succeeded"
	.size	.L.str.3, 27

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"System minor "
	.size	.L.str.4, 14

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"System major "
	.size	.L.str.5, 14

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Agent Prop Name "
	.size	.L.str.6, 17

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Total Global Memory "
	.size	.L.str.7, 21

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	" bytes\n"
	.size	.L.str.8, 8

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Shared Memory Per Block "
	.size	.L.str.9, 25

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Registers per block "
	.size	.L.str.10, 21

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Warp size "
	.size	.L.str.11, 11

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Max Threads Per Block "
	.size	.L.str.12, 23

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Max clock frequency of the multiProcessors "
	.size	.L.str.13, 44

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	" kHz\n"
	.size	.L.str.14, 6

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"Size of shared memory region "
	.size	.L.str.15, 30

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Number of multi-processors (compute units) "
	.size	.L.str.16, 44

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"******************************************************************\n\n"
	.size	.L.str.17, 69

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"Not enough input data, need 4\n"
	.size	.L.str.18, 31

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"Grid_Rows Grid_Collumns Threads_Per_Block Blocks_Per_Grid\n"
	.size	.L.str.19, 59

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"Aborting...\n"
	.size	.L.str.20, 13

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"Invalid Input Data\n"
	.size	.L.str.21, 20

	.type	.L.str.22,@object               # @.str.22
.L.str.22:
	.asciz	"Grid Rows = "
	.size	.L.str.22, 13

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"Grid Cols = "
	.size	.L.str.23, 13

	.type	.L.str.24,@object               # @.str.24
.L.str.24:
	.asciz	"Threads Per Block = "
	.size	.L.str.24, 21

	.type	.L.str.25,@object               # @.str.25
.L.str.25:
	.asciz	"Blocks Per Grid = "
	.size	.L.str.25, 19

	.type	.L.str.26,@object               # @.str.26
.L.str.26:
	.asciz	"Maximum threads per block exceeded for current device\n"
	.size	.L.str.26, 55

	.type	.L.str.27,@object               # @.str.27
.L.str.27:
	.asciz	"Maximum concurrent threads exceeded for current device\n"
	.size	.L.str.27, 56

	.type	.L.str.28,@object               # @.str.28
.L.str.28:
	.asciz	"Error, not enough memory...\nAborting...\n"
	.size	.L.str.28, 41

	.type	.L.str.29,@object               # @.str.29
.L.str.29:
	.asciz	"Serial execution with 1 cuda thread\n"
	.size	.L.str.29, 37

	.type	.L.str.30,@object               # @.str.30
.L.str.30:
	.asciz	"\nElapsed time was "
	.size	.L.str.30, 19

	.type	.L.str.31,@object               # @.str.31
.L.str.31:
	.asciz	" ms\n"
	.size	.L.str.31, 5

	.type	.L.str.32,@object               # @.str.32
.L.str.32:
	.asciz	"Can't parition grid fairly with odd number of threads = "
	.size	.L.str.32, 57

	.type	.L.str.33,@object               # @.str.33
.L.str.33:
	.asciz	"\nAborting...\n"
	.size	.L.str.33, 14

	.type	.L.str.34,@object               # @.str.34
.L.str.34:
	.asciz	"Parallel execution with "
	.size	.L.str.34, 25

	.type	.L.str.35,@object               # @.str.35
.L.str.35:
	.asciz	"Threads Per Block : "
	.size	.L.str.35, 21

	.type	.L.str.36,@object               # @.str.36
.L.str.36:
	.asciz	"Blocks Per Grid : "
	.size	.L.str.36, 19

	.type	.L.str.37,@object               # @.str.37
.L.str.37:
	.asciz	"Total Cuda Threads : "
	.size	.L.str.37, 22

	.type	.L.str.38,@object               # @.str.38
.L.str.38:
	.asciz	"Grid partitioning results to remains...\nAborting...\n"
	.size	.L.str.38, 53

	.type	.L.str.39,@object               # @.str.39
.L.str.39:
	.asciz	"Grid can be partioned without remains...\nRows per block : %d, Columns per block : %d\nVertical threads : %d, Horizontal threads : %d\n\n"
	.size	.L.str.39, 134

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12heatDiscoverPiS_S_S_iiiiiii"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16heatUpdateSerialPKdPdii"
	.size	.L__unnamed_2, 28

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i"
	.size	.L__unnamed_3, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__heatDiscoverPiS_S_S_iiiiiii
	.addrsig_sym _Z31__device_stub__heatUpdateSerialPKdPdii
	.addrsig_sym _Z33__device_stub__heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12heatDiscoverPiS_S_S_iiiiiii
	.addrsig_sym _Z16heatUpdateSerialPKdPdii
	.addrsig_sym _Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.addrsig_sym devNewHeatGrid
	.addrsig_sym devOldHeatGrid
	.addrsig_sym devWorkRowS
	.addrsig_sym devWorkRowE
	.addrsig_sym devWorkColS
	.addrsig_sym devWorkColE
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12heatDiscoverPiS_S_S_iiiiiii ; -- Begin function _Z12heatDiscoverPiS_S_S_iiiiiii
	.globl	_Z12heatDiscoverPiS_S_S_iiiiiii
	.p2align	8
	.type	_Z12heatDiscoverPiS_S_S_iiiiiii,@function
_Z12heatDiscoverPiS_S_S_iiiiiii:        ; @_Z12heatDiscoverPiS_S_S_iiiiiii
; %bb.0:
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b256 s[16:23], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_cmp_lt_i32 s20, 2
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_40
; %bb.1:                                ; %LeafBlock225
	s_cmp_eq_u32 s20, 2
	s_cbranch_scc0 .LBB0_39
; %bb.2:
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_36
; %bb.3:
	s_add_i32 s0, s19, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_33
; %bb.4:
	s_mul_i32 s14, s19, s18
	s_mov_b32 s3, exec_lo
	s_sub_i32 s0, s14, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_ne_u32_e64 s0, v1
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_30
; %bb.5:
	s_add_i32 s14, s14, -1
	s_mov_b32 s12, exec_lo
	v_cmpx_ne_u32_e64 s14, v1
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_27
; %bb.6:
	s_mov_b32 s13, exec_lo
	v_cmpx_le_i32_e64 s19, v1
	s_xor_b32 s13, exec_lo, s13
	s_cbranch_execz .LBB0_24
; %bb.7:
	v_cmp_ge_i32_e32 vcc_lo, s0, v1
	v_cmp_le_i32_e64 s0, s14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s14, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB0_21
; %bb.8:
	s_ashr_i32 s18, s19, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s0, s19, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s23, s0, s18
	v_add_nc_u32_e32 v4, v1, v2
	v_cvt_f32_u32_e32 v0, s23
	s_sub_i32 s0, 0, s23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v2
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s0, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v3
	v_mul_lo_u32 v5, v0, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v5
	v_subrev_nc_u32_e32 v6, s23, v4
	v_cmp_le_u32_e32 vcc_lo, s23, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_xor_b32_e32 v6, s18, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s23, v4
	v_add_nc_u32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_xor_b32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v6
	v_mul_lo_u32 v0, v4, s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v1, v0
	v_cmpx_ne_u32_e32 0, v0
	s_xor_b32 s15, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.9:
	v_add_nc_u32_e32 v4, 1, v1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v6, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v6, v5
	v_mul_hi_u32 v7, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v7, s23
	v_sub_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s23, v6
	v_cmp_le_u32_e32 vcc_lo, s23, v6
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s23, v6
	v_cmp_le_u32_e32 vcc_lo, s23, v6
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v6, v5
	v_sub_nc_u32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v5
	s_xor_b32 s24, exec_lo, s0
	s_cbranch_execz .LBB0_15
; %bb.10:
	s_lshl_b32 s25, s19, 1
	v_cmp_ge_i32_e32 vcc_lo, s19, v1
	s_add_i32 s0, s25, -1
	v_mov_b32_e32 v3, 1
	v_cmp_le_i32_e64 s0, s0, v1
	s_mov_b32 s27, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s26, s0
	s_cbranch_execz .LBB0_14
; %bb.11:                               ; %.lr.ph.preheader
	s_mul_i32 s29, s19, 3
	s_mov_b32 s28, 0
	s_add_i32 s29, s29, -1
	s_mov_b32 s30, 0
.LBB0_12:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s0, s25, s30
	s_add_i32 s31, s29, s30
	v_cmp_lt_i32_e32 vcc_lo, s0, v1
	v_cmp_gt_i32_e64 s0, s31, v1
	s_add_i32 s27, s27, 1
	s_add_i32 s30, s30, s19
	v_mov_b32_e32 v3, s27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s28, s0, s28
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_12
; %bb.13:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s28
.LBB0_14:                               ; %Flow227
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s26
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_mul_lo_u32 v10, v3, s16
	v_mul_lo_u32 v0, v0, s17
	v_add_co_u32 v2, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v5, vcc_lo
	v_add3_u32 v11, s16, -1, v10
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add3_u32 v12, s17, -1, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_store_b32 v[2:3], v10, off
	global_store_b32 v[6:7], v11, off
	global_store_b32 v[8:9], v0, off
	global_store_b32 v[4:5], v12, off
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
.LBB0_15:                               ; %Flow228
	s_and_not1_saveexec_b32 s0, s24
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_subrev_nc_u32_e32 v0, s19, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v0
	v_add_nc_u32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v0, v0, v4
	v_xor_b32_e32 v4, s18, v4
	s_sub_i32 s18, s22, s17
	v_mov_b32_e32 v10, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_mul_lo_u32 v5, v3, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	v_subrev_nc_u32_e32 v6, s23, v0
	v_cmp_le_u32_e32 vcc_lo, s23, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v0, v6 :: v_dual_add_nc_u32 v5, 1, v3
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s23, v0
	v_add_nc_u32_e32 v5, 1, v3
	s_add_i32 s23, s22, -2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v11, s23 :: v_dual_cndmask_b32 v0, v3, v5
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v4
	v_sub_nc_u32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v0, v0, s16
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add3_u32 v12, s16, -1, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[8:9], v10, off
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[6:7], v12, off
	global_store_b32 v[2:3], v11, off
.LBB0_17:                               ; %Flow229
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr4
.LBB0_18:                               ; %Flow230
	s_and_not1_saveexec_b32 s0, s15
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_mul_lo_u32 v0, v4, s16
	s_add_i32 s15, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v11, 1 :: v_dual_mov_b32 v12, s15
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	v_add3_u32 v10, s16, -1, v0
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[6:7], v10, off
	global_store_b32 v[8:9], v11, off
	global_store_b32 v[2:3], v12, off
.LBB0_20:                               ; %Flow231
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_21:                               ; %Flow232
	s_and_not1_saveexec_b32 s0, s14
	s_cbranch_execz .LBB0_23
; %bb.22:
	s_ashr_i32 s14, s19, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s15, s19, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s14, s15, s14
	v_add_nc_u32_e32 v4, v1, v2
	v_cvt_f32_u32_e32 v0, s14
	s_sub_i32 s15, 0, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v2
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s15, v0
	s_add_i32 s15, s21, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v12, s15
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v3
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s14
	v_sub_nc_u32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s14, v0
	v_cmp_le_u32_e32 vcc_lo, s14, v0
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_subrev_nc_u32_e32 v3, s14, v0
	v_cmp_le_u32_e32 vcc_lo, s14, v0
	s_sub_i32 s14, s21, s16
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v11, s14 :: v_dual_cndmask_b32 v0, v0, v3
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v2
	v_add_co_u32 v5, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_sub_nc_u32_e32 v0, v0, v2
	v_add_co_u32 v7, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v0, v0, s17
	v_add_co_u32 v9, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v4, vcc_lo
	v_add3_u32 v13, s17, -1, v0
	global_store_b32 v[5:6], v11, off
	global_store_b32 v[7:8], v12, off
	global_store_b32 v[9:10], v0, off
	global_store_b32 v[2:3], v13, off
.LBB0_23:                               ; %Flow233
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_24:                               ; %Flow234
	s_and_not1_saveexec_b32 s0, s13
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_lo_u32 v10, v1, s17
	s_add_i32 s13, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v11, s13
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v12, s17, -1, v10
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[6:7], v11, off
	global_store_b32 v[8:9], v10, off
	global_store_b32 v[2:3], v12, off
.LBB0_26:                               ; %Flow235
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_27:                               ; %Flow236
	s_and_not1_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_29
; %bb.28:
	v_ashrrev_i32_e32 v2, 31, v1
	s_sub_i32 s12, s21, s16
	s_add_i32 s13, s21, -2
	v_mov_b32_e32 v0, s12
	s_sub_i32 s12, s22, s17
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v10, s13
	s_add_i32 s12, s22, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v12, s12
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[6:7], v10, off
	global_store_b32 v[8:9], v11, off
	global_store_b32 v[2:3], v12, off
.LBB0_29:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_30:                               ; %Flow238
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_32
; %bb.31:
	v_ashrrev_i32_e32 v2, 31, v1
	s_sub_i32 s3, s21, s16
	s_add_i32 s12, s21, -2
	v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v11, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_mov_b32_e32 v10, s12
	s_add_i32 s3, s17, -1
	v_mov_b32_e32 v12, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[6:7], v10, off
	global_store_b32 v[8:9], v11, off
	global_store_b32 v[2:3], v12, off
.LBB0_32:                               ; %Flow239
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_33:                               ; %Flow240
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_35
; %bb.34:
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s2, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v10, s2
	s_sub_i32 s2, s22, s17
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v11, s2
	s_add_i32 s2, s22, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v12, s2
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[6:7], v10, off
	global_store_b32 v[8:9], v11, off
	global_store_b32 v[2:3], v12, off
.LBB0_35:                               ; %Flow241
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_36:                               ; %Flow242
	s_and_not1_saveexec_b32 s0, s1
; %bb.37:
	s_add_i32 s1, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s1
	v_mov_b32_e32 v2, 1
	s_add_i32 s1, s17, -1
	v_mov_b32_e32 v4, s1
	s_clause 0x3
	global_store_b32 v0, v2, s[4:5]
	global_store_b32 v0, v3, s[6:7]
	global_store_b32 v0, v2, s[8:9]
	global_store_b32 v0, v4, s[10:11]
; %bb.38:                               ; %Flow243
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_39:                               ; %Flow244
	s_mov_b32 s0, 0
.LBB0_40:                               ; %Flow248
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_46
; %bb.41:                               ; %LeafBlock
	s_cmp_lg_u32 s20, 1
	s_cbranch_scc1 .LBB0_46
; %bb.42:
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_44
; %bb.43:
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s1, s16, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v8, 1 :: v_dual_mov_b32 v9, s1
	s_add_i32 s1, s22, -2
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_dual_mov_b32 v10, s17 :: v_dual_mov_b32 v11, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[2:3], v8, off
	global_store_b32 v[4:5], v9, off
	global_store_b32 v[6:7], v10, off
	global_store_b32 v[0:1], v11, off
.LBB0_44:                               ; %Flow245
	s_and_not1_saveexec_b32 s0, s0
; %bb.45:
	s_add_i32 s0, s16, -2
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
	v_mov_b32_e32 v2, s0
	s_add_i32 s0, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s0
	s_clause 0x3
	global_store_b32 v0, v1, s[4:5]
	global_store_b32 v0, v2, s[6:7]
	global_store_b32 v0, v1, s[8:9]
	global_store_b32 v0, v3, s[10:11]
.LBB0_46:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12heatDiscoverPiS_S_S_iiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12heatDiscoverPiS_S_S_iiiiiii, .Lfunc_end0-_Z12heatDiscoverPiS_S_S_iiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2384
; NumSgprs: 34
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16heatUpdateSerialPKdPdii ; -- Begin function _Z16heatUpdateSerialPKdPdii
	.globl	_Z16heatUpdateSerialPKdPdii
	.p2align	8
	.type	_Z16heatUpdateSerialPKdPdii,@function
_Z16heatUpdateSerialPKdPdii:            ; @_Z16heatUpdateSerialPKdPdii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 3
	s_cbranch_scc1 .LBB1_8
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_i32 s1, s2, -1
	s_cmp_lt_i32 s3, 3
	v_mov_b32_e32 v0, 0
	s_cselect_b32 s0, -1, 0
	s_add_i32 s2, s3, -2
	v_cndmask_b32_e64 v1, 0, 1, s0
	s_lshl_b32 s20, s3, 1
	s_mov_b32 s8, 0x9999999a
	s_mov_b32 s10, 1
	s_mov_b32 s9, 0x3fb99999
	v_cmp_ne_u32_e64 s0, 1, v1
	s_mov_b32 s11, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s21, s4, 8
	s_addc_u32 s22, s5, 0
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	s_and_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr23
	s_cbranch_vccnz .LBB1_4
; %bb.3:                                ; %.preheader.._crit_edge_crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s23, s10, 1
	s_mov_b32 s12, 0
.LBB1_4:                                ; %Flow62
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_7
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mul_i32 s16, s10, s3
	s_add_i32 s23, s10, 1
	s_add_i32 s14, s16, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s12, s14, s20
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s12, 31
	s_lshl_b64 s[12:13], s[12:13], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s12, s4, s12
	s_addc_u32 s13, s5, s13
	s_add_i32 s10, s14, 1
	s_lshl_b64 s[14:15], s[10:11], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s14, s4, s14
	s_addc_u32 s15, s5, s15
	s_add_i32 s10, s16, 1
	s_lshl_b64 s[18:19], s[10:11], 3
	s_mov_b32 s10, s2
	s_add_u32 s16, s6, s18
	s_addc_u32 s17, s7, s19
	s_add_u32 s18, s21, s18
	s_addc_u32 s19, s22, s19
.LBB1_6:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b64 s[24:25], s[14:15], 0x0
	s_load_b64 s[26:27], s[12:13], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], s[24:25], s[26:27]
	s_add_u32 s24, s18, -16
	s_addc_u32 s25, s19, -1
	s_clause 0x1
	s_load_b128 s[24:27], s[24:25], 0x0
	s_load_b64 s[28:29], s[18:19], 0x0
	s_add_i32 s10, s10, -1
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[3:4], s[28:29], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[1:2], s[26:27], -2.0, v[1:2]
	v_fma_f64 v[3:4], s[26:27], -2.0, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[1:2], s[8:9], s[26:27]
	v_fma_f64 v[1:2], v[3:4], s[8:9], v[1:2]
	global_store_b64 v0, v[1:2], s[16:17]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc0 .LBB1_6
.LBB1_7:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s10, s23
	s_cmp_eq_u32 s23, s1
	s_cbranch_scc0 .LBB1_2
.LBB1_8:                                ; %._crit_edge42
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16heatUpdateSerialPKdPdii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16heatUpdateSerialPKdPdii, .Lfunc_end1-_Z16heatUpdateSerialPKdPdii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 416
; NumSgprs: 32
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i ; -- Begin function _Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.globl	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
	.p2align	8
	.type	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i,@function
_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i: ; @_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v9, v[2:3], off
	global_load_b32 v8, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_le_i32_e64 v9, v8
	s_cbranch_execz .LBB2_7
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b128 s[4:7], s[0:1], 0x20
	s_mov_b32 s2, 0x9999999a
	s_mov_b32 s3, 0x3fb99999
	s_mov_b32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v10, v[2:3], off
	global_load_b32 v11, v[0:1], off
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s8, 1
	s_add_u32 s10, s4, 8
	s_addc_u32 s11, s5, 0
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v12, -1, v10
	s_waitcnt vmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, v10, v11
.LBB2_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v13, 1, v9
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s13, exec_lo, s0
	s_cbranch_execz .LBB2_6
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_mul_lo_u32 v0, v9, s8
	v_add_nc_u32_e32 v13, 1, v9
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, s8, v0
	v_add_nc_u32_e32 v0, v10, v0
	v_subrev_nc_u32_e32 v3, s9, v1
	v_add_nc_u32_e32 v2, v10, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v4, v10, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[6:7], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[14:15], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, s6, v6
	v_add_co_ci_u32_e64 v1, s0, s7, v7, s0
	v_add_co_u32 v2, s0, s10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v3, s0, s11, v7, s0
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_add_co_u32 v4, s0, s4, v14
	v_mov_b32_e32 v14, v12
	v_add_co_ci_u32_e64 v5, s0, s5, v15, s0
	v_add_co_u32 v6, s0, s4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[19:20], v[4:5], off
	global_load_b64 v[21:22], v[6:7], off
	s_clause 0x1
	global_load_b64 v[23:24], v[2:3], off
	global_load_b128 v[15:18], v[2:3], off offset:-16
	v_add_co_u32 v6, s0, v6, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
	v_add_co_u32 v4, s0, v4, 8
	v_add_nc_u32_e32 v14, 1, v14
	v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
	v_add_co_u32 v2, s0, v2, 8
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, v14, v11
	s_or_b32 s14, s0, s14
	s_waitcnt vmcnt(2)
	v_add_f64 v[19:20], v[19:20], v[21:22]
	s_waitcnt vmcnt(0)
	v_add_f64 v[15:16], v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[17:18], -2.0, v[19:20]
	v_fma_f64 v[15:16], v[17:18], -2.0, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[19:20], s[2:3], v[17:18]
	v_fma_f64 v[15:16], v[15:16], s[2:3], v[17:18]
	global_store_b64 v[0:1], v[15:16], off
	v_add_co_u32 v0, s1, v0, 8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s1, 0, v1, s1
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB2_4
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB2_6:                                ; %Flow74
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_and_not1_saveexec_b32 s0, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_ge_i32_e64 s0, v9, v8
	v_mov_b32_e32 v9, v13
	s_or_b32 s12, s0, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB2_2
.LBB2_7:                                ; %._crit_edge59
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i, .Lfunc_end2-_Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 700
; NumSgprs: 18
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  write_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12heatDiscoverPiS_S_S_iiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z12heatDiscoverPiS_S_S_iiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16heatUpdateSerialPKdPdii
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z16heatUpdateSerialPKdPdii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18heatUpdateParallelPKdPdPKiS3_S3_S3_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
