__global__ void ftcsKernel(float *Cxn, float *Cyn, float *Cxo, float *Cyo, float *diffu,float *diffd,float *diffl, float *diffr, float *T2val, float Adx, int dimX)
{
	int x = threadIdx.x + blockDim.x*blockIdx.x;// place in x dim
	int y = blockIdx.y; 						// place in y dim
	int ind = x+y*dimX;							// current index in linear space
	int yp1 = y+1;
	int ym1 = y-1;
	int xp1 = x+1;
	int xm1 = x-1;
	
	// periodic bc
	if (y==0) ym1 = gridDim.y-1;
	if (y==gridDim.y-1) yp1 = 0;
	if (x==0) xm1 = dimX-1;
	if (x==dimX-1) xp1 = 0;

	if (x >= 0 && x <= (dimX-1) && y >= 0 && y <= (gridDim.y-1) )
	{
		Cxn[ind] = Cxo[ind] - T2val[ind]*Cxo[ind]
			+ diffu[ind]*(cos(Adx)*Cxo[yp1*dimX+x] + sin(Adx)*Cyo[yp1*dimX+x] - Cxo[ind])
			+ diffd[ind]*(cos(Adx)*Cxo[ym1*dimX+x] - sin(Adx)*Cyo[ym1*dimX+x] - Cxo[ind])
			+ diffl[ind]*(Cxo[y*dimX+xp1] - Cxo[ind])
			+ diffr[ind]*(Cxo[y*dimX+xm1] - Cxo[ind]);
			
		Cyn[ind] = Cyo[ind] - T2val[ind]*Cyo[ind]
			+ diffu[ind]*(cos(Adx)*Cyo[yp1*dimX+x] - sin(Adx)*Cxo[yp1*dimX+x] - Cyo[ind])
			+ diffd[ind]*(cos(Adx)*Cyo[ym1*dimX+x] + sin(Adx)*Cxo[ym1*dimX+x] - Cyo[ind])
			+ diffl[ind]*(Cyo[y*dimX+xp1] - Cyo[ind])
			+ diffr[ind]*(Cyo[y*dimX+xm1] - Cyo[ind]);
	}
}

	.file	"tmpxft_00258117_00000000-6_dwmr2dp.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z10ftcsKernelPfS_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_fi
	.type	_Z48__device_stub__Z10ftcsKernelPfS_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_fi, @function
_Z48__device_stub__Z10ftcsKernelPfS_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_fi:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z10ftcsKernelPfS_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_fi, .-_Z48__device_stub__Z10ftcsKernelPfS_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_fi
	.globl	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.type	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi, @function
_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z10ftcsKernelPfS_S_S_S_S_S_S_S_fiPfS_S_S_S_S_S_S_S_fi
	.cfi_endproc
.LFE2033:
	.size	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi, .-_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void ftcsKernel(float *Cxn, float *Cyn, float *Cxo, float *Cyo, float *diffu,float *diffd,float *diffl, float *diffr, float *T2val, float Adx, int dimX)
{
	int x = threadIdx.x + blockDim.x*blockIdx.x;// place in x dim
	int y = blockIdx.y; 						// place in y dim
	int ind = x+y*dimX;							// current index in linear space
	int yp1 = y+1;
	int ym1 = y-1;
	int xp1 = x+1;
	int xm1 = x-1;
	
	// periodic bc
	if (y==0) ym1 = gridDim.y-1;
	if (y==gridDim.y-1) yp1 = 0;
	if (x==0) xm1 = dimX-1;
	if (x==dimX-1) xp1 = 0;

	if (x >= 0 && x <= (dimX-1) && y >= 0 && y <= (gridDim.y-1) )
	{
		Cxn[ind] = Cxo[ind] - T2val[ind]*Cxo[ind]
			+ diffu[ind]*(cos(Adx)*Cxo[yp1*dimX+x] + sin(Adx)*Cyo[yp1*dimX+x] - Cxo[ind])
			+ diffd[ind]*(cos(Adx)*Cxo[ym1*dimX+x] - sin(Adx)*Cyo[ym1*dimX+x] - Cxo[ind])
			+ diffl[ind]*(Cxo[y*dimX+xp1] - Cxo[ind])
			+ diffr[ind]*(Cxo[y*dimX+xm1] - Cxo[ind]);
			
		Cyn[ind] = Cyo[ind] - T2val[ind]*Cyo[ind]
			+ diffu[ind]*(cos(Adx)*Cyo[yp1*dimX+x] - sin(Adx)*Cxo[yp1*dimX+x] - Cyo[ind])
			+ diffd[ind]*(cos(Adx)*Cyo[ym1*dimX+x] + sin(Adx)*Cxo[ym1*dimX+x] - Cyo[ind])
			+ diffl[ind]*(Cyo[y*dimX+xp1] - Cyo[ind])
			+ diffr[ind]*(Cyo[y*dimX+xm1] - Cyo[ind]);
	}
}

	.text
	.file	"dwmr2dp.hip"
	.globl	_Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi # -- Begin function _Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.type	_Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi,@function
_Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi: # @_Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	movq	%r9, 72(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi, .Lfunc_end0-_Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi,@object # @_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.section	.rodata,"a",@progbits
	.globl	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.p2align	3, 0x0
_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi:
	.quad	_Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.size	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi ; -- Begin function _Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.globl	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
	.p2align	8
	.type	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi,@function
_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi:     ; @_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
; %bb.0:
	s_load_b32 s4, s[0:1], 0x5c
	s_add_u32 s2, s0, 0x50
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, s14, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_i32_e32 -1, v12
	s_cbranch_execz .LBB0_43
; %bb.1:
	s_load_b32 s6, s[2:3], 0x4
	s_load_b64 s[2:3], s[0:1], 0x48
	s_waitcnt lgkmcnt(0)
	s_add_i32 s7, s6, -1
	v_cmp_gt_i32_e32 vcc_lo, s3, v12
	s_cmp_gt_i32 s15, -1
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s4, vcc_lo
	s_cmp_le_u32 s15, s7
	s_cselect_b32 s5, -1, 0
	s_and_b32 s4, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB0_43
; %bb.2:
	s_load_b512 s[16:31], s[0:1], 0x0
	s_mul_i32 s5, s15, s3
	s_load_b64 s[0:1], s[0:1], 0x40
	v_add_nc_u32_e32 v0, s5, v12
	v_cmp_ngt_f32_e64 s4, 0x48000000, |s2|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s24, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s25, v1, vcc_lo
	global_load_b32 v25, v[2:3], off
	global_load_b32 v26, v[6:7], off
	global_load_b32 v27, v[8:9], off
	s_and_b32 vcc_lo, exec_lo, s4
	s_and_b32 s1, s2, 0x7fffffff
	s_cbranch_vccz .LBB0_4
; %bb.3:
	s_and_b32 s0, s1, 0x7fffff
	s_lshr_b32 s8, s1, 23
	s_bitset1_b32 s0, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s0, 0xfe5163ab
	s_mul_i32 s10, s0, 0x3c439041
	s_mul_hi_u32 s11, s0, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s0, 0xdb629599
	s_mul_hi_u32 s12, s0, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s0, 0xf534ddc0
	s_mul_hi_u32 s13, s0, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s0, 0xfc2757d1
	s_mul_hi_u32 s14, s0, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s14
	s_mul_i32 s14, s0, 0x4e441529
	s_mul_hi_u32 s24, s0, 0x4e441529
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s24
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s24, s0, 0xfe5163ab
	s_mul_hi_u32 s25, s0, 0xa2f9836e
	s_mul_i32 s0, s0, 0xa2f9836e
	s_cselect_b32 s33, s10, s12
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s24, s10
	s_add_u32 s0, s14, s0
	s_addc_u32 s14, 0, s25
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s24, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s0, s12, s0
	s_cselect_b32 s12, s13, s14
	s_add_i32 s24, s24, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s24, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s0
	s_cselect_b32 s0, s0, s12
	s_cselect_b32 s11, s33, s11
	s_cselect_b32 s12, s9, s33
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s0, s13, s0
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s9, s9, s12
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v2, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v3, s0, s13, v2
	v_alignbit_b32 v4, s13, s11, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v3
	v_cndmask_b32_e64 v3, v4, s13, s10
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s0, s0, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v4, s0, v3, 30
	s_bfe_u32 s8, s0, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, 0, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v4, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v5, v4
	v_min_u32_e32 v5, 32, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 23, v5
	v_alignbit_b32 v2, s11, s9, v2
	v_sub_nc_u32_e32 v10, 31, v5
	v_cndmask_b32_e64 v2, v2, s11, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v3, v3, v2, 30
	v_alignbit_b32 v2, v2, s9, 30
	s_lshr_b32 s9, s0, 29
	s_lshl_b32 s9, s9, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, s12, v3
	v_xor_b32_e32 v2, s12, v2
	s_or_b32 s10, s9, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, s10, v11
	v_alignbit_b32 v4, v4, v3, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v2, v3, v2, v10
	v_alignbit_b32 v3, v4, v2, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v10, v3
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, 31, v10
	v_alignbit_b32 v2, v3, v2, v13
	v_lshrrev_b32_e32 v3, 9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v2, 9, v2
	v_or_b32_e32 v3, v3, v11
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 23, v5
	v_sub_nc_u32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x3fc90fda, v3
	v_add_nc_u32_e32 v2, 0x33000000, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, 0x3fc90fda, v3, -v4
	v_or_b32_e32 v2, s9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v3, 0x33a22168, v5
	s_lshr_b32 s9, s0, 30
	s_mov_b32 s0, 0
	s_add_i32 s8, s8, s9
	v_fmac_f32_e32 v3, 0x3fc90fda, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v28, v4, v3
	s_branch .LBB0_5
.LBB0_4:
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $vgpr28
.LBB0_5:                                ; %Flow247
	v_mov_b32_e32 v30, s8
	v_mul_f32_e64 v24, 0x3f22f983, |s2|
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_7
; %bb.6:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v24
	v_fma_f32 v3, 0xbfc90fda, v2, |s2|
	v_cvt_i32_f32_e32 v30, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v2, 0xb3a22168, v3
	v_fmamk_f32 v28, v2, 0xa7c234c4, v3
.LBB0_7:                                ; %_ZL3cosf.exit
	s_add_i32 s0, s15, 1
	s_cmp_lg_u32 s15, s7
	s_cselect_b32 s0, s0, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s0, s3, v[12:13]
	s_mov_b32 s0, 0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s20, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v3, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s4
	global_load_b32 v29, v[4:5], off
	s_cbranch_vccz .LBB0_9
; %bb.8:
	s_and_b32 s7, s1, 0x7fffff
	s_lshr_b32 s8, s1, 23
	s_bitset1_b32 s7, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s7, 0xfe5163ab
	s_mul_i32 s10, s7, 0x3c439041
	s_mul_hi_u32 s11, s7, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s7, 0xdb629599
	s_mul_hi_u32 s12, s7, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s7, 0xf534ddc0
	s_mul_hi_u32 s13, s7, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s7, 0xfc2757d1
	s_mul_hi_u32 s14, s7, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s14
	s_mul_i32 s14, s7, 0x4e441529
	s_mul_hi_u32 s24, s7, 0x4e441529
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s24
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s24, s7, 0xfe5163ab
	s_mul_hi_u32 s25, s7, 0xa2f9836e
	s_mul_i32 s7, s7, 0xa2f9836e
	s_cselect_b32 s33, s10, s12
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s24, s10
	s_add_u32 s7, s14, s7
	s_addc_u32 s14, 0, s25
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s24, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s7, s12, s7
	s_cselect_b32 s12, s13, s14
	s_add_i32 s24, s24, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s24, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s7
	s_cselect_b32 s7, s7, s12
	s_cselect_b32 s11, s33, s11
	s_cselect_b32 s12, s9, s33
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s9, s9, s12
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v10, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v11, s7, s13, v10
	v_alignbit_b32 v13, s13, s11, v10
	v_alignbit_b32 v10, s11, s9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s8, v11
	v_cndmask_b32_e64 v11, v13, s13, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, s11, s10
	s_cselect_b32 s7, s7, s8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v13, s7, v11, 30
	s_bfe_u32 s8, s7, 0x1001d
	s_delay_alu instid0(VALU_DEP_2)
	v_alignbit_b32 v11, v11, v10, 30
	s_sub_i32 s12, 0, s8
	v_alignbit_b32 v10, v10, s9, 30
	v_xor_b32_e32 v13, s12, v13
	s_lshr_b32 s9, s7, 29
	v_xor_b32_e32 v11, s12, v11
	s_lshl_b32 s9, s9, 31
	v_xor_b32_e32 v10, s12, v10
	v_clz_i32_u32_e32 v14, v13
	s_or_b32 s10, s9, 0.5
	s_lshr_b32 s7, s7, 30
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s7, s8, s7
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	v_alignbit_b32 v13, v13, v11, v15
	v_alignbit_b32 v10, v11, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, s10, v16
	v_alignbit_b32 v11, v13, v10, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v15, v11
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v15
	v_add_nc_u32_e32 v14, v15, v14
	v_alignbit_b32 v10, v11, v10, v17
	v_lshrrev_b32_e32 v11, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v13, 23, v14
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v11, v11, v16
	v_sub_nc_u32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, 0x3fc90fda, v11
	v_add_nc_u32_e32 v10, 0x33000000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, 0x3fc90fda, v11, -v13
	v_or_b32_e32 v10, s9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v11, v11, 0x33a22168, v14
	v_fmac_f32_e32 v11, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v31, v13, v11
	s_branch .LBB0_10
.LBB0_9:
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $vgpr31
.LBB0_10:                               ; %Flow246
	v_mov_b32_e32 v34, s7
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_12
; %bb.11:
	v_rndne_f32_e32 v10, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0xbfc90fda, v10, |s2|
	v_cvt_i32_f32_e32 v34, v10
	v_fmamk_f32 v11, v10, 0xb3a22168, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v31, v10, 0xa7c234c4, v11
.LBB0_12:                               ; %_ZL3sinf.exit
	v_add_co_u32 v20, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v21, vcc_lo, s23, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s26, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s27, v1, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s4
	global_load_b32 v33, v[20:21], off
	global_load_b32 v32, v[10:11], off
	s_cbranch_vccz .LBB0_14
; %bb.13:
	s_and_b32 s0, s1, 0x7fffff
	s_lshr_b32 s7, s1, 23
	s_bitset1_b32 s0, 23
	s_addk_i32 s7, 0xff88
	s_mul_hi_u32 s8, s0, 0xfe5163ab
	s_mul_i32 s9, s0, 0x3c439041
	s_mul_hi_u32 s10, s0, 0x3c439041
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s0, 0xdb629599
	s_mul_hi_u32 s11, s0, 0xdb629599
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s0, 0xf534ddc0
	s_mul_hi_u32 s12, s0, 0xf534ddc0
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s0, 0xfc2757d1
	s_mul_hi_u32 s13, s0, 0xfc2757d1
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s0, 0x4e441529
	s_mul_hi_u32 s14, s0, 0x4e441529
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s14
	s_cmp_gt_u32 s7, 63
	s_mul_i32 s14, s0, 0xfe5163ab
	s_mul_hi_u32 s24, s0, 0xa2f9836e
	s_mul_i32 s0, s0, 0xa2f9836e
	s_cselect_b32 s25, s9, s11
	s_cselect_b32 s8, s8, s10
	s_cselect_b32 s9, s14, s9
	s_add_u32 s0, s13, s0
	s_addc_u32 s13, 0, s24
	s_cmp_gt_u32 s7, 63
	s_cselect_b32 s14, 0xffffffc0, 0
	s_cselect_b32 s10, s10, s12
	s_cselect_b32 s0, s11, s0
	s_cselect_b32 s11, s12, s13
	s_add_i32 s14, s14, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s14, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s12, s10, s0
	s_cselect_b32 s0, s0, s11
	s_cselect_b32 s10, s25, s10
	s_cselect_b32 s11, s8, s25
	s_cselect_b32 s8, s9, s8
	s_add_i32 s7, s7, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s7, 31
	s_cselect_b32 s9, 0xffffffe0, 0
	s_cselect_b32 s0, s12, s0
	s_cselect_b32 s12, s10, s12
	s_cselect_b32 s10, s11, s10
	s_cselect_b32 s8, s8, s11
	s_add_i32 s9, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s7, 32, s9
	s_cmp_eq_u32 s9, 0
	v_mov_b32_e32 v2, s7
	s_cselect_b32 s9, -1, 0
	v_alignbit_b32 v3, s0, s12, v2
	v_alignbit_b32 v13, s12, s10, v2
	v_alignbit_b32 v2, s10, s8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s7, v3
	v_cndmask_b32_e64 v3, v13, s12, s9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v2, s10, s9
	s_cselect_b32 s0, s0, s7
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v13, s0, v3, 30
	s_bfe_u32 s7, s0, 0x1001d
	s_delay_alu instid0(VALU_DEP_2)
	v_alignbit_b32 v3, v3, v2, 30
	s_sub_i32 s11, 0, s7
	v_alignbit_b32 v2, v2, s8, 30
	v_xor_b32_e32 v13, s11, v13
	s_lshr_b32 s8, s0, 29
	v_xor_b32_e32 v3, s11, v3
	s_lshl_b32 s8, s8, 31
	v_xor_b32_e32 v2, s11, v2
	v_clz_i32_u32_e32 v14, v13
	s_or_b32 s9, s8, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v15, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v13, v3, v15
	v_alignbit_b32 v2, v3, v2, v15
	v_sub_nc_u32_e32 v16, s9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v3, v13, v2, 9
	v_clz_i32_u32_e32 v15, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v15, 32, v15
	v_sub_nc_u32_e32 v17, 31, v15
	v_add_nc_u32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v2, v3, v2, v17
	v_lshrrev_b32_e32 v3, 9, v13
	v_lshlrev_b32_e32 v13, 23, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v2, 9, v2
	v_or_b32_e32 v3, v3, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v13
	v_mul_f32_e32 v13, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0x33000000, v2
	v_fma_f32 v14, 0x3fc90fda, v3, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v2, s8, v2
	v_fmamk_f32 v3, v3, 0x33a22168, v14
	s_lshr_b32 s8, s0, 30
	s_mov_b32 s0, 0
	s_add_i32 s7, s7, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0x3fc90fda, v2
	v_add_f32_e32 v35, v13, v3
	s_branch .LBB0_15
.LBB0_14:
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $vgpr35
.LBB0_15:                               ; %Flow245
	v_mov_b32_e32 v37, s7
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_17
; %bb.16:
	v_rndne_f32_e32 v2, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, 0xbfc90fda, v2, |s2|
	v_cvt_i32_f32_e32 v37, v2
	v_fmamk_f32 v3, v2, 0xb3a22168, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v35, v2, 0xa7c234c4, v3
.LBB0_17:                               ; %_ZL3cosf.exit146
	s_cmp_eq_u32 s15, 0
	s_cselect_b32 s0, s6, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, -1
	v_mad_u64_u32 v[2:3], null, s0, s3, v[12:13]
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[13:14], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s20, v13
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v14, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s4
	global_load_b32 v36, v[2:3], off
	s_cbranch_vccz .LBB0_19
; %bb.18:
	s_and_b32 s0, s1, 0x7fffff
	s_lshr_b32 s6, s1, 23
	s_bitset1_b32 s0, 23
	s_addk_i32 s6, 0xff88
	s_mul_hi_u32 s7, s0, 0xfe5163ab
	s_mul_i32 s8, s0, 0x3c439041
	s_mul_hi_u32 s9, s0, 0x3c439041
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s0, 0xdb629599
	s_mul_hi_u32 s10, s0, 0xdb629599
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s0, 0xf534ddc0
	s_mul_hi_u32 s11, s0, 0xf534ddc0
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s0, 0xfc2757d1
	s_mul_hi_u32 s12, s0, 0xfc2757d1
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s0, 0x4e441529
	s_mul_hi_u32 s13, s0, 0x4e441529
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_cmp_gt_u32 s6, 63
	s_mul_i32 s13, s0, 0xfe5163ab
	s_mul_hi_u32 s14, s0, 0xa2f9836e
	s_mul_i32 s0, s0, 0xa2f9836e
	s_cselect_b32 s15, s8, s10
	s_cselect_b32 s7, s7, s9
	s_cselect_b32 s8, s13, s8
	s_add_u32 s0, s12, s0
	s_addc_u32 s12, 0, s14
	s_cmp_gt_u32 s6, 63
	s_cselect_b32 s13, 0xffffffc0, 0
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s0, s10, s0
	s_cselect_b32 s10, s11, s12
	s_add_i32 s13, s13, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s13, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s11, s9, s0
	s_cselect_b32 s0, s0, s10
	s_cselect_b32 s9, s15, s9
	s_cselect_b32 s10, s7, s15
	s_cselect_b32 s7, s8, s7
	s_add_i32 s6, s6, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s6, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s0, s11, s0
	s_cselect_b32 s11, s9, s11
	s_cselect_b32 s9, s10, s9
	s_cselect_b32 s7, s7, s10
	s_add_i32 s8, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s6, 32, s8
	s_cmp_eq_u32 s8, 0
	v_mov_b32_e32 v15, s6
	s_cselect_b32 s8, -1, 0
	v_alignbit_b32 v16, s0, s11, v15
	v_alignbit_b32 v17, s11, s9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s6, v16
	v_cndmask_b32_e64 v16, v17, s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s0, s0, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v17, s0, v16, 30
	s_bfe_u32 s6, s0, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s10, 0, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v17, s10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v18, v17
	v_min_u32_e32 v18, 32, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v22, 23, v18
	v_alignbit_b32 v15, s9, s7, v15
	v_sub_nc_u32_e32 v19, 31, v18
	v_cndmask_b32_e64 v15, v15, s9, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v15, v15, s7, 30
	s_lshr_b32 s7, s0, 29
	s_lshr_b32 s0, s0, 30
	s_lshl_b32 s7, s7, 31
	v_xor_b32_e32 v16, s10, v16
	v_xor_b32_e32 v15, s10, v15
	s_or_b32 s8, s7, 0.5
	s_add_i32 s6, s6, s0
	v_sub_nc_u32_e32 v22, s8, v22
	v_alignbit_b32 v17, v17, v16, v19
	v_alignbit_b32 v15, v16, v15, v19
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v17, v15, 9
	v_lshrrev_b32_e32 v17, 9, v17
	v_clz_i32_u32_e32 v19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v19, 32, v19
	v_sub_nc_u32_e32 v23, 31, v19
	v_add_nc_u32_e32 v18, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v16, v15, v23
	v_or_b32_e32 v16, v17, v22
	v_lshlrev_b32_e32 v17, 23, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v15, 9, v15
	v_mul_f32_e32 v18, 0x3fc90fda, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v15, v17
	v_fma_f32 v17, 0x3fc90fda, v16, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v15, 0x33000000, v15
	v_fmamk_f32 v16, v16, 0x33a22168, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v15, s7, v15
	v_fmac_f32_e32 v16, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v38, v18, v16
	s_branch .LBB0_20
.LBB0_19:
                                        ; implicit-def: $sgpr6
                                        ; implicit-def: $vgpr38
.LBB0_20:                               ; %Flow244
	v_mov_b32_e32 v39, s6
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_22
; %bb.21:
	v_rndne_f32_e32 v15, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v16, 0xbfc90fda, v15, |s2|
	v_cvt_i32_f32_e32 v39, v15
	v_fmamk_f32 v16, v15, 0xb3a22168, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v38, v15, 0xa7c234c4, v16
.LBB0_22:                               ; %_ZL3sinf.exit154
	s_add_i32 s0, s3, -1
	v_dual_mul_f32 v45, v35, v35 :: v_dual_and_b32 v48, 1, v30
	v_add_nc_u32_e32 v15, 1, v12
	v_cmp_ne_u32_e32 vcc_lo, s0, v12
	v_dual_mul_f32 v51, v38, v38 :: v_dual_and_b32 v52, 1, v39
	v_and_b32_e32 v46, 1, v37
	s_mov_b32 s0, 0xb94c1982
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	v_dual_mul_f32 v49, v31, v31 :: v_dual_lshlrev_b32 v30, 30, v30
	v_dual_mul_f32 v47, v28, v28 :: v_dual_and_b32 v50, 1, v34
	v_fmaak_f32 v53, s0, v45, 0x3c0881c4
	v_cndmask_b32_e64 v16, v12, s3, vcc_lo
	v_add_nc_u32_e32 v12, s5, v15
	v_add_co_u32 v22, vcc_lo, s22, v13
	v_add_co_ci_u32_e32 v23, vcc_lo, s23, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v14, s5, -1, v16
	v_ashrrev_i32_e32 v13, 31, v12
	s_mov_b32 s3, 0x37d75334
	global_load_b32 v42, v[22:23], off
	v_fmaak_f32 v59, s0, v51, 0x3c0881c4
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[18:19], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s29, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[16:17], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s20, v18
	v_add_co_ci_u32_e32 v15, vcc_lo, s21, v19, vcc_lo
	v_fmaak_f32 v54, s3, v45, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v40, vcc_lo, s20, v16
	v_add_co_ci_u32_e32 v41, vcc_lo, s21, v17, vcc_lo
	global_load_b32 v43, v[14:15], off
	v_add_co_u32 v14, vcc_lo, s30, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, s31, v1, vcc_lo
	global_load_b32 v40, v[40:41], off
	global_load_b32 v41, v[12:13], off
	global_load_b32 v44, v[14:15], off
	v_fmaak_f32 v59, v51, v59, 0xbe2aaa9d
	v_dual_fmaak_f32 v58, s3, v49, 0xbab64f3b :: v_dual_lshlrev_b32 v39, 30, v39
	v_fmaak_f32 v53, v45, v53, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v54, v45, v54, 0x3d2aabf7 :: v_dual_mul_f32 v59, v51, v59
	v_fmaak_f32 v57, s0, v49, 0x3c0881c4
	v_dual_mul_f32 v53, v45, v53 :: v_dual_and_b32 v30, 0x80000000, v30
	v_fmaak_f32 v58, v49, v58, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v38, v38, v59 :: v_dual_fmaak_f32 v57, v49, v57, 0xbe2aaa9d
	v_dual_fmaak_f32 v55, s0, v47, 0x3c0881c4 :: v_dual_lshlrev_b32 v34, 30, v34
	v_dual_fmaak_f32 v60, s3, v51, 0xbab64f3b :: v_dual_fmac_f32 v35, v35, v53
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v57, v49, v57
	v_dual_fmaak_f32 v58, v49, v58, 0xbf000004 :: v_dual_lshlrev_b32 v37, 30, v37
	v_fmaak_f32 v56, s3, v47, 0xbab64f3b
	v_fmaak_f32 v55, v47, v55, 0xbe2aaa9d
	v_and_b32_e32 v34, 0x80000000, v34
	v_dual_fmaak_f32 v54, v45, v54, 0xbf000004 :: v_dual_fmac_f32 v31, v31, v57
	v_fma_f32 v49, v49, v58, 1.0
	v_cmp_eq_u32_e32 vcc_lo, 0, v50
	v_fmaak_f32 v56, v47, v56, 0x3d2aabf7
	v_mul_f32_e32 v55, v47, v55
	v_xor_b32_e32 v34, s1, v34
	v_cmp_class_f32_e64 s0, s2, 0x1f8
	v_cndmask_b32_e32 v31, v49, v31, vcc_lo
	v_fma_f32 v45, v45, v54, 1.0
	v_cmp_eq_u32_e32 vcc_lo, 0, v46
	v_fmaak_f32 v56, v47, v56, 0xbf000004
	v_dual_fmac_f32 v28, v28, v55 :: v_dual_and_b32 v37, 0x80000000, v37
	v_xor_b32_e32 v31, v34, v31
	v_cndmask_b32_e64 v35, -v35, v45, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v52
	v_fma_f32 v47, v47, v56, 1.0
	s_mov_b32 s3, -1
	v_xor_b32_e32 v31, s2, v31
	v_xor_b32_e32 v35, v37, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v31, 0x7fc00000, v31, s0
	s_waitcnt vmcnt(7)
	v_dual_fmaak_f32 v60, v51, v60, 0x3d2aabf7 :: v_dual_mul_f32 v31, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v60, v51, v60, 0xbf000004
	v_fma_f32 v49, v51, v60, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v34, v49, v38 :: v_dual_and_b32 v39, 0x80000000, v39
	v_xor_b32_e32 v39, s1, v39
	v_cmp_eq_u32_e32 vcc_lo, 0, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v34, v39, v34
	v_cndmask_b32_e64 v28, -v28, v47, vcc_lo
	v_xor_b32_e32 v34, s2, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v28, v30, v28
	v_cndmask_b32_e64 v30, 0x7fc00000, v35, s0
	v_cndmask_b32_e64 v33, 0x7fc00000, v34, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, 0x7fc00000, v28, s0
	v_fmac_f32_e32 v31, v29, v28
	v_fma_f32 v29, -v25, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v26, v31, v25
	s_waitcnt vmcnt(4)
	v_dual_fmac_f32 v29, v27, v26 :: v_dual_mul_f32 v28, v42, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, v36, v30, -v28
	v_sub_f32_e32 v26, v28, v25
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v29, v32, v26 :: v_dual_sub_f32 v26, v43, v25
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v27, v40, v25
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v29, v41, v26
	v_add_co_u32 v25, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v26, vcc_lo, s17, v1, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v29, v44, v27
	v_add_co_u32 v27, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v28, vcc_lo, s23, v1, vcc_lo
	global_store_b32 v[25:26], v29, off
	global_load_b32 v25, v[27:28], off
	global_load_b32 v7, v[6:7], off
	global_load_b32 v6, v[8:9], off
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_24
; %bb.23:
	s_and_b32 s3, s1, 0x7fffff
	s_lshr_b32 s5, s1, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s5, 0xff88
	s_mul_hi_u32 s6, s3, 0xfe5163ab
	s_mul_i32 s7, s3, 0x3c439041
	s_mul_hi_u32 s8, s3, 0x3c439041
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s3, 0xdb629599
	s_mul_hi_u32 s9, s3, 0xdb629599
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s3, 0xf534ddc0
	s_mul_hi_u32 s10, s3, 0xf534ddc0
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s3, 0xfc2757d1
	s_mul_hi_u32 s11, s3, 0xfc2757d1
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s3, 0x4e441529
	s_mul_hi_u32 s12, s3, 0x4e441529
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_cmp_gt_u32 s5, 63
	s_mul_i32 s12, s3, 0xfe5163ab
	s_mul_hi_u32 s13, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s14, s7, s9
	s_cselect_b32 s6, s6, s8
	s_cselect_b32 s7, s12, s7
	s_add_u32 s3, s11, s3
	s_addc_u32 s11, 0, s13
	s_cmp_gt_u32 s5, 63
	s_cselect_b32 s12, 0xffffffc0, 0
	s_cselect_b32 s8, s8, s10
	s_cselect_b32 s3, s9, s3
	s_cselect_b32 s9, s10, s11
	s_add_i32 s12, s12, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s12, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s10, s8, s3
	s_cselect_b32 s3, s3, s9
	s_cselect_b32 s8, s14, s8
	s_cselect_b32 s9, s6, s14
	s_cselect_b32 s6, s7, s6
	s_add_i32 s5, s5, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s5, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s3, s10, s3
	s_cselect_b32 s10, s8, s10
	s_cselect_b32 s8, s9, s8
	s_cselect_b32 s6, s6, s9
	s_add_i32 s7, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s5, 32, s7
	s_cmp_eq_u32 s7, 0
	v_mov_b32_e32 v8, s5
	s_cselect_b32 s7, -1, 0
	v_alignbit_b32 v9, s3, s10, v8
	v_alignbit_b32 v26, s10, s8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s5, v9
	v_cndmask_b32_e64 v9, v26, s10, s7
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v26, s3, v9, 30
	s_bfe_u32 s5, s3, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s9, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v26, s9, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v27, v26
	v_min_u32_e32 v27, 32, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v29, 23, v27
	v_alignbit_b32 v8, s8, s6, v8
	v_sub_nc_u32_e32 v28, 31, v27
	v_cndmask_b32_e64 v8, v8, s8, s7
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v8, v8, s6, 30
	s_lshr_b32 s6, s3, 29
	s_lshr_b32 s3, s3, 30
	s_lshl_b32 s6, s6, 31
	v_xor_b32_e32 v9, s9, v9
	v_xor_b32_e32 v8, s9, v8
	s_or_b32 s7, s6, 0.5
	s_add_i32 s5, s5, s3
	v_sub_nc_u32_e32 v29, s7, v29
	v_alignbit_b32 v26, v26, v9, v28
	v_alignbit_b32 v8, v9, v8, v28
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v9, v26, v8, 9
	v_lshrrev_b32_e32 v26, 9, v26
	v_clz_i32_u32_e32 v28, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v28, 32, v28
	v_sub_nc_u32_e32 v30, 31, v28
	v_add_nc_u32_e32 v27, v28, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v9, v8, v30
	v_or_b32_e32 v9, v26, v29
	v_lshlrev_b32_e32 v26, 23, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v8, 9, v8
	v_mul_f32_e32 v27, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v26
	v_fma_f32 v26, 0x3fc90fda, v9, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 0x33000000, v8
	v_fmamk_f32 v9, v9, 0x33a22168, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v8, s6, v8
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v8, v27, v9
	s_branch .LBB0_25
.LBB0_24:
                                        ; implicit-def: $sgpr5
                                        ; implicit-def: $vgpr8
.LBB0_25:                               ; %Flow243
	v_mov_b32_e32 v26, s5
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_27
; %bb.26:
	v_rndne_f32_e32 v9, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0xbfc90fda, v9, |s2|
	v_cvt_i32_f32_e32 v26, v9
	v_fmamk_f32 v8, v9, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v8, v9, 0xa7c234c4, v8
.LBB0_27:                               ; %_ZL3cosf.exit160
	global_load_b32 v9, v[20:21], off
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_29
; %bb.28:
	s_and_b32 s3, s1, 0x7fffff
	s_lshr_b32 s5, s1, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s5, 0xff88
	s_mul_hi_u32 s6, s3, 0xfe5163ab
	s_mul_i32 s7, s3, 0x3c439041
	s_mul_hi_u32 s8, s3, 0x3c439041
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s3, 0xdb629599
	s_mul_hi_u32 s9, s3, 0xdb629599
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s3, 0xf534ddc0
	s_mul_hi_u32 s10, s3, 0xf534ddc0
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s3, 0xfc2757d1
	s_mul_hi_u32 s11, s3, 0xfc2757d1
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s3, 0x4e441529
	s_mul_hi_u32 s12, s3, 0x4e441529
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_cmp_gt_u32 s5, 63
	s_mul_i32 s12, s3, 0xfe5163ab
	s_mul_hi_u32 s13, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s14, s7, s9
	s_cselect_b32 s6, s6, s8
	s_cselect_b32 s7, s12, s7
	s_add_u32 s3, s11, s3
	s_addc_u32 s11, 0, s13
	s_cmp_gt_u32 s5, 63
	s_cselect_b32 s12, 0xffffffc0, 0
	s_cselect_b32 s8, s8, s10
	s_cselect_b32 s3, s9, s3
	s_cselect_b32 s9, s10, s11
	s_add_i32 s12, s12, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s12, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s10, s8, s3
	s_cselect_b32 s3, s3, s9
	s_cselect_b32 s8, s14, s8
	s_cselect_b32 s9, s6, s14
	s_cselect_b32 s6, s7, s6
	s_add_i32 s5, s5, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s5, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s3, s10, s3
	s_cselect_b32 s10, s8, s10
	s_cselect_b32 s8, s9, s8
	s_cselect_b32 s6, s6, s9
	s_add_i32 s7, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s5, 32, s7
	s_cmp_eq_u32 s7, 0
	v_mov_b32_e32 v20, s5
	s_cselect_b32 s7, -1, 0
	v_alignbit_b32 v21, s3, s10, v20
	v_alignbit_b32 v27, s10, s8, v20
	v_alignbit_b32 v20, s8, s6, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s5, v21
	v_cndmask_b32_e64 v21, v27, s10, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v20, s8, s7
	s_cselect_b32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v27, s3, v21, 30
	s_bfe_u32 s5, s3, 0x1001d
	s_delay_alu instid0(VALU_DEP_2)
	v_alignbit_b32 v21, v21, v20, 30
	s_sub_i32 s9, 0, s5
	v_alignbit_b32 v20, v20, s6, 30
	v_xor_b32_e32 v27, s9, v27
	s_lshr_b32 s6, s3, 29
	v_xor_b32_e32 v21, s9, v21
	s_lshl_b32 s6, s6, 31
	v_xor_b32_e32 v20, s9, v20
	v_clz_i32_u32_e32 v28, v27
	s_or_b32 s7, s6, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v28, 32, v28
	v_sub_nc_u32_e32 v29, 31, v28
	v_lshlrev_b32_e32 v30, 23, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v27, v21, v29
	v_alignbit_b32 v20, v21, v20, v29
	v_sub_nc_u32_e32 v30, s7, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v21, v27, v20, 9
	v_clz_i32_u32_e32 v29, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v29, 32, v29
	v_sub_nc_u32_e32 v31, 31, v29
	v_add_nc_u32_e32 v28, v29, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v21, v20, v31
	v_lshrrev_b32_e32 v21, 9, v27
	v_lshlrev_b32_e32 v27, 23, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v20, 9, v20
	v_or_b32_e32 v21, v21, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v20, v20, v27
	v_mul_f32_e32 v27, 0x3fc90fda, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v20, 0x33000000, v20
	v_fma_f32 v28, 0x3fc90fda, v21, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v20, s6, v20
	v_fmamk_f32 v21, v21, 0x33a22168, v28
	s_lshr_b32 s6, s3, 30
	s_mov_b32 s3, 0
	s_add_i32 s5, s5, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, 0x3fc90fda, v20
	v_add_f32_e32 v20, v27, v21
	s_branch .LBB0_30
.LBB0_29:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr5
                                        ; implicit-def: $vgpr20
.LBB0_30:                               ; %Flow242
	v_mov_b32_e32 v21, s5
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_32
; %bb.31:
	v_rndne_f32_e32 v21, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, 0xbfc90fda, v21, |s2|
	v_fmamk_f32 v20, v21, 0xb3a22168, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v20, v21, 0xa7c234c4, v20
	v_cvt_i32_f32_e32 v21, v21
.LBB0_32:                               ; %_ZL3sinf.exit168
	global_load_b32 v5, v[4:5], off
	global_load_b32 v4, v[10:11], off
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_34
; %bb.33:
	s_and_b32 s3, s1, 0x7fffff
	s_lshr_b32 s5, s1, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s5, 0xff88
	s_mul_hi_u32 s6, s3, 0xfe5163ab
	s_mul_i32 s7, s3, 0x3c439041
	s_mul_hi_u32 s8, s3, 0x3c439041
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s3, 0xdb629599
	s_mul_hi_u32 s9, s3, 0xdb629599
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s3, 0xf534ddc0
	s_mul_hi_u32 s10, s3, 0xf534ddc0
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s3, 0xfc2757d1
	s_mul_hi_u32 s11, s3, 0xfc2757d1
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s3, 0x4e441529
	s_mul_hi_u32 s12, s3, 0x4e441529
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_cmp_gt_u32 s5, 63
	s_mul_i32 s12, s3, 0xfe5163ab
	s_mul_hi_u32 s13, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s14, s7, s9
	s_cselect_b32 s6, s6, s8
	s_cselect_b32 s7, s12, s7
	s_add_u32 s3, s11, s3
	s_addc_u32 s11, 0, s13
	s_cmp_gt_u32 s5, 63
	s_cselect_b32 s12, 0xffffffc0, 0
	s_cselect_b32 s8, s8, s10
	s_cselect_b32 s3, s9, s3
	s_cselect_b32 s9, s10, s11
	s_add_i32 s12, s12, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s12, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s10, s8, s3
	s_cselect_b32 s3, s3, s9
	s_cselect_b32 s8, s14, s8
	s_cselect_b32 s9, s6, s14
	s_cselect_b32 s6, s7, s6
	s_add_i32 s5, s5, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s5, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s3, s10, s3
	s_cselect_b32 s10, s8, s10
	s_cselect_b32 s8, s9, s8
	s_cselect_b32 s6, s6, s9
	s_add_i32 s7, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s5, 32, s7
	s_cmp_eq_u32 s7, 0
	v_mov_b32_e32 v10, s5
	s_cselect_b32 s7, -1, 0
	v_alignbit_b32 v11, s3, s10, v10
	v_alignbit_b32 v27, s10, s8, v10
	v_alignbit_b32 v10, s8, s6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s5, v11
	v_cndmask_b32_e64 v11, v27, s10, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, s8, s7
	s_cselect_b32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v27, s3, v11, 30
	s_bfe_u32 s5, s3, 0x1001d
	s_delay_alu instid0(VALU_DEP_2)
	v_alignbit_b32 v11, v11, v10, 30
	s_sub_i32 s9, 0, s5
	v_alignbit_b32 v10, v10, s6, 30
	v_xor_b32_e32 v27, s9, v27
	s_lshr_b32 s6, s3, 29
	v_xor_b32_e32 v11, s9, v11
	s_lshl_b32 s6, s6, 31
	v_xor_b32_e32 v10, s9, v10
	v_clz_i32_u32_e32 v28, v27
	s_or_b32 s7, s6, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v28, 32, v28
	v_sub_nc_u32_e32 v29, 31, v28
	v_lshlrev_b32_e32 v30, 23, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v27, v11, v29
	v_alignbit_b32 v10, v11, v10, v29
	v_sub_nc_u32_e32 v30, s7, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v11, v27, v10, 9
	v_clz_i32_u32_e32 v29, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v29, 32, v29
	v_sub_nc_u32_e32 v31, 31, v29
	v_add_nc_u32_e32 v28, v29, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v10, v31
	v_lshrrev_b32_e32 v11, 9, v27
	v_lshlrev_b32_e32 v27, 23, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v10, 9, v10
	v_or_b32_e32 v11, v11, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v27
	v_mul_f32_e32 v27, 0x3fc90fda, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 0x33000000, v10
	v_fma_f32 v28, 0x3fc90fda, v11, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v10, s6, v10
	v_fmamk_f32 v11, v11, 0x33a22168, v28
	s_lshr_b32 s6, s3, 30
	s_mov_b32 s3, 0
	s_add_i32 s5, s5, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, 0x3fc90fda, v10
	v_add_f32_e32 v10, v27, v11
	s_branch .LBB0_35
.LBB0_34:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr5
                                        ; implicit-def: $vgpr10
.LBB0_35:                               ; %Flow241
	v_mov_b32_e32 v27, s5
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_37
; %bb.36:
	v_rndne_f32_e32 v11, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0xbfc90fda, v11, |s2|
	v_cvt_i32_f32_e32 v27, v11
	v_fmamk_f32 v10, v11, 0xb3a22168, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v10, v11, 0xa7c234c4, v10
.LBB0_37:                               ; %_ZL3cosf.exit174
	global_load_b32 v11, v[22:23], off
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_39
; %bb.38:
	s_and_b32 s3, s1, 0x7fffff
	s_lshr_b32 s4, s1, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s4, 0xff88
	s_mul_hi_u32 s5, s3, 0xfe5163ab
	s_mul_i32 s6, s3, 0x3c439041
	s_mul_hi_u32 s7, s3, 0x3c439041
	s_add_u32 s5, s5, s6
	s_addc_u32 s6, 0, s7
	s_mul_i32 s7, s3, 0xdb629599
	s_mul_hi_u32 s8, s3, 0xdb629599
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s3, 0xf534ddc0
	s_mul_hi_u32 s9, s3, 0xf534ddc0
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s3, 0xfc2757d1
	s_mul_hi_u32 s10, s3, 0xfc2757d1
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s3, 0x4e441529
	s_mul_hi_u32 s11, s3, 0x4e441529
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_cmp_gt_u32 s4, 63
	s_mul_i32 s11, s3, 0xfe5163ab
	s_mul_hi_u32 s12, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s13, s6, s8
	s_cselect_b32 s5, s5, s7
	s_cselect_b32 s6, s11, s6
	s_add_u32 s3, s10, s3
	s_addc_u32 s10, 0, s12
	s_cmp_gt_u32 s4, 63
	s_cselect_b32 s11, 0xffffffc0, 0
	s_cselect_b32 s7, s7, s9
	s_cselect_b32 s3, s8, s3
	s_cselect_b32 s8, s9, s10
	s_add_i32 s11, s11, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s11, 31
	s_cselect_b32 s4, 0xffffffe0, 0
	s_cselect_b32 s9, s7, s3
	s_cselect_b32 s3, s3, s8
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s8, s5, s13
	s_cselect_b32 s5, s6, s5
	s_add_i32 s4, s4, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s4, 31
	s_cselect_b32 s6, 0xffffffe0, 0
	s_cselect_b32 s3, s9, s3
	s_cselect_b32 s9, s7, s9
	s_cselect_b32 s7, s8, s7
	s_cselect_b32 s5, s5, s8
	s_add_i32 s6, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s4, 32, s6
	s_cmp_eq_u32 s6, 0
	v_mov_b32_e32 v22, s4
	s_cselect_b32 s6, -1, 0
	v_alignbit_b32 v23, s3, s9, v22
	v_alignbit_b32 v28, s9, s7, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s4, v23
	v_cndmask_b32_e64 v23, v28, s9, s6
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s3, s3, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v28, s3, v23, 30
	s_bfe_u32 s4, s3, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v28, s8, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v29, v28
	v_min_u32_e32 v29, 32, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v31, 23, v29
	v_alignbit_b32 v22, s7, s5, v22
	v_sub_nc_u32_e32 v30, 31, v29
	v_cndmask_b32_e64 v22, v22, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v23, v23, v22, 30
	v_alignbit_b32 v22, v22, s5, 30
	s_lshr_b32 s5, s3, 29
	s_lshl_b32 s5, s5, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v23, s8, v23
	v_xor_b32_e32 v22, s8, v22
	s_or_b32 s6, s5, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v31, s6, v31
	v_alignbit_b32 v28, v28, v23, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v22, v23, v22, v30
	v_alignbit_b32 v23, v28, v22, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v30, v23
	v_min_u32_e32 v30, 32, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v32, 31, v30
	v_alignbit_b32 v22, v23, v22, v32
	v_lshrrev_b32_e32 v23, 9, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v22, 9, v22
	v_or_b32_e32 v23, v23, v31
	v_add_nc_u32_e32 v29, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v28, 23, v29
	v_sub_nc_u32_e32 v22, v22, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v28, 0x3fc90fda, v23
	v_add_nc_u32_e32 v22, 0x33000000, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, 0x3fc90fda, v23, -v28
	v_or_b32_e32 v22, s5, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v23, v23, 0x33a22168, v29
	s_lshr_b32 s5, s3, 30
	s_mov_b32 s3, 0
	s_add_i32 s4, s4, s5
	v_fmac_f32_e32 v23, 0x3fc90fda, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v22, v28, v23
	s_branch .LBB0_40
.LBB0_39:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $vgpr22
.LBB0_40:                               ; %Flow
	v_mov_b32_e32 v23, s4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_42
; %bb.41:
	v_rndne_f32_e32 v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v22, 0xbfc90fda, v23, |s2|
	v_fmamk_f32 v22, v23, 0xb3a22168, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v22, v23, 0xa7c234c4, v22
	v_cvt_i32_f32_e32 v23, v23
.LBB0_42:                               ; %_ZL3sinf.exit182
	global_load_b32 v24, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s22, v18
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v19, vcc_lo
	v_add_co_u32 v16, vcc_lo, s22, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s23, v17, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[16:17], off
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[14:15], off
	s_mov_b32 s4, 0x37d75334
	v_dual_mul_f32 v17, v8, v8 :: v_dual_lshlrev_b32 v16, 30, v27
	v_and_b32_e32 v18, 1, v26
	v_dual_mul_f32 v26, v20, v20 :: v_dual_lshlrev_b32 v19, 30, v26
	s_mov_b32 s3, 0xb94c1982
	v_dual_mul_f32 v14, v10, v10 :: v_dual_and_b32 v15, 1, v27
	v_dual_mul_f32 v28, v22, v22 :: v_dual_and_b32 v27, 1, v21
	v_dual_fmaak_f32 v32, s3, v17, 0x3c0881c4 :: v_dual_and_b32 v29, 1, v23
	v_dual_fmaak_f32 v34, s3, v26, 0x3c0881c4 :: v_dual_lshlrev_b32 v23, 30, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v30, s3, v14, 0x3c0881c4 :: v_dual_lshlrev_b32 v21, 30, v21
	v_fmaak_f32 v36, s3, v28, 0x3c0881c4
	v_fmaak_f32 v33, s4, v17, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v34, v26, v34, 0xbe2aaa9d
	v_and_b32_e32 v21, 0x80000000, v21
	v_fmaak_f32 v30, v14, v30, 0xbe2aaa9d
	v_fmaak_f32 v36, v28, v36, 0xbe2aaa9d
	v_cmp_eq_u32_e32 vcc_lo, 0, v27
	v_dual_mul_f32 v34, v26, v34 :: v_dual_fmaak_f32 v37, s4, v28, 0xbab64f3b
	s_waitcnt vmcnt(10)
	v_fma_f32 v7, -v25, v7, v25
	v_fmaak_f32 v32, v17, v32, 0xbe2aaa9d
	v_fmaak_f32 v31, s4, v14, 0xbab64f3b
	v_dual_fmac_f32 v20, v20, v34 :: v_dual_and_b32 v19, 0x80000000, v19
	v_dual_mul_f32 v30, v14, v30 :: v_dual_and_b32 v23, 0x80000000, v23
	v_xor_b32_e32 v21, s1, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v32, v17, v32 :: v_dual_fmaak_f32 v31, v14, v31, 0x3d2aabf7
	v_fmac_f32_e32 v10, v10, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v23, s1, v23
	v_dual_fmac_f32 v8, v8, v32 :: v_dual_fmaak_f32 v31, v14, v31, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v14, v14, v31, 1.0
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v3, v3, v25
	v_dual_fmaak_f32 v35, s4, v26, 0xbab64f3b :: v_dual_mul_f32 v34, v28, v36
	v_fmaak_f32 v37, v28, v37, 0x3d2aabf7
	v_sub_f32_e32 v2, v2, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v35, v26, v35, 0x3d2aabf7
	v_fmac_f32_e32 v22, v22, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v35, v26, v35, 0xbf000004
	v_fma_f32 v26, v26, v35, 1.0
	v_fmaak_f32 v33, v17, v33, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v35, v28, v37, 0xbf000004 :: v_dual_cndmask_b32 v20, v26, v20
	v_fmaak_f32 v33, v17, v33, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v26, v28, v35, 1.0
	v_cmp_eq_u32_e32 vcc_lo, 0, v29
	v_and_b32_e32 v16, 0x80000000, v16
	v_xor_b32_e32 v20, v21, v20
	v_fma_f32 v17, v17, v33, 1.0
	v_cndmask_b32_e32 v21, v26, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v18, v23, v21
	v_cndmask_b32_e64 v8, -v8, v17, vcc_lo
	v_xor_b32_e32 v17, s2, v20
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, s2, v18
	v_xor_b32_e32 v8, v19, v8
	v_cndmask_b32_e64 v10, -v10, v14, vcc_lo
	v_cndmask_b32_e64 v14, 0x7fc00000, v17, s0
	v_add_co_u32 v0, vcc_lo, s18, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, 0x7fc00000, v8, s0
	v_xor_b32_e32 v10, v16, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v5, v5, v14
	v_cndmask_b32_e64 v14, 0x7fc00000, v15, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	v_cndmask_b32_e64 v10, 0x7fc00000, v10, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v9, v8, -v5
	v_dual_mul_f32 v8, v24, v14 :: v_dual_sub_f32 v5, v5, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, v11, v10 :: v_dual_fmac_f32 v7, v6, v5
	v_sub_f32_e32 v5, v8, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v4, v5
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v7, v12, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, v13, v3
	global_store_b32 v[0:1], v7, off
.LBB0_43:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 61
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi, .Lfunc_end0-_Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7692
; NumSgprs: 36
; NumVgprs: 61
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 61
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi
    .private_segment_fixed_size: 0
    .sgpr_count:     36
    .sgpr_spill_count: 0
    .symbol:         _Z10ftcsKernelPfS_S_S_S_S_S_S_S_fi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     61
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
