#include <stdio.h>
#include <stdlib.h>
#include <math.h>

#include "cuda_runtime.h"
#include "device_launch_parameters.h"



#define HEIGHT 960
#define WIDTH 1280

#define MASK_WIDTH 53
#define MASK_RADIUS (MASK_WIDTH/2)
#define BLOCK_SIZE 32

// gabor filter.
__global__ void convolution_kernel(float * input, float * output, int height, 
	int width, const float * __restrict__ Mask)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	float accum = 0.0;

	if (row < height && col < width)
	{
		for (int y = -MASK_RADIUS; y <= MASK_RADIUS;++y)
		{
			for (int x = -MASK_RADIUS; x <= MASK_RADIUS; ++x)
			{
				int xoffset = col + x;
				int yoffset = row + y;
				if (xoffset >= 0 && xoffset < WIDTH && yoffset >= 0 && yoffset < HEIGHT)
					accum += input[yoffset*WIDTH + xoffset]*Mask[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
			}
		
		}
		output[row*WIDTH + col] = accum;
	}


}

//	»ñÈ¡½Ø¶ÏÏàÎ»²î
__global__ void get_phase(float * ref, float * sce, const float * __restrict__ maskReal,
	const float * __restrict__ maskImage, float * phase)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;

	float ref_real = 0.0;
	float ref_image = 0.0;
	float sce_real = 0.0;
	float sce_image = 0.0;

	if (row < HEIGHT && col < WIDTH)
	{
		for (int y = -MASK_RADIUS; y <= MASK_RADIUS;++y)
		{
			for (int x = -MASK_RADIUS; x <= MASK_RADIUS; ++x)
			{
				int xoffset = col + x;
				int yoffset = row + y;
				if (xoffset >= 0 && xoffset < WIDTH && yoffset >= 0 && yoffset < HEIGHT)
				{
					ref_real += ref[yoffset*WIDTH + xoffset]*maskReal[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
					ref_image += ref[yoffset*WIDTH + xoffset]*maskImage[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
					sce_real += sce[yoffset*WIDTH + xoffset]*maskReal[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
					sce_image += sce[yoffset*WIDTH + xoffset]*maskImage[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
				}
					
			}
		
		}
		// sce - ref
		phase[row*WIDTH + col] = atan2(sce_image, sce_real) - atan2(ref_image, ref_real);
	}

}

//	´ÓÎÄ¼þÖÐµ¼ÈëÍ¼ÏñÊý¾Ý
void import_data(const char * inputFile, float * hostInput,
	int height, int width)
{
	FILE *input = fopen(inputFile, "r");

	for (int i = 0; i < height; ++i)
	{
		for (int j = 0; j < width; ++j)
		{
			fscanf(input, "%f ",&hostInput[i*width+j]);
		
		}
	
	}

	fclose(input);
}

int main()
{
	float * hostRef;	// ²Î¿¼Æ½Ãæ
	float * hostSce;	// ³¡¾°
	float * hostPhase;	// ½Ø¶ÏÏàÎ»
	float * hostMaskReal;// GaborºËÊµ²¿
	float * hostMaskImage;// GaborºËÐé²¿


	float * deviceRef;
	float * deviceSce;
	float * devicePhase;
	float * deviceMaskReal;
	float * deviceMaskImage;

	float time_elapsed = 0;	//¼ÇÂ¼GPU¼ÆËãµÄÊ±¼ä
	cudaError_t err = cudaSuccess; //GPU ×´Ì¬(¼ÇÂ¼ÄÚ´æ·ÖÅäÊÇ·ñ³É¹¦µÈµÈ)
	cudaEvent_t start, stop;

	//@@ allocate memory on CPU
	hostRef = (float *)malloc(HEIGHT*WIDTH*sizeof(float));
	hostSce = (float *)malloc(HEIGHT*WIDTH*sizeof(float));
	hostPhase = (float *)malloc(HEIGHT*WIDTH*sizeof(float));
	hostMaskReal = (float *)malloc(MASK_WIDTH*MASK_WIDTH*sizeof(float));
	hostMaskImage = (float *)malloc(MASK_WIDTH*MASK_WIDTH*sizeof(float));


	//@@ load image data and Gabor mask. 
	import_data("ref.txt", hostRef, HEIGHT, WIDTH);
	import_data("sce.txt", hostSce, HEIGHT, WIDTH);
	import_data("gabor_kernel_re.txt", hostMaskReal, MASK_WIDTH, MASK_WIDTH);
	import_data("gabor_kernel_im.txt", hostMaskImage, MASK_WIDTH, MASK_WIDTH);

	
	//@@ allocate memory on gpu
	err = cudaMalloc((void **)&deviceRef, HEIGHT*WIDTH*sizeof(float));
	if(err!=cudaSuccess)
    {
		perror("the cudaMalloc on GPU is failed");
		return 1;
    }
	err = cudaMalloc((void **)&deviceSce, HEIGHT*WIDTH*sizeof(float));
	if(err!=cudaSuccess)
    {
		perror("the cudaMalloc on GPU is failed");
		return 1;
    }
	err = cudaMalloc((void **)&devicePhase, HEIGHT*WIDTH*sizeof(float));
	if(err!=cudaSuccess)
    {
		perror("the cudaMalloc on GPU is failed");
		return 1;
    }
	err = cudaMalloc((void **)&deviceMaskReal, MASK_WIDTH*MASK_WIDTH*sizeof(float));
	if(err!=cudaSuccess)
    {
		perror("the cudaMalloc on GPU is failed");
		return 1;
    }
	err = cudaMalloc((void **)&deviceMaskImage, MASK_WIDTH*MASK_WIDTH*sizeof(float));
	if(err!=cudaSuccess)
    {
		perror("the cudaMalloc on GPU is failed");
		return 1;
    }


	//@@ copy data to device
	cudaMemcpy(deviceRef, hostRef, HEIGHT*WIDTH*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(deviceSce, hostSce, HEIGHT*WIDTH*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(deviceMaskReal, hostMaskReal, MASK_WIDTH*MASK_WIDTH*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(deviceMaskImage, hostMaskImage, MASK_WIDTH*MASK_WIDTH*sizeof(float), cudaMemcpyHostToDevice);


	cudaEventCreate(&start);    //´´½¨Event
    cudaEventCreate(&stop);


	//@@ launch the kernel

	dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
	dim3 dimGrid((WIDTH-1)/BLOCK_SIZE+1, (HEIGHT-1)/BLOCK_SIZE+1,1);

	cudaEventRecord(start, 0);
	/*convolution_kernel<<<dimGrid, dimBlock>>>(deviceInputImageData, deviceOutputImageData, HEIGHT, 
		WIDTH, deviceMaskData);*/
	get_phase<<<dimGrid, dimBlock>>>(deviceRef, deviceSce, deviceMaskReal,
		deviceMaskImage, devicePhase);

	cudaDeviceSynchronize();
	cudaEventRecord(stop, 0);

	cudaEventSynchronize(start);    //Waits for an event to complete.
	cudaEventSynchronize(stop);    //Waits for an event to complete.RecordÖ®Ç°µÄÈÎÎñ
    cudaEventElapsedTime(&time_elapsed,start,stop);    //¼ÆËãÊ±¼ä²î


	 printf("Ö´ÐÐÊ±¼ä£º%f(ms)\n",time_elapsed);


	 cudaMemcpy(hostPhase, devicePhase, HEIGHT*WIDTH*sizeof(float), cudaMemcpyDeviceToHost);

	 
	 FILE *outputImage = fopen("phase.txt", "w");

	 for (int i = 0; i < HEIGHT; ++i)
	 {
		 for (int j = 0; j < WIDTH; ++j)
		 {
			 fprintf(outputImage, j < WIDTH -1 ? "%f ":"%f\n", hostPhase[i*WIDTH + j]);
		 }
	 }

	 fclose(outputImage);

	

	cudaEventDestroy(start);    //destory the event
    cudaEventDestroy(stop);

	// free the memory on CPU and GPU.
	cudaFree(deviceRef);
	cudaFree(deviceSce);
	cudaFree(devicePhase);
	cudaFree(deviceMaskReal);
	cudaFree(deviceMaskImage);

	free(hostRef);
	free(hostSce);
	free(hostPhase);
	free(hostMaskReal);
	free(hostMaskImage);

	getchar();

	return 0;

}

	.file	"tmpxft_00394425_00000000-6_GaborKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"%f "
	.text
	.globl	_Z11import_dataPKcPfii
	.type	_Z11import_dataPKcPfii, @function
_Z11import_dataPKcPfii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	leaq	.LC0(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	fopen@PLT
	xorl	%r8d, %r8d
	movq	%rax, %rdi
.L3:
	cmpl	%r14d, %r8d
	jge	.L5
	movslq	%r15d, %rax
	xorl	%r12d, %r12d
	leaq	0(%r13,%rax,4), %rbx
.L6:
	cmpl	%ebp, %r12d
	jge	.L9
	movq	%rbx, %rdx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movq	%rdi, (%rsp)
	movl	%r8d, 12(%rsp)
	incl	%r12d
	addq	$4, %rbx
	call	__isoc23_fscanf@PLT
	movl	12(%rsp), %r8d
	movq	(%rsp), %rdi
	jmp	.L6
.L9:
	incl	%r8d
	addl	%ebp, %r15d
	jmp	.L3
.L5:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z11import_dataPKcPfii, .-_Z11import_dataPKcPfii
	.globl	_Z45__device_stub__Z18convolution_kernelPfS_iiPKfPfS_iiPKf
	.type	_Z45__device_stub__Z18convolution_kernelPfS_iiPKfPfS_iiPKf, @function
_Z45__device_stub__Z18convolution_kernelPfS_iiPKfPfS_iiPKf:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z18convolution_kernelPfS_iiPKf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L10:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z45__device_stub__Z18convolution_kernelPfS_iiPKfPfS_iiPKf, .-_Z45__device_stub__Z18convolution_kernelPfS_iiPKfPfS_iiPKf
	.globl	_Z18convolution_kernelPfS_iiPKf
	.type	_Z18convolution_kernelPfS_iiPKf, @function
_Z18convolution_kernelPfS_iiPKf:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18convolution_kernelPfS_iiPKfPfS_iiPKf
	.cfi_endproc
.LFE2054:
	.size	_Z18convolution_kernelPfS_iiPKf, .-_Z18convolution_kernelPfS_iiPKf
	.globl	_Z38__device_stub__Z9get_phasePfS_PKfS1_S_PfS_PKfS1_S_
	.type	_Z38__device_stub__Z9get_phasePfS_PKfS1_S_PfS_PKfS1_S_, @function
_Z38__device_stub__Z9get_phasePfS_PKfS1_S_PfS_PKfS1_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	76(%rsp), %rsi
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rcx, 40(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z9get_phasePfS_PKfS1_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L15:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z38__device_stub__Z9get_phasePfS_PKfS1_S_PfS_PKfS1_S_, .-_Z38__device_stub__Z9get_phasePfS_PKfS1_S_PfS_PKfS1_S_
	.globl	_Z9get_phasePfS_PKfS1_S_
	.type	_Z9get_phasePfS_PKfS1_S_, @function
_Z9get_phasePfS_PKfS1_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z9get_phasePfS_PKfS1_S_PfS_PKfS1_S_
	.cfi_endproc
.LFE2056:
	.size	_Z9get_phasePfS_PKfS1_S_, .-_Z9get_phasePfS_PKfS1_S_
	.section	.rodata.str1.1
.LC2:
	.string	"%f\n"
.LC4:
	.string	"ref.txt"
.LC5:
	.string	"sce.txt"
.LC6:
	.string	"gabor_kernel_re.txt"
.LC7:
	.string	"gabor_kernel_im.txt"
.LC8:
	.string	"the cudaMalloc on GPU is failed"
.LC9:
	.string	"\303\226\302\264\303\220\303\220\303\212\302\261\302\274\303\244\302\243\302\272%f(ms)\n"
.LC10:
	.string	"w"
.LC11:
	.string	"phase.txt"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$4915200, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 36(%rsp)
	call	malloc@PLT
	movl	$4915200, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$4915200, %edi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movl	$11236, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$11236, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movl	$1280, %ecx
	movq	%r14, %rsi
	movl	$960, %edx
	leaq	.LC4(%rip), %rdi
	movq	%rax, 16(%rsp)
	call	_Z11import_dataPKcPfii
	movq	(%rsp), %rsi
	movl	$1280, %ecx
	movl	$960, %edx
	leaq	.LC5(%rip), %rdi
	call	_Z11import_dataPKcPfii
	movq	8(%rsp), %rsi
	movl	$53, %ecx
	movl	$53, %edx
	leaq	.LC6(%rip), %rdi
	call	_Z11import_dataPKcPfii
	movq	16(%rsp), %rsi
	movl	$53, %ecx
	leaq	.LC7(%rip), %rdi
	movl	$53, %edx
	call	_Z11import_dataPKcPfii
	leaq	40(%rsp), %rdi
	movl	$4915200, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L21
.L23:
	leaq	.LC8(%rip), %rdi
	call	perror@PLT
	movl	$1, %eax
	jmp	.L20
.L21:
	leaq	48(%rsp), %rdi
	movl	$4915200, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L23
	leaq	56(%rsp), %rdi
	movl	$4915200, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L23
	leaq	64(%rsp), %rdi
	movl	$11236, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	jne	.L23
	leaq	72(%rsp), %rdi
	movl	$11236, %esi
	call	cudaMalloc@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L23
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movl	$4915200, %edx
	movq	%r14, %rsi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movl	$4915200, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movl	$11236, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movl	$11236, %edx
	call	cudaMemcpy@PLT
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	movabsq	$137438953504, %rax
	movq	%rax, 96(%rsp)
	movabsq	$128849018920, %rax
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	cudaEventRecord@PLT
	movl	104(%rsp), %ecx
	movl	116(%rsp), %esi
	xorl	%r9d, %r9d
	movq	96(%rsp), %rdx
	movq	108(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	56(%rsp), %r8
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z38__device_stub__Z9get_phasePfS_PKfS1_S_PfS_PKfS1_S_
.L24:
	call	cudaDeviceSynchronize@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	movq	%r12, %r13
	leaq	.LC2(%rip), %r15
	call	cudaEventRecord@PLT
	movq	80(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movl	$4915200, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC11(%rip), %rdi
	leaq	.LC10(%rip), %rsi
	call	fopen@PLT
	movq	%rax, %rdi
.L25:
	xorl	%ebp, %ebp
.L27:
	cmpq	$1279, %rbp
	leaq	.LC1(%rip), %rdx
	cvtss2sd	0(%r13,%rbp,4), %xmm0
	movb	$1, %al
	cmove	%r15, %rdx
	movl	$2, %esi
	incq	%rbp
	movq	%rdi, 24(%rsp)
	call	__fprintf_chk@PLT
	cmpq	$1280, %rbp
	movq	24(%rsp), %rdi
	jne	.L27
	addl	$1280, %ebx
	addq	$5120, %r13
	cmpl	$1228800, %ebx
	jne	.L25
	call	fclose@PLT
	movq	80(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	88(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	call	getchar@PLT
	xorl	%eax, %eax
.L20:
	movq	120(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC12:
	.string	"_Z9get_phasePfS_PKfS1_S_"
.LC13:
	.string	"_Z18convolution_kernelPfS_iiPKf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9get_phasePfS_PKfS1_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18convolution_kernelPfS_iiPKf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <math.h>

#include "hip/hip_runtime.h"




#define HEIGHT 960
#define WIDTH 1280

#define MASK_WIDTH 53
#define MASK_RADIUS (MASK_WIDTH/2)
#define BLOCK_SIZE 32

// gabor filter.
__global__ void convolution_kernel(float * input, float * output, int height, 
	int width, const float * __restrict__ Mask)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	float accum = 0.0;

	if (row < height && col < width)
	{
		for (int y = -MASK_RADIUS; y <= MASK_RADIUS;++y)
		{
			for (int x = -MASK_RADIUS; x <= MASK_RADIUS; ++x)
			{
				int xoffset = col + x;
				int yoffset = row + y;
				if (xoffset >= 0 && xoffset < WIDTH && yoffset >= 0 && yoffset < HEIGHT)
					accum += input[yoffset*WIDTH + xoffset]*Mask[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
			}
		
		}
		output[row*WIDTH + col] = accum;
	}


}

//	»ñÈ¡½Ø¶ÏÏàÎ»²î
__global__ void get_phase(float * ref, float * sce, const float * __restrict__ maskReal,
	const float * __restrict__ maskImage, float * phase)
{
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;

	float ref_real = 0.0;
	float ref_image = 0.0;
	float sce_real = 0.0;
	float sce_image = 0.0;

	if (row < HEIGHT && col < WIDTH)
	{
		for (int y = -MASK_RADIUS; y <= MASK_RADIUS;++y)
		{
			for (int x = -MASK_RADIUS; x <= MASK_RADIUS; ++x)
			{
				int xoffset = col + x;
				int yoffset = row + y;
				if (xoffset >= 0 && xoffset < WIDTH && yoffset >= 0 && yoffset < HEIGHT)
				{
					ref_real += ref[yoffset*WIDTH + xoffset]*maskReal[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
					ref_image += ref[yoffset*WIDTH + xoffset]*maskImage[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
					sce_real += sce[yoffset*WIDTH + xoffset]*maskReal[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
					sce_image += sce[yoffset*WIDTH + xoffset]*maskImage[(y+MASK_RADIUS)*MASK_WIDTH+x+MASK_RADIUS];
				}
					
			}
		
		}
		// sce - ref
		phase[row*WIDTH + col] = atan2(sce_image, sce_real) - atan2(ref_image, ref_real);
	}

}

//	´ÓÎÄ¼þÖÐµ¼ÈëÍ¼ÏñÊý¾Ý
void import_data(const char * inputFile, float * hostInput,
	int height, int width)
{
	FILE *input = fopen(inputFile, "r");

	for (int i = 0; i < height; ++i)
	{
		for (int j = 0; j < width; ++j)
		{
			fscanf(input, "%f ",&hostInput[i*width+j]);
		
		}
	
	}

	fclose(input);
}

int main()
{
	float * hostRef;	// ²Î¿¼Æ½Ãæ
	float * hostSce;	// ³¡¾°
	float * hostPhase;	// ½Ø¶ÏÏàÎ»
	float * hostMaskReal;// GaborºËÊµ²¿
	float * hostMaskImage;// GaborºËÐé²¿


	float * deviceRef;
	float * deviceSce;
	float * devicePhase;
	float * deviceMaskReal;
	float * deviceMaskImage;

	float time_elapsed = 0;	//¼ÇÂ¼GPU¼ÆËãµÄÊ±¼ä
	hipError_t err = hipSuccess; //GPU ×´Ì¬(¼ÇÂ¼ÄÚ´æ·ÖÅäÊÇ·ñ³É¹¦µÈµÈ)
	hipEvent_t start, stop;

	//@@ allocate memory on CPU
	hostRef = (float *)malloc(HEIGHT*WIDTH*sizeof(float));
	hostSce = (float *)malloc(HEIGHT*WIDTH*sizeof(float));
	hostPhase = (float *)malloc(HEIGHT*WIDTH*sizeof(float));
	hostMaskReal = (float *)malloc(MASK_WIDTH*MASK_WIDTH*sizeof(float));
	hostMaskImage = (float *)malloc(MASK_WIDTH*MASK_WIDTH*sizeof(float));


	//@@ load image data and Gabor mask. 
	import_data("ref.txt", hostRef, HEIGHT, WIDTH);
	import_data("sce.txt", hostSce, HEIGHT, WIDTH);
	import_data("gabor_kernel_re.txt", hostMaskReal, MASK_WIDTH, MASK_WIDTH);
	import_data("gabor_kernel_im.txt", hostMaskImage, MASK_WIDTH, MASK_WIDTH);

	
	//@@ allocate memory on gpu
	err = hipMalloc((void **)&deviceRef, HEIGHT*WIDTH*sizeof(float));
	if(err!=hipSuccess)
    {
		perror("the hipMalloc on GPU is failed");
		return 1;
    }
	err = hipMalloc((void **)&deviceSce, HEIGHT*WIDTH*sizeof(float));
	if(err!=hipSuccess)
    {
		perror("the hipMalloc on GPU is failed");
		return 1;
    }
	err = hipMalloc((void **)&devicePhase, HEIGHT*WIDTH*sizeof(float));
	if(err!=hipSuccess)
    {
		perror("the hipMalloc on GPU is failed");
		return 1;
    }
	err = hipMalloc((void **)&deviceMaskReal, MASK_WIDTH*MASK_WIDTH*sizeof(float));
	if(err!=hipSuccess)
    {
		perror("the hipMalloc on GPU is failed");
		return 1;
    }
	err = hipMalloc((void **)&deviceMaskImage, MASK_WIDTH*MASK_WIDTH*sizeof(float));
	if(err!=hipSuccess)
    {
		perror("the hipMalloc on GPU is failed");
		return 1;
    }


	//@@ copy data to device
	hipMemcpy(deviceRef, hostRef, HEIGHT*WIDTH*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(deviceSce, hostSce, HEIGHT*WIDTH*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(deviceMaskReal, hostMaskReal, MASK_WIDTH*MASK_WIDTH*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(deviceMaskImage, hostMaskImage, MASK_WIDTH*MASK_WIDTH*sizeof(float), hipMemcpyHostToDevice);


	hipEventCreate(&start);    //´´½¨Event
    hipEventCreate(&stop);


	//@@ launch the kernel

	dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
	dim3 dimGrid((WIDTH-1)/BLOCK_SIZE+1, (HEIGHT-1)/BLOCK_SIZE+1,1);

	hipEventRecord(start, 0);
	/*convolution_kernel<<<dimGrid, dimBlock>>>(deviceInputImageData, deviceOutputImageData, HEIGHT, 
		WIDTH, deviceMaskData);*/
	get_phase<<<dimGrid, dimBlock>>>(deviceRef, deviceSce, deviceMaskReal,
		deviceMaskImage, devicePhase);

	hipDeviceSynchronize();
	hipEventRecord(stop, 0);

	hipEventSynchronize(start);    //Waits for an event to complete.
	hipEventSynchronize(stop);    //Waits for an event to complete.RecordÖ®Ç°µÄÈÎÎñ
    hipEventElapsedTime(&time_elapsed,start,stop);    //¼ÆËãÊ±¼ä²î


	 printf("Ö´ÐÐÊ±¼ä£º%f(ms)\n",time_elapsed);


	 hipMemcpy(hostPhase, devicePhase, HEIGHT*WIDTH*sizeof(float), hipMemcpyDeviceToHost);

	 
	 FILE *outputImage = fopen("phase.txt", "w");

	 for (int i = 0; i < HEIGHT; ++i)
	 {
		 for (int j = 0; j < WIDTH; ++j)
		 {
			 fprintf(outputImage, j < WIDTH -1 ? "%f ":"%f\n", hostPhase[i*WIDTH + j]);
		 }
	 }

	 fclose(outputImage);

	

	hipEventDestroy(start);    //destory the event
    hipEventDestroy(stop);

	// free the memory on CPU and GPU.
	hipFree(deviceRef);
	hipFree(deviceSce);
	hipFree(devicePhase);
	hipFree(deviceMaskReal);
	hipFree(deviceMaskImage);

	free(hostRef);
	free(hostSce);
	free(hostPhase);
	free(hostMaskReal);
	free(hostMaskImage);

	getchar();

	return 0;

}

	.text
	.file	"GaborKernel.hip"
	.globl	_Z33__device_stub__convolution_kernelPfS_iiPKf # -- Begin function _Z33__device_stub__convolution_kernelPfS_iiPKf
	.type	_Z33__device_stub__convolution_kernelPfS_iiPKf,@function
_Z33__device_stub__convolution_kernelPfS_iiPKf: # @_Z33__device_stub__convolution_kernelPfS_iiPKf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convolution_kernelPfS_iiPKf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convolution_kernelPfS_iiPKf, .Lfunc_end0-_Z33__device_stub__convolution_kernelPfS_iiPKf
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__get_phasePfS_PKfS1_S_ # -- Begin function _Z24__device_stub__get_phasePfS_PKfS1_S_
	.type	_Z24__device_stub__get_phasePfS_PKfS1_S_,@function
_Z24__device_stub__get_phasePfS_PKfS1_S_: # @_Z24__device_stub__get_phasePfS_PKfS1_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9get_phasePfS_PKfS1_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__get_phasePfS_PKfS1_S_, .Lfunc_end1-_Z24__device_stub__get_phasePfS_PKfS1_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11import_dataPKcPfii          # -- Begin function _Z11import_dataPKcPfii
	.type	_Z11import_dataPKcPfii,@function
_Z11import_dataPKcPfii:                 # @_Z11import_dataPKcPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movq	%rsi, 8(%rsp)                   # 8-byte Spill
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %r15
	testl	%ebp, %ebp
	jle	.LBB2_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%ebp, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%ebx, %eax
	movq	%rax, (%rsp)                    # 8-byte Spill
	xorl	%r14d, %r14d
	xorl	%ebp, %ebp
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB2_5
# %bb.3:                                #   in Loop: Header=BB2_2 Depth=1
	movl	%r14d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %r12
	movq	(%rsp), %r13                    # 8-byte Reload
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r12
	decq	%r13
	jne	.LBB2_4
.LBB2_5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%rbp
	addl	%ebx, %r14d
	cmpq	16(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB2_2
.LBB2_6:                                # %._crit_edge16
	movq	%r15, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end2:
	.size	_Z11import_dataPKcPfii, .Lfunc_end2-_Z11import_dataPKcPfii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$0, 68(%rsp)
	movl	$4915200, %edi                  # imm = 0x4B0000
	callq	malloc
	movq	%rax, %rbx
	movl	$4915200, %edi                  # imm = 0x4B0000
	callq	malloc
	movq	%rax, %r14
	movl	$4915200, %edi                  # imm = 0x4B0000
	callq	malloc
	movq	%rax, %r12
	movl	$11236, %edi                    # imm = 0x2BE4
	callq	malloc
	movq	%rax, %r15
	movl	$11236, %edi                    # imm = 0x2BE4
	callq	malloc
	movq	%rax, %r13
	movl	$.L.str.2, %edi
	movq	%rbx, %rsi
	movl	$960, %edx                      # imm = 0x3C0
	movl	$1280, %ecx                     # imm = 0x500
	callq	_Z11import_dataPKcPfii
	movl	$.L.str.3, %edi
	movq	%r14, %rsi
	movl	$960, %edx                      # imm = 0x3C0
	movl	$1280, %ecx                     # imm = 0x500
	callq	_Z11import_dataPKcPfii
	movl	$.L.str.4, %edi
	movq	%r15, %rsi
	movl	$53, %edx
	movl	$53, %ecx
	callq	_Z11import_dataPKcPfii
	movl	$.L.str.5, %edi
	movq	%r13, %rsi
	movl	$53, %edx
	movl	$53, %ecx
	callq	_Z11import_dataPKcPfii
	leaq	56(%rsp), %rdi
	movl	$4915200, %esi                  # imm = 0x4B0000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.2:
	leaq	48(%rsp), %rdi
	movl	$4915200, %esi                  # imm = 0x4B0000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.3:
	leaq	40(%rsp), %rdi
	movl	$4915200, %esi                  # imm = 0x4B0000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.4:
	leaq	32(%rsp), %rdi
	movl	$11236, %esi                    # imm = 0x2BE4
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.5:
	leaq	24(%rsp), %rdi
	movl	$11236, %esi                    # imm = 0x2BE4
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.6:
	movq	56(%rsp), %rdi
	movl	$4915200, %edx                  # imm = 0x4B0000
	movq	%rbx, 96(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rdi
	movl	$4915200, %edx                  # imm = 0x4B0000
	movq	%r14, 88(%rsp)                  # 8-byte Spill
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$11236, %edx                    # imm = 0x2BE4
	movq	%r15, 80(%rsp)                  # 8-byte Spill
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$11236, %edx                    # imm = 0x2BE4
	movq	%r13, 72(%rsp)                  # 8-byte Spill
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$128849018920, %rdi             # imm = 0x1E00000028
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	40(%rsp), %r8
	callq	_Z24__device_stub__get_phasePfS_PKfS1_S_
.LBB3_8:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	68(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbp), %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	movq	40(%rsp), %rsi
	movl	$4915200, %edx                  # imm = 0x4B0000
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.8, %edi
	movl	$.L.str.9, %esi
	callq	fopen
	movq	%rax, %rbp
	movl	$.L.str.10, %ebx
	movq	%r12, %r13
	movq	%r12, %r14
.LBB3_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_10 Depth 2
	movq	$-1280, %rax                    # imm = 0xFB00
	movq	$-1280, %r12                    # imm = 0xFB00
.LBB3_10:                               #   Parent Loop BB3_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	incq	%r12
	movl	$.L.str.1, %esi
	cmoveq	%rbx, %rsi
	xorps	%xmm0, %xmm0
	cvtss2sd	5120(%r14,%rax,4), %xmm0
	movq	%rbp, %rdi
	movb	$1, %al
	callq	fprintf
	movq	%r12, %rax
	testq	%r12, %r12
	jne	.LBB3_10
# %bb.11:                               #   in Loop: Header=BB3_9 Depth=1
	incq	%r15
	addq	$5120, %r14                     # imm = 0x1400
	cmpq	$960, %r15                      # imm = 0x3C0
	jne	.LBB3_9
# %bb.12:
	movq	%rbp, %rdi
	callq	fclose
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	88(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	80(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	72(%rsp), %rdi                  # 8-byte Reload
	callq	free
	callq	getchar
	xorl	%eax, %eax
	jmp	.LBB3_13
.LBB3_1:
	movl	$.L.str.6, %edi
	callq	perror
	movl	$1, %eax
.LBB3_13:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convolution_kernelPfS_iiPKf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9get_phasePfS_PKfS1_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convolution_kernelPfS_iiPKf,@object # @_Z18convolution_kernelPfS_iiPKf
	.section	.rodata,"a",@progbits
	.globl	_Z18convolution_kernelPfS_iiPKf
	.p2align	3, 0x0
_Z18convolution_kernelPfS_iiPKf:
	.quad	_Z33__device_stub__convolution_kernelPfS_iiPKf
	.size	_Z18convolution_kernelPfS_iiPKf, 8

	.type	_Z9get_phasePfS_PKfS1_S_,@object # @_Z9get_phasePfS_PKfS1_S_
	.globl	_Z9get_phasePfS_PKfS1_S_
	.p2align	3, 0x0
_Z9get_phasePfS_PKfS1_S_:
	.quad	_Z24__device_stub__get_phasePfS_PKfS1_S_
	.size	_Z9get_phasePfS_PKfS1_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%f "
	.size	.L.str.1, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"ref.txt"
	.size	.L.str.2, 8

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"sce.txt"
	.size	.L.str.3, 8

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"gabor_kernel_re.txt"
	.size	.L.str.4, 20

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"gabor_kernel_im.txt"
	.size	.L.str.5, 20

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"the hipMalloc on GPU is failed"
	.size	.L.str.6, 31

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\303\226\302\264\303\220\303\220\303\212\302\261\302\274\303\244\302\243\302\272%f(ms)\n"
	.size	.L.str.7, 28

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"phase.txt"
	.size	.L.str.8, 10

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"w"
	.size	.L.str.9, 2

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"%f\n"
	.size	.L.str.10, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convolution_kernelPfS_iiPKf"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9get_phasePfS_PKfS1_S_"
	.size	.L__unnamed_2, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convolution_kernelPfS_iiPKf
	.addrsig_sym _Z24__device_stub__get_phasePfS_PKfS1_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convolution_kernelPfS_iiPKf
	.addrsig_sym _Z9get_phasePfS_PKfS1_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convolution_kernelPfS_iiPKf ; -- Begin function _Z18convolution_kernelPfS_iiPKf
	.globl	_Z18convolution_kernelPfS_iiPKf
	.p2align	8
	.type	_Z18convolution_kernelPfS_iiPKf,@function
_Z18convolution_kernelPfS_iiPKf:        ; @_Z18convolution_kernelPfS_iiPKf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s8, s15, s5
	s_mul_i32 s14, s14, s4
	v_add_nc_u32_e32 v3, s8, v1
	v_add_nc_u32_e32 v0, s14, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	v_cmp_gt_i32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_8
; %bb.1:                                ; %.preheader42
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mulk_i32 s8, 0x500
	v_mul_u32_u24_e32 v1, 0x500, v1
	v_add3_u32 v2, s14, s8, v2
	v_subrev_nc_u32_e32 v5, 26, v0
	v_mov_b32_e32 v4, 0
	s_movk_i32 s10, 0xffe6
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v6, v2, v1, 0xffff7de6
	v_mov_b32_e32 v2, 0
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	v_add_nc_u32_e32 v1, s10, v3
	s_mov_b32 s11, 0
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[8:9], s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	v_cmp_gt_i32_e64 s0, 0x3c0, v1
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v1, s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s1, 0x500, v1
	s_and_b32 s1, s1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s1
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	v_add_nc_u32_e32 v1, s11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_add_co_u32 v7, s1, s4, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s1, s5, v8, s1
	s_load_b32 s1, s[8:9], 0x0
	global_load_b32 v1, v[7:8], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v4, s1, v1
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s11, s11, 1
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s11, 53
	s_cbranch_scc0 .LBB0_3
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s10, s10, 1
	v_add_nc_u32_e32 v6, 0x500, v6
	s_add_u32 s2, s2, 0xd4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s10, 27
	s_cbranch_scc0 .LBB0_2
; %bb.7:
	v_mad_u64_u32 v[1:2], null, 0x500, v3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convolution_kernelPfS_iiPKf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convolution_kernelPfS_iiPKf, .Lfunc_end0-_Z18convolution_kernelPfS_iiPKf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9get_phasePfS_PKfS1_S_ ; -- Begin function _Z9get_phasePfS_PKfS1_S_
	.globl	_Z9get_phasePfS_PKfS1_S_
	.p2align	8
	.type	_Z9get_phasePfS_PKfS1_S_,@function
_Z9get_phasePfS_PKfS1_S_:               ; @_Z9get_phasePfS_PKfS1_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0x3c0, v2
	v_cmp_gt_i32_e64 s2, 0x500, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_8
; %bb.1:                                ; %.preheader.preheader
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mul_lo_u32 v1, 0x500, v2
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	s_movk_i32 s14, 0xffe6
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v9, 0xffff7de6, v1
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	v_dual_mov_b32 v10, v0 :: v_dual_add_nc_u32 v3, s14, v2
	s_mov_b64 s[12:13], 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v3
	v_cmp_gt_i32_e64 s2, 0x3c0, v3
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v3, 26, v10
	v_cmp_gt_u32_e64 s3, 0x500, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, s3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s15, s3
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=2
	v_add_nc_u32_e32 v3, v9, v10
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s8, s12
	s_addc_u32 s17, s9, s13
	s_add_u32 s18, s10, s12
	s_addc_u32 s19, s11, s13
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s3, s4, v11
	v_add_co_ci_u32_e64 v14, s3, s5, v12, s3
	v_add_co_u32 v11, s3, s6, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
	global_load_b32 v3, v[13:14], off
	global_load_b32 v11, v[11:12], off
	s_load_b32 s3, s[16:17], 0x0
	s_load_b32 s16, s[18:19], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v5, s3, v3
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, s3, v11
	v_fmac_f32_e32 v6, s16, v3
	v_fmac_f32_e32 v7, s16, v11
.LBB1_5:                                ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	v_add_nc_u32_e32 v10, 1, v10
	s_add_u32 s12, s12, 4
	s_addc_u32 s13, s13, 0
	s_cmpk_eq_i32 s12, 0xd4
	s_cbranch_scc0 .LBB1_3
; %bb.6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s14, s14, 1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s8, s8, 0xd4
	v_add_nc_u32_e32 v9, 0x500, v9
	s_addc_u32 s9, s9, 0
	s_add_u32 s10, s10, 0xd4
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s14, 27
	s_cbranch_scc0 .LBB1_2
; %bb.7:
	v_max_f32_e64 v2, |v7|, |v7|
	v_max_f32_e64 v3, |v8|, |v8|
	v_max_f32_e64 v4, |v6|, |v6|
	v_max_f32_e64 v9, |v5|, |v5|
	s_mov_b32 s2, 0x3b2d2a58
	v_cmp_gt_i32_e32 vcc_lo, 0, v8
	v_max_f32_e32 v10, v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_min_f32 v2, v3, v2 :: v_dual_min_f32 v3, v9, v4
	v_max_f32_e32 v11, v9, v4
	v_cmp_class_f32_e64 s3, v8, 0x204
	v_frexp_mant_f32_e32 v12, v10
	v_frexp_exp_i32_f32_e32 v4, v10
	v_cmp_class_f32_e64 s4, v7, 0x204
	v_frexp_mant_f32_e32 v13, v11
	v_frexp_exp_i32_f32_e32 v11, v11
	v_rcp_f32_e32 v9, v12
	v_frexp_exp_i32_f32_e32 v12, v2
	v_frexp_mant_f32_e32 v2, v2
	v_rcp_f32_e32 v10, v13
	v_frexp_exp_i32_f32_e32 v13, v3
	v_frexp_mant_f32_e32 v3, v3
	v_sub_nc_u32_e32 v4, v12, v4
	v_cmp_class_f32_e64 s5, v5, 0x204
	v_cmp_class_f32_e64 s6, v6, 0x204
	v_sub_nc_u32_e32 v11, v13, v11
	v_mul_f32_e32 v2, v2, v9
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v3, v3, v10 :: v_dual_add_nc_u32 v0, v1, v0
	v_ldexp_f32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ldexp_f32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v4, v2, v2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v3, v3 :: v_dual_fmaak_f32 v10, s2, v4, 0xbc7a590c
	v_fmaak_f32 v11, s2, v9, 0xbc7a590c
	v_cmp_gt_f32_e64 s2, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v10, v4, v10, 0x3d29fb3f :: v_dual_fmaak_f32 v11, v9, v11, 0x3d29fb3f
	v_dual_fmaak_f32 v10, v4, v10, 0xbd97d4d7 :: v_dual_fmaak_f32 v11, v9, v11, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v10, v4, v10, 0x3dd931b2 :: v_dual_fmaak_f32 v11, v9, v11, 0x3dd931b2
	v_dual_fmaak_f32 v10, v4, v10, 0xbe1160e6 :: v_dual_fmaak_f32 v11, v9, v11, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v10, v4, v10, 0x3e4cb8bf :: v_dual_fmaak_f32 v11, v9, v11, 0x3e4cb8bf
	v_dual_fmaak_f32 v10, v4, v10, 0xbeaaaa62 :: v_dual_fmaak_f32 v11, v9, v11, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v4, v10 :: v_dual_mul_f32 v9, v9, v11
	v_fmac_f32_e32 v2, v2, v4
	v_cndmask_b32_e64 v4, 0, 0x40490fdb, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, |v7|, |v8|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v3, v3, v9 :: v_dual_sub_f32 v10, 0x3fc90fdb, v2
	v_sub_f32_e32 v11, 0x3fc90fdb, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v9, 0x4016cbe4 :: v_dual_cndmask_b32 v2, v2, v10
	v_cmp_gt_f32_e64 vcc_lo, |v6|, |v5|
	v_cndmask_b32_e32 v3, v3, v11, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, 0x40490fdb, v2
	v_cndmask_b32_e64 v10, 0, 0x40490fdb, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v2, v2, v11, vcc_lo
	v_cndmask_b32_e32 v11, 0x3f490fdb, v9, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v9, 0x3f490fdb, v9, s2
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_sub_f32_e32 v12, 0x40490fdb, v3
	v_cmp_eq_f32_e32 vcc_lo, 0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v12, s2
	v_cndmask_b32_e32 v3, v3, v10, vcc_lo
	s_and_b32 vcc_lo, s3, s4
	v_cndmask_b32_e32 v2, v2, v11, vcc_lo
	s_and_b32 vcc_lo, s6, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v8, v7
	v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_bfi_b32 v2, 0x7fffffff, v2, v7
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_bfi_b32 v3, 0x7fffffff, v3, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB1_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9get_phasePfS_PKfS1_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9get_phasePfS_PKfS1_S_, .Lfunc_end1-_Z9get_phasePfS_PKfS1_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1072
; NumSgprs: 22
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convolution_kernelPfS_iiPKf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18convolution_kernelPfS_iiPKf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
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    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
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    .max_flat_workgroup_size: 1024
    .name:           _Z9get_phasePfS_PKfS1_S_
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    .sgpr_spill_count: 0
    .symbol:         _Z9get_phasePfS_PKfS1_S_.kd
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
