//nvcc -ptx EM6.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double *r,
                     double *z,
                     double * a,
                     double * b,
                     int * parDelete,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz) {
    int globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
    int localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
    int threadsPerBlock = blockDim.x*blockDim.y;
    int n = localThreadIdx + globalBlockIndex*threadsPerBlock;
    if ( n >= parNum ){
        return;
    }
    double r0 = r[n];
    double z0 = z[n];
    int ar,az,a1,a2,a3,a4;
    double b1,b2,b3,b4;
    
    ar = floor(r0/dr-0.5);
    az = floor(z0/dz-0.5);
    if (ar<0){
        if (az<0){
            a1 = 1;
            a2 = 1;
            a3 = 1;
            a4 = (ar+1) + (az+1) * gridR + 1;

            b1 = 0;
            b2 = 0;
            b3 = 0;
            b4 = 1;
        }
        else if (az>=gridZ-1){
            a1 = 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = 1;
            a4 = 1;

            b1 = 0;
            b2 = 1;
            b3 = 0;
            b4 = 0;
        }
        else{
            a1 = 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = 1;
            a4 = (ar+1) + (az+1) * gridR + 1;
        
            b1 = 0;
            b2 = ((az+1.5)*dz-z0)/(dz);
            b3 = 0;
            b4 = (z0-(az+0.5)*dz)/(dz);  
        }
    }
    else if (ar>=gridR-1){
        if( az<0 ){
            a1 = 1;
            a2 = 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = 1;

            b1 = 0;
            b2 = 0;
            b3 = 1;
            b4 = 0;
        }
        else if (az>=gridZ-1){
            a1 = ar + az * gridR + 1;
            a2 = 1;
            a3 = 1;
            a4 = 1;

            b1 = 1;
            b2 = 0;
            b3 = 0;
            b4 = 0;
        }
        else{
            a1 = ar + az * gridR + 1;
            a2 = 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = 1;
    
            b1 = ((az+1.5)*dz-z0)/(dz);
            b2 = 0;
            b3 = (z0-(az+0.5)*dz)/(dz);
            b4 = 0;    
        }
    }
    else{
        if( az<0 ){
            a1 = 1;
            a2 = 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = (ar+1) + (az+1) * gridR + 1;

            b1 = 0;
            b2 = 0;
            b3 = ((ar+1.5)*dr-r0)/(dr);
            b4 = (r0-(ar+0.5)*dr)/(dr);   
        }
        else if (az>=gridZ-1){
            a1 = ar + az * gridR + 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = 1;
            a4 = 1;

            b1 = ((ar+1.5)*dr-r0)/(dr);
            b2 = (r0-(ar+0.5)*dr)/(dr);  
            b3 = 0;
            b4 = 0;
        }
        else{
            a1 = ar + az * gridR + 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = (ar+1) + (az+1) * gridR + 1;
    
            b1 = ((ar+1.5)*dr-r0)*((az+1.5)*dz-z0)/(dr*dz);
            b2 = (r0-(ar+0.5)*dr)*((az+1.5)*dz-z0)/(dr*dz);
            b3 = ((ar+1.5)*dr-r0)*(z0-(az+0.5)*dz)/(dr*dz);
            b4 = (r0-(ar+0.5)*dr)*(z0-(az+0.5)*dz)/(dr*dz);    
        }
    }
    if (parDelete[n]==1){
        a1 = 1;
        a2 = 1;
        a3 = 1;
        a4 = 1;

        b1 = 0;
        b2 = 0;
        b3 = 0;
        b4 = 0;
    }

    a[n] = a1;
    a[n+parNum] = a2;
    a[n+2*parNum] = a3;
    a[n+3*parNum] = a4;

    b[n] = b1;
    b[n+parNum] = b2;
    b[n+2*parNum] = b3;
    b[n+3*parNum] = b4;
    
}


__global__ void processMandelbrotElement( 
                     double *r,
                     double *z,
                     double * a,
                     double * b,
                     int * parDelete,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz) {
        EM1(r, z, a, b, parDelete, parNum, gridR, gridZ, dr, dz);
}

	.file	"tmpxft_00228bf4_00000000-6_EM6.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z3EM1PdS_S_S_Piiiidd
	.type	_Z3EM1PdS_S_S_Piiiidd, @function
_Z3EM1PdS_S_S_Piiiidd:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z3EM1PdS_S_S_Piiiidd, .-_Z3EM1PdS_S_S_Piiiidd
	.globl	_Z57__device_stub__Z24processMandelbrotElementPdS_S_S_PiiiiddPdS_S_S_Piiiidd
	.type	_Z57__device_stub__Z24processMandelbrotElementPdS_S_S_PiiiiddPdS_S_S_Piiiidd, @function
_Z57__device_stub__Z24processMandelbrotElementPdS_S_S_PiiiiddPdS_S_S_Piiiidd:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movsd	%xmm0, 8(%rsp)
	movsd	%xmm1, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z24processMandelbrotElementPdS_S_S_Piiiidd(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L4:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z57__device_stub__Z24processMandelbrotElementPdS_S_S_PiiiiddPdS_S_S_Piiiidd, .-_Z57__device_stub__Z24processMandelbrotElementPdS_S_S_PiiiiddPdS_S_S_Piiiidd
	.globl	_Z24processMandelbrotElementPdS_S_S_Piiiidd
	.type	_Z24processMandelbrotElementPdS_S_S_Piiiidd, @function
_Z24processMandelbrotElementPdS_S_S_Piiiidd:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z24processMandelbrotElementPdS_S_S_PiiiiddPdS_S_S_Piiiidd
	.cfi_endproc
.LFE2034:
	.size	_Z24processMandelbrotElementPdS_S_S_Piiiidd, .-_Z24processMandelbrotElementPdS_S_S_Piiiidd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24processMandelbrotElementPdS_S_S_Piiiidd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24processMandelbrotElementPdS_S_S_Piiiidd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//nvcc -ptx EM6.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double *r,
                     double *z,
                     double * a,
                     double * b,
                     int * parDelete,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz) {
    int globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
    int localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
    int threadsPerBlock = blockDim.x*blockDim.y;
    int n = localThreadIdx + globalBlockIndex*threadsPerBlock;
    if ( n >= parNum ){
        return;
    }
    double r0 = r[n];
    double z0 = z[n];
    int ar,az,a1,a2,a3,a4;
    double b1,b2,b3,b4;
    
    ar = floor(r0/dr-0.5);
    az = floor(z0/dz-0.5);
    if (ar<0){
        if (az<0){
            a1 = 1;
            a2 = 1;
            a3 = 1;
            a4 = (ar+1) + (az+1) * gridR + 1;

            b1 = 0;
            b2 = 0;
            b3 = 0;
            b4 = 1;
        }
        else if (az>=gridZ-1){
            a1 = 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = 1;
            a4 = 1;

            b1 = 0;
            b2 = 1;
            b3 = 0;
            b4 = 0;
        }
        else{
            a1 = 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = 1;
            a4 = (ar+1) + (az+1) * gridR + 1;
        
            b1 = 0;
            b2 = ((az+1.5)*dz-z0)/(dz);
            b3 = 0;
            b4 = (z0-(az+0.5)*dz)/(dz);  
        }
    }
    else if (ar>=gridR-1){
        if( az<0 ){
            a1 = 1;
            a2 = 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = 1;

            b1 = 0;
            b2 = 0;
            b3 = 1;
            b4 = 0;
        }
        else if (az>=gridZ-1){
            a1 = ar + az * gridR + 1;
            a2 = 1;
            a3 = 1;
            a4 = 1;

            b1 = 1;
            b2 = 0;
            b3 = 0;
            b4 = 0;
        }
        else{
            a1 = ar + az * gridR + 1;
            a2 = 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = 1;
    
            b1 = ((az+1.5)*dz-z0)/(dz);
            b2 = 0;
            b3 = (z0-(az+0.5)*dz)/(dz);
            b4 = 0;    
        }
    }
    else{
        if( az<0 ){
            a1 = 1;
            a2 = 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = (ar+1) + (az+1) * gridR + 1;

            b1 = 0;
            b2 = 0;
            b3 = ((ar+1.5)*dr-r0)/(dr);
            b4 = (r0-(ar+0.5)*dr)/(dr);   
        }
        else if (az>=gridZ-1){
            a1 = ar + az * gridR + 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = 1;
            a4 = 1;

            b1 = ((ar+1.5)*dr-r0)/(dr);
            b2 = (r0-(ar+0.5)*dr)/(dr);  
            b3 = 0;
            b4 = 0;
        }
        else{
            a1 = ar + az * gridR + 1;
            a2 = (ar+1) + az * gridR + 1;
            a3 = ar + (az+1) * gridR + 1;
            a4 = (ar+1) + (az+1) * gridR + 1;
    
            b1 = ((ar+1.5)*dr-r0)*((az+1.5)*dz-z0)/(dr*dz);
            b2 = (r0-(ar+0.5)*dr)*((az+1.5)*dz-z0)/(dr*dz);
            b3 = ((ar+1.5)*dr-r0)*(z0-(az+0.5)*dz)/(dr*dz);
            b4 = (r0-(ar+0.5)*dr)*(z0-(az+0.5)*dz)/(dr*dz);    
        }
    }
    if (parDelete[n]==1){
        a1 = 1;
        a2 = 1;
        a3 = 1;
        a4 = 1;

        b1 = 0;
        b2 = 0;
        b3 = 0;
        b4 = 0;
    }

    a[n] = a1;
    a[n+parNum] = a2;
    a[n+2*parNum] = a3;
    a[n+3*parNum] = a4;

    b[n] = b1;
    b[n+parNum] = b2;
    b[n+2*parNum] = b3;
    b[n+3*parNum] = b4;
    
}


__global__ void processMandelbrotElement( 
                     double *r,
                     double *z,
                     double * a,
                     double * b,
                     int * parDelete,
                     const int parNum,
                     const int gridR,
                     const int gridZ,
                     const double dr,
                     const double dz) {
        EM1(r, z, a, b, parDelete, parNum, gridR, gridZ, dr, dz);
}

	.text
	.file	"EM6.hip"
	.globl	_Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd # -- Begin function _Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd
	.type	_Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd,@function
_Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd: # @_Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	24(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r10, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24processMandelbrotElementPdS_S_S_Piiiidd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd, .Lfunc_end0-_Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24processMandelbrotElementPdS_S_S_Piiiidd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24processMandelbrotElementPdS_S_S_Piiiidd,@object # @_Z24processMandelbrotElementPdS_S_S_Piiiidd
	.section	.rodata,"a",@progbits
	.globl	_Z24processMandelbrotElementPdS_S_S_Piiiidd
	.p2align	3, 0x0
_Z24processMandelbrotElementPdS_S_S_Piiiidd:
	.quad	_Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd
	.size	_Z24processMandelbrotElementPdS_S_S_Piiiidd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24processMandelbrotElementPdS_S_S_Piiiidd"
	.size	.L__unnamed_1, 44

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__processMandelbrotElementPdS_S_S_Piiiidd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24processMandelbrotElementPdS_S_S_Piiiidd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24processMandelbrotElementPdS_S_S_Piiiidd ; -- Begin function _Z24processMandelbrotElementPdS_S_S_Piiiidd
	.globl	_Z24processMandelbrotElementPdS_S_S_Piiiidd
	.p2align	8
	.type	_Z24processMandelbrotElementPdS_S_S_Piiiidd,@function
_Z24processMandelbrotElementPdS_S_S_Piiiidd: ; @_Z24processMandelbrotElementPdS_S_S_Piiiidd
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x48
	s_load_b32 s5, s[0:1], 0x54
	s_add_u32 s2, s0, 0x48
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s6, s4, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s6, s14
	s_cmp_lt_u32 s14, s4
	s_load_b128 s[12:15], s[0:1], 0x28
	s_cselect_b32 s4, 12, 18
	v_mov_b32_e32 v1, s4
	global_load_u16 v4, v1, s[2:3]
	v_bfe_u32 v1, v0, 10, 10
	s_lshr_b32 s2, s5, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s6, s2, v[1:2]
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, v4, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s12, v0
	s_cbranch_execz .LBB0_32
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[16:17], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	s_load_b128 s[4:7], s[0:1], 0x38
	global_load_b64 v[14:15], v[4:5], off
	global_load_b64 v[12:13], v[6:7], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[14:15]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[6:7], null, s[6:7], s[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[4:5]
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[4:5], v[8:9], 1.0
	v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[8:9]
	v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[4:5], v[8:9], 1.0
	v_fma_f64 v[18:19], -v[6:7], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[16:17], v[8:9]
	v_div_scale_f64 v[16:17], vcc_lo, v[14:15], s[4:5], v[14:15]
	v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11]
	v_div_scale_f64 v[18:19], s2, v[12:13], s[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[20:21], v[16:17], v[8:9]
	v_mul_f64 v[22:23], v[18:19], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], v[20:21], v[16:17]
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
	v_fma_f64 v[6:7], -v[6:7], v[22:23], v[18:19]
                                        ; implicit-def: $vgpr18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[20:21]
	s_mov_b32 vcc_lo, s2
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr21
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[22:23]
                                        ; implicit-def: $vgpr10_vgpr11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[4:5], v[4:5], s[4:5], v[14:15]
	v_div_fixup_f64 v[6:7], v[6:7], s[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], -0.5
	v_add_f64 v[6:7], v[6:7], -0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f64_e32 v[4:5], v[4:5]
	v_floor_f64_e32 v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v20, v[4:5]
                                        ; implicit-def: $vgpr4_vgpr5
	v_cvt_i32_f64_e32 v19, v[6:7]
                                        ; implicit-def: $vgpr6_vgpr7
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 -1, v20
	s_xor_b32 s15, exec_lo, s0
	s_cbranch_execz .LBB0_21
; %bb.2:
	s_add_i32 s0, s13, -1
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s0, v20
	v_cmp_lt_i32_e64 s0, -1, v19
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s1
	s_cbranch_execz .LBB0_10
; %bb.3:
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr2_sgpr3
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $vgpr16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s20, exec_lo, s1
	s_cbranch_execz .LBB0_7
; %bb.4:
	v_mul_lo_u32 v6, v19, s13
	v_mov_b32_e32 v10, 0
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v4, 0
	v_mov_b32_e32 v5, 0x3ff00000
	v_mov_b32_e32 v21, 1
	s_add_i32 s1, s14, -1
	s_mov_b32 s19, 1
	v_add3_u32 v16, v20, v6, 1
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s1, v19
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_cvt_f64_i32_e32 v[4:5], v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], 0x3ff80000, v[4:5]
	v_add_f64 v[4:5], v[4:5], 0.5
	v_fma_f64 v[6:7], v[6:7], s[6:7], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], -v[4:5], s[6:7], v[12:13]
	v_div_scale_f64 v[4:5], null, s[6:7], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[10:11], null, s[6:7], s[6:7], v[8:9]
	v_div_scale_f64 v[21:22], vcc_lo, v[6:7], s[6:7], v[6:7]
	v_rcp_f64_e32 v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[4:5], v[12:13], 1.0
	v_fma_f64 v[19:20], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[17:18], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[19:20], v[14:15]
	v_fma_f64 v[17:18], -v[4:5], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[17:18], v[12:13]
	v_div_scale_f64 v[17:18], s1, v[8:9], s[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[19:20], v[14:15]
	v_mul_f64 v[19:20], v[21:22], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[23:24], v[17:18], v[14:15]
	v_fma_f64 v[4:5], -v[4:5], v[19:20], v[21:22]
	v_add_nc_u32_e32 v21, s13, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], -v[10:11], v[23:24], v[17:18]
	v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[19:20]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[23:24]
	v_div_fixup_f64 v[4:5], v[4:5], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f64 v[10:11], v[10:11], s[6:7], v[8:9]
.LBB0_6:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
.LBB0_7:                                ; %Flow43
	s_or_saveexec_b32 s1, s20
	v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
	v_mov_b32_e32 v18, s19
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.8:
	s_mov_b32 s2, s13
	v_mov_b32_e32 v6, 0
	v_mad_u64_u32 v[8:9], null, s13, v19, s[2:3]
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v11, 0x3ff00000
	v_dual_mov_b32 v18, 1 :: v_dual_mov_b32 v5, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v21, v20, v8, 1
	v_mov_b32_e32 v16, 1
; %bb.9:                                ; %Flow44
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
.LBB0_10:                               ; %Flow49
	s_or_saveexec_b32 s3, s18
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	v_mov_b32_e32 v17, v18
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_20
; %bb.11:
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s1
	s_cbranch_execz .LBB0_17
; %bb.12:
	v_mul_lo_u32 v22, v19, s13
	v_add_nc_u32_e32 v23, 1, v20
	v_add_nc_u32_e32 v24, 2, v20
	s_add_i32 s0, s14, -1
	s_mov_b32 s2, 1
	v_cmp_le_i32_e32 vcc_lo, s0, v19
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr4_vgpr5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v16, v22, v23
	v_add_nc_u32_e32 v17, v22, v24
	s_and_saveexec_b32 s19, vcc_lo
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_cvt_f64_i32_e32 v[4:5], v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], 0x3ff80000, v[4:5]
	v_add_f64 v[4:5], v[4:5], 0.5
	v_fma_f64 v[6:7], v[6:7], s[4:5], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], -v[4:5], s[4:5], v[14:15]
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[10:11], null, s[4:5], s[4:5], v[8:9]
	v_div_scale_f64 v[22:23], vcc_lo, v[6:7], s[4:5], v[6:7]
	v_rcp_f64_e32 v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[4:5], v[12:13], 1.0
	v_fma_f64 v[20:21], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_fma_f64 v[18:19], -v[4:5], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
	v_div_scale_f64 v[18:19], s0, v[8:9], s[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_mul_f64 v[20:21], v[22:23], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[18:19], v[14:15]
	v_fma_f64 v[4:5], -v[4:5], v[20:21], v[22:23]
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], -v[10:11], v[24:25], v[18:19]
                                        ; implicit-def: $vgpr19
	v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[20:21]
	s_mov_b32 vcc_lo, s0
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[24:25]
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
	v_div_fixup_f64 v[4:5], v[4:5], s[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f64 v[8:9], v[10:11], s[4:5], v[8:9]
.LBB0_14:                               ; %Flow45
	s_or_saveexec_b32 s19, s19
	v_dual_mov_b32 v18, s2 :: v_dual_mov_b32 v11, s1
	v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
	v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v21, s2
	s_xor_b32 exec_lo, exec_lo, s19
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_cvt_f64_i32_e32 v[4:5], v20
	v_cvt_f64_i32_e32 v[6:7], v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], 0x3ff80000, v[4:5]
	v_add_f64 v[10:11], 0x3ff80000, v[6:7]
	v_add_f64 v[4:5], v[4:5], 0.5
	v_add_f64 v[6:7], v[6:7], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[8:9], v[8:9], s[4:5], -v[14:15]
	v_fma_f64 v[10:11], v[10:11], s[6:7], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[4:5], -v[4:5], s[4:5], v[14:15]
	v_fma_f64 v[6:7], -v[6:7], s[6:7], v[12:13]
	v_mul_f64 v[12:13], s[4:5], s[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[14:15], v[8:9], v[10:11]
	v_mul_f64 v[10:11], v[4:5], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f64 v[18:19], v[8:9], v[6:7]
	v_mul_f64 v[6:7], v[4:5], v[6:7]
	v_div_scale_f64 v[4:5], null, v[12:13], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[8:9], null, v[12:13], v[12:13], v[10:11]
	v_div_scale_f64 v[20:21], null, v[12:13], v[12:13], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[25:26], null, v[12:13], v[12:13], v[6:7]
	v_div_scale_f64 v[43:44], vcc_lo, v[14:15], v[12:13], v[14:15]
	v_rcp_f64_e32 v[27:28], v[4:5]
	v_rcp_f64_e32 v[29:30], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[31:32], v[20:21]
	v_rcp_f64_e32 v[33:34], v[25:26]
	v_fma_f64 v[35:36], -v[4:5], v[27:28], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[37:38], -v[8:9], v[29:30], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[39:40], -v[20:21], v[31:32], 1.0
	v_fma_f64 v[41:42], -v[25:26], v[33:34], 1.0
	v_fma_f64 v[27:28], v[27:28], v[35:36], v[27:28]
	v_fma_f64 v[29:30], v[29:30], v[37:38], v[29:30]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[31:32], v[31:32], v[39:40], v[31:32]
	v_fma_f64 v[33:34], v[33:34], v[41:42], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[35:36], -v[4:5], v[27:28], 1.0
	v_fma_f64 v[37:38], -v[8:9], v[29:30], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[39:40], -v[20:21], v[31:32], 1.0
	v_fma_f64 v[41:42], -v[25:26], v[33:34], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[27:28], v[27:28], v[35:36], v[27:28]
	v_div_scale_f64 v[35:36], s0, v[10:11], v[12:13], v[10:11]
	v_fma_f64 v[29:30], v[29:30], v[37:38], v[29:30]
	v_div_scale_f64 v[37:38], s1, v[18:19], v[12:13], v[18:19]
	v_fma_f64 v[31:32], v[31:32], v[39:40], v[31:32]
	v_div_scale_f64 v[39:40], s2, v[6:7], v[12:13], v[6:7]
	v_fma_f64 v[33:34], v[33:34], v[41:42], v[33:34]
	v_mul_f64 v[41:42], v[43:44], v[27:28]
	v_mul_f64 v[45:46], v[35:36], v[29:30]
	v_mul_f64 v[47:48], v[37:38], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[49:50], v[39:40], v[33:34]
	v_fma_f64 v[4:5], -v[4:5], v[41:42], v[43:44]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[8:9], -v[8:9], v[45:46], v[35:36]
	v_fma_f64 v[20:21], -v[20:21], v[47:48], v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[25:26], -v[25:26], v[49:50], v[39:40]
	v_div_fmas_f64 v[4:5], v[4:5], v[27:28], v[41:42]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[8:9], v[8:9], v[29:30], v[45:46]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[20:21], v[20:21], v[31:32], v[47:48]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[25:26], v[25:26], v[33:34], v[49:50]
	v_div_fixup_f64 v[4:5], v[4:5], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[8:9], v[8:9], v[12:13], v[10:11]
	v_div_fixup_f64 v[10:11], v[20:21], v[12:13], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[6:7], v[25:26], v[12:13], v[6:7]
	v_add_nc_u32_e32 v12, s13, v22
	v_add_nc_u32_e32 v21, v12, v23
	v_add_nc_u32_e32 v18, v12, v24
.LBB0_16:                               ; %Flow46
	s_or_b32 exec_lo, exec_lo, s19
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr14_vgpr15
.LBB0_17:                               ; %Flow47
	s_and_not1_saveexec_b32 s1, s18
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_cvt_f64_i32_e32 v[4:5], v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], 0x3ff80000, v[4:5]
	v_add_f64 v[4:5], v[4:5], 0.5
	v_fma_f64 v[6:7], v[6:7], s[4:5], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], s[4:5], v[14:15]
	v_div_scale_f64 v[8:9], null, s[4:5], s[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[10:11], null, s[4:5], s[4:5], v[4:5]
	v_div_scale_f64 v[23:24], vcc_lo, v[6:7], s[4:5], v[6:7]
	v_rcp_f64_e32 v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[21:22], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[21:22], v[14:15]
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_div_scale_f64 v[16:17], s0, v[4:5], s[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[21:22], v[14:15]
	v_mul_f64 v[21:22], v[23:24], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[25:26], v[16:17], v[14:15]
	v_fma_f64 v[8:9], -v[8:9], v[21:22], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], -v[10:11], v[25:26], v[16:17]
	v_mov_b32_e32 v16, 1
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[21:22]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[12:13], v[10:11], v[14:15], v[25:26]
	v_div_fixup_f64 v[10:11], v[8:9], s[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[6:7], v[12:13], s[4:5], v[4:5]
	v_mul_lo_u32 v4, s13, v19
	v_add3_u32 v4, v4, s13, v20
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v17, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v21, 1, v4
	v_add_nc_u32_e32 v18, 2, v4
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
.LBB0_19:                               ; %Flow48
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_20:                               ; %Flow50
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr12_vgpr13
.LBB0_21:                               ; %Flow54
	s_and_not1_saveexec_b32 s2, s15
	s_cbranch_execz .LBB0_29
; %bb.22:
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $sgpr4
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 -1, v19
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_26
; %bb.23:
	v_mul_lo_u32 v4, v19, s13
	v_mov_b32_e32 v6, 0
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	v_dual_mov_b32 v9, 0x3ff00000 :: v_dual_mov_b32 v18, 1
	s_add_i32 s0, s14, -1
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v17, v20, v4, 2
	v_cmpx_gt_i32_e64 s0, v19
	s_cbranch_execz .LBB0_25
; %bb.24:
	v_cvt_f64_i32_e32 v[4:5], v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], 0x3ff80000, v[4:5]
	v_add_f64 v[4:5], v[4:5], 0.5
	v_fma_f64 v[6:7], v[6:7], s[6:7], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], s[6:7], v[12:13]
	v_div_scale_f64 v[8:9], null, s[6:7], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[10:11], null, s[6:7], s[6:7], v[4:5]
	v_div_scale_f64 v[22:23], vcc_lo, v[6:7], s[6:7], v[6:7]
	v_rcp_f64_e32 v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[20:21], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
	v_div_scale_f64 v[18:19], s0, v[4:5], s[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_mul_f64 v[20:21], v[22:23], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[18:19], v[14:15]
	v_fma_f64 v[8:9], -v[8:9], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], -v[10:11], v[24:25], v[18:19]
	v_add_nc_u32_e32 v18, s13, v17
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[20:21]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[24:25]
	v_div_fixup_f64 v[8:9], v[8:9], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[10:11], s[6:7], v[4:5]
.LBB0_25:                               ; %Flow51
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s4, 1
	s_mov_b64 s[0:1], 0
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
.LBB0_26:                               ; %Flow52
	s_or_saveexec_b32 s3, s3
	v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
	v_mov_b32_e32 v16, s4
	s_xor_b32 exec_lo, exec_lo, s3
; %bb.27:
	s_mov_b32 s0, s13
	v_mov_b32_e32 v8, 0
	v_mad_u64_u32 v[10:11], null, s13, v19, s[0:1]
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v17, 1 :: v_dual_mov_b32 v4, v8
	v_mov_b32_e32 v7, 0x3ff00000
	v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v16, 1
	v_add3_u32 v18, v20, v10, 2
; %bb.28:                               ; %Flow53
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v21, v16
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
.LBB0_29:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[12:13], 2, v[0:1]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s16, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s17, v13, vcc_lo
	global_load_b32 v1, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 1, v1
; %bb.30:
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v17, 1
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v16, 1
	v_dual_mov_b32 v21, 1 :: v_dual_mov_b32 v18, 1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v8, v4
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; %bb.31:
	s_or_b32 exec_lo, exec_lo, s0
	v_cvt_f64_i32_e32 v[12:13], v16
	v_cvt_f64_i32_e32 v[14:15], v17
	v_cvt_f64_i32_e32 v[16:17], v21
	v_cvt_f64_i32_e32 v[21:22], v18
	v_add3_u32 v0, s12, s12, v0
	v_add_co_u32 v19, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v20, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v23, s12, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s13, s12, 31
	v_add_co_u32 v2, vcc_lo, s10, v2
	s_lshl_b64 s[0:1], s[12:13], 3
	v_ashrrev_i32_e32 v24, 31, v23
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v25, vcc_lo, v19, s0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_ci_u32_e32 v26, vcc_lo, s1, v20, vcc_lo
	v_add_co_u32 v27, vcc_lo, v2, s0
	v_lshlrev_b64 v[23:24], 3, v[23:24]
	v_add_co_ci_u32_e32 v28, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v29, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v30, vcc_lo, s9, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v31, vcc_lo, s8, v23
	v_add_co_ci_u32_e32 v32, vcc_lo, s9, v24, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_clause 0x2
	global_store_b64 v[19:20], v[12:13], off
	global_store_b64 v[25:26], v[14:15], off
	global_store_b64 v[29:30], v[16:17], off
	v_add_co_u32 v12, vcc_lo, s10, v23
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v24, vcc_lo
	global_store_b64 v[31:32], v[21:22], off
	s_clause 0x3
	global_store_b64 v[2:3], v[4:5], off
	global_store_b64 v[27:28], v[8:9], off
	global_store_b64 v[0:1], v[10:11], off
	global_store_b64 v[12:13], v[6:7], off
.LBB0_32:                               ; %_Z3EM1PdS_S_S_Piiiidd.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24processMandelbrotElementPdS_S_S_Piiiidd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 51
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24processMandelbrotElementPdS_S_S_Piiiidd, .Lfunc_end0-_Z24processMandelbrotElementPdS_S_S_Piiiidd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3100
; NumSgprs: 23
; NumVgprs: 51
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 51
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24processMandelbrotElementPdS_S_S_Piiiidd
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z24processMandelbrotElementPdS_S_S_Piiiidd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     51
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
