// CUDA Implementation of the 2D wave equation

#include <stdlib.h>
#include <cuda_runtime.h>
#include <vector>
#include <math.h>

__device__ float src(int t, float dt) {
  float freqMag = 1000000000;  // 10^9 = GHz

  return 45 * sin(2 * acosf(-1.0) * 10 * freqMag * dt * t);
}

__global__ void Update(float* UOld, float* UNew, float* U, float* Ca, int SizeX,
                       int SizeY, int isrc, int jsrc, int t, float dt) {
  int r = blockDim.x * blockIdx.x + threadIdx.x;

  int i = r % SizeX;
  int j = (r - i) / SizeX;  // verify this

  int Idx = SizeX * i + j;
  int IdxLeft = SizeX * (i - 1) + j;
  int IdxRight = SizeX * (i + 1) + j;
  int IdxUp = SizeX * i + (j + 1);
  int IdxDown = SizeX * i + (j - 1);

  // Make sure we're in the grid loop
  if (i > 0 && i < (SizeX - 1) && j > 0 && j < (SizeY - 1))
    UNew[Idx] = 2 * U[Idx] - UOld[Idx] +
                Ca[Idx] * (U[IdxRight] + U[IdxLeft] + U[IdxUp] + U[IdxDown] -
                           4 * U[Idx]);

  if (i == isrc && j == isrc) UNew[Idx] = UNew[Idx] + src(t, dt);

  return;
}

// Mur Boundary Condition Kernel
__global__ void ApplyBC(float* UOld, float* UNew, float* U, int SizeX,
                        int SizeY, float dt, float dx) {
  int r = blockDim.x * blockIdx.x + threadIdx.x;

  int i = r % SizeX;
  int j = (r - i) / SizeX;  // verify this

  float cc = 299792458;

  float ABC_C1 = (cc * dt - dx) / (cc * dt + dx);
  float ABC_C2 = 2 * dx / (cc * dt + dx);
  float ABC_C3 = (cc * dt) * (cc * dt) / (2 * dx * (cc * dt + dx));

  int Idx = SizeX * i + j;
  int IdxLeft = SizeX * (i - 1) + j;
  int IdxRight = SizeX * (i + 1) + j;
  int IdxUp = SizeX * i + (j + 1);
  int IdxDown = SizeX * i + (j - 1);

  /**************
   * i == 0
   *************/
  if (i == 0 && j > 0 && j < (SizeY - 1)) {
    UNew[Idx] = -1 * UOld[IdxRight] + ABC_C1 * (UNew[IdxRight] + UOld[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxRight]) +
                ABC_C3 * (U[IdxUp] - 2 * U[Idx] + U[IdxDown] + U[IdxRight + 1] -
                          2 * U[IdxRight] + U[IdxRight - 1]);
  }

  /**************
   * i == SizeX
   *************/
  if (i == SizeX - 1 && j > 0 && j < (SizeY - 1)) {
    UNew[Idx] = -1 * UOld[IdxLeft] + ABC_C1 * (UNew[IdxLeft] + UNew[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxLeft]) +
                ABC_C3 * (U[IdxUp] - 2 * U[Idx] + U[IdxDown] + U[IdxLeft + 1] -
                          2 * U[IdxLeft] + U[IdxLeft - 1]);
  }
  
  /************
   * j == 0
   ***********/
  if(j == 0 && i > 0 && i < SizeX - 1)
  {
    UNew[Idx] = -1 * UOld[IdxUp] + ABC_C1 * (UNew[IdxUp] + UNew[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxUp]) +
                ABC_C3 * (U[IdxRight] - 2*U[Idx] + U[IdxLeft] +
                          U[IdxRight+1] - 2*U[IdxUp] + U[IdxLeft + 1]);

  }

  /**************
   *  j == SizeY
   *************/
  if(j == SizeY-1 && i > 0 && i < SizeX - 1)
  {
    UNew[Idx] = -1 * UOld[IdxDown] + ABC_C1 * (UNew[IdxDown] + UNew[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxDown]) + 
                ABC_C3 * (U[IdxRight] - 2*U[Idx] + U[IdxLeft] + 
                          U[IdxRight-1] - U[IdxDown] + U[IdxLeft - 1]);
  }
  return;
}  // End of ApplyBC function

int main()
{

  /****************
   * Initialization
   ***************/
  int SizeX = 100;
  int SizeY = 100;
  int MaxTime = 1000; 

  int isrc = 50;
  int jsrc = 50;

  float dx = 0.001;
  float cc = 299792458.0;
  float dt = 0.99 / (sqrt(2) * cc);
  
  float caInit = dt*cc / dx;

  std::vector<float> h_OldU(SizeX*SizeY,0.0);
  std::vector<float> h_NewU(SizeX*SizeY,0.0);
  std::vector<float> h_U(SizeX*SizeY,0.0);
  std::vector<float> h_Ca(SizeX*SizeY,caInit*caInit);
  
  float* d_OldU;
  float* d_NewU;
  float* d_U;
  float* d_Ca;
  
  /******************
   *  Allocate Memory
   *****************/
  cudaMalloc((void**)&d_OldU, h_OldU.size());
  cudaMalloc((void**)&d_NewU, h_NewU.size());
  cudaMalloc((void**)&d_U, h_U.size());
  cudaMalloc((void**)&d_Ca, h_Ca.size());

  cudaMemcpy(d_OldU, h_OldU.data(), h_OldU.size(), cudaMemcpyHostToDevice);
  cudaMemcpy(d_NewU, h_NewU.data(), h_NewU.size(), cudaMemcpyHostToDevice);
  cudaMemcpy(d_U, h_U.data(), h_U.size(), cudaMemcpyHostToDevice);
  cudaMemcpy(d_Ca, h_Ca.data(), h_Ca.size(), cudaMemcpyHostToDevice);
  
  int BlockSize = 32;
  int NumBlocks = (SizeX*SizeY - 1) / BlockSize + 1;

  for(int t = 0; t < MaxTime; t++)
  {
    Update<<<NumBlocks,BlockSize>>>(d_OldU,d_NewU,d_U,d_Ca,SizeX,SizeY,isrc,jsrc,t,dt);
    ApplyBC<<<NumBlocks,BlockSize>>>(d_OldU,d_NewU,d_U,SizeX,SizeY,dt,dx); 
    d_OldU = d_U;
    d_U = d_NewU;
  }

  /***************
   *  Free Memory
   **************/
  cudaFree(d_OldU);
  cudaFree(d_NewU);
  cudaFree(d_U);
  cudaFree(d_Ca);

  return 0;
}









	.file	"tmpxft_00207a3e_00000000-6_CudaWave.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2882:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2882:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z3srcif
	.type	_Z3srcif, @function
_Z3srcif:
.LFB2877:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2877:
	.size	_Z3srcif, .-_Z3srcif
	.globl	_Z37__device_stub__Z6UpdatePfS_S_S_iiiiifPfS_S_S_iiiiif
	.type	_Z37__device_stub__Z6UpdatePfS_S_S_iiiiifPfS_S_S_iiiiif, @function
_Z37__device_stub__Z6UpdatePfS_S_S_iiiiifPfS_S_S_iiiiif:
.LFB2904:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z6UpdatePfS_S_S_iiiiif(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L4:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2904:
	.size	_Z37__device_stub__Z6UpdatePfS_S_S_iiiiifPfS_S_S_iiiiif, .-_Z37__device_stub__Z6UpdatePfS_S_S_iiiiifPfS_S_S_iiiiif
	.globl	_Z6UpdatePfS_S_S_iiiiif
	.type	_Z6UpdatePfS_S_S_iiiiif, @function
_Z6UpdatePfS_S_S_iiiiif:
.LFB2905:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z6UpdatePfS_S_S_iiiiifPfS_S_S_iiiiif
	.cfi_endproc
.LFE2905:
	.size	_Z6UpdatePfS_S_S_iiiiif, .-_Z6UpdatePfS_S_S_iiiiif
	.globl	_Z34__device_stub__Z7ApplyBCPfS_S_iiffPfS_S_iiff
	.type	_Z34__device_stub__Z7ApplyBCPfS_S_iiffPfS_S_iiff, @function
_Z34__device_stub__Z7ApplyBCPfS_S_iiffPfS_S_iiff:
.LFB2906:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7ApplyBCPfS_S_iiff(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2906:
	.size	_Z34__device_stub__Z7ApplyBCPfS_S_iiffPfS_S_iiff, .-_Z34__device_stub__Z7ApplyBCPfS_S_iiffPfS_S_iiff
	.globl	_Z7ApplyBCPfS_S_iiff
	.type	_Z7ApplyBCPfS_S_iiff, @function
_Z7ApplyBCPfS_S_iiff:
.LFB2907:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z7ApplyBCPfS_S_iiffPfS_S_iiff
	.cfi_endproc
.LFE2907:
	.size	_Z7ApplyBCPfS_S_iiff, .-_Z7ApplyBCPfS_S_iiff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7ApplyBCPfS_S_iiff"
.LC1:
	.string	"_Z6UpdatePfS_S_S_iiiiif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2909:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7ApplyBCPfS_S_iiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6UpdatePfS_S_S_iiiiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2909:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.str1.1,"aMS",@progbits,1
.LC2:
	.string	"cannot create std::vector larger than max_size()"
	.section	.text._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKfRKS0_,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
	.type	_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_:
.LFB2964:
	.cfi_startproc
	endbr64
	movabsq	$2305843009213693951, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	pushq	%rcx
	.cfi_def_cfa_offset 48
	cmpq	%rsi, %rax
	jnb	.L18
	leaq	.LC2(%rip), %rdi
	call	_ZSt20__throw_length_errorPKc@PLT
.L18:
	movq	%rdx, %r13
	xorl	%edx, %edx
	movq	%rdi, %rbx
	movq	%rsi, %rbp
	movq	%rdx, (%rdi)
	leaq	0(,%rsi,4), %r12
	xorl	%eax, %eax
	movq	%rdx, 8(%rdi)
	movq	%rdx, 16(%rdi)
	testq	%rsi, %rsi
	je	.L19
	movq	%r12, %rdi
	call	_Znwm@PLT
.L19:
	addq	%rax, %r12
	movq	%rax, (%rbx)
	movq	%r12, 16(%rbx)
	testq	%rbp, %rbp
	je	.L20
	movss	0(%r13), %xmm0
.L21:
	cmpq	%rax, %r12
	je	.L20
	movss	%xmm0, (%rax)
	addq	$4, %rax
	jmp	.L21
.L20:
	movq	%rax, 8(%rbx)
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2964:
	.size	_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
	.weak	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
	.set	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
	.section	.text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEED2Ev
	.type	_ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB2967:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L29
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L29:
	ret
	.cfi_endproc
.LFE2967:
	.size	_ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
	.weak	_ZNSt6vectorIfSaIfEED1Ev
	.set	_ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB2878:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA2878
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$10000, %esi
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	leaq	-80(%rbp), %rbx
	movq	%rbx, %rdx
	subq	$232, %rsp
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	leaq	-104(%rbp), %rax
	movl	$0x00000000, -80(%rbp)
	movq	%rax, -216(%rbp)
	leaq	-152(%rbp), %rax
	movq	-216(%rbp), %rcx
	movq	%rax, %rdi
	movq	%rax, -224(%rbp)
.LEHB0:
	call	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE0:
	leaq	-128(%rbp), %rax
	movq	%rbx, %rdx
	movq	-216(%rbp), %rcx
	movl	$10000, %esi
	movq	%rax, %rdi
	movl	$0x00000000, -80(%rbp)
	movq	%rax, -232(%rbp)
.LEHB1:
	call	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE1:
	leaq	-164(%rbp), %r12
	movq	-216(%rbp), %rdi
	movq	%rbx, %rdx
	movl	$10000, %esi
	movq	%r12, %rcx
	movl	$0x00000000, -80(%rbp)
.LEHB2:
	call	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE2:
	leaq	-176(%rbp), %rcx
	movq	%r12, %rdx
	movl	$10000, %esi
	movq	%rbx, %rdi
	movl	$0x48ef4840, -164(%rbp)
.LEHB3:
	call	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE3:
	movq	-152(%rbp), %r15
	movq	-144(%rbp), %rax
	leaq	-208(%rbp), %rdi
	subq	%r15, %rax
	sarq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, -240(%rbp)
.LEHB4:
	call	cudaMalloc@PLT
	movq	-128(%rbp), %r14
	movq	-120(%rbp), %rax
	leaq	-200(%rbp), %rdi
	subq	%r14, %rax
	sarq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, -248(%rbp)
	call	cudaMalloc@PLT
	movq	-104(%rbp), %r13
	movq	-96(%rbp), %rax
	leaq	-192(%rbp), %rdi
	subq	%r13, %rax
	sarq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, -256(%rbp)
	call	cudaMalloc@PLT
	movq	-80(%rbp), %r12
	movq	-72(%rbp), %rax
	leaq	-184(%rbp), %rdi
	subq	%r12, %rax
	sarq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, -264(%rbp)
	call	cudaMalloc@PLT
	movq	-240(%rbp), %rdx
	movq	-208(%rbp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	call	cudaMemcpy@PLT
	movq	-248(%rbp), %rdx
	movq	-200(%rbp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	call	cudaMemcpy@PLT
	movq	-256(%rbp), %rdx
	movq	-192(%rbp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	call	cudaMemcpy@PLT
	movq	-264(%rbp), %rdx
	movq	-184(%rbp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movabsq	$4294967328, %r13
	xorl	%r12d, %r12d
.L34:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movabsq	$4294967609, %rdi
	movl	$1, %esi
	movq	%r13, -164(%rbp)
	movl	$1, -156(%rbp)
	movq	%rdi, -176(%rbp)
	movl	$1, -168(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	%rax
	movss	.LC5(%rip), %xmm0
	movl	$100, %r9d
	movl	$100, %r8d
	movq	-184(%rbp), %rcx
	movq	-192(%rbp), %rdx
	pushq	%r12
	movq	-200(%rbp), %rsi
	movq	-208(%rbp), %rdi
	pushq	$50
	pushq	$50
	.cfi_escape 0x2e,0x20
	call	_Z37__device_stub__Z6UpdatePfS_S_S_iiiiifPfS_S_S_iiiiif
	addq	$32, %rsp
.L32:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movabsq	$4294967609, %rdi
	movl	$1, %esi
	movq	%r13, -164(%rbp)
	movl	$1, -156(%rbp)
	movq	%rdi, -176(%rbp)
	movl	$1, -168(%rbp)
	.cfi_escape 0x2e,0
	call	__cudaPushCallConfiguration@PLT
	movq	-192(%rbp), %rdx
	movq	-200(%rbp), %rsi
	testl	%eax, %eax
	jne	.L33
	movss	.LC6(%rip), %xmm1
	movss	.LC5(%rip), %xmm0
	movl	$100, %ecx
	movl	$100, %r8d
	movq	-208(%rbp), %rdi
	call	_Z34__device_stub__Z7ApplyBCPfS_S_iiffPfS_S_iiff
.L33:
	movq	-192(%rbp), %rdi
	movq	-200(%rbp), %rax
	incl	%r12d
	movq	%rdi, -208(%rbp)
	movq	%rax, -192(%rbp)
	cmpl	$1000, %r12d
	jne	.L34
	call	cudaFree@PLT
	movq	-200(%rbp), %rdi
	call	cudaFree@PLT
	movq	-192(%rbp), %rdi
	call	cudaFree@PLT
	movq	-184(%rbp), %rdi
	call	cudaFree@PLT
.LEHE4:
	movq	%rbx, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	-216(%rbp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	-232(%rbp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	-224(%rbp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L40
	jmp	.L46
.L44:
	endbr64
	movq	%rax, %r12
.L35:
	movq	%rbx, %rdi
	movq	%r12, %rbx
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L36
.L43:
	endbr64
	movq	%rax, %rbx
.L36:
	movq	-216(%rbp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L37
.L42:
	endbr64
	movq	%rax, %rbx
.L37:
	movq	-232(%rbp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L38
.L41:
	endbr64
	movq	%rax, %rbx
.L38:
	movq	-224(%rbp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	jne	.L46
	movq	%rbx, %rdi
.LEHB5:
	call	_Unwind_Resume@PLT
.LEHE5:
.L46:
	call	__stack_chk_fail@PLT
.L40:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2878:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA2878:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE2878-.LLSDACSB2878
.LLSDACSB2878:
	.uleb128 .LEHB0-.LFB2878
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB2878
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L41-.LFB2878
	.uleb128 0
	.uleb128 .LEHB2-.LFB2878
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L42-.LFB2878
	.uleb128 0
	.uleb128 .LEHB3-.LFB2878
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L43-.LFB2878
	.uleb128 0
	.uleb128 .LEHB4-.LFB2878
	.uleb128 .LEHE4-.LEHB4
	.uleb128 .L44-.LFB2878
	.uleb128 0
	.uleb128 .LEHB5-.LFB2878
	.uleb128 .LEHE5-.LEHB5
	.uleb128 0
	.uleb128 0
.LLSDACSE2878:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC5:
	.long	824211187
	.align 4
.LC6:
	.long	981668463
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// CUDA Implementation of the 2D wave equation

#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <math.h>

__device__ float src(int t, float dt) {
  float freqMag = 1000000000;  // 10^9 = GHz

  return 45 * sin(2 * acosf(-1.0) * 10 * freqMag * dt * t);
}

__global__ void Update(float* UOld, float* UNew, float* U, float* Ca, int SizeX,
                       int SizeY, int isrc, int jsrc, int t, float dt) {
  int r = blockDim.x * blockIdx.x + threadIdx.x;

  int i = r % SizeX;
  int j = (r - i) / SizeX;  // verify this

  int Idx = SizeX * i + j;
  int IdxLeft = SizeX * (i - 1) + j;
  int IdxRight = SizeX * (i + 1) + j;
  int IdxUp = SizeX * i + (j + 1);
  int IdxDown = SizeX * i + (j - 1);

  // Make sure we're in the grid loop
  if (i > 0 && i < (SizeX - 1) && j > 0 && j < (SizeY - 1))
    UNew[Idx] = 2 * U[Idx] - UOld[Idx] +
                Ca[Idx] * (U[IdxRight] + U[IdxLeft] + U[IdxUp] + U[IdxDown] -
                           4 * U[Idx]);

  if (i == isrc && j == isrc) UNew[Idx] = UNew[Idx] + src(t, dt);

  return;
}

// Mur Boundary Condition Kernel
__global__ void ApplyBC(float* UOld, float* UNew, float* U, int SizeX,
                        int SizeY, float dt, float dx) {
  int r = blockDim.x * blockIdx.x + threadIdx.x;

  int i = r % SizeX;
  int j = (r - i) / SizeX;  // verify this

  float cc = 299792458;

  float ABC_C1 = (cc * dt - dx) / (cc * dt + dx);
  float ABC_C2 = 2 * dx / (cc * dt + dx);
  float ABC_C3 = (cc * dt) * (cc * dt) / (2 * dx * (cc * dt + dx));

  int Idx = SizeX * i + j;
  int IdxLeft = SizeX * (i - 1) + j;
  int IdxRight = SizeX * (i + 1) + j;
  int IdxUp = SizeX * i + (j + 1);
  int IdxDown = SizeX * i + (j - 1);

  /**************
   * i == 0
   *************/
  if (i == 0 && j > 0 && j < (SizeY - 1)) {
    UNew[Idx] = -1 * UOld[IdxRight] + ABC_C1 * (UNew[IdxRight] + UOld[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxRight]) +
                ABC_C3 * (U[IdxUp] - 2 * U[Idx] + U[IdxDown] + U[IdxRight + 1] -
                          2 * U[IdxRight] + U[IdxRight - 1]);
  }

  /**************
   * i == SizeX
   *************/
  if (i == SizeX - 1 && j > 0 && j < (SizeY - 1)) {
    UNew[Idx] = -1 * UOld[IdxLeft] + ABC_C1 * (UNew[IdxLeft] + UNew[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxLeft]) +
                ABC_C3 * (U[IdxUp] - 2 * U[Idx] + U[IdxDown] + U[IdxLeft + 1] -
                          2 * U[IdxLeft] + U[IdxLeft - 1]);
  }
  
  /************
   * j == 0
   ***********/
  if(j == 0 && i > 0 && i < SizeX - 1)
  {
    UNew[Idx] = -1 * UOld[IdxUp] + ABC_C1 * (UNew[IdxUp] + UNew[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxUp]) +
                ABC_C3 * (U[IdxRight] - 2*U[Idx] + U[IdxLeft] +
                          U[IdxRight+1] - 2*U[IdxUp] + U[IdxLeft + 1]);

  }

  /**************
   *  j == SizeY
   *************/
  if(j == SizeY-1 && i > 0 && i < SizeX - 1)
  {
    UNew[Idx] = -1 * UOld[IdxDown] + ABC_C1 * (UNew[IdxDown] + UNew[Idx]) +
                ABC_C2 * (U[Idx] + U[IdxDown]) + 
                ABC_C3 * (U[IdxRight] - 2*U[Idx] + U[IdxLeft] + 
                          U[IdxRight-1] - U[IdxDown] + U[IdxLeft - 1]);
  }
  return;
}  // End of ApplyBC function

int main()
{

  /****************
   * Initialization
   ***************/
  int SizeX = 100;
  int SizeY = 100;
  int MaxTime = 1000; 

  int isrc = 50;
  int jsrc = 50;

  float dx = 0.001;
  float cc = 299792458.0;
  float dt = 0.99 / (sqrt(2) * cc);
  
  float caInit = dt*cc / dx;

  std::vector<float> h_OldU(SizeX*SizeY,0.0);
  std::vector<float> h_NewU(SizeX*SizeY,0.0);
  std::vector<float> h_U(SizeX*SizeY,0.0);
  std::vector<float> h_Ca(SizeX*SizeY,caInit*caInit);
  
  float* d_OldU;
  float* d_NewU;
  float* d_U;
  float* d_Ca;
  
  /******************
   *  Allocate Memory
   *****************/
  hipMalloc((void**)&d_OldU, h_OldU.size());
  hipMalloc((void**)&d_NewU, h_NewU.size());
  hipMalloc((void**)&d_U, h_U.size());
  hipMalloc((void**)&d_Ca, h_Ca.size());

  hipMemcpy(d_OldU, h_OldU.data(), h_OldU.size(), hipMemcpyHostToDevice);
  hipMemcpy(d_NewU, h_NewU.data(), h_NewU.size(), hipMemcpyHostToDevice);
  hipMemcpy(d_U, h_U.data(), h_U.size(), hipMemcpyHostToDevice);
  hipMemcpy(d_Ca, h_Ca.data(), h_Ca.size(), hipMemcpyHostToDevice);
  
  int BlockSize = 32;
  int NumBlocks = (SizeX*SizeY - 1) / BlockSize + 1;

  for(int t = 0; t < MaxTime; t++)
  {
    Update<<<NumBlocks,BlockSize>>>(d_OldU,d_NewU,d_U,d_Ca,SizeX,SizeY,isrc,jsrc,t,dt);
    ApplyBC<<<NumBlocks,BlockSize>>>(d_OldU,d_NewU,d_U,SizeX,SizeY,dt,dx); 
    d_OldU = d_U;
    d_U = d_NewU;
  }

  /***************
   *  Free Memory
   **************/
  hipFree(d_OldU);
  hipFree(d_NewU);
  hipFree(d_U);
  hipFree(d_Ca);

  return 0;
}









	.text
	.file	"CudaWave.hip"
	.globl	_Z21__device_stub__UpdatePfS_S_S_iiiiif # -- Begin function _Z21__device_stub__UpdatePfS_S_S_iiiiif
	.type	_Z21__device_stub__UpdatePfS_S_S_iiiiif,@function
_Z21__device_stub__UpdatePfS_S_S_iiiiif: # @_Z21__device_stub__UpdatePfS_S_S_iiiiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	movq	%r9, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6UpdatePfS_S_S_iiiiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__UpdatePfS_S_S_iiiiif, .Lfunc_end0-_Z21__device_stub__UpdatePfS_S_S_iiiiif
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__ApplyBCPfS_S_iiff # -- Begin function _Z22__device_stub__ApplyBCPfS_S_iiff
	.type	_Z22__device_stub__ApplyBCPfS_S_iiff,@function
_Z22__device_stub__ApplyBCPfS_S_iiff:   # @_Z22__device_stub__ApplyBCPfS_S_iiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7ApplyBCPfS_S_iiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__ApplyBCPfS_S_iiff, .Lfunc_end1-_Z22__device_stub__ApplyBCPfS_S_iiff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x312076f3                      # float 2.33506792E-9
.LCPI2_1:
	.long	0x3a83126f                      # float 0.00100000005
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:                                # %.noexc
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	.cfi_escape 0x2e, 0x00
	movl	$40000, %edi                    # imm = 0x9C40
	callq	_Znwm
	movq	%rax, %rbx
	.cfi_escape 0x2e, 0x00
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp0:
	.cfi_escape 0x2e, 0x00
	movl	$40000, %edi                    # imm = 0x9C40
	movq	%rbx, 48(%rsp)                  # 8-byte Spill
	callq	_Znwm
.Ltmp1:
# %bb.1:                                # %.lr.ph.i.i.i.i.i.i.i.i.i56.preheader
	movq	%rax, %r14
	.cfi_escape 0x2e, 0x00
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp3:
	.cfi_escape 0x2e, 0x00
	movl	$40000, %edi                    # imm = 0x9C40
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	callq	_Znwm
.Ltmp4:
# %bb.2:                                # %.lr.ph.i.i.i.i.i.i.i.i.i61.preheader
	movq	%rax, %r15
	.cfi_escape 0x2e, 0x00
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp6:
	.cfi_escape 0x2e, 0x00
	movl	$40000, %edi                    # imm = 0x9C40
	callq	_Znwm
.Ltmp7:
# %bb.3:                                # %.lr.ph.i.i.i.i.i.i.i.i.i66.preheader
	movq	%rax, %r12
	xorl	%eax, %eax
.LBB2_4:                                # %.lr.ph.i.i.i.i.i.i.i.i.i66
                                        # =>This Inner Loop Header: Depth=1
	movl	$1223641152, (%r12,%rax)        # imm = 0x48EF4840
	addq	$4, %rax
	cmpq	$40000, %rax                    # imm = 0x9C40
	jne	.LBB2_4
# %bb.5:                                # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit70
.Ltmp9:
	.cfi_escape 0x2e, 0x00
	leaq	24(%rsp), %rdi
	movl	$10000, %esi                    # imm = 0x2710
	callq	hipMalloc
.Ltmp10:
# %bb.6:
.Ltmp11:
	.cfi_escape 0x2e, 0x00
	leaq	16(%rsp), %rdi
	movl	$10000, %esi                    # imm = 0x2710
	callq	hipMalloc
.Ltmp12:
# %bb.7:
.Ltmp13:
	.cfi_escape 0x2e, 0x00
	leaq	8(%rsp), %rdi
	movl	$10000, %esi                    # imm = 0x2710
	callq	hipMalloc
.Ltmp14:
# %bb.8:
.Ltmp15:
	.cfi_escape 0x2e, 0x00
	leaq	32(%rsp), %rdi
	movl	$10000, %esi                    # imm = 0x2710
	callq	hipMalloc
.Ltmp16:
# %bb.9:
	movq	24(%rsp), %rdi
.Ltmp17:
	.cfi_escape 0x2e, 0x00
	movl	$10000, %edx                    # imm = 0x2710
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp18:
# %bb.10:
	movq	16(%rsp), %rdi
.Ltmp19:
	.cfi_escape 0x2e, 0x00
	movl	$10000, %edx                    # imm = 0x2710
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp20:
# %bb.11:
	movq	8(%rsp), %rdi
.Ltmp21:
	.cfi_escape 0x2e, 0x00
	movl	$10000, %edx                    # imm = 0x2710
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp22:
# %bb.12:
	movq	32(%rsp), %rdi
.Ltmp23:
	.cfi_escape 0x2e, 0x00
	movl	$10000, %edx                    # imm = 0x2710
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp24:
# %bb.13:                               # %.preheader.preheader
	xorl	%ebx, %ebx
	movabsq	$4294967609, %r13               # imm = 0x100000139
	movabsq	$4294967328, %rbp               # imm = 0x100000020
	movl	$50, %r14d
.LBB2_14:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
.Ltmp26:
	.cfi_escape 0x2e, 0x00
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp27:
# %bb.15:                               #   in Loop: Header=BB2_14 Depth=1
	testl	%eax, %eax
	jne	.LBB2_17
# %bb.16:                               #   in Loop: Header=BB2_14 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rcx
.Ltmp28:
	.cfi_escape 0x2e, 0x20
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$100, %r8d
	movl	$100, %r9d
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z21__device_stub__UpdatePfS_S_S_iiiiif
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.Ltmp29:
.LBB2_17:                               #   in Loop: Header=BB2_14 Depth=1
.Ltmp30:
	.cfi_escape 0x2e, 0x00
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp31:
# %bb.18:                               #   in Loop: Header=BB2_14 Depth=1
	testl	%eax, %eax
	jne	.LBB2_20
# %bb.19:                               #   in Loop: Header=BB2_14 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
.Ltmp32:
	.cfi_escape 0x2e, 0x00
	movl	$100, %ecx
	movl	$100, %r8d
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	callq	_Z22__device_stub__ApplyBCPfS_S_iiff
.Ltmp33:
.LBB2_20:                               #   in Loop: Header=BB2_14 Depth=1
	movq	8(%rsp), %rdi
	movq	%rdi, 24(%rsp)
	movq	16(%rsp), %rax
	movq	%rax, 8(%rsp)
	incl	%ebx
	cmpl	$1000, %ebx                     # imm = 0x3E8
	jne	.LBB2_14
# %bb.21:
.Ltmp35:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp36:
# %bb.22:
	movq	16(%rsp), %rdi
.Ltmp37:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp38:
# %bb.23:
	movq	8(%rsp), %rdi
.Ltmp39:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp40:
# %bb.24:
	movq	32(%rsp), %rdi
.Ltmp41:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp42:
# %bb.25:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit76
	.cfi_escape 0x2e, 0x00
	movq	%r12, %rdi
	callq	_ZdlPv
	.cfi_escape 0x2e, 0x00
	movq	%r15, %rdi
	callq	_ZdlPv
	.cfi_escape 0x2e, 0x00
	movq	40(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdlPv
	.cfi_escape 0x2e, 0x00
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdlPv
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_28:
	.cfi_def_cfa_offset 112
.Ltmp8:
	movq	%rax, %r13
	jmp	.LBB2_33
.LBB2_27:
.Ltmp5:
	movq	%rax, %r13
	jmp	.LBB2_34
.LBB2_26:
.Ltmp2:
	movq	%rax, %r13
	jmp	.LBB2_35
.LBB2_31:
.Ltmp43:
	jmp	.LBB2_32
.LBB2_29:
.Ltmp25:
	jmp	.LBB2_32
.LBB2_30:
.Ltmp34:
.LBB2_32:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit78
	movq	%rax, %r13
	.cfi_escape 0x2e, 0x00
	movq	%r12, %rdi
	callq	_ZdlPv
.LBB2_33:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit80
	.cfi_escape 0x2e, 0x00
	movq	%r15, %rdi
	callq	_ZdlPv
.LBB2_34:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit82
	.cfi_escape 0x2e, 0x00
	movq	40(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdlPv
.LBB2_35:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit84
	.cfi_escape 0x2e, 0x00
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdlPv
	.cfi_escape 0x2e, 0x00
	movq	%r13, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table2:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp1-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp3-.Ltmp1                  #   Call between .Ltmp1 and .Ltmp3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp4-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Ltmp6-.Ltmp4                  #   Call between .Ltmp4 and .Ltmp6
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 6 <<
	.uleb128 .Ltmp7-.Ltmp6                  #   Call between .Ltmp6 and .Ltmp7
	.uleb128 .Ltmp8-.Lfunc_begin0           #     jumps to .Ltmp8
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp9-.Lfunc_begin0           # >> Call Site 7 <<
	.uleb128 .Ltmp24-.Ltmp9                 #   Call between .Ltmp9 and .Ltmp24
	.uleb128 .Ltmp25-.Lfunc_begin0          #     jumps to .Ltmp25
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp26-.Lfunc_begin0          # >> Call Site 8 <<
	.uleb128 .Ltmp33-.Ltmp26                #   Call between .Ltmp26 and .Ltmp33
	.uleb128 .Ltmp34-.Lfunc_begin0          #     jumps to .Ltmp34
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp35-.Lfunc_begin0          # >> Call Site 9 <<
	.uleb128 .Ltmp42-.Ltmp35                #   Call between .Ltmp35 and .Ltmp42
	.uleb128 .Ltmp43-.Lfunc_begin0          #     jumps to .Ltmp43
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp42-.Lfunc_begin0          # >> Call Site 10 <<
	.uleb128 .Lfunc_end2-.Ltmp42            #   Call between .Ltmp42 and .Lfunc_end2
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6UpdatePfS_S_S_iiiiif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7ApplyBCPfS_S_iiff, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6UpdatePfS_S_S_iiiiif,@object # @_Z6UpdatePfS_S_S_iiiiif
	.section	.rodata,"a",@progbits
	.globl	_Z6UpdatePfS_S_S_iiiiif
	.p2align	3, 0x0
_Z6UpdatePfS_S_S_iiiiif:
	.quad	_Z21__device_stub__UpdatePfS_S_S_iiiiif
	.size	_Z6UpdatePfS_S_S_iiiiif, 8

	.type	_Z7ApplyBCPfS_S_iiff,@object    # @_Z7ApplyBCPfS_S_iiff
	.globl	_Z7ApplyBCPfS_S_iiff
	.p2align	3, 0x0
_Z7ApplyBCPfS_S_iiff:
	.quad	_Z22__device_stub__ApplyBCPfS_S_iiff
	.size	_Z7ApplyBCPfS_S_iiff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6UpdatePfS_S_S_iiiiif"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7ApplyBCPfS_S_iiff"
	.size	.L__unnamed_2, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__UpdatePfS_S_S_iiiiif
	.addrsig_sym _Z22__device_stub__ApplyBCPfS_S_iiff
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z6UpdatePfS_S_S_iiiiif
	.addrsig_sym _Z7ApplyBCPfS_S_iiff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6UpdatePfS_S_S_iiiiif ; -- Begin function _Z6UpdatePfS_S_S_iiiiif
	.globl	_Z6UpdatePfS_S_S_iiiiif
	.p2align	8
	.type	_Z6UpdatePfS_S_S_iiiiif,@function
_Z6UpdatePfS_S_S_iiiiif:                ; @_Z6UpdatePfS_S_S_iiiiif
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s16, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s4, s16, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, s3
	v_cvt_f32_u32_e32 v1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s4
	s_load_b256 s[8:15], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, s2, v3
	s_add_i32 s2, s16, -1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v3, v0
	v_add_nc_u32_e32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s3, v2
	v_add_nc_u32_e32 v0, v3, v0
	s_add_i32 s3, s17, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v2
	v_sub_nc_u32_e32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v2, s16
	v_sub_nc_u32_e32 v3, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v4, v3, s16
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	v_cmp_gt_i32_e64 s2, s3, v2
	v_cmp_lt_i32_e64 s3, 0, v2
	v_cmp_lt_i32_e64 s4, 0, v3
	s_and_b32 s2, vcc_lo, s2
	v_add_nc_u32_e32 v0, v4, v2
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s4, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_subrev_nc_u32_e32 v4, s16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[0:1]
	v_add_nc_u32_e32 v4, v4, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s12, v10
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v6, s16, 1, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	s_clause 0x2
	global_load_b64 v[12:13], v[12:13], off
	global_load_b32 v14, v[6:7], off
	global_load_b32 v15, v[4:5], off
	v_add_nc_u32_e32 v8, -1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v11, vcc_lo
	global_load_b32 v8, v[4:5], off
	global_load_b32 v6, v[6:7], off
	v_add_co_u32 v4, vcc_lo, s14, v10
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v11, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(3)
	v_add_f32_e32 v5, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v13
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v5, v5, v8
	s_waitcnt vmcnt(1)
	v_fma_f32 v6, v12, 2.0, -v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, -4.0, v12
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v4, v5
	v_add_co_u32 v4, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v11, vcc_lo
	global_store_b32 v[4:5], v6, off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_eq_u32_e32 vcc_lo, s18, v3
	v_cmp_eq_u32_e64 s2, s18, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_9
; %bb.3:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_sqrt_f32_e32 v3, 0
	s_load_b64 s[0:1], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fmac_f32_e32 v3, 0, v3
	global_load_b32 v2, v[0:1], off
	v_add_f32_e32 v3, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, 0x40490fdb, v3
	v_cvt_f32_i32_e32 v4, s0
	v_add_f32_e32 v3, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x41200000, v3
	v_mul_f32_e32 v3, 0x4e6e6b28, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, s1, v3
	s_mov_b32 s1, 0
	v_mul_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e64 s0, 0x48000000, |v3|
	v_readfirstlane_b32 s2, v3
	s_and_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s0, s2, 0x7fffffff
	s_cbranch_vccz .LBB0_5
; %bb.4:
	s_and_b32 s2, s0, 0x7fffff
	s_lshr_b32 s3, s0, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s4, s2, 0xfe5163ab
	s_mul_i32 s5, s2, 0x3c439041
	s_mul_hi_u32 s6, s2, 0x3c439041
	s_add_u32 s4, s4, s5
	s_addc_u32 s5, 0, s6
	s_mul_i32 s6, s2, 0xdb629599
	s_mul_hi_u32 s7, s2, 0xdb629599
	s_add_u32 s5, s5, s6
	s_addc_u32 s6, 0, s7
	s_mul_i32 s7, s2, 0xf534ddc0
	s_mul_hi_u32 s8, s2, 0xf534ddc0
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s8
	s_mul_i32 s8, s2, 0xfc2757d1
	s_mul_hi_u32 s9, s2, 0xfc2757d1
	s_add_u32 s7, s7, s8
	s_addc_u32 s8, 0, s9
	s_mul_i32 s9, s2, 0x4e441529
	s_mul_hi_u32 s10, s2, 0x4e441529
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s10, s2, 0xfe5163ab
	s_mul_hi_u32 s11, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s12, s5, s7
	s_cselect_b32 s4, s4, s6
	s_cselect_b32 s5, s10, s5
	s_add_u32 s2, s9, s2
	s_addc_u32 s9, 0, s11
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s10, 0xffffffc0, 0
	s_cselect_b32 s6, s6, s8
	s_cselect_b32 s2, s7, s2
	s_cselect_b32 s7, s8, s9
	s_add_i32 s10, s10, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s10, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s8, s6, s2
	s_cselect_b32 s2, s2, s7
	s_cselect_b32 s6, s12, s6
	s_cselect_b32 s7, s4, s12
	s_cselect_b32 s4, s5, s4
	s_add_i32 s3, s3, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s2, s8, s2
	s_cselect_b32 s8, s6, s8
	s_cselect_b32 s6, s7, s6
	s_cselect_b32 s4, s4, s7
	s_add_i32 s5, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s5
	s_cmp_eq_u32 s5, 0
	v_mov_b32_e32 v4, s3
	s_cselect_b32 s5, -1, 0
	v_alignbit_b32 v5, s2, s8, v4
	v_alignbit_b32 v6, s8, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v5
	v_cndmask_b32_e64 v5, v6, s8, s5
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, s2, v5, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s7, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v6, s7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v7, v6
	v_min_u32_e32 v7, 32, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v9, 23, v7
	v_alignbit_b32 v4, s6, s4, v4
	v_sub_nc_u32_e32 v8, 31, v7
	v_cndmask_b32_e64 v4, v4, s6, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v5, v5, v4, 30
	v_alignbit_b32 v4, v4, s4, 30
	s_lshr_b32 s4, s2, 29
	s_lshr_b32 s2, s2, 30
	s_lshl_b32 s4, s4, 31
	v_xor_b32_e32 v5, s7, v5
	v_xor_b32_e32 v4, s7, v4
	s_or_b32 s5, s4, 0.5
	s_add_i32 s2, s3, s2
	v_sub_nc_u32_e32 v9, s5, v9
	v_alignbit_b32 v6, v6, v5, v8
	v_alignbit_b32 v4, v5, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v5, v6, v4, 9
	v_clz_i32_u32_e32 v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v8, 32, v8
	v_sub_nc_u32_e32 v10, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v4, v5, v4, v10
	v_lshrrev_b32_e32 v5, 9, v6
	v_lshrrev_b32_e32 v4, 9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v5, v9
	v_add_nc_u32_e32 v7, v8, v7
	v_lshlrev_b32_e32 v6, 23, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v4, v4, v6
	v_mul_f32_e32 v6, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 0x33000000, v4
	v_fma_f32 v7, 0x3fc90fda, v5, -v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v4, s4, v4
	v_fmamk_f32 v5, v5, 0x33a22168, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0x3fc90fda, v4
	v_add_f32_e32 v4, v6, v5
	s_branch .LBB0_6
.LBB0_5:
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr4
.LBB0_6:                                ; %Flow
	v_mov_b32_e32 v5, s2
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_8
; %bb.7:
	v_mul_f32_e64 v4, 0x3f22f983, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v5, v4
	v_fma_f32 v4, 0xbfc90fda, v5, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v4, v5, 0xb3a22168, v4
	v_fmamk_f32 v4, v5, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v5, v5
.LBB0_8:                                ; %_Z3srcif.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v6, v4, v4 :: v_dual_lshlrev_b32 v9, 30, v5
	s_mov_b32 s1, 0xb94c1982
	s_mov_b32 s2, 0x37d75334
	v_xor_b32_e32 v10, s0, v3
	v_fmaak_f32 v7, s1, v6, 0x3c0881c4
	v_and_b32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
	v_fmaak_f32 v8, s2, v6, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v6, v7
	v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v4, v4, v7 :: v_dual_and_b32 v7, 0x80000000, v9
	v_fmaak_f32 v8, v6, v8, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v10, v7
	v_fma_f32 v6, v6, v8, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v6, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x1f8
	v_xor_b32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x42340000, v4
	v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6UpdatePfS_S_S_iiiiif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6UpdatePfS_S_S_iiiiif, .Lfunc_end0-_Z6UpdatePfS_S_S_iiiiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1728
; NumSgprs: 22
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7ApplyBCPfS_S_iiff    ; -- Begin function _Z7ApplyBCPfS_S_iiff
	.globl	_Z7ApplyBCPfS_S_iiff
	.p2align	8
	.type	_Z7ApplyBCPfS_S_iiff,@function
_Z7ApplyBCPfS_S_iiff:                   ; @_Z7ApplyBCPfS_S_iiff
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x18
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s16, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s4, s16, s3
	v_mul_f32_e64 v6, 0x4d8ef3c2, s18
	s_xor_b32 s4, s4, s3
	v_add_f32_e64 v7, s19, s19
	v_cvt_f32_u32_e32 v1, s4
	s_add_i32 s5, s17, -1
	v_mul_f32_e32 v6, v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s4
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v1, v2
	v_dual_mov_b32 v3, s19 :: v_dual_add_nc_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s3, v2
	v_fma_f32 v5, 0x4d8ef3c2, s18, -v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_fmamk_f32 v3, s18, 0x4d8ef3c2, v3
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[6:7], s[0:1], 0x10
	v_div_scale_f32 v9, null, v3, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v8, v0, s4
	v_div_scale_f32 v10, null, v3, v3, v7
	v_rcp_f32_e32 v14, v9
	v_div_scale_f32 v16, s2, v5, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v4, v8
	v_rcp_f32_e32 v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v12, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_dual_mul_f32 v13, v7, v3 :: v_dual_cndmask_b32 v4, v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_2)
	v_div_scale_f32 v15, null, v13, v13, v6
	v_fma_f32 v12, -v9, v14, 1.0
	v_add_nc_u32_e32 v11, 1, v0
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v18, -v10, v8, 1.0
	v_rcp_f32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v12, v14
	v_dual_fmac_f32 v8, v18, v8 :: v_dual_mul_f32 v19, v16, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v15, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v12, v17
	v_cndmask_b32_e32 v0, v0, v11, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_div_scale_f32 v18, s4, v6, v13, v6
	v_div_scale_f32 v4, s3, v7, v3, v7
	v_mul_f32_e32 v21, v18, v17
	v_add_nc_u32_e32 v11, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v11, vcc_lo
	s_mov_b32 vcc_lo, s2
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v0, v2
	v_fma_f32 v2, -v9, v19, v16
	v_mul_lo_u32 v12, v11, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v19, v2, v14
	v_fma_f32 v2, -v15, v21, v18
	v_mul_f32_e32 v0, v4, v8
	v_cmp_gt_i32_e64 s0, s5, v11
	v_fmac_f32_e32 v21, v2, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v20, -v10, v0, v4
	v_sub_nc_u32_e32 v12, v1, v12
	v_fma_f32 v1, -v9, v19, v16
	v_fma_f32 v9, -v15, v21, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v0, v20, v8
	v_mul_lo_u32 v2, v12, s16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v14, v19
	s_mov_b32 vcc_lo, s3
	v_cmp_eq_u32_e64 s1, 0, v12
	v_fma_f32 v4, -v10, v0, v4
	v_div_fmas_f32 v8, v4, v8, v0
	v_subrev_nc_u32_e32 v0, s16, v2
	s_mov_b32 vcc_lo, s4
	v_add_nc_u32_e32 v4, v2, v11
	v_div_fmas_f32 v14, v9, v17, v21
	v_div_fixup_f32 v10, v8, v3, v7
	v_add_nc_u32_e32 v0, v0, v11
	v_cmp_lt_i32_e32 vcc_lo, 0, v11
	v_div_fixup_f32 v9, v1, v3, v5
	v_div_fixup_f32 v8, v14, v13, v6
	v_add_nc_u32_e32 v6, -1, v4
	v_lshl_add_u32 v2, s16, 1, v0
	v_ashrrev_i32_e32 v5, 31, v4
	s_and_b32 s1, s1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v3, 31, v2
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 2, v[2:3]
	v_lshlrev_b64 v[16:17], 2, v[4:5]
	v_lshlrev_b64 v[22:23], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v18, s1, s10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v19, s1, s11, v14, s1
	v_add_co_u32 v20, s1, s6, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v21, s1, s7, v17, s1
	v_add_co_u32 v24, s1, s8, v16
	v_add_co_ci_u32_e64 v25, s1, s9, v17, s1
	v_add_co_u32 v22, s1, s6, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v23, s1, s7, v23, s1
	v_add_co_u32 v26, s1, s6, v13
	v_add_co_ci_u32_e64 v27, s1, s7, v14, s1
	s_clause 0x1
	global_load_b64 v[20:21], v[20:21], off
	global_load_b32 v1, v[22:23], off
	v_add_co_u32 v22, s1, s8, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v23, s1, s9, v14, s1
	global_load_b32 v18, v[18:19], off
	global_load_b32 v19, v[24:25], off
	global_load_b96 v[13:15], v[26:27], off offset:-4
	global_load_b32 v22, v[22:23], off
	s_waitcnt vmcnt(2)
	v_dual_fmac_f32 v21, -2.0, v20 :: v_dual_add_f32 v18, v18, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, v9, v18, -v22
	v_add_f32_e32 v1, v21, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v15
	v_add_f32_e32 v15, v20, v14
	v_dual_fmac_f32 v1, -2.0, v14 :: v_dual_fmac_f32 v18, v10, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v13, v1
	v_add_co_u32 v13, s1, s10, v16
	v_add_co_ci_u32_e64 v14, s1, s11, v17, s1
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v18, v8, v1
	global_store_b32 v[13:14], v18, off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s2, s16, -1
	v_ashrrev_i32_e32 v1, 31, v0
	v_cmp_eq_u32_e64 s1, s2, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, vcc_lo
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_lshlrev_b64 v[13:14], 2, v[0:1]
	v_lshlrev_b64 v[15:16], 2, v[4:5]
	v_lshlrev_b64 v[21:22], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v17, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v18, vcc_lo, s11, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s6, v15
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v16, vcc_lo
	v_add_co_u32 v23, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v24, vcc_lo, s11, v16, vcc_lo
	v_add_co_u32 v15, vcc_lo, s6, v21
	v_add_co_ci_u32_e32 v16, vcc_lo, s7, v22, vcc_lo
	global_load_b64 v[19:20], v[19:20], off
	v_add_co_u32 v21, vcc_lo, s6, v13
	global_load_b32 v16, v[15:16], off
	v_add_co_ci_u32_e32 v22, vcc_lo, s7, v14, vcc_lo
	v_add_co_u32 v25, vcc_lo, s8, v13
	v_add_co_ci_u32_e32 v26, vcc_lo, s9, v14, vcc_lo
	s_clause 0x1
	global_load_b32 v17, v[17:18], off
	global_load_b32 v18, v[23:24], off
	global_load_b96 v[13:15], v[21:22], off offset:-4
	global_load_b32 v21, v[25:26], off
	s_waitcnt vmcnt(2)
	v_dual_fmac_f32 v20, -2.0, v19 :: v_dual_add_f32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v20, v16
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v15, v16, v15
	s_waitcnt vmcnt(0)
	v_fma_f32 v16, v9, v17, -v21
	v_add_f32_e32 v17, v19, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, v10, v17 :: v_dual_fmac_f32 v15, -2.0, v14
	v_add_f32_e32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v16, v8, v13
	global_store_b32 v[23:24], v16, off
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_eq_u32_e64 s1, 0, v11
	v_cmp_lt_i32_e32 vcc_lo, 0, v12
	v_cmp_gt_i32_e64 s0, s2, v12
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_lshlrev_b64 v[12:13], 2, v[4:5]
	v_lshlrev_b64 v[14:15], 2, v[2:3]
	v_lshlrev_b64 v[18:19], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v16, s1, s6, v12
	v_add_co_ci_u32_e64 v17, s1, s7, v13, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s1, s6, v14
	v_add_co_ci_u32_e64 v15, s1, s7, v15, s1
	v_add_co_u32 v18, s1, s6, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s1, s7, v19, s1
	v_add_co_u32 v20, s1, s10, v12
	v_add_co_ci_u32_e64 v21, s1, s11, v13, s1
	s_clause 0x1
	global_load_b64 v[16:17], v[16:17], off
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_u32 v12, s1, s8, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s1, s9, v13, s1
	global_load_b64 v[18:19], v[18:19], off
	global_load_b64 v[22:23], v[20:21], off
	global_load_b32 v12, v[12:13], off offset:4
	s_waitcnt vmcnt(3)
	v_fma_f32 v13, -2.0, v16, v14
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v13, v18
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v14, v23, v22
	s_waitcnt vmcnt(0)
	v_fma_f32 v12, v9, v14, -v12
	v_dual_add_f32 v14, v16, v17 :: v_dual_add_f32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v10, v14 :: v_dual_fmac_f32 v13, -2.0, v17
	v_add_f32_e32 v13, v19, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v12, v8, v13
	global_store_b32 v[20:21], v12, off
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_eq_u32_e64 s1, s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v13, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v15, v[13:14], off
	global_load_b64 v[2:3], v[2:3], off offset:-4
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v11, v[11:12], off
	global_load_b32 v12, v[4:5], off
	global_load_b64 v[0:1], v[0:1], off offset:-4
	v_add_co_u32 v13, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b32 v13, v[13:14], off
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(5)
	v_fma_f32 v3, -2.0, v15, v3
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v3, v1
	v_add_f32_e32 v1, v1, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v6
	v_dual_add_f32 v3, v11, v12 :: v_dual_add_f32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v9, v3, -v13
	v_add_f32_e32 v3, v15, v6
	v_fmac_f32_e32 v2, v10, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, v8, v0
	global_store_b32 v[4:5], v2, off
.LBB1_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7ApplyBCPfS_S_iiff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7ApplyBCPfS_S_iiff, .Lfunc_end1-_Z7ApplyBCPfS_S_iiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1852
; NumSgprs: 22
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6UpdatePfS_S_S_iiiiif
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z6UpdatePfS_S_S_iiiiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7ApplyBCPfS_S_iiff
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z7ApplyBCPfS_S_iiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
