#include <cstdio>
#include <cstdlib>
#include <string>
#include <cuda_runtime.h>

#include <iostream>


__global__
void print(const char * message, size_t length)
{
  //printf("blockIdx.x, threadIdx.x: %d, %d\n", blockIdx.x, threadIdx.x);
  for (size_t i = blockDim.x * blockIdx.x + threadIdx.x; i < length; i += blockDim.x * gridDim.x)
    printf("%c", message[i]);
}


int main(int argc, const char* argv[]) {
  std::string message;
  if (argc == 1) {
    message = "Hello world!";
  } else {
    message = argv[1];
  }
  
  char * buffer;
  cudaMalloc(& buffer, message.size());
  cudaMemcpy(buffer, message.data(), message.size(), cudaMemcpyDefault);
  
  print<<<16,1>>>(buffer, message.size());
  cudaDeviceSynchronize();
  cudaGetLastError();
  std::cout << std::endl;
  
  print<<<4,4>>>(buffer, message.size());
  cudaDeviceSynchronize();
  cudaGetLastError();
  std::cout << std::endl;
  
  print<<<1,16>>>(buffer, message.size());
  cudaDeviceSynchronize();
  cudaGetLastError();
  std::cout << std::endl;
  
  cudaFree(buffer);
}



	.file	"tmpxft_003a1701_00000000-6_test_cuda.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z26__device_stub__Z5printPKcmPKcm
	.type	_Z26__device_stub__Z5printPKcmPKcm, @function
_Z26__device_stub__Z5printPKcmPKcm:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5printPKcm(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z26__device_stub__Z5printPKcmPKcm, .-_Z26__device_stub__Z5printPKcmPKcm
	.globl	_Z5printPKcm
	.type	_Z5printPKcm, @function
_Z5printPKcm:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z5printPKcmPKcm
	.cfi_endproc
.LFE3662:
	.size	_Z5printPKcm, .-_Z5printPKcm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Hello world!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA3635
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$88, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movb	$0, 56(%rsp)
	leaq	40(%rsp), %rbx
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	decl	%edi
	movq	%rax, 48(%rsp)
	jne	.L9
	movl	$12, %r8d
	leaq	.LC0(%rip), %rcx
.L32:
	xorl	%edx, %edx
	xorl	%esi, %esi
	movq	%rbx, %rdi
.LEHB0:
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
	movq	48(%rsp), %rsi
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	jmp	.L33
.L9:
	movq	8(%rsi), %rbp
	movq	%rbp, %rdi
	call	strlen@PLT
	movq	%rbp, %rcx
	movq	%rax, %r8
	jmp	.L32
.L33:
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$4, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$268435457, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	salq	$4, %rdi
	movl	$1, %esi
	movl	$1, 36(%rsp)
	movq	%rdx, 28(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L12
.L14:
	call	cudaDeviceSynchronize@PLT
	jmp	.L34
.L12:
	movq	48(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z26__device_stub__Z5printPKcmPKcm
	jmp	.L14
.L34:
	call	cudaGetLastError@PLT
	leaq	_ZSt4cout(%rip), %rbp
	movq	%rbp, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$2, %rdi
	movl	$1, %esi
	movl	$1, 36(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 28(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L15
.L17:
	call	cudaDeviceSynchronize@PLT
	jmp	.L35
.L15:
	movq	48(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z26__device_stub__Z5printPKcmPKcm
	jmp	.L17
.L35:
	call	cudaGetLastError@PLT
	movq	%rbp, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$4, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 36(%rsp)
	movq	%rdx, 28(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L18
.L20:
	call	cudaDeviceSynchronize@PLT
	jmp	.L36
.L18:
	movq	48(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z26__device_stub__Z5printPKcmPKcm
	jmp	.L20
.L36:
	call	cudaGetLastError@PLT
	movq	%rbp, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
.LEHE0:
	movq	%rbx, %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	jmp	.L29
.L24:
	endbr64
	movq	%rax, %rbp
.L21:
	movq	%rbx, %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L29
	movq	%rbp, %rdi
.LEHB1:
	call	_Unwind_Resume@PLT
.LEHE1:
.L29:
	call	__stack_chk_fail@PLT
.L23:
	addq	$88, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA3635:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE3635-.LLSDACSB3635
.LLSDACSB3635:
	.uleb128 .LEHB0-.LFB3635
	.uleb128 .LEHE0-.LEHB0
	.uleb128 .L24-.LFB3635
	.uleb128 0
	.uleb128 .LEHB1-.LFB3635
	.uleb128 .LEHE1-.LEHB1
	.uleb128 0
	.uleb128 0
.LLSDACSE3635:
	.section	.text.startup
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z5printPKcm"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5printPKcm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <cstdio>
#include <cstdlib>
#include <string>
#include <hip/hip_runtime.h>

#include <iostream>


__global__
void print(const char * message, size_t length)
{
  //printf("blockIdx.x, threadIdx.x: %d, %d\n", blockIdx.x, threadIdx.x);
  for (size_t i = blockDim.x * blockIdx.x + threadIdx.x; i < length; i += blockDim.x * gridDim.x)
    printf("%c", message[i]);
}


int main(int argc, const char* argv[]) {
  std::string message;
  if (argc == 1) {
    message = "Hello world!";
  } else {
    message = argv[1];
  }
  
  char * buffer;
  hipMalloc(& buffer, message.size());
  hipMemcpy(buffer, message.data(), message.size(), hipMemcpyDefault);
  
  print<<<16,1>>>(buffer, message.size());
  hipDeviceSynchronize();
  hipGetLastError();
  std::cout << std::endl;
  
  print<<<4,4>>>(buffer, message.size());
  hipDeviceSynchronize();
  hipGetLastError();
  std::cout << std::endl;
  
  print<<<1,16>>>(buffer, message.size());
  hipDeviceSynchronize();
  hipGetLastError();
  std::cout << std::endl;
  
  hipFree(buffer);
}



	.text
	.file	"test_cuda.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z20__device_stub__printPKcm    # -- Begin function _Z20__device_stub__printPKcm
	.type	_Z20__device_stub__printPKcm,@function
_Z20__device_stub__printPKcm:           # @_Z20__device_stub__printPKcm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5printPKcm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__printPKcm, .Lfunc_end0-_Z20__device_stub__printPKcm
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	24(%rsp), %r14
	movq	%r14, -16(%r14)
	movq	$0, -8(%r14)
	movb	$0, (%r14)
	cmpl	$1, %edi
	jne	.LBB1_2
# %bb.1:
.Ltmp2:
	leaq	8(%rsp), %rdi
	movl	$.L.str, %ecx
	movl	$12, %r8d
	xorl	%esi, %esi
	xorl	%edx, %edx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.Ltmp3:
	jmp	.LBB1_3
.LBB1_2:
	movq	8(%rsi), %rbx
	movq	%rbx, %rdi
	callq	strlen
.Ltmp0:
	leaq	8(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%edx, %edx
	movq	%rbx, %rcx
	movq	%rax, %r8
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.Ltmp1:
.LBB1_3:                                # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEPKc.exit
	movq	16(%rsp), %rsi
.Ltmp5:
	movq	%rsp, %rdi
	callq	hipMalloc
.Ltmp6:
# %bb.4:                                # %_ZL9hipMallocIcE10hipError_tPPT_m.exit
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
.Ltmp7:
	movl	$4, %ecx
	callq	hipMemcpy
.Ltmp8:
# %bb.5:
.Ltmp9:
	movabsq	$4294967312, %rdi               # imm = 0x100000010
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp10:
# %bb.6:
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
.Ltmp11:
	callq	_Z20__device_stub__printPKcm
.Ltmp12:
.LBB1_8:
.Ltmp13:
	callq	hipDeviceSynchronize
.Ltmp14:
# %bb.9:
.Ltmp15:
	callq	hipGetLastError
.Ltmp16:
# %bb.10:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %edi
	addq	-24(%rax), %rdi
.Ltmp17:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp18:
# %bb.11:                               # %.noexc
.Ltmp19:
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
.Ltmp20:
# %bb.12:                               # %.noexc24
.Ltmp21:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp22:
# %bb.13:                               # %_ZNSolsEPFRSoS_E.exit
.Ltmp23:
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp24:
# %bb.14:
	testl	%eax, %eax
	jne	.LBB1_16
# %bb.15:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
.Ltmp25:
	callq	_Z20__device_stub__printPKcm
.Ltmp26:
.LBB1_16:
.Ltmp27:
	callq	hipDeviceSynchronize
.Ltmp28:
# %bb.17:
.Ltmp29:
	callq	hipGetLastError
.Ltmp30:
# %bb.18:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %edi
	addq	-24(%rax), %rdi
.Ltmp31:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp32:
# %bb.19:                               # %.noexc26
.Ltmp33:
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
.Ltmp34:
# %bb.20:                               # %.noexc27
.Ltmp35:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp36:
# %bb.21:                               # %_ZNSolsEPFRSoS_E.exit19
.Ltmp37:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$4294967312, %rdx               # imm = 0x100000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp38:
# %bb.22:
	testl	%eax, %eax
	jne	.LBB1_24
# %bb.23:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
.Ltmp39:
	callq	_Z20__device_stub__printPKcm
.Ltmp40:
.LBB1_24:
.Ltmp41:
	callq	hipDeviceSynchronize
.Ltmp42:
# %bb.25:
.Ltmp43:
	callq	hipGetLastError
.Ltmp44:
# %bb.26:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %edi
	addq	-24(%rax), %rdi
.Ltmp45:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp46:
# %bb.27:                               # %.noexc30
.Ltmp47:
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
.Ltmp48:
# %bb.28:                               # %.noexc31
.Ltmp49:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp50:
# %bb.29:                               # %_ZNSolsEPFRSoS_E.exit20
	movq	(%rsp), %rdi
.Ltmp51:
	callq	hipFree
.Ltmp52:
# %bb.30:
	movq	8(%rsp), %rdi
	cmpq	%r14, %rdi
	je	.LBB1_32
# %bb.31:                               # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
	callq	_ZdlPv
.LBB1_32:                               # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_33:
	.cfi_def_cfa_offset 64
.Ltmp4:
	jmp	.LBB1_34
.LBB1_37:
.Ltmp53:
.LBB1_34:
	movq	%rax, %rbx
	movq	8(%rsp), %rdi
	cmpq	%r14, %rdi
	je	.LBB1_36
# %bb.35:                               # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i21
	callq	_ZdlPv
.LBB1_36:                               # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit23
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table1:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Ltmp2-.Lfunc_begin0           # >> Call Site 1 <<
	.uleb128 .Ltmp1-.Ltmp2                  #   Call between .Ltmp2 and .Ltmp1
	.uleb128 .Ltmp4-.Lfunc_begin0           #     jumps to .Ltmp4
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp5-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp52-.Ltmp5                 #   Call between .Ltmp5 and .Ltmp52
	.uleb128 .Ltmp53-.Lfunc_begin0          #     jumps to .Ltmp53
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp52-.Lfunc_begin0          # >> Call Site 3 <<
	.uleb128 .Lfunc_end1-.Ltmp52            #   Call between .Ltmp52 and .Lfunc_end1
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5printPKcm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5printPKcm,@object            # @_Z5printPKcm
	.section	.rodata,"a",@progbits
	.globl	_Z5printPKcm
	.p2align	3, 0x0
_Z5printPKcm:
	.quad	_Z20__device_stub__printPKcm
	.size	_Z5printPKcm, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Hello world!"
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5printPKcm"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__printPKcm
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z5printPKcm
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5printPKcm            ; -- Begin function _Z5printPKcm
	.globl	_Z5printPKcm
	.p2align	8
	.type	_Z5printPKcm,@function
_Z5printPKcm:                           ; @_Z5printPKcm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s2, 0xffff
	s_mov_b32 s2, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[6:7], v[1:2]
	s_cbranch_execz .LBB0_174
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b32 s10, s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x50
	v_mov_b32_e32 v30, v2
	v_mbcnt_lo_u32_b32 v31, -1, 0
	v_dual_mov_b32 v0, 33 :: v_dual_mov_b32 v5, 2
	v_dual_mov_b32 v6, 1 :: v_dual_mov_b32 v29, v1
	s_mov_b32 s8, 0
	s_mov_b32 s21, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s20, s10, s9
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_19 Depth 2
                                        ;     Child Loop BB0_28 Depth 2
                                        ;     Child Loop BB0_31 Depth 2
                                        ;       Child Loop BB0_34 Depth 3
                                        ;       Child Loop BB0_42 Depth 3
                                        ;       Child Loop BB0_50 Depth 3
                                        ;       Child Loop BB0_58 Depth 3
                                        ;       Child Loop BB0_66 Depth 3
                                        ;       Child Loop BB0_74 Depth 3
                                        ;       Child Loop BB0_82 Depth 3
                                        ;       Child Loop BB0_90 Depth 3
                                        ;       Child Loop BB0_98 Depth 3
                                        ;       Child Loop BB0_104 Depth 3
                                        ;       Child Loop BB0_113 Depth 3
                                        ;     Child Loop BB0_121 Depth 2
                                        ;     Child Loop BB0_129 Depth 2
                                        ;     Child Loop BB0_135 Depth 2
                                        ;     Child Loop BB0_144 Depth 2
                                        ;     Child Loop BB0_149 Depth 2
                                        ;     Child Loop BB0_157 Depth 2
                                        ;     Child Loop BB0_163 Depth 2
                                        ;     Child Loop BB0_172 Depth 2
	v_add_co_u32 v3, vcc_lo, s4, v29
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v30, vcc_lo
	v_mov_b32_e32 v1, v31
	global_load_u8 v32, v[3:4], off
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[9:10], v2, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[7:8], v2, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[9:10]
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_5:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[2:3] offset:40
	global_load_b64 v[11:12], v2, s[2:3]
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[9:10]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow355
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_7:                                ; %Flow357
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_8:                                ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[2:3] offset:40
	global_load_b128 v[7:10], v2, s[2:3]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v11
	v_readfirstlane_b32 s11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v7, s15
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
	global_store_b128 v[11:12], v[3:6], off offset:8
.LBB0_10:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v9, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v10, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v14, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v12, s11
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v10, s9
	v_mov_b32_e32 v11, s10
	v_mov_b32_e32 v9, s8
	s_clause 0x3
	global_store_b128 v[13:14], v[0:3], off
	global_store_b128 v[13:14], v[9:12], off offset:16
	global_store_b128 v[13:14], v[9:12], off offset:32
	global_store_b128 v[13:14], v[9:12], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_18
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	v_dual_mov_b32 v15, s12 :: v_dual_mov_b32 v16, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v3, vcc_lo, v7, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v8, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_14
; %bb.12:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s11, 0
.LBB0_13:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_13
.LBB0_14:                               ; %Flow353
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_16:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_18:                               ; %Flow354
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v7, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s14, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_19:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_19 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_21:                               ;   in Loop: Header=BB0_19 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_19 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_24
.LBB0_23:                               ;   in Loop: Header=BB0_19 Depth=2
	s_mov_b32 s1, -1
.LBB0_24:                               ; %Flow348
                                        ;   in Loop: Header=BB0_19 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_19
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[7:8], v[13:14], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_29
; %bb.26:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[13:14], v2, s[2:3] offset:24 glc
	global_load_b64 v[11:12], v2, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v1
	v_and_b32_e32 v1, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v9, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_29
; %bb.27:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_28:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_28
.LBB0_29:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, .str@rel32@lo+4
	s_addc_u32 s11, s11, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc0 .LBB0_116
; %bb.30:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v10, v8 :: v_dual_and_b32 v33, 2, v7
	v_and_b32_e32 v9, -3, v7
	s_mov_b64 s[12:13], 3
.LBB0_31:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_34 Depth 3
                                        ;       Child Loop BB0_42 Depth 3
                                        ;       Child Loop BB0_50 Depth 3
                                        ;       Child Loop BB0_58 Depth 3
                                        ;       Child Loop BB0_66 Depth 3
                                        ;       Child Loop BB0_74 Depth 3
                                        ;       Child Loop BB0_82 Depth 3
                                        ;       Child Loop BB0_90 Depth 3
                                        ;       Child Loop BB0_98 Depth 3
                                        ;       Child Loop BB0_104 Depth 3
                                        ;       Child Loop BB0_113 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[12:13], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s14, s12, 56
	s_cselect_b32 s15, s13, 0
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_36
; %bb.32:                               ;   in Loop: Header=BB0_31 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_35
; %bb.33:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_lshl_b64 s[0:1], s[14:15], 3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[10:11]
.LBB0_34:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[18:19]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s0, s16
	v_or_b32_e32 v11, v3, v11
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB0_34
.LBB0_35:                               ; %Flow324
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_37
.LBB0_36:                               ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr9
.LBB0_37:                               ; %Flow326
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[10:11]
	s_cbranch_vccnz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[11:12], v2, s[10:11]
	s_add_i32 s9, s14, -8
	s_add_u32 s0, s10, 8
	s_addc_u32 s1, s11, 0
.LBB0_39:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_44
; %bb.40:                               ;   in Loop: Header=BB0_31 Depth=2
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_43
; %bb.41:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_42:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s18
	s_addc_u32 s23, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s9, s18
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB0_42
.LBB0_43:                               ; %Flow319
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s22, 0
	s_branch .LBB0_45
.LBB0_44:                               ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr22
.LBB0_45:                               ; %Flow321
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_47
; %bb.46:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[13:14], v2, s[0:1]
	s_add_i32 s22, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_47:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_cmp_gt_u32 s22, 7
	s_cbranch_scc1 .LBB0_52
; %bb.48:                               ;   in Loop: Header=BB0_31 Depth=2
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s22, 0
	s_cbranch_scc1 .LBB0_51
; %bb.49:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_50:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s22, s18
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB0_50
.LBB0_51:                               ; %Flow314
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_53
.LBB0_52:                               ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr9
.LBB0_53:                               ; %Flow316
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[15:16], v2, s[0:1]
	s_add_i32 s9, s22, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_55:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_60
; %bb.56:                               ;   in Loop: Header=BB0_31 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_59
; %bb.57:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_58:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s18
	s_addc_u32 s23, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s9, s18
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB0_58
.LBB0_59:                               ; %Flow309
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s22, 0
	s_branch .LBB0_61
.LBB0_60:                               ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr22
.LBB0_61:                               ; %Flow311
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_63
; %bb.62:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[17:18], v2, s[0:1]
	s_add_i32 s22, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_63:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_cmp_gt_u32 s22, 7
	s_cbranch_scc1 .LBB0_68
; %bb.64:                               ;   in Loop: Header=BB0_31 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s22, 0
	s_cbranch_scc1 .LBB0_67
; %bb.65:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_66:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s22, s18
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB0_66
.LBB0_67:                               ; %Flow304
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_69
.LBB0_68:                               ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr9
.LBB0_69:                               ; %Flow306
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_71
; %bb.70:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[19:20], v2, s[0:1]
	s_add_i32 s9, s22, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_71:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_76
; %bb.72:                               ;   in Loop: Header=BB0_31 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_75
; %bb.73:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_74:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s18
	s_addc_u32 s23, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[22:23]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s9, s18
	v_or_b32_e32 v21, v3, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB0_74
.LBB0_75:                               ; %Flow299
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s22, 0
	s_branch .LBB0_77
.LBB0_76:                               ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr22
.LBB0_77:                               ; %Flow301
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[21:22], v2, s[0:1]
	s_add_i32 s22, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_79:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_cmp_gt_u32 s22, 7
	s_cbranch_scc1 .LBB0_84
; %bb.80:                               ;   in Loop: Header=BB0_31 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s22, 0
	s_cbranch_scc1 .LBB0_83
; %bb.81:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[0:1]
.LBB0_82:                               ; %.preheader.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[18:19]
	s_add_i32 s22, s22, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s22, 0
	v_or_b32_e32 v23, v3, v23
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB0_82
.LBB0_83:                               ; %Flow294
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s9, 0
	s_branch .LBB0_85
.LBB0_84:                               ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s9, -1
.LBB0_85:                               ; %Flow296
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[23:24], v2, s[0:1]
.LBB0_87:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	v_mov_b32_e32 v1, v31
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_93
; %bb.88:                               ;   in Loop: Header=BB0_31 Depth=2
	global_load_b64 v[27:28], v2, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[25:26], v2, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v28
	v_and_b32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v34, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v34, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v25, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[27:28]
	s_cbranch_execz .LBB0_92
; %bb.89:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s16, 0
.LBB0_90:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[2:3] offset:40
	global_load_b64 v[34:35], v2, s[2:3]
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v27, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v25, 24, v[34:35]
	v_and_b32_e32 v34, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v34, 24, v[4:5]
	v_mov_b32_e32 v4, v25
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[27:28]
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_90
; %bb.91:                               ; %Flow289
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
.LBB0_92:                               ; %Flow291
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_93:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[34:35], v2, s[2:3] offset:40
	global_load_b128 v[25:28], v2, s[2:3]
	v_readfirstlane_b32 s16, v3
	v_readfirstlane_b32 s17, v4
	s_mov_b32 s23, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s18, v34
	v_readfirstlane_b32 s19, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[16:17], s[18:19]
	s_mul_i32 s1, s19, 24
	s_mul_hi_u32 s9, s18, 24
	s_mul_i32 s22, s18, 24
	s_and_saveexec_b32 s24, s0
	s_cbranch_execz .LBB0_95
; %bb.94:                               ;   in Loop: Header=BB0_31 Depth=2
	v_dual_mov_b32 v3, s23 :: v_dual_mov_b32 v4, v2
	s_add_i32 s23, s9, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v25, s22
	v_add_co_ci_u32_e32 v35, vcc_lo, s23, v26, vcc_lo
	global_store_b128 v[34:35], v[3:6], off offset:8
.LBB0_95:                               ;   in Loop: Header=BB0_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	v_cmp_gt_u64_e64 vcc_lo, s[12:13], 56
	v_or_b32_e32 v3, 0, v10
	v_or_b32_e32 v4, v9, v33
	s_lshl_b64 s[18:19], s[18:19], 12
	s_lshl_b32 s23, s14, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s23, s23, 28
	v_dual_cndmask_b32 v10, v3, v10 :: v_dual_cndmask_b32 v9, v4, v9
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v27, s18
	v_add_co_ci_u32_e32 v27, vcc_lo, s19, v28, vcc_lo
	s_and_b32 s23, s23, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v9, 0xffffff1f, v9, s23
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[17:20], off offset:32
	global_store_b128 v[3:4], v[21:24], off offset:48
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_103
; %bb.96:                               ;   in Loop: Header=BB0_31 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[2:3] offset:32 glc
	global_load_b64 v[9:10], v2, s[2:3] offset:40
	v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v16, s17
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s24, v9
	v_readfirstlane_b32 s25, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[24:25], s[24:25], s[16:17]
	s_mul_i32 s19, s25, 24
	s_mul_hi_u32 s23, s24, 24
	s_mul_i32 s24, s24, 24
	s_add_i32 s23, s23, s19
	v_add_co_u32 v13, vcc_lo, v25, s24
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v26, vcc_lo
	s_mov_b32 s19, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_99
; %bb.97:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s23, 0
.LBB0_98:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s16 :: v_dual_mov_b32 v10, s17
	s_sleep 1
	global_store_b64 v[13:14], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_98
.LBB0_99:                               ; %Flow287
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	global_load_b64 v[9:10], v2, s[2:3] offset:16
	s_mov_b32 s23, exec_lo
	s_mov_b32 s19, exec_lo
	v_mbcnt_lo_u32_b32 v1, s23, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_101
; %bb.100:                              ;   in Loop: Header=BB0_31 Depth=2
	s_bcnt1_i32_b32 s23, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s23
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[1:2], off offset:8
.LBB0_101:                              ;   in Loop: Header=BB0_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_31 Depth=2
	global_load_b32 v1, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s19, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s19, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_103:                              ; %Flow288
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s9, s9, s1
	v_add_co_u32 v1, vcc_lo, v25, s22
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_104:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_104 Depth=3
	global_load_b32 v1, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_106:                              ;   in Loop: Header=BB0_104 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_108
; %bb.107:                              ;   in Loop: Header=BB0_104 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_109
.LBB0_108:                              ;   in Loop: Header=BB0_104 Depth=3
	s_mov_b32 s1, -1
.LBB0_109:                              ; %Flow282
                                        ;   in Loop: Header=BB0_104 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_104
; %bb.110:                              ;   in Loop: Header=BB0_31 Depth=2
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_114
; %bb.111:                              ;   in Loop: Header=BB0_31 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[15:16], v2, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v2, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s16
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v1, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v12, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_114
; %bb.112:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mov_b32 s0, 0
.LBB0_113:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v2, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_113
.LBB0_114:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s12, s12, s14
	s_subb_u32 s13, s13, s15
	s_add_u32 s10, s10, s14
	s_addc_u32 s11, s11, s15
	s_cmp_lg_u64 s[12:13], 0
	s_cbranch_scc1 .LBB0_31
; %bb.115:                              ; %Flow327
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_117
.LBB0_116:                              ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_117:                              ; %Flow342
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_146
; %bb.118:                              ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v1, v31
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_124
; %bb.119:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[11:12], v2, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[9:10], v2, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v12
	v_and_b32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[11:12]
	s_cbranch_execz .LBB0_123
; %bb.120:                              ; %.preheader3.i.i.i10.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_121:                              ; %.preheader3.i.i.i10
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[2:3] offset:40
	global_load_b64 v[13:14], v2, s[2:3]
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v9
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_121
; %bb.122:                              ; %Flow339
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_123:                              ; %Flow341
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_124:                              ; %.loopexit4.i.i.i5
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[2:3] offset:40
	global_load_b128 v[11:14], v2, s[2:3]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v9
	v_readfirstlane_b32 s11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_126
; %bb.125:                              ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[9:10], v[3:6], off offset:8
.LBB0_126:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v7, 0xffffff1f, v7, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v16, s11
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v15, s10
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v13, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_134
; %bb.127:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v2, s[2:3] offset:40
	v_dual_mov_b32 v15, s12 :: v_dual_mov_b32 v16, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v13, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v14, vcc_lo, s16, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[17:18]
	s_cbranch_execz .LBB0_130
; %bb.128:                              ; %.preheader1.i.i.i8.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s11, 0
.LBB0_129:                              ; %.preheader1.i.i.i8
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s13
	s_sleep 1
	global_store_b64 v[13:14], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_129
.LBB0_130:                              ; %Flow337
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v2, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_132
; %bb.131:                              ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB0_132:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_134:                              ; %Flow338
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_135:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_137
; %bb.136:                              ;   in Loop: Header=BB0_135 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_137:                              ;   in Loop: Header=BB0_135 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_139
; %bb.138:                              ;   in Loop: Header=BB0_135 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_140
.LBB0_139:                              ;   in Loop: Header=BB0_135 Depth=2
	s_mov_b32 s1, -1
.LBB0_140:                              ; %Flow332
                                        ;   in Loop: Header=BB0_135 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_135
; %bb.141:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_145
; %bb.142:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[7:8], v2, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v2, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v1
	v_and_b32_e32 v1, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v11, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_145
; %bb.143:                              ; %.preheader.i.i.i7.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_144:                              ; %.preheader.i.i.i7
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_144
.LBB0_145:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_146:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v1, v31
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_152
; %bb.147:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[13:14], v2, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[7:8], v2, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v14
	v_and_b32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[13:14]
	s_cbranch_execz .LBB0_151
; %bb.148:                              ; %.preheader3.i.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_149:                              ; %.preheader3.i.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[2:3] offset:40
	global_load_b64 v[11:12], v2, s[2:3]
	v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v13, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[13:14]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_149
; %bb.150:                              ; %Flow275
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_151:                              ; %Flow277
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_152:                              ; %.loopexit4.i.i.i11
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[2:3] offset:40
	global_load_b128 v[13:16], v2, s[2:3]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_154
; %bb.153:                              ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v13, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v14, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB0_154:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_bfe_i32 v11, v32, 0, 8
	v_and_or_b32 v9, 0xffffff1d, v9, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_mov_b32_e32 v12, v2
	v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v15, s8
	v_dual_mov_b32 v17, s10 :: v_dual_mov_b32 v16, s9
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[15:18], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[15:18], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_162
; %bb.155:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v3, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v14, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[11:12]
	s_cbranch_execz .LBB0_158
; %bb.156:                              ; %.preheader1.i.i.i15.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s11, 0
.LBB0_157:                              ; %.preheader1.i.i.i15
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s13
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_157
.LBB0_158:                              ; %Flow273
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_160
; %bb.159:                              ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_160:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_162:                              ; %Flow274
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v13, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s14, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_163:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_165
; %bb.164:                              ;   in Loop: Header=BB0_163 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_165:                              ;   in Loop: Header=BB0_163 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_167
; %bb.166:                              ;   in Loop: Header=BB0_163 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_168
.LBB0_167:                              ;   in Loop: Header=BB0_163 Depth=2
	s_mov_b32 s1, -1
.LBB0_168:                              ; %Flow268
                                        ;   in Loop: Header=BB0_163 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_163
; %bb.169:                              ;   in Loop: Header=BB0_2 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_173
; %bb.170:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[2:3] offset:40
	global_load_b64 v[11:12], v2, s[2:3] offset:24 glc
	global_load_b64 v[9:10], v2, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_173
; %bb.171:                              ; %.preheader.i.i.i14.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_172:                              ; %.preheader.i.i.i14
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_172
.LBB0_173:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v29, vcc_lo, v29, s20
	v_add_co_ci_u32_e32 v30, vcc_lo, 0, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u64_e32 vcc_lo, s[6:7], v[29:30]
	s_or_b32 s21, vcc_lo, s21
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_2
.LBB0_174:                              ; %Flow360
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5printPKcm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5printPKcm, .Lfunc_end0-_Z5printPKcm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6712
; NumSgprs: 28
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%c"
	.size	.str, 3

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         96
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5printPKcm
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z5printPKcm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
