//optimization homework #4 cs 677 Theodore Jagodits
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>

#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
#define GPU_SPEED_LO_LIMIT 1

//add constant memory 
__constant__ float c_inp[MAX_CONST];

//tiling complete
__global__ void unknown_algo_inp2_chunk(float *result, float *inp2, int row, int col, int num_tiles, int chunk){
	//add shared memory
	__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
	//get row col idx
	int tx = blockIdx.x * blockDim.x + threadIdx.x;
	int ty = blockIdx.y * blockDim.y + threadIdx.y;
	float temp = 0.0f;
	unsigned int curr = 0, pos_x;
	
	for(unsigned int count = 0; count < num_tiles; count++){
		//find position
		pos_x = count * TILE_SIZE + threadIdx.x;
		//check bounds and load tile
		if(pos_x < col && ty < row){
			temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = inp2[ty*row + pos_x];
		}
		__syncthreads();
		for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
			if(curr <= tx){
				temp += temp_shared_2[threadIdx.y * TILE_SIZE + tile];
			}
			curr ++;
		}
	}
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

//tiling complete
__global__ void unknown_algo_inp1_chunk(float *result, int row, int col, int num_tiles, int stride, int chunk){
	int tx = blockDim.x * blockIdx.x + threadIdx.x;
	int ty = blockDim.y * blockIdx.y + threadIdx.y;
	
	float temp, local;
	temp = 0.0f;
	if(ty < row && tx < col){
		local = c_inp[ty*row +tx];
		result[ty*row + tx] = temp;
	}
	
	for(int i = 0; i < col; i++){
		temp += local * c_inp[stride + i];
	}
	
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

//tiling complete
__global__ void unknown_algo_inp2_no_chunk(float *result, int row, int col, int num_tiles){
	//add shared memory
	__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
	//get row col idx
	int tx = blockIdx.x * blockDim.x + threadIdx.x;
	int ty = blockIdx.y * blockDim.y + threadIdx.y;
	float temp = 0.0f;
	unsigned int curr = 0, pos_x;
	
	for(unsigned int count = 0; count < num_tiles; count++){
		//find position
		pos_x = count * TILE_SIZE + threadIdx.x;
		//check bounds and load tile
		if(pos_x < col && ty < row){
			temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
		}
		__syncthreads();
		for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
			if(curr <= tx){
				temp += temp_shared_2[threadIdx.y * TILE_SIZE + tile];
			}
			curr ++;
		}
	}
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

//tiling complete no point of tiling here
__global__ void unknown_algo_inp1_no_chunk(float *result, int row, int col, int num_tiles, int stride){
	int tx = blockDim.x * blockIdx.x + threadIdx.x;
	int ty = blockDim.y * blockIdx.y + threadIdx.y;
	
	float temp, local;
	temp = 0.0f;
	if(ty < row && tx < col){
		local = c_inp[ty*row +tx];
		result[ty*row + tx] = temp;
	}
	
	for(int i = 0; i < col; i++){
		temp += local * c_inp[stride + i];
	}
	
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

int main( int argc, char **argv ){
	int row = DEFAULT_ROW;
	int col = DEFAULT_COL;
	if(argc == 3){
		row = atoi(argv[1]);
		col = atoi(argv[2]);
	}
	int num_bytes = row* col * sizeof(float);
	int stride = row * col;
	
	float *h_temp = (float *) calloc(col, sizeof(float)); //store temp results
	float *d_temp = (float *) calloc(col, sizeof(float)); //store temp results
	float *d_result = (float *) malloc(num_bytes);
	float *h_input = (float *) malloc(num_bytes);
	float *h_result = (float *) malloc(num_bytes);
	
	//cudaMalloc(&d_input2, num_bytes);
	cudaMalloc(&d_result, num_bytes);
	cudaMalloc(&d_temp, col * sizeof(float));
	
	//put in data
	for(int o = 0; o < row; o++){
        for(int p = 0; p < col; p++){
            h_input[row * o + p] = 1.0f;
        }
    }
	// add input 1 to input
	for(int p = 0; p < col; p++){
        h_input[stride + p] = 1.0f;
    }
	
	//declare block and grid size for kernel
	int block_size = TILE_SIZE;
	//make grids x y
	int grid_x = (int)ceil((float)col/block_size);
	int grid_y = (int)ceil((float)row/block_size);
	dim3 dim_grid (grid_x, grid_y);
	dim3 dim_block (block_size, block_size);
	
	//run different configs depending on size
	if(col * row + col> MAX_CONST){ //greater than limit of const mem 
	/*
		float *temp_chunk = (float*) calloc(MAX_CONST,sizeof(float));
		for(int chunk = 0; chunk < (int)ceil((float)(row*col)/MAX_CONST); chunk++){
			for(int i = 0; i < MAX_CONST; i++){
				if(i<stride)
					temp_chunk[i] = h_input[chunk*MAX_CONST + i];
				else
					break;
			}
			cudaMemcpyToSymbol(c_inp, temp_chunk, MAX_CONST);
			unknown_algo_inp2_chunk<<< dim_grid, dim_block >>> (d_result, d_temp, row, col, num_tiles, chunk);
		}
		for(int chunk = 0; chunk < (int)ceil((float)(row*col)/MAX_CONST); chunk++){
			unknown_algo_inp1<<< dim_grid, dim_block >>> (d_result, row, col, 0);
		}
		free(temp_chunk);
		*/
		
	} else if(col * row > GPU_SPEED_LO_LIMIT){//check
		cudaMemcpyToSymbol(c_inp, h_input, num_bytes);
		unknown_algo_inp2_no_chunk<<< dim_grid, dim_block >>> (d_result, row, col, grid_x);
		unknown_algo_inp1_no_chunk<<< dim_grid, dim_block >>> (d_result, row, col, grid_x, stride);
	} else{ // run one kernel
		//combined_algo<<< dim_grid, dim_block >>> (d_result, row, col, 0);
	}
	
	// Copy result back to host
	cudaMemcpy(h_result, d_result, num_bytes, cudaMemcpyDeviceToHost);
	
	//print error check
	for(int i = 0; i < row; i++){
		printf("%d. ", i);
		for(int j = 0; j < col; j++){
			printf("%d ", (int)h_result[i*row + j]);
		}
		printf("\n");
	}
	
	free(h_input);
	free(h_result);
	
	cudaFree(d_result);
	cudaFree(d_temp);
	return 0;
}
	.file	"tmpxft_00223836_00000000-6_algo.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z23unknown_algo_inp2_chunkPfS_iiiiPfS_iiii
	.type	_Z49__device_stub__Z23unknown_algo_inp2_chunkPfS_iiiiPfS_iiii, @function
_Z49__device_stub__Z23unknown_algo_inp2_chunkPfS_iiiiPfS_iiii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z23unknown_algo_inp2_chunkPfS_iiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z49__device_stub__Z23unknown_algo_inp2_chunkPfS_iiiiPfS_iiii, .-_Z49__device_stub__Z23unknown_algo_inp2_chunkPfS_iiiiPfS_iiii
	.globl	_Z23unknown_algo_inp2_chunkPfS_iiii
	.type	_Z23unknown_algo_inp2_chunkPfS_iiii, @function
_Z23unknown_algo_inp2_chunkPfS_iiii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z23unknown_algo_inp2_chunkPfS_iiiiPfS_iiii
	.cfi_endproc
.LFE3661:
	.size	_Z23unknown_algo_inp2_chunkPfS_iiii, .-_Z23unknown_algo_inp2_chunkPfS_iiii
	.globl	_Z48__device_stub__Z23unknown_algo_inp1_chunkPfiiiiiPfiiiii
	.type	_Z48__device_stub__Z23unknown_algo_inp1_chunkPfiiiiiPfiiiii, @function
_Z48__device_stub__Z23unknown_algo_inp1_chunkPfiiiiiPfiiiii:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z23unknown_algo_inp1_chunkPfiiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L8:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z48__device_stub__Z23unknown_algo_inp1_chunkPfiiiiiPfiiiii, .-_Z48__device_stub__Z23unknown_algo_inp1_chunkPfiiiiiPfiiiii
	.globl	_Z23unknown_algo_inp1_chunkPfiiiii
	.type	_Z23unknown_algo_inp1_chunkPfiiiii, @function
_Z23unknown_algo_inp1_chunkPfiiiii:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z23unknown_algo_inp1_chunkPfiiiiiPfiiiii
	.cfi_endproc
.LFE3663:
	.size	_Z23unknown_algo_inp1_chunkPfiiiii, .-_Z23unknown_algo_inp1_chunkPfiiiii
	.globl	_Z49__device_stub__Z26unknown_algo_inp2_no_chunkPfiiiPfiii
	.type	_Z49__device_stub__Z26unknown_algo_inp2_no_chunkPfiiiPfiii, @function
_Z49__device_stub__Z26unknown_algo_inp2_no_chunkPfiiiPfiii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26unknown_algo_inp2_no_chunkPfiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z49__device_stub__Z26unknown_algo_inp2_no_chunkPfiiiPfiii, .-_Z49__device_stub__Z26unknown_algo_inp2_no_chunkPfiiiPfiii
	.globl	_Z26unknown_algo_inp2_no_chunkPfiii
	.type	_Z26unknown_algo_inp2_no_chunkPfiii, @function
_Z26unknown_algo_inp2_no_chunkPfiii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z26unknown_algo_inp2_no_chunkPfiiiPfiii
	.cfi_endproc
.LFE3665:
	.size	_Z26unknown_algo_inp2_no_chunkPfiii, .-_Z26unknown_algo_inp2_no_chunkPfiii
	.globl	_Z50__device_stub__Z26unknown_algo_inp1_no_chunkPfiiiiPfiiii
	.type	_Z50__device_stub__Z26unknown_algo_inp1_no_chunkPfiiiiPfiiii, @function
_Z50__device_stub__Z26unknown_algo_inp1_no_chunkPfiiiiPfiiii:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26unknown_algo_inp1_no_chunkPfiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z50__device_stub__Z26unknown_algo_inp1_no_chunkPfiiiiPfiiii, .-_Z50__device_stub__Z26unknown_algo_inp1_no_chunkPfiiiiPfiiii
	.globl	_Z26unknown_algo_inp1_no_chunkPfiiii
	.type	_Z26unknown_algo_inp1_no_chunkPfiiii, @function
_Z26unknown_algo_inp1_no_chunkPfiiii:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z26unknown_algo_inp1_no_chunkPfiiiiPfiiii
	.cfi_endproc
.LFE3667:
	.size	_Z26unknown_algo_inp1_no_chunkPfiiii, .-_Z26unknown_algo_inp1_no_chunkPfiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%d. "
.LC3:
	.string	"%d "
.LC4:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	cmpl	$3, %edi
	jne	.L41
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movl	%eax, %ebx
	jmp	.L24
.L41:
	movl	$128, %ebx
	movl	$128, %ebp
.L24:
	movl	%ebp, %r15d
	movslq	%ebx, %r13
	movl	$4, %esi
	imull	%ebx, %r15d
	movq	%r13, %rdi
	movslq	%r15d, %r8
	movq	%r8, 8(%rsp)
	call	calloc@PLT
	movq	%rax, 16(%rsp)
	leal	0(,%r15,4), %eax
	cltq
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movq	%rax, %r14
	call	cudaMalloc@PLT
	leaq	0(,%r13,4), %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %r8
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movss	.LC0(%rip), %xmm0
.L25:
	cmpl	%ecx, %ebp
	jle	.L27
	movslq	%edx, %rax
	leaq	(%r12,%rax,4), %rsi
	xorl	%eax, %eax
.L28:
	cmpl	%eax, %ebx
	jle	.L46
	movss	%xmm0, (%rsi,%rax,4)
	incq	%rax
	jmp	.L28
.L46:
	incl	%ecx
	addl	%ebp, %edx
	jmp	.L25
.L27:
	movss	.LC0(%rip), %xmm0
	leaq	(%r12,%r8,4), %rdx
	xorl	%eax, %eax
.L29:
	cmpl	%eax, %ebx
	jle	.L47
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	jmp	.L29
.L47:
	cvtsi2ssl	%ebx, %xmm0
	mulss	.LC1(%rip), %xmm0
	call	ceilf@PLT
	cvttss2sil	%xmm0, %r13d
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC1(%rip), %xmm0
	call	ceilf@PLT
	movl	%r13d, 32(%rsp)
	cvttss2sil	%xmm0, %eax
	movl	$1, 40(%rsp)
	movl	$1, 52(%rsp)
	movl	%eax, 36(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 44(%rsp)
	leal	(%r15,%rbx), %eax
	cmpl	$16000, %eax
	jg	.L33
	cmpl	$1, %r15d
	jle	.L33
	movq	(%rsp), %rdx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%r12, %rsi
	leaq	_ZL5c_inp(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	52(%rsp), %ecx
	movl	40(%rsp), %esi
	xorl	%r9d, %r9d
	movq	44(%rsp), %rdx
	movq	32(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	24(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	call	_Z49__device_stub__Z26unknown_algo_inp2_no_chunkPfiiiPfiii
.L34:
	movl	52(%rsp), %ecx
	movq	44(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	24(%rsp), %rdi
	movl	%r15d, %r8d
	movl	%r13d, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	call	_Z50__device_stub__Z26unknown_algo_inp1_no_chunkPfiiiiPfiiii
.L33:
	movq	(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	%r14, %rdi
	xorl	%r15d, %r15d
	movl	$2, %ecx
	xorl	%r13d, %r13d
	call	cudaMemcpy@PLT
.L36:
	cmpl	%r13d, %ebp
	jle	.L48
	movl	%r13d, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	%r15d, %rax
	xorl	%ecx, %ecx
	leaq	(%r14,%rax,4), %r8
.L37:
	cmpl	%ecx, %ebx
	jle	.L49
	cvttss2sil	(%r8,%rcx,4), %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movq	%r8, 8(%rsp)
	movq	%rcx, (%rsp)
	call	__printf_chk@PLT
	movq	(%rsp), %rcx
	movq	8(%rsp), %r8
	incq	%rcx
	jmp	.L37
.L49:
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	incl	%r13d
	addl	%ebp, %r15d
	movl	$2, %edi
	call	__printf_chk@PLT
	jmp	.L36
.L48:
	movq	%r12, %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z26unknown_algo_inp1_no_chunkPfiiii"
.LC6:
	.string	"_Z26unknown_algo_inp2_no_chunkPfiii"
.LC7:
	.string	"_Z23unknown_algo_inp1_chunkPfiiiii"
.LC8:
	.string	"_Z23unknown_algo_inp2_chunkPfS_iiii"
.LC9:
	.string	"c_inp"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z26unknown_algo_inp1_no_chunkPfiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26unknown_algo_inp2_no_chunkPfiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23unknown_algo_inp1_chunkPfiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23unknown_algo_inp2_chunkPfS_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movl	$64000, %r9d
	leaq	_ZL5c_inp(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL5c_inp
	.comm	_ZL5c_inp,64000,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	1031798784
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//optimization homework #4 cs 677 Theodore Jagodits

#include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>

#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
#define GPU_SPEED_LO_LIMIT 1

//add constant memory 
__constant__ float c_inp[MAX_CONST];

//tiling complete
__global__ void unknown_algo_inp2_chunk(float *result, float *inp2, int row, int col, int num_tiles, int chunk){
	//add shared memory
	__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
	//get row col idx
	int tx = blockIdx.x * blockDim.x + threadIdx.x;
	int ty = blockIdx.y * blockDim.y + threadIdx.y;
	float temp = 0.0f;
	unsigned int curr = 0, pos_x;
	
	for(unsigned int count = 0; count < num_tiles; count++){
		//find position
		pos_x = count * TILE_SIZE + threadIdx.x;
		//check bounds and load tile
		if(pos_x < col && ty < row){
			temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = inp2[ty*row + pos_x];
		}
		__syncthreads();
		for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
			if(curr <= tx){
				temp += temp_shared_2[threadIdx.y * TILE_SIZE + tile];
			}
			curr ++;
		}
	}
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

//tiling complete
__global__ void unknown_algo_inp1_chunk(float *result, int row, int col, int num_tiles, int stride, int chunk){
	int tx = blockDim.x * blockIdx.x + threadIdx.x;
	int ty = blockDim.y * blockIdx.y + threadIdx.y;
	
	float temp, local;
	temp = 0.0f;
	if(ty < row && tx < col){
		local = c_inp[ty*row +tx];
		result[ty*row + tx] = temp;
	}
	
	for(int i = 0; i < col; i++){
		temp += local * c_inp[stride + i];
	}
	
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

//tiling complete
__global__ void unknown_algo_inp2_no_chunk(float *result, int row, int col, int num_tiles){
	//add shared memory
	__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
	//get row col idx
	int tx = blockIdx.x * blockDim.x + threadIdx.x;
	int ty = blockIdx.y * blockDim.y + threadIdx.y;
	float temp = 0.0f;
	unsigned int curr = 0, pos_x;
	
	for(unsigned int count = 0; count < num_tiles; count++){
		//find position
		pos_x = count * TILE_SIZE + threadIdx.x;
		//check bounds and load tile
		if(pos_x < col && ty < row){
			temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
		}
		__syncthreads();
		for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
			if(curr <= tx){
				temp += temp_shared_2[threadIdx.y * TILE_SIZE + tile];
			}
			curr ++;
		}
	}
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

//tiling complete no point of tiling here
__global__ void unknown_algo_inp1_no_chunk(float *result, int row, int col, int num_tiles, int stride){
	int tx = blockDim.x * blockIdx.x + threadIdx.x;
	int ty = blockDim.y * blockIdx.y + threadIdx.y;
	
	float temp, local;
	temp = 0.0f;
	if(ty < row && tx < col){
		local = c_inp[ty*row +tx];
		result[ty*row + tx] = temp;
	}
	
	for(int i = 0; i < col; i++){
		temp += local * c_inp[stride + i];
	}
	
	if(ty < row && tx < col){
		result[ty*row + tx] = temp;
	}
}

int main( int argc, char **argv ){
	int row = DEFAULT_ROW;
	int col = DEFAULT_COL;
	if(argc == 3){
		row = atoi(argv[1]);
		col = atoi(argv[2]);
	}
	int num_bytes = row* col * sizeof(float);
	int stride = row * col;
	
	float *h_temp = (float *) calloc(col, sizeof(float)); //store temp results
	float *d_temp = (float *) calloc(col, sizeof(float)); //store temp results
	float *d_result = (float *) malloc(num_bytes);
	float *h_input = (float *) malloc(num_bytes);
	float *h_result = (float *) malloc(num_bytes);
	
	//cudaMalloc(&d_input2, num_bytes);
	hipMalloc(&d_result, num_bytes);
	hipMalloc(&d_temp, col * sizeof(float));
	
	//put in data
	for(int o = 0; o < row; o++){
        for(int p = 0; p < col; p++){
            h_input[row * o + p] = 1.0f;
        }
    }
	// add input 1 to input
	for(int p = 0; p < col; p++){
        h_input[stride + p] = 1.0f;
    }
	
	//declare block and grid size for kernel
	int block_size = TILE_SIZE;
	//make grids x y
	int grid_x = (int)ceil((float)col/block_size);
	int grid_y = (int)ceil((float)row/block_size);
	dim3 dim_grid (grid_x, grid_y);
	dim3 dim_block (block_size, block_size);
	
	//run different configs depending on size
	if(col * row + col> MAX_CONST){ //greater than limit of const mem 
	/*
		float *temp_chunk = (float*) calloc(MAX_CONST,sizeof(float));
		for(int chunk = 0; chunk < (int)ceil((float)(row*col)/MAX_CONST); chunk++){
			for(int i = 0; i < MAX_CONST; i++){
				if(i<stride)
					temp_chunk[i] = h_input[chunk*MAX_CONST + i];
				else
					break;
			}
			cudaMemcpyToSymbol(c_inp, temp_chunk, MAX_CONST);
			unknown_algo_inp2_chunk<<< dim_grid, dim_block >>> (d_result, d_temp, row, col, num_tiles, chunk);
		}
		for(int chunk = 0; chunk < (int)ceil((float)(row*col)/MAX_CONST); chunk++){
			unknown_algo_inp1<<< dim_grid, dim_block >>> (d_result, row, col, 0);
		}
		free(temp_chunk);
		*/
		
	} else if(col * row > GPU_SPEED_LO_LIMIT){//check
		hipMemcpyToSymbol(HIP_SYMBOL(c_inp), h_input, num_bytes);
		unknown_algo_inp2_no_chunk<<< dim_grid, dim_block >>> (d_result, row, col, grid_x);
		unknown_algo_inp1_no_chunk<<< dim_grid, dim_block >>> (d_result, row, col, grid_x, stride);
	} else{ // run one kernel
		//combined_algo<<< dim_grid, dim_block >>> (d_result, row, col, 0);
	}
	
	// Copy result back to host
	hipMemcpy(h_result, d_result, num_bytes, hipMemcpyDeviceToHost);
	
	//print error check
	for(int i = 0; i < row; i++){
		printf("%d. ", i);
		for(int j = 0; j < col; j++){
			printf("%d ", (int)h_result[i*row + j]);
		}
		printf("\n");
	}
	
	free(h_input);
	free(h_result);
	
	hipFree(d_result);
	hipFree(d_temp);
	return 0;
}
	.text
	.file	"algo.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii # -- Begin function _Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii
	.type	_Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii,@function
_Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii: # @_Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23unknown_algo_inp2_chunkPfS_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii, .Lfunc_end0-_Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__unknown_algo_inp1_chunkPfiiiii # -- Begin function _Z38__device_stub__unknown_algo_inp1_chunkPfiiiii
	.type	_Z38__device_stub__unknown_algo_inp1_chunkPfiiiii,@function
_Z38__device_stub__unknown_algo_inp1_chunkPfiiiii: # @_Z38__device_stub__unknown_algo_inp1_chunkPfiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23unknown_algo_inp1_chunkPfiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z38__device_stub__unknown_algo_inp1_chunkPfiiiii, .Lfunc_end1-_Z38__device_stub__unknown_algo_inp1_chunkPfiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii # -- Begin function _Z41__device_stub__unknown_algo_inp2_no_chunkPfiii
	.type	_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii,@function
_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii: # @_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26unknown_algo_inp2_no_chunkPfiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii, .Lfunc_end2-_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii # -- Begin function _Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii
	.type	_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii,@function
_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii: # @_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26unknown_algo_inp1_no_chunkPfiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii, .Lfunc_end3-_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI4_0:
	.long	0x3d800000                      # float 0.0625
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$128, %eax
	movl	$128, %r14d
	cmpl	$3, %edi
	jne	.LBB4_2
# %bb.1:
	movq	%rsi, %r15
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	16(%r15), %rdi
	callq	atoi
                                        # kill: def $eax killed $eax def $rax
.LBB4_2:
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	%r14d, %ecx
	imull	%eax, %ecx
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	leal	(,%rcx,4), %ebx
	movslq	40(%rsp), %r13                  # 4-byte Folded Reload
	movl	$4, %esi
	movq	%r13, %rdi
	callq	calloc
	leaq	56(%rsp), %rcx
	movq	%rax, (%rcx)
	movslq	%ebx, %r12
	movq	40(%rsp), %rbx                  # 8-byte Reload
	movq	%r12, %rdi
	callq	malloc
	leaq	24(%rsp), %rbp
	movq	%rax, (%rbp)
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	%rbp, %rdi
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	callq	hipMalloc
	shlq	$2, %r13
	leaq	56(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movl	%r14d, %ebp
	movl	%ebx, %r12d
	testl	%r14d, %r14d
	jle	.LBB4_8
# %bb.3:                                # %.preheader95.lr.ph
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB4_4:                                # %.preheader95
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_6 Depth 2
	testl	%ebx, %ebx
	jle	.LBB4_7
# %bb.5:                                # %.lr.ph
                                        #   in Loop: Header=BB4_4 Depth=1
	movl	%eax, %edx
	leaq	(%r15,%rdx,4), %rdx
	xorl	%esi, %esi
.LBB4_6:                                #   Parent Loop BB4_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1065353216, (%rdx,%rsi,4)      # imm = 0x3F800000
	incq	%rsi
	cmpq	%rsi, %r12
	jne	.LBB4_6
.LBB4_7:                                # %._crit_edge
                                        #   in Loop: Header=BB4_4 Depth=1
	incq	%rcx
	addl	%r14d, %eax
	cmpq	%rbp, %rcx
	jne	.LBB4_4
.LBB4_8:                                # %.preheader
	testl	%ebx, %ebx
	movq	16(%rsp), %r13                  # 8-byte Reload
	jle	.LBB4_11
# %bb.9:                                # %.lr.ph99.preheader
	movslq	%r13d, %rax
	leaq	(%r15,%rax,4), %rax
	xorl	%ecx, %ecx
.LBB4_10:                               # %.lr.ph99
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rax,%rcx,4)      # imm = 0x3F800000
	incq	%rcx
	cmpq	%rcx, %r12
	jne	.LBB4_10
.LBB4_11:                               # %._crit_edge100
	cvtsi2ss	%ebx, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r14d, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cmpl	$2, %r13d
	jl	.LBB4_17
# %bb.12:                               # %._crit_edge100
	leal	(%rbx,%r13), %eax
	cmpl	$16001, %eax                    # imm = 0x3E81
	jge	.LBB4_17
# %bb.13:
	cvttss2si	8(%rsp), %eax           # 4-byte Folded Reload
	cvttss2si	%xmm0, %r13d
	shlq	$32, %r13
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	orq	%rax, %r13
	movl	$c_inp, %edi
	movq	%r15, %rsi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movq	%r13, %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_15
# %bb.14:
	movq	24(%rsp), %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movq	8(%rsp), %rcx                   # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii
.LBB4_15:
	movq	%r13, %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	16(%rsp), %r8                   # 8-byte Reload
	jne	.LBB4_17
# %bb.16:
	movq	24(%rsp), %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movq	8(%rsp), %rcx                   # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
                                        # kill: def $r8d killed $r8d killed $r8
	callq	_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii
.LBB4_17:
	movq	%r15, 16(%rsp)                  # 8-byte Spill
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%r14d, %r14d
	jle	.LBB4_23
# %bb.18:                               # %.lr.ph107
	xorl	%r15d, %r15d
	xorl	%r13d, %r13d
	movq	%rbp, 64(%rsp)                  # 8-byte Spill
.LBB4_19:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_21 Depth 2
	movl	%r14d, %ebp
	movl	$.L.str, %edi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	printf
	testl	%ebx, %ebx
	jle	.LBB4_22
# %bb.20:                               # %.lr.ph103
                                        #   in Loop: Header=BB4_19 Depth=1
	movl	%r15d, %eax
	movq	32(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbx
	xorl	%r14d, %r14d
.LBB4_21:                               #   Parent Loop BB4_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cvttss2si	(%rbx,%r14,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	%r14, %r12
	jne	.LBB4_21
.LBB4_22:                               # %._crit_edge104
                                        #   in Loop: Header=BB4_19 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r13
	movl	%ebp, %r14d
	addl	%ebp, %r15d
	movq	64(%rsp), %rbp                  # 8-byte Reload
	cmpq	%rbp, %r13
	movq	40(%rsp), %rbx                  # 8-byte Reload
	jne	.LBB4_19
.LBB4_23:                               # %._crit_edge108
	movq	16(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23unknown_algo_inp2_chunkPfS_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23unknown_algo_inp1_chunkPfiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26unknown_algo_inp2_no_chunkPfiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26unknown_algo_inp1_no_chunkPfiiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$c_inp, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$64000, %r9d                    # imm = 0xFA00
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	c_inp,@object                   # @c_inp
	.local	c_inp
	.comm	c_inp,64000,16
	.type	_Z23unknown_algo_inp2_chunkPfS_iiii,@object # @_Z23unknown_algo_inp2_chunkPfS_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z23unknown_algo_inp2_chunkPfS_iiii
	.p2align	3, 0x0
_Z23unknown_algo_inp2_chunkPfS_iiii:
	.quad	_Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii
	.size	_Z23unknown_algo_inp2_chunkPfS_iiii, 8

	.type	_Z23unknown_algo_inp1_chunkPfiiiii,@object # @_Z23unknown_algo_inp1_chunkPfiiiii
	.globl	_Z23unknown_algo_inp1_chunkPfiiiii
	.p2align	3, 0x0
_Z23unknown_algo_inp1_chunkPfiiiii:
	.quad	_Z38__device_stub__unknown_algo_inp1_chunkPfiiiii
	.size	_Z23unknown_algo_inp1_chunkPfiiiii, 8

	.type	_Z26unknown_algo_inp2_no_chunkPfiii,@object # @_Z26unknown_algo_inp2_no_chunkPfiii
	.globl	_Z26unknown_algo_inp2_no_chunkPfiii
	.p2align	3, 0x0
_Z26unknown_algo_inp2_no_chunkPfiii:
	.quad	_Z41__device_stub__unknown_algo_inp2_no_chunkPfiii
	.size	_Z26unknown_algo_inp2_no_chunkPfiii, 8

	.type	_Z26unknown_algo_inp1_no_chunkPfiiii,@object # @_Z26unknown_algo_inp1_no_chunkPfiiii
	.globl	_Z26unknown_algo_inp1_no_chunkPfiiii
	.p2align	3, 0x0
_Z26unknown_algo_inp1_no_chunkPfiiii:
	.quad	_Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii
	.size	_Z26unknown_algo_inp1_no_chunkPfiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d. "
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z23unknown_algo_inp2_chunkPfS_iiii"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z23unknown_algo_inp1_chunkPfiiiii"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z26unknown_algo_inp2_no_chunkPfiii"
	.size	.L__unnamed_3, 36

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z26unknown_algo_inp1_no_chunkPfiiii"
	.size	.L__unnamed_4, 37

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"c_inp"
	.size	.L__unnamed_5, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__unknown_algo_inp2_chunkPfS_iiii
	.addrsig_sym _Z38__device_stub__unknown_algo_inp1_chunkPfiiiii
	.addrsig_sym _Z41__device_stub__unknown_algo_inp2_no_chunkPfiii
	.addrsig_sym _Z41__device_stub__unknown_algo_inp1_no_chunkPfiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym c_inp
	.addrsig_sym _Z23unknown_algo_inp2_chunkPfS_iiii
	.addrsig_sym _Z23unknown_algo_inp1_chunkPfiiiii
	.addrsig_sym _Z26unknown_algo_inp2_no_chunkPfiii
	.addrsig_sym _Z26unknown_algo_inp1_no_chunkPfiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23unknown_algo_inp2_chunkPfS_iiii ; -- Begin function _Z23unknown_algo_inp2_chunkPfS_iiii
	.globl	_Z23unknown_algo_inp2_chunkPfS_iiii
	.p2align	8
	.type	_Z23unknown_algo_inp2_chunkPfS_iiii,@function
_Z23unknown_algo_inp2_chunkPfS_iiii:    ; @_Z23unknown_algo_inp2_chunkPfS_iiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v4, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s0, v[4:5]
	s_and_b32 s0, s2, 0xffff
	s_cmp_eq_u32 s10, 0
	v_mad_u64_u32 v[1:2], null, s14, s0, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 4, v4
	v_mul_lo_u32 v6, v0, s8
	v_lshlrev_b32_e32 v7, 6, v4
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_lshl_u32 v8, v2, v3, 2
	v_mov_b32_e32 v2, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	v_lshl_add_u32 v4, s1, 4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s9, v4
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[4:5]
	v_add_co_u32 v9, s0, s6, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
	global_load_b32 v4, v[9:10], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v4
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, v7
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_5:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s0, s2, s3
	s_mov_b32 s11, exec_lo
	v_cmpx_le_u32_e64 s0, v1
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	ds_load_b32 v9, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v9
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v4, 4, v4
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 16
	s_cbranch_scc0 .LBB0_5
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s1, s1, 1
	s_add_i32 s2, s2, 16
	s_cmp_eq_u32 s1, s10
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_10
.LBB0_9:
	v_mov_b32_e32 v2, 0
.LBB0_10:                               ; %Flow66
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s9, v1
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mad_u64_u32 v[3:4], null, v0, s8, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23unknown_algo_inp2_chunkPfS_iiii
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23unknown_algo_inp2_chunkPfS_iiii, .Lfunc_end0-_Z23unknown_algo_inp2_chunkPfS_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 424
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z23unknown_algo_inp1_chunkPfiiiii ; -- Begin function _Z23unknown_algo_inp1_chunkPfiiiii
	.globl	_Z23unknown_algo_inp1_chunkPfiiiii
	.p2align	8
	.type	_Z23unknown_algo_inp1_chunkPfiiiii,@function
_Z23unknown_algo_inp1_chunkPfiiiii:     ; @_Z23unknown_algo_inp1_chunkPfiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
                                        ; implicit-def: $vgpr2
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s7, v1
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, c_inp@rel32@lo+4
	s_addc_u32 s9, s9, c_inp@rel32@hi+12
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v5, vcc_lo, v3, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v2, v[5:6], off
	v_mov_b32_e32 v5, 0
	global_store_b32 v[3:4], v5, off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s3
	s_cmp_lt_i32 s7, 1
	s_cbranch_scc1 .LBB1_5
; %bb.3:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x14
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, c_inp@rel32@lo+4
	s_addc_u32 s9, s9, c_inp@rel32@hi+12
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s0, s0, s8
	s_addc_u32 s1, s1, s9
.LBB1_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s3, s[0:1], 0x0
	s_add_i32 s7, s7, -1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s7, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v3, s3, v2
	s_cbranch_scc0 .LBB1_4
	s_branch .LBB1_6
.LBB1_5:
	v_mov_b32_e32 v3, 0
.LBB1_6:                                ; %Flow53
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_8
; %bb.7:
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB1_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23unknown_algo_inp1_chunkPfiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z23unknown_algo_inp1_chunkPfiiiii, .Lfunc_end1-_Z23unknown_algo_inp1_chunkPfiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26unknown_algo_inp2_no_chunkPfiii ; -- Begin function _Z26unknown_algo_inp2_no_chunkPfiii
	.globl	_Z26unknown_algo_inp2_no_chunkPfiii
	.p2align	8
	.type	_Z26unknown_algo_inp2_no_chunkPfiii,@function
_Z26unknown_algo_inp2_no_chunkPfiii:    ; @_Z26unknown_algo_inp2_no_chunkPfiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	v_bfe_u32 v4, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	s_cmp_eq_u32 s6, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_cbranch_scc1 .LBB2_9
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 4, v4
	v_mul_lo_u32 v6, v0, s4
	v_lshlrev_b32_e32 v7, 6, v4
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_lshl_u32 v8, v2, v3, 2
	v_mov_b32_e32 v2, 0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, c_inp@rel32@lo+4
	s_addc_u32 s11, s11, c_inp@rel32@hi+12
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_5 Depth 2
	v_lshl_add_u32 v4, s3, 4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s5, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[4:5]
	v_add_co_u32 v9, s2, v9, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s2, s11, v10, s2
	global_load_b32 v4, v[9:10], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v4
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_mov_b32_e32 v4, v7
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_5:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s2, s7, s8
	s_mov_b32 s9, exec_lo
	v_cmpx_le_u32_e64 s2, v1
	s_cbranch_execz .LBB2_7
; %bb.6:                                ;   in Loop: Header=BB2_5 Depth=2
	ds_load_b32 v9, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v9
.LBB2_7:                                ;   in Loop: Header=BB2_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v4, 4, v4
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, 16
	s_cbranch_scc0 .LBB2_5
; %bb.8:                                ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s3, s3, 1
	s_add_i32 s7, s7, 16
	s_cmp_eq_u32 s3, s6
	s_cbranch_scc0 .LBB2_2
	s_branch .LBB2_10
.LBB2_9:
	v_mov_b32_e32 v2, 0
.LBB2_10:                               ; %Flow60
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s5, v1
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_12
; %bb.11:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26unknown_algo_inp2_no_chunkPfiii
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z26unknown_algo_inp2_no_chunkPfiii, .Lfunc_end2-_Z26unknown_algo_inp2_no_chunkPfiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 456
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26unknown_algo_inp1_no_chunkPfiiii ; -- Begin function _Z26unknown_algo_inp1_no_chunkPfiiii
	.globl	_Z26unknown_algo_inp1_no_chunkPfiiii
	.p2align	8
	.type	_Z26unknown_algo_inp1_no_chunkPfiiii,@function
_Z26unknown_algo_inp1_no_chunkPfiiii:   ; @_Z26unknown_algo_inp1_no_chunkPfiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
                                        ; implicit-def: $vgpr2
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s7, v1
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, c_inp@rel32@lo+4
	s_addc_u32 s9, s9, c_inp@rel32@hi+12
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v5, vcc_lo, v3, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v2, v[5:6], off
	v_mov_b32_e32 v5, 0
	global_store_b32 v[3:4], v5, off
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s3
	s_cmp_lt_i32 s7, 1
	s_cbranch_scc1 .LBB3_5
; %bb.3:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x14
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, c_inp@rel32@lo+4
	s_addc_u32 s9, s9, c_inp@rel32@hi+12
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s0, s0, s8
	s_addc_u32 s1, s1, s9
.LBB3_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s3, s[0:1], 0x0
	s_add_i32 s7, s7, -1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s7, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v3, s3, v2
	s_cbranch_scc0 .LBB3_4
	s_branch .LBB3_6
.LBB3_5:
	v_mov_b32_e32 v3, 0
.LBB3_6:                                ; %Flow53
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB3_8
; %bb.7:
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB3_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26unknown_algo_inp1_no_chunkPfiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z26unknown_algo_inp1_no_chunkPfiiii, .Lfunc_end3-_Z26unknown_algo_inp1_no_chunkPfiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	c_inp                   ; @c_inp
	.type	c_inp,@object
	.section	.bss,"aw",@nobits
	.globl	c_inp
	.p2align	4, 0x0
c_inp:
	.zero	64000
	.size	c_inp, 64000

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym c_inp
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23unknown_algo_inp2_chunkPfS_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23unknown_algo_inp2_chunkPfS_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23unknown_algo_inp1_chunkPfiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23unknown_algo_inp1_chunkPfiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
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    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26unknown_algo_inp2_no_chunkPfiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26unknown_algo_inp2_no_chunkPfiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
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    .name:           _Z26unknown_algo_inp1_no_chunkPfiiii
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    .sgpr_spill_count: 0
    .symbol:         _Z26unknown_algo_inp1_no_chunkPfiiii.kd
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
