#define BLOCK_SIZE 512 

__global__ void histogram_kernel(
    float* lats, 
    float* lons, 
    unsigned int* histo_d,
    unsigned int line_count,
    unsigned int histo_row_count, 
    unsigned int histo_col_count,
    float lat_max, 
    float lat_min, 
    float lon_max, 
    float lon_min) 
{
    //Dynamic Shared Memory
    extern __shared__ unsigned int histogram_private[];

    unsigned int histo_size = histo_col_count * histo_row_count;
    
    //Initialize private hisogram
    int i = 0;
    while((blockDim.x * i + threadIdx.x) < histo_size) 
    {
        histogram_private[blockDim.x * i + threadIdx.x] = 0.0f;
        i++;
    }
    __syncthreads();
    //Compute the private histograms
    i = blockDim.x * blockIdx.x + threadIdx.x;
    while(i < line_count) 
    {
        int col = (lats[i] - lat_min) * histo_col_count / (lat_max - lat_min);
        int row = (lons[i] - lon_min) * histo_row_count / (lon_max - lon_min);
        atomicAdd(&(histogram_private[row * histo_col_count + col]), 1);
        i += blockDim.x * gridDim.x;
    }
    __syncthreads();
    //Compute the global histogram
    i = 0;
    while((blockDim.x * i + threadIdx.x) < histo_size) 
    {
        atomicAdd(&(histo_d[blockDim.x * i + threadIdx.x]), histogram_private[blockDim.x * i + threadIdx.x]);
        i++;
    }
}

void histogram(float* lats, 
    float* lons, 
    unsigned int* histo_d, 
    unsigned int line_count,
    unsigned int histo_row_count, 
    unsigned int histo_col_count,
    float lat_max, 
    float lat_min, 
    float lon_max, 
    float lon_min) {

    int MAX_GRID_SIZE = 12;
    int GRID_SIZE = ((line_count - 1) / BLOCK_SIZE) + 1;
    GRID_SIZE = GRID_SIZE > MAX_GRID_SIZE ? MAX_GRID_SIZE : GRID_SIZE;

    dim3 DimGrid(GRID_SIZE, 1, 1);
    dim3 DimBlock(BLOCK_SIZE, 1, 1);

    histogram_kernel<<<DimGrid, DimBlock, histo_col_count * histo_row_count * sizeof(unsigned int)>>>(
        lats,
        lons, 
        histo_d,
        line_count, 
        histo_row_count, 
        histo_col_count, 
        lat_max, 
        lat_min, 
        lon_max, 
        lon_min);

}
	.file	"tmpxft_0022d6a8_00000000-6_kernel_v0.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z16histogram_kernelPfS_PjjjjffffPfS_Pjjjjffff
	.type	_Z47__device_stub__Z16histogram_kernelPfS_PjjjjffffPfS_Pjjjjffff, @function
_Z47__device_stub__Z16histogram_kernelPfS_PjjjjffffPfS_Pjjjjffff:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 36(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 32(%rsp)
	movl	%r9d, 28(%rsp)
	movss	%xmm0, 24(%rsp)
	movss	%xmm1, 20(%rsp)
	movss	%xmm2, 16(%rsp)
	movss	%xmm3, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z16histogram_kernelPfS_Pjjjjffff(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z47__device_stub__Z16histogram_kernelPfS_PjjjjffffPfS_Pjjjjffff, .-_Z47__device_stub__Z16histogram_kernelPfS_PjjjjffffPfS_Pjjjjffff
	.globl	_Z16histogram_kernelPfS_Pjjjjffff
	.type	_Z16histogram_kernelPfS_Pjjjjffff, @function
_Z16histogram_kernelPfS_Pjjjjffff:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z16histogram_kernelPfS_PjjjjffffPfS_Pjjjjffff
	.cfi_endproc
.LFE2034:
	.size	_Z16histogram_kernelPfS_Pjjjjffff, .-_Z16histogram_kernelPfS_Pjjjjffff
	.globl	_Z9histogramPfS_Pjjjjffff
	.type	_Z9histogramPfS_Pjjjjffff, @function
_Z9histogramPfS_Pjjjjffff:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leal	-1(%rcx), %eax
	movl	%r9d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	shrl	$9, %eax
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	incl	%eax
	movq	%rdx, %r13
	movl	$12, %edx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	movl	$1, %ecx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	cmpl	%edx, %eax
	cmova	%edx, %eax
	movl	$8388609, %edx
	movss	%xmm0, 12(%rsp)
	salq	$9, %rdx
	movss	%xmm1, 8(%rsp)
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movl	%r9d, %eax
	movl	32(%rsp), %esi
	xorl	%r9d, %r9d
	imull	%r8d, %eax
	movq	24(%rsp), %rdi
	movss	%xmm2, 4(%rsp)
	movss	%xmm3, (%rsp)
	leaq	0(,%rax,4), %r8
	call	__cudaPushCallConfiguration@PLT
	movss	(%rsp), %xmm3
	movss	4(%rsp), %xmm2
	testl	%eax, %eax
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	jne	.L8
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r15d, %r9d
	movl	%r14d, %r8d
	movl	%ebx, %ecx
	movq	%r13, %rdx
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z47__device_stub__Z16histogram_kernelPfS_PjjjjffffPfS_Pjjjjffff
.L8:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z9histogramPfS_Pjjjjffff, .-_Z9histogramPfS_Pjjjjffff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16histogram_kernelPfS_Pjjjjffff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16histogram_kernelPfS_Pjjjjffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define BLOCK_SIZE 512 

__global__ void histogram_kernel(
    float* lats, 
    float* lons, 
    unsigned int* histo_d,
    unsigned int line_count,
    unsigned int histo_row_count, 
    unsigned int histo_col_count,
    float lat_max, 
    float lat_min, 
    float lon_max, 
    float lon_min) 
{
    //Dynamic Shared Memory
    extern __shared__ unsigned int histogram_private[];

    unsigned int histo_size = histo_col_count * histo_row_count;
    
    //Initialize private hisogram
    int i = 0;
    while((blockDim.x * i + threadIdx.x) < histo_size) 
    {
        histogram_private[blockDim.x * i + threadIdx.x] = 0.0f;
        i++;
    }
    __syncthreads();
    //Compute the private histograms
    i = blockDim.x * blockIdx.x + threadIdx.x;
    while(i < line_count) 
    {
        int col = (lats[i] - lat_min) * histo_col_count / (lat_max - lat_min);
        int row = (lons[i] - lon_min) * histo_row_count / (lon_max - lon_min);
        atomicAdd(&(histogram_private[row * histo_col_count + col]), 1);
        i += blockDim.x * gridDim.x;
    }
    __syncthreads();
    //Compute the global histogram
    i = 0;
    while((blockDim.x * i + threadIdx.x) < histo_size) 
    {
        atomicAdd(&(histo_d[blockDim.x * i + threadIdx.x]), histogram_private[blockDim.x * i + threadIdx.x]);
        i++;
    }
}

void histogram(float* lats, 
    float* lons, 
    unsigned int* histo_d, 
    unsigned int line_count,
    unsigned int histo_row_count, 
    unsigned int histo_col_count,
    float lat_max, 
    float lat_min, 
    float lon_max, 
    float lon_min) {

    int MAX_GRID_SIZE = 12;
    int GRID_SIZE = ((line_count - 1) / BLOCK_SIZE) + 1;
    GRID_SIZE = GRID_SIZE > MAX_GRID_SIZE ? MAX_GRID_SIZE : GRID_SIZE;

    dim3 DimGrid(GRID_SIZE, 1, 1);
    dim3 DimBlock(BLOCK_SIZE, 1, 1);

    histogram_kernel<<<DimGrid, DimBlock, histo_col_count * histo_row_count * sizeof(unsigned int)>>>(
        lats,
        lons, 
        histo_d,
        line_count, 
        histo_row_count, 
        histo_col_count, 
        lat_max, 
        lat_min, 
        lon_max, 
        lon_min);

}
	.text
	.file	"kernel_v0.hip"
	.globl	_Z31__device_stub__histogram_kernelPfS_Pjjjjffff # -- Begin function _Z31__device_stub__histogram_kernelPfS_Pjjjjffff
	.type	_Z31__device_stub__histogram_kernelPfS_Pjjjjffff,@function
_Z31__device_stub__histogram_kernelPfS_Pjjjjffff: # @_Z31__device_stub__histogram_kernelPfS_Pjjjjffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	36(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	28(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	24(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	20(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	16(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	12(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	48(%rsp), %r12
	leaq	40(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16histogram_kernelPfS_Pjjjjffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__histogram_kernelPfS_Pjjjjffff, .Lfunc_end0-_Z31__device_stub__histogram_kernelPfS_Pjjjjffff
	.cfi_endproc
                                        # -- End function
	.globl	_Z9histogramPfS_Pjjjjffff       # -- Begin function _Z9histogramPfS_Pjjjjffff
	.type	_Z9histogramPfS_Pjjjjffff,@function
_Z9histogramPfS_Pjjjjffff:              # @_Z9histogramPfS_Pjjjjffff
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm3, 20(%rsp)                 # 4-byte Spill
	movss	%xmm2, 16(%rsp)                 # 4-byte Spill
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movl	%r9d, %ebx
	movl	%r8d, %ebp
	movl	%ecx, %r14d
	movq	%rdx, %r15
	movq	%rsi, %r12
	movq	%rdi, %r13
	leal	-1(%r14), %eax
	shrl	$9, %eax
	cmpl	$11, %eax
	movl	$11, %ecx
	cmovbl	%eax, %ecx
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	leaq	(%rdx,%rcx), %rdi
	incq	%rdi
	movl	%r9d, %r8d
	imull	%ebp, %r8d
	shlq	$2, %r8
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 80
	movq	%r13, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movl	%ebx, %r9d
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	16(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	20(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z31__device_stub__histogram_kernelPfS_Pjjjjffff # TAILCALL
.Lfunc_end1:
	.size	_Z9histogramPfS_Pjjjjffff, .Lfunc_end1-_Z9histogramPfS_Pjjjjffff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16histogram_kernelPfS_Pjjjjffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16histogram_kernelPfS_Pjjjjffff,@object # @_Z16histogram_kernelPfS_Pjjjjffff
	.section	.rodata,"a",@progbits
	.globl	_Z16histogram_kernelPfS_Pjjjjffff
	.p2align	3, 0x0
_Z16histogram_kernelPfS_Pjjjjffff:
	.quad	_Z31__device_stub__histogram_kernelPfS_Pjjjjffff
	.size	_Z16histogram_kernelPfS_Pjjjjffff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16histogram_kernelPfS_Pjjjjffff"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__histogram_kernelPfS_Pjjjjffff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16histogram_kernelPfS_Pjjjjffff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16histogram_kernelPfS_Pjjjjffff ; -- Begin function _Z16histogram_kernelPfS_Pjjjjffff
	.globl	_Z16histogram_kernelPfS_Pjjjjffff
	.p2align	8
	.type	_Z16histogram_kernelPfS_Pjjjjffff,@function
_Z16histogram_kernelPfS_Pjjjjffff:      ; @_Z16histogram_kernelPfS_Pjjjjffff
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_load_b32 s11, s[0:1], 0x44
	v_lshl_add_u32 v3, v0, 2, 0
	s_add_u32 s20, s0, 56
	s_addc_u32 s21, s1, 0
	s_mul_i32 s3, s6, s5
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s11, 0xffff
	v_cmp_gt_u32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s12, s2
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	v_lshl_add_u32 v1, v0, 2, 0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v4, v0
	s_mov_b32 s13, 0
	s_lshl_b32 s14, s11, 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s11, v4
	ds_store_b32 v1, v2
	v_add_nc_u32_e32 v1, s14, v1
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s12
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e64 s4, v1
	s_cbranch_execz .LBB0_6
; %bb.4:                                ; %.lr.ph41
	s_load_b32 s0, s[20:21], 0x0
	v_cvt_f32_u32_e32 v4, s6
	v_sub_f32_e64 v5, s7, s8
	v_cvt_f32_u32_e32 v6, s5
	v_sub_f32_e64 v7, s9, s10
	v_mov_b32_e32 v8, 1
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s5, s0, s11
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	v_add_co_u32 v11, vcc_lo, s16, v9
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s18, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v10, vcc_lo
	global_load_b32 v2, v[11:12], off
	global_load_b32 v9, v[9:10], off
	s_waitcnt vmcnt(0)
	v_dual_subrev_f32 v2, s8, v2 :: v_dual_subrev_f32 v9, s10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v9, v9, v6
	v_div_scale_f32 v10, null, v5, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v11, null, v7, v7, v9
	v_div_scale_f32 v16, vcc_lo, v2, v5, v2
	v_rcp_f32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v13, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v10, v12, 1.0
	v_fma_f32 v15, -v11, v13, 1.0
	v_dual_fmac_f32 v12, v14, v12 :: v_dual_fmac_f32 v13, v15, v13
	v_div_scale_f32 v14, s0, v9, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v16, v12
	v_mul_f32_e32 v17, v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, -v10, v15, v16
	v_fma_f32 v19, -v11, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v18, v12
	v_fmac_f32_e32 v17, v19, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v10, v15, v16
	v_fma_f32 v11, -v11, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v10, v12, v15
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v11, v11, v13, v17
	v_cmp_le_u32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v2, v10, v5, v2
	v_div_fixup_f32 v9, v11, v7, v9
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v2, v2
	v_cvt_i32_f32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v11, s6, v[2:3]
	v_lshl_add_u32 v2, v9, 2, 0
	ds_add_u32 v2, v8
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
.LBB0_6:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_9
; %bb.7:                                ; %.lr.ph45.preheader
	v_mov_b32_e32 v1, 0
	s_mov_b32 s0, 0
	s_lshl_b32 s1, s11, 2
.LBB0_8:                                ; %.lr.ph45
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v2, v3
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_nc_u32_e32 v0, s11, v0
	v_add_nc_u32_e32 v3, s1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v[4:5], v2, off
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_8
.LBB0_9:                                ; %._crit_edge46
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16histogram_kernelPfS_Pjjjjffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16histogram_kernelPfS_Pjjjjffff, .Lfunc_end0-_Z16histogram_kernelPfS_Pjjjjffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 696
; NumSgprs: 24
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym histogram_private
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16histogram_kernelPfS_Pjjjjffff
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z16histogram_kernelPfS_Pjjjjffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
