#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
// #include<time.h>
#include<float.h>

__constant__ int FIL[32*5*5];

__global__ void conv1(unsigned int *picd, int *resultd){
  int i,j,k,l;
  int sum, offset;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  offset = l*25;
  int xsize = 28;
  int filterdim = 5;
  k=0;
  sum =0;
  if(i<(xsize -filterdim +1)&& j<(xsize -filterdim +1)){
    sum = FIL[offset + k]*picd[ xsize * (i) + j ] + FIL[offset+ k+1]*picd[ xsize*(i) + (j+1) ]
      + FIL[offset+ k+2]*picd[ xsize * (i)+(j+2)] + FIL[offset+k+3]*picd[xsize * (i)+(j+3)]
      + FIL[offset+k+4]*picd[ xsize * (i)+(j+4)]+ FIL[offset+ k+5]*picd[ xsize*(i+1)+(j) ]
      + FIL[offset+k+6]*picd[ xsize * (i+1) + (j+1) ] + FIL[offset+ k+7]*picd[ xsize*(i+1) + (j+2) ] +
      FIL[offset+k+8]*picd[ xsize*(i+1) + (j+3) ] + FIL[offset+k+9]*picd[ xsize*(i+1) + (j+4) ] +
      FIL[offset+k+10]*picd[ xsize*(i+2) + (j) ]	+ FIL[offset+k+11]*picd[ xsize * (i+2) + (j+1) ] +
      FIL[offset+k+12]*picd[ xsize*(i+2) + (j+2)] + FIL[offset+k+13]*picd[ xsize*(i+2) + (j+3)]
      +FIL[offset+k+14]*picd[ xsize*(i+2) + (j+4)] + FIL[offset +k+15]*picd[ xsize*(i+3) + (j)]
      + FIL[offset+k+16]*picd[ xsize*(i+3) + (j+1)] + FIL[offset+k+17]*picd[ xsize*(i+3) + (j+2)]
      + FIL[offset+k+18]*picd[ xsize*(i+3) + (j+3)] + FIL[offset+k+19]*picd[ xsize*(i+3) + (j+4)]
      + FIL[offset+k+20]*picd[ xsize*(i+4) + (j)] +FIL[offset+k+21]*picd[ xsize*(i+3) + (j+1)]
      + FIL[offset+k+22]*picd[ xsize*(i+4) + (j+2)] + FIL[offset+k+23]*picd[ xsize*(i+4) + (j+3)]
      + FIL[offset+ k+24]*picd[ xsize*(i+4) + (j+4)];

      resultd[l*(xsize -filterdim +1)*(xsize -filterdim +1) + i*(xsize - filterdim +1)+j] = sum;
      //printf("resultgpu[%d][%d]=%d\n",l,i*(xsize - filterdim +1)+j,resulth[l*(xsize -filterdim +1)*(xsize -filterdim +1) + i*(xsize - filterdim +1)+j]);
  }
}

__global__ void maxpooling(int *maxip1d, int *maxop1d){

  int i,j,l;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  int xsize = 28;
  int filterdim = 5;
  if(i<((xsize-filterdim+1)/2)&&(j<((xsize-filterdim+1)/2))){
    int a,b,c,d,index, max1, max2;
    index = l*((xsize -filterdim +1)*(xsize -filterdim +1))+ threadIdx.x*2 + threadIdx.y*2*(xsize -filterdim +1);
    a = maxip1d[index];
    b = maxip1d[index +1];
    c = maxip1d[index+(xsize-filterdim+1)];
    d = maxip1d[index + (xsize-filterdim+2)];
    if(a>b){
      max1 = a;
    }
    else{
      max1 = b;
    }
    if(c>d){
      max2 = c;
    }
    else{
      max2 = d;
    }
    if(max1>max2){
      maxop1d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j]=max1;
    }
    else{
      maxop1d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j] = max2;
    }
  }
}

__global__ void conv2(int *cip2d, int *filter2d, int *cop2d){
  int i,j,l,sum;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  int lstar;
  lstar = l*800;
  sum = 0;
  int k =0;
  int di = 12;
  int disquare = di*di;
  int m;
  if(i<8 && j<8){
    for(m = 0; m<32; m++){
      sum = sum + filter2d[lstar + k]*cip2d[(m*disquare)+ (di*i) + j] + filter2d[lstar + k+1]*cip2d[(m*disquare)+ di*(i) + (j+1)]
        + filter2d[lstar+ k+2]*cip2d[(m*disquare)+ di*(i)+(j+2)] + filter2d[lstar +k+3]*cip2d[(m*disquare)+ di*(i)+(j+3)]
        + filter2d[lstar+k+4]*cip2d[(m*disquare)+ di*(i)+(j+4)]+ filter2d[lstar+ k+5]*cip2d[(m*disquare)+ di*(i+1)+(j)]
        + filter2d[lstar +k+6]*cip2d[(m*disquare)+ di* (i+1) + (j+1) ] + filter2d[lstar+ k+7]*cip2d[(m*disquare)+ di*(i+1)+(j+2)]
        + filter2d[lstar+k+8]*cip2d[(m*disquare)+ di*(i+1) + (j+3) ] + filter2d[lstar +k+9]*cip2d[(m*disquare)+ di*(i+1) +(j+4)]
        + filter2d[lstar+k+10]*cip2d[(m*disquare)+ di*(i+2) +(j)]	+ filter2d[lstar+k+11]*cip2d[(m*disquare)+ di* (i+2) + (j+1)]
        + filter2d[lstar+k+12]*cip2d[(m*disquare)+ di*(i+2) + (j+2)] +filter2d[lstar+k+13]*cip2d[(m*disquare)+ di*(i+2)+(j+3)]
        + filter2d[lstar+k+14]*cip2d[(m*disquare)+ di*(i+2)+(j+4)]+filter2d[lstar+k+15]*cip2d[(m*disquare)+ di*(i+3)+(j)]
        + filter2d[lstar+k+16]*cip2d[(m*disquare)+ di*(i+3)+(j+1)]+filter2d[lstar+k+17]*cip2d[(m*disquare)+ di*(i+3)+(j+2)]
        + filter2d[lstar+k+18]*cip2d[(m*disquare)+ di*(i+3)+(j+3)] + filter2d[lstar+k+19]*cip2d[(m*disquare)+di*(i+3)+(j+4)]
        + filter2d[lstar+k+20]*cip2d[(m*disquare)+ di*(i+4)+(j)] +filter2d[lstar+k+21]*cip2d[(m*disquare)+ di*(i+3)+(j+1)]
        + filter2d[lstar +k+22]*cip2d[(m*disquare)+ di*(i+4)+(j+2)] + filter2d[lstar+k+23]*cip2d[(m*disquare)+ di*(i+4)+(j+3)]
        + filter2d[lstar+ k+24]*cip2d[(m*disquare)+ di*(i+4) + (j+4)];

      k+=25;
    }
    cop2d[l*64+i*8+j] = sum;
    // printf("resultdevice[%d][%d]:%d\n",l,i*8+j,cop2d[l*64+i*8+j]);
  }
}

__global__ void maxpool(int *maxip2d, int *maxop2d){

  int i,j,l;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  int xsize = 12;
  int filterdim = 5;
  if(i<((xsize-filterdim+1)/2)&&(j<((xsize-filterdim+1)/2))){
    int a,b,c,d,index, max1, max2;
    index = l*((xsize -filterdim +1)*(xsize -filterdim +1))+ threadIdx.x*2 + threadIdx.y*2*(xsize -filterdim +1);
    a = maxip2d[index];
    b = maxip2d[index +1];
    c = maxip2d[index+(xsize-filterdim+1)];
    d = maxip2d[index + (xsize-filterdim+2)];
    if(a>b){
      max1 = a;
    }
    else{
      max1 = b;
    }
    if(c>d){
      max2 = c;
    }
    else{
      max2 = d;
    }
    if(max1>max2){
      maxop2d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j]=max1;
    }
    else{
      maxop2d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j] = max2;
    }
  }
}

int main(int argc, char **argv){
  int xsize;
  int filterdim;
  int numfilters;
  int numfilters1;
  xsize = 28;
  filterdim = 5;
  numfilters = 32;
  numfilters1 = 64;

  /*Numbytes required for initial image*/
  int numbytes = xsize*xsize*sizeof(int);
  /*Numbytes require for the output of first convolution layer*/
  int numbytes2 = (xsize-filterdim+1)*(xsize-filterdim+1)*sizeof(int); //24x24
  /**Numbytes required for output of first maxpool layer**/
  int numbytes3 = ((xsize-filterdim+1)*(xsize-filterdim+1)/4)*sizeof(int); //12x12
  /*Numbytes required for the output of second convolution layer*/
  int numbytes4 = ((xsize-filterdim+1)/2 - filterdim + 1)*((xsize-filterdim+1)/2 - filterdim + 1)*sizeof(int);//8x8
  /*Numbytes required for the output of second maxpool layer*/
  int numbytes5 = (numbytes4/4)*sizeof(int);//4x4

  /*Image on host side*/
  /*Ip and op to first conv layer*/
  unsigned int *pic = (unsigned int *)malloc(numbytes);
  int *result;
  int filter[numfilters*filterdim*filterdim];
  /*Ip and op to first maxpool layer*/
  int *maxip1;
  int *maxop1;
  /*Ip and op of second conv layer*/
  int *cip2;
  int *cop2;
  int *filter2;
  /*ip and op to second maxpool layer*/
  int *maxip2;
  int *maxop2;

  /*Device side variables*/
  unsigned int *picd;
  int *resultd;
  /*Ip and op to first maxpool layer*/
  int *maxip1d;
  int *maxop1d;
  /*Ip and op of second conv layer*/
  int *cip2d;
  int *cop2d;
  int *filter2d;
  /*ip and op to second maxpool layer*/
  int *maxip2d;
  int *maxop2d;

  result = (int *)malloc(numfilters*numbytes2);
  maxip1 = (int *)malloc(numfilters*numbytes2);
  maxop1 = (int *)malloc(numfilters*numbytes3);
  cip2 = (int *)malloc(numfilters*numbytes3);
  cop2 = (int *)malloc(numfilters1*numbytes4);
  filter2 = (int *)malloc(numfilters1*numfilters*filterdim*filterdim*sizeof(int));
  maxip2 = (int *)malloc(numfilters1*numbytes4);
  maxop2 = (int *)malloc(numfilters1*numbytes5);

  cudaMalloc(&picd, numbytes);
  cudaMalloc(&resultd, numfilters*numbytes2);
  cudaMalloc(&maxip1d, numfilters*numbytes2);
  cudaMalloc(&maxop1d, numfilters*numbytes3);
  cudaMalloc(&cip2d, numfilters*numbytes3);
  cudaMalloc(&cop2d, numfilters1*numbytes4);
  cudaMalloc(&filter2d, numfilters1*numfilters*filterdim*filterdim*sizeof(int));
  cudaMalloc(&maxip2d, numfilters1*numbytes4);
  cudaMalloc(&maxop2d, numfilters1*numbytes5);

  /*Initializing the image on host side*/
  /*Should modify to later on read in image*/
  int i,j,k,l,count,dimx;
  for (i=0; i<xsize; i++) {
   for (j=0; j<xsize; j++) {
     pic[i*xsize + j] = 1;
     //printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
   }
   //  printf("\n");
  }

  /*Initializing the filter for first conv layer to a value*/
  /*TO DO : Read in filter from a file */
  for(int k=0;k<numfilters;k++){
   for (int i=0; i<filterdim; i++) {
     for (int j=0; j<filterdim; j++){
       filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
       // printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
     }
   }
 }

 /*Initializing the filter for second conv layer to a value*/
 /*TO DO : Read in filter from a file */
 for(int k=0;k<numfilters1;k++){
   for(int m= 0; m<numfilters;m++){
     for (int i=0; i<filterdim; i++) {
       for (int j=0; j<filterdim; j++){
         filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
         // printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
       }
     }
   }
   // printf("\n");
 }

 dim3 dimGrid (32);
 dim3 dimBlock (32,32);

 cudaMemcpy(picd,pic,numbytes, cudaMemcpyHostToDevice);
 cudaMemcpyToSymbol(FIL, filter, numfilters*filterdim*filterdim*sizeof(int));

 conv1<<<dimGrid, dimBlock>>>(picd,resultd);

 cudaMemcpy(result,resultd,numfilters*numbytes2,cudaMemcpyDeviceToHost);

 dim3 dimBlock1 (16,16);
 cudaMemcpy(maxip1d, result,numfilters*numbytes2, cudaMemcpyHostToDevice);

 maxpooling<<<dimGrid, dimBlock1>>>(maxip1d, maxop1d);

 cudaMemcpy(maxop1, maxop1d, numfilters*numbytes3, cudaMemcpyDeviceToHost);

 cudaMemcpy(cip2d, maxop1,numfilters*numbytes3,cudaMemcpyHostToDevice);
 cudaMemcpy(filter2d, filter2,numfilters1*numfilters*filterdim*filterdim*sizeof(int), cudaMemcpyHostToDevice);

 dim3 dimGrid2(64);
 dim3 dimBlock2(8,8);

 conv2<<<dimGrid2, dimBlock2>>>(cip2d, filter2d, cop2d);

 cudaMemcpy(cop2, cop2d,numfilters1*numbytes4,cudaMemcpyDeviceToHost);

 cudaMemcpy(maxip2d, cop2,numfilters1*numbytes4,cudaMemcpyHostToDevice);

 maxpool<<<dimGrid2, dimBlock2>>>(maxip2d, maxop2d);

 cudaMemcpy(maxop2, maxop2d, numfilters*numbytes5, cudaMemcpyDeviceToHost);

 for(k=0;k<numfilters1;k++){
   for(i=0;i<4;i++){
     for(j=0;j<4;j++){
       printf("maxpool[%d][%d]:%d\t",k,i*4+j, maxop2[k*16+i*4+j]);
     }
     printf("\n");
   }
   printf("\n\n");
 }

}

	.file	"tmpxft_00209d9a_00000000-6_GpuV1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0:
.LFB2184:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2184:
	.size	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	.globl	_Z26__device_stub__Z5conv1PjPiPjPi
	.type	_Z26__device_stub__Z5conv1PjPiPjPi, @function
_Z26__device_stub__Z5conv1PjPiPjPi:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5conv1PjPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z26__device_stub__Z5conv1PjPiPjPi, .-_Z26__device_stub__Z5conv1PjPiPjPi
	.globl	_Z5conv1PjPi
	.type	_Z5conv1PjPi, @function
_Z5conv1PjPi:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z5conv1PjPiPjPi
	.cfi_endproc
.LFE2057:
	.size	_Z5conv1PjPi, .-_Z5conv1PjPi
	.globl	_Z32__device_stub__Z10maxpoolingPiS_PiS_
	.type	_Z32__device_stub__Z10maxpoolingPiS_PiS_, @function
_Z32__device_stub__Z10maxpoolingPiS_PiS_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10maxpoolingPiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L9:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z32__device_stub__Z10maxpoolingPiS_PiS_, .-_Z32__device_stub__Z10maxpoolingPiS_PiS_
	.globl	_Z10maxpoolingPiS_
	.type	_Z10maxpoolingPiS_, @function
_Z10maxpoolingPiS_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10maxpoolingPiS_PiS_
	.cfi_endproc
.LFE2059:
	.size	_Z10maxpoolingPiS_, .-_Z10maxpoolingPiS_
	.globl	_Z28__device_stub__Z5conv2PiS_S_PiS_S_
	.type	_Z28__device_stub__Z5conv2PiS_S_PiS_S_, @function
_Z28__device_stub__Z5conv2PiS_S_PiS_S_:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z5conv2PiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L14:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z28__device_stub__Z5conv2PiS_S_PiS_S_, .-_Z28__device_stub__Z5conv2PiS_S_PiS_S_
	.globl	_Z5conv2PiS_S_
	.type	_Z5conv2PiS_S_, @function
_Z5conv2PiS_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z5conv2PiS_S_PiS_S_
	.cfi_endproc
.LFE2061:
	.size	_Z5conv2PiS_S_, .-_Z5conv2PiS_S_
	.globl	_Z28__device_stub__Z7maxpoolPiS_PiS_
	.type	_Z28__device_stub__Z7maxpoolPiS_PiS_, @function
_Z28__device_stub__Z7maxpoolPiS_PiS_:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7maxpoolPiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L19:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z28__device_stub__Z7maxpoolPiS_PiS_, .-_Z28__device_stub__Z7maxpoolPiS_PiS_
	.globl	_Z7maxpoolPiS_
	.type	_Z7maxpoolPiS_, @function
_Z7maxpoolPiS_:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7maxpoolPiS_PiS_
	.cfi_endproc
.LFE2063:
	.size	_Z7maxpoolPiS_, .-_Z7maxpoolPiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"maxpool[%d][%d]:%d\t"
.LC1:
	.string	"\n"
.LC2:
	.string	"\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$3136, %edi
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$168, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	call	malloc@PLT
	movq	%rax, %r15
	movq	%rsp, %rax
.L25:
	cmpq	%rax, %rsp
	je	.L26
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L25
.L26:
	subq	$3200, %rsp
	orq	$0, 3192(%rsp)
	movl	$73728, %edi
	movq	%rsp, -208(%rbp)
	call	malloc@PLT
	movl	$18432, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$16384, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$204800, %edi
	movq	%rax, -200(%rbp)
	call	malloc@PLT
	movl	$16384, %edi
	movq	%rax, %r12
	call	malloc@PLT
	leaq	-192(%rbp), %rdi
	movl	$3136, %esi
	movq	%rax, %rbx
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-184(%rbp), %rdi
	movl	$73728, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-176(%rbp), %rdi
	movl	$73728, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-168(%rbp), %rdi
	movl	$18432, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-160(%rbp), %rdi
	movl	$18432, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-152(%rbp), %rdi
	movl	$16384, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-144(%rbp), %rdi
	movl	$204800, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-136(%rbp), %rdi
	movl	$16384, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	leaq	-128(%rbp), %rdi
	movl	$16384, %esi
	call	_Z10cudaMallocIjE9cudaErrorPPT_m.isra.0
	movq	%r15, %rcx
	xorl	%edx, %edx
.L28:
	xorl	%eax, %eax
.L29:
	movl	$1, (%rcx,%rax,4)
	incq	%rax
	cmpq	$28, %rax
	jne	.L29
	addl	$28, %edx
	addq	$112, %rcx
	cmpl	$784, %edx
	jne	.L28
	movq	-208(%rbp), %rcx
	xorl	%esi, %esi
.L32:
	movq	%rcx, %rax
	movl	$5, %edx
.L31:
	movl	$1, (%rax)
	addq	$20, %rax
	movl	$1, -16(%rax)
	movl	$1, -12(%rax)
	movl	$1, -8(%rax)
	movl	$1, -4(%rax)
	decl	%edx
	jne	.L31
	addl	$25, %esi
	addq	$100, %rcx
	cmpl	$800, %esi
	jne	.L32
	movq	%r12, %r8
.L33:
	movq	%r8, %rdi
	movl	%edx, %eax
	movl	$32, %esi
.L39:
	movq	%rdi, %r9
	leal	25(%rax), %r10d
.L37:
	xorl	%ecx, %ecx
.L34:
	movl	$1, (%r9,%rcx,4)
	incq	%rcx
	cmpq	$5, %rcx
	jne	.L34
	addl	$5, %eax
	addq	$20, %r9
	cmpl	%r10d, %eax
	jne	.L37
	addq	$100, %rdi
	decl	%esi
	jne	.L39
	addl	$800, %edx
	addq	$3200, %r8
	cmpl	$51200, %edx
	jne	.L33
	movl	$134217729, %eax
	movq	-192(%rbp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	salq	$5, %rax
	movl	$3136, %edx
	movl	$1, -108(%rbp)
	movq	%rax, -116(%rbp)
	movabsq	$137438953504, %rax
	movq	%rax, -104(%rbp)
	movl	$1, -96(%rbp)
	call	cudaMemcpy@PLT
	movq	-208(%rbp), %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movl	$3200, %edx
	leaq	_ZL3FIL(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	-96(%rbp), %ecx
	movq	-104(%rbp), %rdx
	xorl	%r9d, %r9d
	movq	-116(%rbp), %rdi
	movl	-108(%rbp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	-184(%rbp), %rsi
	movq	-192(%rbp), %rdi
	call	_Z26__device_stub__Z5conv1PjPiPjPi
.L40:
	movq	-184(%rbp), %rsi
	movl	$2, %ecx
	movl	$73728, %edx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movq	-176(%rbp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movabsq	$68719476752, %rax
	movl	$73728, %edx
	movl	$1, -84(%rbp)
	movq	%rax, -92(%rbp)
	call	cudaMemcpy@PLT
	movl	-84(%rbp), %ecx
	movq	-92(%rbp), %rdx
	xorl	%r9d, %r9d
	movq	-116(%rbp), %rdi
	movl	-108(%rbp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	movq	-168(%rbp), %rsi
	movq	-176(%rbp), %rdi
	call	_Z32__device_stub__Z10maxpoolingPiS_PiS_
.L41:
	movq	-168(%rbp), %rsi
	movl	$2, %ecx
	movl	$18432, %edx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	-160(%rbp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$18432, %edx
	call	cudaMemcpy@PLT
	movq	-144(%rbp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$204800, %edx
	call	cudaMemcpy@PLT
	movl	$67108865, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$6, %rdi
	movl	$1, %ecx
	movabsq	$34359738376, %rdx
	movl	$1, %esi
	movq	%rdi, -80(%rbp)
	movl	$1, -72(%rbp)
	movq	%rdx, -68(%rbp)
	movl	$1, -60(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	-152(%rbp), %rdx
	movq	-144(%rbp), %rsi
	movq	-160(%rbp), %rdi
	call	_Z28__device_stub__Z5conv2PiS_S_PiS_S_
.L42:
	movq	-152(%rbp), %rsi
	movl	$2, %ecx
	movl	$16384, %edx
	movq	-200(%rbp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$16384, %edx
	movq	-200(%rbp), %rsi
	movq	-136(%rbp), %rdi
	call	cudaMemcpy@PLT
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	xorl	%r9d, %r9d
	movq	-80(%rbp), %rdi
	movl	-72(%rbp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	movq	-128(%rbp), %rsi
	movq	-136(%rbp), %rdi
	call	_Z28__device_stub__Z7maxpoolPiS_PiS_
.L43:
	movq	-128(%rbp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%r13d, %r13d
	movl	$8192, %edx
	call	cudaMemcpy@PLT
.L44:
	movq	%r13, %r12
	movl	%r13d, -200(%rbp)
	xorl	%r14d, %r14d
	salq	$6, %r12
	addq	%rbx, %r12
.L48:
	xorl	%r15d, %r15d
.L45:
	movl	(%r12,%r15,4), %r8d
	movl	-200(%rbp), %edx
	leal	(%r14,%r15), %ecx
	xorl	%eax, %eax
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	incq	%r15
	call	__printf_chk@PLT
	cmpq	$4, %r15
	jne	.L45
	movl	$2, %edi
	xorl	%eax, %eax
	addl	$4, %r14d
	addq	$16, %r12
	leaq	.LC1(%rip), %rsi
	call	__printf_chk@PLT
	cmpl	$16, %r14d
	jne	.L48
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	cmpq	$64, %r13
	jne	.L44
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z7maxpoolPiS_"
.LC4:
	.string	"_Z5conv2PiS_S_"
.LC5:
	.string	"_Z10maxpoolingPiS_"
.LC6:
	.string	"_Z5conv1PjPi"
.LC7:
	.string	"FIL"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7maxpoolPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z5conv2PiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10maxpoolingPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z5conv1PjPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movl	$3200, %r9d
	leaq	_ZL3FIL(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2065:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL3FIL
	.comm	_ZL3FIL,3200,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
// #include<time.h>
#include<float.h>

__constant__ int FIL[32*5*5];

__global__ void conv1(unsigned int *picd, int *resultd){
  int i,j,k,l;
  int sum, offset;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  offset = l*25;
  int xsize = 28;
  int filterdim = 5;
  k=0;
  sum =0;
  if(i<(xsize -filterdim +1)&& j<(xsize -filterdim +1)){
    sum = FIL[offset + k]*picd[ xsize * (i) + j ] + FIL[offset+ k+1]*picd[ xsize*(i) + (j+1) ]
      + FIL[offset+ k+2]*picd[ xsize * (i)+(j+2)] + FIL[offset+k+3]*picd[xsize * (i)+(j+3)]
      + FIL[offset+k+4]*picd[ xsize * (i)+(j+4)]+ FIL[offset+ k+5]*picd[ xsize*(i+1)+(j) ]
      + FIL[offset+k+6]*picd[ xsize * (i+1) + (j+1) ] + FIL[offset+ k+7]*picd[ xsize*(i+1) + (j+2) ] +
      FIL[offset+k+8]*picd[ xsize*(i+1) + (j+3) ] + FIL[offset+k+9]*picd[ xsize*(i+1) + (j+4) ] +
      FIL[offset+k+10]*picd[ xsize*(i+2) + (j) ]	+ FIL[offset+k+11]*picd[ xsize * (i+2) + (j+1) ] +
      FIL[offset+k+12]*picd[ xsize*(i+2) + (j+2)] + FIL[offset+k+13]*picd[ xsize*(i+2) + (j+3)]
      +FIL[offset+k+14]*picd[ xsize*(i+2) + (j+4)] + FIL[offset +k+15]*picd[ xsize*(i+3) + (j)]
      + FIL[offset+k+16]*picd[ xsize*(i+3) + (j+1)] + FIL[offset+k+17]*picd[ xsize*(i+3) + (j+2)]
      + FIL[offset+k+18]*picd[ xsize*(i+3) + (j+3)] + FIL[offset+k+19]*picd[ xsize*(i+3) + (j+4)]
      + FIL[offset+k+20]*picd[ xsize*(i+4) + (j)] +FIL[offset+k+21]*picd[ xsize*(i+3) + (j+1)]
      + FIL[offset+k+22]*picd[ xsize*(i+4) + (j+2)] + FIL[offset+k+23]*picd[ xsize*(i+4) + (j+3)]
      + FIL[offset+ k+24]*picd[ xsize*(i+4) + (j+4)];

      resultd[l*(xsize -filterdim +1)*(xsize -filterdim +1) + i*(xsize - filterdim +1)+j] = sum;
      //printf("resultgpu[%d][%d]=%d\n",l,i*(xsize - filterdim +1)+j,resulth[l*(xsize -filterdim +1)*(xsize -filterdim +1) + i*(xsize - filterdim +1)+j]);
  }
}

__global__ void maxpooling(int *maxip1d, int *maxop1d){

  int i,j,l;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  int xsize = 28;
  int filterdim = 5;
  if(i<((xsize-filterdim+1)/2)&&(j<((xsize-filterdim+1)/2))){
    int a,b,c,d,index, max1, max2;
    index = l*((xsize -filterdim +1)*(xsize -filterdim +1))+ threadIdx.x*2 + threadIdx.y*2*(xsize -filterdim +1);
    a = maxip1d[index];
    b = maxip1d[index +1];
    c = maxip1d[index+(xsize-filterdim+1)];
    d = maxip1d[index + (xsize-filterdim+2)];
    if(a>b){
      max1 = a;
    }
    else{
      max1 = b;
    }
    if(c>d){
      max2 = c;
    }
    else{
      max2 = d;
    }
    if(max1>max2){
      maxop1d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j]=max1;
    }
    else{
      maxop1d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j] = max2;
    }
  }
}

__global__ void conv2(int *cip2d, int *filter2d, int *cop2d){
  int i,j,l,sum;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  int lstar;
  lstar = l*800;
  sum = 0;
  int k =0;
  int di = 12;
  int disquare = di*di;
  int m;
  if(i<8 && j<8){
    for(m = 0; m<32; m++){
      sum = sum + filter2d[lstar + k]*cip2d[(m*disquare)+ (di*i) + j] + filter2d[lstar + k+1]*cip2d[(m*disquare)+ di*(i) + (j+1)]
        + filter2d[lstar+ k+2]*cip2d[(m*disquare)+ di*(i)+(j+2)] + filter2d[lstar +k+3]*cip2d[(m*disquare)+ di*(i)+(j+3)]
        + filter2d[lstar+k+4]*cip2d[(m*disquare)+ di*(i)+(j+4)]+ filter2d[lstar+ k+5]*cip2d[(m*disquare)+ di*(i+1)+(j)]
        + filter2d[lstar +k+6]*cip2d[(m*disquare)+ di* (i+1) + (j+1) ] + filter2d[lstar+ k+7]*cip2d[(m*disquare)+ di*(i+1)+(j+2)]
        + filter2d[lstar+k+8]*cip2d[(m*disquare)+ di*(i+1) + (j+3) ] + filter2d[lstar +k+9]*cip2d[(m*disquare)+ di*(i+1) +(j+4)]
        + filter2d[lstar+k+10]*cip2d[(m*disquare)+ di*(i+2) +(j)]	+ filter2d[lstar+k+11]*cip2d[(m*disquare)+ di* (i+2) + (j+1)]
        + filter2d[lstar+k+12]*cip2d[(m*disquare)+ di*(i+2) + (j+2)] +filter2d[lstar+k+13]*cip2d[(m*disquare)+ di*(i+2)+(j+3)]
        + filter2d[lstar+k+14]*cip2d[(m*disquare)+ di*(i+2)+(j+4)]+filter2d[lstar+k+15]*cip2d[(m*disquare)+ di*(i+3)+(j)]
        + filter2d[lstar+k+16]*cip2d[(m*disquare)+ di*(i+3)+(j+1)]+filter2d[lstar+k+17]*cip2d[(m*disquare)+ di*(i+3)+(j+2)]
        + filter2d[lstar+k+18]*cip2d[(m*disquare)+ di*(i+3)+(j+3)] + filter2d[lstar+k+19]*cip2d[(m*disquare)+di*(i+3)+(j+4)]
        + filter2d[lstar+k+20]*cip2d[(m*disquare)+ di*(i+4)+(j)] +filter2d[lstar+k+21]*cip2d[(m*disquare)+ di*(i+3)+(j+1)]
        + filter2d[lstar +k+22]*cip2d[(m*disquare)+ di*(i+4)+(j+2)] + filter2d[lstar+k+23]*cip2d[(m*disquare)+ di*(i+4)+(j+3)]
        + filter2d[lstar+ k+24]*cip2d[(m*disquare)+ di*(i+4) + (j+4)];

      k+=25;
    }
    cop2d[l*64+i*8+j] = sum;
    // printf("resultdevice[%d][%d]:%d\n",l,i*8+j,cop2d[l*64+i*8+j]);
  }
}

__global__ void maxpool(int *maxip2d, int *maxop2d){

  int i,j,l;
  i = threadIdx.y;
  j = threadIdx.x;
  l = blockIdx.x;
  int xsize = 12;
  int filterdim = 5;
  if(i<((xsize-filterdim+1)/2)&&(j<((xsize-filterdim+1)/2))){
    int a,b,c,d,index, max1, max2;
    index = l*((xsize -filterdim +1)*(xsize -filterdim +1))+ threadIdx.x*2 + threadIdx.y*2*(xsize -filterdim +1);
    a = maxip2d[index];
    b = maxip2d[index +1];
    c = maxip2d[index+(xsize-filterdim+1)];
    d = maxip2d[index + (xsize-filterdim+2)];
    if(a>b){
      max1 = a;
    }
    else{
      max1 = b;
    }
    if(c>d){
      max2 = c;
    }
    else{
      max2 = d;
    }
    if(max1>max2){
      maxop2d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j]=max1;
    }
    else{
      maxop2d[l*(xsize -filterdim +1)*(xsize -filterdim +1)/4 + i*(xsize - filterdim +1)/2+j] = max2;
    }
  }
}

int main(int argc, char **argv){
  int xsize;
  int filterdim;
  int numfilters;
  int numfilters1;
  xsize = 28;
  filterdim = 5;
  numfilters = 32;
  numfilters1 = 64;

  /*Numbytes required for initial image*/
  int numbytes = xsize*xsize*sizeof(int);
  /*Numbytes require for the output of first convolution layer*/
  int numbytes2 = (xsize-filterdim+1)*(xsize-filterdim+1)*sizeof(int); //24x24
  /**Numbytes required for output of first maxpool layer**/
  int numbytes3 = ((xsize-filterdim+1)*(xsize-filterdim+1)/4)*sizeof(int); //12x12
  /*Numbytes required for the output of second convolution layer*/
  int numbytes4 = ((xsize-filterdim+1)/2 - filterdim + 1)*((xsize-filterdim+1)/2 - filterdim + 1)*sizeof(int);//8x8
  /*Numbytes required for the output of second maxpool layer*/
  int numbytes5 = (numbytes4/4)*sizeof(int);//4x4

  /*Image on host side*/
  /*Ip and op to first conv layer*/
  unsigned int *pic = (unsigned int *)malloc(numbytes);
  int *result;
  int filter[numfilters*filterdim*filterdim];
  /*Ip and op to first maxpool layer*/
  int *maxip1;
  int *maxop1;
  /*Ip and op of second conv layer*/
  int *cip2;
  int *cop2;
  int *filter2;
  /*ip and op to second maxpool layer*/
  int *maxip2;
  int *maxop2;

  /*Device side variables*/
  unsigned int *picd;
  int *resultd;
  /*Ip and op to first maxpool layer*/
  int *maxip1d;
  int *maxop1d;
  /*Ip and op of second conv layer*/
  int *cip2d;
  int *cop2d;
  int *filter2d;
  /*ip and op to second maxpool layer*/
  int *maxip2d;
  int *maxop2d;

  result = (int *)malloc(numfilters*numbytes2);
  maxip1 = (int *)malloc(numfilters*numbytes2);
  maxop1 = (int *)malloc(numfilters*numbytes3);
  cip2 = (int *)malloc(numfilters*numbytes3);
  cop2 = (int *)malloc(numfilters1*numbytes4);
  filter2 = (int *)malloc(numfilters1*numfilters*filterdim*filterdim*sizeof(int));
  maxip2 = (int *)malloc(numfilters1*numbytes4);
  maxop2 = (int *)malloc(numfilters1*numbytes5);

  hipMalloc(&picd, numbytes);
  hipMalloc(&resultd, numfilters*numbytes2);
  hipMalloc(&maxip1d, numfilters*numbytes2);
  hipMalloc(&maxop1d, numfilters*numbytes3);
  hipMalloc(&cip2d, numfilters*numbytes3);
  hipMalloc(&cop2d, numfilters1*numbytes4);
  hipMalloc(&filter2d, numfilters1*numfilters*filterdim*filterdim*sizeof(int));
  hipMalloc(&maxip2d, numfilters1*numbytes4);
  hipMalloc(&maxop2d, numfilters1*numbytes5);

  /*Initializing the image on host side*/
  /*Should modify to later on read in image*/
  int i,j,k,l,count,dimx;
  for (i=0; i<xsize; i++) {
   for (j=0; j<xsize; j++) {
     pic[i*xsize + j] = 1;
     //printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
   }
   //  printf("\n");
  }

  /*Initializing the filter for first conv layer to a value*/
  /*TO DO : Read in filter from a file */
  for(int k=0;k<numfilters;k++){
   for (int i=0; i<filterdim; i++) {
     for (int j=0; j<filterdim; j++){
       filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
       // printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
     }
   }
 }

 /*Initializing the filter for second conv layer to a value*/
 /*TO DO : Read in filter from a file */
 for(int k=0;k<numfilters1;k++){
   for(int m= 0; m<numfilters;m++){
     for (int i=0; i<filterdim; i++) {
       for (int j=0; j<filterdim; j++){
         filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
         // printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
       }
     }
   }
   // printf("\n");
 }

 dim3 dimGrid (32);
 dim3 dimBlock (32,32);

 hipMemcpy(picd,pic,numbytes, hipMemcpyHostToDevice);
 hipMemcpyToSymbol(HIP_SYMBOL(FIL), filter, numfilters*filterdim*filterdim*sizeof(int));

 conv1<<<dimGrid, dimBlock>>>(picd,resultd);

 hipMemcpy(result,resultd,numfilters*numbytes2,hipMemcpyDeviceToHost);

 dim3 dimBlock1 (16,16);
 hipMemcpy(maxip1d, result,numfilters*numbytes2, hipMemcpyHostToDevice);

 maxpooling<<<dimGrid, dimBlock1>>>(maxip1d, maxop1d);

 hipMemcpy(maxop1, maxop1d, numfilters*numbytes3, hipMemcpyDeviceToHost);

 hipMemcpy(cip2d, maxop1,numfilters*numbytes3,hipMemcpyHostToDevice);
 hipMemcpy(filter2d, filter2,numfilters1*numfilters*filterdim*filterdim*sizeof(int), hipMemcpyHostToDevice);

 dim3 dimGrid2(64);
 dim3 dimBlock2(8,8);

 conv2<<<dimGrid2, dimBlock2>>>(cip2d, filter2d, cop2d);

 hipMemcpy(cop2, cop2d,numfilters1*numbytes4,hipMemcpyDeviceToHost);

 hipMemcpy(maxip2d, cop2,numfilters1*numbytes4,hipMemcpyHostToDevice);

 maxpool<<<dimGrid2, dimBlock2>>>(maxip2d, maxop2d);

 hipMemcpy(maxop2, maxop2d, numfilters*numbytes5, hipMemcpyDeviceToHost);

 for(k=0;k<numfilters1;k++){
   for(i=0;i<4;i++){
     for(j=0;j<4;j++){
       printf("maxpool[%d][%d]:%d\t",k,i*4+j, maxop2[k*16+i*4+j]);
     }
     printf("\n");
   }
   printf("\n\n");
 }

}

	.text
	.file	"GpuV1.hip"
	.globl	_Z20__device_stub__conv1PjPi    # -- Begin function _Z20__device_stub__conv1PjPi
	.type	_Z20__device_stub__conv1PjPi,@function
_Z20__device_stub__conv1PjPi:           # @_Z20__device_stub__conv1PjPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5conv1PjPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__conv1PjPi, .Lfunc_end0-_Z20__device_stub__conv1PjPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__maxpoolingPiS_ # -- Begin function _Z25__device_stub__maxpoolingPiS_
	.type	_Z25__device_stub__maxpoolingPiS_,@function
_Z25__device_stub__maxpoolingPiS_:      # @_Z25__device_stub__maxpoolingPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10maxpoolingPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__maxpoolingPiS_, .Lfunc_end1-_Z25__device_stub__maxpoolingPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__conv2PiS_S_  # -- Begin function _Z20__device_stub__conv2PiS_S_
	.type	_Z20__device_stub__conv2PiS_S_,@function
_Z20__device_stub__conv2PiS_S_:         # @_Z20__device_stub__conv2PiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5conv2PiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z20__device_stub__conv2PiS_S_, .Lfunc_end2-_Z20__device_stub__conv2PiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__maxpoolPiS_  # -- Begin function _Z22__device_stub__maxpoolPiS_
	.type	_Z22__device_stub__maxpoolPiS_,@function
_Z22__device_stub__maxpoolPiS_:         # @_Z22__device_stub__maxpoolPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7maxpoolPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__maxpoolPiS_, .Lfunc_end3-_Z22__device_stub__maxpoolPiS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3288, %rsp                     # imm = 0xCD8
	.cfi_def_cfa_offset 3344
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$3136, %edi                     # imm = 0xC40
	callq	malloc
	movq	%rax, %rbp
	movl	$73728, %edi                    # imm = 0x12000
	callq	malloc
	movq	%rax, %r13
	movl	$18432, %edi                    # imm = 0x4800
	callq	malloc
	movq	%rax, %r15
	movl	$16384, %edi                    # imm = 0x4000
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movl	$204800, %edi                   # imm = 0x32000
	callq	malloc
	movq	%rax, %r12
	movl	$16384, %edi                    # imm = 0x4000
	callq	malloc
	movq	%rax, %rbx
	leaq	64(%rsp), %rdi
	movl	$3136, %esi                     # imm = 0xC40
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$73728, %esi                    # imm = 0x12000
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$73728, %esi                    # imm = 0x12000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$18432, %esi                    # imm = 0x4800
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$18432, %esi                    # imm = 0x4800
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$204800, %esi                   # imm = 0x32000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	xorl	%eax, %eax
	movq	%rbp, %rcx
.LBB4_1:                                # %.preheader216
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_2 Depth 2
	xorl	%edx, %edx
.LBB4_2:                                #   Parent Loop BB4_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$28, %rdx
	jne	.LBB4_2
# %bb.3:                                #   in Loop: Header=BB4_1 Depth=1
	incq	%rax
	addq	$112, %rcx
	cmpq	$28, %rax
	jne	.LBB4_1
# %bb.4:                                # %.preheader214.preheader
	leaq	80(%rsp), %rax
	xorl	%ecx, %ecx
.LBB4_5:                                # %.preheader214
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_6 Depth 2
                                        #       Child Loop BB4_7 Depth 3
	movq	%rax, %rdx
	xorl	%esi, %esi
.LBB4_6:                                # %.preheader213
                                        #   Parent Loop BB4_5 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB4_7 Depth 3
	xorl	%edi, %edi
.LBB4_7:                                #   Parent Loop BB4_5 Depth=1
                                        #     Parent Loop BB4_6 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	$1, (%rdx,%rdi,4)
	incq	%rdi
	cmpq	$5, %rdi
	jne	.LBB4_7
# %bb.8:                                #   in Loop: Header=BB4_6 Depth=2
	incq	%rsi
	addq	$20, %rdx
	cmpq	$5, %rsi
	jne	.LBB4_6
# %bb.9:                                #   in Loop: Header=BB4_5 Depth=1
	incq	%rcx
	addq	$100, %rax
	cmpq	$32, %rcx
	jne	.LBB4_5
# %bb.10:                               # %.preheader211.preheader
	xorl	%eax, %eax
	movq	%r12, %rcx
.LBB4_11:                               # %.preheader211
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_12 Depth 2
                                        #       Child Loop BB4_13 Depth 3
                                        #         Child Loop BB4_14 Depth 4
	movq	%rcx, %rdx
	xorl	%esi, %esi
.LBB4_12:                               # %.preheader210
                                        #   Parent Loop BB4_11 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB4_13 Depth 3
                                        #         Child Loop BB4_14 Depth 4
	movq	%rdx, %rdi
	xorl	%r8d, %r8d
.LBB4_13:                               # %.preheader209
                                        #   Parent Loop BB4_11 Depth=1
                                        #     Parent Loop BB4_12 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB4_14 Depth 4
	xorl	%r9d, %r9d
.LBB4_14:                               #   Parent Loop BB4_11 Depth=1
                                        #     Parent Loop BB4_12 Depth=2
                                        #       Parent Loop BB4_13 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movl	$1, (%rdi,%r9,4)
	incq	%r9
	cmpq	$5, %r9
	jne	.LBB4_14
# %bb.15:                               #   in Loop: Header=BB4_13 Depth=3
	incq	%r8
	addq	$20, %rdi
	cmpq	$5, %r8
	jne	.LBB4_13
# %bb.16:                               #   in Loop: Header=BB4_12 Depth=2
	incq	%rsi
	addq	$100, %rdx
	cmpq	$32, %rsi
	jne	.LBB4_12
# %bb.17:                               #   in Loop: Header=BB4_11 Depth=1
	incq	%rax
	addq	$3200, %rcx                     # imm = 0xC80
	cmpq	$64, %rax
	jne	.LBB4_11
# %bb.18:
	movabsq	$4294967328, %r14               # imm = 0x100000020
	movq	64(%rsp), %rdi
	movl	$3136, %edx                     # imm = 0xC40
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	80(%rsp), %rsi
	movl	$FIL, %edi
	movl	$3200, %edx                     # imm = 0xC80
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_20
# %bb.19:
	movq	64(%rsp), %rdi
	movq	56(%rsp), %rsi
	callq	_Z20__device_stub__conv1PjPi
.LBB4_20:
	movq	56(%rsp), %rsi
	movl	$73728, %edx                    # imm = 0x12000
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rdi
	movl	$73728, %edx                    # imm = 0x12000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_22
# %bb.21:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	callq	_Z25__device_stub__maxpoolingPiS_
.LBB4_22:
	movabsq	$34359738376, %r13              # imm = 0x800000008
	movq	40(%rsp), %rsi
	movl	$18432, %edx                    # imm = 0x4800
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$18432, %edx                    # imm = 0x4800
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$204800, %edx                   # imm = 0x32000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	addq	$32, %r14
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_24
# %bb.23:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdx
	callq	_Z20__device_stub__conv2PiS_S_
.LBB4_24:
	movq	24(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movq	72(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_26
# %bb.25:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z22__device_stub__maxpoolPiS_
.LBB4_26:
	movq	(%rsp), %rsi
	movl	$8192, %edx                     # imm = 0x2000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r14d, %r14d
.LBB4_27:                               # %.preheader208
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_28 Depth 2
                                        #       Child Loop BB4_29 Depth 3
	xorl	%r15d, %r15d
	movq	%rbx, %r12
	xorl	%r13d, %r13d
.LBB4_28:                               # %.preheader
                                        #   Parent Loop BB4_27 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB4_29 Depth 3
	xorl	%ebp, %ebp
.LBB4_29:                               #   Parent Loop BB4_27 Depth=1
                                        #     Parent Loop BB4_28 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%r12,%rbp,4), %ecx
	leal	(%r15,%rbp), %edx
	movl	$.L.str, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%rbp
	cmpq	$4, %rbp
	jne	.LBB4_29
# %bb.30:                               #   in Loop: Header=BB4_28 Depth=2
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r13
	addq	$16, %r12
	addq	$4, %r15
	cmpq	$4, %r13
	jne	.LBB4_28
# %bb.31:                               #   in Loop: Header=BB4_27 Depth=1
	movl	$.Lstr, %edi
	callq	puts@PLT
	incq	%r14
	addq	$64, %rbx
	cmpq	$64, %r14
	jne	.LBB4_27
# %bb.32:
	xorl	%eax, %eax
	addq	$3288, %rsp                     # imm = 0xCD8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5conv1PjPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10maxpoolingPiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5conv2PiS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7maxpoolPiS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$FIL, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$3200, %r9d                     # imm = 0xC80
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	FIL,@object                     # @FIL
	.local	FIL
	.comm	FIL,3200,16
	.type	_Z5conv1PjPi,@object            # @_Z5conv1PjPi
	.section	.rodata,"a",@progbits
	.globl	_Z5conv1PjPi
	.p2align	3, 0x0
_Z5conv1PjPi:
	.quad	_Z20__device_stub__conv1PjPi
	.size	_Z5conv1PjPi, 8

	.type	_Z10maxpoolingPiS_,@object      # @_Z10maxpoolingPiS_
	.globl	_Z10maxpoolingPiS_
	.p2align	3, 0x0
_Z10maxpoolingPiS_:
	.quad	_Z25__device_stub__maxpoolingPiS_
	.size	_Z10maxpoolingPiS_, 8

	.type	_Z5conv2PiS_S_,@object          # @_Z5conv2PiS_S_
	.globl	_Z5conv2PiS_S_
	.p2align	3, 0x0
_Z5conv2PiS_S_:
	.quad	_Z20__device_stub__conv2PiS_S_
	.size	_Z5conv2PiS_S_, 8

	.type	_Z7maxpoolPiS_,@object          # @_Z7maxpoolPiS_
	.globl	_Z7maxpoolPiS_
	.p2align	3, 0x0
_Z7maxpoolPiS_:
	.quad	_Z22__device_stub__maxpoolPiS_
	.size	_Z7maxpoolPiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"maxpool[%d][%d]:%d\t"
	.size	.L.str, 20

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5conv1PjPi"
	.size	.L__unnamed_1, 13

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10maxpoolingPiS_"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z5conv2PiS_S_"
	.size	.L__unnamed_3, 15

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7maxpoolPiS_"
	.size	.L__unnamed_4, 15

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"FIL"
	.size	.L__unnamed_5, 4

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n"
	.size	.Lstr, 2

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__conv1PjPi
	.addrsig_sym _Z25__device_stub__maxpoolingPiS_
	.addrsig_sym _Z20__device_stub__conv2PiS_S_
	.addrsig_sym _Z22__device_stub__maxpoolPiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym FIL
	.addrsig_sym _Z5conv1PjPi
	.addrsig_sym _Z10maxpoolingPiS_
	.addrsig_sym _Z5conv2PiS_S_
	.addrsig_sym _Z7maxpoolPiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5conv1PjPi            ; -- Begin function _Z5conv1PjPi
	.globl	_Z5conv1PjPi
	.p2align	8
	.type	_Z5conv1PjPi,@function
_Z5conv1PjPi:                           ; @_Z5conv1PjPi
; %bb.0:
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_u32_e32 v2, v1, v0
	v_cmpx_gt_u32_e32 24, v2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mul_u32_u24_e32 v2, 28, v1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, FIL@rel32@lo+4
	s_addc_u32 s5, s5, FIL@rel32@hi+12
	v_mul_u32_u24_e32 v1, 24, v1
	v_add_lshl_u32 v18, v2, v0, 2
	s_waitcnt lgkmcnt(0)
	s_clause 0x6
	global_load_b128 v[2:5], v18, s[0:1]
	global_load_b32 v21, v18, s[0:1] offset:16
	global_load_b128 v[6:9], v18, s[0:1] offset:112
	global_load_b32 v22, v18, s[0:1] offset:128
	global_load_b128 v[10:13], v18, s[0:1] offset:224
	global_load_b32 v23, v18, s[0:1] offset:240
	global_load_b128 v[14:17], v18, s[0:1] offset:336
	v_add_nc_u32_e32 v19, 8, v18
	s_clause 0x2
	global_load_b32 v24, v18, s[0:1] offset:352
	global_load_b32 v25, v18, s[0:1] offset:448
	global_load_b96 v[18:20], v19, s[0:1] offset:448
	s_mul_i32 s0, s15, 25
	s_mulk_i32 s15, 0x240
	s_ashr_i32 s1, s0, 31
	v_add3_u32 v0, v1, v0, s15
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s4, s0, s4
	s_addc_u32 s5, s1, s5
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b512 s[16:31], s[4:5], 0x0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, FIL@rel32@lo+68
	s_addc_u32 s5, s5, FIL@rel32@hi+76
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_add_i32 s1, s9, s4
	s_waitcnt vmcnt(9)
	v_mul_lo_u32 v2, v2, s16
	v_mul_lo_u32 v26, v4, s18
	v_mul_lo_u32 v27, v5, s19
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v3, s17, v[2:3]
	s_waitcnt vmcnt(8)
	v_mul_lo_u32 v2, v21, s20
	s_waitcnt vmcnt(7)
	v_mul_lo_u32 v3, v6, s21
	v_mul_lo_u32 v5, v7, s22
	v_mul_lo_u32 v6, v8, s23
	v_add3_u32 v4, v4, v26, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add3_u32 v2, v4, v2, v3
	v_mul_lo_u32 v3, v9, s24
	s_waitcnt vmcnt(6)
	v_mul_lo_u32 v4, v22, s25
	v_add3_u32 v2, v2, v5, v6
	s_waitcnt vmcnt(5)
	v_mul_lo_u32 v5, v10, s26
	v_mul_lo_u32 v6, v11, s27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v2, v2, v3, v4
	v_mul_lo_u32 v3, v12, s28
	v_mul_lo_u32 v4, v13, s29
	v_add3_u32 v2, v2, v5, v6
	s_waitcnt vmcnt(4)
	v_mul_lo_u32 v5, v23, s30
	s_waitcnt vmcnt(3)
	v_mul_lo_u32 v6, v14, s31
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v2, v2, v3, v4
	v_mul_lo_u32 v3, v16, s5
	v_mul_lo_u32 v4, v17, s6
	v_add3_u32 v2, v2, v5, v6
	s_waitcnt vmcnt(2)
	v_mul_lo_u32 v5, v24, s7
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v6, v25, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add3_u32 v2, v2, v3, v4
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v3, v18, s10
	v_mul_lo_u32 v4, s1, v15
	v_add3_u32 v2, v2, v5, v6
	v_mul_lo_u32 v5, v19, s11
	v_mul_lo_u32 v6, v20, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v2, v4, v3
	v_add3_u32 v2, v2, v5, v6
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5conv1PjPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5conv1PjPi, .Lfunc_end0-_Z5conv1PjPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 668
; NumSgprs: 34
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10maxpoolingPiS_      ; -- Begin function _Z10maxpoolingPiS_
	.globl	_Z10maxpoolingPiS_
	.p2align	8
	.type	_Z10maxpoolingPiS_,@function
_Z10maxpoolingPiS_:                     ; @_Z10maxpoolingPiS_
; %bb.0:
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_u32_e32 v2, v1, v0
	v_cmpx_gt_u32_e32 12, v2
	s_cbranch_execz .LBB1_2
; %bb.1:                                ; %.sink.split
	v_lshlrev_b32_e32 v2, 1, v0
	v_mul_u32_u24_e32 v3, 48, v1
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mulk_i32 s15, 0x240
	v_mul_u32_u24_e32 v1, 12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, s15, v2, v3
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_ashr_i32 s0, s15, 2
	s_clause 0x1
	global_load_b64 v[4:5], v[2:3], off offset:96
	global_load_b64 v[2:3], v[2:3], off
	v_add3_u32 v0, v1, v0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_max_i32_e32 v4, v4, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_max3_i32 v2, v2, v3, v4
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10maxpoolingPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10maxpoolingPiS_, .Lfunc_end1-_Z10maxpoolingPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 216
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z5conv2PiS_S_          ; -- Begin function _Z5conv2PiS_S_
	.globl	_Z5conv2PiS_S_
	.p2align	8
	.type	_Z5conv2PiS_S_,@function
_Z5conv2PiS_S_:                         ; @_Z5conv2PiS_S_
; %bb.0:
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v3, v2
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB2_4
; %bb.1:                                ; %.preheader
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_u32_u24_e32 v0, 12, v3
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mul_i32 s2, s15, 0x320
	v_mov_b32_e32 v4, 0
	s_ashr_i32 s3, s2, 31
	v_add_lshl_u32 v0, v0, v2, 2
	s_lshl_b64 s[2:3], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s4, v0, s4
	v_add_co_ci_u32_e64 v1, null, 0, s5, s4
	s_add_u32 s4, s6, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, 0x68, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_addc_u32 s5, s7, s3
	s_mov_b64 s[2:3], 0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_clause 0x9
	global_load_b128 v[5:8], v[0:1], off offset:-104
	global_load_b32 v24, v[0:1], off offset:-88
	global_load_b128 v[9:12], v[0:1], off offset:-56
	global_load_b32 v25, v[0:1], off offset:-40
	global_load_b128 v[13:16], v[0:1], off offset:-8
	global_load_b32 v26, v[0:1], off offset:8
	global_load_b128 v[17:20], v[0:1], off offset:40
	global_load_b32 v27, v[0:1], off offset:56
	global_load_b32 v28, v[0:1], off offset:88
	global_load_b96 v[21:23], v[0:1], off offset:96
	s_add_u32 s6, s4, s2
	s_addc_u32 s7, s5, s3
	s_clause 0x2
	s_load_b512 s[16:31], s[6:7], 0x0
	s_load_b256 s[36:43], s[6:7], 0x40
	s_load_b32 s6, s[6:7], 0x60
	v_add_co_u32 v0, vcc_lo, 0x240, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_add_i32 s7, s41, s36
	s_add_u32 s2, s2, 0x64
	s_addc_u32 s3, s3, 0
	s_cmpk_lg_i32 s2, 0xc80
	s_waitcnt vmcnt(9)
	v_mul_lo_u32 v5, v5, s16
	v_mul_lo_u32 v6, v6, s17
	v_mul_lo_u32 v7, v7, s18
	v_mul_lo_u32 v8, v8, s19
	s_waitcnt vmcnt(8)
	v_mul_lo_u32 v24, v24, s20
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v4, v5, v4, v6
	s_waitcnt vmcnt(7)
	v_mul_lo_u32 v5, v9, s21
	v_mul_lo_u32 v6, v10, s22
	s_waitcnt vmcnt(5)
	v_mul_lo_u32 v9, v13, s26
	v_add3_u32 v4, v4, v7, v8
	v_mul_lo_u32 v7, v11, s23
	v_mul_lo_u32 v8, v12, s24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v4, v4, v24, v5
	v_mul_lo_u32 v5, v25, s25
	v_add3_u32 v4, v4, v6, v7
	v_mul_lo_u32 v6, v14, s27
	v_mul_lo_u32 v7, v15, s28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v4, v8, v5
	v_mul_lo_u32 v5, v16, s29
	s_waitcnt vmcnt(4)
	v_mul_lo_u32 v8, v26, s30
	v_add3_u32 v4, v4, v9, v6
	s_waitcnt vmcnt(3)
	v_mul_lo_u32 v6, v17, s31
	v_mul_lo_u32 v9, v19, s37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v4, v7, v5
	v_mul_lo_u32 v5, v20, s38
	s_waitcnt vmcnt(2)
	v_mul_lo_u32 v7, v27, s39
	v_add3_u32 v4, v4, v8, v6
	s_waitcnt vmcnt(1)
	v_mul_lo_u32 v6, v28, s40
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v8, v21, s42
	v_add3_u32 v4, v4, v9, v5
	v_mul_lo_u32 v5, s7, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v4, v7, v6
	v_mul_lo_u32 v6, v22, s43
	v_mul_lo_u32 v7, v23, s6
	v_add3_u32 v4, v4, v5, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v6, v7
	s_cbranch_scc1 .LBB2_2
; %bb.3:
	v_lshlrev_b32_e32 v0, 3, v3
	s_lshl_b32 s2, s15, 6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, v0, v2, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB2_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5conv2PiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z5conv2PiS_S_, .Lfunc_end2-_Z5conv2PiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 724
; NumSgprs: 46
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7maxpoolPiS_          ; -- Begin function _Z7maxpoolPiS_
	.globl	_Z7maxpoolPiS_
	.p2align	8
	.type	_Z7maxpoolPiS_,@function
_Z7maxpoolPiS_:                         ; @_Z7maxpoolPiS_
; %bb.0:
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v1, v0
	v_cmpx_gt_u32_e32 4, v2
	s_cbranch_execz .LBB3_2
; %bb.1:                                ; %.sink.split
	v_lshlrev_b32_e32 v2, 1, v0
	v_lshlrev_b32_e32 v3, 4, v1
	s_load_b128 s[0:3], s[0:1], 0x0
	s_lshl_b32 s4, s15, 6
	v_lshlrev_b32_e32 v1, 2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, s4, v2, v3
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_lshl_b32 s0, s15, 4
	s_clause 0x1
	global_load_b64 v[4:5], v[2:3], off offset:32
	global_load_b64 v[2:3], v[2:3], off
	v_add3_u32 v0, s0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_max_i32_e32 v4, v4, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_max3_i32 v2, v2, v3, v4
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7maxpoolPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z7maxpoolPiS_, .Lfunc_end3-_Z7maxpoolPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 216
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	FIL                     ; @FIL
	.type	FIL,@object
	.section	.bss,"aw",@nobits
	.globl	FIL
	.p2align	4, 0x0
FIL:
	.zero	3200
	.size	FIL, 3200

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym FIL
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5conv1PjPi
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z5conv1PjPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10maxpoolingPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10maxpoolingPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5conv2PiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         _Z5conv2PiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7maxpoolPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7maxpoolPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
