#include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>

#define THREADS_PER_BLOCK 32

__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
    // use x to access each cell and compare it to each point and assign the cell's value to match the closest point
    int x = blockIdx.x * blockDim.x + threadIdx.x;

    double minDistance = DBL_MAX;
    int minPoint = -1;
    for (int k=0; k<numPoints; k++) {
        double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
        if (distance < minDistance) {
            minDistance = distance;
            minPoint = k;
        }
    }
    imageArray[x] = minPoint;
}

extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
    // allocate space for the image and point coordinates on the device and copy the coordinates over
    int *imageArray;
    int *points;
	cudaMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
	cudaMalloc ((void**) &points, sizeof(int) * numPoints * 2);
    cudaMemcpy (points, points_h, sizeof(int) * numPoints * 2, cudaMemcpyHostToDevice);

    // start calculation timing
    struct timeval start, end;
    gettimeofday(&start, NULL);

    // calculate and then synchronize to ensure accurate timing
    voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
    cudaDeviceSynchronize();

    // end timing and print processing time
    gettimeofday(&end, NULL);
    long seconds = (end.tv_sec - start.tv_sec);
    long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
    printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);

    // print CUDA errors
    cudaError_t err = cudaGetLastError();
    printf("CUDA error: %s\n", cudaGetErrorString(err));

    // copy results to host and free device memory
    cudaMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, cudaMemcpyDeviceToHost);
    cudaFree (imageArray);
    cudaFree (points);
}


	.file	"tmpxft_002b0de0_00000000-6_vgpu.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
	.type	_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii, @function
_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9voronoi_dPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii, .-_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
	.globl	_Z9voronoi_dPiS_ii
	.type	_Z9voronoi_dPiS_ii, @function
_Z9voronoi_dPiS_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
	.cfi_endproc
.LFE3661:
	.size	_Z9voronoi_dPiS_ii, .-_Z9voronoi_dPiS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Processing time elpased is %zu seconds or %zu micros\n"
.LC2:
	.string	"CUDA error: %s\n"
	.text
	.globl	_Z10gpuVoronoiPiS_ii
	.type	_Z10gpuVoronoiPiS_ii, @function
_Z10gpuVoronoiPiS_ii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movslq	%ecx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r14, %r13
	salq	$3, %r14
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%edx, %rbx
	movq	%rbx, %r12
	imulq	%rbx, %rbx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	salq	$2, %rbx
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	%r14, %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%r14, %rdx
	movq	%r15, %rsi
	movabsq	$4294967328, %r14
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	xorl	%esi, %esi
	leaq	40(%rsp), %rdi
	call	gettimeofday@PLT
	cvtsi2ssl	%r12d, %xmm0
	movq	%r14, 56(%rsp)
	movl	$1, 64(%rsp)
	mulss	%xmm0, %xmm0
	mulss	.LC0(%rip), %xmm0
	call	ceilf@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r14, %rdx
	cvttss2siq	%xmm0, %rax
	movl	$1, %ecx
	movl	%eax, 28(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	28(%rsp), %rdi
	movl	36(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%r12d, %edx
	call	_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
.L9:
	call	cudaDeviceSynchronize@PLT
	xorl	%esi, %esi
	leaq	56(%rsp), %rdi
	call	gettimeofday@PLT
	movq	56(%rsp), %rdx
	subq	40(%rsp), %rdx
	xorl	%eax, %eax
	imulq	$1000000, %rdx, %rcx
	movl	$2, %edi
	addq	64(%rsp), %rcx
	subq	48(%rsp), %rcx
	leaq	.LC1(%rip), %rsi
	call	__printf_chk@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%rbp, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z10gpuVoronoiPiS_ii, .-_Z10gpuVoronoiPiS_ii
	.section	.rodata.str1.1
.LC3:
	.string	"_Z9voronoi_dPiS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9voronoi_dPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1023410176
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>

#define THREADS_PER_BLOCK 32

__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
    // use x to access each cell and compare it to each point and assign the cell's value to match the closest point
    int x = blockIdx.x * blockDim.x + threadIdx.x;

    double minDistance = DBL_MAX;
    int minPoint = -1;
    for (int k=0; k<numPoints; k++) {
        double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
        if (distance < minDistance) {
            minDistance = distance;
            minPoint = k;
        }
    }
    imageArray[x] = minPoint;
}

extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
    // allocate space for the image and point coordinates on the device and copy the coordinates over
    int *imageArray;
    int *points;
	hipMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
	hipMalloc ((void**) &points, sizeof(int) * numPoints * 2);
    hipMemcpy (points, points_h, sizeof(int) * numPoints * 2, hipMemcpyHostToDevice);

    // start calculation timing
    struct timeval start, end;
    gettimeofday(&start, NULL);

    // calculate and then synchronize to ensure accurate timing
    voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
    hipDeviceSynchronize();

    // end timing and print processing time
    gettimeofday(&end, NULL);
    long seconds = (end.tv_sec - start.tv_sec);
    long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
    printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);

    // print CUDA errors
    hipError_t err = hipGetLastError();
    printf("CUDA error: %s\n", hipGetErrorString(err));

    // copy results to host and free device memory
    hipMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, hipMemcpyDeviceToHost);
    hipFree (imageArray);
    hipFree (points);
}


	.text
	.file	"vgpu.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__voronoi_dPiS_ii # -- Begin function _Z24__device_stub__voronoi_dPiS_ii
	.type	_Z24__device_stub__voronoi_dPiS_ii,@function
_Z24__device_stub__voronoi_dPiS_ii:     # @_Z24__device_stub__voronoi_dPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9voronoi_dPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__voronoi_dPiS_ii, .Lfunc_end0-_Z24__device_stub__voronoi_dPiS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z10gpuVoronoiPiS_ii
.LCPI1_0:
	.long	0x3d000000                      # float 0.03125
	.text
	.globl	_Z10gpuVoronoiPiS_ii
	.type	_Z10gpuVoronoiPiS_ii,@function
_Z10gpuVoronoiPiS_ii:                   # @_Z10gpuVoronoiPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movq	%rsi, %r12
	movq	%rdi, 32(%rsp)                  # 8-byte Spill
	movslq	%edx, %rbx
	movq	%rbx, %rbp
	imulq	%rbx, %rbp
	shlq	$2, %rbp
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	%r14d, 20(%rsp)                 # 4-byte Spill
	movslq	%r14d, %r13
	shlq	$3, %r13
	leaq	24(%rsp), %r14
	movq	%r14, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	%r12, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cvtsi2ss	%ebx, %xmm0
	mulss	%xmm0, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rax
	movl	%eax, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	%r15d, %edx
	movl	20(%rsp), %ecx                  # 4-byte Reload
	callq	_Z24__device_stub__voronoi_dPiS_ii
.LBB1_2:
	callq	hipDeviceSynchronize
	leaq	56(%rsp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r14), %rsi
	subq	40(%rsp), %rsi
	imulq	$1000000, %rsi, %rdx            # imm = 0xF4240
	addq	8(%r14), %rdx
	subq	48(%rsp), %rdx
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z10gpuVoronoiPiS_ii, .Lfunc_end1-_Z10gpuVoronoiPiS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9voronoi_dPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9voronoi_dPiS_ii,@object      # @_Z9voronoi_dPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z9voronoi_dPiS_ii
	.p2align	3, 0x0
_Z9voronoi_dPiS_ii:
	.quad	_Z24__device_stub__voronoi_dPiS_ii
	.size	_Z9voronoi_dPiS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Processing time elpased is %zu seconds or %zu micros\n"
	.size	.L.str, 54

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CUDA error: %s\n"
	.size	.L.str.1, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9voronoi_dPiS_ii"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__voronoi_dPiS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9voronoi_dPiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9voronoi_dPiS_ii      ; -- Begin function _Z9voronoi_dPiS_ii
	.globl	_Z9voronoi_dPiS_ii
	.p2align	8
	.type	_Z9voronoi_dPiS_ii,@function
_Z9voronoi_dPiS_ii:                     ; @_Z9voronoi_dPiS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_cmp_lt_i32 s7, 1
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_ashr_i32 s2, s6, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	s_add_i32 s0, s6, s2
	s_mov_b32 s13, 0
	s_xor_b32 s3, s0, s2
	s_mov_b32 s12, s7
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s0, 0, s3
	v_xor_b32_e32 v4, v4, v2
	s_mov_b32 s14, 0x55555555
	s_mov_b32 s16, 0x968915a9
	v_rcp_iflag_f32_e32 v0, v0
	s_mov_b32 s18, 0x4222de17
	s_mov_b32 s20, 0x3abe935a
	s_mov_b32 s22, 0x47e6c9c2
	s_mov_b32 s24, 0xcfa74449
	s_mov_b32 s26, 0x71bf3c30
	s_mov_b32 s28, 0x1c7792ce
	s_mov_b32 s30, 0x924920da
	s_mov_b32 s34, 0x9999999c
	s_mov_b32 s36, 0xfefa39ef
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_mov_b32 s38, 0x3b39803f
	s_mov_b32 s40, 0xd5df274d
	s_mov_b32 s42, 0x652b82fe
	s_mov_b32 s44, 0xfca7ab0c
	v_cvt_u32_f32_e32 v3, v0
	s_mov_b32 s46, 0x6a5dcb37
	s_mov_b32 s48, 0x623fde64
	s_mov_b32 s50, 0x7c89e6b0
	s_mov_b32 s52, 0x14761f6e
	v_mul_lo_u32 v0, s0, v3
	s_mov_b32 s0, -1
	s_mov_b32 s1, 0x7fefffff
	s_mov_b32 s54, 0x1852b7b0
	s_mov_b32 s56, 0x11122322
	s_mov_b32 s58, 0x555502a1
	s_mov_b32 s60, 0x55555511
	s_mov_b32 s62, 11
	v_mul_hi_u32 v5, v3, v0
	s_mov_b32 s15, 0x3fe55555
	s_mov_b32 s17, 0x3fba6564
	s_mov_b32 s19, 0x3fbdee67
	s_mov_b32 s21, 0x3fbe25e4
	s_mov_b32 s23, 0x3fc110ef
	s_mov_b32 s25, 0x3fc3b13b
	s_mov_b32 s27, 0x3fc745d1
	v_add_nc_u32_e32 v3, v3, v5
	s_mov_b32 s29, 0x3fcc71c7
	s_mov_b32 s31, 0x3fd24924
	s_mov_b32 s35, 0x3fd99999
	s_mov_b32 s37, 0x3fe62e42
	v_mul_hi_u32 v3, v4, v3
	s_mov_b32 s39, 0x3c7abc9e
	s_mov_b32 s41, 0x3c8543b0
	s_mov_b32 s43, 0x3ff71547
	s_mov_b32 s45, 0x3e928af3
	s_mov_b32 s47, 0x3e5ade15
	s_mov_b32 s49, 0x3ec71dee
	s_mov_b32 s51, 0x3efa0199
	v_mul_lo_u32 v5, v3, s3
	v_add_nc_u32_e32 v6, 1, v3
	s_mov_b32 s53, 0x3f2a01a0
	s_mov_b32 s55, 0x3f56c16c
	s_mov_b32 s57, 0x3f811111
	s_mov_b32 s59, 0x3fa55555
	s_mov_b32 s61, 0x3fc55555
	s_mov_b32 s63, 0x3fe00000
	v_sub_nc_u32_e32 v4, v4, v5
	s_lshl_b64 s[64:65], s[12:13], 2
	s_mov_b32 s67, 0xbfe55555
	s_mov_b32 s69, 0xbfe62e42
	s_mov_b32 s71, 0xbc7abc9e
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	v_subrev_nc_u32_e32 v5, s3, v4
	v_dual_mov_b32 v0, -1 :: v_dual_cndmask_b32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_xor_b32_e32 v6, s2, v2
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v6
	v_sub_nc_u32_e32 v11, v3, v6
	v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v11, s6
	v_sub_nc_u32_e32 v12, v1, v5
	v_mov_b32_e32 v5, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_add_u32 s0, s10, s64
	s_addc_u32 s1, s11, s65
	s_mov_b32 s66, s14
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x0
	s_load_b32 s6, s[10:11], 0x0
	s_mov_b32 s68, s36
	s_mov_b32 s70, s38
	s_waitcnt lgkmcnt(0)
	v_subrev_nc_u32_e32 v14, s4, v12
	v_subrev_nc_u32_e32 v13, s6, v11
	v_cmp_eq_u32_e64 s6, s6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[9:10], v14
	v_cvt_f64_i32_e32 v[7:8], v13
	v_cmp_eq_u32_e32 vcc_lo, 1, v14
	v_cndmask_b32_e64 v6, 2.0, 0x3ff00000, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_frexp_mant_f64_e64 v[15:16], |v[9:10]|
	v_frexp_mant_f64_e64 v[17:18], |v[7:8]|
	v_frexp_exp_i32_f64_e32 v9, v[9:10]
	v_frexp_exp_i32_f64_e32 v7, v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e32 vcc_lo, s[14:15], v[15:16]
	v_cmp_gt_f64_e64 s0, s[14:15], v[17:18]
	v_cndmask_b32_e64 v19, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, 0, 1, s0
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_subrev_co_ci_u32_e64 v7, vcc_lo, 0, v7, s0
	v_ldexp_f64 v[15:16], v[15:16], v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[17:18], v[17:18], v20
	v_cvt_f64_i32_e32 v[21:22], v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[25:26], v7
	v_add_f64 v[19:20], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[17:18], 1.0
	v_mul_f64 v[35:36], v[21:22], s[36:37]
	v_add_f64 v[27:28], v[15:16], -1.0
	v_mul_f64 v[39:40], v[25:26], s[36:37]
	v_add_f64 v[29:30], v[17:18], -1.0
	v_rcp_f64_e32 v[33:34], v[19:20]
	v_add_f64 v[31:32], v[19:20], -1.0
	v_add_f64 v[37:38], v[23:24], -1.0
	v_rcp_f64_e32 v[41:42], v[23:24]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[31:32]
	v_fma_f64 v[31:32], v[21:22], s[36:37], -v[35:36]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[43:44], -v[19:20], v[33:34], 1.0
	v_add_f64 v[17:18], v[17:18], -v[37:38]
	v_fma_f64 v[37:38], v[25:26], s[36:37], -v[39:40]
	v_fma_f64 v[45:46], -v[23:24], v[41:42], 1.0
	v_fma_f64 v[21:22], v[21:22], s[38:39], v[31:32]
	v_fma_f64 v[31:32], v[43:44], v[33:34], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[25:26], v[25:26], s[38:39], v[37:38]
	v_fma_f64 v[33:34], v[45:46], v[41:42], v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[35:36], v[21:22]
	v_fma_f64 v[43:44], -v[19:20], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[41:42], v[39:40], v[25:26]
	v_fma_f64 v[45:46], -v[23:24], v[33:34], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[35:36], v[37:38], -v[35:36]
	v_fma_f64 v[31:32], v[43:44], v[31:32], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[39:40], v[41:42], -v[39:40]
	v_fma_f64 v[33:34], v[45:46], v[33:34], v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], -v[35:36]
	v_mul_f64 v[35:36], v[27:28], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[25:26], -v[39:40]
	v_mul_f64 v[43:44], v[29:30], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[45:46], v[19:20], v[35:36]
	v_mul_f64 v[47:48], v[23:24], v[43:44]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[35:36], v[19:20], -v[45:46]
	v_fma_f64 v[23:24], v[43:44], v[23:24], -v[47:48]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[35:36], v[15:16], v[19:20]
	v_fma_f64 v[17:18], v[43:44], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[45:46], v[15:16]
	v_add_f64 v[23:24], v[47:48], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[49:50], v[27:28], -v[19:20]
	v_add_f64 v[45:46], v[19:20], -v[45:46]
	v_add_f64 v[51:52], v[29:30], -v[23:24]
	v_add_f64 v[47:48], v[23:24], -v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[27:28], v[27:28], -v[49:50]
	v_add_f64 v[15:16], v[45:46], -v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[29:30], v[29:30], -v[51:52]
	v_add_f64 v[17:18], v[47:48], -v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[27:28], -v[19:20]
	v_add_f64 v[23:24], v[29:30], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], v[19:20]
	v_add_f64 v[17:18], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[49:50], v[15:16]
	v_add_f64 v[17:18], v[51:52], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[15:16], v[31:32], v[15:16]
	v_mul_f64 v[17:18], v[33:34], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[35:36], v[15:16]
	v_add_f64 v[23:24], v[43:44], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[27:28], v[19:20], -v[35:36]
	v_mul_f64 v[29:30], v[19:20], v[19:20]
	v_ldexp_f64 v[31:32], v[19:20], 1
	v_add_f64 v[33:34], v[23:24], -v[43:44]
	v_mul_f64 v[35:36], v[23:24], v[23:24]
	v_ldexp_f64 v[43:44], v[23:24], 1
	v_add_f64 v[15:16], v[15:16], -v[27:28]
	v_fma_f64 v[27:28], v[19:20], v[19:20], -v[29:30]
	v_add_f64 v[17:18], v[17:18], -v[33:34]
	v_fma_f64 v[33:34], v[23:24], v[23:24], -v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[45:46], v[15:16], v[15:16]
	v_ldexp_f64 v[47:48], v[15:16], 1
	v_add_f64 v[49:50], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[19:20], v[45:46], v[27:28]
	v_fma_f64 v[33:34], v[23:24], v[49:50], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[45:46], v[29:30], v[27:28]
	v_fma_f64 v[51:52], v[45:46], s[18:19], s[16:17]
	v_add_f64 v[29:30], v[45:46], -v[29:30]
	v_mul_f64 v[53:54], v[19:20], v[45:46]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[51:52], v[45:46], v[51:52], s[20:21]
	v_add_f64 v[27:28], v[27:28], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[45:46], v[19:20], -v[53:54]
	v_fma_f64 v[51:52], v[45:46], v[51:52], s[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[45:46], v[15:16], v[29:30]
	v_fma_f64 v[29:30], v[45:46], v[51:52], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[27:28], v[19:20], v[15:16]
	v_fma_f64 v[29:30], v[45:46], v[29:30], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[45:46], v[29:30], s[28:29]
	v_fma_f64 v[29:30], v[45:46], v[29:30], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[45:46], v[29:30], s[34:35]
	v_mul_f64 v[51:52], v[45:46], v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[45:46], v[45:46], v[29:30], -v[51:52]
	v_fma_f64 v[29:30], v[27:28], v[29:30], v[45:46]
	v_add_f64 v[27:28], v[53:54], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[45:46], v[51:52], v[29:30]
	v_add_f64 v[53:54], v[27:28], -v[53:54]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[55:56], v[45:46], s[14:15]
	v_add_f64 v[51:52], v[45:46], -v[51:52]
	v_add_f64 v[15:16], v[15:16], -v[53:54]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[57:58], v[55:56], s[66:67]
	v_add_f64 v[29:30], v[29:30], -v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[45:46], v[45:46], -v[57:58]
	v_add_f64 v[29:30], v[29:30], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[29:30], v[45:46]
	v_ldexp_f64 v[45:46], v[17:18], 1
	v_add_f64 v[29:30], v[55:56], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[51:52], v[55:56], -v[29:30]
	v_mul_f64 v[55:56], v[27:28], v[29:30]
	v_add_f64 v[19:20], v[19:20], v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[51:52], v[27:28], v[29:30], -v[55:56]
	v_fma_f64 v[19:20], v[27:28], v[19:20], v[51:52]
	v_add_f64 v[27:28], v[35:36], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[15:16], v[29:30], v[19:20]
	v_add_f64 v[19:20], v[27:28], -v[35:36]
	v_fma_f64 v[29:30], v[27:28], s[18:19], s[16:17]
	v_mul_f64 v[49:50], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[35:36], v[55:56], v[15:16]
	v_add_f64 v[19:20], v[33:34], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[20:21]
	v_fma_f64 v[53:54], v[27:28], v[23:24], -v[49:50]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[31:32], v[35:36]
	v_add_f64 v[51:52], v[35:36], -v[55:56]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[27:28], v[17:18], v[53:54]
	v_add_f64 v[31:32], v[33:34], -v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[15:16], -v[51:52]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[19:20], v[23:24], v[17:18]
	v_add_f64 v[31:32], v[35:36], -v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[47:48], v[15:16]
	v_fma_f64 v[23:24], v[27:28], v[29:30], s[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[49:50], v[17:18]
	v_add_f64 v[15:16], v[15:16], v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[27:28], v[23:24], s[28:29]
	v_add_f64 v[35:36], v[29:30], -v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[31:32], v[33:34], v[15:16]
	v_fma_f64 v[23:24], v[27:28], v[23:24], s[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], -v[35:36]
	v_add_f64 v[47:48], v[37:38], v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[27:28], v[23:24], s[34:35]
	v_add_f64 v[33:34], v[31:32], -v[33:34]
	v_add_f64 v[35:36], v[47:48], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[51:52], v[27:28], v[23:24]
	v_add_f64 v[15:16], v[15:16], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[49:50], v[47:48], -v[35:36]
	v_add_f64 v[31:32], v[31:32], -v[35:36]
	v_fma_f64 v[27:28], v[27:28], v[23:24], -v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[35:36], v[21:22], v[15:16]
	v_add_f64 v[33:34], v[37:38], -v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[27:28]
	v_add_f64 v[23:24], v[35:36], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[31:32], v[33:34]
	v_add_f64 v[33:34], v[35:36], -v[23:24]
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[27:28], v[35:36], v[31:32]
	v_add_f64 v[31:32], v[51:52], v[19:20]
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[47:48], v[27:28]
	v_add_f64 v[37:38], v[31:32], s[14:15]
	v_add_f64 v[33:34], v[31:32], -v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[15:16], v[21:22]
	v_add_f64 v[23:24], v[35:36], -v[47:48]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[47:48], v[37:38], s[66:67]
	v_add_f64 v[19:20], v[19:20], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[27:28], -v[23:24]
	v_add_f64 v[23:24], v[31:32], -v[47:48]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], s[40:41]
	v_add_f64 v[15:16], v[15:16], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[19:20], v[23:24]
	v_add_f64 v[21:22], v[35:36], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[37:38], v[19:20]
	v_add_f64 v[23:24], v[21:22], -v[35:36]
	v_mul_f64 v[27:28], v[5:6], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[37:38], -v[31:32]
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[5:6], v[21:22], -v[27:28]
	v_mul_f64 v[23:24], v[29:30], v[31:32]
	v_add_f64 v[19:20], v[19:20], v[33:34]
	v_cmp_class_f64_e64 vcc_lo, v[27:28], 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[15:16], v[5:6], v[15:16], v[21:22]
	v_fma_f64 v[21:22], v[29:30], v[31:32], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[27:28], v[15:16]
	v_fma_f64 v[19:20], v[29:30], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v22, v34, v28 :: v_dual_cndmask_b32 v21, v33, v27
	v_fma_f64 v[17:18], v[17:18], v[31:32], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[29:30], v[21:22], s[42:43]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[21:22]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[21:22]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[21:22]
	v_rndne_f64_e32 v[19:20], v[29:30]
	v_add_f64 v[29:30], v[23:24], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[19:20], s[68:69], v[21:22]
	v_add_f64 v[31:32], v[43:44], v[29:30]
	v_add_f64 v[23:24], v[29:30], -v[23:24]
	v_cvt_i32_f64_e32 v7, v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[35:36], v[19:20], s[70:71], v[35:36]
	v_add_f64 v[37:38], v[31:32], -v[43:44]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	v_add_f64 v[23:24], v[29:30], -v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[35:36], s[46:47], s[44:45]
	v_add_f64 v[17:18], v[45:46], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[35:36], v[29:30], s[48:49]
	v_add_f64 v[17:18], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[35:36], v[29:30], s[50:51]
	v_add_f64 v[29:30], v[31:32], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[35:36], v[23:24], s[52:53]
	v_add_f64 v[37:38], v[41:42], v[29:30]
	v_add_f64 v[31:32], v[29:30], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[35:36], v[23:24], s[54:55]
	v_add_f64 v[39:40], v[37:38], -v[41:42]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], -v[31:32]
	v_fma_f64 v[23:24], v[35:36], v[23:24], s[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[43:44], v[37:38], -v[39:40]
	v_add_f64 v[29:30], v[29:30], -v[39:40]
	v_add_f64 v[39:40], v[25:26], v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[35:36], v[23:24], s[58:59]
	v_add_f64 v[31:32], v[41:42], -v[43:44]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[35:36], v[23:24], s[60:61]
	v_add_f64 v[29:30], v[29:30], v[31:32]
	v_add_f64 v[31:32], v[39:40], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[35:36], v[23:24], s[62:63]
	v_add_f64 v[29:30], v[39:40], v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[39:40], v[39:40], -v[31:32]
	v_add_f64 v[17:18], v[17:18], -v[31:32]
	v_fma_f64 v[23:24], v[35:36], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[31:32], v[37:38], v[29:30]
	v_add_f64 v[25:26], v[25:26], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[35:36], v[23:24], 1.0
	v_add_f64 v[23:24], v[31:32], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[17:18], v[17:18], v[25:26]
	v_add_f64 v[25:26], v[33:34], -v[27:28]
	v_ldexp_f64 v[19:20], v[19:20], v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[29:30], -v[23:24]
	v_add_f64 v[15:16], v[15:16], -v[25:26]
	v_mul_f64 v[26:27], v[5:6], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, 0x7ff00000, v20, s0
	v_add_f64 v[17:18], v[17:18], v[23:24]
	v_trunc_f64_e32 v[20:21], v[5:6]
	v_dual_cndmask_b32 v16, 0, v16 :: v_dual_cndmask_b32 v15, 0, v15
	s_and_b32 vcc_lo, s1, s0
	v_cndmask_b32_e64 v23, 0, v7, s1
	v_cndmask_b32_e32 v22, 0, v19, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f64 v[15:16], v[22:23], v[15:16], v[22:23]
	v_cmp_class_f64_e64 s0, v[22:23], 0x204
	v_add_f64 v[24:25], v[31:32], v[17:18]
	v_cmp_eq_f64_e64 s1, v[20:21], v[5:6]
	v_cndmask_b32_e64 v6, 2.0, 0x3ff00000, vcc_lo
	v_cndmask_b32_e64 v7, v15, v22, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[24:25], -v[31:32]
	v_mul_f64 v[19:20], v[5:6], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], -v[28:29]
	v_fma_f64 v[21:22], v[5:6], v[24:25], -v[19:20]
	v_cmp_class_f64_e64 vcc_lo, v[19:20], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[5:6], v[17:18], v[21:22]
	v_add_f64 v[21:22], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v25, v22, v20 :: v_dual_cndmask_b32 v24, v21, v19
	v_add_f64 v[19:20], v[21:22], -v[19:20]
	v_mul_f64 v[28:29], v[24:25], s[42:43]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[24:25]|
	v_cmp_nlt_f64_e64 s2, 0x40900000, v[24:25]
	v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[24:25]
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	v_mul_f64 v[19:20], v[5:6], 0.5
	v_rndne_f64_e32 v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, 0, v17, vcc_lo
	v_fma_f64 v[30:31], v[28:29], s[68:69], v[24:25]
	v_cvt_i32_f64_e32 v9, v[28:29]
	v_trunc_f64_e32 v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[28:29], s[70:71], v[30:31]
	v_fma_f64 v[32:33], v[30:31], s[46:47], s[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[48:49]
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[52:53]
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[56:57]
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[58:59]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[60:61]
	v_fma_f64 v[32:33], v[30:31], v[32:33], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[32:33], v[30:31], v[32:33], 1.0
	v_fma_f64 v[28:29], v[30:31], v[32:33], 1.0
	v_trunc_f64_e32 v[30:31], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[21:22], v[28:29], v9
	v_trunc_f64_e32 v[28:29], v[5:6]
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	s_and_b32 vcc_lo, s3, s2
	v_cndmask_b32_e32 v21, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 0x7ff00000, v22, s2
	v_cmp_neq_f64_e64 s2, v[24:25], v[26:27]
	v_cmp_eq_f64_e64 s5, v[28:29], v[5:6]
	v_cmp_eq_u32_e32 vcc_lo, s4, v12
	v_cndmask_b32_e64 v6, v16, v23, s0
	v_cndmask_b32_e64 v22, 0, v9, s3
	v_cmp_neq_f64_e64 s3, v[30:31], v[19:20]
	v_cndmask_b32_e64 v16, 0, v7, s1
	v_cndmask_b32_e64 v9, 0x7ff00000, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[21:22], v[17:18], v[21:22]
	v_cmp_class_f64_e64 s4, v[21:22], 0x204
	s_and_b32 s0, s1, s2
	v_cndmask_b32_e64 v19, 0x3ff00000, v10, s0
	v_cndmask_b32_e64 v10, 0, v10, s0
	v_cmp_gt_i32_e64 s0, 0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v6, 0x7fffffff, v6, v19
	v_bfi_b32 v9, 0x7fffffff, v9, v10
	v_cndmask_b32_e64 v15, v17, v21, s4
	v_cndmask_b32_e64 v17, 0x7ff00000, 0, s6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, 0x7ff80000, v6, s1
	v_cndmask_b32_e64 v10, v6, v10, s0
	v_cndmask_b32_e64 v6, v7, v16, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v10, v9, vcc_lo
	v_cndmask_b32_e64 v6, v6, 0, vcc_lo
	s_and_b32 vcc_lo, s5, s3
	v_cndmask_b32_e64 v9, v18, v22, s4
	v_cndmask_b32_e32 v14, 0x3ff00000, v8, vcc_lo
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cndmask_b32_e64 v10, 0, v15, s5
	v_cmp_gt_i32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v9, 0x7fffffff, v9, v14
	v_bfi_b32 v14, 0x7fffffff, v17, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v8, 0x7ff80000, v9, s5
	v_dual_cndmask_b32 v9, v9, v8 :: v_dual_cndmask_b32 v8, v15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v9, v14, s6
	v_cndmask_b32_e64 v8, v8, 0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_cndmask_b32_e64 v10, 0, 0xffffff80, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v8, 8, v8
	v_ldexp_f64 v[6:7], v[6:7], v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[8:9], v[6:7]
	v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[13:14], v[6:7], v[8:9]
	v_mul_f64 v[8:9], v[8:9], 0.5
	v_fma_f64 v[15:16], -v[8:9], v[13:14], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[8:9], v[8:9], v[15:16], v[8:9]
	v_fma_f64 v[15:16], -v[13:14], v[13:14], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[15:16], v[8:9], v[13:14]
	v_fma_f64 v[15:16], -v[13:14], v[13:14], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[15:16], v[8:9], v[13:14]
	v_ldexp_f64 v[8:9], v[8:9], v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v9, v7 :: v_dual_cndmask_b32 v6, v8, v6
	v_cmp_lt_f64_e32 vcc_lo, v[6:7], v[3:4]
	v_cndmask_b32_e64 v0, v0, s13, vcc_lo
	s_add_i32 s13, s13, 1
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v6
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s7, s13
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_4
.LBB0_3:
	v_mov_b32_e32 v0, -1
.LBB0_4:                                ; %Flow40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9voronoi_dPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 59
		.amdhsa_next_free_sgpr 72
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9voronoi_dPiS_ii, .Lfunc_end0-_Z9voronoi_dPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4160
; NumSgprs: 74
; NumVgprs: 59
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 74
; NumVGPRsForWavesPerEU: 59
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9voronoi_dPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     74
    .sgpr_spill_count: 0
    .symbol:         _Z9voronoi_dPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     59
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
