#include <iostream>
#include <algorithm>
#include <stdio.h>
using namespace std;

#define BLOCK_SIZE 16
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

static void HandleError(cudaError_t err, const char *file, int line)
{
    if (err != cudaSuccess) {
        printf("%s in %s at line %d\n", cudaGetErrorString( err ), file, line);
        exit(EXIT_FAILURE);
    }
}

__global__ void add(int *a, int *b, int *c, int n) {
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    if (index < n)
        c[index] = a[index] + b[index];
    }

void print_mat(const char * name, int r, int c, double *m){
    printf("Printing %s\n", name);
    for (int i = 0; i < r; i++) {
        for (int j = 0; j < c; j++) {
            printf("%.2lf ", m[i * c + j]);
        }
        printf("\n");
    }
}

/*

    Leaky RELU

*/
__global__  void gpu_l_relu(double *res, int n, int k, int channel){
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int offset = blockIdx.z * n * k;
    if( col < k && row < n) 
    {
        int index = offset + row * k + col;
        if(res[index] < 0.0) res[index] *= 0.1;
    }
}

extern "C" {
    void leaky_relu(double *res, int n, int k, int channel){
        // Allocate memory space on the device 
        double *dev_res;
        cudaMalloc((void **) &dev_res, sizeof(double)*n*k*channel);

        // copy matrix A and B from host to device memory
        cudaMemcpy(dev_res, res, sizeof(double)*n*k*channel, cudaMemcpyHostToDevice);

        unsigned int gridev_rows = (n + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int channels = channel;
        dim3 dimGrid(gridev_cols, gridev_rows, channels);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_l_relu<<<dimGrid, dimBlock>>>(dev_res, n, k, channel);    

        // Transefr results from device to host 
        cudaMemcpy(res, dev_res, sizeof(double)*n*k*channel, cudaMemcpyDeviceToHost);
        cudaDeviceSynchronize();

        // free memory
        cudaFree(dev_res);
    }
}


/*

    Batch Norm

*/
__global__ void gpu_b_norm (double *res, double *mean, double *gamma, 
                    double *variance, int n, int k, int channel){
    
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int offset = blockIdx.z * n * k;
    if( col < k && row < n) {
            int index = offset + row * k + col;
            // double divisor = sqrt(variance[blockIdx.z] + epsilon);
            double divident = gamma[blockIdx.z] * (res[index] - mean[blockIdx.z]);
            res[index] = divident / variance[blockIdx.z];
    }
}

extern "C" {
    void batch_norm(double *res, double *mean, double *gamma, 
                    double *variance, int n, int k, int channel){
        // Allocate memory space on the device 
        double *dev_res, *dev_mean, *dev_gamma, *dev_variance;
        cudaMalloc((void **) &dev_res, sizeof(double)*n*k*channel);

        cudaMalloc((void **) &dev_mean, sizeof(double)*channel);
        cudaMalloc((void **) &dev_gamma, sizeof(double)*channel);
        cudaMalloc((void **) &dev_variance, sizeof(double)*channel);

        // copy matrix A and B from host to device memory
        cudaMemcpy(dev_res, res, sizeof(double)*n*k*channel, cudaMemcpyHostToDevice);

        cudaMemcpy(dev_mean, mean, sizeof(double)*channel, cudaMemcpyHostToDevice);
        cudaMemcpy(dev_gamma, gamma, sizeof(double)*channel, cudaMemcpyHostToDevice);
        cudaMemcpy(dev_variance, variance, sizeof(double)*channel, cudaMemcpyHostToDevice);

        unsigned int gridev_rows = (n + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int channels = channel;
        dim3 dimGrid(gridev_cols, gridev_rows, channels);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_b_norm<<<dimGrid, dimBlock>>>(dev_res, dev_mean, dev_gamma, dev_variance, 
                                            n, k, channel);    

        // Transefr results from device to host 
        cudaMemcpy(res, dev_res, sizeof(double)*n*k*channel, cudaMemcpyDeviceToHost);
        cudaDeviceSynchronize();

        // free memory
        cudaFree(dev_res);
    }
}

/*

    Add Bias

*/

__global__ void gpu_add_bias (double *res, double *bias, int n, int k, int channel){
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int offset = blockIdx.z * n * k;
    if( col < k && row < n) 
    {
        res[offset + row * k + col] += bias[blockIdx.z];
    }
}

extern "C" {
    void add_bias(double * C, double * bias, int n, int k, int channel){
        // Allocate memory space on the device 
        double *dev_b, *dev_c;
        cudaMalloc((void **) &dev_b, sizeof(double)*channel);
        cudaMalloc((void **) &dev_c, sizeof(double)*n*k*channel);

        // copy matrix A and B from host to device memory
        cudaMemcpy(dev_b, bias, sizeof(double)*channel, cudaMemcpyHostToDevice);
        cudaMemcpy(dev_c, C, sizeof(double)*n*k*channel, cudaMemcpyHostToDevice);

        unsigned int gridev_rows = (n + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int channels = channel;
        dim3 dimGrid(gridev_cols, gridev_rows, channels);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_add_bias<<<dimGrid, dimBlock>>>(dev_c, dev_b, n, k, channel);    

        // Transefr results from device to host 
        cudaMemcpy(C, dev_c, sizeof(double)*n*k*channel, cudaMemcpyDeviceToHost);
        cudaDeviceSynchronize();

        // free memory
        cudaFree(dev_b);
        cudaFree(dev_c);
    }
}

/*

    MAX Pool

*/

__global__ void gpu_max (double *res, double *cols, int n, int size){
    int index = threadIdx.x + blockIdx.x * blockDim.x;

    if (index < n)
    {
        int offset = index;
        // printf("%d\n", offset);
        double max = -10000.0;
        for(int i =0; i<size; i++){
            if(cols[offset + i*n] > max){
                max = cols[offset + i*n];
            } 
        }
        // printf("Max value for index %d: %.2lf\n", index, max);
        res[index] = max;
    }
}

extern "C" {
    void maxpool(double * C, double * cols, int n, int size){
        // Allocate memory space on the device 
        double *dev_cols, *dev_c;

        cudaMalloc((void **) &dev_cols, sizeof(double)*n*size);
        cudaMalloc((void **) &dev_c, sizeof(double)*n);

        // copy matrix A and B from host to device memory
        cudaMemcpy(dev_cols, cols, sizeof(double)*n*size, cudaMemcpyHostToDevice);
        cudaMemcpy(dev_c, C, sizeof(double)*n, cudaMemcpyHostToDevice);

        // Launch kernel 
        gpu_max<<<(n + 1024 - 1)/1024, 1024>>>( dev_c, dev_cols, n, size);   

        // Transefr results from device to host 
        cudaMemcpy(C, dev_c, sizeof(double)*n, cudaMemcpyDeviceToHost);
        cudaDeviceSynchronize();

        // free memory
        cudaFree(dev_cols);
        cudaFree(dev_c);
    }
}

/*

    Convolution

*/
__global__ void gpu_multABtoC(double *a,double *b, double *c, int m, int n, int k)
{ 
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    double sum = 0.0;
    if( col < k && row < m) 
    {
        for(int i = 0; i < n; i++) 
        {
            sum += a[row * n + i] * b[i * k + col];
        }
        c[row * k + col] = sum;
    }
} 

extern "C"{
    void conv2d(double *C, double *A, double *B, int m, int n, int k)
    {
        // Allocate memory space on the device 
        double *dev_a, *dev_b, *dev_c;
        cudaMalloc((void **) &dev_a, sizeof(double)*m*n);
        cudaMalloc((void **) &dev_b, sizeof(double)*n*k);
        cudaMalloc((void **) &dev_c, sizeof(double)*m*k);

        // copy matrix A and B from host to device memory
        cudaMemcpy(dev_a, A, sizeof(double)*m*n, cudaMemcpyHostToDevice);
        cudaMemcpy(dev_b, B, sizeof(double)*n*k, cudaMemcpyHostToDevice);
        cudaMemcpy(dev_c, C, sizeof(double)*m*k, cudaMemcpyHostToDevice);

        unsigned int gridev_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        dim3 dimGrid(gridev_cols, gridev_rows);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_multABtoC<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, m, n, k);    

        // Transefr results from device to host 
        cudaMemcpy(C, dev_c, sizeof(double)*m*k, cudaMemcpyDeviceToHost);
        cudaDeviceSynchronize();

        // free memory
        cudaFree(dev_a);
        cudaFree(dev_b);
        cudaFree(dev_c);
    }
}
	.file	"tmpxft_0024c8b1_00000000-6_dnn_cuda.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3898:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3898:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Printing %s\n"
.LC1:
	.string	"%.2lf "
.LC2:
	.string	"\n"
	.text
	.globl	_Z9print_matPKciiPd
	.type	_Z9print_matPKciiPd, @function
_Z9print_matPKciiPd:
.LFB3890:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%eax, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%esi, %r14d
	leaq	.LC0(%rip), %rsi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	movq	%rdi, %rdx
	movl	$2, %edi
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	__printf_chk@PLT
.L3:
	cmpl	%r14d, %r13d
	jge	.L2
	movslq	%r12d, %rax
	xorl	%r15d, %r15d
	leaq	0(%rbp,%rax,8), %rcx
.L6:
	cmpl	%r15d, %ebx
	jle	.L9
	movsd	(%rcx,%r15,8), %xmm0
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movq	%rcx, 8(%rsp)
	incq	%r15
	call	__printf_chk@PLT
	movq	8(%rsp), %rcx
	jmp	.L6
.L9:
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	incl	%r13d
	addl	%ebx, %r12d
	movl	$2, %edi
	call	__printf_chk@PLT
	jmp	.L3
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3890:
	.size	_Z9print_matPKciiPd, .-_Z9print_matPKciiPd
	.globl	_Z27__device_stub__Z3addPiS_S_iPiS_S_i
	.type	_Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3920:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3addPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3920:
	.size	_Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
	.globl	_Z3addPiS_S_i
	.type	_Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3921:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3addPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3921:
	.size	_Z3addPiS_S_i, .-_Z3addPiS_S_i
	.globl	_Z33__device_stub__Z10gpu_l_reluPdiiiPdiii
	.type	_Z33__device_stub__Z10gpu_l_reluPdiiiPdiii, @function
_Z33__device_stub__Z10gpu_l_reluPdiiiPdiii:
.LFB3922:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10gpu_l_reluPdiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3922:
	.size	_Z33__device_stub__Z10gpu_l_reluPdiiiPdiii, .-_Z33__device_stub__Z10gpu_l_reluPdiiiPdiii
	.globl	_Z10gpu_l_reluPdiii
	.type	_Z10gpu_l_reluPdiii, @function
_Z10gpu_l_reluPdiii:
.LFB3923:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10gpu_l_reluPdiiiPdiii
	.cfi_endproc
.LFE3923:
	.size	_Z10gpu_l_reluPdiii, .-_Z10gpu_l_reluPdiii
	.globl	leaky_relu
	.type	leaky_relu, @function
leaky_relu:
.LFB3891:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movslq	%edx, %rbx
	movq	%rbx, %r12
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movslq	%ecx, %rax
	leaq	8(%rsp), %rdi
	imulq	%rax, %rbx
	movslq	%esi, %rax
	imulq	%rax, %rbx
	salq	$3, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	15(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16, %ecx
	cltd
	movl	%r13d, %esi
	idivl	%ecx
	movl	%eax, 16(%rsp)
	leal	15(%rbp), %eax
	cltd
	idivl	%ecx
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	%eax, 20(%rsp)
	movq	16(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	8(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movl	%ebp, %esi
	call	_Z33__device_stub__Z10gpu_l_reluPdiiiPdiii
.L21:
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	movl	$2, %ecx
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3891:
	.size	leaky_relu, .-leaky_relu
	.globl	_Z39__device_stub__Z10gpu_b_normPdS_S_S_iiiPdS_S_S_iii
	.type	_Z39__device_stub__Z10gpu_b_normPdS_S_S_iiiPdS_S_S_iii, @function
_Z39__device_stub__Z10gpu_b_normPdS_S_S_iiiPdS_S_S_iii:
.LFB3924:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10gpu_b_normPdS_S_S_iii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L24:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3924:
	.size	_Z39__device_stub__Z10gpu_b_normPdS_S_S_iiiPdS_S_S_iii, .-_Z39__device_stub__Z10gpu_b_normPdS_S_S_iiiPdS_S_S_iii
	.globl	_Z10gpu_b_normPdS_S_S_iii
	.type	_Z10gpu_b_normPdS_S_S_iii, @function
_Z10gpu_b_normPdS_S_S_iii:
.LFB3925:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z10gpu_b_normPdS_S_S_iiiPdS_S_S_iii
	.cfi_endproc
.LFE3925:
	.size	_Z10gpu_b_normPdS_S_S_iii, .-_Z10gpu_b_normPdS_S_S_iii
	.globl	batch_norm
	.type	batch_norm, @function
batch_norm:
.LFB3892:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	movslq	%r8d, %rdx
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r9d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 8(%rsp)
	movslq	144(%rsp), %rbx
	leaq	16(%rsp), %rdi
	salq	$3, %rbx
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movslq	%r9d, %rax
	imulq	%rbx, %rax
	imulq	%rdx, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	15(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16, %ecx
	cltd
	movl	144(%rsp), %esi
	idivl	%ecx
	movl	%eax, 48(%rsp)
	leal	15(%rbp), %eax
	cltd
	idivl	%ecx
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	%eax, 52(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	152(%rsp), %eax
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	pushq	%rax
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z39__device_stub__Z10gpu_b_normPdS_S_S_iiiPdS_S_S_iii
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L30:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rdx
	movl	$2, %ecx
	movq	16(%rsp), %rsi
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3892:
	.size	batch_norm, .-batch_norm
	.globl	_Z37__device_stub__Z12gpu_add_biasPdS_iiiPdS_iii
	.type	_Z37__device_stub__Z12gpu_add_biasPdS_iiiPdS_iii, @function
_Z37__device_stub__Z12gpu_add_biasPdS_iiiPdS_iii:
.LFB3926:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12gpu_add_biasPdS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3926:
	.size	_Z37__device_stub__Z12gpu_add_biasPdS_iiiPdS_iii, .-_Z37__device_stub__Z12gpu_add_biasPdS_iiiPdS_iii
	.globl	_Z12gpu_add_biasPdS_iii
	.type	_Z12gpu_add_biasPdS_iii, @function
_Z12gpu_add_biasPdS_iii:
.LFB3927:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12gpu_add_biasPdS_iiiPdS_iii
	.cfi_endproc
.LFE3927:
	.size	_Z12gpu_add_biasPdS_iii, .-_Z12gpu_add_biasPdS_iii
	.globl	add_bias
	.type	add_bias, @function
add_bias:
.LFB3893:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movslq	%r8d, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%edx, %rbx
	leaq	0(,%r14,8), %rdx
	movq	%rdx, %rsi
	movq	%rbx, %rbp
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, (%rsp)
	leaq	16(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rdx, 8(%rsp)
	call	cudaMalloc@PLT
	movslq	%r12d, %rax
	leaq	24(%rsp), %rdi
	imulq	%rax, %rbx
	imulq	%r14, %rbx
	salq	$3, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	15(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16, %ecx
	cltd
	movl	%r14d, %esi
	idivl	%ecx
	movl	%eax, 32(%rsp)
	leal	15(%rbp), %eax
	cltd
	idivl	%ecx
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	%eax, 36(%rsp)
	movq	32(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	%r14d, %r8d
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z37__device_stub__Z12gpu_add_biasPdS_iiiPdS_iii
.L39:
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3893:
	.size	add_bias, .-add_bias
	.globl	_Z30__device_stub__Z7gpu_maxPdS_iiPdS_ii
	.type	_Z30__device_stub__Z7gpu_maxPdS_iiPdS_ii, @function
_Z30__device_stub__Z7gpu_maxPdS_iiPdS_ii:
.LFB3928:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7gpu_maxPdS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L42:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L44
	call	__stack_chk_fail@PLT
.L44:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3928:
	.size	_Z30__device_stub__Z7gpu_maxPdS_iiPdS_ii, .-_Z30__device_stub__Z7gpu_maxPdS_iiPdS_ii
	.globl	_Z7gpu_maxPdS_ii
	.type	_Z7gpu_maxPdS_ii, @function
_Z7gpu_maxPdS_ii:
.LFB3929:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z7gpu_maxPdS_iiPdS_ii
	.cfi_endproc
.LFE3929:
	.size	_Z7gpu_maxPdS_ii, .-_Z7gpu_maxPdS_ii
	.globl	maxpool
	.type	maxpool, @function
maxpool:
.LFB3894:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movslq	%ecx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%edx, %rbx
	movq	%rbp, %r14
	imulq	%rbx, %rbp
	movq	%rbx, %r12
	salq	$3, %rbx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	salq	$3, %rbp
	movq	%rsp, %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$1024, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leal	1023(%r12), %eax
	cltd
	idivl	%ecx
	movl	$4194305, %edx
	movl	$1, %ecx
	salq	$10, %rdx
	movl	%eax, 16(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	%r14d, %ecx
	movl	%r12d, %edx
	call	_Z30__device_stub__Z7gpu_maxPdS_iiPdS_ii
.L48:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3894:
	.size	maxpool, .-maxpool
	.globl	_Z40__device_stub__Z13gpu_multABtoCPdS_S_iiiPdS_S_iii
	.type	_Z40__device_stub__Z13gpu_multABtoCPdS_S_iiiPdS_S_iii, @function
_Z40__device_stub__Z13gpu_multABtoCPdS_S_iiiPdS_S_iii:
.LFB3930:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z13gpu_multABtoCPdS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L51:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3930:
	.size	_Z40__device_stub__Z13gpu_multABtoCPdS_S_iiiPdS_S_iii, .-_Z40__device_stub__Z13gpu_multABtoCPdS_S_iiiPdS_S_iii
	.globl	_Z13gpu_multABtoCPdS_S_iii
	.type	_Z13gpu_multABtoCPdS_S_iii, @function
_Z13gpu_multABtoCPdS_S_iii:
.LFB3931:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z13gpu_multABtoCPdS_S_iiiPdS_S_iii
	.cfi_endproc
.LFE3931:
	.size	_Z13gpu_multABtoCPdS_S_iii, .-_Z13gpu_multABtoCPdS_S_iii
	.globl	conv2d
	.type	conv2d, @function
conv2d:
.LFB3895:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%ecx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movslq	%r8d, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	movq	%r12, %r13
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r15, %rbx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdx, 16(%rsp)
	movq	%r15, %rdx
	imulq	%r12, %rdx
	movq	%rdi, (%rsp)
	leaq	40(%rsp), %rdi
	movq	%rsi, 8(%rsp)
	salq	$3, %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movq	%rdx, %rsi
	movq	%rdx, 24(%rsp)
	call	cudaMalloc@PLT
	movslq	%ebp, %rcx
	leaq	48(%rsp), %rdi
	leaq	0(,%rcx,8), %r14
	imulq	%r14, %r12
	imulq	%r14, %r15
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movq	%r15, %rsi
	movq	%r15, %r14
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	48(%rsp), %rdi
	movq	%r12, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	movq	56(%rsp), %rdi
	movq	%r15, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	15(%rbp), %eax
	movl	$16, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movl	$1, %esi
	idivl	%ecx
	movl	%eax, 64(%rsp)
	leal	15(%rbx), %eax
	cltd
	idivl	%ecx
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	%eax, 68(%rsp)
	movq	64(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L57
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%ebp, %r9d
	movl	%r13d, %r8d
	movq	40(%rsp), %rdi
	movl	%ebx, %ecx
	call	_Z40__device_stub__Z13gpu_multABtoCPdS_S_iiiPdS_S_iii
.L57:
	movq	56(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movq	%r14, %rdx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3895:
	.size	conv2d, .-conv2d
	.section	.rodata.str1.1
.LC3:
	.string	"_Z13gpu_multABtoCPdS_S_iii"
.LC4:
	.string	"_Z7gpu_maxPdS_ii"
.LC5:
	.string	"_Z12gpu_add_biasPdS_iii"
.LC6:
	.string	"_Z10gpu_b_normPdS_S_S_iii"
.LC7:
	.string	"_Z10gpu_l_reluPdiii"
.LC8:
	.string	"_Z3addPiS_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3933:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13gpu_multABtoCPdS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7gpu_maxPdS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12gpu_add_biasPdS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10gpu_b_normPdS_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10gpu_l_reluPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3addPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3933:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <stdio.h>
using namespace std;

#define BLOCK_SIZE 16
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

static void HandleError(hipError_t err, const char *file, int line)
{
    if (err != hipSuccess) {
        printf("%s in %s at line %d\n", hipGetErrorString( err ), file, line);
        exit(EXIT_FAILURE);
    }
}

__global__ void add(int *a, int *b, int *c, int n) {
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    if (index < n)
        c[index] = a[index] + b[index];
    }

void print_mat(const char * name, int r, int c, double *m){
    printf("Printing %s\n", name);
    for (int i = 0; i < r; i++) {
        for (int j = 0; j < c; j++) {
            printf("%.2lf ", m[i * c + j]);
        }
        printf("\n");
    }
}

/*

    Leaky RELU

*/
__global__  void gpu_l_relu(double *res, int n, int k, int channel){
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int offset = blockIdx.z * n * k;
    if( col < k && row < n) 
    {
        int index = offset + row * k + col;
        if(res[index] < 0.0) res[index] *= 0.1;
    }
}

extern "C" {
    void leaky_relu(double *res, int n, int k, int channel){
        // Allocate memory space on the device 
        double *dev_res;
        hipMalloc((void **) &dev_res, sizeof(double)*n*k*channel);

        // copy matrix A and B from host to device memory
        hipMemcpy(dev_res, res, sizeof(double)*n*k*channel, hipMemcpyHostToDevice);

        unsigned int gridev_rows = (n + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int channels = channel;
        dim3 dimGrid(gridev_cols, gridev_rows, channels);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_l_relu<<<dimGrid, dimBlock>>>(dev_res, n, k, channel);    

        // Transefr results from device to host 
        hipMemcpy(res, dev_res, sizeof(double)*n*k*channel, hipMemcpyDeviceToHost);
        hipDeviceSynchronize();

        // free memory
        hipFree(dev_res);
    }
}


/*

    Batch Norm

*/
__global__ void gpu_b_norm (double *res, double *mean, double *gamma, 
                    double *variance, int n, int k, int channel){
    
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int offset = blockIdx.z * n * k;
    if( col < k && row < n) {
            int index = offset + row * k + col;
            // double divisor = sqrt(variance[blockIdx.z] + epsilon);
            double divident = gamma[blockIdx.z] * (res[index] - mean[blockIdx.z]);
            res[index] = divident / variance[blockIdx.z];
    }
}

extern "C" {
    void batch_norm(double *res, double *mean, double *gamma, 
                    double *variance, int n, int k, int channel){
        // Allocate memory space on the device 
        double *dev_res, *dev_mean, *dev_gamma, *dev_variance;
        hipMalloc((void **) &dev_res, sizeof(double)*n*k*channel);

        hipMalloc((void **) &dev_mean, sizeof(double)*channel);
        hipMalloc((void **) &dev_gamma, sizeof(double)*channel);
        hipMalloc((void **) &dev_variance, sizeof(double)*channel);

        // copy matrix A and B from host to device memory
        hipMemcpy(dev_res, res, sizeof(double)*n*k*channel, hipMemcpyHostToDevice);

        hipMemcpy(dev_mean, mean, sizeof(double)*channel, hipMemcpyHostToDevice);
        hipMemcpy(dev_gamma, gamma, sizeof(double)*channel, hipMemcpyHostToDevice);
        hipMemcpy(dev_variance, variance, sizeof(double)*channel, hipMemcpyHostToDevice);

        unsigned int gridev_rows = (n + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int channels = channel;
        dim3 dimGrid(gridev_cols, gridev_rows, channels);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_b_norm<<<dimGrid, dimBlock>>>(dev_res, dev_mean, dev_gamma, dev_variance, 
                                            n, k, channel);    

        // Transefr results from device to host 
        hipMemcpy(res, dev_res, sizeof(double)*n*k*channel, hipMemcpyDeviceToHost);
        hipDeviceSynchronize();

        // free memory
        hipFree(dev_res);
    }
}

/*

    Add Bias

*/

__global__ void gpu_add_bias (double *res, double *bias, int n, int k, int channel){
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    int offset = blockIdx.z * n * k;
    if( col < k && row < n) 
    {
        res[offset + row * k + col] += bias[blockIdx.z];
    }
}

extern "C" {
    void add_bias(double * C, double * bias, int n, int k, int channel){
        // Allocate memory space on the device 
        double *dev_b, *dev_c;
        hipMalloc((void **) &dev_b, sizeof(double)*channel);
        hipMalloc((void **) &dev_c, sizeof(double)*n*k*channel);

        // copy matrix A and B from host to device memory
        hipMemcpy(dev_b, bias, sizeof(double)*channel, hipMemcpyHostToDevice);
        hipMemcpy(dev_c, C, sizeof(double)*n*k*channel, hipMemcpyHostToDevice);

        unsigned int gridev_rows = (n + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int channels = channel;
        dim3 dimGrid(gridev_cols, gridev_rows, channels);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_add_bias<<<dimGrid, dimBlock>>>(dev_c, dev_b, n, k, channel);    

        // Transefr results from device to host 
        hipMemcpy(C, dev_c, sizeof(double)*n*k*channel, hipMemcpyDeviceToHost);
        hipDeviceSynchronize();

        // free memory
        hipFree(dev_b);
        hipFree(dev_c);
    }
}

/*

    MAX Pool

*/

__global__ void gpu_max (double *res, double *cols, int n, int size){
    int index = threadIdx.x + blockIdx.x * blockDim.x;

    if (index < n)
    {
        int offset = index;
        // printf("%d\n", offset);
        double max = -10000.0;
        for(int i =0; i<size; i++){
            if(cols[offset + i*n] > max){
                max = cols[offset + i*n];
            } 
        }
        // printf("Max value for index %d: %.2lf\n", index, max);
        res[index] = max;
    }
}

extern "C" {
    void maxpool(double * C, double * cols, int n, int size){
        // Allocate memory space on the device 
        double *dev_cols, *dev_c;

        hipMalloc((void **) &dev_cols, sizeof(double)*n*size);
        hipMalloc((void **) &dev_c, sizeof(double)*n);

        // copy matrix A and B from host to device memory
        hipMemcpy(dev_cols, cols, sizeof(double)*n*size, hipMemcpyHostToDevice);
        hipMemcpy(dev_c, C, sizeof(double)*n, hipMemcpyHostToDevice);

        // Launch kernel 
        gpu_max<<<(n + 1024 - 1)/1024, 1024>>>( dev_c, dev_cols, n, size);   

        // Transefr results from device to host 
        hipMemcpy(C, dev_c, sizeof(double)*n, hipMemcpyDeviceToHost);
        hipDeviceSynchronize();

        // free memory
        hipFree(dev_cols);
        hipFree(dev_c);
    }
}

/*

    Convolution

*/
__global__ void gpu_multABtoC(double *a,double *b, double *c, int m, int n, int k)
{ 
    int row = blockIdx.y * blockDim.y + threadIdx.y; 
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    double sum = 0.0;
    if( col < k && row < m) 
    {
        for(int i = 0; i < n; i++) 
        {
            sum += a[row * n + i] * b[i * k + col];
        }
        c[row * k + col] = sum;
    }
} 

extern "C"{
    void conv2d(double *C, double *A, double *B, int m, int n, int k)
    {
        // Allocate memory space on the device 
        double *dev_a, *dev_b, *dev_c;
        hipMalloc((void **) &dev_a, sizeof(double)*m*n);
        hipMalloc((void **) &dev_b, sizeof(double)*n*k);
        hipMalloc((void **) &dev_c, sizeof(double)*m*k);

        // copy matrix A and B from host to device memory
        hipMemcpy(dev_a, A, sizeof(double)*m*n, hipMemcpyHostToDevice);
        hipMemcpy(dev_b, B, sizeof(double)*n*k, hipMemcpyHostToDevice);
        hipMemcpy(dev_c, C, sizeof(double)*m*k, hipMemcpyHostToDevice);

        unsigned int gridev_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
        unsigned int gridev_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
        dim3 dimGrid(gridev_cols, gridev_rows);
        dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    
        // Launch kernel 
        gpu_multABtoC<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, m, n, k);    

        // Transefr results from device to host 
        hipMemcpy(C, dev_c, sizeof(double)*m*k, hipMemcpyDeviceToHost);
        hipDeviceSynchronize();

        // free memory
        hipFree(dev_a);
        hipFree(dev_b);
        hipFree(dev_c);
    }
}
	.text
	.file	"dnn_cuda.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__addPiS_S_i   # -- Begin function _Z18__device_stub__addPiS_S_i
	.type	_Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i:          # @_Z18__device_stub__addPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z9print_matPKciiPd             # -- Begin function _Z9print_matPKciiPd
	.type	_Z9print_matPKciiPd,@function
_Z9print_matPKciiPd:                    # @_Z9print_matPKciiPd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, 8(%rsp)                   # 8-byte Spill
	movl	%edx, %ebp
	movl	%esi, %r14d
	movq	%rdi, %rsi
	xorl	%r15d, %r15d
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	testl	%r14d, %r14d
	jle	.LBB1_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%r14d, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%ebp, %r12d
	xorl	%r13d, %r13d
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%ebp, %ebp
	jle	.LBB1_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%r15d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,8), %rbx
	xorl	%r14d, %r14d
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%rbx,%r14,8), %xmm0            # xmm0 = mem[0],zero
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	%r14, %r12
	jne	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r13
	addl	%ebp, %r15d
	cmpq	16(%rsp), %r13                  # 8-byte Folded Reload
	jne	.LBB1_2
.LBB1_6:                                # %._crit_edge14
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z9print_matPKciiPd, .Lfunc_end1-_Z9print_matPKciiPd
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpu_l_reluPdiii # -- Begin function _Z25__device_stub__gpu_l_reluPdiii
	.type	_Z25__device_stub__gpu_l_reluPdiii,@function
_Z25__device_stub__gpu_l_reluPdiii:     # @_Z25__device_stub__gpu_l_reluPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_l_reluPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__gpu_l_reluPdiii, .Lfunc_end2-_Z25__device_stub__gpu_l_reluPdiii
	.cfi_endproc
                                        # -- End function
	.globl	leaky_relu                      # -- Begin function leaky_relu
	.type	leaky_relu,@function
leaky_relu:                             # @leaky_relu
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rbx
	movl	%esi, 12(%rsp)                  # 4-byte Spill
	movslq	%esi, %r13
	movl	%edx, 16(%rsp)                  # 4-byte Spill
	movslq	%edx, %r12
	movq	%r13, %r14
	imulq	%r12, %r14
	movl	%ecx, 20(%rsp)                  # 4-byte Spill
	movslq	%ecx, %rbp
	imulq	%rbp, %r14
	shlq	$3, %r14
	movq	%rsp, %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%r13), %eax
	addl	$30, %r13d
	testl	%eax, %eax
	cmovnsl	%eax, %r13d
	sarl	$4, %r13d
	leal	15(%r12), %eax
	addl	$30, %r12d
	testl	%eax, %eax
	cmovnsl	%eax, %r12d
	sarl	$4, %r12d
	shlq	$32, %r13
	orq	%r12, %r13
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r13, %rdi
	movl	%ebp, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	(%rsp), %rdi
	movl	12(%rsp), %esi                  # 4-byte Reload
	movl	16(%rsp), %edx                  # 4-byte Reload
	movl	20(%rsp), %ecx                  # 4-byte Reload
	callq	_Z25__device_stub__gpu_l_reluPdiii
.LBB3_2:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	leaky_relu, .Lfunc_end3-leaky_relu
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpu_b_normPdS_S_S_iii # -- Begin function _Z25__device_stub__gpu_b_normPdS_S_S_iii
	.type	_Z25__device_stub__gpu_b_normPdS_S_S_iii,@function
_Z25__device_stub__gpu_b_normPdS_S_S_iii: # @_Z25__device_stub__gpu_b_normPdS_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_b_normPdS_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__gpu_b_normPdS_S_S_iii, .Lfunc_end4-_Z25__device_stub__gpu_b_normPdS_S_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	batch_norm                      # -- Begin function batch_norm
	.type	batch_norm,@function
batch_norm:                             # @batch_norm
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	movq	%rdx, 56(%rsp)                  # 8-byte Spill
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	movq	%rdi, %r14
	movslq	128(%rsp), %rbp
	movl	%r8d, 16(%rsp)                  # 4-byte Spill
	movslq	%r8d, %r13
	movl	%r9d, 20(%rsp)                  # 4-byte Spill
	movslq	%r9d, %rbx
	movq	%r13, %r15
	imulq	%rbx, %r15
	imulq	%rbp, %r15
	shlq	$3, %r15
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	%rbp, %r12
	shlq	$3, %r12
	leaq	40(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%r13), %eax
	addl	$30, %r13d
	testl	%eax, %eax
	cmovnsl	%eax, %r13d
	sarl	$4, %r13d
	leal	15(%rbx), %eax
	addl	$30, %ebx
	testl	%eax, %eax
	cmovnsl	%eax, %ebx
	sarl	$4, %ebx
	shlq	$32, %r13
	orq	%rbx, %r13
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r13, %rdi
	movl	%ebp, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	%ebp, (%rsp)
	movl	16(%rsp), %r8d                  # 4-byte Reload
	movl	20(%rsp), %r9d                  # 4-byte Reload
	callq	_Z25__device_stub__gpu_b_normPdS_S_S_iii
.LBB5_2:
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	batch_norm, .Lfunc_end5-batch_norm
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__gpu_add_biasPdS_iii # -- Begin function _Z27__device_stub__gpu_add_biasPdS_iii
	.type	_Z27__device_stub__gpu_add_biasPdS_iii,@function
_Z27__device_stub__gpu_add_biasPdS_iii: # @_Z27__device_stub__gpu_add_biasPdS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12gpu_add_biasPdS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z27__device_stub__gpu_add_biasPdS_iii, .Lfunc_end6-_Z27__device_stub__gpu_add_biasPdS_iii
	.cfi_endproc
                                        # -- End function
	.globl	add_bias                        # -- Begin function add_bias
	.type	add_bias,@function
add_bias:                               # @add_bias
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	movl	%r8d, 36(%rsp)                  # 4-byte Spill
	movslq	%r8d, %r13
	leaq	(,%r13,8), %r15
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	%ebp, 28(%rsp)                  # 4-byte Spill
	movslq	%ebp, %r12
	movl	%ebx, 32(%rsp)                  # 4-byte Spill
	movslq	%ebx, %r14
	movq	%r12, %rbp
	imulq	%r14, %rbp
	imulq	%r13, %rbp
	shlq	$3, %rbp
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movq	48(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%r12), %eax
	addl	$30, %r12d
	testl	%eax, %eax
	cmovnsl	%eax, %r12d
	sarl	$4, %r12d
	leal	15(%r14), %eax
	addl	$30, %r14d
	testl	%eax, %eax
	cmovnsl	%eax, %r14d
	sarl	$4, %r14d
	shlq	$32, %r12
	orq	%r14, %r12
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	28(%rsp), %edx                  # 4-byte Reload
	movl	32(%rsp), %ecx                  # 4-byte Reload
	movl	36(%rsp), %r8d                  # 4-byte Reload
	callq	_Z27__device_stub__gpu_add_biasPdS_iii
.LBB7_2:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	add_bias, .Lfunc_end7-add_bias
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__gpu_maxPdS_ii # -- Begin function _Z22__device_stub__gpu_maxPdS_ii
	.type	_Z22__device_stub__gpu_maxPdS_ii,@function
_Z22__device_stub__gpu_maxPdS_ii:       # @_Z22__device_stub__gpu_maxPdS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7gpu_maxPdS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z22__device_stub__gpu_maxPdS_ii, .Lfunc_end8-_Z22__device_stub__gpu_maxPdS_ii
	.cfi_endproc
                                        # -- End function
	.globl	maxpool                         # -- Begin function maxpool
	.type	maxpool,@function
maxpool:                                # @maxpool
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r13
	movq	%rdi, 32(%rsp)                  # 8-byte Spill
	movl	%edx, 16(%rsp)                  # 4-byte Spill
	movslq	%edx, %r12
	leaq	(,%r12,8), %rbx
	movl	%ecx, 20(%rsp)                  # 4-byte Spill
	movslq	%ecx, %rbp
	imulq	%rbx, %rbp
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movq	32(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	1023(%r12), %eax
	addl	$2046, %r12d                    # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %r12d
	sarl	$10, %r12d
	btsq	$32, %r12
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	16(%rsp), %edx                  # 4-byte Reload
	movl	20(%rsp), %ecx                  # 4-byte Reload
	callq	_Z22__device_stub__gpu_maxPdS_ii
.LBB9_2:
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	maxpool, .Lfunc_end9-maxpool
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__gpu_multABtoCPdS_S_iii # -- Begin function _Z28__device_stub__gpu_multABtoCPdS_S_iii
	.type	_Z28__device_stub__gpu_multABtoCPdS_S_iii,@function
_Z28__device_stub__gpu_multABtoCPdS_S_iii: # @_Z28__device_stub__gpu_multABtoCPdS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13gpu_multABtoCPdS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z28__device_stub__gpu_multABtoCPdS_S_iii, .Lfunc_end10-_Z28__device_stub__gpu_multABtoCPdS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	conv2d                          # -- Begin function conv2d
	.type	conv2d,@function
conv2d:                                 # @conv2d
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebp
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, %r12
	movq	%rdi, 40(%rsp)                  # 8-byte Spill
	movl	%ecx, 28(%rsp)                  # 4-byte Spill
	movslq	%ecx, %r13
	leaq	(,%r13,8), %r14
	movl	%r8d, 32(%rsp)                  # 4-byte Spill
	movslq	%r8d, %r15
	movq	%r14, %rbx
	imulq	%r15, %rbx
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	%ebp, 36(%rsp)                  # 4-byte Spill
	movslq	%ebp, %rbp
	imulq	%rbp, %r15
	shlq	$3, %r15
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	imulq	%rbp, %r14
	movq	%rsp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r12, %rsi
	movq	%rbx, %rdx
	movq	40(%rsp), %rbx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%r13), %eax
	addl	$30, %r13d
	testl	%eax, %eax
	cmovnsl	%eax, %r13d
	sarl	$4, %r13d
	leal	15(%rbp), %eax
	addl	$30, %ebp
	testl	%eax, %eax
	cmovnsl	%eax, %ebp
	sarl	$4, %ebp
	shlq	$32, %r13
	orq	%rbp, %r13
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r13, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	28(%rsp), %ecx                  # 4-byte Reload
	movl	32(%rsp), %r8d                  # 4-byte Reload
	movl	36(%rsp), %r9d                  # 4-byte Reload
	callq	_Z28__device_stub__gpu_multABtoCPdS_S_iii
.LBB11_2:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	conv2d, .Lfunc_end11-conv2d
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB12_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB12_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_l_reluPdiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_b_normPdS_S_S_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12gpu_add_biasPdS_iii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7gpu_maxPdS_ii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13gpu_multABtoCPdS_S_iii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end12:
	.size	__hip_module_ctor, .Lfunc_end12-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB13_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB13_2:
	retq
.Lfunc_end13:
	.size	__hip_module_dtor, .Lfunc_end13-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3addPiS_S_i,@object           # @_Z3addPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z3addPiS_S_i
	.p2align	3, 0x0
_Z3addPiS_S_i:
	.quad	_Z18__device_stub__addPiS_S_i
	.size	_Z3addPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Printing %s\n"
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%.2lf "
	.size	.L.str.1, 7

	.type	_Z10gpu_l_reluPdiii,@object     # @_Z10gpu_l_reluPdiii
	.section	.rodata,"a",@progbits
	.globl	_Z10gpu_l_reluPdiii
	.p2align	3, 0x0
_Z10gpu_l_reluPdiii:
	.quad	_Z25__device_stub__gpu_l_reluPdiii
	.size	_Z10gpu_l_reluPdiii, 8

	.type	_Z10gpu_b_normPdS_S_S_iii,@object # @_Z10gpu_b_normPdS_S_S_iii
	.globl	_Z10gpu_b_normPdS_S_S_iii
	.p2align	3, 0x0
_Z10gpu_b_normPdS_S_S_iii:
	.quad	_Z25__device_stub__gpu_b_normPdS_S_S_iii
	.size	_Z10gpu_b_normPdS_S_S_iii, 8

	.type	_Z12gpu_add_biasPdS_iii,@object # @_Z12gpu_add_biasPdS_iii
	.globl	_Z12gpu_add_biasPdS_iii
	.p2align	3, 0x0
_Z12gpu_add_biasPdS_iii:
	.quad	_Z27__device_stub__gpu_add_biasPdS_iii
	.size	_Z12gpu_add_biasPdS_iii, 8

	.type	_Z7gpu_maxPdS_ii,@object        # @_Z7gpu_maxPdS_ii
	.globl	_Z7gpu_maxPdS_ii
	.p2align	3, 0x0
_Z7gpu_maxPdS_ii:
	.quad	_Z22__device_stub__gpu_maxPdS_ii
	.size	_Z7gpu_maxPdS_ii, 8

	.type	_Z13gpu_multABtoCPdS_S_iii,@object # @_Z13gpu_multABtoCPdS_S_iii
	.globl	_Z13gpu_multABtoCPdS_S_iii
	.p2align	3, 0x0
_Z13gpu_multABtoCPdS_S_iii:
	.quad	_Z28__device_stub__gpu_multABtoCPdS_S_iii
	.size	_Z13gpu_multABtoCPdS_S_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z3addPiS_S_i"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10gpu_l_reluPdiii"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10gpu_b_normPdS_S_S_iii"
	.size	.L__unnamed_3, 26

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z12gpu_add_biasPdS_iii"
	.size	.L__unnamed_4, 24

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z7gpu_maxPdS_ii"
	.size	.L__unnamed_5, 17

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z13gpu_multABtoCPdS_S_iii"
	.size	.L__unnamed_6, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__addPiS_S_i
	.addrsig_sym _Z25__device_stub__gpu_l_reluPdiii
	.addrsig_sym _Z25__device_stub__gpu_b_normPdS_S_S_iii
	.addrsig_sym _Z27__device_stub__gpu_add_biasPdS_iii
	.addrsig_sym _Z22__device_stub__gpu_maxPdS_ii
	.addrsig_sym _Z28__device_stub__gpu_multABtoCPdS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3addPiS_S_i
	.addrsig_sym _Z10gpu_l_reluPdiii
	.addrsig_sym _Z10gpu_b_normPdS_S_S_iii
	.addrsig_sym _Z12gpu_add_biasPdS_iii
	.addrsig_sym _Z7gpu_maxPdS_ii
	.addrsig_sym _Z13gpu_multABtoCPdS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3addPiS_S_i           ; -- Begin function _Z3addPiS_S_i
	.globl	_Z3addPiS_S_i
	.p2align	8
	.type	_Z3addPiS_S_i,@function
_Z3addPiS_S_i:                          ; @_Z3addPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10gpu_l_reluPdiii     ; -- Begin function _Z10gpu_l_reluPdiii
	.globl	_Z10gpu_l_reluPdiii
	.p2align	8
	.type	_Z10gpu_l_reluPdiii,@function
_Z10gpu_l_reluPdiii:                    ; @_Z10gpu_l_reluPdiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_3
; %bb.1:
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[3:4], null, v2, s5, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_mov_b32 s0, 0x9999999a
	s_mov_b32 s1, 0x3fb99999
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_f64 v[2:3], v[2:3], s[0:1]
	global_store_b64 v[0:1], v[2:3], off
.LBB1_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_l_reluPdiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10gpu_l_reluPdiii, .Lfunc_end1-_Z10gpu_l_reluPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10gpu_b_normPdS_S_S_iii ; -- Begin function _Z10gpu_b_normPdS_S_S_iii
	.globl	_Z10gpu_b_normPdS_S_S_iii
	.p2align	8
	.type	_Z10gpu_b_normPdS_S_S_iii,@function
_Z10gpu_b_normPdS_S_S_iii:              ; @_Z10gpu_b_normPdS_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[6:7], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s7, v0
	v_cmp_gt_i32_e64 s2, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_mov_b32 s4, s15
	s_load_b256 s[8:15], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, s4, s6, v[1:2]
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mad_u64_u32 v[3:4], null, v2, s7, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s12, s0
	s_addc_u32 s3, s13, s1
	v_lshlrev_b64 v[0:1], 3, v[3:4]
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[4:5], s[4:5], 0x0
	s_add_u32 s0, s14, s0
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_addc_u32 s1, s15, s1
	s_load_b64 s[0:1], s[0:1], 0x0
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], -s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], s[2:3], v[2:3]
	v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	v_div_fixup_f64 v[2:3], v[4:5], s[0:1], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_b_normPdS_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10gpu_b_normPdS_S_S_iii, .Lfunc_end2-_Z10gpu_b_normPdS_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 380
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12gpu_add_biasPdS_iii ; -- Begin function _Z12gpu_add_biasPdS_iii
	.globl	_Z12gpu_add_biasPdS_iii
	.p2align	8
	.type	_Z12gpu_add_biasPdS_iii,@function
_Z12gpu_add_biasPdS_iii:                ; @_Z12gpu_add_biasPdS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[6:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s7, v0
	v_cmp_gt_i32_e64 s2, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_mov_b32 s4, s15
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, s4, s6, v[1:2]
	s_mov_b32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s7, v[0:1]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	global_load_b64 v[2:3], v[0:1], off
	s_addc_u32 s1, s3, s1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], s[0:1], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12gpu_add_biasPdS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z12gpu_add_biasPdS_iii, .Lfunc_end3-_Z12gpu_add_biasPdS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7gpu_maxPdS_ii        ; -- Begin function _Z7gpu_maxPdS_ii
	.globl	_Z7gpu_maxPdS_ii
	.p2align	8
	.type	_Z7gpu_maxPdS_ii,@function
_Z7gpu_maxPdS_ii:                       ; @_Z7gpu_maxPdS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB4_5
; %bb.1:                                ; %.preheader
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0xc0c38800
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB4_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v5, v1
.LBB4_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_add_i32 s5, s5, -1
	s_cmp_eq_u32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[6:7], v[3:4]
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v5, s4, v5
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_cbranch_scc0 .LBB4_3
.LBB4_4:                                ; %Flow38
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
.LBB4_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7gpu_maxPdS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z7gpu_maxPdS_ii, .Lfunc_end4-_Z7gpu_maxPdS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13gpu_multABtoCPdS_S_iii ; -- Begin function _Z13gpu_multABtoCPdS_S_iii
	.globl	_Z13gpu_multABtoCPdS_S_iii
	.p2align	8
	.type	_Z13gpu_multABtoCPdS_S_iii,@function
_Z13gpu_multABtoCPdS_S_iii:             ; @_Z13gpu_multABtoCPdS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB5_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB5_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v1, s5
	v_mov_b32_e32 v6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 3, v[2:3]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
.LBB5_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v7, 31, v6
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s5, 0
	v_lshlrev_b64 v[7:8], 3, v[6:7]
	v_add_nc_u32_e32 v6, s6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b64 v[9:10], v[4:5], off
	global_load_b64 v[7:8], v[7:8], off
	v_add_co_u32 v4, vcc_lo, v4, 8
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc0 .LBB5_3
	s_branch .LBB5_5
.LBB5_4:
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
.LBB5_5:                                ; %Flow54
	v_mad_u64_u32 v[4:5], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB5_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13gpu_multABtoCPdS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z13gpu_multABtoCPdS_S_iii, .Lfunc_end5-_Z13gpu_multABtoCPdS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
