#include <bits/stdc++.h>
#include <cuda.h>

#define N 15
#define M 4096
__global__ void histogram_creation(int *A, int *hist, int no_of_threads) {
	
	int global_x = blockDim.x * blockIdx.x + threadIdx.x;
	__shared__ int local_hist[N+1];

	for(int i = threadIdx.x; i<=N; i = i + (blockDim.x ) ){
		local_hist[i] = 0;
	}
	__syncthreads();
	
	for(int i = global_x; i <= M; i = i + (blockDim.x * no_of_threads)) {
		atomicAdd(&local_hist[A[i]],1);
	}
	__syncthreads();
	
	for(int i = threadIdx.x ; i <= N; i = i + (blockDim.x) ) {
		atomicAdd(&hist[i],local_hist[i]);
		printf("%d histogram_local %d \n",local_hist[i],i);
	}
	__syncthreads();
	
}
__global__ void histogram_saturation(int *hist) {
	int index = threadIdx.x;
	if(hist[index] > 127) {
		hist[index] = 127;
	}
}
void handle_error(cudaError_t error) {
	if (error != cudaSuccess) {
		printf("Cuda Error. Exiting....\n");
		exit(0);
	}
}

void init_matrix( int A[], long long n) {
	for (long long i = 0; i< n; i++) {
		A[i] = rand() % 4096 + 1;
	}
}

int main() {
	int A[M];
	int hist[N +1];
	
	for(int i=0; i < N + 1; i++) {
		hist[i] = 0;
	}
	init_matrix(A, M);
	int *deviceA;
	int *deviceHist;
	
	size_t size_histogram = (N + 1) * sizeof(int);
	size_t size_array = M * sizeof(int);
	
	handle_error(cudaMalloc((void**) &deviceA, size_array));
	handle_error(cudaMalloc((void**) &deviceHist, size_histogram));
	
	cudaMemcpy(A, deviceA, size_array, cudaMemcpyHostToDevice);
	cudaMemcpy(hist, deviceHist, size_histogram, cudaMemcpyHostToDevice);
	dim3 grid_dim(256,1,1);
	dim3 block_dim(256,1,1);
	
	histogram_creation<<<grid_dim, block_dim>>>(deviceA, deviceHist,256);
	
	cudaMemcpy(hist, deviceHist, size_histogram, cudaMemcpyDeviceToHost);
	histogram_saturation<<<1,4096>>>(deviceHist);
	
	cudaMemcpy(hist, deviceHist, size_histogram, cudaMemcpyDeviceToHost);
	
	for(int i=0;i<=4096; i++)
	{
		printf("%d\n", hist[i]);
	}
} 


	.file	"tmpxft_0026feea_00000000-6_prog7.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10830:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE10830:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Cuda Error. Exiting....\n"
	.text
	.globl	_Z12handle_error9cudaError
	.type	_Z12handle_error9cudaError, @function
_Z12handle_error9cudaError:
.LFB10825:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10825:
	.size	_Z12handle_error9cudaError, .-_Z12handle_error9cudaError
	.globl	_Z11init_matrixPix
	.type	_Z11init_matrixPix, @function
_Z11init_matrixPix:
.LFB10826:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$4096, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 48
.L9:
	cmpq	%rbp, %rbx
	jge	.L12
	call	rand@PLT
	cltd
	idivl	%r13d
	incl	%edx
	movl	%edx, (%r12,%rbx,4)
	incq	%rbx
	jmp	.L9
.L12:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10826:
	.size	_Z11init_matrixPix, .-_Z11init_matrixPix
	.globl	_Z41__device_stub__Z18histogram_creationPiS_iPiS_i
	.type	_Z41__device_stub__Z18histogram_creationPiS_iPiS_i, @function
_Z41__device_stub__Z18histogram_creationPiS_iPiS_i:
.LFB10852:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18histogram_creationPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10852:
	.size	_Z41__device_stub__Z18histogram_creationPiS_iPiS_i, .-_Z41__device_stub__Z18histogram_creationPiS_iPiS_i
	.globl	_Z18histogram_creationPiS_i
	.type	_Z18histogram_creationPiS_i, @function
_Z18histogram_creationPiS_i:
.LFB10853:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z18histogram_creationPiS_iPiS_i
	.cfi_endproc
.LFE10853:
	.size	_Z18histogram_creationPiS_i, .-_Z18histogram_creationPiS_i
	.globl	_Z40__device_stub__Z20histogram_saturationPiPi
	.type	_Z40__device_stub__Z20histogram_saturationPiPi, @function
_Z40__device_stub__Z20histogram_saturationPiPi:
.LFB10854:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z20histogram_saturationPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L18:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10854:
	.size	_Z40__device_stub__Z20histogram_saturationPiPi, .-_Z40__device_stub__Z20histogram_saturationPiPi
	.globl	_Z20histogram_saturationPi
	.type	_Z20histogram_saturationPi, @function
_Z20histogram_saturationPi:
.LFB10855:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z20histogram_saturationPiPi
	.cfi_endproc
.LFE10855:
	.size	_Z20histogram_saturationPi, .-_Z20histogram_saturationPi
	.section	.rodata.str1.1
.LC1:
	.string	"%d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB10827:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	leaq	-16384(%rsp), %r11
	.cfi_def_cfa 11, 16408
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$152, %rsp
	.cfi_def_cfa_offset 16560
	movl	$16, %ecx
	movl	$4096, %esi
	movq	%fs:40, %rax
	movq	%rax, 16520(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rbx
	leaq	136(%rsp), %rbp
	movq	%rbx, %rdi
	rep stosl
	movq	%rbp, %rdi
	call	_Z11init_matrixPix
	movl	$16384, %esi
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z12handle_error9cudaError
	movl	$64, %esi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z12handle_error9cudaError
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	movl	$16777217, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 32(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 24(%rsp)
	movq	%rdi, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$256, %edx
	call	_Z41__device_stub__Z18histogram_creationPiS_iPiS_i
.L24:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$64, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	$1048577, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$12, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	16(%rsp), %rdi
	call	_Z40__device_stub__Z20histogram_saturationPiPi
.L25:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$64, %edx
	movq	%rbx, %rdi
	leaq	.LC1(%rip), %rbp
	call	cudaMemcpy@PLT
.L26:
	movl	(%rbx), %edx
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$4, %rbx
	call	__printf_chk@PLT
	jmp	.L26
	.cfi_endproc
.LFE10827:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z20histogram_saturationPi"
.LC3:
	.string	"_Z18histogram_creationPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10857:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20histogram_saturationPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18histogram_creationPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE10857:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <bits/stdc++.h>
#include <hip/hip_runtime.h>

#define N 15
#define M 4096
__global__ void histogram_creation(int *A, int *hist, int no_of_threads) {
	
	int global_x = blockDim.x * blockIdx.x + threadIdx.x;
	__shared__ int local_hist[N+1];

	for(int i = threadIdx.x; i<=N; i = i + (blockDim.x ) ){
		local_hist[i] = 0;
	}
	__syncthreads();
	
	for(int i = global_x; i <= M; i = i + (blockDim.x * no_of_threads)) {
		atomicAdd(&local_hist[A[i]],1);
	}
	__syncthreads();
	
	for(int i = threadIdx.x ; i <= N; i = i + (blockDim.x) ) {
		atomicAdd(&hist[i],local_hist[i]);
		printf("%d histogram_local %d \n",local_hist[i],i);
	}
	__syncthreads();
	
}
__global__ void histogram_saturation(int *hist) {
	int index = threadIdx.x;
	if(hist[index] > 127) {
		hist[index] = 127;
	}
}
void handle_error(hipError_t error) {
	if (error != hipSuccess) {
		printf("Cuda Error. Exiting....\n");
		exit(0);
	}
}

void init_matrix( int A[], long long n) {
	for (long long i = 0; i< n; i++) {
		A[i] = rand() % 4096 + 1;
	}
}

int main() {
	int A[M];
	int hist[N +1];
	
	for(int i=0; i < N + 1; i++) {
		hist[i] = 0;
	}
	init_matrix(A, M);
	int *deviceA;
	int *deviceHist;
	
	size_t size_histogram = (N + 1) * sizeof(int);
	size_t size_array = M * sizeof(int);
	
	handle_error(hipMalloc((void**) &deviceA, size_array));
	handle_error(hipMalloc((void**) &deviceHist, size_histogram));
	
	hipMemcpy(A, deviceA, size_array, hipMemcpyHostToDevice);
	hipMemcpy(hist, deviceHist, size_histogram, hipMemcpyHostToDevice);
	dim3 grid_dim(256,1,1);
	dim3 block_dim(256,1,1);
	
	histogram_creation<<<grid_dim, block_dim>>>(deviceA, deviceHist,256);
	
	hipMemcpy(hist, deviceHist, size_histogram, hipMemcpyDeviceToHost);
	histogram_saturation<<<1,4096>>>(deviceHist);
	
	hipMemcpy(hist, deviceHist, size_histogram, hipMemcpyDeviceToHost);
	
	for(int i=0;i<=4096; i++)
	{
		printf("%d\n", hist[i]);
	}
} 


	.text
	.file	"prog7.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__histogram_creationPiS_i # -- Begin function _Z33__device_stub__histogram_creationPiS_i
	.type	_Z33__device_stub__histogram_creationPiS_i,@function
_Z33__device_stub__histogram_creationPiS_i: # @_Z33__device_stub__histogram_creationPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18histogram_creationPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__histogram_creationPiS_i, .Lfunc_end0-_Z33__device_stub__histogram_creationPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__histogram_saturationPi # -- Begin function _Z35__device_stub__histogram_saturationPi
	.type	_Z35__device_stub__histogram_saturationPi,@function
_Z35__device_stub__histogram_saturationPi: # @_Z35__device_stub__histogram_saturationPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20histogram_saturationPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__histogram_saturationPi, .Lfunc_end1-_Z35__device_stub__histogram_saturationPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z12handle_error10hipError_t    # -- Begin function _Z12handle_error10hipError_t
	.type	_Z12handle_error10hipError_t,@function
_Z12handle_error10hipError_t:           # @_Z12handle_error10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB2_2
# %bb.1:
	retq
.LBB2_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%edi, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z12handle_error10hipError_t, .Lfunc_end2-_Z12handle_error10hipError_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z11init_matrixPix              # -- Begin function _Z11init_matrixPix
	.type	_Z11init_matrixPix,@function
_Z11init_matrixPix:                     # @_Z11init_matrixPix
	.cfi_startproc
# %bb.0:
	testq	%rsi, %rsi
	jle	.LBB3_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	xorl	%r15d, %r15d
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	4095(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-4096, %ecx                    # imm = 0xF000
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%r14,%r15,4)
	incq	%r15
	cmpq	%r15, %rbx
	jne	.LBB3_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB3_4:                                # %._crit_edge
	retq
.Lfunc_end3:
	.size	_Z11init_matrixPix, .Lfunc_end3-_Z11init_matrixPix
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:                                # %.lr.ph.i.preheader
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16464, %rsp                    # imm = 0x4050
	.cfi_def_cfa_offset 16480
	.cfi_offset %rbx, -16
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 64(%rsp)
	movaps	%xmm0, 48(%rsp)
	movaps	%xmm0, 32(%rsp)
	movaps	%xmm0, 16(%rsp)
	xorl	%ebx, %ebx
.LBB4_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	4095(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-4096, %ecx                    # imm = 0xF000
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, 80(%rsp,%rbx,4)
	incq	%rbx
	cmpq	$4096, %rbx                     # imm = 0x1000
	jne	.LBB4_1
# %bb.2:                                # %_Z11init_matrixPix.exit
	leaq	8(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_11
# %bb.3:                                # %_Z12handle_error10hipError_t.exit
	movq	%rsp, %rdi
	movl	$64, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_11
# %bb.4:                                # %_Z12handle_error10hipError_t.exit27
	movabsq	$4294967552, %rbx               # imm = 0x100000100
	movq	8(%rsp), %rsi
	leaq	80(%rsp), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$64, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	callq	_Z33__device_stub__histogram_creationPiS_i
.LBB4_6:
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$64, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	-255(%rbx), %rdi
	addq	$3840, %rbx                     # imm = 0xF00
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	(%rsp), %rdi
	callq	_Z35__device_stub__histogram_saturationPi
.LBB4_8:
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$64, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB4_9:                                # =>This Inner Loop Header: Depth=1
	movl	16(%rsp,%rbx,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$4097, %rbx                     # imm = 0x1001
	jne	.LBB4_9
# %bb.10:
	xorl	%eax, %eax
	addq	$16464, %rsp                    # imm = 0x4050
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB4_11:
	.cfi_def_cfa_offset 16480
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%edi, %edi
	callq	exit
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18histogram_creationPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20histogram_saturationPi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18histogram_creationPiS_i,@object # @_Z18histogram_creationPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z18histogram_creationPiS_i
	.p2align	3, 0x0
_Z18histogram_creationPiS_i:
	.quad	_Z33__device_stub__histogram_creationPiS_i
	.size	_Z18histogram_creationPiS_i, 8

	.type	_Z20histogram_saturationPi,@object # @_Z20histogram_saturationPi
	.globl	_Z20histogram_saturationPi
	.p2align	3, 0x0
_Z20histogram_saturationPi:
	.quad	_Z35__device_stub__histogram_saturationPi
	.size	_Z20histogram_saturationPi, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d\n"
	.size	.L.str.1, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18histogram_creationPiS_i"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z20histogram_saturationPi"
	.size	.L__unnamed_2, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Cuda Error. Exiting...."
	.size	.Lstr, 24

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__histogram_creationPiS_i
	.addrsig_sym _Z35__device_stub__histogram_saturationPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18histogram_creationPiS_i
	.addrsig_sym _Z20histogram_saturationPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18histogram_creationPiS_i ; -- Begin function _Z18histogram_creationPiS_i
	.globl	_Z18histogram_creationPiS_i
	.p2align	8
	.type	_Z18histogram_creationPiS_i,@function
_Z18histogram_creationPiS_i:            ; @_Z18histogram_creationPiS_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	v_mov_b32_e32 v2, v0
	s_add_u32 s8, s0, 24
	s_addc_u32 s9, s1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 16, v2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s18, s2, 0xffff
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v2
	v_mov_b32_e32 v3, v2
	s_lshl_b32 s4, s18, 2
	s_mov_b32 s5, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s18, v3
	ds_store_b32 v0, v1
	v_add_nc_u32_e32 v0, s4, v0
	v_cmp_lt_u32_e64 s2, 15, v3
	s_or_b32 s5, s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow450
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[0:1], null, s15, s18, v[2:3]
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e32 0x1001, v0
	s_cbranch_execz .LBB0_6
; %bb.4:                                ; %.lr.ph56
	s_load_b32 s0, s[0:1], 0x10
	v_mov_b32_e32 v3, 1
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s18, s0
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_nc_u32_e32 v0, s1, v0
	v_add_co_u32 v4, s0, s4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
	v_cmp_lt_i32_e64 s0, 0x1000, v0
	global_load_b32 v1, v[4:5], off
	s_or_b32 s2, s0, s2
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v1, 2, v1
	ds_add_u32 v1, v3
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_5
.LBB0_6:                                ; %Flow447
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s19, vcc_lo
	s_cbranch_execz .LBB0_207
; %bb.7:                                ; %.lr.ph60
	s_load_b64 s[2:3], s[8:9], 0x50
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, 2
	v_mov_b32_e32 v4, 33
	v_mov_b32_e32 v10, 1
	s_mov_b32 s8, 0
	s_mov_b32 s20, 0
.LBB0_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
                                        ;     Child Loop BB0_19 Depth 2
                                        ;     Child Loop BB0_25 Depth 2
                                        ;     Child Loop BB0_34 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;       Child Loop BB0_40 Depth 3
                                        ;       Child Loop BB0_48 Depth 3
                                        ;       Child Loop BB0_56 Depth 3
                                        ;       Child Loop BB0_64 Depth 3
                                        ;       Child Loop BB0_72 Depth 3
                                        ;       Child Loop BB0_80 Depth 3
                                        ;       Child Loop BB0_88 Depth 3
                                        ;       Child Loop BB0_96 Depth 3
                                        ;       Child Loop BB0_104 Depth 3
                                        ;       Child Loop BB0_110 Depth 3
                                        ;       Child Loop BB0_119 Depth 3
                                        ;     Child Loop BB0_127 Depth 2
                                        ;     Child Loop BB0_135 Depth 2
                                        ;     Child Loop BB0_141 Depth 2
                                        ;     Child Loop BB0_150 Depth 2
                                        ;     Child Loop BB0_155 Depth 2
                                        ;     Child Loop BB0_163 Depth 2
                                        ;     Child Loop BB0_169 Depth 2
                                        ;     Child Loop BB0_178 Depth 2
                                        ;     Child Loop BB0_182 Depth 2
                                        ;     Child Loop BB0_190 Depth 2
                                        ;     Child Loop BB0_196 Depth 2
                                        ;     Child Loop BB0_205 Depth 2
	v_dual_mov_b32 v3, v6 :: v_dual_lshlrev_b32 v0, 2, v2
	v_mov_b32_e32 v5, v33
	ds_load_b32 v34, v0
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v[0:1], v34, off
	v_mov_b32_e32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v5
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_14
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	global_load_b64 v[13:14], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v14
	v_and_b32_e32 v0, v0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[13:14]
	s_cbranch_execz .LBB0_13
; %bb.10:                               ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s5, 0
.LBB0_11:                               ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[13:14]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_11
; %bb.12:                               ; %Flow439
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_13:                               ; %Flow441
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_14:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[11:14], v6, s[2:3]
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[4:5], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_16:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v16, s11
	v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v14, s9
	v_mov_b32_e32 v15, s10
	v_mov_b32_e32 v13, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[4:7], off
	global_store_b128 v[0:1], v[13:16], off offset:16
	global_store_b128 v[0:1], v[13:16], off offset:32
	global_store_b128 v[0:1], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_24
; %bb.17:                               ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s14, s14, s11
	v_add_co_u32 v7, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[7:8], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_20
; %bb.18:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s11, 0
.LBB0_19:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
	s_sleep 1
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_19
.LBB0_20:                               ; %Flow437
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_8 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_22:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_24:                               ; %Flow438
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s12, s12, s1
	v_add_co_u32 v5, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_25:                               ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_25 Depth=2
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_27:                               ;   in Loop: Header=BB0_25 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_25 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_30
.LBB0_29:                               ;   in Loop: Header=BB0_25 Depth=2
	s_mov_b32 s1, -1
.LBB0_30:                               ; %Flow432
                                        ;   in Loop: Header=BB0_25 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_25
; %bb.31:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b64 v[11:12], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_35
; %bb.32:                               ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v5, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_cndmask_b32_e32 v13, v13, v5, vcc_lo
	v_cndmask_b32_e32 v14, v14, v17, vcc_lo
	v_and_b32_e32 v0, v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, v0
	v_mov_b32_e32 v15, v7
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v16, v1, vcc_lo
	v_mov_b32_e32 v16, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_35
; %bb.33:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s0, 0
.LBB0_34:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[15:16]
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_34
.LBB0_35:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB0_122
; %bb.36:                               ;   in Loop: Header=BB0_8 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v14, v12 :: v_dual_and_b32 v35, 2, v11
	v_and_b32_e32 v13, -3, v11
	s_mov_b64 s[10:11], 24
.LBB0_37:                               ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_40 Depth 3
                                        ;       Child Loop BB0_48 Depth 3
                                        ;       Child Loop BB0_56 Depth 3
                                        ;       Child Loop BB0_64 Depth 3
                                        ;       Child Loop BB0_72 Depth 3
                                        ;       Child Loop BB0_80 Depth 3
                                        ;       Child Loop BB0_88 Depth 3
                                        ;       Child Loop BB0_96 Depth 3
                                        ;       Child Loop BB0_104 Depth 3
                                        ;       Child Loop BB0_110 Depth 3
                                        ;       Child Loop BB0_119 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[10:11], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s12, s10, 56
	s_cselect_b32 s13, s11, 0
	s_cmp_gt_u32 s12, 7
	s_cbranch_scc1 .LBB0_42
; %bb.38:                               ;   in Loop: Header=BB0_37 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc1 .LBB0_41
; %bb.39:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_lshl_b64 s[0:1], s[12:13], 3
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[4:5]
.LBB0_40:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v0, v6, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s14, v[5:6]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s0, s14
	v_or_b32_e32 v15, v0, v15
	v_or_b32_e32 v16, v1, v16
	s_cbranch_scc1 .LBB0_40
.LBB0_41:                               ; %Flow408
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_43
.LBB0_42:                               ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr9
.LBB0_43:                               ; %Flow410
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB0_45
; %bb.44:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[15:16], v6, s[4:5]
	s_add_i32 s9, s12, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB0_45:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_50
; %bb.46:                               ;   in Loop: Header=BB0_37 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_49
; %bb.47:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_48:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v6, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s14, v[5:6]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s9, s16
	v_or_b32_e32 v17, v0, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v1, v18
	s_cbranch_scc1 .LBB0_48
.LBB0_49:                               ; %Flow403
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s21, 0
	s_branch .LBB0_51
.LBB0_50:                               ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr21
.LBB0_51:                               ; %Flow405
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_53
; %bb.52:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[17:18], v6, s[0:1]
	s_add_i32 s21, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_53:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB0_58
; %bb.54:                               ;   in Loop: Header=BB0_37 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB0_57
; %bb.55:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_56:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v6, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s14, v[5:6]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v19, v0, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v1, v20
	s_cbranch_scc1 .LBB0_56
.LBB0_57:                               ; %Flow398
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_59
.LBB0_58:                               ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr9
.LBB0_59:                               ; %Flow400
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_61
; %bb.60:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[19:20], v6, s[0:1]
	s_add_i32 s9, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_61:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_66
; %bb.62:                               ;   in Loop: Header=BB0_37 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_65
; %bb.63:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_64:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v6, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s14, v[5:6]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s9, s16
	v_or_b32_e32 v21, v0, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v1, v22
	s_cbranch_scc1 .LBB0_64
.LBB0_65:                               ; %Flow393
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s21, 0
	s_branch .LBB0_67
.LBB0_66:                               ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr21
.LBB0_67:                               ; %Flow395
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_69
; %bb.68:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[21:22], v6, s[0:1]
	s_add_i32 s21, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_69:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB0_74
; %bb.70:                               ;   in Loop: Header=BB0_37 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB0_73
; %bb.71:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_72:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v6, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s14, v[5:6]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v23, v0, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v1, v24
	s_cbranch_scc1 .LBB0_72
.LBB0_73:                               ; %Flow388
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_75
.LBB0_74:                               ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr9
.LBB0_75:                               ; %Flow390
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[23:24], v6, s[0:1]
	s_add_i32 s9, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_77:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_82
; %bb.78:                               ;   in Loop: Header=BB0_37 Depth=2
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_81
; %bb.79:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_80:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v0, v6, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s14, v[5:6]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s9, s16
	v_or_b32_e32 v25, v0, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v26, v1, v26
	s_cbranch_scc1 .LBB0_80
.LBB0_81:                               ; %Flow383
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s21, 0
	s_branch .LBB0_83
.LBB0_82:                               ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr21
.LBB0_83:                               ; %Flow385
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_85
; %bb.84:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[25:26], v6, s[0:1]
	s_add_i32 s21, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_85:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB0_90
; %bb.86:                               ;   in Loop: Header=BB0_37 Depth=2
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB0_89
; %bb.87:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[0:1]
.LBB0_88:                               ; %.preheader.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v0, v6, s[16:17]
	s_add_i32 s21, s21, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s14, v[5:6]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s21, 0
	v_or_b32_e32 v27, v0, v27
	v_or_b32_e32 v28, v1, v28
	s_cbranch_scc1 .LBB0_88
.LBB0_89:                               ; %Flow378
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s9, 0
	s_branch .LBB0_91
.LBB0_90:                               ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s9, -1
.LBB0_91:                               ; %Flow380
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_93
; %bb.92:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[27:28], v6, s[0:1]
.LBB0_93:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	v_dual_mov_b32 v5, v33 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_99
; %bb.94:                               ;   in Loop: Header=BB0_37 Depth=2
	global_load_b64 v[31:32], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v32
	v_and_b32_e32 v0, v0, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v29, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v29, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[29:30], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[29:32], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[31:32]
	s_cbranch_execz .LBB0_98
; %bb.95:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s14, 0
.LBB0_96:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[29:30], v6, s[2:3]
	v_dual_mov_b32 v32, v1 :: v_dual_mov_b32 v31, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v31
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[29:30]
	v_and_b32_e32 v29, v8, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v29, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[29:30], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[29:32], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[31:32]
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_96
; %bb.97:                               ; %Flow373
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_98:                               ; %Flow375
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_99:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[29:32], v6, s[2:3]
	v_readfirstlane_b32 s14, v0
	v_readfirstlane_b32 s15, v1
	s_mov_b32 s22, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v7
	v_readfirstlane_b32 s17, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[14:15], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s9, s16, 24
	s_mul_i32 s21, s16, 24
	s_and_saveexec_b32 s23, s0
	s_cbranch_execz .LBB0_101
; %bb.100:                              ;   in Loop: Header=BB0_37 Depth=2
	v_dual_mov_b32 v7, s22 :: v_dual_mov_b32 v8, v6
	s_add_i32 s22, s9, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v29, s21
	v_add_co_ci_u32_e32 v1, vcc_lo, s22, v30, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_101:                              ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	v_cmp_gt_u64_e64 vcc_lo, s[10:11], 56
	v_or_b32_e32 v0, 0, v14
	v_or_b32_e32 v1, v13, v35
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s22, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s22, s22, 28
	v_dual_cndmask_b32 v14, v0, v14 :: v_dual_cndmask_b32 v7, v1, v13
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v31, s16
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v32, vcc_lo
	s_and_b32 s22, s22, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v5, v0
	v_and_or_b32 v13, 0xffffff1f, v7, s22
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[21:24], off offset:32
	global_store_b128 v[0:1], v[25:28], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_109
; %bb.102:                              ;   in Loop: Header=BB0_37 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s14 :: v_dual_mov_b32 v16, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v7
	v_readfirstlane_b32 s23, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[14:15]
	s_mul_i32 s17, s23, 24
	s_mul_hi_u32 s23, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s23, s23, s17
	v_add_co_u32 v7, vcc_lo, v29, s22
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v30, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[7:8], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_105
; %bb.103:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s22, 0
.LBB0_104:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v13, s14 :: v_dual_mov_b32 v14, s15
	s_sleep 1
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_104
.LBB0_105:                              ; %Flow371
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s22, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v5, s22, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_37 Depth=2
	s_bcnt1_i32_b32 s22, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s22
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_107:                              ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_37 Depth=2
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[5:6], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_109:                              ; %Flow372
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s9, s9, s1
	v_add_co_u32 v5, vcc_lo, v29, s21
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_110:                              ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_112
; %bb.111:                              ;   in Loop: Header=BB0_110 Depth=3
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_112:                              ;   in Loop: Header=BB0_110 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_114
; %bb.113:                              ;   in Loop: Header=BB0_110 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_115
.LBB0_114:                              ;   in Loop: Header=BB0_110 Depth=3
	s_mov_b32 s1, -1
.LBB0_115:                              ; %Flow366
                                        ;   in Loop: Header=BB0_110 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_110
; %bb.116:                              ;   in Loop: Header=BB0_37 Depth=2
	global_load_b128 v[13:16], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_120
; %bb.117:                              ;   in Loop: Header=BB0_37 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[17:18], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v5, s14
	v_add_co_ci_u32_e32 v16, vcc_lo, s15, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v19 :: v_dual_cndmask_b32 v15, v15, v5
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v17, v0
	v_mov_b32_e32 v17, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v18, v1, vcc_lo
	v_mov_b32_e32 v18, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_120
; %bb.118:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_mov_b32 s0, 0
.LBB0_119:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[17:18]
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_119
.LBB0_120:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_37 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s10, s10, s12
	s_subb_u32 s11, s11, s13
	s_add_u32 s4, s4, s12
	s_addc_u32 s5, s5, s13
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_37
; %bb.121:                              ; %Flow411
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_123
.LBB0_122:                              ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_123:                              ; %Flow426
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_152
; %bb.124:                              ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v5, v33 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_130
; %bb.125:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b64 v[15:16], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v16
	v_and_b32_e32 v0, v0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[15:16]
	s_cbranch_execz .LBB0_129
; %bb.126:                              ; %.preheader3.i.i.i24.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s5, 0
.LBB0_127:                              ; %.preheader3.i.i.i24
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[13:14], v6, s[2:3]
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v15, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[13:14]
	v_and_b32_e32 v13, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[15:16]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_127
; %bb.128:                              ; %Flow423
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_129:                              ; %Flow425
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_130:                              ; %.loopexit4.i.i.i19
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[15:18], v6, s[2:3]
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[4:5], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_132
; %bb.131:                              ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v16, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_132:                              ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v17, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v18, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v11, 0xffffff1f, v11, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v13, v6 :: v_dual_mov_b32 v20, s11
	v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v19, s10
	v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v17, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[11:14], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[17:20], off offset:32
	global_store_b128 v[0:1], v[17:20], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_140
; %bb.133:                              ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x1
	global_load_b64 v[19:20], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v17, s4 :: v_dual_mov_b32 v18, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s14, s14, s11
	v_add_co_u32 v7, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v16, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[7:8], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[17:20], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_136
; %bb.134:                              ; %.preheader1.i.i.i22.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s11, 0
.LBB0_135:                              ; %.preheader1.i.i.i22
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_135
.LBB0_136:                              ; %Flow421
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_8 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_138:                              ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_140
; %bb.139:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_140:                              ; %Flow422
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s12, s12, s1
	v_add_co_u32 v5, vcc_lo, v15, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_141:                              ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_143
; %bb.142:                              ;   in Loop: Header=BB0_141 Depth=2
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_143:                              ;   in Loop: Header=BB0_141 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_145
; %bb.144:                              ;   in Loop: Header=BB0_141 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_146
.LBB0_145:                              ;   in Loop: Header=BB0_141 Depth=2
	s_mov_b32 s1, -1
.LBB0_146:                              ; %Flow416
                                        ;   in Loop: Header=BB0_141 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_141
; %bb.147:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b128 v[13:16], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_151
; %bb.148:                              ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[11:12], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v18, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v5, s4
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_mov_b32 v17, v7
	v_cndmask_b32_e32 v15, v15, v5, vcc_lo
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v11, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_151
; %bb.149:                              ; %.preheader.i.i.i21.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s0, 0
.LBB0_150:                              ; %.preheader.i.i.i21
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[17:18]
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_150
.LBB0_151:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_152:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v5, v33 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_158
; %bb.153:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b64 v[17:18], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v18
	v_and_b32_e32 v0, v0, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[17:18]
	s_cbranch_execz .LBB0_157
; %bb.154:                              ; %.preheader3.i.i.i31.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s5, 0
.LBB0_155:                              ; %.preheader3.i.i.i31
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v17, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v17
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[17:18]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_155
; %bb.156:                              ; %Flow359
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_157:                              ; %Flow361
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_158:                              ; %.loopexit4.i.i.i25
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[17:20], v6, s[2:3]
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[4:5], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_160
; %bb.159:                              ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v17, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v18, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_160:                              ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v19, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v20, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v13, 0xffffff1f, v13, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v15, v34 :: v_dual_mov_b32 v22, s11
	v_dual_mov_b32 v16, v6 :: v_dual_mov_b32 v21, s10
	v_dual_mov_b32 v20, s9 :: v_dual_mov_b32 v19, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[19:22], off offset:16
	global_store_b128 v[0:1], v[19:22], off offset:32
	global_store_b128 v[0:1], v[19:22], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_168
; %bb.161:                              ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s14, s14, s11
	v_add_co_u32 v7, vcc_lo, v17, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v18, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[15:16]
	s_cbranch_execz .LBB0_164
; %bb.162:                              ; %.preheader1.i.i.i29.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s11, 0
.LBB0_163:                              ; %.preheader1.i.i.i29
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_163
.LBB0_164:                              ; %Flow357
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_166
; %bb.165:                              ;   in Loop: Header=BB0_8 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_166:                              ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_168
; %bb.167:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_168:                              ; %Flow358
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s12, s12, s1
	v_add_co_u32 v5, vcc_lo, v17, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_169:                              ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_171
; %bb.170:                              ;   in Loop: Header=BB0_169 Depth=2
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_171:                              ;   in Loop: Header=BB0_169 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_173
; %bb.172:                              ;   in Loop: Header=BB0_169 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_174
.LBB0_173:                              ;   in Loop: Header=BB0_169 Depth=2
	s_mov_b32 s1, -1
.LBB0_174:                              ; %Flow352
                                        ;   in Loop: Header=BB0_169 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_169
; %bb.175:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_179
; %bb.176:                              ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x2
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[15:16], v6, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v7, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v5, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v5, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v12, v8
	v_mul_hi_u32 v8, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v5, v8, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v13, v7
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v8, vcc_lo, v14, v5, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_179
; %bb.177:                              ; %.preheader.i.i.i28.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s0, 0
.LBB0_178:                              ; %.preheader.i.i.i28
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_178
.LBB0_179:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, v33
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v5
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_185
; %bb.180:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b64 v[13:14], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v14
	v_and_b32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, 24
	v_mul_hi_u32 v15, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v15, v8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	global_load_b64 v[11:12], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[13:14]
	s_cbranch_execz .LBB0_184
; %bb.181:                              ; %.preheader3.i.i.i38.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s5, 0
.LBB0_182:                              ; %.preheader3.i.i.i38
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v6, s[2:3] offset:40
	global_load_b64 v[15:16], v6, s[2:3]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[15:16]
	v_and_b32_e32 v15, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v15, 24, v[8:9]
	v_mov_b32_e32 v8, v11
	global_load_b64 v[11:12], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_182
; %bb.183:                              ; %Flow345
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_184:                              ; %Flow347
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_185:                              ; %.loopexit4.i.i.i32
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[2:3] offset:40
	global_load_b128 v[11:14], v6, s[2:3]
	v_readfirstlane_b32 s4, v7
	v_readfirstlane_b32 s5, v8
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v15
	v_readfirstlane_b32 s11, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[4:5], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_187
; %bb.186:                              ;   in Loop: Header=BB0_8 Depth=1
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[15:16], v[7:10], off offset:8
.LBB0_187:                              ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v13, v7
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v8, vcc_lo, v14, v8, vcc_lo
	v_dual_mov_b32 v16, s11 :: v_dual_mov_b32 v15, s10
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v13, s8
	s_clause 0x3
	global_store_b128 v[7:8], v[0:3], off
	global_store_b128 v[7:8], v[13:16], off offset:16
	global_store_b128 v[7:8], v[13:16], off offset:32
	global_store_b128 v[7:8], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_195
; %bb.188:                              ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s14, s14, s11
	v_add_co_u32 v0, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s14, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_191
; %bb.189:                              ; %.preheader1.i.i.i36.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s11, 0
.LBB0_190:                              ; %.preheader1.i.i.i36
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[15:16]
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_190
.LBB0_191:                              ; %Flow343
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[0:1], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v3, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_193
; %bb.192:                              ;   in Loop: Header=BB0_8 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[5:6], off offset:8
.LBB0_193:                              ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v5, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_195:                              ; %Flow344
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s12, s12, s1
	v_add_co_u32 v0, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_196:                              ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_198
; %bb.197:                              ;   in Loop: Header=BB0_196 Depth=2
	global_load_b32 v3, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_198:                              ;   in Loop: Header=BB0_196 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_200
; %bb.199:                              ;   in Loop: Header=BB0_196 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_201
.LBB0_200:                              ;   in Loop: Header=BB0_196 Depth=2
	s_mov_b32 s1, -1
.LBB0_201:                              ; %Flow338
                                        ;   in Loop: Header=BB0_196 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_196
; %bb.202:                              ;   in Loop: Header=BB0_8 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_206
; %bb.203:                              ;   in Loop: Header=BB0_8 Depth=1
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v3, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v5 :: v_dual_cndmask_b32 v11, v11, v3
	v_and_b32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v11, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v3, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v13, v0
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_206
; %bb.204:                              ; %.preheader.i.i.i35.preheader
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_mov_b32 s0, 0
.LBB0_205:                              ; %.preheader.i.i.i35
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_205
.LBB0_206:                              ; %__ockl_printf_append_args.exit39
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v2, s18, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_u32_e32 vcc_lo, 15, v2
	s_or_b32 s20, vcc_lo, s20
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_8
.LBB0_207:                              ; %Flow444
	s_or_b32 exec_lo, exec_lo, s19
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18histogram_creationPiS_i
		.amdhsa_group_segment_fixed_size 64
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18histogram_creationPiS_i, .Lfunc_end0-_Z18histogram_creationPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8280
; NumSgprs: 26
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 64 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20histogram_saturationPi ; -- Begin function _Z20histogram_saturationPi
	.globl	_Z20histogram_saturationPi
	.p2align	8
	.type	_Z20histogram_saturationPi,@function
_Z20histogram_saturationPi:             ; @_Z20histogram_saturationPi
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b32 v1, v0, s[0:1]
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0x7f, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_add_co_u32 v0, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s1, 0, s0
	v_mov_b32_e32 v2, 0x7f
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20histogram_saturationPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 3
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z20histogram_saturationPi, .Lfunc_end1-_Z20histogram_saturationPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 92
; NumSgprs: 3
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 3
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d histogram_local %d \n"
	.size	.str, 24

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         104
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 64
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18histogram_creationPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z18histogram_creationPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20histogram_saturationPi
    .private_segment_fixed_size: 0
    .sgpr_count:     3
    .sgpr_spill_count: 0
    .symbol:         _Z20histogram_saturationPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
