/*
 ===============================================================================
 Name        : simulatorutils.cu
 Author      : Mridul & Srinidhi
 Version     :
 Copyright   : Copyleft
 Description : Parallel implementation of Rigid Body Dynamics on GPU using CUDA
 ===============================================================================
 */

#include <stdio.h>

#define EPSILON 1


__device__ int checkIntersection(double x1,double x2,double y1,double y2,double z1,double z2,double a1,double a2,double b1,double b2,double c1, double c2)
{
    if((a1 < (x2 + EPSILON) && x1 < (a2 + EPSILON)) && (b1 < (y2 + EPSILON) && y1 < (b2 + EPSILON)) &&
        (c1 < (z2 + EPSILON) && z1 < (c2 + EPSILON)))
        return 1;
    return 0;
}

__global__ void checkCollision(double *d_x, double *d_y, double *d_z, int *d_mat, int n)
{
    int row = threadIdx.y ;
    int col = threadIdx.x ;
    int idx = row*n + col;

    for (long int j = 0; j < n; ++j)
    {
        if(idx != j && checkIntersection(d_x[2*idx], d_x[2*idx+1], d_y[2*idx], d_y[2*idx+1], d_z[2*idx], d_z[2*idx+1], d_x[2*j], d_x[2*j+1], d_y[2*j], d_y[2*j+1], d_z[2*j], d_z[2*j+1]))
            d_mat[idx*n+j] = 1;
        else
            d_mat[idx*n+j] = 0;

        __syncthreads();
    }
}

__host__ void collisionWrapper(double *x, double *y, double *z, int *mat, int n)
{
    double *d_x, *d_y, *d_z;
    int *d_mat;

    cudaMalloc(&d_x, n*sizeof(double));
    cudaMalloc(&d_y, n*sizeof(double));
    cudaMalloc(&d_z, n*sizeof(double));
    cudaMalloc(&d_mat, n*n*sizeof(int));

    cudaMemcpy(d_x, x, n*sizeof(double), cudaMemcpyHostToDevice);
    cudaMemcpy(d_y, y, n*sizeof(double), cudaMemcpyHostToDevice);
    cudaMemcpy(d_z, z, n*sizeof(double), cudaMemcpyHostToDevice);

    dim3 dimGrid(n,1);
    dim3 dimBlock(n,1);

    checkCollision <<< dimGrid, dimBlock >>> (d_x, d_y, d_z, d_mat, n);

    cudaMemcpy(mat, d_mat, n*n*sizeof(int), cudaMemcpyDeviceToHost);

}

	.file	"tmpxft_0025bd56_00000000-6_simulatorutils.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z17checkIntersectiondddddddddddd
	.type	_Z17checkIntersectiondddddddddddd, @function
_Z17checkIntersectiondddddddddddd:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z17checkIntersectiondddddddddddd, .-_Z17checkIntersectiondddddddddddd
	.globl	_Z41__device_stub__Z14checkCollisionPdS_S_PiiPdS_S_Pii
	.type	_Z41__device_stub__Z14checkCollisionPdS_S_PiiPdS_S_Pii, @function
_Z41__device_stub__Z14checkCollisionPdS_S_PiiPdS_S_Pii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z14checkCollisionPdS_S_Pii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L4:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z41__device_stub__Z14checkCollisionPdS_S_PiiPdS_S_Pii, .-_Z41__device_stub__Z14checkCollisionPdS_S_PiiPdS_S_Pii
	.globl	_Z14checkCollisionPdS_S_Pii
	.type	_Z14checkCollisionPdS_S_Pii, @function
_Z14checkCollisionPdS_S_Pii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z14checkCollisionPdS_S_PiiPdS_S_Pii
	.cfi_endproc
.LFE2054:
	.size	_Z14checkCollisionPdS_S_Pii, .-_Z14checkCollisionPdS_S_Pii
	.globl	_Z16collisionWrapperPdS_S_Pii
	.type	_Z16collisionWrapperPdS_S_Pii, @function
_Z16collisionWrapperPdS_S_Pii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movslq	%r8d, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rbp, %rbx
	salq	$3, %rbp
	movq	%rbp, %rsi
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	%ebx, %eax
	leaq	40(%rsp), %rdi
	imull	%ebx, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%ebx, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	%ebx, 60(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movq	%rax, 64(%rsp)
	movl	56(%rsp), %esi
	movl	68(%rsp), %ecx
	movq	60(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	%ebx, %r8d
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z41__device_stub__Z14checkCollisionPdS_S_PiiPdS_S_Pii
.L11:
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z16collisionWrapperPdS_S_Pii, .-_Z16collisionWrapperPdS_S_Pii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14checkCollisionPdS_S_Pii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14checkCollisionPdS_S_Pii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 ===============================================================================
 Name        : simulatorutils.cu
 Author      : Mridul & Srinidhi
 Version     :
 Copyright   : Copyleft
 Description : Parallel implementation of Rigid Body Dynamics on GPU using CUDA
 ===============================================================================
 */


#include <hip/hip_runtime.h>
#include <stdio.h>

#define EPSILON 1


__device__ int checkIntersection(double x1,double x2,double y1,double y2,double z1,double z2,double a1,double a2,double b1,double b2,double c1, double c2)
{
    if((a1 < (x2 + EPSILON) && x1 < (a2 + EPSILON)) && (b1 < (y2 + EPSILON) && y1 < (b2 + EPSILON)) &&
        (c1 < (z2 + EPSILON) && z1 < (c2 + EPSILON)))
        return 1;
    return 0;
}

__global__ void checkCollision(double *d_x, double *d_y, double *d_z, int *d_mat, int n)
{
    int row = threadIdx.y ;
    int col = threadIdx.x ;
    int idx = row*n + col;

    for (long int j = 0; j < n; ++j)
    {
        if(idx != j && checkIntersection(d_x[2*idx], d_x[2*idx+1], d_y[2*idx], d_y[2*idx+1], d_z[2*idx], d_z[2*idx+1], d_x[2*j], d_x[2*j+1], d_y[2*j], d_y[2*j+1], d_z[2*j], d_z[2*j+1]))
            d_mat[idx*n+j] = 1;
        else
            d_mat[idx*n+j] = 0;

        __syncthreads();
    }
}

__host__ void collisionWrapper(double *x, double *y, double *z, int *mat, int n)
{
    double *d_x, *d_y, *d_z;
    int *d_mat;

    hipMalloc(&d_x, n*sizeof(double));
    hipMalloc(&d_y, n*sizeof(double));
    hipMalloc(&d_z, n*sizeof(double));
    hipMalloc(&d_mat, n*n*sizeof(int));

    hipMemcpy(d_x, x, n*sizeof(double), hipMemcpyHostToDevice);
    hipMemcpy(d_y, y, n*sizeof(double), hipMemcpyHostToDevice);
    hipMemcpy(d_z, z, n*sizeof(double), hipMemcpyHostToDevice);

    dim3 dimGrid(n,1);
    dim3 dimBlock(n,1);

    checkCollision <<< dimGrid, dimBlock >>> (d_x, d_y, d_z, d_mat, n);

    hipMemcpy(mat, d_mat, n*n*sizeof(int), hipMemcpyDeviceToHost);

}

	.text
	.file	"simulatorutils.hip"
	.globl	_Z29__device_stub__checkCollisionPdS_S_Pii # -- Begin function _Z29__device_stub__checkCollisionPdS_S_Pii
	.type	_Z29__device_stub__checkCollisionPdS_S_Pii,@function
_Z29__device_stub__checkCollisionPdS_S_Pii: # @_Z29__device_stub__checkCollisionPdS_S_Pii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14checkCollisionPdS_S_Pii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__checkCollisionPdS_S_Pii, .Lfunc_end0-_Z29__device_stub__checkCollisionPdS_S_Pii
	.cfi_endproc
                                        # -- End function
	.globl	_Z16collisionWrapperPdS_S_Pii   # -- Begin function _Z16collisionWrapperPdS_S_Pii
	.type	_Z16collisionWrapperPdS_S_Pii,@function
_Z16collisionWrapperPdS_S_Pii:          # @_Z16collisionWrapperPdS_S_Pii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, 40(%rsp)                  # 8-byte Spill
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rsi, %r13
	movq	%rdi, %rbx
	movl	%r8d, 4(%rsp)                   # 4-byte Spill
	movslq	%r8d, %r15
	leaq	(,%r15,8), %r12
	leaq	48(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%r15d, %r14d
	imull	%r14d, %r14d
	shlq	$2, %r14
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r15d, %edi
	btsq	$32, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	48(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	4(%rsp), %r8d                   # 4-byte Reload
	callq	_Z29__device_stub__checkCollisionPdS_S_Pii
.LBB1_2:
	movq	8(%rsp), %rsi
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z16collisionWrapperPdS_S_Pii, .Lfunc_end1-_Z16collisionWrapperPdS_S_Pii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14checkCollisionPdS_S_Pii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14checkCollisionPdS_S_Pii,@object # @_Z14checkCollisionPdS_S_Pii
	.section	.rodata,"a",@progbits
	.globl	_Z14checkCollisionPdS_S_Pii
	.p2align	3, 0x0
_Z14checkCollisionPdS_S_Pii:
	.quad	_Z29__device_stub__checkCollisionPdS_S_Pii
	.size	_Z14checkCollisionPdS_S_Pii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14checkCollisionPdS_S_Pii"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__checkCollisionPdS_S_Pii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14checkCollisionPdS_S_Pii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14checkCollisionPdS_S_Pii ; -- Begin function _Z14checkCollisionPdS_S_Pii
	.globl	_Z14checkCollisionPdS_S_Pii
	.p2align	8
	.type	_Z14checkCollisionPdS_S_Pii,@function
_Z14checkCollisionPdS_S_Pii:            ; @_Z14checkCollisionPdS_S_Pii
; %bb.0:
	s_load_b32 s8, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s8, 1
	s_cbranch_scc1 .LBB0_7
; %bb.1:                                ; %.lr.ph
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_load_b256 s[0:7], s[0:1], 0x0
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s8, v[2:3]
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v3, v1 :: v_dual_lshlrev_b32 v2, 1, v0
	v_mul_lo_u32 v4, v0, s8
	v_mov_b32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v8
	s_add_u32 s6, s0, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_addc_u32 s7, s1, 0
	s_add_u32 s10, s4, 8
	s_addc_u32 s5, s5, 0
	s_add_u32 s11, s2, 8
	s_addc_u32 s12, s3, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_cmp_eq_u64_e64 s13, 0, v[0:1]
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $sgpr0
	v_cmpx_ne_u64_e32 0, v[0:1]
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[10:13], v[2:3], off
	global_load_b128 v[14:17], v[4:5], off
	global_load_b128 v[18:21], v[6:7], off
	s_add_u32 s0, s6, -8
	s_addc_u32 s1, s7, -1
	s_add_u32 s16, s11, -8
	s_load_b128 s[0:3], s[0:1], 0x0
	s_addc_u32 s17, s12, -1
	s_add_u32 s20, s10, -8
	s_load_b128 s[16:19], s[16:17], 0x0
	s_addc_u32 s21, s5, -1
	s_load_b128 s[20:23], s[20:21], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[22:23], s[2:3], 1.0
	v_add_f64 v[24:25], s[18:19], 1.0
	v_add_f64 v[26:27], s[22:23], 1.0
	s_waitcnt vmcnt(2)
	v_add_f64 v[12:13], v[12:13], 1.0
	s_waitcnt vmcnt(1)
	v_add_f64 v[16:17], v[16:17], 1.0
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[20:21], 1.0
	v_cmp_ngt_f64_e64 s2, v[24:25], v[14:15]
	v_cmp_ngt_f64_e64 s4, v[26:27], v[18:19]
	v_cmp_nlt_f64_e32 vcc_lo, s[0:1], v[12:13]
	v_cmp_ngt_f64_e64 s0, v[22:23], v[10:11]
	v_cmp_nlt_f64_e64 s1, s[16:17], v[16:17]
	v_cmp_nlt_f64_e64 s3, s[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3)
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_and_not1_b32 s1, s13, exec_lo
	s_or_b32 s0, s0, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s4
	s_and_b32 s2, s0, exec_lo
	s_mov_b32 s0, 1
	s_or_b32 s13, s1, s2
.LBB0_4:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_mov_b32_e32 v10, s0
	s_and_saveexec_b32 s0, s13
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v10, 0
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	global_store_b32 v[8:9], v10, off
	v_add_co_u32 v8, vcc_lo, v8, 4
	s_add_u32 s8, s8, -1
	s_addc_u32 s9, s9, -1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_add_u32 s6, s6, 16
	v_add_co_u32 v0, vcc_lo, v0, -1
	s_addc_u32 s7, s7, 0
	s_add_u32 s10, s10, 16
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	s_addc_u32 s5, s5, 0
	s_add_u32 s11, s11, 16
	s_addc_u32 s12, s12, 0
	s_cmp_eq_u64 s[8:9], 0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_7:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14checkCollisionPdS_S_Pii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14checkCollisionPdS_S_Pii, .Lfunc_end0-_Z14checkCollisionPdS_S_Pii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 548
; NumSgprs: 26
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14checkCollisionPdS_S_Pii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z14checkCollisionPdS_S_Pii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
