#define t_max 1
#define t 1
/*
(u[0][0][0][1][0]=((((u[1][0][0][0][0]+(u[-1][0][0][0][0]+u[0][1][0][0][0]))+(u[0][-1][0][0][0]+(u[0][0][1][0][0]+u[0][0][-1][0][0])))*0.25)-u[0][0][0][0][0]))

*/
__global__ void laplacian(float *  *  u_0_1_out, float *  u_0_0, float *  u_0_1, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
	//float *  const u__u_0[16] =  { u_0_0, u_0_1 } ;
	int _idx0;
	int _idx1;
	int _idx2;
	int _idx3;
	int _idx4;
	int _idx5;
	int _idx6;
	int chunk_idx_x;
	int chunk_idx_x_max;
	int chunk_idx_y;
	int chunk_idx_y_max;
	int chunk_idx_z;
	int chunk_idx_z_max;
	int idx_1_2;
	int size_1_1;
	int size_1_2;
	//int t;
	int thd_idx_x;
	int thd_idx_y;
	int thd_idx_z;
	int thdblks_idx_x;
	int thdblks_idx_x_max;
	int thdblks_idx_y;
	int thdblks_idx_y_max;
	int thdblks_idx_z;
	int thdblks_idx_z_max;
	int tmp;
	/*
	Initializations
	*/
	size_1_1=(y_max/blockDim.y);
	size_1_2=(z_max/blockDim.z);
	idx_1_2=(blockIdx.y/size_1_2);
	tmp=(blockIdx.y-(idx_1_2*size_1_2));
	chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
	chunk_idx_x_max=(chunk_idx_x+c);
	chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
	chunk_idx_y_max=(chunk_idx_y+1);
	chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
	chunk_idx_z_max=(chunk_idx_z+1);
	thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
	thdblks_idx_x_max=(thdblks_idx_x+tbx);
	thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
	thdblks_idx_y_max=(thdblks_idx_y+tby);
	thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
	thdblks_idx_z_max=(thdblks_idx_z+tbz);
	/*
	Implementation
	*/
	/*
	for t = 1..t_max by 1 parallel 1 <level 0> schedule  { ... }
	*/
	//for (t=1; t<=t_max; t+=1)
	{
		/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
		/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
		/*
		for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
		*/
		{
			/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
			thd_idx_z=chunk_idx_z;
			thd_idx_y=chunk_idx_y;
			for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
			{
				/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
				/*
				u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
				*/
				/* _idx0 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+2) */
				_idx0=((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+2);
				/* _idx1 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t)) */
				_idx1=(_idx0-2);
				/* _idx2 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+2)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(4*t))+1) */
				_idx2=(((_idx1+x_max)+(2*t))+1);
				/* _idx3 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+1) */
				_idx3=(((_idx1-x_max)-(2*t))+1);
				/* _idx4 = ((((((((((((thd_idx_z+2)*x_max)+((2*t)*thd_idx_z))+(4*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(4*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(8*(t*t)))+(2*t))+1) */
				_idx4=((((_idx1+((x_max+(2*t))*y_max))+((2*t)*x_max))+(4*(t*t)))+1);
				/* _idx5 = (((((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(2*t))+1) */
				_idx5=((((_idx1+((( - x_max)-(2*t))*y_max))-((2*t)*x_max))-(4*(t*t)))+1);
				/* _idx6 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+1) */
				_idx6=(_idx1+1);
				u_0_1[_idx6]=((((u_0_0[_idx0]+(u_0_0[_idx1]+u_0_0[_idx2]))+(u_0_0[_idx3]+(u_0_0[_idx4]+u_0_0[_idx5])))*0.25)-u_0_0[_idx6]);
			}
		}
	}
}

__global__ void initialize(float *  u_0_0, float *  u_0_1, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
	float *  const u__u_0[16] =  { u_0_0, u_0_1 } ;
	int _idx0;
	int _idx1;
	int _idx2;
	int _idx3;
	int _idx4;
	int _idx5;
	int _idx6;
	int chunk_idx_x;
	int chunk_idx_x_max;
	int chunk_idx_y;
	int chunk_idx_y_max;
	int chunk_idx_z;
	int chunk_idx_z_max;
	int idx_1_2;
	int size_1_1;
	int size_1_2;
	//int t;
	int thd_idx_x;
	int thd_idx_y;
	int thd_idx_z;
	int thdblks_idx_x;
	int thdblks_idx_x_max;
	int thdblks_idx_y;
	int thdblks_idx_y_max;
	int thdblks_idx_z;
	int thdblks_idx_z_max;
	int tmp;
	/*
	Initializations
	*/
	size_1_1=(y_max/blockDim.y);
	size_1_2=(z_max/blockDim.z);
	idx_1_2=(blockIdx.y/size_1_2);
	tmp=(blockIdx.y-(idx_1_2*size_1_2));
	chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
	chunk_idx_x_max=(chunk_idx_x+c);
	chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
	chunk_idx_y_max=(chunk_idx_y+1);
	chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
	chunk_idx_z_max=(chunk_idx_z+1);
	thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
	thdblks_idx_x_max=(thdblks_idx_x+tbx);
	thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
	thdblks_idx_y_max=(thdblks_idx_y+tby);
	thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
	thdblks_idx_z_max=(thdblks_idx_z+tbz);
	/*
	Implementation
	*/
	/*
	for t = 1..t_max by 1 parallel 1 <level 0> schedule  { ... }
	*/
	//for (t=1; t<=t_max; t+=1)
	{
		/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
		/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
		/*
		for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
		*/
		{
			/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
			thd_idx_z=chunk_idx_z;
			thd_idx_y=chunk_idx_y;
			for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
			{
				/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
				/*
				u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
				*/
				/* _idx0 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t)) */
				_idx0=(((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t));
				u__u_0[(t-1)][_idx0]=0.1;
				/* _idx1 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+1) */
				_idx1=(((_idx0-x_max)-(2*t))+1);
				u__u_0[(t-1)][_idx1]=0.1;
				/* _idx2 = (((((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(2*t))+1) */
				_idx2=((((_idx0+((( - x_max)-(2*t))*y_max))-((2*t)*x_max))-(4*(t*t)))+1);
				u__u_0[(t-1)][_idx2]=0.1;
				/* _idx3 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+1) */
				_idx3=(_idx0+1);
				u__u_0[(t-1)][_idx3]=0.1;
				/* _idx4 = ((((((((((((thd_idx_z+2)*x_max)+((2*t)*thd_idx_z))+(4*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(4*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(8*(t*t)))+(2*t))+1) */
				_idx4=(((_idx3+((x_max+(2*t))*y_max))+((2*t)*x_max))+(4*(t*t)));
				u__u_0[(t-1)][_idx4]=0.1;
				/* _idx5 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+2)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(4*t))+1) */
				_idx5=((_idx3+x_max)+(2*t));
				u__u_0[(t-1)][_idx5]=0.1;
				/* _idx6 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+2) */
				_idx6=(_idx0+2);
				u__u_0[(t-1)][_idx6]=0.1;
				u__u_0[t][_idx3]=1.1;
			}
		}
	}
}


	.file	"tmpxft_002286f6_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z9laplacianPPfS_S_iiiiiiiPPfS_S_iiiiiii
	.type	_Z40__device_stub__Z9laplacianPPfS_S_iiiiiiiPPfS_S_iiiiiii, @function
_Z40__device_stub__Z9laplacianPPfS_S_iiiiiiiPPfS_S_iiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z9laplacianPPfS_S_iiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z40__device_stub__Z9laplacianPPfS_S_iiiiiiiPPfS_S_iiiiiii, .-_Z40__device_stub__Z9laplacianPPfS_S_iiiiiiiPPfS_S_iiiiiii
	.globl	_Z9laplacianPPfS_S_iiiiiii
	.type	_Z9laplacianPPfS_S_iiiiiii, @function
_Z9laplacianPPfS_S_iiiiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z9laplacianPPfS_S_iiiiiiiPPfS_S_iiiiiii
	.cfi_endproc
.LFE2033:
	.size	_Z9laplacianPPfS_S_iiiiiii, .-_Z9laplacianPPfS_S_iiiiiii
	.globl	_Z39__device_stub__Z10initializePfS_iiiiiiiPfS_iiiiiii
	.type	_Z39__device_stub__Z10initializePfS_iiiiiiiPfS_iiiiiii, @function
_Z39__device_stub__Z10initializePfS_iiiiiiiPfS_iiiiiii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10initializePfS_iiiiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 208
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z39__device_stub__Z10initializePfS_iiiiiiiPfS_iiiiiii, .-_Z39__device_stub__Z10initializePfS_iiiiiiiPfS_iiiiiii
	.globl	_Z10initializePfS_iiiiiii
	.type	_Z10initializePfS_iiiiiii, @function
_Z10initializePfS_iiiiiii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z10initializePfS_iiiiiiiPfS_iiiiiii
	.cfi_endproc
.LFE2035:
	.size	_Z10initializePfS_iiiiiii, .-_Z10initializePfS_iiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10initializePfS_iiiiiii"
.LC1:
	.string	"_Z9laplacianPPfS_S_iiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10initializePfS_iiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9laplacianPPfS_S_iiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define t_max 1
#define t 1
/*
(u[0][0][0][1][0]=((((u[1][0][0][0][0]+(u[-1][0][0][0][0]+u[0][1][0][0][0]))+(u[0][-1][0][0][0]+(u[0][0][1][0][0]+u[0][0][-1][0][0])))*0.25)-u[0][0][0][0][0]))

*/
__global__ void laplacian(float *  *  u_0_1_out, float *  u_0_0, float *  u_0_1, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
	//float *  const u__u_0[16] =  { u_0_0, u_0_1 } ;
	int _idx0;
	int _idx1;
	int _idx2;
	int _idx3;
	int _idx4;
	int _idx5;
	int _idx6;
	int chunk_idx_x;
	int chunk_idx_x_max;
	int chunk_idx_y;
	int chunk_idx_y_max;
	int chunk_idx_z;
	int chunk_idx_z_max;
	int idx_1_2;
	int size_1_1;
	int size_1_2;
	//int t;
	int thd_idx_x;
	int thd_idx_y;
	int thd_idx_z;
	int thdblks_idx_x;
	int thdblks_idx_x_max;
	int thdblks_idx_y;
	int thdblks_idx_y_max;
	int thdblks_idx_z;
	int thdblks_idx_z_max;
	int tmp;
	/*
	Initializations
	*/
	size_1_1=(y_max/blockDim.y);
	size_1_2=(z_max/blockDim.z);
	idx_1_2=(blockIdx.y/size_1_2);
	tmp=(blockIdx.y-(idx_1_2*size_1_2));
	chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
	chunk_idx_x_max=(chunk_idx_x+c);
	chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
	chunk_idx_y_max=(chunk_idx_y+1);
	chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
	chunk_idx_z_max=(chunk_idx_z+1);
	thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
	thdblks_idx_x_max=(thdblks_idx_x+tbx);
	thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
	thdblks_idx_y_max=(thdblks_idx_y+tby);
	thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
	thdblks_idx_z_max=(thdblks_idx_z+tbz);
	/*
	Implementation
	*/
	/*
	for t = 1..t_max by 1 parallel 1 <level 0> schedule  { ... }
	*/
	//for (t=1; t<=t_max; t+=1)
	{
		/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
		/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
		/*
		for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
		*/
		{
			/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
			thd_idx_z=chunk_idx_z;
			thd_idx_y=chunk_idx_y;
			for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
			{
				/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
				/*
				u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
				*/
				/* _idx0 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+2) */
				_idx0=((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+2);
				/* _idx1 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t)) */
				_idx1=(_idx0-2);
				/* _idx2 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+2)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(4*t))+1) */
				_idx2=(((_idx1+x_max)+(2*t))+1);
				/* _idx3 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+1) */
				_idx3=(((_idx1-x_max)-(2*t))+1);
				/* _idx4 = ((((((((((((thd_idx_z+2)*x_max)+((2*t)*thd_idx_z))+(4*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(4*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(8*(t*t)))+(2*t))+1) */
				_idx4=((((_idx1+((x_max+(2*t))*y_max))+((2*t)*x_max))+(4*(t*t)))+1);
				/* _idx5 = (((((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(2*t))+1) */
				_idx5=((((_idx1+((( - x_max)-(2*t))*y_max))-((2*t)*x_max))-(4*(t*t)))+1);
				/* _idx6 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+1) */
				_idx6=(_idx1+1);
				u_0_1[_idx6]=((((u_0_0[_idx0]+(u_0_0[_idx1]+u_0_0[_idx2]))+(u_0_0[_idx3]+(u_0_0[_idx4]+u_0_0[_idx5])))*0.25)-u_0_0[_idx6]);
			}
		}
	}
}

__global__ void initialize(float *  u_0_0, float *  u_0_1, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
	float *  const u__u_0[16] =  { u_0_0, u_0_1 } ;
	int _idx0;
	int _idx1;
	int _idx2;
	int _idx3;
	int _idx4;
	int _idx5;
	int _idx6;
	int chunk_idx_x;
	int chunk_idx_x_max;
	int chunk_idx_y;
	int chunk_idx_y_max;
	int chunk_idx_z;
	int chunk_idx_z_max;
	int idx_1_2;
	int size_1_1;
	int size_1_2;
	//int t;
	int thd_idx_x;
	int thd_idx_y;
	int thd_idx_z;
	int thdblks_idx_x;
	int thdblks_idx_x_max;
	int thdblks_idx_y;
	int thdblks_idx_y_max;
	int thdblks_idx_z;
	int thdblks_idx_z_max;
	int tmp;
	/*
	Initializations
	*/
	size_1_1=(y_max/blockDim.y);
	size_1_2=(z_max/blockDim.z);
	idx_1_2=(blockIdx.y/size_1_2);
	tmp=(blockIdx.y-(idx_1_2*size_1_2));
	chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
	chunk_idx_x_max=(chunk_idx_x+c);
	chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
	chunk_idx_y_max=(chunk_idx_y+1);
	chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
	chunk_idx_z_max=(chunk_idx_z+1);
	thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
	thdblks_idx_x_max=(thdblks_idx_x+tbx);
	thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
	thdblks_idx_y_max=(thdblks_idx_y+tby);
	thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
	thdblks_idx_z_max=(thdblks_idx_z+tbz);
	/*
	Implementation
	*/
	/*
	for t = 1..t_max by 1 parallel 1 <level 0> schedule  { ... }
	*/
	//for (t=1; t<=t_max; t+=1)
	{
		/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
		/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
		/*
		for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
		*/
		{
			/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
			thd_idx_z=chunk_idx_z;
			thd_idx_y=chunk_idx_y;
			for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
			{
				/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
				/*
				u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
				*/
				/* _idx0 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t)) */
				_idx0=(((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t));
				u__u_0[(t-1)][_idx0]=0.1;
				/* _idx1 = (((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+1) */
				_idx1=(((_idx0-x_max)-(2*t))+1);
				u__u_0[(t-1)][_idx1]=0.1;
				/* _idx2 = (((((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(2*t))+1) */
				_idx2=((((_idx0+((( - x_max)-(2*t))*y_max))-((2*t)*x_max))-(4*(t*t)))+1);
				u__u_0[(t-1)][_idx2]=0.1;
				/* _idx3 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+1) */
				_idx3=(_idx0+1);
				u__u_0[(t-1)][_idx3]=0.1;
				/* _idx4 = ((((((((((((thd_idx_z+2)*x_max)+((2*t)*thd_idx_z))+(4*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(4*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(8*(t*t)))+(2*t))+1) */
				_idx4=(((_idx3+((x_max+(2*t))*y_max))+((2*t)*x_max))+(4*(t*t)));
				u__u_0[(t-1)][_idx4]=0.1;
				/* _idx5 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+2)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(4*t))+1) */
				_idx5=((_idx3+x_max)+(2*t));
				u__u_0[(t-1)][_idx5]=0.1;
				/* _idx6 = ((((((((((((thd_idx_z+1)*x_max)+((2*t)*thd_idx_z))+(2*t))*y_max)+((((((2*t)*thd_idx_z)+thd_idx_y)+(2*t))+1)*x_max))+((4*(t*t))*thd_idx_z))+((2*t)*thd_idx_y))+thd_idx_x)+(4*(t*t)))+(2*t))+2) */
				_idx6=(_idx0+2);
				u__u_0[(t-1)][_idx6]=0.1;
				u__u_0[t][_idx3]=1.1;
			}
		}
	}
}


	.text
	.file	"kernel.hip"
	.globl	_Z24__device_stub__laplacianPPfS_S_iiiiiii # -- Begin function _Z24__device_stub__laplacianPPfS_S_iiiiiii
	.type	_Z24__device_stub__laplacianPPfS_S_iiiiiii,@function
_Z24__device_stub__laplacianPPfS_S_iiiiiii: # @_Z24__device_stub__laplacianPPfS_S_iiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9laplacianPPfS_S_iiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__laplacianPPfS_S_iiiiiii, .Lfunc_end0-_Z24__device_stub__laplacianPPfS_S_iiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__initializePfS_iiiiiii # -- Begin function _Z25__device_stub__initializePfS_iiiiiii
	.type	_Z25__device_stub__initializePfS_iiiiiii,@function
_Z25__device_stub__initializePfS_iiiiiii: # @_Z25__device_stub__initializePfS_iiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10initializePfS_iiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__initializePfS_iiiiiii, .Lfunc_end1-_Z25__device_stub__initializePfS_iiiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9laplacianPPfS_S_iiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10initializePfS_iiiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9laplacianPPfS_S_iiiiiii,@object # @_Z9laplacianPPfS_S_iiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z9laplacianPPfS_S_iiiiiii
	.p2align	3, 0x0
_Z9laplacianPPfS_S_iiiiiii:
	.quad	_Z24__device_stub__laplacianPPfS_S_iiiiiii
	.size	_Z9laplacianPPfS_S_iiiiiii, 8

	.type	_Z10initializePfS_iiiiiii,@object # @_Z10initializePfS_iiiiiii
	.globl	_Z10initializePfS_iiiiiii
	.p2align	3, 0x0
_Z10initializePfS_iiiiiii:
	.quad	_Z25__device_stub__initializePfS_iiiiiii
	.size	_Z10initializePfS_iiiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9laplacianPPfS_S_iiiiiii"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10initializePfS_iiiiiii"
	.size	.L__unnamed_2, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__laplacianPPfS_S_iiiiiii
	.addrsig_sym _Z25__device_stub__initializePfS_iiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9laplacianPPfS_S_iiiiiii
	.addrsig_sym _Z10initializePfS_iiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9laplacianPPfS_S_iiiiiii ; -- Begin function _Z9laplacianPPfS_S_iiiiiii
	.globl	_Z9laplacianPPfS_S_iiiiiii
	.p2align	8
	.type	_Z9laplacianPPfS_S_iiiiiii,@function
_Z9laplacianPPfS_S_iiiiiii:             ; @_Z9laplacianPPfS_S_iiiiiii
; %bb.0:
	s_load_b32 s3, s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_mov_b32_e32 v1, 0
	v_bfe_u32 v5, v0, 10, 10
	global_load_b32 v4, v1, s[0:1] offset:70
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s0, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v4
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s2, 16
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s11, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_mul_i32 s11, s11, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s11, s1, s11
	s_add_i32 s1, s1, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s1, s10, s1
	s_mul_i32 s11, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s10, s10, s11
	s_add_i32 s11, s1, 1
	s_sub_i32 s12, s10, s2
	s_cmp_ge_u32 s10, s2
	s_cselect_b32 s1, s11, s1
	s_cselect_b32 s10, s12, s10
	s_add_i32 s11, s1, 1
	s_cmp_ge_u32 s10, s2
	s_cselect_b32 s10, s11, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s10
	s_sub_i32 s11, 0, s10
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s1, v1
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s11, s11, s1
	v_mad_u64_u32 v[2:3], null, s14, s0, v[1:2]
	s_mul_hi_u32 s11, s1, s11
	v_bfe_u32 v1, v0, 20, 10
	s_add_i32 s1, s1, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s0, s15, s1
	s_mul_i32 s1, s0, s10
	s_add_i32 s11, s0, 1
	s_sub_i32 s1, s15, s1
	v_mul_lo_u32 v0, v2, s3
	s_sub_i32 s12, s1, s10
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s11, s0
	s_cselect_b32 s1, s12, s1
	s_add_i32 s11, s0, 1
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s11, s0
	s_add_i32 s11, s8, 2
	v_mad_u64_u32 v[2:3], null, s0, s2, v[1:2]
	s_mul_i32 s0, s0, s10
	s_ashr_i32 s1, s8, 31
	s_sub_i32 s0, s15, s0
	s_add_u32 s2, s4, 36
	v_mul_lo_u32 v1, s0, v4
	s_addc_u32 s10, s5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 2, v2
	v_lshlrev_b32_e32 v6, 1, v2
	v_mad_u64_u32 v[3:4], null, s8, v2, s[8:9]
	s_mul_i32 s16, s11, s9
	v_mul_lo_u32 v4, s8, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add3_u32 v7, v1, v5, v6
	s_add_u32 s11, s4, 20
	s_addc_u32 s12, s5, 0
	v_lshlrev_b32_e32 v1, 1, v1
	v_add3_u32 v3, v6, v3, 2
	v_add_nc_u32_e32 v8, 3, v7
	v_add_nc_u32_e32 v9, 5, v7
	v_add3_u32 v4, v4, v6, 4
	v_add_nc_u32_e32 v6, 2, v7
	s_add_u32 s13, s4, -12
	v_mul_lo_u32 v7, s8, v7
	v_mul_lo_u32 v10, v3, s9
	v_mul_lo_u32 v9, s8, v9
	v_mul_lo_u32 v11, s9, v4
	v_mul_lo_u32 v6, s8, v6
	s_addc_u32 s14, s5, -1
	s_add_u32 s6, s6, 28
	s_addc_u32 s7, s7, 0
	s_add_i32 s16, s16, 4
	v_mad_u64_u32 v[3:4], null, v8, s8, v[1:2]
	v_mul_lo_u32 v4, v2, s16
	v_lshlrev_b32_e32 v2, 2, v2
	v_add3_u32 v7, v1, s8, v7
	v_add3_u32 v8, v1, v9, v11
	v_add3_u32 v1, v1, v6, v10
	v_lshlrev_b32_e32 v5, 1, v5
	v_add3_u32 v3, v3, v10, v0
	s_mov_b32 s9, 0
	v_add3_u32 v4, v7, v0, v4
	v_add3_u32 v6, v8, v0, v2
	v_add3_u32 v7, v1, v0, v2
	v_add_nc_u32_e32 v1, s3, v0
	v_add3_u32 v2, v3, v2, v5
	v_add3_u32 v3, v4, v5, 6
	v_add3_u32 v4, v6, v5, 6
	v_add3_u32 v5, v7, v5, 5
	s_mov_b32 s3, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v6, s9, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v8, s9, v5
	v_add_nc_u32_e32 v10, s9, v4
	v_add_nc_u32_e32 v12, s9, v3
	s_add_i32 s9, s9, 1
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_u32 v14, vcc_lo, v6, s8
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[16:17], 2, v[6:7]
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_ci_u32_e32 v15, vcc_lo, s1, v7, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[8:9]
	v_lshlrev_b64 v[8:9], 2, v[10:11]
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[12:13], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v17, vcc_lo
	v_add_co_u32 v18, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v20, vcc_lo, s11, v8
	v_add_co_ci_u32_e32 v21, vcc_lo, s12, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s13, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s14, v11, vcc_lo
	v_add_co_u32 v9, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v10, vcc_lo, s10, v13, vcc_lo
	s_clause 0x4
	global_load_b32 v11, v[6:7], off
	global_load_b96 v[6:8], v[14:15], off offset:24
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[20:21], off
	global_load_b32 v12, v[18:19], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v6, v6, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v10, v11 :: v_dual_add_f32 v6, v8, v6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v8, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v6, v8
	v_cvt_f64_f32_e32 v[6:7], v7
	v_cvt_f64_f32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], 0x3fd00000, v[8:9], -v[6:7]
	v_cvt_f32_f64_e32 v8, v[6:7]
	v_add_nc_u32_e32 v6, s9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v6, v1
	v_add_co_u32 v6, s0, s6, v16
	v_add_co_ci_u32_e64 v7, s0, s7, v17, s0
	s_or_b32 s3, vcc_lo, s3
	global_store_b32 v[6:7], v8, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9laplacianPPfS_S_iiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9laplacianPPfS_S_iiiiiii, .Lfunc_end0-_Z9laplacianPPfS_S_iiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 980
; NumSgprs: 19
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z10initializePfS_iiiiiii ; -- Begin function _Z10initializePfS_iiiiiii
	.globl	_Z10initializePfS_iiiiiii
	.p2align	8
	.type	_Z10initializePfS_iiiiiii,@function
_Z10initializePfS_iiiiiii:              ; @_Z10initializePfS_iiiiiii
; %bb.0:
	s_load_b32 s12, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s12, 1
	s_cbranch_scc1 .LBB1_3
; %bb.1:                                ; %.lr.ph
	v_mov_b32_e32 v1, 0
	v_bfe_u32 v7, v0, 10, 10
	global_load_b32 v4, v1, s[0:1] offset:62
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v4
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s2, 16
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s3, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_mul_i32 s3, s3, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s1, s3
	s_add_i32 s1, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s1, s10, s1
	s_mul_i32 s3, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s3, s10, s3
	s_add_i32 s10, s1, 1
	s_sub_i32 s11, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s1, s10, s1
	s_cselect_b32 s3, s11, s3
	s_add_i32 s10, s1, 1
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s1, s10, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s1
	s_sub_i32 s10, 0, s1
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s3, v1
	v_and_b32_e32 v1, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s10, s10, s3
	v_mad_u64_u32 v[2:3], null, s14, s0, v[1:2]
	s_mul_hi_u32 s10, s3, s10
	v_bfe_u32 v1, v0, 20, 10
	s_add_i32 s3, s3, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s0, s15, s3
	s_mul_i32 s3, s0, s1
	s_add_i32 s10, s0, 1
	s_sub_i32 s3, s15, s3
	v_mul_lo_u32 v0, v2, s12
	s_sub_i32 s11, s3, s1
	s_cmp_ge_u32 s3, s1
	s_cselect_b32 s0, s10, s0
	s_cselect_b32 s3, s11, s3
	s_add_i32 s10, s0, 1
	s_cmp_ge_u32 s3, s1
	s_cselect_b32 s0, s10, s0
	s_add_i32 s3, s8, 2
	v_mad_u64_u32 v[2:3], null, s0, s2, v[1:2]
	s_mul_i32 s0, s0, s1
	s_mul_i32 s16, s3, s9
	s_sub_i32 s0, s15, s0
	s_add_u32 s1, s4, -12
	v_mul_lo_u32 v1, s0, v4
	s_addc_u32 s2, s5, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, 2, v2
	v_lshlrev_b32_e32 v5, 1, v2
	v_mad_u64_u32 v[3:4], null, s8, v2, s[8:9]
	s_add_u32 s3, s4, 16
	v_mul_lo_u32 v6, s8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add3_u32 v8, v1, v7, v5
	v_lshlrev_b32_e32 v4, 1, v1
	s_addc_u32 s10, s5, 0
	s_ashr_i32 s11, s8, 31
	v_add3_u32 v1, v5, v3, 2
	v_add_nc_u32_e32 v9, 5, v8
	v_add_nc_u32_e32 v10, 2, v8
	v_add3_u32 v5, v6, v5, 4
	s_add_u32 s13, s4, 36
	v_add_nc_u32_e32 v3, 3, v8
	v_mul_lo_u32 v8, s8, v8
	v_mul_lo_u32 v11, v1, s9
	v_mov_b32_e32 v1, 0x3dcccccd
	v_mul_lo_u32 v9, s8, v9
	v_mul_lo_u32 v10, s8, v10
	v_mul_lo_u32 v12, s9, v5
	s_addc_u32 s14, s5, 0
	s_add_u32 s6, s6, 28
	s_addc_u32 s7, s7, 0
	s_add_i32 s16, s16, 4
	v_mad_u64_u32 v[5:6], null, v3, s8, v[4:5]
	v_mul_lo_u32 v3, v2, s16
	v_lshlrev_b32_e32 v6, 2, v2
	v_add3_u32 v2, v4, s8, v8
	v_add3_u32 v8, v4, v10, v11
	v_add3_u32 v4, v4, v9, v12
	v_lshlrev_b32_e32 v7, 1, v7
	v_add3_u32 v5, v5, v11, v0
	s_mov_b32 s9, 0
	v_add3_u32 v9, v2, v0, v3
	v_add3_u32 v8, v8, v0, v6
	v_add3_u32 v10, v4, v0, v6
	v_add_nc_u32_e32 v2, s12, v0
	v_add3_u32 v3, v5, v6, v7
	v_add3_u32 v4, v9, v7, 6
	v_add3_u32 v5, v8, v7, 5
	v_add3_u32 v6, v10, v7, 7
	v_mov_b32_e32 v7, 0x3f8ccccd
	s_mov_b32 s12, 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v8, s12, v3
	v_add_nc_u32_e32 v10, s12, v5
	v_add_nc_u32_e32 v12, s12, v4
	v_add_nc_u32_e32 v14, s12, v6
	s_add_i32 s12, s12, 1
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v17, s12, v0
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v16, vcc_lo, v8, s8
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[18:19], 2, v[8:9]
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	v_cmp_ge_i32_e64 s0, v17, v2
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v9, vcc_lo
	v_lshlrev_b64 v[8:9], 2, v[10:11]
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	v_lshlrev_b64 v[12:13], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 2, v[16:17]
	v_add_co_u32 v16, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s1, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s2, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s3, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v13, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	v_add_co_u32 v14, vcc_lo, s13, v14
	s_or_b32 s9, s0, s9
	v_add_co_ci_u32_e32 v15, vcc_lo, s14, v15, vcc_lo
	s_clause 0x6
	global_store_b32 v[16:17], v1, off offset:24
	global_store_b32 v[8:9], v1, off
	global_store_b32 v[10:11], v1, off
	global_store_b32 v[16:17], v1, off offset:28
	global_store_b32 v[12:13], v1, off
	global_store_b32 v[14:15], v1, off
	global_store_b32 v[16:17], v1, off offset:32
	global_store_b32 v[18:19], v7, off
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10initializePfS_iiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10initializePfS_iiiiiii, .Lfunc_end1-_Z10initializePfS_iiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 940
; NumSgprs: 19
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9laplacianPPfS_S_iiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z9laplacianPPfS_S_iiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10initializePfS_iiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z10initializePfS_iiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
