#include <stdio.h>
#include <stdlib.h>

/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {
            dtype temp9 = temp[j] * 1.0e-9;
            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                switch(k)
                {
                    case 0:
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
                        break;
                    case 6: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * log(temp9)); 
                        break;
                    default: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * pow(temp9, (2 * k - 5) / 3.0)); 
                        break;
                }
            }
        }
    }
}

template <>
__device__ void rates<float>(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {
            float temp9 = temp[j] * 1.0e-9;
            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                switch(k)
                {
                    case 0:
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
                        break;
                    case 6: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9)); 
                        break;
                    default: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f)); 
                        break;
                }
            }
        }
    }
}

template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype* lam)
{
    // Tensors
    __shared__ dtype a[nsets * ncoeff];
    __shared__ dtype temp[ncells];
    
    int xInd = blockIdx.x * blockDim.x + threadIdx.x;
    int yInd = blockIdx.y * blockDim.y + threadIdx.y;
    int ySize = blockDim.y * gridDim.y;
    int zInd = blockIdx.z * blockDim.z + threadIdx.z;
    int zSize = blockDim.z * gridDim.z;
    
    int ind = xInd * ySize * zSize + yInd * zSize + zInd;
    
    /********************************
    * Initialize coefficient matrix *
    ********************************/
    if(ind < nsets * ncoeff)
    {
        if(ind % ncoeff != 7)
        {
            a[ind] = ind - (ind / ncoeff - 1);
        }
        else
        {
            a[ind] = 0.0;
        }
    }
    
    /******************************************
    * Initialize the temperature in each cell *
    ******************************************/
    if(ind < ncells)
    {
        temp[ind] = (ind + 1) * 1e9;
    }
    
    /****************************
    * Zero the array of results *
    ****************************/
    if(ind < nsets * ncells)
    {
        lam[ind] = 0.0;
    }
    
    /*******************************************
    * Compute ln(lambda) for each set and cell *
    *******************************************/
    rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}

int main()
{
    // Tensor dimensions
    const int nsets = 4, ncells = 4, ncoeff = 8;
    
    // Results and elapsed time
    float *lam;
    cudaMallocManaged(&lam, nsets * ncells * sizeof(float));
    
    // Compute the rates
    dim3 threadsPerBlock(nsets, ncells, ncoeff);
    dim3 numBlocks(1, 1, 1);
    exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
    
    // Print ln(lambda)
    cudaDeviceSynchronize();
    printf("lambda:\n");
    
    for(int i = 0; i < nsets; i++)
    {
        for(int j = 0; j < ncells; j++)
        {
            printf("%.3f\t", lam[i * ncells + j]);
        }
        
        printf("\n");
    }
    
    return 0;
}

	.file	"tmpxft_0030e1e5_00000000-6_react_shared.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL40__device_stub__Z4execIfLi4ELi4ELi8EEvPT_Pf, @function
_ZL40__device_stub__Z4execIfLi4ELi4ELi8EEvPT_Pf:
.LFB2056:
	.cfi_startproc
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z4execIfLi4ELi4ELi8EEvPT_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_ZL40__device_stub__Z4execIfLi4ELi4ELi8EEvPT_Pf, .-_ZL40__device_stub__Z4execIfLi4ELi4ELi8EEvPT_Pf
	.section	.text._Z4execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
	.weak	_Z4execIfLi4ELi4ELi8EEvPT_
	.type	_Z4execIfLi4ELi4ELi8EEvPT_, @function
_Z4execIfLi4ELi4ELi8EEvPT_:
.LFB2106:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z4execIfLi4ELi4ELi8EEvPT_Pf
	.cfi_endproc
.LFE2106:
	.size	_Z4execIfLi4ELi4ELi8EEvPT_, .-_Z4execIfLi4ELi4ELi8EEvPT_
	.text
	.globl	_Z5ratesIfEvPT_S1_S1_iii
	.type	_Z5ratesIfEvPT_S1_S1_iii, @function
_Z5ratesIfEvPT_S1_S1_iii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z5ratesIfEvPT_S1_S1_iii, .-_Z5ratesIfEvPT_S1_S1_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"lambda:\n"
.LC1:
	.string	"%.3f\t"
.LC2:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1, %edx
	movl	$64, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8, %ecx
	movabsq	$17179869188, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$8, 24(%rsp)
	movq	%rdx, 16(%rsp)
	movq	%rdi, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	8(%rsp), %rdi
	call	_ZL40__device_stub__Z4execIfLi4ELi4ELi8EEvPT_Pf
.L11:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	xorl	%ebp, %ebp
	movl	$2, %edi
	leaq	.LC1(%rip), %r12
	call	__printf_chk@PLT
.L12:
	xorl	%ebx, %ebx
.L13:
	leaq	0(,%rbx,4), %rax
	addq	8(%rsp), %rax
	movq	%r12, %rsi
	movl	$2, %edi
	cvtss2sd	(%rax,%rbp), %xmm0
	incq	%rbx
	movb	$1, %al
	call	__printf_chk@PLT
	cmpq	$4, %rbx
	jne	.L13
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$16, %rbp
	call	__printf_chk@PLT
	cmpq	$64, %rbp
	jne	.L12
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z4execIfLi4ELi4ELi8EEvPT_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4execIfLi4ELi4ELi8EEvPT_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {
            dtype temp9 = temp[j] * 1.0e-9;
            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                switch(k)
                {
                    case 0:
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
                        break;
                    case 6: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * log(temp9)); 
                        break;
                    default: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * pow(temp9, (2 * k - 5) / 3.0)); 
                        break;
                }
            }
        }
    }
}

template <>
__device__ void rates<float>(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
    int istart = blockIdx.x * blockDim.x + threadIdx.x;
    int istep = blockDim.x * gridDim.x;
    
    int jstart = blockIdx.y * blockDim.y + threadIdx.y;
    int jstep = blockDim.y * gridDim.y;
    
    int kstart = blockIdx.z * blockDim.z + threadIdx.z;
    int kstep = blockDim.z * gridDim.z;
    
    for(int i = istart; i < nsets; i += istep)
    {
        for(int j = jstart; j < ncells; j += jstep)
        {
            float temp9 = temp[j] * 1.0e-9;
            
            for(int k = kstart; k < ncoeff; k += kstep)
            {
                switch(k)
                {
                    case 0:
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
                        break;
                    case 6: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9)); 
                        break;
                    default: 
                        atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f)); 
                        break;
                }
            }
        }
    }
}

template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype* lam)
{
    // Tensors
    __shared__ dtype a[nsets * ncoeff];
    __shared__ dtype temp[ncells];
    
    int xInd = blockIdx.x * blockDim.x + threadIdx.x;
    int yInd = blockIdx.y * blockDim.y + threadIdx.y;
    int ySize = blockDim.y * gridDim.y;
    int zInd = blockIdx.z * blockDim.z + threadIdx.z;
    int zSize = blockDim.z * gridDim.z;
    
    int ind = xInd * ySize * zSize + yInd * zSize + zInd;
    
    /********************************
    * Initialize coefficient matrix *
    ********************************/
    if(ind < nsets * ncoeff)
    {
        if(ind % ncoeff != 7)
        {
            a[ind] = ind - (ind / ncoeff - 1);
        }
        else
        {
            a[ind] = 0.0;
        }
    }
    
    /******************************************
    * Initialize the temperature in each cell *
    ******************************************/
    if(ind < ncells)
    {
        temp[ind] = (ind + 1) * 1e9;
    }
    
    /****************************
    * Zero the array of results *
    ****************************/
    if(ind < nsets * ncells)
    {
        lam[ind] = 0.0;
    }
    
    /*******************************************
    * Compute ln(lambda) for each set and cell *
    *******************************************/
    rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}

int main()
{
    // Tensor dimensions
    const int nsets = 4, ncells = 4, ncoeff = 8;
    
    // Results and elapsed time
    float *lam;
    hipMallocManaged(&lam, nsets * ncells * sizeof(float));
    
    // Compute the rates
    dim3 threadsPerBlock(nsets, ncells, ncoeff);
    dim3 numBlocks(1, 1, 1);
    exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
    
    // Print ln(lambda)
    hipDeviceSynchronize();
    printf("lambda:\n");
    
    for(int i = 0; i < nsets; i++)
    {
        for(int j = 0; j < ncells; j++)
        {
            printf("%.3f\t", lam[i * ncells + j]);
        }
        
        printf("\n");
    }
    
    return 0;
}

	.text
	.file	"react_shared.hip"
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	8(%rsp), %rdi
	movl	$64, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	$1, %esi
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	8(%rsp), %rdi
	callq	_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.LBB0_2:
	callq	hipDeviceSynchronize
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB0_3:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
	xorl	%r15d, %r15d
.LBB0_4:                                #   Parent Loop BB0_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	8(%rsp), %rax
	addq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r15,4), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$4, %r15
	jne	.LBB0_4
# %bb.5:                                #   in Loop: Header=BB0_3 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r14
	addq	$16, %rbx
	cmpq	$4, %r14
	jne	.LBB0_3
# %bb.6:
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.text._Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,comdat
	.weak	_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_ # -- Begin function _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
	.type	_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,@function
_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_: # @_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4execIfLi4ELi4ELi8EEvPT_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_, .Lfunc_end1-_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4execIfLi4ELi4ELi8EEvPT_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4execIfLi4ELi4ELi8EEvPT_,@object # @_Z4execIfLi4ELi4ELi8EEvPT_
	.section	.rodata._Z4execIfLi4ELi4ELi8EEvPT_,"aG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
	.weak	_Z4execIfLi4ELi4ELi8EEvPT_
	.p2align	3, 0x0
_Z4execIfLi4ELi4ELi8EEvPT_:
	.quad	_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
	.size	_Z4execIfLi4ELi4ELi8EEvPT_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%.3f\t"
	.size	.L.str.1, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4execIfLi4ELi4ELi8EEvPT_"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"lambda:"
	.size	.Lstr, 8

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4execIfLi4ELi4ELi8EEvPT_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z4execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
	.protected	_Z4execIfLi4ELi4ELi8EEvPT_ ; -- Begin function _Z4execIfLi4ELi4ELi8EEvPT_
	.globl	_Z4execIfLi4ELi4ELi8EEvPT_
	.p2align	8
	.type	_Z4execIfLi4ELi4ELi8EEvPT_,@function
_Z4execIfLi4ELi4ELi8EEvPT_:             ; @_Z4execIfLi4ELi4ELi8EEvPT_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s8, s[0:1], 0x18
	v_bfe_u32 v3, v0, 10, 10
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s9, s7, 16
	s_and_b32 s7, s7, 0xffff
	v_mad_u64_u32 v[1:2], null, s14, s9, v[3:4]
	v_mad_u64_u32 v[6:7], null, s13, s7, v[5:6]
	s_and_b32 s7, s8, 0xffff
	s_mul_i32 s10, s5, s9
	s_mul_i32 s11, s6, s7
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s7, v[0:1]
	v_mad_u64_u32 v[7:8], null, s10, v6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v7, s11, v[2:3]
	v_cmpx_gt_i32_e32 32, v3
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_and_b32_e32 v0, 0x80000007, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 7, v0
	v_mov_b32_e32 v0, 0
	s_and_saveexec_b32 s6, vcc_lo
; %bb.2:
	v_ashrrev_i32_e32 v0, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 29, v0
	v_add_nc_u32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 3, v0
	v_sub_nc_u32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 1, v0
	v_cvt_f32_i32_e32 v0, v0
; %bb.3:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s6
	v_lshlrev_b32_e32 v4, 2, v3
	ds_store_b32 v4, v0
.LBB0_4:                                ; %Flow42
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_i32_e32 4, v3
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_add_nc_u32_e32 v0, 1, v3
	v_lshlrev_b32_e32 v4, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[6:7], v0
	v_mul_f64 v[6:7], 0x41cdcd65, v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[6:7]
	ds_store_b32 v4, v0 offset:128
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s5
	s_load_b64 s[6:7], s[0:1], 0x0
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e32 16, v3
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_ashrrev_i32_e32 v4, 31, v3
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_store_b32 v[3:4], v0, off
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_lt_u32 s13, s4
	s_cselect_b32 s0, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, s0
	s_mov_b32 s0, exec_lo
	global_load_u16 v0, v0, s[2:3]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, s13, v0, v[5:6]
	v_cmpx_gt_i32_e32 4, v3
	s_cbranch_execz .LBB0_29
; %bb.9:                                ; %.preheader.lr.ph.i
	v_mul_lo_u32 v0, s4, v0
	v_cmp_gt_i32_e64 s0, 4, v1
	v_cmp_gt_i32_e64 s1, 8, v2
	s_mov_b32 s8, 0xe826d695
	s_mov_b32 s9, 0x3e112e0b
	s_mov_b32 s12, 0
	s_mov_b32 s13, 0x3e76c4e1
.LBB0_10:                               ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_12 Depth 2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;         Child Loop BB0_25 Depth 4
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_28
; %bb.11:                               ; %.lr.ph59.i
                                        ;   in Loop: Header=BB0_10 Depth=1
	v_lshlrev_b32_e32 v8, 2, v3
	v_dual_mov_b32 v10, v1 :: v_dual_lshlrev_b32 v9, 5, v3
	s_mov_b32 s15, 0
.LBB0_12:                               ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;         Child Loop BB0_25 Depth 4
	s_and_saveexec_b32 s16, s1
	s_cbranch_execz .LBB0_27
; %bb.13:                               ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 2, v10
	s_mov_b32 s17, 0
	v_mov_b32_e32 v13, v2
	ds_load_b32 v4, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[4:5], s[8:9]
	v_cvt_f32_f64_e32 v11, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v11
	v_cmp_eq_f32_e64 s2, 1.0, v11
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	v_mul_f32_e32 v4, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_log_f32_e32 v6, v4
	v_add_nc_u32_e32 v4, v10, v8
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x3f317217, v6
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, 0x3f317217, v6, -v7
	v_fmac_f32_e32 v12, 0x3377d1cf, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, v7, v12
	v_cndmask_b32_e64 v12, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v12, v6, v12
.LBB0_14:                               ; %NodeBlock
                                        ;   Parent Loop BB0_10 Depth=1
                                        ;     Parent Loop BB0_12 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_25 Depth 4
	s_mov_b32 s18, 0
	s_mov_b32 s3, 0
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $vgpr14
	v_cmpx_lt_i32_e32 5, v13
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_18
; %bb.15:                               ; %LeafBlock31
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_mov_b32 s3, -1
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $vgpr14
	v_cmpx_eq_u32_e32 6, v13
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_14 Depth=3
	ds_load_b32 v6, v9 offset:24
	s_xor_b32 s3, exec_lo, -1
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v14, v12, v6
.LBB0_17:                               ; %Flow33
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
.LBB0_18:                               ; %Flow
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_and_not1_saveexec_b32 s4, s4
; %bb.19:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_14 Depth=3
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	s_and_not1_b32 s3, s3, exec_lo
	s_mov_b32 s18, exec_lo
                                        ; implicit-def: $vgpr14
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s5
; %bb.20:                               ; %Flow34
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s4
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_14 Depth=3
	v_lshl_add_u32 v6, v13, 1, -5
	s_and_not1_b32 s18, s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v6, v6
	v_div_scale_f32 v7, null, 0x40400000, 0x40400000, v6
	v_div_scale_f32 v16, vcc_lo, v6, 0x40400000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v7, v14, 1.0
	v_fmac_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v16, v14
	v_fma_f32 v17, -v7, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v17, v14
	v_fma_f32 v7, -v7, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v14, v15
	v_div_fixup_f32 v6, v7, 0x40400000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v6, 1.0, s2
	v_cmp_neq_f32_e32 vcc_lo, 0, v6
	v_cmp_neq_f32_e64 s20, v6, |v6|
	v_cndmask_b32_e32 v7, 1.0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v14, |v7|
	v_cmp_lt_f32_e64 s21, |v7|, 1.0
	v_cmp_eq_f32_e64 s5, 0, v7
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_xor_b32 s20, s20, s21
	v_cndmask_b32_e64 v15, 0, 1, vcc_lo
	v_ldexp_f32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, 1.0, v14
	v_add_f32_e32 v17, -1.0, v14
	v_rcp_f32_e32 v16, v15
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v18, v17, v16 :: v_dual_add_f32 v19, -1.0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, v15, v18
	v_sub_f32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, v18, v15, -v20
	v_fmac_f32_e32 v15, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v20, v15
	v_dual_sub_f32 v19, v17, v14 :: v_dual_sub_f32 v20, v14, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v20, v15
	v_sub_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v17, v14
	v_add_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v19, v14
	v_mul_f32_e32 v14, v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v18, v14
	v_mul_f32_e32 v17, v15, v15
	v_sub_f32_e32 v16, v15, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v14, v16
	v_fma_f32 v16, v15, v15, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v14, v14
	v_fmac_f32_e32 v16, v15, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v17, v16
	v_fmaak_f32 v19, s13, v18, 0x3e91f4c4
	v_sub_f32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v19, v18, v19, 0x3ecccdef :: v_dual_sub_f32 v16, v16, v17
	v_mul_f32_e32 v20, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, v18, v19, -v20
	v_fmac_f32_e32 v17, v16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v20, v17
	v_dual_sub_f32 v20, v19, v20 :: v_dual_add_f32 v21, 0x3f2aaaaa, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v22, v15, v18 :: v_dual_sub_f32 v17, v17, v20
	v_fma_f32 v23, v18, v15, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, 0xbf2aaaaa, v21
	v_add_f32_e32 v17, 0x31739010, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, v18, v14
	v_ldexp_f32 v14, v14, 1
	v_fmac_f32_e32 v23, v16, v15
	v_sub_f32_e32 v19, v19, v20
	v_ldexp_f32 v15, v15, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v18, v22, v23
	v_add_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v21, v17
	v_mul_f32_e32 v20, v18, v16
	v_sub_f32_e32 v19, v21, v16
	v_sub_f32_e32 v21, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v17, v17, v19
	v_fma_f32 v19, v18, v16, -v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v23, v21
	v_fmac_f32_e32 v19, v18, v17
	v_frexp_exp_i32_f32_e32 v17, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v21, v16
	v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v20, v19
	v_cvt_f32_i32_e32 v16, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v20, v17, v20
	v_dual_mul_f32 v21, 0x3f317218, v16 :: v_dual_add_f32 v18, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v19, v20
	v_fma_f32 v20, 0x3f317218, v16, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v14, v19
	v_dual_fmac_f32 v20, 0xb102e308, v16 :: v_dual_sub_f32 v15, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v17, v15
	v_add_f32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v16, v18, v14 :: v_dual_add_f32 v15, v21, v20
	v_dual_sub_f32 v18, v16, v18 :: v_dual_add_f32 v17, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v14, v18 :: v_dual_sub_f32 v19, v17, v15
	v_sub_f32_e32 v22, v17, v19
	v_dual_sub_f32 v16, v16, v19 :: v_dual_sub_f32 v21, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v15, v22 :: v_dual_sub_f32 v20, v20, v21
	v_add_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v20, v14
	v_sub_f32_e32 v16, v18, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v18, v15
	v_sub_f32_e32 v18, v18, v16
	v_sub_f32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v20, v18 :: v_dual_add_f32 v19, v17, v15
	v_dual_add_f32 v14, v14, v16 :: v_dual_sub_f32 v17, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v17
	v_add_f32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v19, v14
	v_sub_f32_e32 v16, v15, v19
	v_mul_f32_e32 v17, v6, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v14, v16
	v_fma_f32 v15, v6, v15, -v17
	v_cmp_class_f32_e64 vcc_lo, v17, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v6, v14
	v_add_f32_e32 v14, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v16, v14, v17, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v16
	v_cndmask_b32_e64 v18, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v16|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v19, v16, v18 :: v_dual_sub_f32 v14, v14, v17
	v_trunc_f32_e32 v16, v6
	v_mul_f32_e32 v20, 0x3fb8aa3b, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v15, v14
	v_fma_f32 v21, 0x3fb8aa3b, v19, -v20
	v_rndne_f32_e32 v22, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v21, 0x32a5705f, v19 :: v_dual_sub_f32 v20, v20, v22
	v_cvt_i32_f32_e32 v17, v22
	v_add_f32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_exp_f32_e32 v20, v20
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v15, v20, v17
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v19
	v_mul_f32_e32 v17, 0.5, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v19
	v_trunc_f32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v14, v18, v14 :: v_dual_cndmask_b32 v15, 0x7f800000, v15
	v_cmp_eq_f32_e32 vcc_lo, v16, v6
	v_cmp_neq_f32_e64 s3, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v15, v14, v15
	v_cmp_eq_f32_e64 s4, 0x7f800000, v15
	s_and_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v16, 1.0, v7, s3
	v_cndmask_b32_e64 v14, v14, v15, s4
	v_cmp_gt_f32_e64 s4, 0, v6
	v_lshl_add_u32 v15, v13, 2, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v14, 0x7fffffff, v14, v16
	s_xor_b32 s4, s4, s5
	ds_load_b32 v15, v15
	v_cndmask_b32_e64 v16, |v6|, 0, s20
	v_cndmask_b32_e64 v18, 0x7f800000, 0, s4
	v_cndmask_b32_e32 v17, 0x7fc00000, v14, vcc_lo
	v_cmp_eq_f32_e64 s4, |v7|, 1.0
	v_cmp_gt_f32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v16, |v7|, s4
	v_cndmask_b32_e32 v14, v14, v17, vcc_lo
	v_cndmask_b32_e64 v17, 0, v7, s3
	v_cmp_class_f32_e64 vcc_lo, v6, 0x204
	v_cmp_class_f32_e64 s3, v7, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v6, v14, v16, vcc_lo
	v_bfi_b32 v14, 0x7fffffff, v18, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 vcc_lo, s5, s3
	v_cndmask_b32_e32 v6, v6, v14, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v14, v6, v15
.LBB0_22:                               ; %Flow35
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s19
	s_and_saveexec_b32 s3, s18
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_14 Depth=3
	ds_load_b32 v14, v9
.LBB0_24:                               ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v7, v[4:5], off
	s_mov_b32 s3, 0
.LBB0_25:                               ; %atomicrmw.start
                                        ;   Parent Loop BB0_10 Depth=1
                                        ;     Parent Loop BB0_12 Depth=2
                                        ;       Parent Loop BB0_14 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v7, v14
	global_atomic_cmpswap_b32 v6, v[4:5], v[6:7], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_25
; %bb.26:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v13, s11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 7, v13
	s_or_b32 s17, vcc_lo, s17
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_14
.LBB0_27:                               ; %Flow37
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	v_add_nc_u32_e32 v10, s10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 3, v10
	s_or_b32 s15, vcc_lo, s15
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_12
.LBB0_28:                               ; %Flow39
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v3, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 3, v3
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_10
.LBB0_29:                               ; %_Z5ratesIfEvPT_S1_S1_iii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4execIfLi4ELi4ELi8EEvPT_
		.amdhsa_group_segment_fixed_size 144
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z4execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
.Lfunc_end0:
	.size	_Z4execIfLi4ELi4ELi8EEvPT_, .Lfunc_end0-_Z4execIfLi4ELi4ELi8EEvPT_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2272
; NumSgprs: 24
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 144 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 144
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4execIfLi4ELi4ELi8EEvPT_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z4execIfLi4ELi4ELi8EEvPT_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
