// Copyright 2022 Huawei Technologies Co., Ltd
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ============================================================================
#define CUDA_NUM_THREADS 512
#define THREADS_PER_BLOCK 64

#include <algorithm>

__device__ __forceinline__ float MsAtomicAdd(float *address, const float val) {
  return atomicAdd(address, val);
}

__global__ void Resample2dInitKernel(size_t size_init, float *input) {
  auto idx = blockIdx.x * CUDA_NUM_THREADS + threadIdx.x;
  if (idx < size_init) {
     input[idx] = static_cast<float>(.0);
  }
}


__device__ int GET_INDEX(const int batch , const int channels, const int height, const int width,
                        const int batch_stride , const int channels_stride, const int height_stride) {
     return batch*batch_stride+channels*channels_stride+height*height_stride+width;
}

__device__ float DIM3_INDEX(const float *input, const int batch , const int channels, const int height, const int width,
                        const int batch_stride , const int channels_stride, const int height_stride) {
    return input[batch*batch_stride+channels*channels_stride+height*height_stride+width];
}


__global__ void Resample2dKernel(size_t size, const float *input1, const float *input2, float *out_data,
                    int batch_stride_x1, int channel_stride_x1, int height_stride_x1,
                    int batch_stride_x2, int channel_stride_x2, int height_stride_x2,
                    int batch_output, int channel_output, int height_output, int width_output,
                    int kernel_size, bool bilinear) {
    int index = blockIdx.x * blockDim.x + threadIdx.x;

    if (index >= size) {
        return;
    }

    float val = 0.0;

    int dim_b = batch_output;
    int dim_c = channel_output;
    int dim_h = height_output;
    int dim_w = width_output;
    int dim_chw = dim_c * dim_h * dim_w;
    int dim_hw  = dim_h * dim_w;
    int b = (index / dim_chw) % dim_b;
    int c = (index / dim_hw) % dim_c;
    int y = (index / dim_w) % dim_h;
    int x = (index) % dim_w;

    float dx = DIM3_INDEX(input2, b, 0, y, x, batch_stride_x2, channel_stride_x2, height_stride_x2);
    float dy = DIM3_INDEX(input2, b, 1, y, x, batch_stride_x2, channel_stride_x2, height_stride_x2);

    float xf = x + dx;
    float yf = y + dy;  // img+flow
    float alpha = xf - (floor(xf));  // alpha
    float beta = yf - (floor(yf));  // beta
    if (bilinear) {
        int xL = max(min(static_cast<int>(floor(xf)),    dim_w-1), 0);
        int xR = max(min(static_cast<int>(floor(xf)+1), dim_w -1), 0);
        int yT = max(min(static_cast<int>(floor(yf)),    dim_h-1), 0);
        int yB = max(min(static_cast<int>(floor(yf)+1),  dim_h-1), 0);
        for (int fy = 0; fy < kernel_size; fy += 1) {
            for (int fx = 0; fx < kernel_size; fx += 1) {
                float offTL = DIM3_INDEX(input1, b, c, yT + fy, xL + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                float offTR = DIM3_INDEX(input1, b, c, yT + fy, xR + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                float offBL = DIM3_INDEX(input1, b, c, yB + fy, xL + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                float offBR = DIM3_INDEX(input1, b, c, yB + fy, xR + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                val += (1. - alpha)*(1. - beta) *  offTL;
                val += (alpha)*(1. - beta) * offTR;
                val += (1. - alpha)*(beta) * offBL;
                val += (alpha)*(beta) * offBR;
            }
        }
        out_data[index] = val;
    } else {
        int xN = max(min(static_cast<int>(floor(xf + 0.5)), dim_w - 1), 0);
        int yN = max(min(static_cast<int>(floor(yf + 0.5)), dim_h - 1), 0);
        out_data[index] = DIM3_INDEX(input1, b, c, yN, xN, batch_stride_x1, channel_stride_x1, height_stride_x1);
    }
}



extern "C" int Resample2d(int nparam, void **params, int *ndims, int64_t **shapes, const char **dtypes, void *stream,
                         void *extra) {
    cudaStream_t custream = static_cast<cudaStream_t>(stream);
    constexpr int INPUT1_INDEX = 0;
    constexpr int INPUT2_INDEX = 1;
    constexpr int OUTPUT_INDEX = 2;
    constexpr int TOTAL_PARAM_NUM = 3;

    if (nparam != TOTAL_PARAM_NUM) {
    return 1;
    }
    // This is to check if the type of parameters the same as what the user wants.
    for (int i = 0; i < nparam; i++) {
        if (strcmp(dtypes[i], "float32") != 0) {
            return 2;
        }
    }

    float *x1 = static_cast<float *>(params[0]);
    float *x2 = static_cast<float *>(params[1]);

    float *out_data = static_cast<float *>(params[2]);

//     int batch_x1 = shapes[INPUT1_INDEX][0];
    int channel_x1 = shapes[INPUT1_INDEX][1];
    int height_x1 = shapes[INPUT1_INDEX][2];
    int width_x1 = shapes[INPUT1_INDEX][3];

//     int batch_x2 = shapes[INPUT2_INDEX][0];
    int channel_x2 = shapes[INPUT2_INDEX][1];
    int height_x2 = shapes[INPUT2_INDEX][2];
    int width_x2 = shapes[INPUT2_INDEX][3];

    int batch_output = shapes[OUTPUT_INDEX][0];
    int channel_output = shapes[OUTPUT_INDEX][1];
    int height_output = shapes[OUTPUT_INDEX][2];
    int width_output = shapes[OUTPUT_INDEX][3];

    // fix at now ,need to be changed in future
    const int kernel_size = 1;
    const bool bilinear = true;

    int batch_stride_x1  = channel_x1 * height_x1 * width_x1;
    int channel_stride_x1  = height_x1 * width_x1;
    int height_stride_x1 = width_x1;
    int batch_stride_x2 = channel_x2 * height_x2 * width_x2;
    int channel_stride_x2  = height_x2 * width_x2;
    int height_stride_x2  = width_x2;
    size_t size = batch_output * channel_output * height_output * width_output;
    Resample2dInitKernel<<<size / CUDA_NUM_THREADS +1, CUDA_NUM_THREADS, 0, custream>>>(size, out_data);

    Resample2dKernel<<< (size + CUDA_NUM_THREADS - 1)/CUDA_NUM_THREADS, CUDA_NUM_THREADS, 0, custream>>>
                   (size, x1, x2, out_data, batch_stride_x1, channel_stride_x1, height_stride_x1,
                   batch_stride_x2, channel_stride_x2, height_stride_x2, batch_output, channel_output,
                    height_output, width_output, kernel_size , bilinear);
    return 0;
}


__global__ void kernel_resample2d_grad_input1(size_t size,
    const float* input1, int batch_input1, int channel_input1, int height_input1, int width_input1,
    const float* input2, int batch_stride_input2, int channel_stride_input2, int height_stride_input2,
    const float* gradOutput, int batch_gradOutput, int channel_gradOutput, int height_gradOutput, int width_gradOutput,
    int batch_stride_gradOutput, int channel_stride_gradOutput, int height_stride_gradOutput,
    float* gradInput, int batch_stride_gradInput, int channel_stride_gradInput, int height_stride_gradInput,
    int kernel_size, bool bilinear) {

    int index = blockIdx.x * blockDim.x + threadIdx.x;

    if (index >= size) {
        return;
    }

    int dim_b = batch_gradOutput;
    int dim_c = channel_gradOutput;
    int dim_h = height_gradOutput;
    int dim_w = width_gradOutput;
    int dim_chw = dim_c * dim_h * dim_w;
    int dim_hw  = dim_h * dim_w;

    int b = (index / dim_chw) % dim_b;
    int c = (index / dim_hw)  % dim_c;
    int y = (index / dim_w)   % dim_h;
    int x = (index)  % dim_w;

    float dx = DIM3_INDEX(input2, b, 0, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);
    float dy = DIM3_INDEX(input2, b, 1, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);

    float xf = x + dx;
    float yf = y + dy;
    float alpha = xf - static_cast<int>(xf);  // alpha
    float beta = yf - static_cast<int>(yf);  // beta

    int idim_h = height_input1;
    int idim_w = width_input1;

    int xL = max(min(static_cast<int>(floor(xf)),    idim_w-1), 0);
    int xR = max(min(static_cast<int>(floor(xf)+1), idim_w -1), 0);
    int yT = max(min(static_cast<int>(floor(yf)),    idim_h-1), 0);
    int yB = max(min(static_cast<int>(floor(yf)+1),  idim_h-1), 0);

    float w1, w2, w3, w4;
    float num = 1.f;
    w1 = (num-alpha)*(num-beta);
    w2 = (alpha)*(num-beta);
    w3 = (num-alpha)*(beta);
    w4 = (alpha)*(beta);

    float gradnum = DIM3_INDEX(gradOutput, b, c, y, x,
            batch_stride_gradOutput, channel_stride_gradOutput, height_stride_gradOutput);
    for (int fy = 0; fy < kernel_size; fy += 1) {
        for (int fx = 0; fx < kernel_size; fx += 1) {
            int indexTL = GET_INDEX(b, c, (yT + fy), (xL + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexTL], w1 * gradnum);

            int indexTR = GET_INDEX(b, c, (yT + fy), (xR + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexTR], w2 * gradnum);

            int indexBL = GET_INDEX(b, c, (yB + fy), (xL + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexBL], w3 * gradnum);

            int indexBR = GET_INDEX(b, c, (yB + fy), (xR + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexBR], w4 * gradnum);
        }
    }
}


__global__ void kernel_resample2d_grad_input2(size_t size,
    const float  *input1, int batch_stride_input1, int channel_stride_input1, int height_stride_input1,
    const float  *input2, int batch_stride_input2, int channel_stride_input2, int height_stride_input2,
    const float  *gradOutput, int channel_gradOutput, int batch_stride_gradOutput,
    int channel_stride_gradOutput, int height_stride_gradOutput,
    float  *gradInput, int batch_gradInput, int channel_gradInput, int height_gradInput, int width_gradInput,
    int batch_stride_gradInput, int channel_stride_gradInput, int height_stride_gradInput,
    int kernel_size, bool bilinear) {
    int index = blockIdx.x * blockDim.x + threadIdx.x;

    if (index >= size) {
        return;
    }

    float output = 0.0;
    int kernel_rad = (kernel_size - 1)/2;

    int dim_b = batch_gradInput;
    int dim_c = channel_gradInput;
    int dim_h = height_gradInput;
    int dim_w = width_gradInput;
    int dim_chw = dim_c * dim_h * dim_w;
    int dim_hw  = dim_h * dim_w;

    int b = (index / dim_chw) % dim_b;
    int c = (index / dim_hw)  % dim_c;
    int y = (index / dim_w)   % dim_h;
    int x = (index)  % dim_w;

    int odim_c = channel_gradOutput;

    float dx = DIM3_INDEX(input2, b, 0, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);
    float dy = DIM3_INDEX(input2, b, 1, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);

    float xf = x + dx;
    float yf = y + dy;

    int xL = max(min(static_cast<int>(floor(xf)),    dim_w-1), 0);
    int xR = max(min(static_cast<int>(floor(xf)+1), dim_w -1), 0);
    int yT = max(min(static_cast<int>(floor(yf)),    dim_h-1), 0);
    int yB = max(min(static_cast<int>(floor(yf)+1),  dim_h-1), 0);

    if (c % 2) {
        float gamma = 1 - (xf - floor(xf));  // alpha
        for (int i = 0; i <= 2*kernel_rad ; ++i) {
            for (int j = 0; j <= 2*kernel_rad; ++j) {
                for (int ch = 0; ch < odim_c; ++ch) {
                    float gradout = DIM3_INDEX(gradOutput, b, ch, y, x,
                     batch_stride_gradOutput, channel_stride_gradOutput, height_stride_gradOutput);
                    output += (gamma) * gradout * DIM3_INDEX(input1, b, ch, (yB + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                    output -= (gamma) * gradout * DIM3_INDEX(input1, b, ch, (yT + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                    output += (1-gamma) * gradout * DIM3_INDEX(input1, b, ch, (yB + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                    output -= (1-gamma) * gradout * DIM3_INDEX(input1, b, ch, (yT + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                }
            }
        }
    } else {
        float gamma = 1 - (yf - floor(yf));  // alpha
        for (int i = 0; i <= 2*kernel_rad; ++i) {
            for (int j = 0; j <= 2*kernel_rad; ++j) {
                for (int ch = 0; ch < odim_c; ++ch) {
                    float gradout = static_cast<float>(DIM3_INDEX(gradOutput, b, ch, y, x,
                                batch_stride_gradOutput, channel_stride_gradOutput, height_stride_gradOutput));
                    output += (gamma) * gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yT + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                    output -= (gamma)* gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yT + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                    output += (1-gamma)* gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yB + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                    output -= (1-gamma) * gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yB + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                }
            }
        }
    }
    gradInput[index] = output;
}


extern "C" int Resample2dGrad(int nparam, void **params, int *ndims, int64_t **shapes, const char **dtypes,
                              void *stream, void *extra) {
    cudaStream_t custream = static_cast<cudaStream_t>(stream);
    constexpr int INPUT1_INDEX = 0;
    constexpr int INPUT2_INDEX = 1;
    constexpr int GRAD_OUTPUT_INDEX = 2;
    constexpr int TOTAL_PARAM_NUM = 5;

    if (nparam != TOTAL_PARAM_NUM) {
        return 1;
    }
    // This is to check if the type of parameters the same as what the user wants.
    for (int i = 0; i < nparam; i++) {
        if (strcmp(dtypes[i], "float32") != 0) {
            return 2;
        }
    }

    float *x1 = static_cast<float *>(params[0]);
    float *x2 = static_cast<float *>(params[1]);
    float *dout = static_cast<float *>(params[2]);
    float *dx1 = static_cast<float *>(params[3]);
    float *dx2 = static_cast<float *>(params[4]);

    int batch_x1 = shapes[INPUT1_INDEX][0];
    int channel_x1 = shapes[INPUT1_INDEX][1];
    int height_x1 = shapes[INPUT1_INDEX][2];
    int width_x1 = shapes[INPUT1_INDEX][3];

    int batch_x2 = shapes[INPUT2_INDEX][0];
    int channel_x2 = shapes[INPUT2_INDEX][1];
    int height_x2 = shapes[INPUT2_INDEX][2];
    int width_x2 = shapes[INPUT2_INDEX][3];

    int batch_dout = shapes[GRAD_OUTPUT_INDEX][0];
    int channel_dout = shapes[GRAD_OUTPUT_INDEX][1];
    int height_dout = shapes[GRAD_OUTPUT_INDEX][2];
    int width_dout = shapes[GRAD_OUTPUT_INDEX][3];

    // fix at now ,need to be changed in future
    const int kernel_size = 1;
    const bool bilinear = true;

    int batch_dx1  = batch_x1;
    int channel_dx1  = channel_x1;
    int height_dx1  = height_x1;
    int width_dx1 = width_x1;
    int batch_dx2  = batch_x2;
    int channel_dx2 = channel_x2;
    int height_dx2 = height_x2;
    int width_dx2 = width_x2;
    int batch_stride_x1  = channel_x1 * height_x1 * width_x1;
    int channel_stride_x1  = height_x1 * width_x1;
    int height_stride_x1  = width_x1;
//     int width_stride_x1 = 1;
    int batch_stride_x2  = channel_x2 * height_x2 * width_x2;
    int channel_stride_x2  = height_x2 * width_x2;
    int height_stride_x2 = width_x2;
//     int width_stride_x2 = 1;
    int batch_stride_dx1  = batch_stride_x1;
    int channel_stride_dx1 = channel_stride_x1;
    int height_stride_dx1 = height_stride_x1;
//     int width_stride_dx1 = width_stride_x1;
    int batch_stride_dx2  = batch_stride_x2;
    int channel_stride_dx2 = channel_stride_x2;
    int height_stride_dx2 = height_stride_x2;
//     int width_stride_dx2 = width_stride_x2;
    int batch_stride_dout  = channel_dout * height_dout * width_dout;
    int channel_stride_dout  = height_dout * width_dout;
    int height_stride_dout  = width_dout;
//     int width_stride_dout  = 1;

    size_t dx1_size = batch_dx1 * channel_dx1 * height_dx1 * width_dx1;

    Resample2dInitKernel<<<dx1_size / CUDA_NUM_THREADS +1, CUDA_NUM_THREADS, 0, custream>>>(dx1_size, dx1);
    size_t dx2_size = batch_dx2 * channel_dx2 * height_dx2 * width_dx2;
    Resample2dInitKernel<<<dx2_size / CUDA_NUM_THREADS +1, CUDA_NUM_THREADS, 0, custream>>>(dx2_size, dx2);

    size_t dout_size = batch_dout * channel_dout * height_dout * width_dout;

    kernel_resample2d_grad_input1<<<(dout_size + CUDA_NUM_THREADS - 1)/CUDA_NUM_THREADS, CUDA_NUM_THREADS,
                                     0, custream>>>(dout_size,
                                     x1, batch_x1, channel_x1, height_x1, width_x1,
                                     x2, batch_stride_x2, channel_stride_x2, height_stride_x2,
                                     dout, batch_dout, channel_dout, height_dout, width_dout,
                                     batch_stride_dout, channel_stride_dout, height_stride_dout,
                                     dx1, batch_stride_dx1, channel_stride_dx1, height_stride_dx1,
                                     kernel_size, bilinear);

    kernel_resample2d_grad_input2<<<(dx2_size + CUDA_NUM_THREADS - 1)/CUDA_NUM_THREADS, CUDA_NUM_THREADS,
                                    0, custream>>>(dx2_size,
                                     x1, batch_stride_x1, channel_stride_x1, height_stride_x1,
                                     x2, batch_stride_x2, channel_stride_x2, height_stride_x2,
                                     dout, channel_dout, batch_stride_dout, channel_stride_dout, height_stride_dout,
                                     dx2, batch_dx2, channel_dx2, height_dx2, width_dx2,
                                     batch_stride_dx2, channel_stride_dx2, height_stride_dx2,
                                     kernel_size, bilinear);
    return 0;
}

	.file	"tmpxft_002a7970_00000000-6_resample2d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2295:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2295:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9GET_INDEXiiiiiii
	.type	_Z9GET_INDEXiiiiiii, @function
_Z9GET_INDEXiiiiiii:
.LFB2289:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2289:
	.size	_Z9GET_INDEXiiiiiii, .-_Z9GET_INDEXiiiiiii
	.globl	_Z10DIM3_INDEXPKfiiiiiii
	.type	_Z10DIM3_INDEXPKfiiiiiii, @function
_Z10DIM3_INDEXPKfiiiiiii:
.LFB2290:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2290:
	.size	_Z10DIM3_INDEXPKfiiiiiii, .-_Z10DIM3_INDEXPKfiiiiiii
	.globl	_Z41__device_stub__Z20Resample2dInitKernelmPfmPf
	.type	_Z41__device_stub__Z20Resample2dInitKernelmPfmPf, @function
_Z41__device_stub__Z20Resample2dInitKernelmPfmPf:
.LFB2317:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z20Resample2dInitKernelmPf(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L6:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2317:
	.size	_Z41__device_stub__Z20Resample2dInitKernelmPfmPf, .-_Z41__device_stub__Z20Resample2dInitKernelmPfmPf
	.globl	_Z20Resample2dInitKernelmPf
	.type	_Z20Resample2dInitKernelmPf, @function
_Z20Resample2dInitKernelmPf:
.LFB2318:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z20Resample2dInitKernelmPfmPf
	.cfi_endproc
.LFE2318:
	.size	_Z20Resample2dInitKernelmPf, .-_Z20Resample2dInitKernelmPf
	.globl	_Z55__device_stub__Z16Resample2dKernelmPKfS0_PfiiiiiiiiiiibmPKfS0_Pfiiiiiiiiiiib
	.type	_Z55__device_stub__Z16Resample2dKernelmPKfS0_PfiiiiiiiiiiibmPKfS0_Pfiiiiiiiiiiib, @function
_Z55__device_stub__Z16Resample2dKernelmPKfS0_PfiiiiiiiiiiibmPKfS0_Pfiiiiiiiiiiib:
.LFB2319:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movl	344(%rsp), %eax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movb	%al, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	64(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 288
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L12:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2319:
	.size	_Z55__device_stub__Z16Resample2dKernelmPKfS0_PfiiiiiiiiiiibmPKfS0_Pfiiiiiiiiiiib, .-_Z55__device_stub__Z16Resample2dKernelmPKfS0_PfiiiiiiiiiiibmPKfS0_Pfiiiiiiiiiiib
	.globl	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.type	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib, @function
_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib:
.LFB2320:
	.cfi_startproc
	endbr64
	movzbl	80(%rsp), %eax
	movl	%eax, 80(%rsp)
	jmp	_Z55__device_stub__Z16Resample2dKernelmPKfS0_PfiiiiiiiiiiibmPKfS0_Pfiiiiiiiiiiib
	.cfi_endproc
.LFE2320:
	.size	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib, .-_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"float32"
	.text
	.globl	Resample2d
	.type	Resample2d, @function
Resample2d:
.LFB2291:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$1, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%r9, 24(%rsp)
	cmpl	$3, %edi
	jne	.L17
	movq	%rsi, %rbp
	movq	%rcx, %r14
	movq	%r8, %r15
	xorl	%r12d, %r12d
	leaq	.LC0(%rip), %r13
.L19:
	movq	(%r15,%r12,8), %rdi
	movq	%r13, %rsi
	call	strcmp@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L23
	incq	%r12
	cmpq	$3, %r12
	jne	.L19
	movq	0(%rbp), %rax
	movl	$1, 108(%rsp)
	xorl	%r8d, %r8d
	movq	24(%rsp), %r9
	movq	%rax, 64(%rsp)
	movq	8(%rbp), %rax
	movq	%rax, 72(%rsp)
	movq	16(%rbp), %rax
	movq	%rax, 16(%rsp)
	movq	(%r14), %rax
	movq	8(%rax), %rcx
	movq	16(%rax), %r13
	movq	24(%rax), %rbp
	movq	8(%r14), %rax
	movq	%rcx, 48(%rsp)
	movq	16(%rax), %rsi
	movq	8(%rax), %rcx
	movq	24(%rax), %r12
	movq	16(%r14), %rax
	movq	%rcx, 56(%rsp)
	movq	(%rax), %rdx
	movq	8(%rax), %rcx
	movq	%rsi, 8(%rsp)
	movq	16(%rax), %r14
	movq	24(%rax), %r15
	movq	%rdx, 32(%rsp)
	movl	32(%rsp), %eax
	movl	$8388609, %edx
	movq	%rcx, 40(%rsp)
	movl	40(%rsp), %esi
	salq	$9, %rdx
	movl	$1, %ecx
	movq	%rdx, 100(%rsp)
	imull	%esi, %eax
	imull	%r14d, %eax
	imull	%r15d, %eax
	cltq
	movq	%rax, (%rsp)
	shrq	$9, %rax
	incl	%eax
	movl	%eax, 88(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 92(%rsp)
	movq	88(%rsp), %rdi
	movl	96(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z41__device_stub__Z20Resample2dInitKernelmPfmPf
.L20:
	movq	(%rsp), %rax
	movl	$8388609, %edx
	movq	24(%rsp), %r9
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, 108(%rsp)
	addq	$511, %rax
	movq	%rdx, 100(%rsp)
	shrq	$9, %rax
	movl	%eax, 88(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 92(%rsp)
	movq	88(%rsp), %rdi
	movl	96(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movl	48(%rsp), %r8d
	pushq	$1
	.cfi_def_cfa_offset 184
	movl	%r13d, %r9d
	pushq	$1
	.cfi_def_cfa_offset 192
	imull	%ebp, %r9d
	pushq	%r15
	.cfi_def_cfa_offset 200
	imull	%r13d, %r8d
	pushq	%r14
	.cfi_def_cfa_offset 208
	movl	72(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 216
	movl	72(%rsp), %eax
	imull	%ebp, %r8d
	pushq	%rax
	.cfi_def_cfa_offset 224
	pushq	%r12
	.cfi_def_cfa_offset 232
	movl	64(%rsp), %eax
	imull	%r12d, %eax
	pushq	%rax
	.cfi_def_cfa_offset 240
	movl	120(%rsp), %edi
	movl	72(%rsp), %eax
	imull	%edi, %eax
	imull	%r12d, %eax
	pushq	%rax
	.cfi_def_cfa_offset 248
	pushq	%rbp
	.cfi_def_cfa_offset 256
	movq	96(%rsp), %rcx
	movq	152(%rsp), %rdx
	movq	144(%rsp), %rsi
	movq	80(%rsp), %rdi
	call	_Z55__device_stub__Z16Resample2dKernelmPKfS0_PfiiiiiiiiiiibmPKfS0_Pfiiiiiiiiiiib
	addq	$80, %rsp
	.cfi_def_cfa_offset 176
	jmp	.L17
.L23:
	movl	$2, %ebx
.L17:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	movl	%ebx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2291:
	.size	Resample2d, .-Resample2d
	.globl	_Z78__device_stub__Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiibmPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.type	_Z78__device_stub__Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiibmPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, @function
_Z78__device_stub__Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiibmPKfiiiiS0_iiiS0_iiiiiiiPfiiiib:
.LFB2321:
	.cfi_startproc
	endbr64
	subq	$344, %rsp
	.cfi_def_cfa_offset 352
	movq	352(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	384(%rsp), %rax
	movl	%edx, 44(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	448(%rsp), %rax
	movl	%ecx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movl	488(%rsp), %eax
	movl	%r8d, 36(%rsp)
	movl	%r9d, 32(%rsp)
	movb	%al, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 328(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	416(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	424(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	432(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	472(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	480(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 320(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	80(%rsp)
	.cfi_def_cfa_offset 360
	leaq	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 368
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 360
	popq	%rdx
	.cfi_def_cfa_offset 352
.L26:
	movq	328(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$344, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2321:
	.size	_Z78__device_stub__Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiibmPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, .-_Z78__device_stub__Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiibmPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.globl	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.type	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, @function
_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib:
.LFB2322:
	.cfi_startproc
	endbr64
	movzbl	144(%rsp), %eax
	movl	%eax, 144(%rsp)
	jmp	_Z78__device_stub__Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiibmPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.cfi_endproc
.LFE2322:
	.size	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, .-_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.globl	_Z78__device_stub__Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiibmPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.type	_Z78__device_stub__Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiibmPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, @function
_Z78__device_stub__Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiibmPKfiiiS0_iiiS0_iiiiPfiiiiiiiib:
.LFB2323:
	.cfi_startproc
	endbr64
	subq	$344, %rsp
	.cfi_def_cfa_offset 352
	movq	376(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	416(%rsp), %rax
	movl	%edx, 44(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movl	488(%rsp), %eax
	movl	%ecx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 36(%rsp)
	movq	%r9, 24(%rsp)
	movb	%al, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 328(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	424(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	432(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	448(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	472(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	480(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 320(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	80(%rsp)
	.cfi_def_cfa_offset 360
	leaq	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 368
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 360
	popq	%rdx
	.cfi_def_cfa_offset 352
.L31:
	movq	328(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$344, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2323:
	.size	_Z78__device_stub__Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiibmPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, .-_Z78__device_stub__Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiibmPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.globl	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.type	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, @function
_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib:
.LFB2324:
	.cfi_startproc
	endbr64
	movzbl	144(%rsp), %eax
	movl	%eax, 144(%rsp)
	jmp	_Z78__device_stub__Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiibmPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.cfi_endproc
.LFE2324:
	.size	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, .-_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.globl	Resample2dGrad
	.type	Resample2dGrad, @function
Resample2dGrad:
.LFB2292:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	movq	%r9, 16(%rsp)
	movl	$1, 12(%rsp)
	cmpl	$5, %edi
	jne	.L36
	movq	%rsi, %rbx
	movq	%rcx, %r13
	movq	%r8, %r14
	xorl	%ebp, %ebp
	leaq	.LC0(%rip), %r12
.L38:
	movq	(%r14,%rbp,8), %rdi
	movq	%r12, %rsi
	call	strcmp@PLT
	movl	%eax, 12(%rsp)
	testl	%eax, %eax
	jne	.L44
	incq	%rbp
	cmpq	$5, %rbp
	jne	.L38
	movq	(%rbx), %rax
	xorl	%r8d, %r8d
	movq	%rax, 56(%rsp)
	movq	8(%rbx), %rax
	movq	%rax, 64(%rsp)
	movq	16(%rbx), %rax
	movq	%rax, 72(%rsp)
	movq	24(%rbx), %rax
	movq	%rax, 80(%rsp)
	movq	32(%rbx), %rax
	movq	%rax, 88(%rsp)
	movq	0(%r13), %rax
	movq	(%rax), %rdx
	movq	8(%rax), %rbx
	movq	24(%rax), %r12
	movq	16(%rax), %rcx
	movq	8(%r13), %rax
	movl	%edx, 128(%rsp)
	movq	%rcx, 24(%rsp)
	movq	(%rax), %rcx
	movq	8(%rax), %rsi
	movl	%ebx, 132(%rsp)
	movq	24(%rax), %rbp
	movq	%rcx, 112(%rsp)
	movq	16(%rax), %rcx
	movq	16(%r13), %rax
	movq	%rsi, 48(%rsp)
	movq	%rcx, 32(%rsp)
	movl	$1, %ecx
	movq	(%rax), %rsi
	movq	16(%rax), %r15
	movq	24(%rax), %r13
	movq	8(%rax), %r14
	movq	%rsi, 120(%rsp)
	movl	24(%rsp), %eax
	movl	32(%rsp), %edi
	movq	16(%rsp), %r9
	movl	$1, 172(%rsp)
	imull	%ebx, %eax
	imull	%edx, %ebx
	movl	$8388609, %edx
	salq	$9, %rdx
	imull	%r12d, %eax
	movq	%rdx, 164(%rsp)
	movl	%eax, 96(%rsp)
	movl	24(%rsp), %eax
	imull	%r12d, %eax
	movl	%eax, 100(%rsp)
	movl	48(%rsp), %eax
	imull	%edi, %eax
	imull	%ebp, %eax
	movl	%eax, 40(%rsp)
	movl	%edi, %eax
	imull	%ebp, %eax
	movl	%eax, 44(%rsp)
	movl	%r15d, %eax
	imull	%r14d, %eax
	imull	%r13d, %eax
	movl	%eax, 104(%rsp)
	movl	%r13d, %eax
	imull	%r15d, %eax
	movl	%eax, 108(%rsp)
	movl	24(%rsp), %eax
	imull	%eax, %ebx
	imull	%r12d, %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rax
	shrq	$9, %rax
	incl	%eax
	movl	%eax, 152(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 156(%rsp)
	movq	152(%rsp), %rdi
	movl	160(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	80(%rsp), %rsi
	movq	%rbx, %rdi
	call	_Z41__device_stub__Z20Resample2dInitKernelmPfmPf
.L39:
	movl	112(%rsp), %ecx
	movl	48(%rsp), %eax
	movl	$8388609, %edx
	xorl	%r8d, %r8d
	movl	32(%rsp), %esi
	movq	16(%rsp), %r9
	salq	$9, %rdx
	movl	$1, 172(%rsp)
	imull	%ecx, %eax
	movl	$1, %ecx
	movq	%rdx, 164(%rsp)
	imull	%esi, %eax
	imull	%ebp, %eax
	movslq	%eax, %rbx
	movq	%rbx, %rax
	shrq	$9, %rax
	incl	%eax
	movl	%eax, 152(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 156(%rsp)
	movq	152(%rsp), %rdi
	movl	160(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	88(%rsp), %rsi
	movq	%rbx, %rdi
	call	_Z41__device_stub__Z20Resample2dInitKernelmPfmPf
.L40:
	movl	120(%rsp), %r10d
	movq	16(%rsp), %r9
	movl	$8388609, %edx
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, 172(%rsp)
	imull	%r14d, %r10d
	movq	%rdx, 164(%rsp)
	imull	%r15d, %r10d
	imull	%r13d, %r10d
	movslq	%r10d, %r10
	leaq	511(%r10), %rax
	movq	%r10, 136(%rsp)
	shrq	$9, %rax
	movl	%eax, 152(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 156(%rsp)
	movq	152(%rsp), %rdi
	movl	160(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movq	136(%rsp), %r10
	testl	%eax, %eax
	jne	.L41
	pushq	$1
	.cfi_def_cfa_offset 248
	movl	%r12d, %r9d
	movq	%r10, %rdi
	pushq	$1
	.cfi_def_cfa_offset 256
	pushq	%r12
	.cfi_def_cfa_offset 264
	movl	124(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 272
	movl	128(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 280
	pushq	120(%rsp)
	.cfi_def_cfa_offset 288
	pushq	%r13
	.cfi_def_cfa_offset 296
	movl	164(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 304
	movl	168(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 312
	pushq	%r13
	.cfi_def_cfa_offset 320
	pushq	%r15
	.cfi_def_cfa_offset 328
	pushq	%r14
	.cfi_def_cfa_offset 336
	movl	216(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 344
	pushq	176(%rsp)
	.cfi_def_cfa_offset 352
	pushq	%rbp
	.cfi_def_cfa_offset 360
	movl	164(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 368
	movl	168(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 376
	pushq	200(%rsp)
	.cfi_def_cfa_offset 384
	movl	168(%rsp), %r8d
	movl	276(%rsp), %ecx
	movl	272(%rsp), %edx
	movq	200(%rsp), %rsi
	call	_Z78__device_stub__Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiibmPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	addq	$144, %rsp
	.cfi_def_cfa_offset 240
.L41:
	leaq	511(%rbx), %rax
	movl	$8388609, %edx
	movq	16(%rsp), %r9
	xorl	%r8d, %r8d
	shrq	$9, %rax
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, 172(%rsp)
	movl	%eax, 152(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 156(%rsp)
	movq	152(%rsp), %rdi
	movl	160(%rsp), %esi
	movq	%rdx, 164(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	$1
	.cfi_def_cfa_offset 248
	movl	%r12d, %r8d
	movq	%rbx, %rdi
	pushq	$1
	.cfi_def_cfa_offset 256
	pushq	%rbp
	.cfi_def_cfa_offset 264
	movl	68(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 272
	movl	72(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 280
	pushq	%rbp
	.cfi_def_cfa_offset 288
	movl	80(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 296
	movl	104(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 304
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 312
	pushq	160(%rsp)
	.cfi_def_cfa_offset 320
	pushq	%r13
	.cfi_def_cfa_offset 328
	movl	196(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 336
	movl	200(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 344
	pushq	%r14
	.cfi_def_cfa_offset 352
	pushq	184(%rsp)
	.cfi_def_cfa_offset 360
	pushq	%rbp
	.cfi_def_cfa_offset 368
	movl	172(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 376
	movl	176(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 384
	movq	208(%rsp), %r9
	movl	244(%rsp), %ecx
	movl	240(%rsp), %edx
	movq	200(%rsp), %rsi
	call	_Z78__device_stub__Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiibmPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	addq	$144, %rsp
	.cfi_def_cfa_offset 240
	jmp	.L36
.L44:
	movl	$2, 12(%rsp)
.L36:
	movl	12(%rsp), %eax
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2292:
	.size	Resample2dGrad, .-Resample2dGrad
	.section	.rodata.str1.1
.LC1:
	.string	"_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib"
.LC2:
	.string	"_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib"
.LC3:
	.string	"_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib"
.LC4:
	.string	"_Z20Resample2dInitKernelmPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2326:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20Resample2dInitKernelmPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2326:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Copyright 2022 Huawei Technologies Co., Ltd
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ============================================================================
#define CUDA_NUM_THREADS 512
#define THREADS_PER_BLOCK 64


#include <hip/hip_runtime.h>
#include <algorithm>

__device__ __forceinline__ float MsAtomicAdd(float *address, const float val) {
  return atomicAdd(address, val);
}

__global__ void Resample2dInitKernel(size_t size_init, float *input) {
  auto idx = blockIdx.x * CUDA_NUM_THREADS + threadIdx.x;
  if (idx < size_init) {
     input[idx] = static_cast<float>(.0);
  }
}


__device__ int GET_INDEX(const int batch , const int channels, const int height, const int width,
                        const int batch_stride , const int channels_stride, const int height_stride) {
     return batch*batch_stride+channels*channels_stride+height*height_stride+width;
}

__device__ float DIM3_INDEX(const float *input, const int batch , const int channels, const int height, const int width,
                        const int batch_stride , const int channels_stride, const int height_stride) {
    return input[batch*batch_stride+channels*channels_stride+height*height_stride+width];
}


__global__ void Resample2dKernel(size_t size, const float *input1, const float *input2, float *out_data,
                    int batch_stride_x1, int channel_stride_x1, int height_stride_x1,
                    int batch_stride_x2, int channel_stride_x2, int height_stride_x2,
                    int batch_output, int channel_output, int height_output, int width_output,
                    int kernel_size, bool bilinear) {
    int index = blockIdx.x * blockDim.x + threadIdx.x;

    if (index >= size) {
        return;
    }

    float val = 0.0;

    int dim_b = batch_output;
    int dim_c = channel_output;
    int dim_h = height_output;
    int dim_w = width_output;
    int dim_chw = dim_c * dim_h * dim_w;
    int dim_hw  = dim_h * dim_w;
    int b = (index / dim_chw) % dim_b;
    int c = (index / dim_hw) % dim_c;
    int y = (index / dim_w) % dim_h;
    int x = (index) % dim_w;

    float dx = DIM3_INDEX(input2, b, 0, y, x, batch_stride_x2, channel_stride_x2, height_stride_x2);
    float dy = DIM3_INDEX(input2, b, 1, y, x, batch_stride_x2, channel_stride_x2, height_stride_x2);

    float xf = x + dx;
    float yf = y + dy;  // img+flow
    float alpha = xf - (floor(xf));  // alpha
    float beta = yf - (floor(yf));  // beta
    if (bilinear) {
        int xL = max(min(static_cast<int>(floor(xf)),    dim_w-1), 0);
        int xR = max(min(static_cast<int>(floor(xf)+1), dim_w -1), 0);
        int yT = max(min(static_cast<int>(floor(yf)),    dim_h-1), 0);
        int yB = max(min(static_cast<int>(floor(yf)+1),  dim_h-1), 0);
        for (int fy = 0; fy < kernel_size; fy += 1) {
            for (int fx = 0; fx < kernel_size; fx += 1) {
                float offTL = DIM3_INDEX(input1, b, c, yT + fy, xL + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                float offTR = DIM3_INDEX(input1, b, c, yT + fy, xR + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                float offBL = DIM3_INDEX(input1, b, c, yB + fy, xL + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                float offBR = DIM3_INDEX(input1, b, c, yB + fy, xR + fx,
                                    batch_stride_x1, channel_stride_x1, height_stride_x1);
                val += (1. - alpha)*(1. - beta) *  offTL;
                val += (alpha)*(1. - beta) * offTR;
                val += (1. - alpha)*(beta) * offBL;
                val += (alpha)*(beta) * offBR;
            }
        }
        out_data[index] = val;
    } else {
        int xN = max(min(static_cast<int>(floor(xf + 0.5)), dim_w - 1), 0);
        int yN = max(min(static_cast<int>(floor(yf + 0.5)), dim_h - 1), 0);
        out_data[index] = DIM3_INDEX(input1, b, c, yN, xN, batch_stride_x1, channel_stride_x1, height_stride_x1);
    }
}



extern "C" int Resample2d(int nparam, void **params, int *ndims, int64_t **shapes, const char **dtypes, void *stream,
                         void *extra) {
    hipStream_t custream = static_cast<hipStream_t>(stream);
    constexpr int INPUT1_INDEX = 0;
    constexpr int INPUT2_INDEX = 1;
    constexpr int OUTPUT_INDEX = 2;
    constexpr int TOTAL_PARAM_NUM = 3;

    if (nparam != TOTAL_PARAM_NUM) {
    return 1;
    }
    // This is to check if the type of parameters the same as what the user wants.
    for (int i = 0; i < nparam; i++) {
        if (strcmp(dtypes[i], "float32") != 0) {
            return 2;
        }
    }

    float *x1 = static_cast<float *>(params[0]);
    float *x2 = static_cast<float *>(params[1]);

    float *out_data = static_cast<float *>(params[2]);

//     int batch_x1 = shapes[INPUT1_INDEX][0];
    int channel_x1 = shapes[INPUT1_INDEX][1];
    int height_x1 = shapes[INPUT1_INDEX][2];
    int width_x1 = shapes[INPUT1_INDEX][3];

//     int batch_x2 = shapes[INPUT2_INDEX][0];
    int channel_x2 = shapes[INPUT2_INDEX][1];
    int height_x2 = shapes[INPUT2_INDEX][2];
    int width_x2 = shapes[INPUT2_INDEX][3];

    int batch_output = shapes[OUTPUT_INDEX][0];
    int channel_output = shapes[OUTPUT_INDEX][1];
    int height_output = shapes[OUTPUT_INDEX][2];
    int width_output = shapes[OUTPUT_INDEX][3];

    // fix at now ,need to be changed in future
    const int kernel_size = 1;
    const bool bilinear = true;

    int batch_stride_x1  = channel_x1 * height_x1 * width_x1;
    int channel_stride_x1  = height_x1 * width_x1;
    int height_stride_x1 = width_x1;
    int batch_stride_x2 = channel_x2 * height_x2 * width_x2;
    int channel_stride_x2  = height_x2 * width_x2;
    int height_stride_x2  = width_x2;
    size_t size = batch_output * channel_output * height_output * width_output;
    Resample2dInitKernel<<<size / CUDA_NUM_THREADS +1, CUDA_NUM_THREADS, 0, custream>>>(size, out_data);

    Resample2dKernel<<< (size + CUDA_NUM_THREADS - 1)/CUDA_NUM_THREADS, CUDA_NUM_THREADS, 0, custream>>>
                   (size, x1, x2, out_data, batch_stride_x1, channel_stride_x1, height_stride_x1,
                   batch_stride_x2, channel_stride_x2, height_stride_x2, batch_output, channel_output,
                    height_output, width_output, kernel_size , bilinear);
    return 0;
}


__global__ void kernel_resample2d_grad_input1(size_t size,
    const float* input1, int batch_input1, int channel_input1, int height_input1, int width_input1,
    const float* input2, int batch_stride_input2, int channel_stride_input2, int height_stride_input2,
    const float* gradOutput, int batch_gradOutput, int channel_gradOutput, int height_gradOutput, int width_gradOutput,
    int batch_stride_gradOutput, int channel_stride_gradOutput, int height_stride_gradOutput,
    float* gradInput, int batch_stride_gradInput, int channel_stride_gradInput, int height_stride_gradInput,
    int kernel_size, bool bilinear) {

    int index = blockIdx.x * blockDim.x + threadIdx.x;

    if (index >= size) {
        return;
    }

    int dim_b = batch_gradOutput;
    int dim_c = channel_gradOutput;
    int dim_h = height_gradOutput;
    int dim_w = width_gradOutput;
    int dim_chw = dim_c * dim_h * dim_w;
    int dim_hw  = dim_h * dim_w;

    int b = (index / dim_chw) % dim_b;
    int c = (index / dim_hw)  % dim_c;
    int y = (index / dim_w)   % dim_h;
    int x = (index)  % dim_w;

    float dx = DIM3_INDEX(input2, b, 0, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);
    float dy = DIM3_INDEX(input2, b, 1, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);

    float xf = x + dx;
    float yf = y + dy;
    float alpha = xf - static_cast<int>(xf);  // alpha
    float beta = yf - static_cast<int>(yf);  // beta

    int idim_h = height_input1;
    int idim_w = width_input1;

    int xL = max(min(static_cast<int>(floor(xf)),    idim_w-1), 0);
    int xR = max(min(static_cast<int>(floor(xf)+1), idim_w -1), 0);
    int yT = max(min(static_cast<int>(floor(yf)),    idim_h-1), 0);
    int yB = max(min(static_cast<int>(floor(yf)+1),  idim_h-1), 0);

    float w1, w2, w3, w4;
    float num = 1.f;
    w1 = (num-alpha)*(num-beta);
    w2 = (alpha)*(num-beta);
    w3 = (num-alpha)*(beta);
    w4 = (alpha)*(beta);

    float gradnum = DIM3_INDEX(gradOutput, b, c, y, x,
            batch_stride_gradOutput, channel_stride_gradOutput, height_stride_gradOutput);
    for (int fy = 0; fy < kernel_size; fy += 1) {
        for (int fx = 0; fx < kernel_size; fx += 1) {
            int indexTL = GET_INDEX(b, c, (yT + fy), (xL + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexTL], w1 * gradnum);

            int indexTR = GET_INDEX(b, c, (yT + fy), (xR + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexTR], w2 * gradnum);

            int indexBL = GET_INDEX(b, c, (yB + fy), (xL + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexBL], w3 * gradnum);

            int indexBR = GET_INDEX(b, c, (yB + fy), (xR + fx),
                        batch_stride_gradInput, channel_stride_gradInput, height_stride_gradInput);
            MsAtomicAdd(&gradInput[indexBR], w4 * gradnum);
        }
    }
}


__global__ void kernel_resample2d_grad_input2(size_t size,
    const float  *input1, int batch_stride_input1, int channel_stride_input1, int height_stride_input1,
    const float  *input2, int batch_stride_input2, int channel_stride_input2, int height_stride_input2,
    const float  *gradOutput, int channel_gradOutput, int batch_stride_gradOutput,
    int channel_stride_gradOutput, int height_stride_gradOutput,
    float  *gradInput, int batch_gradInput, int channel_gradInput, int height_gradInput, int width_gradInput,
    int batch_stride_gradInput, int channel_stride_gradInput, int height_stride_gradInput,
    int kernel_size, bool bilinear) {
    int index = blockIdx.x * blockDim.x + threadIdx.x;

    if (index >= size) {
        return;
    }

    float output = 0.0;
    int kernel_rad = (kernel_size - 1)/2;

    int dim_b = batch_gradInput;
    int dim_c = channel_gradInput;
    int dim_h = height_gradInput;
    int dim_w = width_gradInput;
    int dim_chw = dim_c * dim_h * dim_w;
    int dim_hw  = dim_h * dim_w;

    int b = (index / dim_chw) % dim_b;
    int c = (index / dim_hw)  % dim_c;
    int y = (index / dim_w)   % dim_h;
    int x = (index)  % dim_w;

    int odim_c = channel_gradOutput;

    float dx = DIM3_INDEX(input2, b, 0, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);
    float dy = DIM3_INDEX(input2, b, 1, y, x, batch_stride_input2, channel_stride_input2, height_stride_input2);

    float xf = x + dx;
    float yf = y + dy;

    int xL = max(min(static_cast<int>(floor(xf)),    dim_w-1), 0);
    int xR = max(min(static_cast<int>(floor(xf)+1), dim_w -1), 0);
    int yT = max(min(static_cast<int>(floor(yf)),    dim_h-1), 0);
    int yB = max(min(static_cast<int>(floor(yf)+1),  dim_h-1), 0);

    if (c % 2) {
        float gamma = 1 - (xf - floor(xf));  // alpha
        for (int i = 0; i <= 2*kernel_rad ; ++i) {
            for (int j = 0; j <= 2*kernel_rad; ++j) {
                for (int ch = 0; ch < odim_c; ++ch) {
                    float gradout = DIM3_INDEX(gradOutput, b, ch, y, x,
                     batch_stride_gradOutput, channel_stride_gradOutput, height_stride_gradOutput);
                    output += (gamma) * gradout * DIM3_INDEX(input1, b, ch, (yB + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                    output -= (gamma) * gradout * DIM3_INDEX(input1, b, ch, (yT + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                    output += (1-gamma) * gradout * DIM3_INDEX(input1, b, ch, (yB + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                    output -= (1-gamma) * gradout * DIM3_INDEX(input1, b, ch, (yT + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1);
                }
            }
        }
    } else {
        float gamma = 1 - (yf - floor(yf));  // alpha
        for (int i = 0; i <= 2*kernel_rad; ++i) {
            for (int j = 0; j <= 2*kernel_rad; ++j) {
                for (int ch = 0; ch < odim_c; ++ch) {
                    float gradout = static_cast<float>(DIM3_INDEX(gradOutput, b, ch, y, x,
                                batch_stride_gradOutput, channel_stride_gradOutput, height_stride_gradOutput));
                    output += (gamma) * gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yT + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                    output -= (gamma)* gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yT + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                    output += (1-gamma)* gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yB + j), (xR + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                    output -= (1-gamma) * gradout * static_cast<float>(DIM3_INDEX(input1, b, ch, (yB + j), (xL + i),
                                batch_stride_input1, channel_stride_input1, height_stride_input1));
                }
            }
        }
    }
    gradInput[index] = output;
}


extern "C" int Resample2dGrad(int nparam, void **params, int *ndims, int64_t **shapes, const char **dtypes,
                              void *stream, void *extra) {
    hipStream_t custream = static_cast<hipStream_t>(stream);
    constexpr int INPUT1_INDEX = 0;
    constexpr int INPUT2_INDEX = 1;
    constexpr int GRAD_OUTPUT_INDEX = 2;
    constexpr int TOTAL_PARAM_NUM = 5;

    if (nparam != TOTAL_PARAM_NUM) {
        return 1;
    }
    // This is to check if the type of parameters the same as what the user wants.
    for (int i = 0; i < nparam; i++) {
        if (strcmp(dtypes[i], "float32") != 0) {
            return 2;
        }
    }

    float *x1 = static_cast<float *>(params[0]);
    float *x2 = static_cast<float *>(params[1]);
    float *dout = static_cast<float *>(params[2]);
    float *dx1 = static_cast<float *>(params[3]);
    float *dx2 = static_cast<float *>(params[4]);

    int batch_x1 = shapes[INPUT1_INDEX][0];
    int channel_x1 = shapes[INPUT1_INDEX][1];
    int height_x1 = shapes[INPUT1_INDEX][2];
    int width_x1 = shapes[INPUT1_INDEX][3];

    int batch_x2 = shapes[INPUT2_INDEX][0];
    int channel_x2 = shapes[INPUT2_INDEX][1];
    int height_x2 = shapes[INPUT2_INDEX][2];
    int width_x2 = shapes[INPUT2_INDEX][3];

    int batch_dout = shapes[GRAD_OUTPUT_INDEX][0];
    int channel_dout = shapes[GRAD_OUTPUT_INDEX][1];
    int height_dout = shapes[GRAD_OUTPUT_INDEX][2];
    int width_dout = shapes[GRAD_OUTPUT_INDEX][3];

    // fix at now ,need to be changed in future
    const int kernel_size = 1;
    const bool bilinear = true;

    int batch_dx1  = batch_x1;
    int channel_dx1  = channel_x1;
    int height_dx1  = height_x1;
    int width_dx1 = width_x1;
    int batch_dx2  = batch_x2;
    int channel_dx2 = channel_x2;
    int height_dx2 = height_x2;
    int width_dx2 = width_x2;
    int batch_stride_x1  = channel_x1 * height_x1 * width_x1;
    int channel_stride_x1  = height_x1 * width_x1;
    int height_stride_x1  = width_x1;
//     int width_stride_x1 = 1;
    int batch_stride_x2  = channel_x2 * height_x2 * width_x2;
    int channel_stride_x2  = height_x2 * width_x2;
    int height_stride_x2 = width_x2;
//     int width_stride_x2 = 1;
    int batch_stride_dx1  = batch_stride_x1;
    int channel_stride_dx1 = channel_stride_x1;
    int height_stride_dx1 = height_stride_x1;
//     int width_stride_dx1 = width_stride_x1;
    int batch_stride_dx2  = batch_stride_x2;
    int channel_stride_dx2 = channel_stride_x2;
    int height_stride_dx2 = height_stride_x2;
//     int width_stride_dx2 = width_stride_x2;
    int batch_stride_dout  = channel_dout * height_dout * width_dout;
    int channel_stride_dout  = height_dout * width_dout;
    int height_stride_dout  = width_dout;
//     int width_stride_dout  = 1;

    size_t dx1_size = batch_dx1 * channel_dx1 * height_dx1 * width_dx1;

    Resample2dInitKernel<<<dx1_size / CUDA_NUM_THREADS +1, CUDA_NUM_THREADS, 0, custream>>>(dx1_size, dx1);
    size_t dx2_size = batch_dx2 * channel_dx2 * height_dx2 * width_dx2;
    Resample2dInitKernel<<<dx2_size / CUDA_NUM_THREADS +1, CUDA_NUM_THREADS, 0, custream>>>(dx2_size, dx2);

    size_t dout_size = batch_dout * channel_dout * height_dout * width_dout;

    kernel_resample2d_grad_input1<<<(dout_size + CUDA_NUM_THREADS - 1)/CUDA_NUM_THREADS, CUDA_NUM_THREADS,
                                     0, custream>>>(dout_size,
                                     x1, batch_x1, channel_x1, height_x1, width_x1,
                                     x2, batch_stride_x2, channel_stride_x2, height_stride_x2,
                                     dout, batch_dout, channel_dout, height_dout, width_dout,
                                     batch_stride_dout, channel_stride_dout, height_stride_dout,
                                     dx1, batch_stride_dx1, channel_stride_dx1, height_stride_dx1,
                                     kernel_size, bilinear);

    kernel_resample2d_grad_input2<<<(dx2_size + CUDA_NUM_THREADS - 1)/CUDA_NUM_THREADS, CUDA_NUM_THREADS,
                                    0, custream>>>(dx2_size,
                                     x1, batch_stride_x1, channel_stride_x1, height_stride_x1,
                                     x2, batch_stride_x2, channel_stride_x2, height_stride_x2,
                                     dout, channel_dout, batch_stride_dout, channel_stride_dout, height_stride_dout,
                                     dx2, batch_dx2, channel_dx2, height_dx2, width_dx2,
                                     batch_stride_dx2, channel_stride_dx2, height_stride_dx2,
                                     kernel_size, bilinear);
    return 0;
}

	.text
	.file	"resample2d.hip"
	.globl	_Z35__device_stub__Resample2dInitKernelmPf # -- Begin function _Z35__device_stub__Resample2dInitKernelmPf
	.type	_Z35__device_stub__Resample2dInitKernelmPf,@function
_Z35__device_stub__Resample2dInitKernelmPf: # @_Z35__device_stub__Resample2dInitKernelmPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20Resample2dInitKernelmPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__Resample2dInitKernelmPf, .Lfunc_end0-_Z35__device_stub__Resample2dInitKernelmPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib # -- Begin function _Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.type	_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib,@function
_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib: # @_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	344(%rsp), %al
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	7(%rsp), %r9
	movb	%al, (%r9)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	movq	%r9, 120(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib, .Lfunc_end1-_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.cfi_endproc
                                        # -- End function
	.globl	Resample2d                      # -- Begin function Resample2d
	.type	Resample2d,@function
Resample2d:                             # @Resample2d
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1, %r14d
	cmpl	$3, %edi
	jne	.LBB2_9
# %bb.1:                                # %.preheader.preheader
	movq	%r9, %rbx
	movq	%r8, %r13
	movq	%rcx, %r15
	movq	%rsi, %r12
	xorl	%r14d, %r14d
.LBB2_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	(%r13,%r14,8), %rdi
	movl	$.L.str, %esi
	callq	strcmp
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.2:                                #   in Loop: Header=BB2_3 Depth=1
	incq	%r14
	cmpq	$3, %r14
	jne	.LBB2_3
# %bb.5:                                # %.critedge
	movq	(%r12), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	16(%r12), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	(%r15), %rax
	movq	8(%r15), %rcx
	movl	24(%rax), %esi
	movl	24(%rcx), %edi
	movq	16(%r15), %rdx
	movl	(%rdx), %r8d
	movl	8(%rdx), %r9d
	movl	16(%rdx), %r10d
	movl	24(%rdx), %edx
	movl	16(%rax), %ebp
	movq	%rsi, 80(%rsp)                  # 8-byte Spill
	imull	%esi, %ebp
	movl	8(%rax), %eax
	imull	%ebp, %eax
	movl	%eax, 4(%rsp)                   # 4-byte Spill
	movl	16(%rcx), %r15d
	movq	%rdi, 72(%rsp)                  # 8-byte Spill
	imull	%edi, %r15d
	movl	8(%rcx), %eax
	imull	%r15d, %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	%r8, 64(%rsp)                   # 8-byte Spill
	movl	%r8d, %eax
	movq	%r9, 56(%rsp)                   # 8-byte Spill
	imull	%r9d, %eax
	movq	%r10, 40(%rsp)                  # 8-byte Spill
	movl	%r10d, %ecx
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	imull	%edx, %ecx
	imull	%eax, %ecx
	movslq	%ecx, %r12
	movq	%r12, %rdi
	shrq	$9, %rdi
	incl	%edi
	btsq	$32, %rdi
	movabsq	$4294967296, %r13               # imm = 0x100000000
	leaq	512(%r13), %rdx
	xorl	%r14d, %r14d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rbx, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.6:
	movq	%r12, %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	callq	_Z35__device_stub__Resample2dInitKernelmPf
.LBB2_7:
	leaq	511(%r12), %rax
	shrq	$9, %rax
	movl	%eax, %edi
	orq	%r13, %rdi
	addq	$512, %r13                      # imm = 0x200
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rbx, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_9
# %bb.8:
	movq	%r12, %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movq	8(%rsp), %rcx                   # 8-byte Reload
	movl	4(%rsp), %r8d                   # 4-byte Reload
	movl	%ebp, %r9d
	movl	$1, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	jmp	.LBB2_9
.LBB2_4:
	movl	$2, %r14d
.LBB2_9:                                # %.loopexit
	movl	%r14d, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	Resample2d, .Lfunc_end2-Resample2d
	.cfi_endproc
                                        # -- End function
	.globl	_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib # -- Begin function _Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.type	_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib,@function
_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib: # @_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$288, %rsp                      # imm = 0x120
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	472(%rsp), %r10b
	leaq	56(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	28(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	20(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	16(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	15(%rsp), %rax
	movb	%r10b, (%rax)
	leaq	96(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	336(%rsp), %rcx
	movq	%rcx, 48(%rbx)
	leaq	344(%rsp), %rcx
	movq	%rcx, 56(%rbx)
	leaq	352(%rsp), %rcx
	movq	%rcx, 64(%rbx)
	leaq	360(%rsp), %rcx
	movq	%rcx, 72(%rbx)
	leaq	368(%rsp), %rcx
	movq	%rcx, 80(%rbx)
	leaq	376(%rsp), %rcx
	movq	%rcx, 88(%rbx)
	leaq	384(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	392(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	leaq	400(%rsp), %rcx
	movq	%rcx, 112(%rbx)
	leaq	408(%rsp), %rcx
	movq	%rcx, 120(%rbx)
	leaq	416(%rsp), %rcx
	movq	%rcx, 128(%rbx)
	leaq	424(%rsp), %rcx
	movq	%rcx, 136(%rbx)
	leaq	432(%rsp), %rcx
	movq	%rcx, 144(%rbx)
	leaq	440(%rsp), %rcx
	movq	%rcx, 152(%rbx)
	leaq	448(%rsp), %rcx
	movq	%rcx, 160(%rbx)
	leaq	456(%rsp), %rcx
	movq	%rcx, 168(%rbx)
	leaq	464(%rsp), %rcx
	movq	%rcx, 176(%rbx)
	movq	%rax, 184(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, .Lfunc_end3-_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.cfi_endproc
                                        # -- End function
	.globl	_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib # -- Begin function _Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.type	_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib,@function
_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib: # @_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$288, %rsp                      # imm = 0x120
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	472(%rsp), %r10b
	leaq	56(%rsp), %r11
	movq	%rdi, (%r11)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	11(%rsp), %rax
	movb	%r10b, (%rax)
	leaq	96(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	336(%rsp), %rcx
	movq	%rcx, 48(%rbx)
	leaq	344(%rsp), %rcx
	movq	%rcx, 56(%rbx)
	leaq	352(%rsp), %rcx
	movq	%rcx, 64(%rbx)
	leaq	360(%rsp), %rcx
	movq	%rcx, 72(%rbx)
	leaq	368(%rsp), %rcx
	movq	%rcx, 80(%rbx)
	leaq	376(%rsp), %rcx
	movq	%rcx, 88(%rbx)
	leaq	384(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	392(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	leaq	400(%rsp), %rcx
	movq	%rcx, 112(%rbx)
	leaq	408(%rsp), %rcx
	movq	%rcx, 120(%rbx)
	leaq	416(%rsp), %rcx
	movq	%rcx, 128(%rbx)
	leaq	424(%rsp), %rcx
	movq	%rcx, 136(%rbx)
	leaq	432(%rsp), %rcx
	movq	%rcx, 144(%rbx)
	leaq	440(%rsp), %rcx
	movq	%rcx, 152(%rbx)
	leaq	448(%rsp), %rcx
	movq	%rcx, 160(%rbx)
	leaq	456(%rsp), %rcx
	movq	%rcx, 168(%rbx)
	leaq	464(%rsp), %rcx
	movq	%rcx, 176(%rbx)
	movq	%rax, 184(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, .Lfunc_end4-_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.cfi_endproc
                                        # -- End function
	.globl	Resample2dGrad                  # -- Begin function Resample2dGrad
	.type	Resample2dGrad,@function
Resample2dGrad:                         # @Resample2dGrad
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1, %ebx
	cmpl	$5, %edi
	jne	.LBB5_13
# %bb.1:                                # %.preheader.preheader
	movq	%r9, %r14
	movq	%r8, %r13
	movq	%rcx, %r15
	movq	%rsi, %r12
	xorl	%ebx, %ebx
.LBB5_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	(%r13,%rbx,8), %rdi
	movl	$.L.str, %esi
	callq	strcmp
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.2:                                #   in Loop: Header=BB5_3 Depth=1
	incq	%rbx
	cmpq	$5, %rbx
	jne	.LBB5_3
# %bb.5:                                # %.critedge
	movq	(%r12), %rax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movq	16(%r12), %rax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movq	24(%r12), %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	32(%r12), %rax
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	movq	(%r15), %rax
	movq	8(%r15), %rcx
	movl	(%rax), %esi
	movl	8(%rax), %edi
	movl	16(%rax), %r8d
	movl	24(%rax), %edx
	movq	(%rcx), %rbp
	movq	8(%rcx), %r13
	movq	%r14, %r9
	movq	16(%rcx), %r14
	movq	24(%rcx), %r12
	movq	16(%r15), %rax
	movq	(%rax), %rcx
	movq	%rcx, 168(%rsp)                 # 8-byte Spill
	movq	8(%rax), %rcx
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movq	16(%rax), %rcx
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movq	24(%rax), %r15
	movq	%rdx, 88(%rsp)                  # 8-byte Spill
                                        # kill: def $edx killed $edx killed $rdx def $rdx
	movl	%r8d, 44(%rsp)                  # 4-byte Spill
	imull	%r8d, %edx
	movl	%esi, 48(%rsp)                  # 4-byte Spill
	movl	%esi, %eax
	movl	%edi, 52(%rsp)                  # 4-byte Spill
	imull	%edi, %eax
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	imull	%edx, %eax
	movslq	%eax, %rbx
	movq	%rbx, %rdi
	shrq	$9, %rdi
	incl	%edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	leaq	512(%rax), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%r9, (%rsp)                     # 8-byte Spill
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_7
# %bb.6:
	movq	%rbx, %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	callq	_Z35__device_stub__Resample2dInitKernelmPf
.LBB5_7:
	movl	%r12d, %ebx
	imull	%r14d, %ebx
	movq	%r15, 8(%rsp)                   # 8-byte Spill
                                        # kill: def $r15d killed $r15d killed $r15 def $r15
	imull	32(%rsp), %r15d                 # 4-byte Folded Reload
	movq	%rbp, 160(%rsp)                 # 8-byte Spill
	movl	%ebp, %eax
	imull	%r13d, %eax
	movq	%r12, 112(%rsp)                 # 8-byte Spill
	movl	%r12d, %ecx
	movq	%r14, 176(%rsp)                 # 8-byte Spill
	imull	%r14d, %ecx
	imull	%eax, %ecx
	movslq	%ecx, %rdi
	movq	%rdi, 128(%rsp)                 # 8-byte Spill
	shrq	$9, %rdi
	incl	%edi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	leaq	512(%rax), %rdx
	movl	$1, %esi
	movq	%rdx, 144(%rsp)                 # 8-byte Spill
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	(%rsp), %rbp                    # 8-byte Reload
	movq	%rbp, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	136(%rsp), %rsi                 # 8-byte Reload
	jne	.LBB5_9
# %bb.8:
	movq	128(%rsp), %rdi                 # 8-byte Reload
	callq	_Z35__device_stub__Resample2dInitKernelmPf
.LBB5_9:
	movq	16(%rsp), %rax                  # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax def $rax
	movl	52(%rsp), %r14d                 # 4-byte Reload
	imull	%r14d, %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	%rbx, (%rsp)                    # 8-byte Spill
                                        # kill: def $ebx killed $ebx killed $rbx def $rbx
	movq	%r13, 152(%rsp)                 # 8-byte Spill
	imull	%r13d, %ebx
	movq	%rbx, 80(%rsp)                  # 8-byte Spill
	movl	%r15d, %ecx
	movq	24(%rsp), %rax                  # 8-byte Reload
	imull	%eax, %ecx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
                                        # kill: def $eax killed $eax killed $rax
	movq	168(%rsp), %r13                 # 8-byte Reload
	imull	%r13d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	imull	32(%rsp), %ecx                  # 4-byte Folded Reload
	imull	%eax, %ecx
	movslq	%ecx, %r12
	leaq	511(%r12), %rax
	shrq	$9, %rax
	movl	%eax, %edi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	xorl	%ebx, %ebx
	movl	$1, %esi
	movq	144(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rbp, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_11
# %bb.10:
	movq	%r12, %rdi
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movl	48(%rsp), %edx                  # 4-byte Reload
	movl	%r14d, %ecx
	movl	44(%rsp), %r8d                  # 4-byte Reload
	movq	88(%rsp), %r9                   # 8-byte Reload
	movl	$1, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r9
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	movq	56(%rsp), %rax                  # 8-byte Reload
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	128(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	224(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	224(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	208(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	240(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
.LBB5_11:
	movq	128(%rsp), %r13                 # 8-byte Reload
	leaq	511(%r13), %rax
	shrq	$9, %rax
	movl	%eax, %edi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %r12d
	movl	$1, %esi
	movq	144(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rbp, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	176(%rsp), %r10                 # 8-byte Reload
	jne	.LBB5_13
# %bb.12:
	movq	%r13, %rdi
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movq	56(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movq	16(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movq	88(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	movq	104(%rsp), %r9                  # 8-byte Reload
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	movq	128(%rsp), %rax                 # 8-byte Reload
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movq	24(%rsp), %r11                  # 8-byte Reload
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	movq	112(%rsp), %r14                 # 8-byte Reload
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	208(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	224(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	208(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	128(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	232(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	callq	_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	jmp	.LBB5_13
.LBB5_4:
	movl	$2, %ebx
.LBB5_13:                               # %.loopexit
	movl	%ebx, %eax
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	Resample2dGrad, .Lfunc_end5-Resample2dGrad
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20Resample2dInitKernelmPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20Resample2dInitKernelmPf,@object # @_Z20Resample2dInitKernelmPf
	.section	.rodata,"a",@progbits
	.globl	_Z20Resample2dInitKernelmPf
	.p2align	3, 0x0
_Z20Resample2dInitKernelmPf:
	.quad	_Z35__device_stub__Resample2dInitKernelmPf
	.size	_Z20Resample2dInitKernelmPf, 8

	.type	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib,@object # @_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.globl	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.p2align	3, 0x0
_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib:
	.quad	_Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.size	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"float32"
	.size	.L.str, 8

	.type	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib,@object # @_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.section	.rodata,"a",@progbits
	.globl	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.p2align	3, 0x0
_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib:
	.quad	_Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.size	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, 8

	.type	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib,@object # @_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.globl	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.p2align	3, 0x0
_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib:
	.quad	_Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.size	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20Resample2dInitKernelmPf"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib"
	.size	.L__unnamed_2, 42

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib"
	.size	.L__unnamed_3, 65

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib"
	.size	.L__unnamed_4, 65

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__Resample2dInitKernelmPf
	.addrsig_sym _Z31__device_stub__Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.addrsig_sym _Z44__device_stub__kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.addrsig_sym _Z44__device_stub__kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20Resample2dInitKernelmPf
	.addrsig_sym _Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.addrsig_sym _Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.addrsig_sym _Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20Resample2dInitKernelmPf ; -- Begin function _Z20Resample2dInitKernelmPf
	.globl	_Z20Resample2dInitKernelmPf
	.p2align	8
	.type	_Z20Resample2dInitKernelmPf,@function
_Z20Resample2dInitKernelmPf:            ; @_Z20Resample2dInitKernelmPf
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v0, s15, 9, v0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20Resample2dInitKernelmPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20Resample2dInitKernelmPf, .Lfunc_end0-_Z20Resample2dInitKernelmPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 84
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib ; -- Begin function _Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.globl	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
	.p2align	8
	.type	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib,@function
_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib: ; @_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB1_12
; %bb.1:
	s_clause 0x1
	s_load_b128 s[20:23], s[0:1], 0x40
	s_load_b256 s[12:19], s[0:1], 0x20
	v_ashrrev_i32_e32 v7, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v1, v7
	v_xor_b32_e32 v8, v6, v7
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s0, s21, 31
	s_mul_i32 s1, s21, s20
	s_add_i32 s3, s21, s0
	s_mul_i32 s2, s1, s19
	s_xor_b32 s3, s3, s0
	s_ashr_i32 s4, s2, 31
	v_cvt_f32_u32_e32 v0, s3
	s_add_i32 s2, s2, s4
	s_sub_i32 s5, 0, s3
	s_xor_b32 s2, s2, s4
	s_ashr_i32 s24, s20, 31
	v_cvt_f32_u32_e32 v3, s2
	v_rcp_iflag_f32_e32 v0, v0
	s_add_i32 s25, s20, s24
	v_xor_b32_e32 v11, s4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s5, v0
	s_sub_i32 s5, 0, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v5, s5, v3
	s_ashr_i32 s5, s18, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s18, s18, s5
	v_mul_hi_u32 v4, v0, v4
	s_xor_b32 s5, s18, s5
	s_xor_b32 s18, s25, s24
	v_cvt_f32_u32_e32 v6, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v5, v3, v5
	v_cvt_f32_u32_e32 v10, s18
	s_sub_i32 s24, 0, s5
	v_add_nc_u32_e32 v0, v0, v4
	v_rcp_iflag_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v10, v10
	v_xor_b32_e32 v4, s0, v7
	v_mul_hi_u32 v0, v8, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	v_add_nc_u32_e32 v12, 1, v0
	v_add_nc_u32_e32 v3, v3, v5
	v_mul_lo_u32 v5, v0, s3
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v5
	v_cmp_le_u32_e32 vcc_lo, s3, v5
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	v_mul_hi_u32 v3, v8, v3
	v_subrev_nc_u32_e32 v12, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v5, v12, vcc_lo
	v_add_nc_u32_e32 v12, 1, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v9, v3, s2
	v_add_nc_u32_e32 v13, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v5
	v_cvt_u32_f32_e32 v5, v10
	v_mul_lo_u32 v10, s24, v6
	v_sub_nc_u32_e32 v9, v8, v9
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v14, s2, v9
	v_cmp_le_u32_e64 s0, s2, v9
	v_mul_hi_u32 v10, v6, v10
	v_xor_b32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v13, s0
	v_cndmask_b32_e64 v9, v9, v14, s0
	s_sub_i32 s0, 0, s18
	v_sub_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v6, v6, v10
	v_add_nc_u32_e32 v13, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s2, v9
	v_mul_lo_u32 v9, s0, v5
	s_ashr_i32 s0, s1, 31
	v_ashrrev_i32_e32 v4, 31, v0
	s_add_i32 s1, s1, s0
	v_cndmask_b32_e32 v3, v3, v13, vcc_lo
	s_xor_b32 s1, s1, s0
	v_xor_b32_e32 v7, s0, v7
	s_sub_i32 s2, 0, s1
	v_mul_hi_u32 v9, v5, v9
	v_xor_b32_e32 v3, v3, v11
	v_add_nc_u32_e32 v12, v0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v3, v3, v11
	v_add_nc_u32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v12, v4
	v_ashrrev_i32_e32 v11, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v9, v5
	v_add_nc_u32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v11
	v_mul_lo_u32 v5, v5, s18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, v6
	v_sub_nc_u32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, s5
	v_cmp_le_u32_e32 vcc_lo, s18, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v6
	v_subrev_nc_u32_e32 v6, s18, v5
	v_subrev_nc_u32_e32 v9, s5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_subrev_nc_u32_e32 v6, s18, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v5
	v_subrev_nc_u32_e32 v9, s5, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_mul_lo_u32 v6, v0, s21
	v_xor_b32_e32 v5, v5, v4
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v5, v4
	v_xor_b32_e32 v3, v3, v11
	v_sub_nc_u32_e32 v10, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v0, v3, v11
	v_mul_lo_u32 v3, v9, s17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v0, s15
	v_add3_u32 v3, v10, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s16, v3
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[5:6], off
	v_cvt_f32_u32_e32 v5, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v6, s2, v5
	s_ashr_i32 s2, s19, 31
	s_add_i32 s3, s19, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s3, s2
	v_cvt_f32_u32_e32 v11, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v5, v6
	s_sub_i32 s0, 0, s2
	v_rcp_iflag_f32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v6
	v_mul_hi_u32 v5, v8, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, 0x4f7ffffe, v11
	v_mul_lo_u32 v6, v5, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v8, v6
	v_add_nc_u32_e32 v8, 1, v5
	v_subrev_nc_u32_e32 v12, s1, v6
	v_cmp_le_u32_e32 vcc_lo, s1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	v_cndmask_b32_e32 v6, v6, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 1, v5
	v_cmp_le_u32_e32 vcc_lo, s1, v6
	v_cvt_u32_f32_e32 v6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	v_mul_lo_u32 v8, s0, v6
	s_and_b32 s0, s23, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s0, 0
	v_xor_b32_e32 v5, v5, v7
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v6, v8
	v_sub_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v5
	v_add_nc_u32_e32 v6, v6, v8
	v_cvt_f32_i32_e32 v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v5, v7
	v_xor_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v6
	v_mul_lo_u32 v6, v6, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v6
	v_subrev_nc_u32_e32 v6, s2, v5
	v_cmp_le_u32_e32 vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_subrev_nc_u32_e32 v6, s2, v5
	v_cmp_le_u32_e32 vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cvt_f32_i32_e32 v6, v10
	v_xor_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, v5, v7
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v3, v3, v6 :: v_dual_add_f32 v4, v4, v8
	s_cbranch_scc0 .LBB1_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[5:6], v4
	v_cvt_f64_f32_e32 v[7:8], v3
	s_add_i32 s1, s20, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], 0.5
	v_add_f64 v[7:8], v[7:8], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f64_e32 v[5:6], v[5:6]
	v_floor_f64_e32 v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v6, v[5:6]
	v_cvt_i32_f64_e32 v8, v[7:8]
	v_mul_lo_u32 v5, v0, s12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_minmax_i32 v9, v6, s1, 0
	v_mad_u64_u32 v[6:7], null, v10, s13, v[5:6]
	s_add_i32 s1, s21, -1
	s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
	v_minmax_i32 v7, v8, s1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v9, s14
	v_add3_u32 v5, v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v9, v[5:6], off
	s_branch .LBB1_4
.LBB1_3:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9
.LBB1_4:                                ; %Flow196
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_11
; %bb.5:
	s_cmp_lt_i32 s22, 1
	s_cbranch_scc1 .LBB1_10
; %bb.6:                                ; %.preheader.lr.ph
	s_waitcnt vmcnt(0)
	v_floor_f32_e32 v9, v3
	v_floor_f32_e32 v15, v4
	s_add_i32 s0, s20, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v3, v9 :: v_dual_sub_f32 v17, v4, v15
	v_cvt_f64_f32_e32 v[5:6], v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[7:8], v17
	v_add_f64 v[11:12], -v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], -v[7:8], 1.0
	v_mul_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[3:4], v[11:12], v[13:14]
	v_add_f32_e32 v11, 1.0, v15
	v_mul_f64 v[5:6], v[13:14], v[5:6]
	v_mul_lo_u32 v14, v0, s12
	v_mul_f32_e32 v0, v16, v17
	v_cvt_i32_f32_e32 v12, v15
	v_cvt_i32_f32_e32 v11, v11
	v_mul_lo_u32 v15, v10, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_minmax_i32 v12, v12, s0, 0
	v_minmax_i32 v11, v11, s0, 0
	s_add_i32 s0, s21, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v12, s14, v12
	v_mul_lo_u32 v11, s14, v11
	v_add_f32_e32 v13, 1.0, v9
	v_cvt_i32_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v9, v9, s0, 0
	v_add_nc_u32_e32 v10, v9, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v13, v13
	v_add_nc_u32_e32 v9, v9, v12
	v_add3_u32 v10, v10, v15, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_minmax_i32 v13, v13, s0, 0
	s_mov_b32 s0, 0
	v_add_nc_u32_e32 v18, v13, v11
	v_add_nc_u32_e32 v13, v13, v12
	v_add3_u32 v11, v9, v15, v14
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v12, v18, v15, v14
	v_add3_u32 v13, v13, v15, v14
.LBB1_7:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_8 Depth 2
	s_mov_b32 s1, 0
.LBB1_8:                                ;   Parent Loop BB1_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, s1, v11
	v_cvt_f64_f32_e32 v[16:17], v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v18, v[14:15], off
	v_add_nc_u32_e32 v14, s1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v19, v[14:15], off
	v_add_nc_u32_e32 v14, s1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v20, v[14:15], off
	v_add_nc_u32_e32 v14, s1, v12
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s22, s1
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v21, v[14:15], off
	s_waitcnt vmcnt(3)
	v_cvt_f64_f32_e32 v[14:15], v18
	v_fma_f64 v[14:15], v[3:4], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v9, v[14:15]
	s_waitcnt vmcnt(2)
	v_cvt_f64_f32_e32 v[14:15], v19
	v_cvt_f64_f32_e32 v[16:17], v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[5:6], v[14:15], v[16:17]
	v_cvt_f32_f64_e32 v9, v[14:15]
	s_waitcnt vmcnt(1)
	v_cvt_f64_f32_e32 v[14:15], v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[16:17], v9
	v_fma_f64 v[14:15], v[7:8], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v9, v[14:15]
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v0, v21
	s_cbranch_scc0 .LBB1_8
; %bb.9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_7 Depth=1
	v_add_nc_u32_e32 v10, s14, v10
	v_add_nc_u32_e32 v11, s14, v11
	v_add_nc_u32_e32 v12, s14, v12
	v_add_nc_u32_e32 v13, s14, v13
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, s22
	s_cbranch_scc0 .LBB1_7
	s_branch .LBB1_11
.LBB1_10:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v9, 0
.LBB1_11:                               ; %.sink.split
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v9, off
.LBB1_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib, .Lfunc_end1-_Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2032
; NumSgprs: 28
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib ; -- Begin function _Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.globl	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
	.p2align	8
	.type	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib,@function
_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib: ; @_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x8c
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_14
; %bb.1:
	s_load_b128 s[20:23], s[0:1], 0x68
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s23, 1
	s_cbranch_scc1 .LBB2_14
; %bb.2:                                ; %.preheader.lr.ph
	s_load_b256 s[4:11], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s7, 31
	s_mul_i32 s2, s7, s6
	s_add_i32 s12, s7, s3
	s_mul_i32 s11, s2, s5
	s_xor_b32 s12, s12, s3
	s_ashr_i32 s13, s11, 31
	v_cvt_f32_u32_e32 v0, s12
	s_add_i32 s11, s11, s13
	s_ashr_i32 s15, s2, 31
	s_xor_b32 s11, s11, s13
	s_add_i32 s2, s2, s15
	v_rcp_iflag_f32_e32 v0, v0
	v_cvt_f32_u32_e32 v4, s11
	s_xor_b32 s18, s2, s15
	v_add_nc_u32_e32 v3, v1, v2
	v_cvt_f32_u32_e32 v5, s18
	v_xor_b32_e32 v6, s3, v2
	v_rcp_iflag_f32_e32 v4, v4
	s_sub_i32 s3, 0, s12
	s_ashr_i32 s14, s4, 31
	v_rcp_iflag_f32_e32 v5, v5
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_add_i32 s2, s4, s14
	v_xor_b32_e32 v3, v3, v2
	s_ashr_i32 s16, s6, 31
	s_ashr_i32 s17, s5, 31
	v_cvt_u32_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	s_add_i32 s4, s6, s16
	s_add_i32 s5, s5, s17
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_mul_lo_u32 v7, s3, v0
	v_cvt_u32_f32_e32 v4, v4
	s_sub_i32 s3, 0, s11
	s_xor_b32 s4, s4, s16
	v_cvt_u32_f32_e32 v5, v5
	s_xor_b32 s5, s5, s17
	v_mul_lo_u32 v8, s3, v4
	s_xor_b32 s3, s2, s14
	v_mul_hi_u32 v7, v0, v7
	v_cvt_f32_u32_e32 v10, s3
	s_sub_i32 s2, 0, s18
	v_cvt_f32_u32_e32 v11, s4
	v_cvt_f32_u32_e32 v12, s5
	v_xor_b32_e32 v9, s15, v2
	v_mul_hi_u32 v8, v4, v8
	v_xor_b32_e32 v2, s13, v2
	v_add_nc_u32_e32 v0, v0, v7
	v_rcp_iflag_f32_e32 v7, v10
	v_mul_lo_u32 v10, s2, v5
	s_sub_i32 s13, 0, s4
	s_sub_i32 s6, 0, s3
	v_mul_hi_u32 v0, v3, v0
	v_add_nc_u32_e32 v4, v4, v8
	v_rcp_iflag_f32_e32 v8, v11
	v_rcp_iflag_f32_e32 v11, v12
	s_sub_i32 s14, 0, s5
	v_mul_hi_u32 v10, v5, v10
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	v_mul_hi_u32 v4, v3, v4
	v_mul_lo_u32 v12, v0, s12
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_u32_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v8, 0x4f7ffffe, v8 :: v_dual_mul_f32 v11, 0x4f7ffffe, v11
	v_add_nc_u32_e32 v5, v5, v10
	v_mul_lo_u32 v13, v4, s11
	v_sub_nc_u32_e32 v10, v3, v12
	v_add_nc_u32_e32 v12, 1, v0
	v_add_nc_u32_e32 v14, 1, v4
	v_cvt_u32_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s12, v10
	v_sub_nc_u32_e32 v13, v3, v13
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	v_subrev_nc_u32_e32 v12, s12, v10
	v_mul_hi_u32 v5, v3, v5
	v_subrev_nc_u32_e32 v15, s11, v13
	v_cmp_le_u32_e64 s2, s11, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v10, v12, vcc_lo
	v_add_nc_u32_e32 v12, 1, v0
	v_cndmask_b32_e64 v4, v4, v14, s2
	v_cndmask_b32_e64 v13, v13, v15, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s12, v10
	v_mul_lo_u32 v16, v5, s18
	v_mul_lo_u32 v14, s13, v8
	v_cvt_u32_f32_e32 v10, v11
	v_mul_lo_u32 v11, s6, v7
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v13
	v_add_nc_u32_e32 v13, 1, v5
	v_add_nc_u32_e32 v15, 1, v4
	v_sub_nc_u32_e32 v3, v3, v16
	v_xor_b32_e32 v0, v0, v6
	v_mul_hi_u32 v12, v8, v14
	v_mul_hi_u32 v11, v7, v11
	v_cndmask_b32_e32 v4, v4, v15, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v3
	v_sub_nc_u32_e32 v0, v0, v6
	v_subrev_nc_u32_e32 v6, s18, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v2
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_add_nc_u32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v2, v4, v2
	v_cndmask_b32_e32 v4, v5, v13, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v0
	v_cmp_le_u32_e32 vcc_lo, s18, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v2
	v_add_nc_u32_e32 v6, 1, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v14, v0, v5
	v_mul_lo_u32 v0, v0, s7
	v_dual_cndmask_b32 v3, v4, v6 :: v_dual_add_nc_u32 v2, v2, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v14, v5
	v_add_nc_u32_e32 v6, v7, v11
	v_mul_lo_u32 v7, s14, v10
	v_xor_b32_e32 v2, v2, v13
	v_xor_b32_e32 v3, v3, v9
	v_mul_hi_u32 v8, v4, v8
	s_load_b256 s[12:19], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v6, v2, v6
	v_sub_nc_u32_e32 v3, v3, v9
	v_mul_hi_u32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v8, v8, s4
	v_ashrrev_i32_e32 v9, 31, v3
	v_mul_lo_u32 v6, v6, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, v3, v9
	v_sub_nc_u32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, v2, v6
	v_xor_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v6, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_add_nc_u32_e32 v7, v10, v7
	v_subrev_nc_u32_e32 v8, s3, v2
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, v3, v7
	v_subrev_nc_u32_e32 v6, s4, v4
	v_cndmask_b32_e32 v2, v2, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v7, v7, s5
	v_subrev_nc_u32_e32 v8, s3, v2
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x38
	s_load_b64 s[0:1], s[0:1], 0x60
	v_xor_b32_e32 v4, v4, v5
	v_cndmask_b32_e32 v2, v2, v8, vcc_lo
	v_sub_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v4, v5
	v_xor_b32_e32 v2, v2, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v6, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_sub_nc_u32_e32 v7, v2, v13
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v3, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v3, v5, s18
	v_sub_nc_u32_e32 v6, v1, v0
	v_mul_lo_u32 v4, v7, s16
	v_subrev_nc_u32_e32 v1, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v6, v4, v3
	v_dual_cndmask_b32 v3, v2, v1 :: v_dual_add_nc_u32 v2, s17, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v3, v9
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_sub_nc_u32_e32 v8, v4, v9
	v_mul_lo_u32 v4, v7, s8
	v_mul_lo_u32 v9, v5, s10
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v10, v[0:1], off
	global_load_b32 v2, v[2:3], off
	v_mad_u64_u32 v[0:1], null, v8, s9, v[4:5]
	v_cvt_f32_i32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v6, v9
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_add_i32 s3, s13, -1
	s_add_i32 s2, s12, -1
	global_load_b32 v3, v[0:1], off
	v_cvt_f32_i32_e32 v1, v6
	v_mul_lo_u32 v0, v7, s20
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v10, v1
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v2, v4
	v_mad_u64_u32 v[1:2], null, v8, s21, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v6, v5
	v_floor_f32_e32 v7, v5
	v_cvt_i32_f32_e32 v0, v4
	v_floor_f32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v6, v6
	v_add_f32_e32 v8, 1.0, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_f32_i32_e32 v0, v0
	v_cvt_i32_f32_e32 v7, v7
	v_cvt_i32_f32_e32 v9, v2
	v_add_f32_e32 v2, 1.0, v2
	v_sub_f32_e32 v10, v5, v6
	v_sub_f32_e32 v0, v4, v0
	v_cvt_i32_f32_e32 v5, v8
	v_minmax_i32 v6, v7, s3, 0
	v_cvt_i32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_sub_f32 v7, 1.0, v10 :: v_dual_sub_f32 v8, 1.0, v0
	v_minmax_i32 v4, v9, s2, 0
	v_minmax_i32 v9, v5, s3, 0
	v_add_nc_u32_e32 v5, v1, v6
	v_minmax_i32 v6, v2, s2, 0
	v_mul_f32_e32 v2, v7, v0
	v_mul_f32_e32 v11, v7, v8
	v_mul_f32_e32 v12, v10, v8
	v_dual_mul_f32 v0, v10, v0 :: v_dual_add_nc_u32 v7, v1, v9
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v8, v3, v2
	v_mul_f32_e32 v9, v3, v11
	v_mul_f32_e32 v10, v3, v12
	v_mul_f32_e32 v11, v3, v0
.LBB2_3:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
                                        ;       Child Loop BB2_5 Depth 3
                                        ;       Child Loop BB2_7 Depth 3
                                        ;       Child Loop BB2_9 Depth 3
                                        ;       Child Loop BB2_11 Depth 3
	v_add_nc_u32_e32 v0, s2, v4
	v_add_nc_u32_e32 v1, s2, v6
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v12, v0, s22
	v_mul_lo_u32 v13, v1, s22
.LBB2_4:                                ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_5 Depth 3
                                        ;       Child Loop BB2_7 Depth 3
                                        ;       Child Loop BB2_9 Depth 3
                                        ;       Child Loop BB2_11 Depth 3
	v_add_nc_u32_e32 v14, s3, v5
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v14, v12
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
.LBB2_5:                                ; %atomicrmw.start
                                        ;   Parent Loop BB2_3 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v9
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB2_5
; %bb.6:                                ; %atomicrmw.end
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v15, s3, v7
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v15, v12
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
.LBB2_7:                                ; %atomicrmw.start141
                                        ;   Parent Loop BB2_3 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v10
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB2_7
; %bb.8:                                ; %atomicrmw.end140
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v0, v14, v13
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
.LBB2_9:                                ; %atomicrmw.start147
                                        ;   Parent Loop BB2_3 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v8
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB2_9
; %bb.10:                               ; %atomicrmw.end146
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v0, v15, v13
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
.LBB2_11:                               ; %atomicrmw.start153
                                        ;   Parent Loop BB2_3 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v11
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB2_11
; %bb.12:                               ; %atomicrmw.end152
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, s23
	s_cbranch_scc0 .LBB2_4
; %bb.13:                               ; %._crit_edge
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, s23
	s_cbranch_scc0 .LBB2_3
.LBB2_14:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib, .Lfunc_end2-_Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1836
; NumSgprs: 26
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib ; -- Begin function _Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.globl	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
	.p2align	8
	.type	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib,@function
_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib: ; @_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x8c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB3_25
; %bb.1:
	s_load_b128 s[16:19], s[0:1], 0x58
	v_ashrrev_i32_e32 v10, 31, v1
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s19, 31
	s_mul_i32 s4, s19, s18
	s_add_i32 s5, s19, s2
	s_mul_i32 s3, s4, s17
	s_xor_b32 s5, s5, s2
	s_ashr_i32 s8, s3, 31
	v_cvt_f32_u32_e32 v0, s5
	s_add_i32 s3, s3, s8
	s_sub_i32 s9, 0, s5
	s_xor_b32 s3, s3, s8
	s_ashr_i32 s10, s18, 31
	v_cvt_f32_u32_e32 v3, s3
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v8, s8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s9, v0
	s_sub_i32 s9, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v5, s9, v3
	s_ashr_i32 s9, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s11, s16, s9
	v_mul_hi_u32 v4, v0, v4
	s_xor_b32 s12, s11, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_sub_i32 s8, 0, s12
	v_mul_hi_u32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v0, v0, v4
	v_xor_b32_e32 v4, s2, v10
	s_add_i32 s2, s18, s10
	s_xor_b32 s13, s2, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v9, s13
	v_rcp_iflag_f32_e32 v9, v9
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v9, 0x4f7ffffe, v9 :: v_dual_add_nc_u32 v6, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v11, v6, v10
	v_cvt_f32_u32_e32 v6, s12
	v_mul_hi_u32 v0, v11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v6, v6
	v_add_nc_u32_e32 v12, 1, v0
	v_add_nc_u32_e32 v3, v3, v5
	v_mul_lo_u32 v5, v0, s5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v6, v6
	v_sub_nc_u32_e32 v5, v11, v5
	v_cmp_le_u32_e32 vcc_lo, s5, v5
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	v_mul_hi_u32 v3, v11, v3
	v_subrev_nc_u32_e32 v12, s5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v5, v12, vcc_lo
	v_add_nc_u32_e32 v12, 1, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v7, v3, s3
	v_add_nc_u32_e32 v13, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v5
	v_cvt_u32_f32_e32 v5, v9
	v_mul_lo_u32 v9, s8, v6
	s_load_b128 s[8:11], s[0:1], 0x28
	s_ashr_i32 s5, s4, 31
	v_sub_nc_u32_e32 v7, v11, v7
	s_add_i32 s4, s4, s5
	v_xor_b32_e32 v10, s5, v10
	s_xor_b32 s4, s4, s5
	s_load_b32 s5, s[0:1], 0x74
	v_subrev_nc_u32_e32 v14, s3, v7
	v_cmp_le_u32_e64 s2, s3, v7
	v_mul_hi_u32 v9, v6, v9
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v13, s2
	v_cndmask_b32_e64 v7, v7, v14, s2
	v_xor_b32_e32 v0, v0, v4
	s_sub_i32 s2, 0, s13
	v_add_nc_u32_e32 v6, v6, v9
	v_add_nc_u32_e32 v13, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v7
	v_mul_lo_u32 v7, s2, v5
	v_sub_nc_u32_e32 v0, v0, v4
	s_load_b64 s[2:3], s[0:1], 0x38
	v_cndmask_b32_e32 v3, v3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v4, 31, v0
	v_mul_hi_u32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v8
	v_add_nc_u32_e32 v12, v0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v3, v3, v8
	v_add_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v12, v4
	v_ashrrev_i32_e32 v8, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v7, v5
	v_add_nc_u32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v8
	v_mul_lo_u32 v5, v5, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, v6
	v_sub_nc_u32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, s12
	v_cmp_le_u32_e32 vcc_lo, s13, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v6
	v_subrev_nc_u32_e32 v6, s13, v5
	v_subrev_nc_u32_e32 v7, s12, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s12, v3
	v_subrev_nc_u32_e32 v6, s13, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v5
	v_subrev_nc_u32_e32 v7, s12, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s12, v3
	s_load_b128 s[12:15], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s19, -1
	v_xor_b32_e32 v5, v5, v4
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v4
	v_xor_b32_e32 v6, v3, v8
	v_mul_lo_u32 v3, v0, s19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, v5, s10
	v_sub_nc_u32_e32 v4, v6, v8
	s_load_b64 s[10:11], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v1, v3
	v_mul_lo_u32 v6, v4, s8
	s_sub_i32 s8, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v12, v6, v0
	v_add_nc_u32_e32 v8, s9, v6
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	s_clause 0x1
	global_load_b32 v0, v[6:7], off
	global_load_b32 v6, v[8:9], off
	v_cvt_f32_u32_e32 v7, s4
	v_rcp_iflag_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v7, v7
	v_mul_lo_u32 v8, s8, v7
	s_ashr_i32 s8, s17, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s9, s17, s8
	s_xor_b32 s16, s9, s8
	s_load_b128 s[8:11], s[0:1], 0x40
	v_cvt_f32_u32_e32 v9, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v7, v8
	v_rcp_iflag_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v7, v8
	v_mul_hi_u32 v7, v11, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, 0x4f7ffffe, v9
	v_mul_lo_u32 v8, v7, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, 1, v7
	v_subrev_nc_u32_e32 v13, s4, v8
	v_cmp_le_u32_e32 vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v8, v8, v13
	v_add_nc_u32_e32 v11, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s4, v8
	v_cvt_u32_f32_e32 v8, v9
	s_sub_i32 s4, 0, s16
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v9, s4, v8
	s_add_i32 s4, s5, -1
	s_lshr_b32 s17, s4, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v7, v7, v10
	s_add_i32 s4, s4, s17
	s_ashr_i32 s4, s4, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v8, v9
	v_sub_nc_u32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v11, 31, v7
	v_add_nc_u32_e32 v8, v8, v9
	v_cvt_f32_i32_e32 v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v7, v11
	v_xor_b32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v7, v8
	v_mul_lo_u32 v8, v8, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v8
	v_subrev_nc_u32_e32 v8, s16, v7
	v_cmp_le_u32_e32 vcc_lo, s16, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_cvt_f32_i32_e32 v8, v12
	v_subrev_nc_u32_e32 v12, s16, v7
	v_cmp_le_u32_e32 vcc_lo, s16, v7
	s_add_i32 s16, s18, -1
	s_cmp_gt_i32 s5, -1
	s_cselect_b32 s5, -1, 0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v10, v0, v8
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v8, v6, v9
	v_cndmask_b32_e32 v0, v7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v13, v10
	v_floor_f32_e32 v9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v11
	v_add_f32_e32 v6, 1.0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, 1.0, v9
	v_sub_nc_u32_e32 v0, v0, v11
	v_cvt_i32_f32_e32 v11, v13
	v_cvt_i32_f32_e32 v14, v9
	v_cvt_i32_f32_e32 v6, v6
	v_cvt_i32_f32_e32 v7, v7
	v_and_b32_e32 v0, 1, v0
	v_minmax_i32 v11, v11, s15, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_minmax_i32 v12, v6, s15, 0
	v_minmax_i32 v6, v14, s16, 0
	v_minmax_i32 v7, v7, s16, 0
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s15, vcc_lo
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB3_13
; %bb.2:
	v_mov_b32_e32 v0, 0
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_12
; %bb.3:                                ; %.preheader215.lr.ph
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v8, v4, s9
	v_mul_lo_u32 v9, v5, s11
	v_sub_f32_e32 v0, v13, v10
	v_mul_lo_u32 v4, v4, s12
	v_mul_lo_u32 v10, s14, v6
	v_mul_lo_u32 v13, s14, v7
	s_lshl_b32 s17, s4, 1
	v_add_f32_e32 v5, 1.0, v0
	s_cmp_gt_i32 s8, 0
	v_add3_u32 v0, v1, v9, v8
	s_cselect_b32 s16, -1, 0
	s_mov_b32 s18, 0
	v_add3_u32 v6, v12, v10, v4
	v_add3_u32 v7, v12, v13, v4
	v_sub_nc_u32_e32 v9, v0, v3
	v_mov_b32_e32 v0, 0
	v_sub_f32_e32 v8, 1.0, v5
	v_add3_u32 v10, v11, v10, v4
	v_add3_u32 v11, v11, v13, v4
	s_max_i32 s17, s17, 0
.LBB3_4:                                ; %.preheader215
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_5 Depth 2
                                        ;       Child Loop BB3_7 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v12, v11 :: v_dual_mov_b32 v13, v10
	v_dual_mov_b32 v14, v7 :: v_dual_mov_b32 v15, v6
	s_mov_b32 s19, 0
.LBB3_5:                                ; %.preheader214
                                        ;   Parent Loop BB3_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_7 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB3_8
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_5 Depth=2
	v_mov_b32_e32 v3, v9
	s_mov_b32 s20, 0
	s_mov_b32 s21, s8
.LBB3_7:                                ;   Parent Loop BB3_4 Depth=1
                                        ;     Parent Loop BB3_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v16, s20, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v18, s20, v13
	v_add_nc_u32_e32 v20, s20, v14
	v_add_nc_u32_e32 v22, s20, v15
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[24:25], 2, v[3:4]
	v_ashrrev_i32_e32 v19, 31, v18
	v_ashrrev_i32_e32 v21, 31, v20
	v_ashrrev_i32_e32 v23, 31, v22
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_add_i32 s21, s21, -1
	v_add_co_u32 v24, vcc_lo, s2, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, s6, v16
	global_load_b32 v4, v[24:25], off
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	global_load_b32 v24, v[16:17], off
	v_add_co_u32 v16, vcc_lo, s6, v20
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v21, vcc_lo
	global_load_b32 v20, v[18:19], off
	v_add_co_u32 v18, vcc_lo, s6, v22
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v23, vcc_lo
	s_clause 0x1
	global_load_b32 v16, v[16:17], off
	global_load_b32 v17, v[18:19], off
	s_add_i32 s20, s20, s13
	s_cmp_eq_u32 s21, 0
	s_waitcnt vmcnt(4)
	v_dual_mul_f32 v18, v5, v4 :: v_dual_add_nc_u32 v3, s10, v3
	v_mul_f32_e32 v4, v8, v4
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v18, v24
	s_waitcnt vmcnt(2)
	v_fma_f32 v0, -v18, v20, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v4, v16
	s_waitcnt vmcnt(0)
	v_fma_f32 v0, -v4, v17, v0
	s_cbranch_scc0 .LBB3_7
.LBB3_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB3_5 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v15, s14, v15
	v_add_nc_u32_e32 v14, s14, v14
	v_add_nc_u32_e32 v13, s14, v13
	v_add_nc_u32_e32 v12, s14, v12
	s_add_i32 s20, s19, 1
	s_cmp_eq_u32 s19, s17
	s_cbranch_scc1 .LBB3_10
; %bb.9:                                ;   in Loop: Header=BB3_5 Depth=2
	s_mov_b32 s19, s20
	s_branch .LBB3_5
.LBB3_10:                               ; %._crit_edge222
                                        ;   in Loop: Header=BB3_4 Depth=1
	v_add_nc_u32_e32 v6, 1, v6
	v_add_nc_u32_e32 v7, 1, v7
	v_add_nc_u32_e32 v10, 1, v10
	v_add_nc_u32_e32 v11, 1, v11
	s_add_i32 s19, s18, 1
	s_cmp_eq_u32 s18, s17
	s_cbranch_scc1 .LBB3_12
; %bb.11:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s18, s19
	s_branch .LBB3_4
.LBB3_12:                               ; %Flow359
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr7
.LBB3_13:                               ; %Flow364
	s_and_not1_saveexec_b32 s15, s15
	s_cbranch_execz .LBB3_24
; %bb.14:
	v_mov_b32_e32 v0, 0
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_24
; %bb.15:                               ; %.preheader213.lr.ph
	v_sub_f32_e32 v0, v9, v8
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v8, v4, s9
	v_mul_lo_u32 v9, v5, s11
	v_mul_lo_u32 v4, v4, s12
	v_mul_lo_u32 v10, s14, v7
	v_mul_lo_u32 v13, s14, v6
	v_add_f32_e32 v5, 1.0, v0
	s_lshl_b32 s5, s4, 1
	s_cmp_gt_i32 s8, 0
	s_mov_b32 s9, 0
	v_add3_u32 v0, v1, v9, v8
	s_cselect_b32 s4, -1, 0
	v_add3_u32 v6, v11, v10, v4
	v_add3_u32 v7, v11, v13, v4
	v_add3_u32 v10, v12, v10, v4
	v_sub_nc_u32_e32 v9, v0, v3
	v_mov_b32_e32 v0, 0
	v_sub_f32_e32 v8, 1.0, v5
	v_add3_u32 v11, v12, v13, v4
	s_max_i32 s5, s5, 0
.LBB3_16:                               ; %.preheader213
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_17 Depth 2
                                        ;       Child Loop BB3_19 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v12, v11 :: v_dual_mov_b32 v13, v10
	v_dual_mov_b32 v14, v7 :: v_dual_mov_b32 v15, v6
	s_mov_b32 s11, 0
.LBB3_17:                               ; %.preheader
                                        ;   Parent Loop BB3_16 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_19 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB3_20
; %bb.18:                               ; %.lr.ph230
                                        ;   in Loop: Header=BB3_17 Depth=2
	v_mov_b32_e32 v3, v9
	s_mov_b32 s12, 0
	s_mov_b32 s16, s8
.LBB3_19:                               ;   Parent Loop BB3_16 Depth=1
                                        ;     Parent Loop BB3_17 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v16, s12, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v18, s12, v14
	v_add_nc_u32_e32 v20, s12, v13
	v_add_nc_u32_e32 v22, s12, v15
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[24:25], 2, v[3:4]
	v_ashrrev_i32_e32 v19, 31, v18
	v_ashrrev_i32_e32 v21, 31, v20
	v_ashrrev_i32_e32 v23, 31, v22
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_add_i32 s16, s16, -1
	v_add_co_u32 v24, vcc_lo, s2, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, s6, v16
	global_load_b32 v4, v[24:25], off
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	global_load_b32 v24, v[16:17], off
	v_add_co_u32 v16, vcc_lo, s6, v20
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v21, vcc_lo
	global_load_b32 v20, v[18:19], off
	v_add_co_u32 v18, vcc_lo, s6, v22
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v23, vcc_lo
	s_clause 0x1
	global_load_b32 v16, v[16:17], off
	global_load_b32 v17, v[18:19], off
	s_add_i32 s12, s12, s13
	s_cmp_eq_u32 s16, 0
	s_waitcnt vmcnt(4)
	v_dual_mul_f32 v18, v5, v4 :: v_dual_add_nc_u32 v3, s10, v3
	v_mul_f32_e32 v4, v8, v4
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v18, v24
	s_waitcnt vmcnt(2)
	v_fma_f32 v0, -v18, v20, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v4, v16
	s_waitcnt vmcnt(0)
	v_fma_f32 v0, -v4, v17, v0
	s_cbranch_scc0 .LBB3_19
.LBB3_20:                               ; %._crit_edge231
                                        ;   in Loop: Header=BB3_17 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v15, s14, v15
	v_add_nc_u32_e32 v14, s14, v14
	v_add_nc_u32_e32 v13, s14, v13
	v_add_nc_u32_e32 v12, s14, v12
	s_add_i32 s12, s11, 1
	s_cmp_eq_u32 s11, s5
	s_cbranch_scc1 .LBB3_22
; %bb.21:                               ;   in Loop: Header=BB3_17 Depth=2
	s_mov_b32 s11, s12
	s_branch .LBB3_17
.LBB3_22:                               ; %._crit_edge236
                                        ;   in Loop: Header=BB3_16 Depth=1
	v_add_nc_u32_e32 v6, 1, v6
	v_add_nc_u32_e32 v7, 1, v7
	v_add_nc_u32_e32 v10, 1, v10
	v_add_nc_u32_e32 v11, 1, v11
	s_add_i32 s11, s9, 1
	s_cmp_eq_u32 s9, s5
	s_cbranch_scc1 .LBB3_24
; %bb.23:                               ;   in Loop: Header=BB3_16 Depth=1
	s_mov_b32 s9, s11
	s_branch .LBB3_16
.LBB3_24:                               ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s15
	s_load_b64 s[0:1], s[0:1], 0x50
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB3_25:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 384
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib, .Lfunc_end3-_Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2476
; NumSgprs: 24
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20Resample2dInitKernelmPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20Resample2dInitKernelmPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           1
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z16Resample2dKernelmPKfS0_Pfiiiiiiiiiiib.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .offset:         108
        .size:           4
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     by_value
      - .offset:         116
        .size:           4
        .value_kind:     by_value
      - .offset:         120
        .size:           1
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         132
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         140
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         142
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         144
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         146
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         148
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         150
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         192
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z29kernel_resample2d_grad_input1mPKfiiiiS0_iiiS0_iiiiiiiPfiiiib.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .offset:         108
        .size:           4
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     by_value
      - .offset:         116
        .size:           4
        .value_kind:     by_value
      - .offset:         120
        .size:           1
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         132
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         136
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         140
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         142
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         144
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         146
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         148
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         150
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         192
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 384
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z29kernel_resample2d_grad_input2mPKfiiiS0_iiiS0_iiiiPfiiiiiiiib.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
