#include <cuda.h>
#include <device_launch_parameters.h>

/*
Inspired by the implementation of CustomPong.cu + GridWorld.cu

@author mp
*/
extern "C"
{
	__device__ __inline__ unsigned int AsUint(float *sourceImage, int pixelId)
	{
		return *(((unsigned int*)sourceImage) + pixelId);
	}

	__device__ __inline__ unsigned int GetComponent(unsigned int pixel, int comp)
	{
		return (pixel >> (comp * 8)) & 0xFF;
	}

	/*
	Draws a background color into a 3-component image.
	inputWidth & inputHeight: map dimensions in pixels
	gridDim.y = 3, one for each color component
	*/
	__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight,
		float r, float g, float b)
	{
		int column = threadIdx.x + blockDim.x * blockIdx.z;
		if (column >= inputWidth)
			return;

		int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel 
			+ column;

		int imagePixels = inputWidth * inputHeight; 

		if (id < 3*imagePixels) // 3 for RGB 
		{
			float color = 0.0f;
			switch (blockIdx.y)
			{
			case 0:
				color = r;
				break;
			case 1:
				color = g;
				break;
			case 2:
				color = b;
				break;
			}
			target[id] = color;
		}
	}

	/*
	Adds noise into a 3-component image.
	inputWidth & inputHeight: map dimensions in pixels
	*/
	__global__ void AddRgbNoiseKernel(float *target, int inputWidth, int inputHeight, float *randoms, int isBlackAndWhiteNoise)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int imagePixels = inputWidth * inputHeight;

		if (id < imagePixels)
		{
			unsigned int tg = *((unsigned int*)(&target[id]));

			int random = randoms[id];

			int blue = (tg >> 0) & (0xFF);
			blue += random;
			blue = blue < 255 ? blue : 255;
			blue = blue > 0 ? blue : 0;

			int green = ((tg >> 8) & (0xFF));
			green += (isBlackAndWhiteNoise ? random : (int)(randoms[id + imagePixels]));
			green = green < 255 ? green : 255;
			green = green > 0 ? green : 0;

			int red = ((tg >> 16) & (0xFF));
			red += (isBlackAndWhiteNoise ? random : (int)(randoms[id + imagePixels * 2]));
			red = red < 255 ? red : 255;
			red = red > 0 ? red : 0;

			// alpha is the last channel (<< 24)
			unsigned int tmp = (*((unsigned int *)(&blue)) << 0)
						     | (*((unsigned int *)(&green)) << 8)
							 | (*((unsigned int *)(&red)) << 16);

			target[id] = *((float *)(&tmp));
		}
	}

	/* Fill specified rectangle with color */
	__global__ void DrawRgbaColorKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		int areaWidth, int areaHeight, float r, float g, float b)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = areaWidth * areaHeight;

		int idTextureRgb = id / texturePixels;
		int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
		int idTextureY = idTexturePixel / areaWidth;
		int idTextureX = (idTexturePixel - idTextureY * areaWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idTextureRgb < 3) // 3 channels that we will write to
		{
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				float color = 0.0f;
				switch (idTextureRgb)
				{
				case 0:
					color = r;
					break;
				case 1:
					color = g;
					break;
				case 2:
					color = b;
					break;
				}
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				target[tIndex] = color;
			}
		}
	}

	/*
	Draws a texture into a 3-component target. RGBA. Checks bounds.
	*/
	__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x 
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = id / texturePixels;
		int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
		int idTextureY = idTexturePixel / textureWidth; 
		int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idTextureRgb < 3) // 3 channels that we will write to
		{
			// the texture is in BGR format, we want RGB
			switch (idTextureRgb)
			{
			case 0: // R
				idTextureRgb = 2; // B
				break;
			case 2: // B
				idTextureRgb = 0; // R
				break;
			}
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];
				target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
			}
		}
	}

	/*
	Draws a texture into a 3-component target. RGBA. Checks bounds. Stretches the texture.
	*/
	__global__ void DrawRgbaTextureKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int objectPixels = objectWidth * objectHeight;

		int idObjectRgb = id / objectPixels;
		int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
		int idObjectY = idObjectPixel / objectWidth;
		int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idObjectRgb < 3) // 3 channels that we will write to
		{
			int targetRgb = idObjectRgb;
			// the texture is in BGR format, we want RGB
			switch (idObjectRgb)
			{
			case 0: // R
				targetRgb = 2; // B
				break;
			case 2: // B
				targetRgb = 0; // R
				break;
			}
			// if the object pixel offset by inputX, inputY, lies inside the target
			if (idObjectX + inputX < targetWidth &&
				idObjectX + inputX >= 0 &&
				idObjectY + inputY < targetHeight &&
				idObjectY + inputY >= 0)
			{
				// nearest neighbor texture X,Y:
				int textureX = textureWidth * idObjectX / objectWidth;
				int textureY = textureHeight * idObjectY / objectHeight;
				int textureId = textureY * textureWidth + textureX;
				
				int rgbIndex = textureId + idObjectRgb * texturePixels;
				float textureValue = texture[rgbIndex];

				int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
				int aIndex = textureId + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];
				target[tIndex] = target[tIndex] * (1.0f - a) + a * textureValue;
			}
		}
	}

	/*
	Same as DrawRgbaTextureKernelNearestNeighbor, but texture = mask and texture's pixel values are replaced by a single color
	*/
	__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, 
		float r, float g, float b ) // texture = mask
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int objectPixels = objectWidth * objectHeight;

		int idObjectRgb = id / objectPixels;
		int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
		int idObjectY = idObjectPixel / objectWidth;
		int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idObjectRgb < 3) // 3 channels that we will write to
		{
			int targetRgb = idObjectRgb;
			// the texture is in BGR format, we want RGB
			switch (idObjectRgb)
			{
			case 0: // R
				targetRgb = 2; // B
				break;
			case 2: // B
				targetRgb = 0; // R
				break;
			}
			// if the object pixel offset by inputX, inputY, lies inside the target
			if (idObjectX + inputX < targetWidth &&
				idObjectX + inputX >= 0 &&
				idObjectY + inputY < targetHeight &&
				idObjectY + inputY >= 0)
			{
				// nearest neighbor texture X,Y:
				int textureX = textureWidth * idObjectX / objectWidth;
				int textureY = textureHeight * idObjectY / objectHeight;
				int textureId = textureY * textureWidth + textureX;

				int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
				int aIndex = textureId + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];

				if (a > 0) // mask allows color here
				{
					// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
					target[tIndex] = target[tIndex] * (1.0f - a);
					switch (idObjectRgb)
					{
					case 0:
						target[tIndex] += a*r;
						break;
					case 1:
						target[tIndex] += a*g;
						break;
					case 2:
					default:
						target[tIndex] += a*b;
						break;
					}
				}
			}
		}
	}

	/*
	Optimized version of DrawRgbaTextureKernel : avoids division operations (~30% speedup)
	The width of the texture is in blockDim.x
	The height of the texture is distributed between blockDim.y and gridDim.x
	*/
	__global__ void DrawRgbaTextureKernel2DBlock(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight)
	{
		int id = blockDim.x * blockDim.y * (blockIdx.y * gridDim.x + blockIdx.x)
			+ blockDim.x * threadIdx.y
			+ threadIdx.x; // 2D grid of 2D blocks; block dimension x = texture width; 
		// grid dimension x + block dimension y = texture height

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = blockIdx.y;
		int idTexturePixel = (id - idTextureRgb * texturePixels);
		int idTextureY = blockIdx.x * blockDim.y + threadIdx.y;
		int idTextureX = threadIdx.x;


		if (idTextureRgb < 3) // 3 channels that we will write to
		{
			// the texture is in BGR format, we want RGB
			switch (idTextureRgb)
			{
			case 0: // R
				idTextureRgb = 2; // B
				break;
			case 2: // B
				idTextureRgb = 0; // R
				break;
			}
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];
				target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
			}
		}
	}

	/*
	Draws an RGB color into the masked area. The color is drawn in each pixel that has non-0 alpha.
	*/
	__global__ void DrawMaskedColorKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *textureMask, int textureWidth, int textureHeight, float r, float g, float b) 
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = id / texturePixels;
		int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
		int idTextureY = idTexturePixel / textureWidth;
		int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster

		if (idTextureRgb < 3) // only RGB channels are interesting
		{
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = textureMask[aIndex];

				if (a > 0) // mask allows color here
				{
					switch (idTextureRgb)
					{
					case 0:
						target[tIndex] = r;
						break;
					case 1:
						target[tIndex] = g;
						break;
					case 2:
					default:
						target[tIndex] = b;
						break;
					}
				}
			}
		}
	}

	/*
	Optimized version of DrawMaskedColorKernel : avoids division operations (~30% speedup)
	The width of the texture is in blockDim.x
	The height of the texture is distributed between blockDim.y and gridDim.x
	*/
	__global__ void DrawMaskedColorKernel2DBlock(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *textureMask, int textureWidth, int textureHeight, float r, float g, float b)
	{
		int id = blockDim.x * blockDim.y * (blockIdx.y * gridDim.x + blockIdx.x)
			+ blockDim.x * threadIdx.y
			+ threadIdx.x; // 2D grid of 2D blocks; block dimension x = texture width; 
		// grid dimension x + block dimension y = texture height

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = blockIdx.y;
		int idTexturePixel = (id - idTextureRgb * texturePixels);
		int idTextureY = blockIdx.x * blockDim.y + threadIdx.y;
		int idTextureX = threadIdx.x;


		if (idTextureRgb < 3) // only RGB channels are interesting
		{
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = textureMask[aIndex];

				if (a > 0) // mask allows color here
				{
					switch (idTextureRgb)
					{
					case 0:
						target[tIndex] = r;
						break;
					case 1:
						target[tIndex] = g;
						break;
					case 2:
					default:
						target[tIndex] = b;
						break;
					}
				}
			}
		}
	}

	/*
	Convert Raw to RGB
	*/
	__global__ void ExtractRawComponentsToRgbKernel(float *target, int inputWidth, int inputHeight)
	{
		int pixelId = blockDim.x*blockIdx.y*gridDim.x
			+ blockDim.x*blockIdx.x
			+ threadIdx.x;

		int imagePixels = inputWidth * inputHeight;

		if (pixelId >= imagePixels)
			return;

		unsigned int* uTarget = (unsigned int*)target;
		unsigned int pixel = uTarget[pixelId];

		for (int i = 2; i >= 0; i--)
		{
			unsigned int component = pixel;
			component = component >> (8 * (2-i)); // 2-i == RGB -> BGR
			component = component & 0xFF;
			target[imagePixels * i + pixelId] = ((float)component)/255.0f;
			__syncthreads();
		}
	}

	/*
	Convert Raw to RGB
	*/
	__global__ void RawToRgbKernel(float *source, float *target, int pixelCount)
	{
		int pixelId = blockDim.x*blockIdx.x
			+ threadIdx.x;

		if (pixelId >= pixelCount)
			return;

		unsigned int pixel = AsUint(source, pixelId);

		for (int i = 0; i < 3; i++) // 3: don't care about alpha
		{
			target[pixelCount * i + pixelId] = GetComponent(pixel,2-i) / 255.0f; // /255.0f to re-scale from 0 to 1, 
			// 2-i to convert between RGB and BGR
		}
	}

	/*
	Convert Raw to Raw grayscale
	http://stackoverflow.com/questions/687261/converting-rgb-to-grayscale-intensity
	*/
	__global__ void RawToRawGrayscaleKernel(float *source, float *target, int pixelCount)
	{
		int pixelId = blockDim.x*blockIdx.x
			+ threadIdx.x;

		if (pixelId >= pixelCount)
			return;

		unsigned int pixel = AsUint(source, pixelId);

		unsigned int luminance = (unsigned int)
			(.2126f * GetComponent(pixel, 2) + .7152f * GetComponent(pixel, 1) + .0722f * GetComponent(pixel, 0));

		unsigned int alpha = GetComponent(pixel, 3);

		*((unsigned int*)&target[pixelId]) = luminance | (luminance << 8) | (luminance << 16) | (alpha << 24);
	}

	/*
	Convert Raw to Grayscale
	http://stackoverflow.com/questions/687261/converting-rgb-to-grayscale-intensity
	*/
	__global__ void RawToGrayscaleKernel(float *source, float *target, int pixelCount)
	{
		int pixelId = blockDim.x*blockIdx.x
			+ threadIdx.x;

		if (pixelId >= pixelCount)
			return;

		unsigned int pixel = AsUint(source, pixelId);

		float luminance =
			(.2126f * GetComponent(pixel, 2) + .7152f * GetComponent(pixel, 1) + .0722f * GetComponent(pixel, 0));

		target[pixelId] = luminance / 255.0f; // to re-scale from 0 to 1
	}

}

	.file	"tmpxft_0024c557_00000000-6_RgbaDrawing.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2177:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2177:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.globl	_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
	.type	_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff, @function
_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	DrawRgbBackgroundKernel(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L3:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff, .-_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
	.globl	DrawRgbBackgroundKernel
	.type	DrawRgbBackgroundKernel, @function
DrawRgbBackgroundKernel:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
	.cfi_endproc
.LFE2035:
	.size	DrawRgbBackgroundKernel, .-DrawRgbBackgroundKernel
	.globl	_Z42__device_stub__Z17AddRgbNoiseKernelPfiiS_iPfiiS_i
	.type	_Z42__device_stub__Z17AddRgbNoiseKernelPfiiS_iPfiiS_i, @function
_Z42__device_stub__Z17AddRgbNoiseKernelPfiiS_iPfiiS_i:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	AddRgbNoiseKernel(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L9:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z42__device_stub__Z17AddRgbNoiseKernelPfiiS_iPfiiS_i, .-_Z42__device_stub__Z17AddRgbNoiseKernelPfiiS_iPfiiS_i
	.globl	AddRgbNoiseKernel
	.type	AddRgbNoiseKernel, @function
AddRgbNoiseKernel:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z17AddRgbNoiseKernelPfiiS_iPfiiS_i
	.cfi_endproc
.LFE2037:
	.size	AddRgbNoiseKernel, .-AddRgbNoiseKernel
	.globl	_Z48__device_stub__Z19DrawRgbaColorKernelPfiiiiiifffPfiiiiiifff
	.type	_Z48__device_stub__Z19DrawRgbaColorKernelPfiiiiiifffPfiiiiiifff, @function
_Z48__device_stub__Z19DrawRgbaColorKernelPfiiiiiifffPfiiiiiifff:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movss	%xmm0, 16(%rsp)
	movss	%xmm1, 12(%rsp)
	movss	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 88(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	DrawRgbaColorKernel(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L14:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z48__device_stub__Z19DrawRgbaColorKernelPfiiiiiifffPfiiiiiifff, .-_Z48__device_stub__Z19DrawRgbaColorKernelPfiiiiiifffPfiiiiiifff
	.globl	DrawRgbaColorKernel
	.type	DrawRgbaColorKernel, @function
DrawRgbaColorKernel:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z19DrawRgbaColorKernelPfiiiiiifffPfiiiiiifff
	.cfi_endproc
.LFE2039:
	.size	DrawRgbaColorKernel, .-DrawRgbaColorKernel
	.globl	_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
	.type	_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii, @function
_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	%rsp, %rax
	movq	%rax, 112(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	DrawRgbaTextureKernel(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L19:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii, .-_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
	.globl	DrawRgbaTextureKernel
	.type	DrawRgbaTextureKernel, @function
DrawRgbaTextureKernel:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
	.cfi_endproc
.LFE2041:
	.size	DrawRgbaTextureKernel, .-DrawRgbaTextureKernel
	.globl	_Z66__device_stub__Z36DrawRgbaTextureKernelNearestNeighborPfiiiiS_iiiiPfiiiiS_iiii
	.type	_Z66__device_stub__Z36DrawRgbaTextureKernelNearestNeighborPfiiiiS_iiiiPfiiiiS_iiii, @function
_Z66__device_stub__Z36DrawRgbaTextureKernelNearestNeighborPfiiiiS_iiiiPfiiiiS_iiii:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	%rsp, %rax
	movq	%rax, 112(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	DrawRgbaTextureKernelNearestNeighbor(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L24:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z66__device_stub__Z36DrawRgbaTextureKernelNearestNeighborPfiiiiS_iiiiPfiiiiS_iiii, .-_Z66__device_stub__Z36DrawRgbaTextureKernelNearestNeighborPfiiiiS_iiiiPfiiiiS_iiii
	.globl	DrawRgbaTextureKernelNearestNeighbor
	.type	DrawRgbaTextureKernelNearestNeighbor, @function
DrawRgbaTextureKernelNearestNeighbor:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z36DrawRgbaTextureKernelNearestNeighborPfiiiiS_iiiiPfiiiiS_iiii
	.cfi_endproc
.LFE2043:
	.size	DrawRgbaTextureKernelNearestNeighbor, .-DrawRgbaTextureKernelNearestNeighbor
	.globl	_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
	.type	_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff, @function
_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	DrawMaskedColorKernelNearestNeighbor(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L29:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff, .-_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
	.globl	DrawMaskedColorKernelNearestNeighbor
	.type	DrawMaskedColorKernelNearestNeighbor, @function
DrawMaskedColorKernelNearestNeighbor:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
	.cfi_endproc
.LFE2045:
	.size	DrawMaskedColorKernelNearestNeighbor, .-DrawMaskedColorKernelNearestNeighbor
	.globl	_Z56__device_stub__Z28DrawRgbaTextureKernel2DBlockPfiiiiS_iiPfiiiiS_ii
	.type	_Z56__device_stub__Z28DrawRgbaTextureKernel2DBlockPfiiiiS_iiPfiiiiS_ii, @function
_Z56__device_stub__Z28DrawRgbaTextureKernel2DBlockPfiiiiS_iiPfiiiiS_ii:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	%rsp, %rax
	movq	%rax, 112(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	DrawRgbaTextureKernel2DBlock(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L34:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z56__device_stub__Z28DrawRgbaTextureKernel2DBlockPfiiiiS_iiPfiiiiS_ii, .-_Z56__device_stub__Z28DrawRgbaTextureKernel2DBlockPfiiiiS_iiPfiiiiS_ii
	.globl	DrawRgbaTextureKernel2DBlock
	.type	DrawRgbaTextureKernel2DBlock, @function
DrawRgbaTextureKernel2DBlock:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z28DrawRgbaTextureKernel2DBlockPfiiiiS_iiPfiiiiS_ii
	.cfi_endproc
.LFE2047:
	.size	DrawRgbaTextureKernel2DBlock, .-DrawRgbaTextureKernel2DBlock
	.globl	_Z52__device_stub__Z21DrawMaskedColorKernelPfiiiiS_iifffPfiiiiS_iifff
	.type	_Z52__device_stub__Z21DrawMaskedColorKernelPfiiiiS_iifffPfiiiiS_iifff, @function
_Z52__device_stub__Z21DrawMaskedColorKernelPfiiiiS_iifffPfiiiiS_iifff:
.LFB2048:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	DrawMaskedColorKernel(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L39:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z52__device_stub__Z21DrawMaskedColorKernelPfiiiiS_iifffPfiiiiS_iifff, .-_Z52__device_stub__Z21DrawMaskedColorKernelPfiiiiS_iifffPfiiiiS_iifff
	.globl	DrawMaskedColorKernel
	.type	DrawMaskedColorKernel, @function
DrawMaskedColorKernel:
.LFB2049:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z21DrawMaskedColorKernelPfiiiiS_iifffPfiiiiS_iifff
	.cfi_endproc
.LFE2049:
	.size	DrawMaskedColorKernel, .-DrawMaskedColorKernel
	.globl	_Z59__device_stub__Z28DrawMaskedColorKernel2DBlockPfiiiiS_iifffPfiiiiS_iifff
	.type	_Z59__device_stub__Z28DrawMaskedColorKernel2DBlockPfiiiiS_iifffPfiiiiS_iifff, @function
_Z59__device_stub__Z28DrawMaskedColorKernel2DBlockPfiiiiS_iifffPfiiiiS_iifff:
.LFB2050:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	DrawMaskedColorKernel2DBlock(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L44:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z59__device_stub__Z28DrawMaskedColorKernel2DBlockPfiiiiS_iifffPfiiiiS_iifff, .-_Z59__device_stub__Z28DrawMaskedColorKernel2DBlockPfiiiiS_iifffPfiiiiS_iifff
	.globl	DrawMaskedColorKernel2DBlock
	.type	DrawMaskedColorKernel2DBlock, @function
DrawMaskedColorKernel2DBlock:
.LFB2051:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z28DrawMaskedColorKernel2DBlockPfiiiiS_iifffPfiiiiS_iifff
	.cfi_endproc
.LFE2051:
	.size	DrawMaskedColorKernel2DBlock, .-DrawMaskedColorKernel2DBlock
	.globl	_Z53__device_stub__Z31ExtractRawComponentsToRgbKernelPfiiPfii
	.type	_Z53__device_stub__Z31ExtractRawComponentsToRgbKernelPfiiPfii, @function
_Z53__device_stub__Z31ExtractRawComponentsToRgbKernelPfiiPfii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	40(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	24(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%rsp, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	ExtractRawComponentsToRgbKernel(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L49:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z53__device_stub__Z31ExtractRawComponentsToRgbKernelPfiiPfii, .-_Z53__device_stub__Z31ExtractRawComponentsToRgbKernelPfiiPfii
	.globl	ExtractRawComponentsToRgbKernel
	.type	ExtractRawComponentsToRgbKernel, @function
ExtractRawComponentsToRgbKernel:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z31ExtractRawComponentsToRgbKernelPfiiPfii
	.cfi_endproc
.LFE2053:
	.size	ExtractRawComponentsToRgbKernel, .-ExtractRawComponentsToRgbKernel
	.globl	_Z37__device_stub__Z14RawToRgbKernelPfS_iPfS_i
	.type	_Z37__device_stub__Z14RawToRgbKernelPfS_iPfS_i, @function
_Z37__device_stub__Z14RawToRgbKernelPfS_iPfS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	RawToRgbKernel(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L54:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z37__device_stub__Z14RawToRgbKernelPfS_iPfS_i, .-_Z37__device_stub__Z14RawToRgbKernelPfS_iPfS_i
	.globl	RawToRgbKernel
	.type	RawToRgbKernel, @function
RawToRgbKernel:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z14RawToRgbKernelPfS_iPfS_i
	.cfi_endproc
.LFE2055:
	.size	RawToRgbKernel, .-RawToRgbKernel
	.globl	_Z46__device_stub__Z23RawToRawGrayscaleKernelPfS_iPfS_i
	.type	_Z46__device_stub__Z23RawToRawGrayscaleKernelPfS_iPfS_i, @function
_Z46__device_stub__Z23RawToRawGrayscaleKernelPfS_iPfS_i:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	RawToRawGrayscaleKernel(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L59:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z46__device_stub__Z23RawToRawGrayscaleKernelPfS_iPfS_i, .-_Z46__device_stub__Z23RawToRawGrayscaleKernelPfS_iPfS_i
	.globl	RawToRawGrayscaleKernel
	.type	RawToRawGrayscaleKernel, @function
RawToRawGrayscaleKernel:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z23RawToRawGrayscaleKernelPfS_iPfS_i
	.cfi_endproc
.LFE2057:
	.size	RawToRawGrayscaleKernel, .-RawToRawGrayscaleKernel
	.globl	_Z43__device_stub__Z20RawToGrayscaleKernelPfS_iPfS_i
	.type	_Z43__device_stub__Z20RawToGrayscaleKernelPfS_iPfS_i, @function
_Z43__device_stub__Z20RawToGrayscaleKernelPfS_iPfS_i:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	RawToGrayscaleKernel(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L64:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z43__device_stub__Z20RawToGrayscaleKernelPfS_iPfS_i, .-_Z43__device_stub__Z20RawToGrayscaleKernelPfS_iPfS_i
	.globl	RawToGrayscaleKernel
	.type	RawToGrayscaleKernel, @function
RawToGrayscaleKernel:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z20RawToGrayscaleKernelPfS_iPfS_i
	.cfi_endproc
.LFE2059:
	.size	RawToGrayscaleKernel, .-RawToGrayscaleKernel
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"RawToGrayscaleKernel"
.LC1:
	.string	"RawToRawGrayscaleKernel"
.LC2:
	.string	"RawToRgbKernel"
.LC3:
	.string	"ExtractRawComponentsToRgbKernel"
.LC4:
	.string	"DrawMaskedColorKernel2DBlock"
.LC5:
	.string	"DrawMaskedColorKernel"
.LC6:
	.string	"DrawRgbaTextureKernel2DBlock"
.LC7:
	.string	"DrawMaskedColorKernelNearestNeighbor"
.LC8:
	.string	"DrawRgbaTextureKernelNearestNeighbor"
.LC9:
	.string	"DrawRgbaTextureKernel"
.LC10:
	.string	"DrawRgbaColorKernel"
.LC11:
	.string	"AddRgbNoiseKernel"
.LC12:
	.string	"DrawRgbBackgroundKernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	RawToGrayscaleKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	RawToRawGrayscaleKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	RawToRgbKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	ExtractRawComponentsToRgbKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	DrawMaskedColorKernel2DBlock(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	DrawMaskedColorKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	DrawRgbaTextureKernel2DBlock(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	DrawMaskedColorKernelNearestNeighbor(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	DrawRgbaTextureKernelNearestNeighbor(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	DrawRgbaTextureKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	DrawRgbaColorKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	AddRgbNoiseKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	DrawRgbBackgroundKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>


/*
Inspired by the implementation of CustomPong.cu + GridWorld.cu

@author mp
*/
extern "C"
{
	__device__ __inline__ unsigned int AsUint(float *sourceImage, int pixelId)
	{
		return *(((unsigned int*)sourceImage) + pixelId);
	}

	__device__ __inline__ unsigned int GetComponent(unsigned int pixel, int comp)
	{
		return (pixel >> (comp * 8)) & 0xFF;
	}

	/*
	Draws a background color into a 3-component image.
	inputWidth & inputHeight: map dimensions in pixels
	gridDim.y = 3, one for each color component
	*/
	__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight,
		float r, float g, float b)
	{
		int column = threadIdx.x + blockDim.x * blockIdx.z;
		if (column >= inputWidth)
			return;

		int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel 
			+ column;

		int imagePixels = inputWidth * inputHeight; 

		if (id < 3*imagePixels) // 3 for RGB 
		{
			float color = 0.0f;
			switch (blockIdx.y)
			{
			case 0:
				color = r;
				break;
			case 1:
				color = g;
				break;
			case 2:
				color = b;
				break;
			}
			target[id] = color;
		}
	}

	/*
	Adds noise into a 3-component image.
	inputWidth & inputHeight: map dimensions in pixels
	*/
	__global__ void AddRgbNoiseKernel(float *target, int inputWidth, int inputHeight, float *randoms, int isBlackAndWhiteNoise)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int imagePixels = inputWidth * inputHeight;

		if (id < imagePixels)
		{
			unsigned int tg = *((unsigned int*)(&target[id]));

			int random = randoms[id];

			int blue = (tg >> 0) & (0xFF);
			blue += random;
			blue = blue < 255 ? blue : 255;
			blue = blue > 0 ? blue : 0;

			int green = ((tg >> 8) & (0xFF));
			green += (isBlackAndWhiteNoise ? random : (int)(randoms[id + imagePixels]));
			green = green < 255 ? green : 255;
			green = green > 0 ? green : 0;

			int red = ((tg >> 16) & (0xFF));
			red += (isBlackAndWhiteNoise ? random : (int)(randoms[id + imagePixels * 2]));
			red = red < 255 ? red : 255;
			red = red > 0 ? red : 0;

			// alpha is the last channel (<< 24)
			unsigned int tmp = (*((unsigned int *)(&blue)) << 0)
						     | (*((unsigned int *)(&green)) << 8)
							 | (*((unsigned int *)(&red)) << 16);

			target[id] = *((float *)(&tmp));
		}
	}

	/* Fill specified rectangle with color */
	__global__ void DrawRgbaColorKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		int areaWidth, int areaHeight, float r, float g, float b)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = areaWidth * areaHeight;

		int idTextureRgb = id / texturePixels;
		int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
		int idTextureY = idTexturePixel / areaWidth;
		int idTextureX = (idTexturePixel - idTextureY * areaWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idTextureRgb < 3) // 3 channels that we will write to
		{
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				float color = 0.0f;
				switch (idTextureRgb)
				{
				case 0:
					color = r;
					break;
				case 1:
					color = g;
					break;
				case 2:
					color = b;
					break;
				}
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				target[tIndex] = color;
			}
		}
	}

	/*
	Draws a texture into a 3-component target. RGBA. Checks bounds.
	*/
	__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x 
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = id / texturePixels;
		int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
		int idTextureY = idTexturePixel / textureWidth; 
		int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idTextureRgb < 3) // 3 channels that we will write to
		{
			// the texture is in BGR format, we want RGB
			switch (idTextureRgb)
			{
			case 0: // R
				idTextureRgb = 2; // B
				break;
			case 2: // B
				idTextureRgb = 0; // R
				break;
			}
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];
				target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
			}
		}
	}

	/*
	Draws a texture into a 3-component target. RGBA. Checks bounds. Stretches the texture.
	*/
	__global__ void DrawRgbaTextureKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight)
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int objectPixels = objectWidth * objectHeight;

		int idObjectRgb = id / objectPixels;
		int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
		int idObjectY = idObjectPixel / objectWidth;
		int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idObjectRgb < 3) // 3 channels that we will write to
		{
			int targetRgb = idObjectRgb;
			// the texture is in BGR format, we want RGB
			switch (idObjectRgb)
			{
			case 0: // R
				targetRgb = 2; // B
				break;
			case 2: // B
				targetRgb = 0; // R
				break;
			}
			// if the object pixel offset by inputX, inputY, lies inside the target
			if (idObjectX + inputX < targetWidth &&
				idObjectX + inputX >= 0 &&
				idObjectY + inputY < targetHeight &&
				idObjectY + inputY >= 0)
			{
				// nearest neighbor texture X,Y:
				int textureX = textureWidth * idObjectX / objectWidth;
				int textureY = textureHeight * idObjectY / objectHeight;
				int textureId = textureY * textureWidth + textureX;
				
				int rgbIndex = textureId + idObjectRgb * texturePixels;
				float textureValue = texture[rgbIndex];

				int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
				int aIndex = textureId + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];
				target[tIndex] = target[tIndex] * (1.0f - a) + a * textureValue;
			}
		}
	}

	/*
	Same as DrawRgbaTextureKernelNearestNeighbor, but texture = mask and texture's pixel values are replaced by a single color
	*/
	__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, 
		float r, float g, float b ) // texture = mask
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int objectPixels = objectWidth * objectHeight;

		int idObjectRgb = id / objectPixels;
		int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
		int idObjectY = idObjectPixel / objectWidth;
		int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster


		if (idObjectRgb < 3) // 3 channels that we will write to
		{
			int targetRgb = idObjectRgb;
			// the texture is in BGR format, we want RGB
			switch (idObjectRgb)
			{
			case 0: // R
				targetRgb = 2; // B
				break;
			case 2: // B
				targetRgb = 0; // R
				break;
			}
			// if the object pixel offset by inputX, inputY, lies inside the target
			if (idObjectX + inputX < targetWidth &&
				idObjectX + inputX >= 0 &&
				idObjectY + inputY < targetHeight &&
				idObjectY + inputY >= 0)
			{
				// nearest neighbor texture X,Y:
				int textureX = textureWidth * idObjectX / objectWidth;
				int textureY = textureHeight * idObjectY / objectHeight;
				int textureId = textureY * textureWidth + textureX;

				int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
				int aIndex = textureId + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];

				if (a > 0) // mask allows color here
				{
					// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
					target[tIndex] = target[tIndex] * (1.0f - a);
					switch (idObjectRgb)
					{
					case 0:
						target[tIndex] += a*r;
						break;
					case 1:
						target[tIndex] += a*g;
						break;
					case 2:
					default:
						target[tIndex] += a*b;
						break;
					}
				}
			}
		}
	}

	/*
	Optimized version of DrawRgbaTextureKernel : avoids division operations (~30% speedup)
	The width of the texture is in blockDim.x
	The height of the texture is distributed between blockDim.y and gridDim.x
	*/
	__global__ void DrawRgbaTextureKernel2DBlock(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *texture, int textureWidth, int textureHeight)
	{
		int id = blockDim.x * blockDim.y * (blockIdx.y * gridDim.x + blockIdx.x)
			+ blockDim.x * threadIdx.y
			+ threadIdx.x; // 2D grid of 2D blocks; block dimension x = texture width; 
		// grid dimension x + block dimension y = texture height

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = blockIdx.y;
		int idTexturePixel = (id - idTextureRgb * texturePixels);
		int idTextureY = blockIdx.x * blockDim.y + threadIdx.y;
		int idTextureX = threadIdx.x;


		if (idTextureRgb < 3) // 3 channels that we will write to
		{
			// the texture is in BGR format, we want RGB
			switch (idTextureRgb)
			{
			case 0: // R
				idTextureRgb = 2; // B
				break;
			case 2: // B
				idTextureRgb = 0; // R
				break;
			}
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = texture[aIndex];
				target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
			}
		}
	}

	/*
	Draws an RGB color into the masked area. The color is drawn in each pixel that has non-0 alpha.
	*/
	__global__ void DrawMaskedColorKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *textureMask, int textureWidth, int textureHeight, float r, float g, float b) 
	{
		int id = blockDim.x * blockIdx.y * gridDim.x
			+ blockDim.x * blockIdx.x
			+ threadIdx.x;

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = id / texturePixels;
		int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
		int idTextureY = idTexturePixel / textureWidth;
		int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster

		if (idTextureRgb < 3) // only RGB channels are interesting
		{
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = textureMask[aIndex];

				if (a > 0) // mask allows color here
				{
					switch (idTextureRgb)
					{
					case 0:
						target[tIndex] = r;
						break;
					case 1:
						target[tIndex] = g;
						break;
					case 2:
					default:
						target[tIndex] = b;
						break;
					}
				}
			}
		}
	}

	/*
	Optimized version of DrawMaskedColorKernel : avoids division operations (~30% speedup)
	The width of the texture is in blockDim.x
	The height of the texture is distributed between blockDim.y and gridDim.x
	*/
	__global__ void DrawMaskedColorKernel2DBlock(float *target, int targetWidth, int targetHeight, int inputX, int inputY,
		float *textureMask, int textureWidth, int textureHeight, float r, float g, float b)
	{
		int id = blockDim.x * blockDim.y * (blockIdx.y * gridDim.x + blockIdx.x)
			+ blockDim.x * threadIdx.y
			+ threadIdx.x; // 2D grid of 2D blocks; block dimension x = texture width; 
		// grid dimension x + block dimension y = texture height

		int targetPixels = targetWidth * targetHeight;

		int texturePixels = textureWidth * textureHeight;

		int idTextureRgb = blockIdx.y;
		int idTexturePixel = (id - idTextureRgb * texturePixels);
		int idTextureY = blockIdx.x * blockDim.y + threadIdx.y;
		int idTextureX = threadIdx.x;


		if (idTextureRgb < 3) // only RGB channels are interesting
		{
			// if the texture pixel offset by inputX, inputY, lies inside the target
			if (idTextureX + inputX < targetWidth &&
				idTextureX + inputX >= 0 &&
				idTextureY + inputY < targetHeight &&
				idTextureY + inputY >= 0)
			{
				int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
				int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
				float a = textureMask[aIndex];

				if (a > 0) // mask allows color here
				{
					switch (idTextureRgb)
					{
					case 0:
						target[tIndex] = r;
						break;
					case 1:
						target[tIndex] = g;
						break;
					case 2:
					default:
						target[tIndex] = b;
						break;
					}
				}
			}
		}
	}

	/*
	Convert Raw to RGB
	*/
	__global__ void ExtractRawComponentsToRgbKernel(float *target, int inputWidth, int inputHeight)
	{
		int pixelId = blockDim.x*blockIdx.y*gridDim.x
			+ blockDim.x*blockIdx.x
			+ threadIdx.x;

		int imagePixels = inputWidth * inputHeight;

		if (pixelId >= imagePixels)
			return;

		unsigned int* uTarget = (unsigned int*)target;
		unsigned int pixel = uTarget[pixelId];

		for (int i = 2; i >= 0; i--)
		{
			unsigned int component = pixel;
			component = component >> (8 * (2-i)); // 2-i == RGB -> BGR
			component = component & 0xFF;
			target[imagePixels * i + pixelId] = ((float)component)/255.0f;
			__syncthreads();
		}
	}

	/*
	Convert Raw to RGB
	*/
	__global__ void RawToRgbKernel(float *source, float *target, int pixelCount)
	{
		int pixelId = blockDim.x*blockIdx.x
			+ threadIdx.x;

		if (pixelId >= pixelCount)
			return;

		unsigned int pixel = AsUint(source, pixelId);

		for (int i = 0; i < 3; i++) // 3: don't care about alpha
		{
			target[pixelCount * i + pixelId] = GetComponent(pixel,2-i) / 255.0f; // /255.0f to re-scale from 0 to 1, 
			// 2-i to convert between RGB and BGR
		}
	}

	/*
	Convert Raw to Raw grayscale
	http://stackoverflow.com/questions/687261/converting-rgb-to-grayscale-intensity
	*/
	__global__ void RawToRawGrayscaleKernel(float *source, float *target, int pixelCount)
	{
		int pixelId = blockDim.x*blockIdx.x
			+ threadIdx.x;

		if (pixelId >= pixelCount)
			return;

		unsigned int pixel = AsUint(source, pixelId);

		unsigned int luminance = (unsigned int)
			(.2126f * GetComponent(pixel, 2) + .7152f * GetComponent(pixel, 1) + .0722f * GetComponent(pixel, 0));

		unsigned int alpha = GetComponent(pixel, 3);

		*((unsigned int*)&target[pixelId]) = luminance | (luminance << 8) | (luminance << 16) | (alpha << 24);
	}

	/*
	Convert Raw to Grayscale
	http://stackoverflow.com/questions/687261/converting-rgb-to-grayscale-intensity
	*/
	__global__ void RawToGrayscaleKernel(float *source, float *target, int pixelCount)
	{
		int pixelId = blockDim.x*blockIdx.x
			+ threadIdx.x;

		if (pixelId >= pixelCount)
			return;

		unsigned int pixel = AsUint(source, pixelId);

		float luminance =
			(.2126f * GetComponent(pixel, 2) + .7152f * GetComponent(pixel, 1) + .0722f * GetComponent(pixel, 0));

		target[pixelId] = luminance / 255.0f; // to re-scale from 0 to 1
	}

}

	.text
	.file	"RgbaDrawing.hip"
	.globl	__device_stub__DrawRgbBackgroundKernel # -- Begin function __device_stub__DrawRgbBackgroundKernel
	.type	__device_stub__DrawRgbBackgroundKernel,@function
__device_stub__DrawRgbBackgroundKernel: # @__device_stub__DrawRgbBackgroundKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	8(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	4(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rdi, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawRgbBackgroundKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__DrawRgbBackgroundKernel, .Lfunc_end0-__device_stub__DrawRgbBackgroundKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__AddRgbNoiseKernel # -- Begin function __device_stub__AddRgbNoiseKernel
	.type	__device_stub__AddRgbNoiseKernel,@function
__device_stub__AddRgbNoiseKernel:       # @__device_stub__AddRgbNoiseKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$AddRgbNoiseKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__AddRgbNoiseKernel, .Lfunc_end1-__device_stub__AddRgbNoiseKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DrawRgbaColorKernel # -- Begin function __device_stub__DrawRgbaColorKernel
	.type	__device_stub__DrawRgbaColorKernel,@function
__device_stub__DrawRgbaColorKernel:     # @__device_stub__DrawRgbaColorKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	36(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	28(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	20(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	16(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	12(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	8(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	movq	%r10, 64(%rbx)
	movq	%r11, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	48(%rsp), %r12
	leaq	40(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawRgbaColorKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__DrawRgbaColorKernel, .Lfunc_end2-__device_stub__DrawRgbaColorKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DrawRgbaTextureKernel # -- Begin function __device_stub__DrawRgbaTextureKernel
	.type	__device_stub__DrawRgbaTextureKernel,@function
__device_stub__DrawRgbaTextureKernel:   # @__device_stub__DrawRgbaTextureKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawRgbaTextureKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__DrawRgbaTextureKernel, .Lfunc_end3-__device_stub__DrawRgbaTextureKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DrawRgbaTextureKernelNearestNeighbor # -- Begin function __device_stub__DrawRgbaTextureKernelNearestNeighbor
	.type	__device_stub__DrawRgbaTextureKernelNearestNeighbor,@function
__device_stub__DrawRgbaTextureKernelNearestNeighbor: # @__device_stub__DrawRgbaTextureKernelNearestNeighbor
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawRgbaTextureKernelNearestNeighbor, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__DrawRgbaTextureKernelNearestNeighbor, .Lfunc_end4-__device_stub__DrawRgbaTextureKernelNearestNeighbor
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DrawMaskedColorKernelNearestNeighbor # -- Begin function __device_stub__DrawMaskedColorKernelNearestNeighbor
	.type	__device_stub__DrawMaskedColorKernelNearestNeighbor,@function
__device_stub__DrawMaskedColorKernelNearestNeighbor: # @__device_stub__DrawMaskedColorKernelNearestNeighbor
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	28(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	24(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r9, 80(%rbx)
	movq	%r10, 88(%rbx)
	movq	%r11, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawMaskedColorKernelNearestNeighbor, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub__DrawMaskedColorKernelNearestNeighbor, .Lfunc_end5-__device_stub__DrawMaskedColorKernelNearestNeighbor
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DrawRgbaTextureKernel2DBlock # -- Begin function __device_stub__DrawRgbaTextureKernel2DBlock
	.type	__device_stub__DrawRgbaTextureKernel2DBlock,@function
__device_stub__DrawRgbaTextureKernel2DBlock: # @__device_stub__DrawRgbaTextureKernel2DBlock
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawRgbaTextureKernel2DBlock, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	__device_stub__DrawRgbaTextureKernel2DBlock, .Lfunc_end6-__device_stub__DrawRgbaTextureKernel2DBlock
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DrawMaskedColorKernel # -- Begin function __device_stub__DrawMaskedColorKernel
	.type	__device_stub__DrawMaskedColorKernel,@function
__device_stub__DrawMaskedColorKernel:   # @__device_stub__DrawMaskedColorKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	28(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	24(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r10, 72(%rbx)
	movq	%r11, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawMaskedColorKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	__device_stub__DrawMaskedColorKernel, .Lfunc_end7-__device_stub__DrawMaskedColorKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__DrawMaskedColorKernel2DBlock # -- Begin function __device_stub__DrawMaskedColorKernel2DBlock
	.type	__device_stub__DrawMaskedColorKernel2DBlock,@function
__device_stub__DrawMaskedColorKernel2DBlock: # @__device_stub__DrawMaskedColorKernel2DBlock
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	28(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	24(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r10, 72(%rbx)
	movq	%r11, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$DrawMaskedColorKernel2DBlock, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	__device_stub__DrawMaskedColorKernel2DBlock, .Lfunc_end8-__device_stub__DrawMaskedColorKernel2DBlock
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__ExtractRawComponentsToRgbKernel # -- Begin function __device_stub__ExtractRawComponentsToRgbKernel
	.type	__device_stub__ExtractRawComponentsToRgbKernel,@function
__device_stub__ExtractRawComponentsToRgbKernel: # @__device_stub__ExtractRawComponentsToRgbKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$ExtractRawComponentsToRgbKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	__device_stub__ExtractRawComponentsToRgbKernel, .Lfunc_end9-__device_stub__ExtractRawComponentsToRgbKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__RawToRgbKernel   # -- Begin function __device_stub__RawToRgbKernel
	.type	__device_stub__RawToRgbKernel,@function
__device_stub__RawToRgbKernel:          # @__device_stub__RawToRgbKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$RawToRgbKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	__device_stub__RawToRgbKernel, .Lfunc_end10-__device_stub__RawToRgbKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__RawToRawGrayscaleKernel # -- Begin function __device_stub__RawToRawGrayscaleKernel
	.type	__device_stub__RawToRawGrayscaleKernel,@function
__device_stub__RawToRawGrayscaleKernel: # @__device_stub__RawToRawGrayscaleKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$RawToRawGrayscaleKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	__device_stub__RawToRawGrayscaleKernel, .Lfunc_end11-__device_stub__RawToRawGrayscaleKernel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__RawToGrayscaleKernel # -- Begin function __device_stub__RawToGrayscaleKernel
	.type	__device_stub__RawToGrayscaleKernel,@function
__device_stub__RawToGrayscaleKernel:    # @__device_stub__RawToGrayscaleKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$RawToGrayscaleKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	__device_stub__RawToGrayscaleKernel, .Lfunc_end12-__device_stub__RawToGrayscaleKernel
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB13_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB13_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawRgbBackgroundKernel, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$AddRgbNoiseKernel, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawRgbaColorKernel, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawRgbaTextureKernel, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawRgbaTextureKernelNearestNeighbor, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawMaskedColorKernelNearestNeighbor, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawRgbaTextureKernel2DBlock, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawMaskedColorKernel, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$DrawMaskedColorKernel2DBlock, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$ExtractRawComponentsToRgbKernel, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$RawToRgbKernel, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$RawToRawGrayscaleKernel, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$RawToGrayscaleKernel, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end13:
	.size	__hip_module_ctor, .Lfunc_end13-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB14_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB14_2:
	retq
.Lfunc_end14:
	.size	__hip_module_dtor, .Lfunc_end14-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	DrawRgbBackgroundKernel,@object # @DrawRgbBackgroundKernel
	.section	.rodata,"a",@progbits
	.globl	DrawRgbBackgroundKernel
	.p2align	3, 0x0
DrawRgbBackgroundKernel:
	.quad	__device_stub__DrawRgbBackgroundKernel
	.size	DrawRgbBackgroundKernel, 8

	.type	AddRgbNoiseKernel,@object       # @AddRgbNoiseKernel
	.globl	AddRgbNoiseKernel
	.p2align	3, 0x0
AddRgbNoiseKernel:
	.quad	__device_stub__AddRgbNoiseKernel
	.size	AddRgbNoiseKernel, 8

	.type	DrawRgbaColorKernel,@object     # @DrawRgbaColorKernel
	.globl	DrawRgbaColorKernel
	.p2align	3, 0x0
DrawRgbaColorKernel:
	.quad	__device_stub__DrawRgbaColorKernel
	.size	DrawRgbaColorKernel, 8

	.type	DrawRgbaTextureKernel,@object   # @DrawRgbaTextureKernel
	.globl	DrawRgbaTextureKernel
	.p2align	3, 0x0
DrawRgbaTextureKernel:
	.quad	__device_stub__DrawRgbaTextureKernel
	.size	DrawRgbaTextureKernel, 8

	.type	DrawRgbaTextureKernelNearestNeighbor,@object # @DrawRgbaTextureKernelNearestNeighbor
	.globl	DrawRgbaTextureKernelNearestNeighbor
	.p2align	3, 0x0
DrawRgbaTextureKernelNearestNeighbor:
	.quad	__device_stub__DrawRgbaTextureKernelNearestNeighbor
	.size	DrawRgbaTextureKernelNearestNeighbor, 8

	.type	DrawMaskedColorKernelNearestNeighbor,@object # @DrawMaskedColorKernelNearestNeighbor
	.globl	DrawMaskedColorKernelNearestNeighbor
	.p2align	3, 0x0
DrawMaskedColorKernelNearestNeighbor:
	.quad	__device_stub__DrawMaskedColorKernelNearestNeighbor
	.size	DrawMaskedColorKernelNearestNeighbor, 8

	.type	DrawRgbaTextureKernel2DBlock,@object # @DrawRgbaTextureKernel2DBlock
	.globl	DrawRgbaTextureKernel2DBlock
	.p2align	3, 0x0
DrawRgbaTextureKernel2DBlock:
	.quad	__device_stub__DrawRgbaTextureKernel2DBlock
	.size	DrawRgbaTextureKernel2DBlock, 8

	.type	DrawMaskedColorKernel,@object   # @DrawMaskedColorKernel
	.globl	DrawMaskedColorKernel
	.p2align	3, 0x0
DrawMaskedColorKernel:
	.quad	__device_stub__DrawMaskedColorKernel
	.size	DrawMaskedColorKernel, 8

	.type	DrawMaskedColorKernel2DBlock,@object # @DrawMaskedColorKernel2DBlock
	.globl	DrawMaskedColorKernel2DBlock
	.p2align	3, 0x0
DrawMaskedColorKernel2DBlock:
	.quad	__device_stub__DrawMaskedColorKernel2DBlock
	.size	DrawMaskedColorKernel2DBlock, 8

	.type	ExtractRawComponentsToRgbKernel,@object # @ExtractRawComponentsToRgbKernel
	.globl	ExtractRawComponentsToRgbKernel
	.p2align	3, 0x0
ExtractRawComponentsToRgbKernel:
	.quad	__device_stub__ExtractRawComponentsToRgbKernel
	.size	ExtractRawComponentsToRgbKernel, 8

	.type	RawToRgbKernel,@object          # @RawToRgbKernel
	.globl	RawToRgbKernel
	.p2align	3, 0x0
RawToRgbKernel:
	.quad	__device_stub__RawToRgbKernel
	.size	RawToRgbKernel, 8

	.type	RawToRawGrayscaleKernel,@object # @RawToRawGrayscaleKernel
	.globl	RawToRawGrayscaleKernel
	.p2align	3, 0x0
RawToRawGrayscaleKernel:
	.quad	__device_stub__RawToRawGrayscaleKernel
	.size	RawToRawGrayscaleKernel, 8

	.type	RawToGrayscaleKernel,@object    # @RawToGrayscaleKernel
	.globl	RawToGrayscaleKernel
	.p2align	3, 0x0
RawToGrayscaleKernel:
	.quad	__device_stub__RawToGrayscaleKernel
	.size	RawToGrayscaleKernel, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"DrawRgbBackgroundKernel"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"AddRgbNoiseKernel"
	.size	.L__unnamed_2, 18

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"DrawRgbaColorKernel"
	.size	.L__unnamed_3, 20

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"DrawRgbaTextureKernel"
	.size	.L__unnamed_4, 22

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"DrawRgbaTextureKernelNearestNeighbor"
	.size	.L__unnamed_5, 37

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"DrawMaskedColorKernelNearestNeighbor"
	.size	.L__unnamed_6, 37

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"DrawRgbaTextureKernel2DBlock"
	.size	.L__unnamed_7, 29

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"DrawMaskedColorKernel"
	.size	.L__unnamed_8, 22

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"DrawMaskedColorKernel2DBlock"
	.size	.L__unnamed_9, 29

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"ExtractRawComponentsToRgbKernel"
	.size	.L__unnamed_10, 32

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"RawToRgbKernel"
	.size	.L__unnamed_11, 15

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"RawToRawGrayscaleKernel"
	.size	.L__unnamed_12, 24

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"RawToGrayscaleKernel"
	.size	.L__unnamed_13, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__DrawRgbBackgroundKernel
	.addrsig_sym __device_stub__AddRgbNoiseKernel
	.addrsig_sym __device_stub__DrawRgbaColorKernel
	.addrsig_sym __device_stub__DrawRgbaTextureKernel
	.addrsig_sym __device_stub__DrawRgbaTextureKernelNearestNeighbor
	.addrsig_sym __device_stub__DrawMaskedColorKernelNearestNeighbor
	.addrsig_sym __device_stub__DrawRgbaTextureKernel2DBlock
	.addrsig_sym __device_stub__DrawMaskedColorKernel
	.addrsig_sym __device_stub__DrawMaskedColorKernel2DBlock
	.addrsig_sym __device_stub__ExtractRawComponentsToRgbKernel
	.addrsig_sym __device_stub__RawToRgbKernel
	.addrsig_sym __device_stub__RawToRawGrayscaleKernel
	.addrsig_sym __device_stub__RawToGrayscaleKernel
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym DrawRgbBackgroundKernel
	.addrsig_sym AddRgbNoiseKernel
	.addrsig_sym DrawRgbaColorKernel
	.addrsig_sym DrawRgbaTextureKernel
	.addrsig_sym DrawRgbaTextureKernelNearestNeighbor
	.addrsig_sym DrawMaskedColorKernelNearestNeighbor
	.addrsig_sym DrawRgbaTextureKernel2DBlock
	.addrsig_sym DrawMaskedColorKernel
	.addrsig_sym DrawMaskedColorKernel2DBlock
	.addrsig_sym ExtractRawComponentsToRgbKernel
	.addrsig_sym RawToRgbKernel
	.addrsig_sym RawToRawGrayscaleKernel
	.addrsig_sym RawToGrayscaleKernel
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	DrawRgbBackgroundKernel ; -- Begin function DrawRgbBackgroundKernel
	.globl	DrawRgbBackgroundKernel
	.p2align	8
	.type	DrawRgbBackgroundKernel,@function
DrawRgbBackgroundKernel:                ; @DrawRgbBackgroundKernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s8, v[0:1]
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_i32_e64 s4, v2
	s_cbranch_execz .LBB0_15
; %bb.1:
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s13
	v_mad_u64_u32 v[0:1], null, s2, s4, v[2:3]
	s_mul_i32 s2, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s2, s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.2:                                ; %NodeBlock35
	s_cmp_lt_i32 s14, 1
	s_cbranch_scc1 .LBB0_6
; %bb.3:                                ; %NodeBlock
	s_cmp_lt_i32 s14, 2
	s_cbranch_scc1 .LBB0_7
; %bb.4:                                ; %LeafBlock33
	s_mov_b32 s4, 0
	s_cmp_eq_u32 s14, 2
	s_mov_b32 s2, 0
	s_cbranch_scc0 .LBB0_8
; %bb.5:
	s_mov_b32 s2, s3
	s_branch .LBB0_8
.LBB0_6:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr2
	s_branch .LBB0_11
.LBB0_7:
	s_mov_b32 s4, -1
                                        ; implicit-def: $sgpr2
.LBB0_8:                                ; %Flow37
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_10
; %bb.9:
	s_mov_b32 s2, s7
.LBB0_10:                               ; %Flow38
	s_mov_b32 s3, 0
.LBB0_11:                               ; %Flow40
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_14
; %bb.12:                               ; %LeafBlock
	s_cmp_lg_u32 s14, 0
	s_mov_b32 s2, 0
	s_cbranch_scc1 .LBB0_14
; %bb.13:
	s_mov_b32 s2, s6
.LBB0_14:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v2, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawRgbBackgroundKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	DrawRgbBackgroundKernel, .Lfunc_end0-DrawRgbBackgroundKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	AddRgbNoiseKernel       ; -- Begin function AddRgbNoiseKernel
	.globl	AddRgbNoiseKernel
	.p2align	8
	.type	AddRgbNoiseKernel,@function
AddRgbNoiseKernel:                      ; @AddRgbNoiseKernel
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x20
	s_load_b32 s5, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s4, s15
	s_and_b32 s5, s5, 0xffff
	s_add_i32 s4, s4, s14
	s_mul_i32 s2, s3, s2
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB1_6
; %bb.1:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b64 s[6:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b32 s1, s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_cmp_eq_u32 s1, 0
	global_load_b32 v5, v[0:1], off
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(1)
	v_cvt_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v6, v4
	s_cbranch_scc1 .LBB1_3
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[2:3], 2
	v_add_co_u32 v6, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cvt_i32_f32_e32 v6, v6
.LBB1_3:
	v_mov_b32_e32 v7, v4
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_5
; %bb.4:
	s_lshl_b32 s0, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_i32_f32_e32 v7, v2
.LBB1_5:
	s_waitcnt vmcnt(0)
	v_bfe_u32 v2, v5, 8, 8
	v_bfe_u32 v3, v5, 16, 8
	v_and_b32_e32 v5, 0xff, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, v6, v2
	v_add_nc_u32_e32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, v5, v4
	v_med3_i32 v2, v2, 0, 0xff
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_med3_i32 v3, v3, 0, 0xff
	v_med3_i32 v4, v4, 0, 0xff
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v2, 8, v2
	v_lshlrev_b32_e32 v3, 16, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v2, v2, v4, v3
	global_store_b32 v[0:1], v2, off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel AddRgbNoiseKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	AddRgbNoiseKernel, .Lfunc_end1-AddRgbNoiseKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 436
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	DrawRgbaColorKernel     ; -- Begin function DrawRgbaColorKernel
	.globl	DrawRgbaColorKernel
	.p2align	8
	.type	DrawRgbaColorKernel,@function
DrawRgbaColorKernel:                    ; @DrawRgbaColorKernel
; %bb.0:
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s12, s[0:1], 0x30
	s_load_b32 s13, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s12, s15
	s_mul_i32 s2, s9, s8
	s_and_b32 s13, s13, 0xffff
	s_ashr_i32 s3, s2, 31
	s_add_i32 s12, s12, s14
	s_add_i32 s9, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s9, s9, s3
	v_cvt_f32_u32_e32 v1, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s12, s13, v[0:1]
	s_sub_i32 s12, 0, s9
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s12, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	s_mov_b32 s3, exec_lo
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s9
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s9, v3
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	v_cmpx_gt_i32_e32 3, v2
	s_cbranch_execz .LBB2_12
; %bb.1:
	s_ashr_i32 s3, s8, 31
	v_mul_lo_u32 v3, v2, s2
	s_add_i32 s9, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s9, s9, s3
	v_cvt_f32_u32_e32 v0, s9
	s_sub_i32 s2, 0, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v1, v3
	v_rcp_iflag_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v5, v3, v1
	v_xor_b32_e32 v5, v5, v1
	v_xor_b32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	s_load_b32 s3, s[0:1], 0x28
	v_mul_lo_u32 v4, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v0, v4
	v_add_nc_u32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v5, v0
	v_mul_lo_u32 v4, v0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v5, v4
	v_subrev_nc_u32_e32 v6, s9, v4
	v_cmp_le_u32_e32 vcc_lo, s9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s9, v4
	v_add_nc_u32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_xor_b32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v0, v1
	v_mul_lo_u32 v0, v1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v3, v0
	v_add_nc_u32_e32 v0, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_lt_i32_e64 s2, -1, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_12
; %bb.2:
	v_add_nc_u32_e32 v1, s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s5, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_12
; %bb.3:                                ; %NodeBlock75
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr3
	v_cmpx_lt_i32_e32 0, v2
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB2_7
; %bb.4:                                ; %NodeBlock
	s_mov_b32 s6, exec_lo
	v_cmpx_lt_i32_e32 1, v2
	s_xor_b32 s6, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_saveexec_b32 s6, s6
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v3, s3
	s_xor_b32 exec_lo, exec_lo, s6
; %bb.5:
	v_mov_b32_e32 v3, s11
; %bb.6:                                ; %Flow77
	s_or_b32 exec_lo, exec_lo, s6
.LBB2_7:                                ; %Flow79
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB2_11
; %bb.8:                                ; %LeafBlock
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v2
; %bb.9:
	v_mov_b32_e32 v3, s10
; %bb.10:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_11:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_mad_u64_u32 v[4:5], null, v2, s5, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, v4, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB2_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawRgbaColorKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	DrawRgbaColorKernel, .Lfunc_end2-DrawRgbaColorKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 716
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	DrawRgbaTextureKernel   ; -- Begin function DrawRgbaTextureKernel
	.globl	DrawRgbaTextureKernel
	.p2align	8
	.type	DrawRgbaTextureKernel,@function
DrawRgbaTextureKernel:                  ; @DrawRgbaTextureKernel
; %bb.0:
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b32 s4, s[0:1], 0x28
	s_load_b32 s5, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s2
	s_mul_i32 s4, s4, s15
	s_ashr_i32 s6, s3, 31
	s_and_b32 s5, s5, 0xffff
	s_add_i32 s7, s3, s6
	s_add_i32 s4, s4, s14
	s_xor_b32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s7
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	s_sub_i32 s4, 0, s7
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s4, v3
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s7
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s7, v3
	v_cmp_le_u32_e32 vcc_lo, s7, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s7, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	v_cmpx_gt_i32_e32 3, v0
	s_cbranch_execz .LBB3_10
; %bb.1:                                ; %NodeBlock
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $sgpr5
	v_cmpx_lt_i32_e32 1, v0
	s_xor_b32 s4, exec_lo, s4
; %bb.2:
	s_mov_b32 s5, 0
; %bb.3:                                ; %Flow77
	s_or_saveexec_b32 s4, s4
	v_mov_b32_e32 v5, s5
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB3_7
; %bb.4:                                ; %LeafBlock
	v_mov_b32_e32 v5, v0
	s_mov_b32 s5, exec_lo
	v_cmpx_eq_u32_e32 0, v0
; %bb.5:
	v_mov_b32_e32 v5, 2
; %bb.6:                                ; %Flow76
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_7:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	s_ashr_i32 s4, s2, 31
	v_mul_lo_u32 v0, v0, s3
	s_add_i32 s5, s2, s4
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v3, s5
	s_sub_i32 s6, 0, s5
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	v_ashrrev_i32_e32 v6, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v0, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_xor_b32_e32 v7, v7, v6
	v_xor_b32_e32 v6, s4, v6
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s6, v3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_hi_u32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s5
	v_sub_nc_u32_e32 v4, v7, v4
	v_add_nc_u32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s5, v4
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	v_dual_cndmask_b32 v4, v4, v8 :: v_dual_cndmask_b32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	v_add_nc_u32_e32 v7, 1, v3
	s_load_b128 s[4:7], s[0:1], 0x8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	v_xor_b32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v3, v6
	v_mul_lo_u32 v3, v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, s6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v3
	v_cmp_lt_i32_e64 s2, -1, v3
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB3_10
; %bb.8:
	v_add_nc_u32_e32 v4, s7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s5, v4
	v_cmp_lt_i32_e64 s2, -1, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB3_10
; %bb.9:
	s_load_b64 s[6:7], s[0:1], 0x18
	v_mad_u64_u32 v[8:9], null, v5, s5, v[4:5]
	v_mad_u64_u32 v[6:7], null, s3, 3, v[0:1]
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v8, s4, v[3:4]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v6
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[2:3], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v4, 1.0, v6
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v0, v6, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, v1, v4
	global_store_b32 v[2:3], v0, off
.LBB3_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawRgbaTextureKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	DrawRgbaTextureKernel, .Lfunc_end3-DrawRgbaTextureKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 800
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	DrawRgbaTextureKernelNearestNeighbor ; -- Begin function DrawRgbaTextureKernelNearestNeighbor
	.globl	DrawRgbaTextureKernelNearestNeighbor
	.p2align	8
	.type	DrawRgbaTextureKernelNearestNeighbor,@function
DrawRgbaTextureKernelNearestNeighbor:   ; @DrawRgbaTextureKernelNearestNeighbor
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x20
	s_load_b32 s3, s[0:1], 0x30
	s_load_b32 s8, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s7, s6
	s_mul_i32 s3, s3, s15
	s_ashr_i32 s9, s2, 31
	s_and_b32 s8, s8, 0xffff
	s_add_i32 s10, s2, s9
	s_add_i32 s3, s3, s14
	s_xor_b32 s10, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s10
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s3, s8, v[0:1]
	s_sub_i32 s3, 0, s10
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s3, v3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s9, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s10
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s10, v3
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	v_cmpx_gt_i32_e32 3, v2
	s_cbranch_execz .LBB4_10
; %bb.1:                                ; %NodeBlock
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $sgpr8
	v_cmpx_lt_i32_e32 1, v2
	s_xor_b32 s3, exec_lo, s3
; %bb.2:
	s_mov_b32 s8, 0
; %bb.3:                                ; %Flow99
	s_or_saveexec_b32 s3, s3
	v_mov_b32_e32 v3, s8
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB4_7
; %bb.4:                                ; %LeafBlock
	v_mov_b32_e32 v3, v2
	s_mov_b32 s8, exec_lo
	v_cmpx_eq_u32_e32 0, v2
; %bb.5:
	v_mov_b32_e32 v3, 2
; %bb.6:                                ; %Flow98
	s_or_b32 exec_lo, exec_lo, s8
.LBB4_7:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_ashr_i32 s12, s6, 31
	v_mul_lo_u32 v4, v2, s2
	s_add_i32 s3, s6, s12
	s_load_b128 s[8:11], s[0:1], 0x8
	s_xor_b32 s3, s3, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s2, 0, s3
	v_sub_nc_u32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_ashrrev_i32_e32 v6, 31, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v5, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v0, v5
	v_add_nc_u32_e32 v5, v1, v6
	v_xor_b32_e32 v5, v5, v6
	v_xor_b32_e32 v6, s12, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v0, v4
	v_mul_hi_u32 v0, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v0, s3
	v_sub_nc_u32_e32 v5, v5, v7
	v_add_nc_u32_e32 v7, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s3, v5
	v_cmp_le_u32_e32 vcc_lo, s3, v5
	v_dual_cndmask_b32 v0, v0, v7 :: v_dual_cndmask_b32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v7, vcc_lo
	v_xor_b32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v0, v6
	v_mul_lo_u32 v0, v5, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v1, v0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, s10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	v_cmp_lt_i32_e64 s2, -1, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB4_10
; %bb.8:
	v_add_nc_u32_e32 v1, s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s9, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB4_10
; %bb.9:
	s_ashr_i32 s6, s7, 31
	v_mul_lo_u32 v6, v6, s4
	s_add_i32 s2, s7, s6
	v_mul_lo_u32 v5, v5, s5
	s_xor_b32 s7, s2, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v7, s7
	s_sub_i32 s2, 0, s7
	v_ashrrev_i32_e32 v9, 31, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v10, 31, v5
	v_rcp_iflag_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v6, v9
	v_xor_b32_e32 v6, v6, v9
	v_xor_b32_e32 v9, s12, v9
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	v_mul_hi_u32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v7, v7
	v_mul_lo_u32 v8, s2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v7, v8
	v_add_nc_u32_e32 v7, v7, v8
	v_mul_lo_u32 v8, v4, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_nc_u32_e32 v8, 1, v4
	v_cmp_le_u32_e32 vcc_lo, s3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v8 :: v_dual_add_nc_u32 v5, v5, v10
	v_xor_b32_e32 v5, v5, v10
	v_subrev_nc_u32_e32 v8, s3, v6
	v_xor_b32_e32 v10, s6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, v5, v7
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_add_nc_u32_e32 v8, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s3, v6
	v_mul_lo_u32 v11, v7, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v8, vcc_lo
	v_sub_nc_u32_e32 v5, v5, v11
	v_add_nc_u32_e32 v11, 1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v9
	v_subrev_nc_u32_e32 v12, s7, v5
	v_cmp_le_u32_e64 s2, s7, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, v4, v9
	v_mad_u64_u32 v[8:9], null, v3, s9, v[1:2]
	v_cndmask_b32_e64 v7, v7, v11, s2
	v_cndmask_b32_e64 v5, v5, v12, s2
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v11, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v7, v11, vcc_lo
	v_xor_b32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v5, v10
	v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
	s_mul_i32 s4, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[6:7], null, s4, 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v2, s4, v[5:6]
	v_mad_u64_u32 v[1:2], null, v8, s8, v[0:1]
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v4, v[5:6], off
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v5, v[0:1], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v3, 1.0, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v5, v3
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, v2, v4
	global_store_b32 v[0:1], v3, off
.LBB4_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawRgbaTextureKernelNearestNeighbor
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	DrawRgbaTextureKernelNearestNeighbor, .Lfunc_end4-DrawRgbaTextureKernelNearestNeighbor
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1128
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	DrawMaskedColorKernelNearestNeighbor ; -- Begin function DrawMaskedColorKernelNearestNeighbor
	.globl	DrawMaskedColorKernelNearestNeighbor
	.p2align	8
	.type	DrawMaskedColorKernelNearestNeighbor,@function
DrawMaskedColorKernelNearestNeighbor:   ; @DrawMaskedColorKernelNearestNeighbor
; %bb.0:
	s_clause 0x2
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b32 s3, s[0:1], 0x40
	s_load_b32 s4, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s11, s10
	s_mul_i32 s3, s3, s15
	s_ashr_i32 s5, s2, 31
	s_and_b32 s4, s4, 0xffff
	s_add_i32 s6, s2, s5
	s_add_i32 s3, s3, s14
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s6
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
	s_sub_i32 s3, 0, s6
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s3, v3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s5, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s6
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s6, v3
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v0, v2
	v_cmpx_gt_i32_e32 3, v2
	s_cbranch_execz .LBB5_19
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x30
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $sgpr7
	v_cmpx_lt_i32_e32 1, v2
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB5_3
; %bb.2:
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s7, 0
.LBB5_3:                                ; %Flow129
	s_or_saveexec_b32 s3, s3
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v3, s7
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB5_7
; %bb.4:                                ; %LeafBlock
	v_mov_b32_e32 v3, v2
	s_mov_b32 s7, exec_lo
	v_cmpx_eq_u32_e32 0, v2
; %bb.5:
	v_mov_b32_e32 v3, 2
; %bb.6:                                ; %Flow128
	s_or_b32 exec_lo, exec_lo, s7
.LBB5_7:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_ashr_i32 s3, s10, 31
	v_mul_lo_u32 v4, v2, s2
	s_add_i32 s7, s10, s3
	s_load_b128 s[12:15], s[0:1], 0x8
	s_xor_b32 s7, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v0, s7
	s_sub_i32 s2, 0, s7
	v_sub_nc_u32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_ashrrev_i32_e32 v6, 31, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v5, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v0, v5
	v_add_nc_u32_e32 v5, v1, v6
	v_xor_b32_e32 v5, v5, v6
	v_xor_b32_e32 v6, s3, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v0, v4
	v_mul_hi_u32 v0, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v0, s7
	v_sub_nc_u32_e32 v5, v5, v7
	v_add_nc_u32_e32 v7, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s7, v5
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	v_dual_cndmask_b32 v0, v0, v7 :: v_dual_cndmask_b32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v7, vcc_lo
	v_xor_b32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v0, v6
	v_mul_lo_u32 v0, v6, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v1, v0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, s14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s12, v0
	v_cmp_lt_i32_e64 s2, -1, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB5_19
; %bb.8:
	v_add_nc_u32_e32 v1, s15, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s13, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB5_19
; %bb.9:
	s_ashr_i32 s2, s11, 31
	v_mul_lo_u32 v6, v6, s9
	s_add_i32 s10, s11, s2
	v_mul_lo_u32 v5, v5, s8
	s_xor_b32 s10, s10, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v7, s10
	s_sub_i32 s11, 0, s10
	v_ashrrev_i32_e32 v9, 31, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v10, 31, v5
	v_rcp_iflag_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v6, v9
	v_add_nc_u32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v6, v9
	v_xor_b32_e32 v5, v5, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	v_mul_hi_u32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v7, v7
	v_mul_lo_u32 v8, s11, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v4, s7
	v_mul_hi_u32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v11
	v_add_nc_u32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v7
	v_mul_lo_u32 v8, v7, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v6, v8
	v_subrev_nc_u32_e32 v12, s10, v6
	v_cmp_le_u32_e32 vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v12, vcc_lo
	v_subrev_nc_u32_e32 v12, s7, v5
	v_add_nc_u32_e32 v8, 1, v7
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_xor_b32_e32 v8, s2, v9
	v_add_nc_u32_e32 v9, 1, v4
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	v_cmp_le_u32_e64 s2, s10, v6
	v_add_nc_u32_e32 v11, 1, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v9
	v_cndmask_b32_e64 v6, v7, v11, s2
	v_xor_b32_e32 v9, s3, v10
	s_load_b64 s[2:3], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	v_add_nc_u32_e32 v7, 1, v4
	v_xor_b32_e32 v6, v6, v8
	v_cndmask_b32_e32 v5, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v8
	v_xor_b32_e32 v7, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, s9, 3, v[4:5]
	v_sub_nc_u32_e32 v4, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v5, s8, v[4:5]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_19
; %bb.10:                               ; %NodeBlock121
	v_mad_u64_u32 v[5:6], null, v3, s13, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v5, s12, v[0:1]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, 0
	s_mov_b32 s1, exec_lo
	global_load_b32 v3, v[0:1], off
	v_cmpx_lt_i32_e32 0, v2
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB5_14
; %bb.11:                               ; %LeafBlock119
	s_mov_b32 s0, -1
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 1, v2
; %bb.12:
	s_xor_b32 s0, exec_lo, -1
; %bb.13:                               ; %Flow123
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
                                        ; implicit-def: $vgpr2
.LBB5_14:                               ; %Flow
	s_or_saveexec_b32 s1, s1
	v_mov_b32_e32 v5, s5
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.15:                               ; %LeafBlock117
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_mov_b32_e32 v5, s4
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s2
; %bb.16:                               ; %Flow124
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
; %bb.17:
	v_mov_b32_e32 v5, s6
; %bb.18:                               ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_f32_e32 v2, 1.0, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	v_fmac_f32_e32 v2, v4, v5
	global_store_b32 v[0:1], v2, off
.LBB5_19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawMaskedColorKernelNearestNeighbor
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	DrawMaskedColorKernelNearestNeighbor, .Lfunc_end5-DrawMaskedColorKernelNearestNeighbor
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1212
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	DrawRgbaTextureKernel2DBlock ; -- Begin function DrawRgbaTextureKernel2DBlock
	.globl	DrawRgbaTextureKernel2DBlock
	.p2align	8
	.type	DrawRgbaTextureKernel2DBlock,@function
DrawRgbaTextureKernel2DBlock:           ; @DrawRgbaTextureKernel2DBlock
; %bb.0:
	s_cmp_gt_i32 s15, 2
	s_cbranch_scc1 .LBB6_10
; %bb.1:                                ; %NodeBlock
	s_cmp_gt_i32 s15, 1
	s_cbranch_scc0 .LBB6_3
; %bb.2:
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0
	s_branch .LBB6_4
.LBB6_3:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
.LBB6_4:                                ; %Flow76
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB6_7
; %bb.5:                                ; %LeafBlock
	s_cmp_lg_u32 s15, 0
	s_mov_b32 s3, s15
	s_cbranch_scc1 .LBB6_7
; %bb.6:
	s_mov_b32 s3, 2
.LBB6_7:
	s_load_b128 s[8:11], s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s10, v2
	v_cmp_gt_i32_e32 vcc_lo, s8, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB6_10
; %bb.8:
	s_load_b32 s10, s[0:1], 0x34
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s10, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s2, s14, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s2, s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s9, v0
	v_cmp_lt_i32_e64 s2, -1, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB6_10
; %bb.9:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x28
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	v_mad_u64_u32 v[4:5], null, s2, s12, v[3:4]
	s_and_b32 s2, s10, 0xffff
	v_mad_u64_u32 v[5:6], null, s3, s9, v[0:1]
	s_mul_i32 s3, s7, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, v4, s2, v[2:3]
	s_sub_i32 s2, 3, s15
	v_mad_u64_u32 v[2:3], null, v5, s8, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[0:1], null, s3, s2, v[6:7]
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[4:5], off
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v5, 1.0, v0 :: v_dual_mul_f32 v0, v0, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, v4, v5
	global_store_b32 v[2:3], v0, off
.LBB6_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawRgbaTextureKernel2DBlock
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	DrawRgbaTextureKernel2DBlock, .Lfunc_end6-DrawRgbaTextureKernel2DBlock
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	DrawMaskedColorKernel   ; -- Begin function DrawMaskedColorKernel
	.globl	DrawMaskedColorKernel
	.p2align	8
	.type	DrawMaskedColorKernel,@function
DrawMaskedColorKernel:                  ; @DrawMaskedColorKernel
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x38
	s_load_b32 s8, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s5, s4
	s_mul_i32 s2, s2, s15
	s_ashr_i32 s5, s3, 31
	s_and_b32 s8, s8, 0xffff
	s_add_i32 s9, s3, s5
	s_add_i32 s2, s2, s14
	s_xor_b32 s9, s9, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s9
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s2, s8, v[0:1]
	s_sub_i32 s2, 0, s9
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	v_xor_b32_e32 v2, s5, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s9
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s9, v3
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s9, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v2
	v_cmpx_gt_i32_e32 3, v3
	s_cbranch_execz .LBB7_13
; %bb.1:
	s_ashr_i32 s2, s4, 31
	v_mul_lo_u32 v2, v3, s3
	s_add_i32 s5, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s2
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s8, 0, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v1, v2
	v_rcp_iflag_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v5, v2, v1
	v_xor_b32_e32 v5, v5, v1
	v_xor_b32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v4, s8, v0
	s_load_b128 s[8:11], s[0:1], 0x8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v0, v4
	v_add_nc_u32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v5, v0
	v_mul_lo_u32 v4, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v5, v4
	v_subrev_nc_u32_e32 v6, s5, v4
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	v_add_nc_u32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_xor_b32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v0, v1
	v_mul_lo_u32 v0, v1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v2, v0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	v_cmp_lt_i32_e64 s2, -1, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB7_13
; %bb.2:
	v_add_nc_u32_e32 v1, s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s9, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB7_13
; %bb.3:
	s_load_b64 s[4:5], s[0:1], 0x18
	v_mad_u64_u32 v[4:5], null, s3, 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_13
; %bb.4:
	s_load_b32 s2, s[0:1], 0x30
	s_mov_b32 s3, 0
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_i32_e32 0, v3
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB7_8
; %bb.5:                                ; %LeafBlock85
	s_mov_b32 s3, -1
	s_mov_b32 s5, exec_lo
	v_cmpx_eq_u32_e32 1, v3
; %bb.6:
	s_xor_b32 s3, exec_lo, -1
; %bb.7:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
.LBB7_8:                                ; %Flow
	s_or_saveexec_b32 s4, s4
	v_mov_b32_e32 v2, s7
	s_xor_b32 exec_lo, exec_lo, s4
; %bb.9:                                ; %LeafBlock
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_mov_b32_e32 v2, s6
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s5
; %bb.10:                               ; %Flow88
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB7_12
; %bb.11:
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v2, s2
.LBB7_12:                               ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s9, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[5:6], null, v4, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB7_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawMaskedColorKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	DrawMaskedColorKernel, .Lfunc_end7-DrawMaskedColorKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 820
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	DrawMaskedColorKernel2DBlock ; -- Begin function DrawMaskedColorKernel2DBlock
	.globl	DrawMaskedColorKernel2DBlock
	.p2align	8
	.type	DrawMaskedColorKernel2DBlock,@function
DrawMaskedColorKernel2DBlock:           ; @DrawMaskedColorKernel2DBlock
; %bb.0:
	s_cmp_gt_i32 s15, 2
	s_cbranch_scc1 .LBB8_15
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s6, v3
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB8_15
; %bb.2:
	s_load_b32 s3, s[0:1], 0x44
	s_add_u32 s8, s0, 56
	v_bfe_u32 v2, v0, 10, 10
	s_addc_u32 s9, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s6, s3, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s14, s6
	v_add3_u32 v0, s2, s7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_lt_i32_e64 s2, -1, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB8_15
; %bb.3:
	s_load_b32 s2, s[8:9], 0x0
	s_load_b128 s[8:11], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_mul_i32 s7, s9, s8
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s2, s6, v[2:3]
	s_and_b32 s2, s3, 0xffff
	s_sub_i32 s6, 3, s15
	s_mul_i32 s7, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v4, s2
	s_load_b64 s[2:3], s[0:1], 0x18
	v_add3_u32 v2, v2, v3, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB8_15
; %bb.4:
	s_load_b32 s2, s[0:1], 0x30
	s_cmp_lt_i32 s15, 1
	s_cbranch_scc1 .LBB8_7
; %bb.5:                                ; %LeafBlock84
	s_cmp_eq_u32 s15, 1
	s_cbranch_scc0 .LBB8_8
; %bb.6:
	s_mov_b32 s3, 0
	s_branch .LBB8_9
.LBB8_7:
	s_mov_b32 s6, -1
	s_mov_b32 s3, 0
	s_branch .LBB8_10
.LBB8_8:
	s_mov_b32 s3, -1
.LBB8_9:                                ; %Flow86
	s_mov_b32 s6, 0
.LBB8_10:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB8_12
; %bb.11:                               ; %LeafBlock
	s_cmp_lg_u32 s15, 0
	s_mov_b32 s11, s10
	s_cselect_b32 s3, -1, 0
.LBB8_12:                               ; %Flow87
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB8_14
; %bb.13:
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s11, s2
.LBB8_14:                               ; %.sink.split
	v_mad_u64_u32 v[2:3], null, s15, s5, v[0:1]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
	v_mov_b32_e32 v2, s11
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB8_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel DrawMaskedColorKernel2DBlock
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	DrawMaskedColorKernel2DBlock, .Lfunc_end8-DrawMaskedColorKernel2DBlock
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	ExtractRawComponentsToRgbKernel ; -- Begin function ExtractRawComponentsToRgbKernel
	.globl	ExtractRawComponentsToRgbKernel
	.p2align	8
	.type	ExtractRawComponentsToRgbKernel,@function
ExtractRawComponentsToRgbKernel:        ; @ExtractRawComponentsToRgbKernel
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x10
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s4, s15
	s_and_b32 s5, s5, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	s_mul_i32 s4, s3, s2
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB9_3
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_lshl_b32 s2, s4, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s1, 0
	global_load_b32 v2, v[0:1], off
.LBB9_2:                                ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s1, v2
	s_ashr_i32 s3, s2, 31
	s_add_i32 s1, s1, 8
	s_lshl_b64 s[6:7], s[2:3], 2
	s_sub_i32 s2, s2, s4
	v_cvt_f32_ubyte0_e32 v5, v3
	s_cmp_lg_u32 s1, 24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, 0x437f0000, 0x437f0000, v5
	v_div_scale_f32 v7, vcc_lo, v5, 0x437f0000, v5
	v_rcp_f32_e32 v6, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v4, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v3, v6
	v_mul_f32_e32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v4, v8, v7
	v_fmac_f32_e32 v8, v3, v6
	v_add_co_u32 v3, s0, v0, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v8, v7
	v_div_fmas_f32 v6, v4, v6, v8
	v_add_co_ci_u32_e64 v4, vcc_lo, s7, v1, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v5, v6, 0x437f0000, v5
	global_store_b32 v[3:4], v5, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB9_2
.LBB9_3:                                ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel ExtractRawComponentsToRgbKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	ExtractRawComponentsToRgbKernel, .Lfunc_end9-ExtractRawComponentsToRgbKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	RawToRgbKernel          ; -- Begin function RawToRgbKernel
	.globl	RawToRgbKernel
	.p2align	8
	.type	RawToRgbKernel,@function
RawToRgbKernel:                         ; @RawToRgbKernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB10_3
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_mov_b32 s0, 16
	global_load_b32 v0, v[2:3], off
.LBB10_2:                               ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v2, s0, v0
	s_add_i32 s0, s0, -8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, -8
	v_cvt_f32_ubyte0_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, 0x437f0000, 0x437f0000, v4
	v_div_scale_f32 v6, vcc_lo, v4, 0x437f0000, v4
	v_rcp_f32_e32 v5, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v3, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v2, v5
	v_mul_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v3, v7, v6
	v_fmac_f32_e32 v7, v2, v5
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v3, v7, v6
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_nc_u32_e32 v1, s4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v5, v6, v5, v7
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_div_fixup_f32 v4, v5, 0x437f0000, v4
	global_store_b32 v[2:3], v4, off
	s_cbranch_scc1 .LBB10_2
.LBB10_3:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel RawToRgbKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	RawToRgbKernel, .Lfunc_end10-RawToRgbKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	RawToRawGrayscaleKernel ; -- Begin function RawToRawGrayscaleKernel
	.globl	RawToRawGrayscaleKernel
	.p2align	8
	.type	RawToRawGrayscaleKernel,@function
RawToRawGrayscaleKernel:                ; @RawToRawGrayscaleKernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB11_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte1_e32 v3, v2
	v_cvt_f32_ubyte2_e32 v4, v2
	v_cvt_f32_ubyte0_e32 v5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x3f371759, v3
	v_fmamk_f32 v3, v4, 0x3e59b3d0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v5, 0x3d93dd98, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v4, 16, v3
	v_lshlrev_b32_e32 v5, 8, v3
	v_and_or_b32 v2, 0xff000000, v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v2, v2, v5, v3
	global_store_b32 v[0:1], v2, off
.LBB11_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel RawToRawGrayscaleKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	RawToRawGrayscaleKernel, .Lfunc_end11-RawToRawGrayscaleKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	RawToGrayscaleKernel    ; -- Begin function RawToGrayscaleKernel
	.globl	RawToGrayscaleKernel
	.p2align	8
	.type	RawToGrayscaleKernel,@function
RawToGrayscaleKernel:                   ; @RawToGrayscaleKernel
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB12_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte1_e32 v3, v2
	v_cvt_f32_ubyte2_e32 v4, v2
	v_cvt_f32_ubyte0_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x3f371759, v3
	v_fmamk_f32 v3, v4, 0x3e59b3d0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v2, v2, 0x3d93dd98, v3
	v_div_scale_f32 v3, null, 0x437f0000, 0x437f0000, v2
	v_div_scale_f32 v6, vcc_lo, v2, 0x437f0000, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v4
	v_fma_f32 v7, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v4
	v_fma_f32 v3, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v3, v3, v4, v5
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_div_fixup_f32 v2, v3, 0x437f0000, v2
	global_store_b32 v[0:1], v2, off
.LBB12_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel RawToGrayscaleKernel
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	RawToGrayscaleKernel, .Lfunc_end12-RawToGrayscaleKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           DrawRgbBackgroundKernel
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         DrawRgbBackgroundKernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           AddRgbNoiseKernel
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         AddRgbNoiseKernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
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    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           RawToRawGrayscaleKernel
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         RawToRawGrayscaleKernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           RawToGrayscaleKernel
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         RawToGrayscaleKernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
