//pass
//--blockDim=32 --gridDim=2

#include "../common.h"

__global__ void Pathcalc_Portfolio_KernelGPU2(float *d_v)
{
  const int     tid = blockDim.x * blockIdx.x + threadIdx.x;
  const int threadN = blockDim.x * gridDim.x;

  int   i, path;
  float L[NN], z[NN];
  
  /* Monte Carlo LIBOR path calculation*/

  for(path = tid; path < NPATH; path += threadN){
    // initialise the data for current thread
    for (i=0; i<N; i++) {
      // for real application, z should be randomly generated
      z[i] = 0.3;
      L[i] = 0.05;
    }	   
    path_calc(L, z);
    d_v[path] = portfolio(L);
  }
}

	.file	"tmpxft_002f89ab_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2015:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2015:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
	.type	_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf, @function
_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z29Pathcalc_Portfolio_KernelGPU2Pf(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf, .-_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
	.globl	_Z29Pathcalc_Portfolio_KernelGPU2Pf
	.type	_Z29Pathcalc_Portfolio_KernelGPU2Pf, @function
_Z29Pathcalc_Portfolio_KernelGPU2Pf:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z29Pathcalc_Portfolio_KernelGPU2PfPf
	.cfi_endproc
.LFE2038:
	.size	_Z29Pathcalc_Portfolio_KernelGPU2Pf, .-_Z29Pathcalc_Portfolio_KernelGPU2Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z29Pathcalc_Portfolio_KernelGPU2Pf"
.LC1:
	.string	"N"
.LC2:
	.string	"Nmat"
.LC3:
	.string	"Nopt"
.LC4:
	.string	"maturities"
.LC5:
	.string	"delta"
.LC6:
	.string	"swaprates"
.LC7:
	.string	"lambda"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z29Pathcalc_Portfolio_KernelGPU2Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$4, %r9d
	leaq	_ZL1N(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL4Nmat(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL4Nopt(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$60, %r9d
	leaq	_ZL10maturities(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL5delta(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$60, %r9d
	leaq	_ZL9swaprates(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$320, %r9d
	leaq	_ZL6lambda(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL6lambda
	.comm	_ZL6lambda,320,32
	.local	_ZL9swaprates
	.comm	_ZL9swaprates,60,32
	.local	_ZL5delta
	.comm	_ZL5delta,4,4
	.local	_ZL10maturities
	.comm	_ZL10maturities,60,32
	.local	_ZL4Nopt
	.comm	_ZL4Nopt,4,4
	.local	_ZL4Nmat
	.comm	_ZL4Nmat,4,4
	.local	_ZL1N
	.comm	_ZL1N,4,4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//pass
//--blockDim=32 --gridDim=2


#include <hip/hip_runtime.h>
#include "../common.h"

__global__ void Pathcalc_Portfolio_KernelGPU2(float *d_v)
{
  const int     tid = blockDim.x * blockIdx.x + threadIdx.x;
  const int threadN = blockDim.x * gridDim.x;

  int   i, path;
  float L[NN], z[NN];
  
  /* Monte Carlo LIBOR path calculation*/

  for(path = tid; path < NPATH; path += threadN){
    // initialise the data for current thread
    for (i=0; i<N; i++) {
      // for real application, z should be randomly generated
      z[i] = 0.3;
      L[i] = 0.05;
    }	   
    path_calc(L, z);
    d_v[path] = portfolio(L);
  }
}

	.text
	.file	"kernel.hip"
	.globl	_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf # -- Begin function _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
	.type	_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf,@function
_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf: # @_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29Pathcalc_Portfolio_KernelGPU2Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf, .Lfunc_end0-_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29Pathcalc_Portfolio_KernelGPU2Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$N, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$Nmat, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$Nopt, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$maturities, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$60, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$delta, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$swaprates, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movl	$60, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$lambda, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movl	$320, %r9d                      # imm = 0x140
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	N,@object                       # @N
	.local	N
	.comm	N,4,4
	.type	Nmat,@object                    # @Nmat
	.local	Nmat
	.comm	Nmat,4,4
	.type	Nopt,@object                    # @Nopt
	.local	Nopt
	.comm	Nopt,4,4
	.type	maturities,@object              # @maturities
	.local	maturities
	.comm	maturities,60,16
	.type	delta,@object                   # @delta
	.local	delta
	.comm	delta,4,4
	.type	swaprates,@object               # @swaprates
	.local	swaprates
	.comm	swaprates,60,16
	.type	lambda,@object                  # @lambda
	.local	lambda
	.comm	lambda,320,16
	.type	_Z29Pathcalc_Portfolio_KernelGPU2Pf,@object # @_Z29Pathcalc_Portfolio_KernelGPU2Pf
	.section	.rodata,"a",@progbits
	.globl	_Z29Pathcalc_Portfolio_KernelGPU2Pf
	.p2align	3, 0x0
_Z29Pathcalc_Portfolio_KernelGPU2Pf:
	.quad	_Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
	.size	_Z29Pathcalc_Portfolio_KernelGPU2Pf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z29Pathcalc_Portfolio_KernelGPU2Pf"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"N"
	.size	.L__unnamed_2, 2

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"Nmat"
	.size	.L__unnamed_3, 5

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"Nopt"
	.size	.L__unnamed_4, 5

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"maturities"
	.size	.L__unnamed_5, 11

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"delta"
	.size	.L__unnamed_6, 6

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"swaprates"
	.size	.L__unnamed_7, 10

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"lambda"
	.size	.L__unnamed_8, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z44__device_stub__Pathcalc_Portfolio_KernelGPU2Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym N
	.addrsig_sym Nmat
	.addrsig_sym Nopt
	.addrsig_sym maturities
	.addrsig_sym delta
	.addrsig_sym swaprates
	.addrsig_sym lambda
	.addrsig_sym _Z29Pathcalc_Portfolio_KernelGPU2Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z29Pathcalc_Portfolio_KernelGPU2Pf ; -- Begin function _Z29Pathcalc_Portfolio_KernelGPU2Pf
	.globl	_Z29Pathcalc_Portfolio_KernelGPU2Pf
	.p2align	8
	.type	_Z29Pathcalc_Portfolio_KernelGPU2Pf,@function
_Z29Pathcalc_Portfolio_KernelGPU2Pf:    ; @_Z29Pathcalc_Portfolio_KernelGPU2Pf
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_add_u32 s4, s0, 8
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s2, 0xffff
	s_mov_b32 s2, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x1000, v1
	s_cbranch_execz .LBB0_23
; %bb.1:                                ; %.preheader.lr.ph
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, N@rel32@lo+4
	s_addc_u32 s3, s3, N@rel32@hi+12
	s_mov_b32 s15, 0
	s_load_b32 s6, s[2:3], 0x0
	v_mov_b32_e32 v7, 0x3d4ccccd
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s6, 0
	s_cselect_b32 s7, -1, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Nmat@rel32@lo+4
	s_addc_u32 s3, s3, Nmat@rel32@hi+12
	s_load_b32 s8, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s8, 0
	s_cselect_b32 s9, -1, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, delta@rel32@lo+4
	s_addc_u32 s3, s3, delta@rel32@hi+12
	s_cmp_lt_i32 s8, s6
	s_load_b32 s10, s[2:3], 0x0
	s_cselect_b32 s11, -1, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Nopt@rel32@lo+4
	s_addc_u32 s3, s3, Nopt@rel32@hi+12
	s_load_b32 s12, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v0, 0x4f800000, s10
	v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s10
	s_cmp_gt_i32 s12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, s10, v0, vcc_lo
	s_cselect_b32 s13, -1, 0
	v_sqrt_f32_e32 v0, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v0
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v3, v0, v2
	v_fma_f32 v6, -v4, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s2, 0, v5
	v_or_b32_e64 v5, 0x150, 4
	v_cndmask_b32_e64 v3, v0, v3, s2
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s1, s[4:5], 0x0
	v_cmp_lt_f32_e64 s0, 0, v6
	v_add_nc_u32_e64 v0, 16, -4
	v_mov_b32_e32 v6, 0x3e99999a
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v4, s0
	s_lshl_b32 s0, s8, 2
	v_add_nc_u32_e64 v4, 0xb0, -4
	v_mul_f32_e32 v8, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	v_add_nc_u32_e64 v8, 0x150, s0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s1, s14
	v_cndmask_b32_e32 v9, v3, v2, vcc_lo
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_9 Depth 3
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_16 Depth 2
                                        ;     Child Loop BB0_20 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_5
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, 0x290
	v_mov_b32_e32 v3, 0x150
	s_mov_b32 s0, s6
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_store_b32 v2, v6, off
	scratch_store_b32 v3, v7, off
	v_add_nc_u32_e32 v2, 4, v2
	v_add_nc_u32_e32 v3, 4, v3
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 0
	s_cbranch_scc1 .LBB0_4
.LBB0_5:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_11
; %bb.6:                                ; %.lr.ph30.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v10, v5
	s_mov_b32 s4, 0
.LBB0_7:                                ; %.lr.ph30.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_9 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_mov_b32 s0, s4
	s_add_i32 s4, s4, 1
	s_cmp_ge_i32 s4, s6
	s_cbranch_scc1 .LBB0_10
; %bb.8:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_lshl_b32 s0, s0, 2
	v_mov_b32_e32 v12, v10
	s_addk_i32 s0, 0x290
	s_mov_b32 s5, s4
	scratch_load_b32 v2, off, s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, lambda@rel32@lo+4
	s_addc_u32 s1, s1, lambda@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v11, 0 :: v_dual_mul_f32 v2, v9, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[2:3], v2
.LBB0_9:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	scratch_load_b32 v19, v12, off
	s_load_b32 s16, s[0:1], 0x0
	s_add_i32 s5, s5, 1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_ge_i32 s5, s6
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v15, s10, s16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, v15, v19
	v_fma_f32 v17, s10, v19, 1.0
	v_div_scale_f32 v18, null, v17, v17, v16
	v_div_scale_f32 v21, vcc_lo, v16, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v20, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v18, v20, 1.0
	v_fmac_f32_e32 v20, v13, v20
	v_cvt_f64_f32_e32 v[13:14], v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v21, v20
	v_fma_f32 v23, -v18, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v23, v20
	v_fma_f32 v18, -v18, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v18, v18, v20, v22
	v_div_fixup_f32 v16, v18, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v11, v16
	v_fma_f64 v[13:14], v[13:14], -0.5, v[2:3]
	v_mul_f32_e32 v17, v15, v11
	v_cvt_f64_f32_e32 v[15:16], s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[17:18], v17
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v13, v[13:14]
	v_mul_f32_e32 v13, 0x3fb8aa3b, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_exp_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v13, v19, v13
	scratch_store_b32 v12, v13, off
	v_add_nc_u32_e32 v12, 4, v12
	s_cbranch_scc0 .LBB0_9
.LBB0_10:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_7 Depth=2
	v_add_nc_u32_e32 v10, 4, v10
	s_cmp_eq_u32 s4, s8
	s_cbranch_scc0 .LBB0_7
.LBB0_11:                               ; %_ZL9path_calcPfS_.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_14
; %bb.12:                               ; %.lr.ph.i12.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v2, 0xb0 :: v_dual_mov_b32 v3, 16
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, v8
	v_mov_b32_e32 v12, 1.0
	s_mov_b32 s0, s8
.LBB0_13:                               ; %.lr.ph.i12
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v13, v11, off
	v_cvt_f64_f32_e32 v[15:16], v12
	v_add_nc_u32_e32 v11, 4, v11
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_ge_i32 s0, s6
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v13, s10, v13
	v_cvt_f64_f32_e32 v[13:14], v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[13:14], 1.0
	v_div_scale_f64 v[17:18], null, v[12:13], v[12:13], v[15:16]
	v_div_scale_f64 v[23:24], vcc_lo, v[15:16], v[12:13], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[23:24], v[19:20]
	v_fma_f64 v[17:18], -v[17:18], v[21:22], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[21:22]
	v_div_fixup_f64 v[12:13], v[17:18], v[12:13], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v12, v[12:13]
	v_fmac_f32_e32 v10, s10, v12
	scratch_store_b32 v3, v12, off
	v_add_nc_u32_e32 v3, 4, v3
	scratch_store_b32 v2, v10, off
	v_add_nc_u32_e32 v2, 4, v2
	s_cbranch_scc0 .LBB0_13
.LBB0_14:                               ; %.preheader34.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s13
	s_cbranch_vccnz .LBB0_17
; %bb.15:                               ; %.lr.ph40.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v3, 0
	s_mov_b32 s16, s12
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, swaprates@rel32@lo+4
	s_addc_u32 s1, s1, swaprates@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, maturities@rel32@lo+4
	s_addc_u32 s5, s5, maturities@rel32@hi+12
.LBB0_16:                               ; %.lr.ph40.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b32 s17, s[4:5], 0x0
	s_add_i32 s16, s16, -1
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s17, s17, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s17, v0
	v_add_nc_u32_e32 v10, s17, v4
	scratch_load_b32 v2, v2, off
	scratch_load_b32 v10, v10, off
	s_load_b32 s17, s[0:1], 0x0
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s16, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v2, s17, v10
	v_cvt_f64_f32_e32 v[10:11], v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, -1.0, v2
	v_cvt_f64_f32_e32 v[12:13], v2
	v_cmp_gt_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], 0xc0590000, v[12:13], v[10:11]
	v_cvt_f32_f64_e32 v10, v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v10, vcc_lo
	s_cbranch_scc0 .LBB0_16
	s_branch .LBB0_18
.LBB0_17:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v3, 0
.LBB0_18:                               ; %.preheader.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_21
; %bb.19:                               ; %.lr.ph43.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, 0x150
	v_mov_b32_e32 v10, 1.0
	s_mov_b32 s0, s8
.LBB0_20:                               ; %.lr.ph43.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v11, v2, off
	v_cvt_f64_f32_e32 v[13:14], v10
	s_add_i32 s0, s0, -1
	v_add_nc_u32_e32 v2, 4, v2
	s_cmp_lg_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v11, s10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[11:12], v11
	v_add_f64 v[10:11], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[15:16], null, v[10:11], v[10:11], v[13:14]
	v_div_scale_f64 v[21:22], vcc_lo, v[13:14], v[10:11], v[13:14]
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[10:11], v[15:16], v[10:11], v[13:14]
	v_cvt_f32_f64_e32 v10, v[10:11]
	s_cbranch_scc1 .LBB0_20
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v10, 1.0
.LBB0_22:                               ; %_ZL9portfolioPf.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, v3, v10
	v_lshlrev_b64 v[11:12], 2, v[1:2]
	v_add_nc_u32_e32 v1, s14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e32 vcc_lo, 0xfff, v1
	v_add_co_u32 v2, s0, s2, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s3, v12, s0
	s_or_b32 s15, vcc_lo, s15
	global_store_b32 v[2:3], v10, off
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_2
.LBB0_23:                               ; %._crit_edge16
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29Pathcalc_Portfolio_KernelGPU2Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 976
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z29Pathcalc_Portfolio_KernelGPU2Pf, .Lfunc_end0-_Z29Pathcalc_Portfolio_KernelGPU2Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1580
; NumSgprs: 20
; NumVgprs: 25
; ScratchSize: 976
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	N                       ; @N
	.type	N,@object
	.section	.bss,"aw",@nobits
	.globl	N
	.p2align	2, 0x0
N:
	.long	0                               ; 0x0
	.size	N, 4

	.protected	Nmat                    ; @Nmat
	.type	Nmat,@object
	.globl	Nmat
	.p2align	2, 0x0
Nmat:
	.long	0                               ; 0x0
	.size	Nmat, 4

	.protected	Nopt                    ; @Nopt
	.type	Nopt,@object
	.globl	Nopt
	.p2align	2, 0x0
Nopt:
	.long	0                               ; 0x0
	.size	Nopt, 4

	.protected	maturities              ; @maturities
	.type	maturities,@object
	.globl	maturities
	.p2align	4, 0x0
maturities:
	.zero	60
	.size	maturities, 60

	.protected	delta                   ; @delta
	.type	delta,@object
	.globl	delta
	.p2align	2, 0x0
delta:
	.long	0x00000000                      ; float 0
	.size	delta, 4

	.protected	swaprates               ; @swaprates
	.type	swaprates,@object
	.globl	swaprates
	.p2align	4, 0x0
swaprates:
	.zero	60
	.size	swaprates, 60

	.protected	lambda                  ; @lambda
	.type	lambda,@object
	.globl	lambda
	.p2align	4, 0x0
lambda:
	.zero	320
	.size	lambda, 320

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym N
	.addrsig_sym Nmat
	.addrsig_sym Nopt
	.addrsig_sym maturities
	.addrsig_sym delta
	.addrsig_sym swaprates
	.addrsig_sym lambda
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z29Pathcalc_Portfolio_KernelGPU2Pf
    .private_segment_fixed_size: 976
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z29Pathcalc_Portfolio_KernelGPU2Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
