#include <stdio.h>

// TMC Faster
__constant__ int mapping[20] = {0, -1, 3, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1};

// Thread i will score genome[i*seqlength] to genome[i*seqlength+(seqlength-1)]
__global__ void scoreReads(char* genome, int seqLength, int order, float* model, float* scores) {
   int i = blockIdx.x;  // Thread identifier, assign to i
   int j = threadIdx.x;
   // Keep scores in shared memory
   extern __shared__ float kmer_scores[];  // Call this with [lengths[i] / order + 1];

   //if (i ==0) printf("%s\n", genome);
   // Start spot
   int seqspot = i*seqLength;
   int startspot, stopspot;
   if (j == 0) {
      startspot = seqspot;
      stopspot = startspot+(order-1);
   }
   else{
      startspot = seqspot+(j-1);
      stopspot = startspot+order;
   }
   //printf("Block %d Thread %d Startspot %d Stopspot %d\n", i, j, startspot, stopspot);
   // Quick loop, check for n's
   // Actually, decided to inline it rather than loop twice.
   int a;
   bool nFlag = false;
   int mapVal = 0;
   for (a = startspot; a < stopspot; a++) {
      //if (j == 0 && i == 0) printf("%d %d\n", startspot, a);
      //if (j == 0 && i == 0) printf("%c\n", genome[a]);
      if (genome[a] == 'N') { 
         //if (i == 0) printf("FOUND N, BREAKING.\n");
         kmer_scores[j] = 0;
         nFlag = true;
         break;
      }
      else 
         mapVal = 4*mapVal + mapping[(int)genome[a]-65];
   }
   if (!nFlag) {
      if (j == 0) {mapVal += pow(4.0, 9.0);}
      kmer_scores[j] = model[mapVal]; // Illegal here
      //if (i == 0) printf("Thread: %d  Mapval: %d  Score: %f\n", j, mapVal, kmer_scores[j]);
    }
   __syncthreads();

    /////// TMC TAKE OUT LATER
   /*if (j == 0) {
      int m;
      float tmpscore=0;
      for (m = seqspot; m < seqspot+seqLength-order+1+1; m++) {
         if (i == 0) printf("%d: Score: %f  New Partial Score: %f\n", m+8, kmer_scores[m-seqspot], tmpscore); 
         tmpscore += kmer_scores[m-seqspot];
      }
      if (i == 0) printf("The score for sequence %d should be: %f\n", i, tmpscore);
     
   }
   __syncthreads();*/
   //////////////////////////


   // Do the addition in parallel as well.
   //if (j == 0 && i == 0) printf("Number: %d", seqLength-order+1);
   if ((j == 0) && (((seqLength-order+1+1) % 2 == 1))) {/*if (i == 0) printf("Thread %d adding %d (%f) and %d (%f)", j, j, kmer_scores[j], seqLength-order+1, kmer_scores[seqLength-order+1]);*/ kmer_scores[j] = kmer_scores[j] + kmer_scores[seqLength-order+1]; /*if (i == 0) printf(" to get: %f\n", kmer_scores[j]);*/ }
   int k = (seqLength-order+1+1)/2;
   while (k >= 1) {
      //if (i == 0 && j == 0) printf("k is %d\n", k);
      if (j < k) {
	 //if (i == 0) printf("k: %d Thread %d adding %d (%f) and %d (%f) to get: %f\n", k, j, j, kmer_scores[j], j+k, kmer_scores[j+k], kmer_scores[j]+kmer_scores[j+k]);
         kmer_scores[j] = kmer_scores[j] + kmer_scores[j+k]; // Illegal here
      }
      __syncthreads();
      if (k != 1 && k % 2 != 0 && j == 0) {/*printf("k: %d Thread %d adding %d (%f) and %d (%f) to get: %f\n", k, j, j, kmer_scores[j], k-1, kmer_scores[k-1], kmer_scores[j]+kmer_scores[k-1]);*/              kmer_scores[j] = kmer_scores[j] + kmer_scores[k-1]; }// Uneven split, would be left out otherwise.
      k /= 2;
   }

   // The first kmer_score is now the final.
   if (j == 0) {
      scores[i] = kmer_scores[0];
      //printf("Kernel score for sequence %d: %f\n", i, scores[i]);
   }
}



	.file	"tmpxft_002ed762_00000000-6_scoreReads.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z37__device_stub__Z10scoreReadsPciiPfS0_PciiPfS0_
	.type	_Z37__device_stub__Z10scoreReadsPciiPfS0_PciiPfS0_, @function
_Z37__device_stub__Z10scoreReadsPciiPfS0_PciiPfS0_:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10scoreReadsPciiPfS0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z37__device_stub__Z10scoreReadsPciiPfS0_PciiPfS0_, .-_Z37__device_stub__Z10scoreReadsPciiPfS0_PciiPfS0_
	.globl	_Z10scoreReadsPciiPfS0_
	.type	_Z10scoreReadsPciiPfS0_, @function
_Z10scoreReadsPciiPfS0_:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z10scoreReadsPciiPfS0_PciiPfS0_
	.cfi_endproc
.LFE2052:
	.size	_Z10scoreReadsPciiPfS0_, .-_Z10scoreReadsPciiPfS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10scoreReadsPciiPfS0_"
.LC1:
	.string	"mapping"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10scoreReadsPciiPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$80, %r9d
	leaq	_ZL7mapping(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL7mapping
	.comm	_ZL7mapping,80,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

// TMC Faster
__constant__ int mapping[20] = {0, -1, 3, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1};

// Thread i will score genome[i*seqlength] to genome[i*seqlength+(seqlength-1)]
__global__ void scoreReads(char* genome, int seqLength, int order, float* model, float* scores) {
   int i = blockIdx.x;  // Thread identifier, assign to i
   int j = threadIdx.x;
   // Keep scores in shared memory
   extern __shared__ float kmer_scores[];  // Call this with [lengths[i] / order + 1];

   //if (i ==0) printf("%s\n", genome);
   // Start spot
   int seqspot = i*seqLength;
   int startspot, stopspot;
   if (j == 0) {
      startspot = seqspot;
      stopspot = startspot+(order-1);
   }
   else{
      startspot = seqspot+(j-1);
      stopspot = startspot+order;
   }
   //printf("Block %d Thread %d Startspot %d Stopspot %d\n", i, j, startspot, stopspot);
   // Quick loop, check for n's
   // Actually, decided to inline it rather than loop twice.
   int a;
   bool nFlag = false;
   int mapVal = 0;
   for (a = startspot; a < stopspot; a++) {
      //if (j == 0 && i == 0) printf("%d %d\n", startspot, a);
      //if (j == 0 && i == 0) printf("%c\n", genome[a]);
      if (genome[a] == 'N') { 
         //if (i == 0) printf("FOUND N, BREAKING.\n");
         kmer_scores[j] = 0;
         nFlag = true;
         break;
      }
      else 
         mapVal = 4*mapVal + mapping[(int)genome[a]-65];
   }
   if (!nFlag) {
      if (j == 0) {mapVal += pow(4.0, 9.0);}
      kmer_scores[j] = model[mapVal]; // Illegal here
      //if (i == 0) printf("Thread: %d  Mapval: %d  Score: %f\n", j, mapVal, kmer_scores[j]);
    }
   __syncthreads();

    /////// TMC TAKE OUT LATER
   /*if (j == 0) {
      int m;
      float tmpscore=0;
      for (m = seqspot; m < seqspot+seqLength-order+1+1; m++) {
         if (i == 0) printf("%d: Score: %f  New Partial Score: %f\n", m+8, kmer_scores[m-seqspot], tmpscore); 
         tmpscore += kmer_scores[m-seqspot];
      }
      if (i == 0) printf("The score for sequence %d should be: %f\n", i, tmpscore);
     
   }
   __syncthreads();*/
   //////////////////////////


   // Do the addition in parallel as well.
   //if (j == 0 && i == 0) printf("Number: %d", seqLength-order+1);
   if ((j == 0) && (((seqLength-order+1+1) % 2 == 1))) {/*if (i == 0) printf("Thread %d adding %d (%f) and %d (%f)", j, j, kmer_scores[j], seqLength-order+1, kmer_scores[seqLength-order+1]);*/ kmer_scores[j] = kmer_scores[j] + kmer_scores[seqLength-order+1]; /*if (i == 0) printf(" to get: %f\n", kmer_scores[j]);*/ }
   int k = (seqLength-order+1+1)/2;
   while (k >= 1) {
      //if (i == 0 && j == 0) printf("k is %d\n", k);
      if (j < k) {
	 //if (i == 0) printf("k: %d Thread %d adding %d (%f) and %d (%f) to get: %f\n", k, j, j, kmer_scores[j], j+k, kmer_scores[j+k], kmer_scores[j]+kmer_scores[j+k]);
         kmer_scores[j] = kmer_scores[j] + kmer_scores[j+k]; // Illegal here
      }
      __syncthreads();
      if (k != 1 && k % 2 != 0 && j == 0) {/*printf("k: %d Thread %d adding %d (%f) and %d (%f) to get: %f\n", k, j, j, kmer_scores[j], k-1, kmer_scores[k-1], kmer_scores[j]+kmer_scores[k-1]);*/              kmer_scores[j] = kmer_scores[j] + kmer_scores[k-1]; }// Uneven split, would be left out otherwise.
      k /= 2;
   }

   // The first kmer_score is now the final.
   if (j == 0) {
      scores[i] = kmer_scores[0];
      //printf("Kernel score for sequence %d: %f\n", i, scores[i]);
   }
}



	.text
	.file	"scoreReads.hip"
	.globl	_Z25__device_stub__scoreReadsPciiPfS0_ # -- Begin function _Z25__device_stub__scoreReadsPciiPfS0_
	.type	_Z25__device_stub__scoreReadsPciiPfS0_,@function
_Z25__device_stub__scoreReadsPciiPfS0_: # @_Z25__device_stub__scoreReadsPciiPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rdi
	movl	%esi, (%rdi)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10scoreReadsPciiPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__scoreReadsPciiPfS0_, .Lfunc_end0-_Z25__device_stub__scoreReadsPciiPfS0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10scoreReadsPciiPfS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$mapping, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$80, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	mapping,@object                 # @mapping
	.local	mapping
	.comm	mapping,80,16
	.type	_Z10scoreReadsPciiPfS0_,@object # @_Z10scoreReadsPciiPfS0_
	.section	.rodata,"a",@progbits
	.globl	_Z10scoreReadsPciiPfS0_
	.p2align	3, 0x0
_Z10scoreReadsPciiPfS0_:
	.quad	_Z25__device_stub__scoreReadsPciiPfS0_
	.size	_Z10scoreReadsPciiPfS0_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10scoreReadsPciiPfS0_"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"mapping"
	.size	.L__unnamed_2, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__scoreReadsPciiPfS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym mapping
	.addrsig_sym _Z10scoreReadsPciiPfS0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10scoreReadsPciiPfS0_ ; -- Begin function _Z10scoreReadsPciiPfS0_
	.globl	_Z10scoreReadsPciiPfS0_
	.p2align	8
	.type	_Z10scoreReadsPciiPfS0_,@function
_Z10scoreReadsPciiPfS0_:                ; @_Z10scoreReadsPciiPfS0_
; %bb.0:
	s_load_b64 s[6:7], s[0:1], 0x8
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, s15
	s_mov_b32 s8, 0
	s_mov_b32 s9, -1
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $sgpr10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s15, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, s2, -1, v0
	v_cndmask_b32_e64 v4, v1, s2, vcc_lo
	v_add_nc_u32_e32 v5, s7, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v4, v5
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[2:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v4
	v_mov_b32_e32 v3, 0
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr10
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s2, s3, v2, s2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_u8 v6, v[1:2], off
	s_or_b32 s10, s10, exec_lo
	s_or_b32 s11, s11, exec_lo
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0x4e, v6
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_bfe_i32 v6, v6, 0, 8
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, mapping@rel32@lo-256
	s_addc_u32 s3, s3, mapping@rel32@hi-248
	v_add_nc_u32_e32 v4, 1, v4
	s_and_not1_b32 s10, s10, exec_lo
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, s2, v6, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s2, s3, v7, s2
	v_cmp_ge_i32_e64 s2, v4, v5
	v_add_co_u32 v1, s3, v1, 1
	global_load_b32 v6, v[6:7], off
	v_add_co_ci_u32_e64 v2, s3, 0, v2, s3
	s_and_not1_b32 s3, s11, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s3, s2
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v3, v3, 2, v6
.LBB0_4:                                ; %Flow90
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_xor_b32 s2, s10, -1
	s_and_b32 s3, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s8, s3, s8
	s_and_not1_b32 s3, s9, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s9, s3, s2
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_2
; %bb.5:                                ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s8
	s_mov_b32 s10, 0
	s_or_not1_b32 s9, s9, exec_lo
.LBB0_6:                                ; %Flow91
	s_or_b32 exec_lo, exec_lo, s5
	s_load_b128 s[0:3], s[0:1], 0x10
	v_mov_b32_e32 v2, s10
	s_and_saveexec_b32 s5, s9
	s_cbranch_execz .LBB0_8
; %bb.7:                                ; %._crit_edge
	v_add_nc_u32_e32 v1, 0x40000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v3, v1, vcc_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, s1, v2, s0
	global_load_b32 v2, v[1:2], off
.LBB0_8:                                ; %.critedge
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.9:
	s_sub_i32 s1, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s1, 2
	s_and_b32 s5, s5, 0x80000001
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s5, 1
	s_cbranch_scc1 .LBB0_11
; %bb.10:
	s_lshl_b32 s1, s1, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s1
	ds_load_b32 v4, v2
	ds_load_b32 v3, v3 offset:4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s0
	s_sub_i32 s0, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s0, 2
	s_cmp_lt_i32 s1, 2
	s_cbranch_scc1 .LBB0_20
; %bb.12:
	v_mov_b32_e32 v2, 0
.LBB0_13:                               ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s5, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s5, v0
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	v_lshl_add_u32 v3, s5, 2, v1
	ds_load_b32 v4, v1
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v4, v3
	ds_store_b32 v1, v3
.LBB0_15:                               ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_eq_u32 s5, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_19
; %bb.16:                               ;   in Loop: Header=BB0_13 Depth=1
	s_bitcmp1_b32 s1, 1
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, vcc_lo, s0
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_13 Depth=1
	s_lshl_b32 s6, s5, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s6, 0
	s_add_i32 s6, s6, -4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s6
	ds_load_b32 v4, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB0_18:                               ; %Flow
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_19:                               ;   in Loop: Header=BB0_13 Depth=1
	s_cmp_gt_u32 s1, 3
	s_mov_b32 s1, s5
	s_cbranch_scc1 .LBB0_13
.LBB0_20:                               ; %._crit_edge69
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_mov_b32_e32 v0, 0
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_22:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10scoreReadsPciiPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10scoreReadsPciiPfS0_, .Lfunc_end0-_Z10scoreReadsPciiPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	mapping                 ; @mapping
	.type	mapping,@object
	.data
	.globl	mapping
	.p2align	4, 0x0
mapping:
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.size	mapping, 80

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym mapping
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10scoreReadsPciiPfS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10scoreReadsPciiPfS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
