//#include "stdafx.h"
#include <stdio.h>
#include <math.h>
#include <time.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>

struct pixel
{  
    unsigned char r;
    unsigned char g;
    unsigned char b;
  
};
__device__
int power(int a,int b){
   for (int i=0;i<b;i++){
       a*=a;     
   }
   return a; 
}

__device__
void hamming_code(long *a)
{
    long z=*a;
    int d1,d2,d3,d4,d6,d7,d8,p1,p2,p3,tmp1,tmp2;
    tmp2=power(10,7);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d1=tmp2;
    tmp2=power(10,6);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d2=tmp2;
    tmp2=power(10,5);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d3=tmp2;
    tmp2=power(10,4);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d4=tmp2;
    tmp2=power(10,2);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d6=tmp2;
    tmp2=power(10,1);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d7=tmp2;
    tmp2=(*a)%10;
    d8=tmp2;

    p1=d1^d2^d3;
    p2=d1^d2^d4;
    p3=d1^d3^d4;
    *a=(*a)-100*d6-10*d7-d8+100*p1+10*p2+p3;
return ;
}

__device__
void bit_rotation(long *a)
{
    long z=*a,tmp,tmp1,tmp2,p1,p2,p3;
    tmp1=z/power(10,2);
    tmp2=tmp1%10;
    p1=tmp2;
    tmp1=z/power(10,1);
    tmp2=tmp1%10;
    p2=tmp2;
    tmp2=*a%10;
    p3=tmp2;
    *a=(*a)-100*p1-10*p2-p3;
    tmp=p1;
    p1=p2;
    p2=p3;
    p3=tmp;
    *a=(*a)+100*p1+10*p2+p3;
    return;
}

__device__
void rev_bit_rotation(long *a)
{
    long z=*a,tmp1,tmp2,p1,p2,p3,tmp;
    tmp1=z/power(10,2);
    tmp2=tmp1%10;
    p1=tmp2;
    tmp1=z/power(10,1);
    tmp2=tmp1%10;
    p2=tmp2;
    tmp2=*a%10;
    p3=tmp2;
    *a=(*a)-100*p1-10*p2-p3;
    tmp=p3;
    p3=p2;
    p2=p1;
    p1=tmp;
    //printf("%d\n",*a);
    *a=(*a)+100*p1+10*p2+p3;
    //printf("%d",*a);
    return;
}

__device__
void Torus_Auromorphism(int *a,int *b,int c)
{
    //k=1
    int x,y;
    x = (*a+*b)%c;
    y= (*a + 2*(*b))%c;
 
    *a=x;*b=y;
    return;
}

__device__
void Anti_Torus(int *a,int *b,int c)
{
    int x,y;
    x=(2*(*a)+(-1)*(*b)+100000*c)%c;
    y=((-1)*(*a)+*b+10000*c)%c;
    //printf("a=%d b=%d x=%d y=%d\n",*a,*b,x,y);
    *a=x;*b=y;
    //if(*a=2&&*b2)
    
    //*a=x;*b=y;
}



__device__
int DecToBinary(int num)
{
    int count=0, remainder, base = 1, binary = 0, no_of_1s = 0;
    
    while (num > 0)
    {
        count++;
        remainder = num % 2;
        if (remainder == 1)
        {
            no_of_1s++;
        }
        binary = binary + remainder * base;
        num = num / 2;
        base = base * 10;

    }
    binary+=100000000;

//    printf("binary = %d\n",binary);
    return binary;
}

__device__
int BinToDec(int num){
    num-=100000000;
    int dec=0,k=1,i=0;
    //printf("%d",num);

    while(1){
        
        dec=dec + k*(num%10);
        if(i==0)
            i=1;
        else
            i=2*i;
        if(num==0)
        {
            break;
        }

        k=2*i;
        
        num/=10;
    }
    //printf("\n%d",dec);
    return dec;
}



__global__
void PictureKernel(struct pixel* IPimage, struct pixel* OPimage,long* R,long* G,long* B,int w,int h)
{
    // Calculate the row # of the d_Pin and d_Pout element
    int Col = blockIdx.x*blockDim.x + threadIdx.x;
    // Calculate the column # of the d_Pin and d_Pout element
    int Row = blockIdx.y*blockDim.y + threadIdx.y;
    // each thread computes one element of d_Pout if in range
    
    int tmp1,tmp2;
    tmp2=Col;tmp1=Row;
    Anti_Torus(&tmp1,&tmp2,w);
    
    //Anti Torus
    OPimage[tmp1*w+tmp2]=IPimage[Row*w+Col];
    


    R[Col+Row*w]=DecToBinary(IPimage[Col+Row*w].r);
    G[Col+Row*w]=DecToBinary(IPimage[Col+Row*w].g);
    B[Col+Row*w]=DecToBinary(IPimage[Col+Row*w].b);


    rev_bit_rotation(&R[Col+Row*w]);rev_bit_rotation(&G[Col+Row*w]);rev_bit_rotation(&B[Col+Row*w]);

    IPimage[Col+Row*w].r=BinToDec(R[Col+Row*w]);
    IPimage[Col+Row*w].g=BinToDec(G[Col+Row*w]);
    IPimage[Col+Row*w].b=BinToDec(B[Col+Row*w]);



    return;
}



int main(void)
{
    int i, w, h;
    char blah[3];

    FILE *f, *f2;
    
   

    f=fopen("encrypted.ppm", "rb");
    f2=fopen("plldecrypted.ppm", "wb"); 
    fscanf(f, "%s\n", blah);
    fscanf(f, "%d %d\n", &w, &h);
    fscanf(f, "%d\n", &i);
    struct pixel image[h][w]; 
    fread(&image, sizeof(image), 1, f);
    
  
   // clock_t end = clock();
    //double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
    //printf("%f",time_spent);

    //long R[h][w],G[h][w],B[h][w];
    struct pixel *d_A,*d_F;
    long *d_R,*d_G,*d_B;
    
    long n=w*h;
    //const long size=n;
    const long bytes = 3*sizeof(unsigned char)*n;

    //clock_t begin = clock();
 
    //Assigning memory in device

    cudaMalloc((void **)&d_A,sizeof(pixel)*n);
    cudaMalloc((void **)&d_F,sizeof(pixel)*n);
    cudaMalloc((void **)&d_R,sizeof(long)*n);
    cudaMalloc((void **)&d_G,sizeof(long)*n);
    cudaMalloc((void **)&d_B,sizeof(long)*n);


    cudaMemcpy(d_A,image,bytes,cudaMemcpyHostToDevice);
    clock_t begin = clock();

    dim3 threadsPerBlock(32, 32);
    dim3 numBlocks(w/threadsPerBlock.x,h/threadsPerBlock.y); 

    PictureKernel<<<numBlocks,threadsPerBlock>>>(d_A,d_F,d_R,d_G,d_B,w,h);    

    
    clock_t end = clock();
    double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
    printf("%f microseconds\n",time_spent*1000000);
    
    cudaMemcpy(image,d_F,bytes,cudaMemcpyDeviceToHost);


    cudaFree(d_A);
    cudaFree(d_F);
    cudaFree(d_R);
    cudaFree(d_G);
    cudaFree(d_B);



    fprintf(f2, "%s\n", blah);
    fprintf(f2, "%d %d\n", w, h);
    fprintf(f2, "%d\n", 255);
    
    fwrite(&image, sizeof(image), 1, f2);
    
    fclose(f);
    fclose(f2);
    
    return 0;
}


	.file	"tmpxft_00388512_00000000-6_parallel_decryption.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5powerii
	.type	_Z5powerii, @function
_Z5powerii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z5powerii, .-_Z5powerii
	.globl	_Z12hamming_codePl
	.type	_Z12hamming_codePl, @function
_Z12hamming_codePl:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z12hamming_codePl, .-_Z12hamming_codePl
	.globl	_Z12bit_rotationPl
	.type	_Z12bit_rotationPl, @function
_Z12bit_rotationPl:
.LFB2180:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z12hamming_codePl
	.cfi_endproc
.LFE2180:
	.size	_Z12bit_rotationPl, .-_Z12bit_rotationPl
	.globl	_Z16rev_bit_rotationPl
	.type	_Z16rev_bit_rotationPl, @function
_Z16rev_bit_rotationPl:
.LFB2182:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z12hamming_codePl
	.cfi_endproc
.LFE2182:
	.size	_Z16rev_bit_rotationPl, .-_Z16rev_bit_rotationPl
	.globl	_Z18Torus_AuromorphismPiS_i
	.type	_Z18Torus_AuromorphismPiS_i, @function
_Z18Torus_AuromorphismPiS_i:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z18Torus_AuromorphismPiS_i, .-_Z18Torus_AuromorphismPiS_i
	.globl	_Z10Anti_TorusPiS_i
	.type	_Z10Anti_TorusPiS_i, @function
_Z10Anti_TorusPiS_i:
.LFB2186:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2186:
	.size	_Z10Anti_TorusPiS_i, .-_Z10Anti_TorusPiS_i
	.globl	_Z11DecToBinaryi
	.type	_Z11DecToBinaryi, @function
_Z11DecToBinaryi:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z11DecToBinaryi, .-_Z11DecToBinaryi
	.globl	_Z8BinToDeci
	.type	_Z8BinToDeci, @function
_Z8BinToDeci:
.LFB2184:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z11DecToBinaryi
	.cfi_endproc
.LFE2184:
	.size	_Z8BinToDeci, .-_Z8BinToDeci
	.globl	_Z51__device_stub__Z13PictureKernelP5pixelS0_PlS1_S1_iiP5pixelS0_PlS1_S1_ii
	.type	_Z51__device_stub__Z13PictureKernelP5pixelS0_PlS1_S1_iiP5pixelS0_PlS1_S1_ii, @function
_Z51__device_stub__Z13PictureKernelP5pixelS0_PlS1_S1_iiP5pixelS0_PlS1_S1_ii:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z13PictureKernelP5pixelS0_PlS1_S1_ii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L18:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z51__device_stub__Z13PictureKernelP5pixelS0_PlS1_S1_iiP5pixelS0_PlS1_S1_ii, .-_Z51__device_stub__Z13PictureKernelP5pixelS0_PlS1_S1_iiP5pixelS0_PlS1_S1_ii
	.globl	_Z13PictureKernelP5pixelS0_PlS1_S1_ii
	.type	_Z13PictureKernelP5pixelS0_PlS1_S1_ii, @function
_Z13PictureKernelP5pixelS0_PlS1_S1_ii:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z13PictureKernelP5pixelS0_PlS1_S1_iiP5pixelS0_PlS1_S1_ii
	.cfi_endproc
.LFE2061:
	.size	_Z13PictureKernelP5pixelS0_PlS1_S1_ii, .-_Z13PictureKernelP5pixelS0_PlS1_S1_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"rb"
.LC1:
	.string	"encrypted.ppm"
.LC2:
	.string	"wb"
.LC3:
	.string	"plldecrypted.ppm"
.LC4:
	.string	"%s\n"
.LC5:
	.string	"%d %d\n"
.LC6:
	.string	"%d\n"
.LC8:
	.string	"%f microseconds\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC0(%rip), %rsi
	leaq	.LC1(%rip), %rdi
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	leaq	-59(%rbp), %r15
	leaq	.LC4(%rip), %r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$136, %rsp
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	call	fopen@PLT
	leaq	.LC2(%rip), %rsi
	leaq	.LC3(%rip), %rdi
	movq	%rax, -152(%rbp)
	call	fopen@PLT
	movq	-152(%rbp), %rdi
	movq	%r15, %rdx
	movq	%r14, %rsi
	movq	%rax, -160(%rbp)
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movq	-152(%rbp), %rdi
	xorl	%eax, %eax
	leaq	-132(%rbp), %rcx
	leaq	-136(%rbp), %rdx
	leaq	.LC5(%rip), %rsi
	call	__isoc23_fscanf@PLT
	movq	-152(%rbp), %rdi
	leaq	-140(%rbp), %rdx
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rsi
	call	__isoc23_fscanf@PLT
	movslq	-132(%rbp), %rax
	movslq	-136(%rbp), %rbx
	movq	%rsp, %rcx
	imulq	%rax, %rbx
	leaq	(%rbx,%rbx,2), %rbx
	leaq	15(%rbx), %rdx
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rcx
.L25:
	cmpq	%rcx, %rsp
	je	.L26
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L25
.L26:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L27
	orq	$0, -8(%rsp,%rax)
.L27:
	movq	-152(%rbp), %r8
	movq	%rbx, %rdx
	movq	%rbx, %rsi
	movq	%rsp, %rdi
	movl	$1, %ecx
	movq	%rsp, -168(%rbp)
	call	__fread_chk@PLT
	movl	-136(%rbp), %r13d
	leaq	-128(%rbp), %rdi
	imull	-132(%rbp), %r13d
	movslq	%r13d, %r13
	leaq	0(%r13,%r13,2), %r12
	salq	$3, %r13
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	leaq	-120(%rbp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	-112(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	-104(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	-96(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	-128(%rbp), %rdi
	movq	%r12, %rdx
	movq	%rsp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	call	clock@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	-136(%rbp), %edx
	movq	%rax, %r13
	movl	-132(%rbp), %eax
	movl	$1, %esi
	shrl	$5, %edx
	shrl	$5, %eax
	movl	%edx, -72(%rbp)
	movabsq	$137438953504, %rdx
	movl	%eax, -68(%rbp)
	movq	-72(%rbp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	%rax
	movl	-132(%rbp), %eax
	movq	-104(%rbp), %rcx
	movq	-112(%rbp), %rdx
	movq	-96(%rbp), %r8
	movq	-120(%rbp), %rsi
	pushq	%rax
	movq	-128(%rbp), %rdi
	movl	-136(%rbp), %r9d
	call	_Z51__device_stub__Z13PictureKernelP5pixelS0_PlS1_S1_iiP5pixelS0_PlS1_S1_ii
	popq	%rdx
	popq	%rcx
.L28:
	call	clock@PLT
	movsd	.LC7(%rip), %xmm1
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	subq	%r13, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	%xmm1, %xmm0
	mulsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	-120(%rbp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdx
	movq	-168(%rbp), %rdi
	call	cudaMemcpy@PLT
	movq	-128(%rbp), %rdi
	call	cudaFree@PLT
	movq	-120(%rbp), %rdi
	call	cudaFree@PLT
	movq	-112(%rbp), %rdi
	call	cudaFree@PLT
	movq	-104(%rbp), %rdi
	call	cudaFree@PLT
	movq	-96(%rbp), %rdi
	call	cudaFree@PLT
	movq	%r15, %rcx
	movq	%r14, %rdx
	movl	$2, %esi
	movq	-160(%rbp), %rdi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	-132(%rbp), %r8d
	xorl	%eax, %eax
	movl	-136(%rbp), %ecx
	movq	-160(%rbp), %rdi
	leaq	.LC5(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movq	-160(%rbp), %rdi
	movl	$255, %ecx
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movq	-160(%rbp), %rcx
	movl	$1, %edx
	movq	%rbx, %rsi
	movq	-168(%rbp), %rdi
	call	fwrite@PLT
	movq	-152(%rbp), %rdi
	call	fclose@PLT
	movq	-160(%rbp), %rdi
	call	fclose@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2035:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z13PictureKernelP5pixelS0_PlS1_S1_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13PictureKernelP5pixelS0_PlS1_S1_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC7:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//#include "stdafx.h"
#include <stdio.h>
#include <math.h>
#include <time.h>
#include "hip/hip_runtime.h"



struct pixel
{  
    unsigned char r;
    unsigned char g;
    unsigned char b;
  
};
__device__
int power(int a,int b){
   for (int i=0;i<b;i++){
       a*=a;     
   }
   return a; 
}

__device__
void hamming_code(long *a)
{
    long z=*a;
    int d1,d2,d3,d4,d6,d7,d8,p1,p2,p3,tmp1,tmp2;
    tmp2=power(10,7);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d1=tmp2;
    tmp2=power(10,6);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d2=tmp2;
    tmp2=power(10,5);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d3=tmp2;
    tmp2=power(10,4);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d4=tmp2;
    tmp2=power(10,2);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d6=tmp2;
    tmp2=power(10,1);
    tmp1=z/tmp2;
    tmp2=tmp1%10;
    d7=tmp2;
    tmp2=(*a)%10;
    d8=tmp2;

    p1=d1^d2^d3;
    p2=d1^d2^d4;
    p3=d1^d3^d4;
    *a=(*a)-100*d6-10*d7-d8+100*p1+10*p2+p3;
return ;
}

__device__
void bit_rotation(long *a)
{
    long z=*a,tmp,tmp1,tmp2,p1,p2,p3;
    tmp1=z/power(10,2);
    tmp2=tmp1%10;
    p1=tmp2;
    tmp1=z/power(10,1);
    tmp2=tmp1%10;
    p2=tmp2;
    tmp2=*a%10;
    p3=tmp2;
    *a=(*a)-100*p1-10*p2-p3;
    tmp=p1;
    p1=p2;
    p2=p3;
    p3=tmp;
    *a=(*a)+100*p1+10*p2+p3;
    return;
}

__device__
void rev_bit_rotation(long *a)
{
    long z=*a,tmp1,tmp2,p1,p2,p3,tmp;
    tmp1=z/power(10,2);
    tmp2=tmp1%10;
    p1=tmp2;
    tmp1=z/power(10,1);
    tmp2=tmp1%10;
    p2=tmp2;
    tmp2=*a%10;
    p3=tmp2;
    *a=(*a)-100*p1-10*p2-p3;
    tmp=p3;
    p3=p2;
    p2=p1;
    p1=tmp;
    //printf("%d\n",*a);
    *a=(*a)+100*p1+10*p2+p3;
    //printf("%d",*a);
    return;
}

__device__
void Torus_Auromorphism(int *a,int *b,int c)
{
    //k=1
    int x,y;
    x = (*a+*b)%c;
    y= (*a + 2*(*b))%c;
 
    *a=x;*b=y;
    return;
}

__device__
void Anti_Torus(int *a,int *b,int c)
{
    int x,y;
    x=(2*(*a)+(-1)*(*b)+100000*c)%c;
    y=((-1)*(*a)+*b+10000*c)%c;
    //printf("a=%d b=%d x=%d y=%d\n",*a,*b,x,y);
    *a=x;*b=y;
    //if(*a=2&&*b2)
    
    //*a=x;*b=y;
}



__device__
int DecToBinary(int num)
{
    int count=0, remainder, base = 1, binary = 0, no_of_1s = 0;
    
    while (num > 0)
    {
        count++;
        remainder = num % 2;
        if (remainder == 1)
        {
            no_of_1s++;
        }
        binary = binary + remainder * base;
        num = num / 2;
        base = base * 10;

    }
    binary+=100000000;

//    printf("binary = %d\n",binary);
    return binary;
}

__device__
int BinToDec(int num){
    num-=100000000;
    int dec=0,k=1,i=0;
    //printf("%d",num);

    while(1){
        
        dec=dec + k*(num%10);
        if(i==0)
            i=1;
        else
            i=2*i;
        if(num==0)
        {
            break;
        }

        k=2*i;
        
        num/=10;
    }
    //printf("\n%d",dec);
    return dec;
}



__global__
void PictureKernel(struct pixel* IPimage, struct pixel* OPimage,long* R,long* G,long* B,int w,int h)
{
    // Calculate the row # of the d_Pin and d_Pout element
    int Col = blockIdx.x*blockDim.x + threadIdx.x;
    // Calculate the column # of the d_Pin and d_Pout element
    int Row = blockIdx.y*blockDim.y + threadIdx.y;
    // each thread computes one element of d_Pout if in range
    
    int tmp1,tmp2;
    tmp2=Col;tmp1=Row;
    Anti_Torus(&tmp1,&tmp2,w);
    
    //Anti Torus
    OPimage[tmp1*w+tmp2]=IPimage[Row*w+Col];
    


    R[Col+Row*w]=DecToBinary(IPimage[Col+Row*w].r);
    G[Col+Row*w]=DecToBinary(IPimage[Col+Row*w].g);
    B[Col+Row*w]=DecToBinary(IPimage[Col+Row*w].b);


    rev_bit_rotation(&R[Col+Row*w]);rev_bit_rotation(&G[Col+Row*w]);rev_bit_rotation(&B[Col+Row*w]);

    IPimage[Col+Row*w].r=BinToDec(R[Col+Row*w]);
    IPimage[Col+Row*w].g=BinToDec(G[Col+Row*w]);
    IPimage[Col+Row*w].b=BinToDec(B[Col+Row*w]);



    return;
}



int main(void)
{
    int i, w, h;
    char blah[3];

    FILE *f, *f2;
    
   

    f=fopen("encrypted.ppm", "rb");
    f2=fopen("plldecrypted.ppm", "wb"); 
    fscanf(f, "%s\n", blah);
    fscanf(f, "%d %d\n", &w, &h);
    fscanf(f, "%d\n", &i);
    struct pixel image[h][w]; 
    fread(&image, sizeof(image), 1, f);
    
  
   // clock_t end = clock();
    //double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
    //printf("%f",time_spent);

    //long R[h][w],G[h][w],B[h][w];
    struct pixel *d_A,*d_F;
    long *d_R,*d_G,*d_B;
    
    long n=w*h;
    //const long size=n;
    const long bytes = 3*sizeof(unsigned char)*n;

    //clock_t begin = clock();
 
    //Assigning memory in device

    hipMalloc((void **)&d_A,sizeof(pixel)*n);
    hipMalloc((void **)&d_F,sizeof(pixel)*n);
    hipMalloc((void **)&d_R,sizeof(long)*n);
    hipMalloc((void **)&d_G,sizeof(long)*n);
    hipMalloc((void **)&d_B,sizeof(long)*n);


    hipMemcpy(d_A,image,bytes,hipMemcpyHostToDevice);
    clock_t begin = clock();

    dim3 threadsPerBlock(32, 32);
    dim3 numBlocks(w/threadsPerBlock.x,h/threadsPerBlock.y); 

    PictureKernel<<<numBlocks,threadsPerBlock>>>(d_A,d_F,d_R,d_G,d_B,w,h);    

    
    clock_t end = clock();
    double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
    printf("%f microseconds\n",time_spent*1000000);
    
    hipMemcpy(image,d_F,bytes,hipMemcpyDeviceToHost);


    hipFree(d_A);
    hipFree(d_F);
    hipFree(d_R);
    hipFree(d_G);
    hipFree(d_B);



    fprintf(f2, "%s\n", blah);
    fprintf(f2, "%d %d\n", w, h);
    fprintf(f2, "%d\n", 255);
    
    fwrite(&image, sizeof(image), 1, f2);
    
    fclose(f);
    fclose(f2);
    
    return 0;
}


	.text
	.file	"parallel_decryption.hip"
	.globl	_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii # -- Begin function _Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii
	.type	_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii,@function
_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii: # @_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13PictureKernelP5pixelS0_PlS1_S1_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii, .Lfunc_end0-_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.2, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	-51(%rbp), %rdx
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	leaq	-48(%rbp), %rdx
	leaq	-44(%rbp), %rcx
	movl	$.L.str.5, %esi
	movq	%rbx, %rdi
	movq	%rdx, %r12
	movq	%rcx, %r15
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	leaq	-124(%rbp), %rdx
	movl	$.L.str.6, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	%rsp, -112(%rbp)                # 8-byte Spill
	movl	(%r15), %eax
	movq	%r15, %r13
	movl	(%r12), %ecx
	imulq	%rax, %rcx
	leaq	(%rcx,%rcx,2), %rax
	addq	$15, %rax
	andq	$-16, %rax
	movq	%rsp, %r15
	subq	%rax, %r15
	leaq	(%rcx,%rcx,2), %rsi
	movq	%r15, %rsp
	movl	$1, %edx
	movq	%r15, %rdi
	movq	%rsi, -104(%rbp)                # 8-byte Spill
	movq	%rbx, -120(%rbp)                # 8-byte Spill
	movq	%rbx, %rcx
	callq	fread
	movslq	(%r12), %rax
	movslq	(%r13), %r12
	imulq	%rax, %r12
	leaq	(%r12,%r12,2), %r13
	leaq	-96(%rbp), %rbx
	movq	%rbx, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	-64(%rbp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	shlq	$3, %r12
	leaq	-88(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	-80(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	-72(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r15, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	callq	clock
	movq	%rax, %r12
	leaq	-48(%rbp), %rax
	movl	(%rax), %eax
	shrl	$5, %eax
	leaq	-44(%rbp), %rcx
	movl	(%rcx), %edi
	shrl	$5, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	-96(%rbp), %rdi
	movq	-64(%rbp), %rsi
	movq	-88(%rbp), %rdx
	movq	-80(%rbp), %rcx
	movq	-72(%rbp), %r8
	movl	-48(%rbp), %r9d
	movl	-44(%rbp), %eax
	subq	$8, %rsp
	pushq	%rax
	callq	_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii
	addq	$16, %rsp
.LBB1_2:
	callq	clock
	subq	%r12, %rax
	cvtsi2sd	%rax, %xmm0
	movsd	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm1, %xmm0
	mulsd	%xmm1, %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	movq	-64(%rbp), %rsi
	movq	%r15, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	-96(%rbp), %rdi
	callq	hipFree
	movq	-64(%rbp), %rdi
	callq	hipFree
	movq	-88(%rbp), %rdi
	callq	hipFree
	movq	-80(%rbp), %rdi
	callq	hipFree
	movq	-72(%rbp), %rdi
	callq	hipFree
	leaq	-51(%rbp), %rdx
	movl	$.L.str.4, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movl	-48(%rbp), %edx
	movl	-44(%rbp), %ecx
	movl	$.L.str.5, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movl	$.L.str.6, %esi
	movq	%r14, %rdi
	movl	$255, %edx
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edx
	movq	%r15, %rdi
	movq	-104(%rbp), %rsi                # 8-byte Reload
	movq	%r14, %rcx
	callq	fwrite
	movq	-120(%rbp), %rdi                # 8-byte Reload
	callq	fclose
	movq	%r14, %rdi
	callq	fclose
	movq	-112(%rbp), %rsp                # 8-byte Reload
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13PictureKernelP5pixelS0_PlS1_S1_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13PictureKernelP5pixelS0_PlS1_S1_ii,@object # @_Z13PictureKernelP5pixelS0_PlS1_S1_ii
	.section	.rodata,"a",@progbits
	.globl	_Z13PictureKernelP5pixelS0_PlS1_S1_ii
	.p2align	3, 0x0
_Z13PictureKernelP5pixelS0_PlS1_S1_ii:
	.quad	_Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii
	.size	_Z13PictureKernelP5pixelS0_PlS1_S1_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"encrypted.ppm"
	.size	.L.str, 14

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"rb"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"plldecrypted.ppm"
	.size	.L.str.2, 17

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"wb"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%s\n"
	.size	.L.str.4, 4

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d %d\n"
	.size	.L.str.5, 7

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%d\n"
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%f microseconds\n"
	.size	.L.str.7, 17

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13PictureKernelP5pixelS0_PlS1_S1_ii"
	.size	.L__unnamed_1, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__PictureKernelP5pixelS0_PlS1_S1_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13PictureKernelP5pixelS0_PlS1_S1_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13PictureKernelP5pixelS0_PlS1_S1_ii ; -- Begin function _Z13PictureKernelP5pixelS0_PlS1_S1_ii
	.globl	_Z13PictureKernelP5pixelS0_PlS1_S1_ii
	.p2align	8
	.type	_Z13PictureKernelP5pixelS0_PlS1_S1_ii,@function
_Z13PictureKernelP5pixelS0_PlS1_S1_ii:  ; @_Z13PictureKernelP5pixelS0_PlS1_S1_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x28
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_load_b64 s[0:1], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[5:6], null, s15, s12, v[0:1]
	s_ashr_i32 s2, s3, 31
	s_add_i32 s12, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_xor_b32 s2, s12, s2
	s_mul_i32 s12, s3, 0x186a0
	v_mad_u64_u32 v[2:3], null, v5, s3, v[4:5]
	v_cvt_f32_u32_e32 v3, s2
	v_sub_nc_u32_e32 v9, s12, v4
	v_mad_u64_u32 v[6:7], null, 0x2710, s3, v[4:5]
	s_sub_i32 s12, 0, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rcp_iflag_f32_e32 v3, v3
	v_mad_i64_i32 v[0:1], null, v2, 3, s[4:5]
	v_lshl_add_u32 v7, v5, 1, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v6, v5
	v_ashrrev_i32_e32 v6, 31, v7
	global_load_u16 v8, v[0:1], off
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_ashrrev_i32_e32 v9, 31, v5
	v_add_nc_u32_e32 v7, v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v3, v3
	v_add_nc_u32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v6
	v_mul_lo_u32 v4, s12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	v_xor_b32_e32 v4, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v7, v3
	v_mul_hi_u32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, s2
	v_mul_lo_u32 v3, v3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v7, v5
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v4, s2, v5
	v_cmp_le_u32_e32 vcc_lo, s2, v5
	v_subrev_nc_u32_e32 v7, s2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v5, v4, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v3
	v_subrev_nc_u32_e32 v5, s2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	v_subrev_nc_u32_e32 v7, s2, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v3
	s_mov_b32 s2, exec_lo
	v_xor_b32_e32 v4, v4, v6
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v4, v6
	v_xor_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v9
	v_mad_u64_u32 v[4:5], null, v6, s3, v[3:4]
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[5:6], null, v4, 3, s[6:7]
	s_mov_b32 s6, 1
	s_waitcnt vmcnt(0)
	global_store_b16 v[5:6], v8, off
	v_mov_b32_e32 v8, 0x5f5e100
	global_load_u8 v3, v[0:1], off offset:2
	v_mov_b32_e32 v9, 0
	s_waitcnt vmcnt(0)
	global_store_b8 v[5:6], v3, off offset:2
	global_load_u8 v4, v[0:1], off
	v_ashrrev_i32_e32 v3, 31, v2
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v4
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.lr.ph.i.preheader
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v5, 0xffff, v4
.LBB0_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfe_i32 v6, v5, 0, 1
	v_lshrrev_b32_e32 v7, 1, v5
	v_cmp_gt_u32_e32 vcc_lo, 2, v5
	v_dual_mov_b32 v5, v7 :: v_dual_and_b32 v6, s6, v6
	s_or_b32 s3, vcc_lo, s3
	s_mul_i32 s6, s6, 10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v6, v4
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %._crit_edge.loopexit.i
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, 0x5f5e100, v4
.LBB0_4:                                ; %Flow181
	s_or_b32 exec_lo, exec_lo, s2
	v_mad_i64_i32 v[4:5], null, v2, 3, s[4:5]
	v_lshlrev_b64 v[10:11], 3, v[2:3]
	v_mov_b32_e32 v12, 0x5f5e100
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s8, v10
	global_load_u8 v14, v[4:5], off offset:1
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v11, vcc_lo
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v14
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.lr.ph.i75.preheader
	v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v9, 0xffff, v14
	s_mov_b32 s4, 1
.LBB0_6:                                ; %.lr.ph.i75
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfe_i32 v12, v9, 0, 1
	v_lshrrev_b32_e32 v13, 1, v9
	v_cmp_gt_u32_e32 vcc_lo, 2, v9
	v_dual_mov_b32 v9, v13 :: v_dual_and_b32 v12, s4, v12
	s_or_b32 s3, vcc_lo, s3
	s_mul_i32 s4, s4, 10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v8, v12, v8
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %._crit_edge.loopexit.i81
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, 0x5f5e100, v8
.LBB0_8:                                ; %Flow180
	s_or_b32 exec_lo, exec_lo, s2
	global_load_u8 v16, v[4:5], off offset:2
	v_add_co_u32 v8, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v11, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, 2
	v_mov_b32_e32 v14, 0x5f5e100
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v16
	s_cbranch_execz .LBB0_12
; %bb.9:                                ; %.lr.ph.i84.preheader
	v_dual_mov_b32 v12, 0 :: v_dual_and_b32 v13, 0xffff, v16
	s_mov_b32 s4, 1
.LBB0_10:                               ; %.lr.ph.i84
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfe_i32 v14, v13, 0, 1
	v_lshrrev_b32_e32 v15, 1, v13
	v_cmp_gt_u32_e32 vcc_lo, 2, v13
	v_dual_mov_b32 v13, v15 :: v_dual_and_b32 v14, s4, v14
	s_or_b32 s3, vcc_lo, s3
	s_mul_i32 s4, s4, 10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v12, v14, v12
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_10
; %bb.11:                               ; %._crit_edge.loopexit.i90
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v15, 0 :: v_dual_add_nc_u32 v14, 0x5f5e100, v12
.LBB0_12:                               ; %Flow179
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	s_mov_b32 s0, 0x1ac70dd0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, 0x28d, s0
	global_store_b64 v[10:11], v[14:15], off
	global_load_b64 v[12:13], v[6:7], off
	v_add_co_u32 v14, s0, 0xa0000000, s0
	s_addc_u32 s1, 0, 0
	s_cmp_lg_u32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readfirstlane_b32 s0, v14
	s_addc_u32 s1, s1, 0x68db8
	s_mul_i32 s2, s1, 0xffffd8f0
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s3, s0, 0xffffd8f0
	s_mul_i32 s4, s0, 0xffffd8f0
	s_add_i32 s3, s3, s2
	s_mul_hi_u32 s2, s1, s4
	s_sub_i32 s3, s3, s0
	s_mul_i32 s5, s1, s4
	s_mul_hi_u32 s4, s0, s4
	s_mul_hi_u32 s7, s0, s3
	s_mul_i32 s0, s0, s3
	s_mul_hi_u32 s6, s1, s3
	s_add_u32 s0, s4, s0
	s_addc_u32 s4, 0, s7
	s_add_u32 s0, s0, s5
	s_mul_i32 s3, s1, s3
	s_addc_u32 s0, s4, s2
	s_addc_u32 s2, s6, 0
	s_add_u32 s0, s0, s3
	s_addc_u32 s2, 0, s2
	v_add_co_u32 v15, s0, v14, s0
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u32 s0, 0
	s_addc_u32 s3, s1, s2
	s_add_u32 s1, 0, 0x99986000
	s_addc_u32 s0, 0, 0x59
	s_mul_hi_u32 s4, s1, -10
	s_add_i32 s5, s0, 0x19999940
	s_mul_i32 s2, s1, -10
	s_mul_i32 s0, s5, -10
	s_mul_hi_u32 s6, s1, s2
	s_add_i32 s4, s4, s0
	s_mul_hi_u32 s7, s5, s2
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v16, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, v12, v16
	v_add_co_ci_u32_e32 v14, vcc_lo, v13, v16, vcc_lo
	v_xor_b32_e32 v29, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v30, v14, v16
	v_mad_u64_u32 v[17:18], null, v29, s3, 0
	v_mul_hi_u32 v14, v29, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[19:20], null, v30, v15, 0
	v_mad_u64_u32 v[21:22], null, v30, s3, 0
	v_mul_hi_u32 v33, 0xf5c28f5c, v29
	v_add_co_u32 v14, vcc_lo, v14, v17
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v14, v19
	v_add_co_ci_u32_e32 v14, vcc_lo, v17, v20, vcc_lo
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, v14, v21
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0x2710, v20, 0
	v_mov_b32_e32 v14, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[18:19], null, 0x2710, v21, v[14:15]
	v_sub_co_u32 v14, vcc_lo, v29, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v17, vcc_lo, v30, v18, vcc_lo
	v_subrev_co_u32 v18, vcc_lo, 0x2710, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v19, vcc_lo, 0, v17, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x270f, v18
	v_cmp_eq_u32_e64 s0, 0, v17
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_add_co_u32 v22, vcc_lo, v20, 2
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v21, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x270f, v14
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, -1, v14, s0
	v_cndmask_b32_e32 v18, -1, v18, vcc_lo
	v_add_co_u32 v19, vcc_lo, v20, 1
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v21, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v18
	s_mul_i32 s0, s5, s2
	s_sub_i32 s2, s4, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s8, s1, s2
	v_dual_cndmask_b32 v17, v24, v23 :: v_dual_cndmask_b32 v18, v19, v22
	v_cmp_ne_u32_e32 vcc_lo, 0, v14
	s_mul_hi_u32 s4, s1, s2
	s_add_u32 s6, s6, s8
	s_addc_u32 s4, 0, s4
	s_mul_hi_u32 s9, s5, s2
	v_dual_cndmask_b32 v14, v21, v17 :: v_dual_cndmask_b32 v17, v20, v18
	s_add_u32 s0, s6, s0
	s_mul_i32 s2, s5, s2
	s_addc_u32 s0, s4, s7
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v14, v14, v16
	v_xor_b32_e32 v17, v17, v16
	s_addc_u32 s4, s9, 0
	s_add_u32 s0, s0, s2
	s_addc_u32 s2, 0, s4
	v_mad_u64_u32 v[23:24], null, 0x28f5c28, v30, 0
	v_sub_co_u32 v17, vcc_lo, v17, v16
	v_sub_co_ci_u32_e32 v19, vcc_lo, v14, v16, vcc_lo
	v_add_co_u32 v14, s0, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s0, 0
	v_ashrrev_i32_e32 v31, 31, v19
	s_addc_u32 s2, s5, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v17, v31
	v_add_co_ci_u32_e32 v21, vcc_lo, v19, v31, vcc_lo
	v_mad_u64_u32 v[17:18], null, 0xf5c28f5c, v30, 0
	v_xor_b32_e32 v32, v20, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v34, v21, v31
	v_mad_u64_u32 v[19:20], null, 0x28f5c28, v29, 0
	v_mad_u64_u32 v[21:22], null, v32, s2, 0
	v_mul_hi_u32 v35, v32, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[25:26], null, v34, v14, 0
	v_mad_u64_u32 v[27:28], null, v34, s2, 0
	v_add_co_u32 v21, vcc_lo, v35, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	v_add_co_u32 v19, vcc_lo, v33, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v21, vcc_lo, v21, v25
	v_add_co_ci_u32_e32 v25, vcc_lo, v22, v26, vcc_lo
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v28, vcc_lo
	v_add_co_u32 v17, vcc_lo, v19, v17
	v_add_co_ci_u32_e32 v17, vcc_lo, v20, v18, vcc_lo
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v24, vcc_lo
	v_mad_u64_u32 v[19:20], null, v29, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v28, vcc_lo, v17, v23
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v18, vcc_lo
	v_add_co_u32 v23, s0, v25, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[17:18], null, 0x64, v28, 0
	v_add_co_ci_u32_e64 v25, s0, 0, v26, s0
	v_mul_hi_u32 v35, v29, v14
	v_mad_u64_u32 v[21:22], null, 0x64, v33, v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_co_u32 v22, vcc_lo, v29, v17
	v_mad_u64_u32 v[17:18], null, v23, 10, 0
	v_sub_co_ci_u32_e32 v21, vcc_lo, v30, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v24, vcc_lo, 0x64, v22
	v_subrev_co_ci_u32_e32 v23, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v24
	v_cmp_eq_u32_e64 s0, 0, v21
	v_cndmask_b32_e64 v24, 0, -1, vcc_lo
	v_add_co_u32 v26, vcc_lo, v28, 2
	v_add_co_ci_u32_e32 v27, vcc_lo, 0, v33, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v22
	v_cndmask_b32_e64 v22, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v23
	v_cndmask_b32_e32 v23, -1, v24, vcc_lo
	v_add_co_u32 v24, vcc_lo, v28, 1
	v_add_co_ci_u32_e32 v36, vcc_lo, 0, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v23
	v_cndmask_b32_e64 v23, -1, v22, s0
	v_mad_u64_u32 v[21:22], null, v30, s2, 0
	v_cndmask_b32_e32 v27, v36, v27, vcc_lo
	v_cndmask_b32_e32 v26, v24, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v23
	v_mad_u64_u32 v[23:24], null, v30, v14, 0
	v_dual_cndmask_b32 v27, v33, v27 :: v_dual_cndmask_b32 v26, v28, v26
	v_add_co_u32 v28, vcc_lo, v35, v19
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v20, vcc_lo
	v_mad_u64_u32 v[19:20], null, v25, 10, v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v26, v16
	v_xor_b32_e32 v20, v27, v16
	v_sub_co_u32 v27, vcc_lo, v32, v17
	v_sub_co_u32 v17, s0, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_co_ci_u32_e64 v18, s0, v20, v16, s0
	v_sub_co_ci_u32_e32 v19, vcc_lo, v34, v19, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 9, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v32, 31, v18
	v_cndmask_b32_e64 v20, 0, -1, vcc_lo
	v_sub_co_u32 v34, vcc_lo, v27, 10
	v_subrev_co_ci_u32_e32 v25, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v17, vcc_lo, v17, v32
	v_add_co_ci_u32_e32 v18, vcc_lo, v18, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s0, 9, v34
	v_xor_b32_e32 v36, v17, v32
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_4)
	v_xor_b32_e32 v38, v18, v32
	v_add_nc_u32_e32 v35, -10, v34
	v_cndmask_b32_e64 v26, 0, -1, s0
	v_mad_u64_u32 v[17:18], null, v36, s2, 0
	v_mul_hi_u32 v39, v36, v14
	v_cndmask_b32_e32 v37, -1, v20, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	v_mad_u64_u32 v[19:20], null, v38, v14, 0
	v_cndmask_b32_e32 v40, -1, v26, vcc_lo
	v_add_co_u32 v17, vcc_lo, v39, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v40
	v_mad_u64_u32 v[25:26], null, v38, s2, 0
	v_cndmask_b32_e32 v34, v34, v35, vcc_lo
	v_add_co_u32 v17, vcc_lo, v17, v19
	v_add_co_ci_u32_e32 v17, vcc_lo, v18, v20, vcc_lo
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v26, vcc_lo
	v_add_co_u32 v19, vcc_lo, v28, v23
	v_add_co_ci_u32_e32 v19, vcc_lo, v33, v24, vcc_lo
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	v_add_co_u32 v20, s0, v17, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v21, vcc_lo, v19, v21
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v22, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v37
	v_add_co_ci_u32_e64 v23, s0, 0, v18, s0
	v_mad_u64_u32 v[17:18], null, v20, 10, 0
	v_mad_u64_u32 v[19:20], null, v21, 10, 0
	v_cndmask_b32_e32 v21, v27, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v17, vcc_lo, v36, v17
	v_xor_b32_e32 v25, v21, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[21:22], null, v23, 10, v[18:19]
	v_sub_co_u32 v18, s0, v29, v19
	v_cmp_lt_u32_e64 s1, 9, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v19, vcc_lo, v38, v21, vcc_lo
	v_mad_u64_u32 v[22:23], null, v24, 10, v[20:21]
	v_sub_co_u32 v20, vcc_lo, v17, 10
	v_subrev_co_ci_u32_e32 v23, vcc_lo, 0, v19, vcc_lo
	v_cndmask_b32_e64 v21, 0, -1, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e32 vcc_lo, 9, v20
	v_cndmask_b32_e64 v24, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	v_cndmask_b32_e32 v21, -1, v21, vcc_lo
	v_sub_co_ci_u32_e64 v22, vcc_lo, v30, v22, s0
	v_cmp_lt_u32_e64 s0, 9, v18
	v_sub_co_u32 v26, vcc_lo, v18, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v30, vcc_lo, 0, v22, vcc_lo
	v_cndmask_b32_e64 v27, 0, -1, s0
	v_sub_co_u32 v28, s0, v20, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v29, s0, 0, v23, s0
	v_cmp_eq_u32_e64 s0, 0, v23
	v_cmp_lt_u32_e32 vcc_lo, 9, v26
	v_cmp_eq_u32_e64 s1, 0, v30
	v_cndmask_b32_e64 v24, -1, v24, s0
	v_cndmask_b32_e64 v33, 0, -1, vcc_lo
	v_cmp_ne_u32_e64 s0, 0, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v24
	v_cndmask_b32_e64 v21, -1, v33, s1
	v_sub_co_u32 v24, s1, v26, 10
	v_cndmask_b32_e32 v23, v23, v29, vcc_lo
	v_subrev_co_ci_u32_e64 v29, s1, 0, v30, s1
	v_cmp_eq_u32_e64 s1, 0, v22
	v_cndmask_b32_e32 v20, v20, v28, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v21
	v_cndmask_b32_e64 v19, v19, v23, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, -1, v27, s1
	v_cndmask_b32_e64 v17, v17, v20, s0
	v_cndmask_b32_e32 v20, v26, v24, vcc_lo
	v_cndmask_b32_e32 v23, v30, v29, vcc_lo
	v_xor_b32_e32 v19, v19, v32
	v_cmp_ne_u32_e32 vcc_lo, 0, v21
	v_xor_b32_e32 v17, v17, v32
	v_sub_nc_u32_e32 v21, v25, v31
	v_cndmask_b32_e32 v18, v18, v20, vcc_lo
	v_cndmask_b32_e32 v22, v22, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_co_u32 v17, vcc_lo, v17, v32
	v_sub_co_ci_u32_e32 v19, vcc_lo, v19, v32, vcc_lo
	v_xor_b32_e32 v18, v18, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v20, v22, v16
	v_sub_nc_u32_e32 v22, v21, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v18, vcc_lo, v18, v16
	v_sub_co_ci_u32_e32 v16, vcc_lo, v20, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_i32_i24_e32 v20, 10, v22
	v_sub_nc_u32_e32 v21, v18, v21
	v_sub_co_u32 v12, vcc_lo, v12, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v13, vcc_lo, v13, v16, vcc_lo
	v_mul_i32_i24_e32 v18, 0x64, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, v12, v17
	v_mul_hi_i32_i24_e32 v16, 0x64, v21
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v19, vcc_lo
	v_mul_i32_i24_e32 v17, 10, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, v12, v18
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v12, v17
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v20, vcc_lo
	global_store_b64 v[6:7], v[12:13], off
	global_load_b64 v[12:13], v[8:9], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v28, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v12, v28
	v_add_co_ci_u32_e32 v17, vcc_lo, v13, v28, vcc_lo
	v_xor_b32_e32 v29, v16, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v30, v17, v28
	v_mad_u64_u32 v[16:17], null, v29, s3, 0
	v_mul_hi_u32 v22, v29, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[18:19], null, v30, v15, 0
	v_mad_u64_u32 v[20:21], null, v30, s3, 0
	v_mul_hi_u32 v33, 0xf5c28f5c, v29
	v_add_co_u32 v16, vcc_lo, v22, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v16, v18
	v_add_co_ci_u32_e32 v16, vcc_lo, v17, v19, vcc_lo
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, v16, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0x2710, v20, 0
	v_mad_u64_u32 v[18:19], null, 0x2710, v21, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v16, vcc_lo, v29, v16
	v_sub_co_ci_u32_e32 v17, vcc_lo, v30, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v18, vcc_lo, 0x2710, v16
	v_subrev_co_ci_u32_e32 v19, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, 0x270f, v18
	v_cmp_eq_u32_e64 s0, 0, v17
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_add_co_u32 v22, vcc_lo, v20, 2
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v21, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x270f, v16
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, -1, v16, s0
	v_cndmask_b32_e32 v18, -1, v18, vcc_lo
	v_add_co_u32 v19, vcc_lo, v20, 1
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v21, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v24, v23 :: v_dual_cndmask_b32 v18, v19, v22
	v_cmp_ne_u32_e32 vcc_lo, 0, v16
	v_mad_u64_u32 v[22:23], null, 0x28f5c28, v30, 0
	v_dual_cndmask_b32 v16, v21, v17 :: v_dual_cndmask_b32 v17, v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v16, v16, v28
	v_xor_b32_e32 v17, v17, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v17, vcc_lo, v17, v28
	v_sub_co_ci_u32_e32 v18, vcc_lo, v16, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v31, 31, v18
	v_add_co_u32 v19, vcc_lo, v17, v31
	v_add_co_ci_u32_e32 v20, vcc_lo, v18, v31, vcc_lo
	v_mad_u64_u32 v[16:17], null, 0xf5c28f5c, v30, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v32, v19, v31
	v_xor_b32_e32 v34, v20, v31
	v_mad_u64_u32 v[18:19], null, 0x28f5c28, v29, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[20:21], null, v32, s2, 0
	v_mul_hi_u32 v35, v32, v14
	v_mad_u64_u32 v[24:25], null, v34, v14, 0
	v_mad_u64_u32 v[26:27], null, v34, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, v35, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v18, vcc_lo, v33, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, v20, v24
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v24, vcc_lo, v21, v25, vcc_lo
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v16, vcc_lo, v18, v16
	v_add_co_ci_u32_e32 v16, vcc_lo, v19, v17, vcc_lo
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v23, vcc_lo
	v_mad_u64_u32 v[18:19], null, v29, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v27, vcc_lo, v16, v22
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v22, s0, v24, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, 0x64, v27, 0
	v_add_co_ci_u32_e64 v24, s0, 0, v25, s0
	v_mul_hi_u32 v35, v29, v14
	v_mad_u64_u32 v[20:21], null, 0x64, v33, v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_co_u32 v21, vcc_lo, v29, v16
	v_mad_u64_u32 v[16:17], null, v22, 10, 0
	v_sub_co_ci_u32_e32 v20, vcc_lo, v30, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v23, vcc_lo, 0x64, v21
	v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v23
	v_cmp_eq_u32_e64 s0, 0, v20
	v_cndmask_b32_e64 v23, 0, -1, vcc_lo
	v_add_co_u32 v25, vcc_lo, v27, 2
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v33, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v21
	v_cndmask_b32_e64 v21, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v22
	v_cndmask_b32_e32 v22, -1, v23, vcc_lo
	v_add_co_u32 v23, vcc_lo, v27, 1
	v_add_co_ci_u32_e32 v36, vcc_lo, 0, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v22
	v_cndmask_b32_e64 v22, -1, v21, s0
	v_mad_u64_u32 v[20:21], null, v30, s2, 0
	v_dual_cndmask_b32 v25, v23, v25 :: v_dual_cndmask_b32 v26, v36, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v22
	v_mad_u64_u32 v[22:23], null, v30, v14, 0
	v_dual_cndmask_b32 v25, v27, v25 :: v_dual_cndmask_b32 v26, v33, v26
	v_add_co_u32 v27, vcc_lo, v35, v18
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v19, vcc_lo
	v_mad_u64_u32 v[18:19], null, v24, 10, v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v17, v25, v28
	v_xor_b32_e32 v19, v26, v28
	v_sub_co_u32 v26, vcc_lo, v32, v16
	v_sub_co_u32 v16, s0, v17, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_co_ci_u32_e64 v17, s0, v19, v28, s0
	v_sub_co_ci_u32_e32 v18, vcc_lo, v34, v18, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 9, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v32, 31, v17
	v_cndmask_b32_e64 v19, 0, -1, vcc_lo
	v_sub_co_u32 v34, vcc_lo, v26, 10
	v_subrev_co_ci_u32_e32 v24, vcc_lo, 0, v18, vcc_lo
	v_add_co_u32 v16, vcc_lo, v16, v32
	v_add_co_ci_u32_e32 v17, vcc_lo, v17, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s0, 9, v34
	v_xor_b32_e32 v36, v16, v32
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_4)
	v_xor_b32_e32 v38, v17, v32
	v_add_nc_u32_e32 v35, -10, v34
	v_cndmask_b32_e64 v25, 0, -1, s0
	v_mad_u64_u32 v[16:17], null, v36, s2, 0
	v_mul_hi_u32 v39, v36, v14
	v_cndmask_b32_e32 v37, -1, v19, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v24
	v_mad_u64_u32 v[18:19], null, v38, v14, 0
	v_cndmask_b32_e32 v40, -1, v25, vcc_lo
	v_add_co_u32 v16, vcc_lo, v39, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v40
	v_mad_u64_u32 v[24:25], null, v38, s2, 0
	v_cndmask_b32_e32 v34, v34, v35, vcc_lo
	v_add_co_u32 v16, vcc_lo, v16, v18
	v_add_co_ci_u32_e32 v16, vcc_lo, v17, v19, vcc_lo
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v25, vcc_lo
	v_add_co_u32 v18, vcc_lo, v27, v22
	v_add_co_ci_u32_e32 v18, vcc_lo, v33, v23, vcc_lo
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v19, s0, v16, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v18, v20
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v21, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v37
	v_add_co_ci_u32_e64 v22, s0, 0, v17, s0
	v_mad_u64_u32 v[16:17], null, v19, 10, 0
	v_mad_u64_u32 v[18:19], null, v20, 10, 0
	v_cndmask_b32_e32 v20, v26, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v16, vcc_lo, v36, v16
	v_xor_b32_e32 v24, v20, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[20:21], null, v22, 10, v[17:18]
	v_sub_co_u32 v17, s0, v29, v18
	v_cmp_lt_u32_e64 s1, 9, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v18, vcc_lo, v38, v20, vcc_lo
	v_mad_u64_u32 v[21:22], null, v23, 10, v[19:20]
	v_sub_co_u32 v19, vcc_lo, v16, 10
	v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v18, vcc_lo
	v_cndmask_b32_e64 v20, 0, -1, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e32 vcc_lo, 9, v19
	v_cndmask_b32_e64 v23, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e32 v20, -1, v20, vcc_lo
	v_sub_co_ci_u32_e64 v21, vcc_lo, v30, v21, s0
	v_cmp_lt_u32_e64 s0, 9, v17
	v_sub_co_u32 v25, vcc_lo, v17, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v30, vcc_lo, 0, v21, vcc_lo
	v_cndmask_b32_e64 v26, 0, -1, s0
	v_sub_co_u32 v27, s0, v19, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v29, s0, 0, v22, s0
	v_cmp_eq_u32_e64 s0, 0, v22
	v_cmp_lt_u32_e32 vcc_lo, 9, v25
	v_cmp_eq_u32_e64 s1, 0, v30
	v_cndmask_b32_e64 v23, -1, v23, s0
	v_cndmask_b32_e64 v33, 0, -1, vcc_lo
	v_cmp_ne_u32_e64 s0, 0, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v23
	v_cndmask_b32_e64 v20, -1, v33, s1
	v_sub_co_u32 v23, s1, v25, 10
	v_cndmask_b32_e32 v22, v22, v29, vcc_lo
	v_subrev_co_ci_u32_e64 v29, s1, 0, v30, s1
	v_cmp_eq_u32_e64 s1, 0, v21
	v_cndmask_b32_e32 v19, v19, v27, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v20
	v_cndmask_b32_e64 v18, v18, v22, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, -1, v26, s1
	v_cndmask_b32_e64 v16, v16, v19, s0
	v_dual_cndmask_b32 v22, v30, v29 :: v_dual_cndmask_b32 v19, v25, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v18, v18, v32
	v_cmp_ne_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v32
	v_sub_nc_u32_e32 v20, v24, v31
	v_cndmask_b32_e32 v17, v17, v19, vcc_lo
	v_cndmask_b32_e32 v21, v21, v22, vcc_lo
	v_sub_co_u32 v16, vcc_lo, v16, v32
	v_sub_co_ci_u32_e32 v18, vcc_lo, v18, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v17, v17, v28
	v_xor_b32_e32 v19, v21, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v21, v20, v16
	v_sub_co_u32 v17, vcc_lo, v17, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v19, vcc_lo, v19, v28, vcc_lo
	v_mul_hi_i32_i24_e32 v22, 10, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v20, v17, v20
	v_sub_co_u32 v12, vcc_lo, v12, v17
	v_sub_co_ci_u32_e32 v13, vcc_lo, v13, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_i32_i24_e32 v19, 0x64, v20
	v_add_co_u32 v12, vcc_lo, v12, v16
	v_mul_hi_i32_i24_e32 v17, 0x64, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v18, vcc_lo
	v_mul_i32_i24_e32 v16, 10, v21
	v_add_co_u32 v12, vcc_lo, v12, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v17, vcc_lo
	v_add_co_u32 v12, vcc_lo, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v22, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	global_load_b64 v[12:13], v[10:11], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v27, 31, v13
	v_add_co_u32 v16, vcc_lo, v12, v27
	v_add_co_ci_u32_e32 v17, vcc_lo, v13, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v28, v16, v27
	v_xor_b32_e32 v29, v17, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, v28, s3, 0
	v_mul_hi_u32 v22, v28, v15
	v_mad_u64_u32 v[18:19], null, v29, v15, 0
	v_mad_u64_u32 v[20:21], null, v29, s3, 0
	v_mul_hi_u32 v32, 0xf5c28f5c, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v22, v16
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v15, vcc_lo, v15, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, v16, v19, vcc_lo
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v19, vcc_lo, v15, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v16, vcc_lo
	v_mad_u64_u32 v[15:16], null, 0x2710, v19, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x2710, v20, v[16:17]
	v_sub_co_u32 v15, vcc_lo, v28, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v16, vcc_lo, v29, v17, vcc_lo
	v_subrev_co_u32 v17, vcc_lo, 0x2710, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v18, vcc_lo, 0, v16, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x270f, v17
	v_cmp_eq_u32_e64 s0, 0, v16
	v_cndmask_b32_e64 v17, 0, -1, vcc_lo
	v_add_co_u32 v21, vcc_lo, v19, 2
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v20, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x270f, v15
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, -1, v15, s0
	v_cndmask_b32_e32 v17, -1, v17, vcc_lo
	v_add_co_u32 v18, vcc_lo, v19, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v20, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v23, v22 :: v_dual_cndmask_b32 v17, v18, v21
	v_cmp_ne_u32_e32 vcc_lo, 0, v15
	v_mad_u64_u32 v[21:22], null, 0x28f5c28, v29, 0
	v_dual_cndmask_b32 v15, v20, v16 :: v_dual_cndmask_b32 v16, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v15, v15, v27
	v_xor_b32_e32 v16, v16, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v16, vcc_lo, v16, v27
	v_sub_co_ci_u32_e32 v17, vcc_lo, v15, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v30, 31, v17
	v_add_co_u32 v18, vcc_lo, v16, v30
	v_add_co_ci_u32_e32 v19, vcc_lo, v17, v30, vcc_lo
	v_mad_u64_u32 v[15:16], null, 0xf5c28f5c, v29, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v31, v18, v30
	v_xor_b32_e32 v33, v19, v30
	v_mad_u64_u32 v[17:18], null, 0x28f5c28, v28, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[19:20], null, v31, s2, 0
	v_mul_hi_u32 v34, v31, v14
	v_mad_u64_u32 v[23:24], null, v33, v14, 0
	v_mad_u64_u32 v[25:26], null, v33, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, v34, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v17, vcc_lo, v32, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
	v_add_co_u32 v19, vcc_lo, v19, v23
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v23, vcc_lo, v20, v24, vcc_lo
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v26, vcc_lo
	v_add_co_u32 v15, vcc_lo, v17, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, v18, v16, vcc_lo
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v22, vcc_lo
	v_mad_u64_u32 v[17:18], null, v28, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v15, v21
	v_add_co_ci_u32_e32 v32, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v21, s0, v23, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[15:16], null, 0x64, v26, 0
	v_add_co_ci_u32_e64 v23, s0, 0, v24, s0
	v_mul_hi_u32 v34, v28, v14
	v_mad_u64_u32 v[19:20], null, 0x64, v32, v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_co_u32 v20, vcc_lo, v28, v15
	v_mad_u64_u32 v[15:16], null, v21, 10, 0
	v_sub_co_ci_u32_e32 v19, vcc_lo, v29, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v22, vcc_lo, 0x64, v20
	v_subrev_co_ci_u32_e32 v21, vcc_lo, 0, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v22
	v_cmp_eq_u32_e64 s0, 0, v19
	v_cndmask_b32_e64 v22, 0, -1, vcc_lo
	v_add_co_u32 v24, vcc_lo, v26, 2
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v32, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v20
	v_cndmask_b32_e64 v20, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_cndmask_b32_e32 v21, -1, v22, vcc_lo
	v_add_co_u32 v22, vcc_lo, v26, 1
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v21
	v_cndmask_b32_e64 v21, -1, v20, s0
	v_mad_u64_u32 v[19:20], null, v29, s2, 0
	v_dual_cndmask_b32 v25, v35, v25 :: v_dual_cndmask_b32 v24, v22, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v21
	v_mad_u64_u32 v[21:22], null, v29, v14, 0
	v_dual_cndmask_b32 v25, v32, v25 :: v_dual_cndmask_b32 v24, v26, v24
	v_add_co_u32 v26, vcc_lo, v34, v17
	v_add_co_ci_u32_e32 v32, vcc_lo, 0, v18, vcc_lo
	v_mad_u64_u32 v[17:18], null, v23, 10, v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v16, v24, v27
	v_xor_b32_e32 v18, v25, v27
	v_sub_co_u32 v25, vcc_lo, v31, v15
	v_sub_co_u32 v15, s0, v16, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_co_ci_u32_e64 v16, s0, v18, v27, s0
	v_sub_co_ci_u32_e32 v17, vcc_lo, v33, v17, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 9, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v31, 31, v16
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_sub_co_u32 v33, vcc_lo, v25, 10
	v_subrev_co_ci_u32_e32 v23, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v15, vcc_lo, v15, v31
	v_add_co_ci_u32_e32 v16, vcc_lo, v16, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s0, 9, v33
	v_xor_b32_e32 v35, v15, v31
	v_cmp_eq_u32_e32 vcc_lo, 0, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_xor_b32_e32 v37, v16, v31
	v_add_nc_u32_e32 v34, -10, v33
	v_cndmask_b32_e64 v24, 0, -1, s0
	v_mad_u64_u32 v[15:16], null, v35, s2, 0
	v_mul_hi_u32 v38, v35, v14
	v_cndmask_b32_e32 v36, -1, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v23
	v_mad_u64_u32 v[17:18], null, v37, v14, 0
	v_cndmask_b32_e32 v39, -1, v24, vcc_lo
	v_add_co_u32 v14, vcc_lo, v38, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v39
	v_mad_u64_u32 v[23:24], null, v37, s2, 0
	v_cndmask_b32_e32 v33, v33, v34, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v17
	v_add_co_ci_u32_e32 v14, vcc_lo, v15, v18, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v24, vcc_lo
	v_add_co_u32 v16, vcc_lo, v26, v21
	v_add_co_ci_u32_e32 v16, vcc_lo, v32, v22, vcc_lo
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v17, s0, v14, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v19, vcc_lo, v16, v19
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v18, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v36
	v_add_co_ci_u32_e64 v21, s0, 0, v15, s0
	v_mad_u64_u32 v[14:15], null, v17, 10, 0
	v_mad_u64_u32 v[16:17], null, v19, 10, 0
	v_cndmask_b32_e32 v18, v25, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v14, vcc_lo, v35, v14
	v_xor_b32_e32 v23, v18, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[18:19], null, v21, 10, v[15:16]
	v_sub_co_u32 v15, s0, v28, v16
	v_cmp_lt_u32_e64 s1, 9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v16, vcc_lo, v37, v18, vcc_lo
	v_mad_u64_u32 v[19:20], null, v22, 10, v[17:18]
	v_sub_co_u32 v17, vcc_lo, v14, 10
	v_subrev_co_ci_u32_e32 v20, vcc_lo, 0, v16, vcc_lo
	v_cndmask_b32_e64 v18, 0, -1, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e32 vcc_lo, 9, v17
	v_cndmask_b32_e64 v21, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v16
	v_cndmask_b32_e32 v18, -1, v18, vcc_lo
	v_sub_co_ci_u32_e64 v19, vcc_lo, v29, v19, s0
	v_cmp_lt_u32_e64 s0, 9, v15
	v_sub_co_u32 v22, vcc_lo, v15, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v28, vcc_lo, 0, v19, vcc_lo
	v_cndmask_b32_e64 v24, 0, -1, s0
	v_sub_co_u32 v25, s0, v17, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v26, s0, 0, v20, s0
	v_cmp_eq_u32_e64 s0, 0, v20
	v_cmp_lt_u32_e32 vcc_lo, 9, v22
	v_cmp_eq_u32_e64 s1, 0, v28
	v_cndmask_b32_e64 v21, -1, v21, s0
	v_cndmask_b32_e64 v29, 0, -1, vcc_lo
	v_cmp_ne_u32_e64 s0, 0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v21
	v_cndmask_b32_e64 v18, -1, v29, s1
	v_sub_co_u32 v21, s1, v22, 10
	v_cndmask_b32_e32 v20, v20, v26, vcc_lo
	v_subrev_co_ci_u32_e64 v26, s1, 0, v28, s1
	v_cmp_eq_u32_e64 s1, 0, v19
	v_cndmask_b32_e32 v17, v17, v25, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v16, v16, v20, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, -1, v24, s1
	v_cndmask_b32_e64 v14, v14, v17, s0
	v_dual_cndmask_b32 v20, v28, v26 :: v_dual_cndmask_b32 v17, v22, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v31
	v_cmp_ne_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_4)
	v_xor_b32_e32 v14, v14, v31
	v_sub_nc_u32_e32 v18, v23, v30
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	v_cndmask_b32_e32 v19, v19, v20, vcc_lo
	v_sub_co_u32 v14, vcc_lo, v14, v31
	v_sub_co_ci_u32_e32 v16, vcc_lo, v16, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v15, v27
	v_xor_b32_e32 v17, v19, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, v18, v14
	v_sub_co_u32 v15, vcc_lo, v15, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v17, vcc_lo, v17, v27, vcc_lo
	v_mul_hi_i32_i24_e32 v20, 10, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v18, v15, v18
	v_sub_co_u32 v12, vcc_lo, v12, v15
	v_sub_co_ci_u32_e32 v13, vcc_lo, v13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_i32_i24_e32 v17, 0x64, v18
	v_add_co_u32 v12, vcc_lo, v12, v14
	v_mul_hi_i32_i24_e32 v15, 0x64, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v16, vcc_lo
	v_mul_i32_i24_e32 v14, 10, v19
	v_add_co_u32 v12, vcc_lo, v12, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v15, vcc_lo
	v_add_co_u32 v12, vcc_lo, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v20, vcc_lo
	global_store_b64 v[10:11], v[12:13], off
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v7, 0xfa0a1f00, v6
	v_cmpx_ne_u32_e32 0, v7
	s_cbranch_execz .LBB0_16
; %bb.13:                               ; %.lr.ph.i100.preheader
	v_mul_hi_i32 v6, 0x66666667, v7
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v10, 31, v6
	v_ashrrev_i32_e32 v6, 2, v6
	v_add_nc_u32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, 10
	v_sub_nc_u32_e32 v6, v7, v6
.LBB0_14:                               ; %.lr.ph.i100
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v10, 0x66666667, v7
	s_lshl_b32 s3, s2, 1
	s_cmp_lg_u32 s2, 0
	v_add_nc_u32_e32 v7, 9, v7
	s_cselect_b32 s2, s3, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_u32_e32 vcc_lo, 19, v7
	v_lshrrev_b32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v10, 2, v10
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v11
	v_mul_hi_i32 v11, 0x66666667, v10
	v_mov_b32_e32 v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v13, 31, v11
	v_ashrrev_i32_e32 v11, 2, v11
	v_add_nc_u32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v11, 10
	v_sub_nc_u32_e32 v11, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, s2, v11
	v_lshl_add_u32 v6, v11, 1, v6
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_14
; %bb.15:                               ; %_Z8BinToDeci.exit.loopexit
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_16:                               ; %Flow178
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v7, v[8:9], off
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	global_store_b8 v[0:1], v6, off
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v8, 0xfa0a1f00, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB0_20
; %bb.17:                               ; %.lr.ph.i101.preheader
	v_mul_hi_i32 v0, 0x66666667, v8
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v0, 2, v0
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, 10
	v_sub_nc_u32_e32 v7, v8, v0
.LBB0_18:                               ; %.lr.ph.i101
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v0, 0x66666667, v8
	s_lshl_b32 s3, s2, 1
	s_cmp_lg_u32 s2, 0
	s_cselect_b32 s2, s3, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v0, 2, v0
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v1, 0x66666667, v0
	v_lshrrev_b32_e32 v6, 31, v1
	v_ashrrev_i32_e32 v1, 2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v1, v6
	v_add_nc_u32_e32 v6, 9, v8
	v_mov_b32_e32 v8, v0
	v_mul_lo_u32 v1, v1, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e32 vcc_lo, 19, v6
	s_or_b32 s1, vcc_lo, s1
	v_sub_nc_u32_e32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s2, v1
	v_lshl_add_u32 v7, v1, 1, v7
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_18
; %bb.19:                               ; %_Z8BinToDeci.exit107.loopexit
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_20:                               ; %Flow177
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, 0xfa0a1f00, v12
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	global_store_b8 v[2:3], v7, off
	v_cmpx_ne_u32_e32 0, v1
	s_cbranch_execz .LBB0_24
; %bb.21:                               ; %.lr.ph.i108.preheader
	v_mul_hi_i32 v0, 0x66666667, v1
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 31, v0
	v_ashrrev_i32_e32 v0, 2, v0
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, 10
	v_sub_nc_u32_e32 v0, v1, v0
.LBB0_22:                               ; %.lr.ph.i108
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v2, 0x66666667, v1
	s_lshl_b32 s3, s2, 1
	s_cmp_lg_u32 s2, 0
	v_add_nc_u32_e32 v1, 9, v1
	s_cselect_b32 s2, s3, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_u32_e32 vcc_lo, 19, v1
	v_lshrrev_b32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v2, 2, v2
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_hi_i32 v3, 0x66666667, v2
	v_mov_b32_e32 v1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 31, v3
	v_ashrrev_i32_e32 v3, 2, v3
	v_add_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, 10
	v_sub_nc_u32_e32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s2, v3
	v_lshl_add_u32 v0, v3, 1, v0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_22
; %bb.23:                               ; %_Z8BinToDeci.exit114.loopexit
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_24:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	global_store_b8 v[4:5], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13PictureKernelP5pixelS0_PlS1_S1_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 41
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13PictureKernelP5pixelS0_PlS1_S1_ii, .Lfunc_end0-_Z13PictureKernelP5pixelS0_PlS1_S1_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6600
; NumSgprs: 18
; NumVgprs: 41
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 41
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13PictureKernelP5pixelS0_PlS1_S1_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13PictureKernelP5pixelS0_PlS1_S1_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     41
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
