//Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#define N 16
#define BLOCK_SIZE 16
#define NUM_BLOCKS N/BLOCK_SIZE

#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(int) * (ARRAY_SIZE))

__constant__ int opNum = 1;
__constant__ int gpu_array1_c[ARRAY_SIZE_IN_BYTES];
__constant__ int gpu_array2_c[ARRAY_SIZE_IN_BYTES];

////////////////////////OPERATIONS//////////////////////

//SHARED MEMORY
__global__  void operations_shared(int * array1, int * array2, int *array3)
{
	int i = threadIdx.x;

	__shared__ int tmpArray1_s[ARRAY_SIZE];
	__shared__ int tmpArray2_s[ARRAY_SIZE];
	__shared__ int tmpArray3_s[ARRAY_SIZE];

	tmpArray1_s[i] = array1[i];
	tmpArray2_s[i] = array2[i];
	tmpArray3_s[i] = array3[i];

	if (opNum ==1)
	{ tmpArray3_s[i]=tmpArray1_s[i]+tmpArray2_s[i];}
	else if (opNum ==2)
	{ tmpArray3_s[i]=tmpArray1_s[i]-tmpArray2_s[i];}
	else if (opNum ==3)
	{ tmpArray3_s[i]=tmpArray1_s[i]*tmpArray2_s[i];}
	else //if (opNum ==4)
	{ tmpArray3_s[i]=tmpArray1_s[i]%tmpArray2_s[i];}

	__syncthreads();

	array1[i] = tmpArray1_s[i];
	array2[i] = tmpArray2_s[i];
	array3[i] = tmpArray3_s[i];

}

//CONSTANT MEMORY
__global__  void operations_constant(int* array3)
{
	int marker = threadIdx.x+blockDim.x*blockIdx.x;

	if (opNum ==1){ array3[marker]=gpu_array1_c[marker]+gpu_array2_c[marker];}
	else if (opNum ==2){array3[marker]=gpu_array1_c[marker]-gpu_array2_c[marker];}
	else if (opNum ==3){ array3[marker]=gpu_array1_c[marker]*gpu_array2_c[marker];}
	else { array3[marker]=gpu_array1_c[marker]%gpu_array2_c[marker];}

	__syncthreads();


}

//////////////////////////MAIN CPU FUNCTION////////////////////////////
int main(int argc, char** argv)
{

	cudaEvent_t start, stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);

	int isConst = 1;
	
	if (argc >= 2) {
		isConst = atoi(argv[1]);
	}				

	/* Declare statically 3 array sized ARRAY_SIZE*/

	
	int* host_array1;
	int* host_array2;
	int* host_array3;

	host_array1=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array2=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array3=(int*)malloc(ARRAY_SIZE_IN_BYTES);

	/* Declare pointers for GPU based params */
	int *gpu_array1;
	int *gpu_array2;
	int *gpu_array3;

	for(int i= 0; i < ARRAY_SIZE; i++)
	{
		host_array1[i] = i;
		host_array2[i] = 1; 
		host_array3[i] = 0;

		//Check thathost_array1 and array 2 inputs are correct
		//printf("ARRAY1 at %u\nARRAY2 at %u\nARRAY3 at %u\n\n",host_array1[i], host_array2[i],host_array3[i]);
	}


	cudaMalloc((void**)&gpu_array1, ARRAY_SIZE_IN_BYTES);
	cudaMalloc((void**)&gpu_array2, ARRAY_SIZE_IN_BYTES);
	cudaMalloc((void**)&gpu_array3, ARRAY_SIZE_IN_BYTES);

	cudaEventRecord(start);
	/////////////////USE SHARED MEMORY///////////////
	if (isConst==0)
	{

	cudaMemcpy( gpu_array1,host_array1, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
	cudaMemcpy( gpu_array2,host_array2, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
	cudaMemcpy( gpu_array3,host_array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );

	operations_shared<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array1,gpu_array2,gpu_array3);

	cudaEventRecord(stop);
	cudaEventSynchronize(stop);
	float milliseconds = 0;
	cudaEventElapsedTime(&milliseconds, start, stop);
	printf("Time elapsed: %f\n", milliseconds);

	/* Free the arrays on the GPU as now we're done with them */
	cudaMemcpy(host_array1, gpu_array1, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
	cudaMemcpy(host_array2, gpu_array2, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
	cudaMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);


	cudaFree(gpu_array1);
	cudaFree(gpu_array2);
	cudaFree(gpu_array3);
	}
	////////////////////USE CONSTANT MEMORY////////////////////////////////
	else if (isConst==1)
	{
		cudaMemcpyToSymbol( gpu_array1_c,host_array1, ARRAY_SIZE_IN_BYTES);
		cudaMemcpyToSymbol( gpu_array2_c,host_array2, ARRAY_SIZE_IN_BYTES);
		cudaMemcpy( gpu_array3,host_array3,ARRAY_SIZE_IN_BYTES,cudaMemcpyHostToDevice);

		operations_constant<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array3);

		
		cudaEventRecord(stop);
		cudaEventSynchronize(stop);
		float milliseconds = 0;
		cudaEventElapsedTime(&milliseconds, start, stop);
		printf("Time elapsed: %f\n", milliseconds);

		cudaMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);

		
		cudaFree(gpu_array1);
		cudaFree(gpu_array2);
		cudaFree(gpu_array3);
	}	
	for( int k=0; k<ARRAY_SIZE; k++)
	{
		printf("\nINDEX: %i\tVALUE:%i\n",k, host_array3[k]);

	}
	
	
}


	.file	"tmpxft_0027fb7f_00000000-6_assignment.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z17operations_sharedPiS_S_PiS_S_
	.type	_Z41__device_stub__Z17operations_sharedPiS_S_PiS_S_, @function
_Z41__device_stub__Z17operations_sharedPiS_S_PiS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z17operations_sharedPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z41__device_stub__Z17operations_sharedPiS_S_PiS_S_, .-_Z41__device_stub__Z17operations_sharedPiS_S_PiS_S_
	.globl	_Z17operations_sharedPiS_S_
	.type	_Z17operations_sharedPiS_S_, @function
_Z17operations_sharedPiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z17operations_sharedPiS_S_PiS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z17operations_sharedPiS_S_, .-_Z17operations_sharedPiS_S_
	.globl	_Z39__device_stub__Z19operations_constantPiPi
	.type	_Z39__device_stub__Z19operations_constantPiPi, @function
_Z39__device_stub__Z19operations_constantPiPi:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z19operations_constantPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L8:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z39__device_stub__Z19operations_constantPiPi, .-_Z39__device_stub__Z19operations_constantPiPi
	.globl	_Z19operations_constantPi
	.type	_Z19operations_constantPi, @function
_Z19operations_constantPi:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z19operations_constantPiPi
	.cfi_endproc
.LFE2055:
	.size	_Z19operations_constantPi, .-_Z19operations_constantPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Time elapsed: %f\n"
.LC2:
	.string	"\nINDEX: %i\tVALUE:%i\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$1, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rsi, %rbx
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	decl	%ebp
	jle	.L14
	movq	8(%rbx), %rdi
	call	atoi@PLT
	movl	%eax, %r13d
.L14:
	movl	$64, %edi
	call	malloc@PLT
	movl	$64, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$64, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	xorl	%ecx, %ecx
	movq	%rax, %rbx
.L15:
	movl	%ecx, (%r12,%rcx,4)
	movl	$1, 0(%rbp,%rcx,4)
	incq	%rcx
	cmpq	$16, %rcx
	jne	.L15
	xorl	%eax, %eax
	movq	%rbx, %rdi
	movl	$64, %esi
	rep stosl
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$64, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$64, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	testl	%r13d, %r13d
	jne	.L16
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$64, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z41__device_stub__Z17operations_sharedPiS_S_PiS_S_
.L17:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	60(%rsp), %rdi
	movl	$0x00000000, 60(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	60(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movq	%r12, %rdi
	movl	$2, %ecx
	movl	$64, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	jmp	.L27
.L16:
	decl	%r13d
	jne	.L18
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movl	$64, %edx
	movq	%r12, %rsi
	leaq	_ZL12gpu_array1_c(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbp, %rsi
	movl	$64, %edx
	leaq	_ZL12gpu_array2_c(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	40(%rsp), %rdi
	call	_Z39__device_stub__Z19operations_constantPiPi
.L19:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	60(%rsp), %rdi
	movl	$0x00000000, 60(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	60(%rsp), %xmm0
	call	__printf_chk@PLT
.L27:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$64, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
.L18:
	xorl	%ebp, %ebp
	leaq	.LC2(%rip), %r12
.L20:
	movl	(%rbx,%rbp,4), %ecx
	movl	%ebp, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$16, %rbp
	jne	.L20
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z19operations_constantPi"
.LC4:
	.string	"_Z17operations_sharedPiS_S_"
.LC5:
	.string	"opNum"
.LC6:
	.string	"gpu_array1_c"
.LC7:
	.string	"gpu_array2_c"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19operations_constantPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17operations_sharedPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movl	$4, %r9d
	leaq	_ZL5opNum(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$256, %r9d
	leaq	_ZL12gpu_array1_c(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$256, %r9d
	movq	%rdx, %rcx
	leaq	_ZL12gpu_array2_c(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL12gpu_array2_c
	.comm	_ZL12gpu_array2_c,256,32
	.local	_ZL12gpu_array1_c
	.comm	_ZL12gpu_array1_c,256,32
	.local	_ZL5opNum
	.comm	_ZL5opNum,4,4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//Based on the work of Andrew Krepps

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#define N 16
#define BLOCK_SIZE 16
#define NUM_BLOCKS N/BLOCK_SIZE

#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(int) * (ARRAY_SIZE))

__constant__ int opNum = 1;
__constant__ int gpu_array1_c[ARRAY_SIZE_IN_BYTES];
__constant__ int gpu_array2_c[ARRAY_SIZE_IN_BYTES];

////////////////////////OPERATIONS//////////////////////

//SHARED MEMORY
__global__  void operations_shared(int * array1, int * array2, int *array3)
{
	int i = threadIdx.x;

	__shared__ int tmpArray1_s[ARRAY_SIZE];
	__shared__ int tmpArray2_s[ARRAY_SIZE];
	__shared__ int tmpArray3_s[ARRAY_SIZE];

	tmpArray1_s[i] = array1[i];
	tmpArray2_s[i] = array2[i];
	tmpArray3_s[i] = array3[i];

	if (opNum ==1)
	{ tmpArray3_s[i]=tmpArray1_s[i]+tmpArray2_s[i];}
	else if (opNum ==2)
	{ tmpArray3_s[i]=tmpArray1_s[i]-tmpArray2_s[i];}
	else if (opNum ==3)
	{ tmpArray3_s[i]=tmpArray1_s[i]*tmpArray2_s[i];}
	else //if (opNum ==4)
	{ tmpArray3_s[i]=tmpArray1_s[i]%tmpArray2_s[i];}

	__syncthreads();

	array1[i] = tmpArray1_s[i];
	array2[i] = tmpArray2_s[i];
	array3[i] = tmpArray3_s[i];

}

//CONSTANT MEMORY
__global__  void operations_constant(int* array3)
{
	int marker = threadIdx.x+blockDim.x*blockIdx.x;

	if (opNum ==1){ array3[marker]=gpu_array1_c[marker]+gpu_array2_c[marker];}
	else if (opNum ==2){array3[marker]=gpu_array1_c[marker]-gpu_array2_c[marker];}
	else if (opNum ==3){ array3[marker]=gpu_array1_c[marker]*gpu_array2_c[marker];}
	else { array3[marker]=gpu_array1_c[marker]%gpu_array2_c[marker];}

	__syncthreads();


}

//////////////////////////MAIN CPU FUNCTION////////////////////////////
int main(int argc, char** argv)
{

	hipEvent_t start, stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);

	int isConst = 1;
	
	if (argc >= 2) {
		isConst = atoi(argv[1]);
	}				

	/* Declare statically 3 array sized ARRAY_SIZE*/

	
	int* host_array1;
	int* host_array2;
	int* host_array3;

	host_array1=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array2=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array3=(int*)malloc(ARRAY_SIZE_IN_BYTES);

	/* Declare pointers for GPU based params */
	int *gpu_array1;
	int *gpu_array2;
	int *gpu_array3;

	for(int i= 0; i < ARRAY_SIZE; i++)
	{
		host_array1[i] = i;
		host_array2[i] = 1; 
		host_array3[i] = 0;

		//Check thathost_array1 and array 2 inputs are correct
		//printf("ARRAY1 at %u\nARRAY2 at %u\nARRAY3 at %u\n\n",host_array1[i], host_array2[i],host_array3[i]);
	}


	hipMalloc((void**)&gpu_array1, ARRAY_SIZE_IN_BYTES);
	hipMalloc((void**)&gpu_array2, ARRAY_SIZE_IN_BYTES);
	hipMalloc((void**)&gpu_array3, ARRAY_SIZE_IN_BYTES);

	hipEventRecord(start);
	/////////////////USE SHARED MEMORY///////////////
	if (isConst==0)
	{

	hipMemcpy( gpu_array1,host_array1, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
	hipMemcpy( gpu_array2,host_array2, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
	hipMemcpy( gpu_array3,host_array3, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );

	operations_shared<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array1,gpu_array2,gpu_array3);

	hipEventRecord(stop);
	hipEventSynchronize(stop);
	float milliseconds = 0;
	hipEventElapsedTime(&milliseconds, start, stop);
	printf("Time elapsed: %f\n", milliseconds);

	/* Free the arrays on the GPU as now we're done with them */
	hipMemcpy(host_array1, gpu_array1, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
	hipMemcpy(host_array2, gpu_array2, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
	hipMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);


	hipFree(gpu_array1);
	hipFree(gpu_array2);
	hipFree(gpu_array3);
	}
	////////////////////USE CONSTANT MEMORY////////////////////////////////
	else if (isConst==1)
	{
		hipMemcpyToSymbol( HIP_SYMBOL(gpu_array1_c),host_array1, ARRAY_SIZE_IN_BYTES);
		hipMemcpyToSymbol( HIP_SYMBOL(gpu_array2_c),host_array2, ARRAY_SIZE_IN_BYTES);
		hipMemcpy( gpu_array3,host_array3,ARRAY_SIZE_IN_BYTES,hipMemcpyHostToDevice);

		operations_constant<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array3);

		
		hipEventRecord(stop);
		hipEventSynchronize(stop);
		float milliseconds = 0;
		hipEventElapsedTime(&milliseconds, start, stop);
		printf("Time elapsed: %f\n", milliseconds);

		hipMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);

		
		hipFree(gpu_array1);
		hipFree(gpu_array2);
		hipFree(gpu_array3);
	}	
	for( int k=0; k<ARRAY_SIZE; k++)
	{
		printf("\nINDEX: %i\tVALUE:%i\n",k, host_array3[k]);

	}
	
	
}


	.text
	.file	"assignment.hip"
	.globl	_Z32__device_stub__operations_sharedPiS_S_ # -- Begin function _Z32__device_stub__operations_sharedPiS_S_
	.type	_Z32__device_stub__operations_sharedPiS_S_,@function
_Z32__device_stub__operations_sharedPiS_S_: # @_Z32__device_stub__operations_sharedPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17operations_sharedPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__operations_sharedPiS_S_, .Lfunc_end0-_Z32__device_stub__operations_sharedPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__operations_constantPi # -- Begin function _Z34__device_stub__operations_constantPi
	.type	_Z34__device_stub__operations_constantPi,@function
_Z34__device_stub__operations_constantPi: # @_Z34__device_stub__operations_constantPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19operations_constantPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__operations_constantPi, .Lfunc_end1-_Z34__device_stub__operations_constantPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %r14d
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movl	$1, %ebp
	cmpl	$2, %r14d
	jl	.LBB2_2
# %bb.1:
	movq	8(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
.LBB2_2:
	movl	$64, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$64, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$1, %edi
	movl	$64, %esi
	callq	calloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%r15,%rax,4)
	movl	$1, (%r14,%rax,4)
	incq	%rax
	cmpq	$16, %rax
	jne	.LBB2_3
# %bb.4:
	leaq	24(%rsp), %rdi
	movl	$64, %esi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$64, %esi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$64, %esi
	callq	hipMalloc
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%ebp, %ebp
	je	.LBB2_9
# %bb.5:
	cmpl	$1, %ebp
	jne	.LBB2_13
# %bb.6:
	movl	$gpu_array1_c, %edi
	movl	$64, %edx
	movq	%r15, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$gpu_array2_c, %edi
	movl	$64, %edx
	movq	%r14, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movq	(%rsp), %rdi
	movl	$64, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	15(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	(%rsp), %rdi
	callq	_Z34__device_stub__operations_constantPi
.LBB2_8:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	44(%rsp), %r14
	movl	$0, (%r14)
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	jmp	.LBB2_12
.LBB2_9:
	movq	24(%rsp), %rdi
	movl	$64, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$64, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	movl	$64, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	15(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_11
# %bb.10:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdx
	callq	_Z32__device_stub__operations_sharedPiS_S_
.LBB2_11:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	44(%rsp), %r12
	movl	$0, (%r12)
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	24(%rsp), %rsi
	movl	$64, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movl	$64, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.LBB2_12:                               # %.preheader
	movq	(%rsp), %rsi
	movl	$64, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
.LBB2_13:                               # %.preheader
	xorl	%r14d, %r14d
.LBB2_14:                               # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %edx
	movl	$.L.str.1, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$16, %r14
	jne	.LBB2_14
# %bb.15:
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17operations_sharedPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19operations_constantPi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$opNum, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$gpu_array1_c, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$gpu_array2_c, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	opNum,@object                   # @opNum
	.local	opNum
	.comm	opNum,4,4
	.type	gpu_array1_c,@object            # @gpu_array1_c
	.local	gpu_array1_c
	.comm	gpu_array1_c,256,16
	.type	gpu_array2_c,@object            # @gpu_array2_c
	.local	gpu_array2_c
	.comm	gpu_array2_c,256,16
	.type	_Z17operations_sharedPiS_S_,@object # @_Z17operations_sharedPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z17operations_sharedPiS_S_
	.p2align	3, 0x0
_Z17operations_sharedPiS_S_:
	.quad	_Z32__device_stub__operations_sharedPiS_S_
	.size	_Z17operations_sharedPiS_S_, 8

	.type	_Z19operations_constantPi,@object # @_Z19operations_constantPi
	.globl	_Z19operations_constantPi
	.p2align	3, 0x0
_Z19operations_constantPi:
	.quad	_Z34__device_stub__operations_constantPi
	.size	_Z19operations_constantPi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Time elapsed: %f\n"
	.size	.L.str, 18

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\nINDEX: %i\tVALUE:%i\n"
	.size	.L.str.1, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17operations_sharedPiS_S_"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19operations_constantPi"
	.size	.L__unnamed_2, 26

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"opNum"
	.size	.L__unnamed_3, 6

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"gpu_array1_c"
	.size	.L__unnamed_4, 13

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"gpu_array2_c"
	.size	.L__unnamed_5, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__operations_sharedPiS_S_
	.addrsig_sym _Z34__device_stub__operations_constantPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym opNum
	.addrsig_sym gpu_array1_c
	.addrsig_sym gpu_array2_c
	.addrsig_sym _Z17operations_sharedPiS_S_
	.addrsig_sym _Z19operations_constantPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17operations_sharedPiS_S_ ; -- Begin function _Z17operations_sharedPiS_S_
	.globl	_Z17operations_sharedPiS_S_
	.p2align	8
	.type	_Z17operations_sharedPiS_S_,@function
_Z17operations_sharedPiS_S_:            ; @_Z17operations_sharedPiS_S_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v5, 2, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v7, v5, s[4:5]
	global_load_b32 v8, v5, s[6:7]
	v_add_co_u32 v1, s2, s4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, null, s5, 0, s2
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, opNum@rel32@lo+4
	s_addc_u32 s5, s5, opNum@rel32@hi+12
	v_add_co_u32 v3, s2, s6, v5
	s_load_b32 s3, s[4:5], 0x0
	v_add_co_ci_u32_e64 v4, null, s7, 0, s2
	v_add_nc_u32_e32 v6, 64, v5
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 2
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v5, v7, v8 offset1:16
	s_cbranch_scc1 .LBB0_4
; %bb.1:                                ; %NodeBlock
	s_cmp_gt_i32 s3, 2
	s_cbranch_scc0 .LBB0_5
; %bb.2:                                ; %LeafBlock40
	s_cmp_eq_u32 s3, 3
	s_cbranch_scc0 .LBB0_6
; %bb.3:
	v_mul_lo_u32 v9, v8, v7
	s_branch .LBB0_7
.LBB0_4:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr9
	s_branch .LBB0_11
.LBB0_5:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr9
	s_branch .LBB0_8
.LBB0_6:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr9
.LBB0_7:                                ; %Flow45
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow44
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_10
; %bb.9:
	v_sub_nc_u32_e32 v9, v7, v8
.LBB0_10:                               ; %Flow46
	s_mov_b32 s4, 0
.LBB0_11:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_mov_b32 s4, 0
	s_cbranch_vccz .LBB0_13
; %bb.12:                               ; %LeafBlock
	s_cmp_lg_u32 s3, 1
	s_mov_b32 s4, -1
	s_cselect_b32 s2, -1, 0
                                        ; implicit-def: $vgpr9
.LBB0_13:                               ; %Flow47
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_15
; %bb.14:
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v12, 31, v7
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v8, v9
	v_add_nc_u32_e32 v13, v7, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v10, v9
	v_xor_b32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v10, v9
	v_sub_nc_u32_e32 v11, 0, v9
	v_rcp_iflag_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v10, v10
	v_mul_lo_u32 v11, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v10, v11
	v_add_nc_u32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v10, v13, v10
	v_mul_lo_u32 v10, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v13, v10
	v_sub_nc_u32_e32 v11, v10, v9
	v_cmp_ge_u32_e32 vcc_lo, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_sub_nc_u32_e32 v11, v10, v9
	v_cmp_ge_u32_e32 vcc_lo, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, v10, v11, vcc_lo
	v_xor_b32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v9, v12
.LBB0_15:                               ; %Flow48
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_17
; %bb.16:
	v_add_nc_u32_e32 v9, v8, v7
.LBB0_17:
	v_lshlrev_b32_e32 v0, 2, v0
	ds_store_b32 v0, v9 offset:128
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v5, v5
	ds_load_b32 v6, v6
	ds_load_b32 v7, v0 offset:128
	s_waitcnt lgkmcnt(2)
	global_store_b32 v[1:2], v5, off
	s_waitcnt lgkmcnt(1)
	global_store_b32 v[3:4], v6, off
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v7, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17operations_sharedPiS_S_
		.amdhsa_group_segment_fixed_size 192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17operations_sharedPiS_S_, .Lfunc_end0-_Z17operations_sharedPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 532
; NumSgprs: 10
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 192 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19operations_constantPi ; -- Begin function _Z19operations_constantPi
	.globl	_Z19operations_constantPi
	.p2align	8
	.type	_Z19operations_constantPi,@function
_Z19operations_constantPi:              ; @_Z19operations_constantPi
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gpu_array1_c@rel32@lo+4
	s_addc_u32 s3, s3, gpu_array1_c@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gpu_array2_c@rel32@lo+4
	s_addc_u32 s5, s5, gpu_array2_c@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, opNum@rel32@lo+4
	s_addc_u32 s3, s3, opNum@rel32@hi+12
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	s_load_b32 s3, s[2:3], 0x0
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s3, 2
	s_cbranch_scc1 .LBB1_4
; %bb.1:                                ; %NodeBlock
	s_cmp_gt_i32 s3, 2
	s_cbranch_scc0 .LBB1_5
; %bb.2:                                ; %LeafBlock17
	s_cmp_eq_u32 s3, 3
	s_cbranch_scc0 .LBB1_6
; %bb.3:
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v3, v2
	s_mov_b32 s4, 0
	s_branch .LBB1_7
.LBB1_4:
	s_mov_b32 s5, -1
	s_mov_b32 s4, 0
                                        ; implicit-def: $vgpr4
	s_branch .LBB1_11
.LBB1_5:
	s_mov_b32 s5, -1
	s_mov_b32 s4, 0
                                        ; implicit-def: $vgpr4
	s_branch .LBB1_8
.LBB1_6:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr4
.LBB1_7:                                ; %Flow22
	s_mov_b32 s5, 0
.LBB1_8:                                ; %Flow21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB1_10
; %bb.9:
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v4, v2, v3
.LBB1_10:                               ; %Flow23
	s_mov_b32 s5, 0
.LBB1_11:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB1_13
; %bb.12:                               ; %LeafBlock
	s_cmp_lg_u32 s3, 1
	s_mov_b32 s2, -1
	s_cselect_b32 s4, -1, 0
                                        ; implicit-def: $vgpr4
.LBB1_13:                               ; %Flow24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_15
; %bb.14:
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v7, 31, v2
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v3, v4
	v_add_nc_u32_e32 v8, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v5, v4
	v_xor_b32_e32 v8, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, v4
	v_sub_nc_u32_e32 v6, 0, v4
	v_rcp_iflag_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v5, v5
	v_mul_lo_u32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v6
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v8, v5
	v_mul_lo_u32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v5
	v_sub_nc_u32_e32 v6, v5, v4
	v_cmp_ge_u32_e32 vcc_lo, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_sub_nc_u32_e32 v6, v5, v4
	v_cmp_ge_u32_e32 vcc_lo, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v5, v6, vcc_lo
	v_xor_b32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v7
.LBB1_15:                               ; %Flow25
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_17
; %bb.16:
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v3, v2
.LBB1_17:
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
	s_waitcnt vmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19operations_constantPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19operations_constantPi, .Lfunc_end1-_Z19operations_constantPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 548
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	opNum                   ; @opNum
	.type	opNum,@object
	.data
	.globl	opNum
	.p2align	2, 0x0
opNum:
	.long	1                               ; 0x1
	.size	opNum, 4

	.protected	gpu_array1_c            ; @gpu_array1_c
	.type	gpu_array1_c,@object
	.section	.bss,"aw",@nobits
	.globl	gpu_array1_c
	.p2align	4, 0x0
gpu_array1_c:
	.zero	256
	.size	gpu_array1_c, 256

	.protected	gpu_array2_c            ; @gpu_array2_c
	.type	gpu_array2_c,@object
	.globl	gpu_array2_c
	.p2align	4, 0x0
gpu_array2_c:
	.zero	256
	.size	gpu_array2_c, 256

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym opNum
	.addrsig_sym gpu_array1_c
	.addrsig_sym gpu_array2_c
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17operations_sharedPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z17operations_sharedPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19operations_constantPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19operations_constantPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
