/* objective
 * 	C = A*B  // A[m][k], B[k][n], C[m][n]
 * compile: nvcc --gpu-architecture=compute_60 --gpu-code=sm_60 -O3 matmul_double.cu -o matmul_double
  Using nvprof for this lab

            nvprof -- query-metrics
            nvprof dram_read_transactions ./test 1024 1024  128
            nvprof ./test 1024 1024 128 

                second line of result shows time for GPU kernel

                GFlop   ( 2MNK * 10^-9 ) / time (second)

 */

#include <iostream>
#include <cstdlib>

#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>

#define TILE_WIDTH 16

#define EC(ans) { chkerr((ans), __FILE__, __LINE__); }
inline void chkerr(cudaError_t code, const char *file, int line)
{
    if (code != cudaSuccess)
    {
        std::cerr << "ERROR!!!:" << cudaGetErrorString(code) << " File: " << file << " Line: " << line << '\n';
        exit(-1);
    }
}

void init (double *A, double *B, int M , int N, int K)
{
    for (int i = 0; i < M; ++i)
    {
        for (int j = 0; j < K; ++j)
        {
            A[i * K + j] = i * K + j;
        }
    }

    for (int i = 0; i < K; ++i)
    {
        for (int j = 0; j < N; ++j)
        {
            B[i * N + j] = i * N + j + 1;
        }
    }

}


void matmul_double_host(double* A, double* B, double* C, int M, int N, int K)
{
    for (int i = 0; i < M; ++i)
    {
        for (int j = 0; j < N; ++j)
        {
            double tmp = 0;

            for (int k = 0; k < K; ++k)
            {
                tmp += A[i * K + k] * B[k * N + j];
            }

            C[i * N + j] = tmp;
        }
    }
}

__global__ void matmul_double(double* A, double* B , double* C, int M, int N, int K)
{
    /// complete code

    int bx = blockIdx.x ;
    int by = blockIdx.y ;

    int tx = threadIdx.x ;
    int ty = threadIdx.y ;

    int row = by * TILE_WIDTH + ty ;
    int col = bx * TILE_WIDTH + tx ;

    __shared__ double SA[TILE_WIDTH][TILE_WIDTH] ;
    __shared__ double SB[TILE_WIDTH][TILE_WIDTH] ;

    double Csub = 0;

    for (int i = 0; i < (K-1)/TILE_WIDTH +1 ; ++i)
    {
        /* code */
        //SA[ty][tx] = A[row*n + i * TILE_WIDTH + tx] ;
        //SB[ty][tx] = B[(i * TILE_WIDTH + ty )*n + col   ] ;

        if ( (row < M) && (i * TILE_WIDTH + tx < K ) ){
            SA[ty][tx] = A[row*K + i * TILE_WIDTH + tx] ;
        }
        else{
            SA[ty][tx] = 0;
        }

        if ( (col < N ) && ( i * TILE_WIDTH + ty < K) ){
            SB[ty][tx] = B[(i*TILE_WIDTH + ty)*N + col] ;
        }
        else{
            SB[ty][tx] = 0;
        }



        __syncthreads() ;

        for (int k = 0; k < TILE_WIDTH; ++k){   
            Csub += SA[ty][k] * SB[k][tx] ;
        }

        __syncthreads() ;
        

    }

    //C[row*n + col] = Csub ;

    if ( (row < M ) && ( col < N )){
        C[ row * N + col] = Csub ;
    }



}

void validate (double *host, double *gpu, int M, int N)
{
    for (int i = 0; i < M; ++i)
    {
        for (int j = 0; j < N; ++j)
        {
            if(std::abs(host[i * N + j] - gpu[i * N + j]) > 1e-3)
            {
                std::cerr << "possible error at position " << i << ',' << j << " host: " << host[i * N + j] << " device " << gpu[i * N + j] << '\n';
            }

        }
    }
}


int main(int argc, char *argv[])
{
    if(argc < 3)
    {
        std::cerr << "Usage: ./matmul_double M N K\n";
        exit(-1);
    }

    int M = std::atoi(argv[1]);
    int N = std::atoi(argv[2]);
    int K = std::atoi(argv[3]);

    /* Host alloc */
    double *hA = (double*) malloc (M * K * sizeof(double));
    double *hB = (double*) malloc (K * N * sizeof(double));
    double *hC = (double*) malloc (M * N * sizeof(double));
    double *dtohC = (double*) malloc (M * N * sizeof(double));

    /* Device alloc */
    /// complete code

    double *dA;
    double *dB;
    double *dC;

    cudaMalloc((void**) &dA, M*K * sizeof(double)) ;
    cudaMalloc((void**) &dB, K*N * sizeof(double)) ;
    cudaMalloc((void**) &dC, M*N * sizeof(double)) ;


    /* Initialize host memory*/
    init(hA, hB, M, N, K);

    /* host compute */
    matmul_double_host(hA, hB, hC, M, N, K);


    /* Copy from host to device */
    /// complete code
    cudaMemcpy(dA,hA ,M*K * sizeof(double) , cudaMemcpyHostToDevice ) ;
    cudaMemcpy(dB,hB ,K*N * sizeof(double) , cudaMemcpyHostToDevice ) ;

    
    /* call gpu kernel */
    /// complete code

    //Initialize the grid and block dimensions here
    //dim3 dimGrid( ceil())
    dim3 dimGrid( (N - 1) / TILE_WIDTH + 1 , (M - 1)/ TILE_WIDTH + 1 , 1) ;
    //dim3 dimGrid( (M - 1) / TILE_WIDTH + 1 , (N - 1)/ TILE_WIDTH + 1 , 1) ;
    dim3 dimBlock(TILE_WIDTH , TILE_WIDTH , 1) ;


    matmul_double<<<dimGrid, dimBlock>>>(dA, dB , dC , M , N , K) ;


    /* Copy from device to host (dC -> dtohC) */
    /// complete code

    cudaMemcpy(dtohC, dC , sizeof(double)*M*N , cudaMemcpyDeviceToHost) ;

    /* host vs device validation */
    validate(hC, dtohC, M, N);


    /* be clean */
    free(hA);
    free(hB);
    free(hC);
    free(dtohC);

    /// add code to free gpu memory

    cudaFree(dA) ;
    cudaFree(dB) ;
    cudaFree(dC) ;


    return 0;
}





	.file	"tmpxft_002dc5cb_00000000-6_matmul_double.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3642:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3642:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4initPdS_iii
	.type	_Z4initPdS_iii, @function
_Z4initPdS_iii:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edx, %r10d
	xorl	%r9d, %r9d
	xorl	%edx, %edx
.L3:
	cmpl	%r10d, %r9d
	jge	.L5
	movslq	%edx, %rax
	leaq	(%rdi,%rax,8), %r11
	xorl	%eax, %eax
.L6:
	cmpl	%eax, %r8d
	jle	.L13
	leal	(%rdx,%rax), %ebx
	cvtsi2sdl	%ebx, %xmm0
	movsd	%xmm0, (%r11,%rax,8)
	incq	%rax
	jmp	.L6
.L13:
	incl	%r9d
	addl	%r8d, %edx
	jmp	.L3
.L5:
	xorl	%edx, %edx
	xorl	%edi, %edi
.L7:
	cmpl	%r8d, %edi
	jge	.L2
	movslq	%edx, %rax
	leal	1(%rdx), %r9d
	leaq	(%rsi,%rax,8), %r10
	xorl	%eax, %eax
.L10:
	cmpl	%eax, %ecx
	jle	.L14
	leal	(%r9,%rax), %r11d
	cvtsi2sdl	%r11d, %xmm0
	movsd	%xmm0, (%r10,%rax,8)
	incq	%rax
	jmp	.L10
.L14:
	incl	%edi
	addl	%ecx, %edx
	jmp	.L7
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z4initPdS_iii, .-_Z4initPdS_iii
	.globl	_Z18matmul_double_hostPdS_S_iii
	.type	_Z18matmul_double_hostPdS_S_iii, @function
_Z18matmul_double_hostPdS_S_iii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r10d, %r10d
	xorl	%r11d, %r11d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	xorl	%ecx, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	movq	%rdx, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%r8d, %rbx
	salq	$3, %rbx
.L16:
	cmpl	%r12d, %r11d
	jge	.L15
	movslq	%r10d, %rax
	leaq	(%rsi,%rax,8), %r15
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,8), %r14
	xorl	%eax, %eax
.L21:
	cmpl	%eax, %r8d
	jle	.L18
	leaq	0(%rbp,%rax,8), %r13
	xorl	%edx, %edx
	xorps	%xmm0, %xmm0
.L19:
	cmpl	%edx, %r9d
	jle	.L23
	movsd	(%r14,%rdx,8), %xmm1
	mulsd	0(%r13), %xmm1
	incq	%rdx
	addq	%rbx, %r13
	addsd	%xmm1, %xmm0
	jmp	.L19
.L23:
	movsd	%xmm0, (%r15,%rax,8)
	incq	%rax
	jmp	.L21
.L18:
	incl	%r11d
	addl	%r8d, %r10d
	addl	%r9d, %ecx
	jmp	.L16
.L15:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z18matmul_double_hostPdS_S_iii, .-_Z18matmul_double_hostPdS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"possible error at position "
.LC4:
	.string	" host: "
.LC5:
	.string	" device "
	.text
	.globl	_Z8validatePdS_ii
	.type	_Z8validatePdS_ii, @function
_Z8validatePdS_ii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %r15d
	xorl	%ecx, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
.L25:
	cmpl	%edx, %r12d
	jge	.L24
	movslq	%ecx, %rbx
	xorl	%ebp, %ebp
	salq	$3, %rbx
.L30:
	cmpl	%r15d, %ebp
	jge	.L33
	movsd	0(%r13,%rbx), %xmm0
	subsd	(%r14,%rbx), %xmm0
	andps	.LC1(%rip), %xmm0
	comisd	.LC2(%rip), %xmm0
	jbe	.L26
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	movl	%edx, 12(%rsp)
	movl	%ecx, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movl	$44, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	0(%r13,%rbx), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	(%r14,%rbx), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$10, %esi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
	movl	12(%rsp), %edx
	movl	8(%rsp), %ecx
.L26:
	incl	%ebp
	addq	$8, %rbx
	jmp	.L30
.L33:
	incl	%r12d
	addl	%r15d, %ecx
	jmp	.L25
.L24:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z8validatePdS_ii, .-_Z8validatePdS_ii
	.globl	_Z40__device_stub__Z13matmul_doublePdS_S_iiiPdS_S_iii
	.type	_Z40__device_stub__Z13matmul_doublePdS_S_iiiPdS_S_iii, @function
_Z40__device_stub__Z13matmul_doublePdS_S_iiiPdS_S_iii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z13matmul_doublePdS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L34:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z40__device_stub__Z13matmul_doublePdS_S_iiiPdS_S_iii, .-_Z40__device_stub__Z13matmul_doublePdS_S_iiiPdS_S_iii
	.globl	_Z13matmul_doublePdS_S_iii
	.type	_Z13matmul_doublePdS_S_iii, @function
_Z13matmul_doublePdS_S_iii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z13matmul_doublePdS_S_iiiPdS_S_iii
	.cfi_endproc
.LFE3665:
	.size	_Z13matmul_doublePdS_S_iii, .-_Z13matmul_doublePdS_S_iii
	.section	.rodata.str1.1
.LC6:
	.string	"Usage: ./matmul_double M N K\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	jg	.L40
	leaq	_ZSt4cerr(%rip), %rdi
	leaq	.LC6(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	orl	$-1, %edi
	call	exit@PLT
.L40:
	movq	8(%rsi), %rdi
	movq	%rsi, %r12
	call	atoi@PLT
	movq	16(%r12), %rdi
	movl	%eax, %ebx
	call	atoi@PLT
	movq	24(%r12), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movl	%eax, %r12d
	movl	%ebx, %eax
	imull	%r12d, %eax
	cltq
	salq	$3, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	%rax, %r14
	movl	%ebp, %eax
	imull	%r12d, %eax
	cltq
	salq	$3, %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	%rax, %r13
	movl	%ebx, %eax
	imull	%ebp, %eax
	cltq
	salq	$3, %rax
	movq	%rax, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movq	16(%rsp), %rdi
	movq	%rax, %r15
	call	malloc@PLT
	movq	(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	movl	%r12d, %r8d
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movq	%r14, %rdi
	call	_Z4initPdS_iii
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	movl	%ebx, %ecx
	movq	%r15, %rdx
	movq	%r14, %rdi
	call	_Z18matmul_double_hostPdS_S_iii
	movq	(%rsp), %rdx
	movq	40(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	-1(%rbp), %eax
	movl	$16, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movl	$1, %esi
	idivl	%ecx
	incl	%eax
	movl	%eax, 64(%rsp)
	leal	-1(%rbx), %eax
	cltd
	idivl	%ecx
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 68(%rsp)
	movq	64(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	movq	40(%rsp), %rdi
	movl	%ebx, %ecx
	call	_Z40__device_stub__Z13matmul_doublePdS_S_iiiPdS_S_iii
.L41:
	movslq	%ebp, %rax
	movslq	%ebx, %rdx
	movq	56(%rsp), %rsi
	movq	24(%rsp), %rdi
	imulq	%rax, %rdx
	movl	$2, %ecx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movq	%r15, %rdi
	call	_Z8validatePdS_ii
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r15, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z13matmul_doublePdS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3667:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13matmul_doublePdS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3667:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	-1
	.long	2147483647
	.long	0
	.long	0
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	-755914244
	.long	1062232653
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* objective
 * 	C = A*B  // A[m][k], B[k][n], C[m][n]
 * compile: nvcc --gpu-architecture=compute_60 --gpu-code=sm_60 -O3 matmul_double.cu -o matmul_double
  Using nvprof for this lab

            nvprof -- query-metrics
            nvprof dram_read_transactions ./test 1024 1024  128
            nvprof ./test 1024 1024 128 

                second line of result shows time for GPU kernel

                GFlop   ( 2MNK * 10^-9 ) / time (second)

 */

#include <iostream>
#include <cstdlib>

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>

#define TILE_WIDTH 16

#define EC(ans) { chkerr((ans), __FILE__, __LINE__); }
inline void chkerr(hipError_t code, const char *file, int line)
{
    if (code != hipSuccess)
    {
        std::cerr << "ERROR!!!:" << hipGetErrorString(code) << " File: " << file << " Line: " << line << '\n';
        exit(-1);
    }
}

void init (double *A, double *B, int M , int N, int K)
{
    for (int i = 0; i < M; ++i)
    {
        for (int j = 0; j < K; ++j)
        {
            A[i * K + j] = i * K + j;
        }
    }

    for (int i = 0; i < K; ++i)
    {
        for (int j = 0; j < N; ++j)
        {
            B[i * N + j] = i * N + j + 1;
        }
    }

}


void matmul_double_host(double* A, double* B, double* C, int M, int N, int K)
{
    for (int i = 0; i < M; ++i)
    {
        for (int j = 0; j < N; ++j)
        {
            double tmp = 0;

            for (int k = 0; k < K; ++k)
            {
                tmp += A[i * K + k] * B[k * N + j];
            }

            C[i * N + j] = tmp;
        }
    }
}

__global__ void matmul_double(double* A, double* B , double* C, int M, int N, int K)
{
    /// complete code

    int bx = blockIdx.x ;
    int by = blockIdx.y ;

    int tx = threadIdx.x ;
    int ty = threadIdx.y ;

    int row = by * TILE_WIDTH + ty ;
    int col = bx * TILE_WIDTH + tx ;

    __shared__ double SA[TILE_WIDTH][TILE_WIDTH] ;
    __shared__ double SB[TILE_WIDTH][TILE_WIDTH] ;

    double Csub = 0;

    for (int i = 0; i < (K-1)/TILE_WIDTH +1 ; ++i)
    {
        /* code */
        //SA[ty][tx] = A[row*n + i * TILE_WIDTH + tx] ;
        //SB[ty][tx] = B[(i * TILE_WIDTH + ty )*n + col   ] ;

        if ( (row < M) && (i * TILE_WIDTH + tx < K ) ){
            SA[ty][tx] = A[row*K + i * TILE_WIDTH + tx] ;
        }
        else{
            SA[ty][tx] = 0;
        }

        if ( (col < N ) && ( i * TILE_WIDTH + ty < K) ){
            SB[ty][tx] = B[(i*TILE_WIDTH + ty)*N + col] ;
        }
        else{
            SB[ty][tx] = 0;
        }



        __syncthreads() ;

        for (int k = 0; k < TILE_WIDTH; ++k){   
            Csub += SA[ty][k] * SB[k][tx] ;
        }

        __syncthreads() ;
        

    }

    //C[row*n + col] = Csub ;

    if ( (row < M ) && ( col < N )){
        C[ row * N + col] = Csub ;
    }



}

void validate (double *host, double *gpu, int M, int N)
{
    for (int i = 0; i < M; ++i)
    {
        for (int j = 0; j < N; ++j)
        {
            if(std::abs(host[i * N + j] - gpu[i * N + j]) > 1e-3)
            {
                std::cerr << "possible error at position " << i << ',' << j << " host: " << host[i * N + j] << " device " << gpu[i * N + j] << '\n';
            }

        }
    }
}


int main(int argc, char *argv[])
{
    if(argc < 3)
    {
        std::cerr << "Usage: ./matmul_double M N K\n";
        exit(-1);
    }

    int M = std::atoi(argv[1]);
    int N = std::atoi(argv[2]);
    int K = std::atoi(argv[3]);

    /* Host alloc */
    double *hA = (double*) malloc (M * K * sizeof(double));
    double *hB = (double*) malloc (K * N * sizeof(double));
    double *hC = (double*) malloc (M * N * sizeof(double));
    double *dtohC = (double*) malloc (M * N * sizeof(double));

    /* Device alloc */
    /// complete code

    double *dA;
    double *dB;
    double *dC;

    hipMalloc((void**) &dA, M*K * sizeof(double)) ;
    hipMalloc((void**) &dB, K*N * sizeof(double)) ;
    hipMalloc((void**) &dC, M*N * sizeof(double)) ;


    /* Initialize host memory*/
    init(hA, hB, M, N, K);

    /* host compute */
    matmul_double_host(hA, hB, hC, M, N, K);


    /* Copy from host to device */
    /// complete code
    hipMemcpy(dA,hA ,M*K * sizeof(double) , hipMemcpyHostToDevice ) ;
    hipMemcpy(dB,hB ,K*N * sizeof(double) , hipMemcpyHostToDevice ) ;

    
    /* call gpu kernel */
    /// complete code

    //Initialize the grid and block dimensions here
    //dim3 dimGrid( ceil())
    dim3 dimGrid( (N - 1) / TILE_WIDTH + 1 , (M - 1)/ TILE_WIDTH + 1 , 1) ;
    //dim3 dimGrid( (M - 1) / TILE_WIDTH + 1 , (N - 1)/ TILE_WIDTH + 1 , 1) ;
    dim3 dimBlock(TILE_WIDTH , TILE_WIDTH , 1) ;


    matmul_double<<<dimGrid, dimBlock>>>(dA, dB , dC , M , N , K) ;


    /* Copy from device to host (dC -> dtohC) */
    /// complete code

    hipMemcpy(dtohC, dC , sizeof(double)*M*N , hipMemcpyDeviceToHost) ;

    /* host vs device validation */
    validate(hC, dtohC, M, N);


    /* be clean */
    free(hA);
    free(hB);
    free(hC);
    free(dtohC);

    /// add code to free gpu memory

    hipFree(dA) ;
    hipFree(dB) ;
    hipFree(dC) ;


    return 0;
}





	.text
	.file	"matmul_double.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z4initPdS_iii                  # -- Begin function _Z4initPdS_iii
	.type	_Z4initPdS_iii,@function
_Z4initPdS_iii:                         # @_Z4initPdS_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %eax
	testl	%edx, %edx
	jle	.LBB0_6
# %bb.1:                                # %.preheader31.lr.ph
	movl	%edx, %edx
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB0_2:                                # %.preheader31
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
	testl	%r8d, %r8d
	jle	.LBB0_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,8), %r11
	xorl	%ebx, %ebx
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%r9,%rbx), %ebp
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebp, %xmm0
	movsd	%xmm0, (%r11,%rbx,8)
	incq	%rbx
	cmpq	%rbx, %rax
	jne	.LBB0_4
.LBB0_5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r10
	addq	%rax, %r9
	cmpq	%rdx, %r10
	jne	.LBB0_2
.LBB0_6:                                # %.preheader30
	testl	%r8d, %r8d
	jle	.LBB0_12
# %bb.7:                                # %.preheader.lr.ph
	movl	%ecx, %edx
	movl	$1, %edi
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
.LBB0_8:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_10 Depth 2
	testl	%ecx, %ecx
	jle	.LBB0_11
# %bb.9:                                # %.lr.ph35
                                        #   in Loop: Header=BB0_8 Depth=1
	movl	%r8d, %r10d
	leaq	(%rsi,%r10,8), %r10
	xorl	%r11d, %r11d
.LBB0_10:                               #   Parent Loop BB0_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rdi,%r11), %ebx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebx, %xmm0
	movsd	%xmm0, (%r10,%r11,8)
	incq	%r11
	cmpq	%r11, %rdx
	jne	.LBB0_10
.LBB0_11:                               # %._crit_edge36
                                        #   in Loop: Header=BB0_8 Depth=1
	incq	%r9
	addq	%rdx, %rdi
	addl	%ecx, %r8d
	cmpq	%rax, %r9
	jne	.LBB0_8
.LBB0_12:                               # %._crit_edge38
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z4initPdS_iii, .Lfunc_end0-_Z4initPdS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18matmul_double_hostPdS_S_iii # -- Begin function _Z18matmul_double_hostPdS_S_iii
	.type	_Z18matmul_double_hostPdS_S_iii,@function
_Z18matmul_double_hostPdS_S_iii:        # @_Z18matmul_double_hostPdS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB1_9
# %bb.1:                                # %.preheader27.lr.ph
	movslq	%r8d, %rdi
	movl	%ecx, %ecx
	movl	%edi, %r10d
	movl	%r9d, %r11d
	leaq	(,%rdi,8), %rbx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB1_2:                                # %.preheader27
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
                                        #       Child Loop BB1_6 Depth 3
	testl	%r8d, %r8d
	jle	.LBB1_8
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%r14d, %eax
	movq	-24(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,8), %r12
	movq	%r15, %rax
	imulq	%rdi, %rax
	movq	-8(%rsp), %rdx                  # 8-byte Reload
	leaq	(%rdx,%rax,8), %r13
	movq	-16(%rsp), %rsi                 # 8-byte Reload
	xorl	%eax, %eax
.LBB1_4:                                # %.preheader
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_6 Depth 3
	xorpd	%xmm0, %xmm0
	testl	%r9d, %r9d
	jle	.LBB1_7
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_4 Depth=2
	movq	%rsi, %rbp
	xorl	%edx, %edx
.LBB1_6:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movsd	(%r12,%rdx,8), %xmm1            # xmm1 = mem[0],zero
	mulsd	(%rbp), %xmm1
	addsd	%xmm1, %xmm0
	incq	%rdx
	addq	%rbx, %rbp
	cmpq	%rdx, %r11
	jne	.LBB1_6
.LBB1_7:                                # %._crit_edge
                                        #   in Loop: Header=BB1_4 Depth=2
	movsd	%xmm0, (%r13,%rax,8)
	incq	%rax
	addq	$8, %rsi
	cmpq	%r10, %rax
	jne	.LBB1_4
.LBB1_8:                                # %._crit_edge31
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r15
	addl	%r9d, %r14d
	cmpq	%rcx, %r15
	jne	.LBB1_2
.LBB1_9:                                # %._crit_edge33
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18matmul_double_hostPdS_S_iii, .Lfunc_end1-_Z18matmul_double_hostPdS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__matmul_doublePdS_S_iii # -- Begin function _Z28__device_stub__matmul_doublePdS_S_iii
	.type	_Z28__device_stub__matmul_doublePdS_S_iii,@function
_Z28__device_stub__matmul_doublePdS_S_iii: # @_Z28__device_stub__matmul_doublePdS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matmul_doublePdS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__matmul_doublePdS_S_iii, .Lfunc_end2-_Z28__device_stub__matmul_doublePdS_S_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z8validatePdS_ii
.LCPI3_0:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI3_1:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
	.text
	.globl	_Z8validatePdS_ii
	.type	_Z8validatePdS_ii,@function
_Z8validatePdS_ii:                      # @_Z8validatePdS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, 32(%rsp)                  # 8-byte Spill
	testl	%edx, %edx
	jle	.LBB3_8
# %bb.1:                                # %.preheader.lr.ph
	movl	%edx, %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	%ecx, %ebx
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movapd	.LCPI3_0(%rip), %xmm1           # xmm1 = [NaN,NaN]
	movsd	.LCPI3_1(%rip), %xmm2           # xmm2 = mem[0],zero
	xorl	%ebp, %ebp
	movl	%ecx, 28(%rsp)                  # 4-byte Spill
.LBB3_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
	testl	%ecx, %ecx
	jle	.LBB3_7
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	16(%rsp), %eax                  # 4-byte Reload
	movq	40(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,8), %r13
	movq	32(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,8), %r12
	xorl	%r14d, %r14d
.LBB3_4:                                #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%r12,%r14,8), %xmm0            # xmm0 = mem[0],zero
	subsd	(%r13,%r14,8), %xmm0
	andpd	%xmm1, %xmm0
	ucomisd	%xmm2, %xmm0
	jbe	.LBB3_14
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=2
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$27, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movb	$44, 14(%rsp)
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%r15,%rax)
	je	.LBB3_9
# %bb.6:                                #   in Loop: Header=BB3_4 Depth=2
	movl	$1, %edx
	movq	%r15, %rdi
	leaq	14(%rsp), %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rax, %r15
	jmp	.LBB3_10
.LBB3_9:                                #   in Loop: Header=BB3_4 Depth=2
	movq	%r15, %rdi
	movl	$44, %esi
	callq	_ZNSo3putEc
.LBB3_10:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
                                        #   in Loop: Header=BB3_4 Depth=2
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	(%r12,%r14,8), %xmm0            # xmm0 = mem[0],zero
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.2, %esi
	movl	$8, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	(%r13,%r14,8), %xmm0            # xmm0 = mem[0],zero
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movb	$10, 15(%rsp)
	movq	(%rax), %rcx
	movq	-24(%rcx), %rcx
	cmpq	$0, 16(%rax,%rcx)
	je	.LBB3_12
# %bb.11:                               #   in Loop: Header=BB3_4 Depth=2
	movl	$1, %edx
	movq	%rax, %rdi
	leaq	15(%rsp), %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB3_13
.LBB3_12:                               #   in Loop: Header=BB3_4 Depth=2
	movq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNSo3putEc
.LBB3_13:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit27
                                        #   in Loop: Header=BB3_4 Depth=2
	movapd	.LCPI3_0(%rip), %xmm1           # xmm1 = [NaN,NaN]
	movsd	.LCPI3_1(%rip), %xmm2           # xmm2 = mem[0],zero
.LBB3_14:                               #   in Loop: Header=BB3_4 Depth=2
	incq	%r14
	cmpq	%r14, %rbx
	jne	.LBB3_4
.LBB3_7:                                # %._crit_edge
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%rbp
	movl	28(%rsp), %ecx                  # 4-byte Reload
	movq	16(%rsp), %rax                  # 8-byte Reload
	addl	%ecx, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	cmpq	48(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB3_2
.LBB3_8:                                # %._crit_edge30
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z8validatePdS_ii, .Lfunc_end3-_Z8validatePdS_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jle	.LBB4_4
# %bb.1:
	movq	%rsi, %r15
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r12d
	movq	16(%r15), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	24(%r15), %rdi
	callq	atoi
	movl	%eax, %ecx
	movl	%eax, %ebx
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	imull	%r12d, %ecx
	movslq	%ecx, %r13
	shlq	$3, %r13
	movq	%r13, %rdi
	movq	%r13, 48(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, %rbp
	movl	%ebx, %eax
	movq	%r14, 56(%rsp)                  # 8-byte Spill
	imull	%r14d, %eax
	movslq	%eax, %r15
	shlq	$3, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	%r14d, %eax
	imull	%r12d, %eax
	movq	%r12, %rbx
	movslq	%eax, %r12
	shlq	$3, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	leaq	32(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%rbp, %rdi
	movq	64(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	movq	%rbx, %r12
	movl	%r12d, %edx
	movq	56(%rsp), %rbx                  # 8-byte Reload
	movl	%ebx, %ecx
	movl	12(%rsp), %r13d                 # 4-byte Reload
	movl	%r13d, %r8d
	callq	_Z4initPdS_iii
	movq	%rbp, %rdi
	movq	%r14, %rsi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	%r12d, %ecx
	movl	%ebx, %r8d
	movl	%r13d, %r9d
	callq	_Z18matmul_double_hostPdS_S_iii
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbp, 72(%rsp)                  # 8-byte Spill
	movq	%rbp, %rsi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%rbx, %r15
	movl	$1, %ecx
	callq	hipMemcpy
	leal	-1(%rbx), %eax
	leal	14(%rbx), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$4, %ecx
	incl	%ecx
	leal	-1(%r12), %eax
	leal	14(%r12), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$4, %edi
	incl	%edi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_3
# %bb.2:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	%r12d, %ecx
	movl	%r15d, %r8d
	movl	12(%rsp), %r9d                  # 4-byte Reload
	callq	_Z28__device_stub__matmul_doublePdS_S_iii
.LBB4_3:
	movq	16(%rsp), %rsi
	movslq	%r12d, %rax
	movslq	%r15d, %rdx
	imulq	%rax, %rdx
	shlq	$3, %rdx
	movq	80(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	callq	_Z8validatePdS_ii
	movq	72(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_4:
	.cfi_def_cfa_offset 144
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$-1, %edi
	callq	exit
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matmul_doublePdS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13matmul_doublePdS_S_iii,@object # @_Z13matmul_doublePdS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z13matmul_doublePdS_S_iii
	.p2align	3, 0x0
_Z13matmul_doublePdS_S_iii:
	.quad	_Z28__device_stub__matmul_doublePdS_S_iii
	.size	_Z13matmul_doublePdS_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"possible error at position "
	.size	.L.str, 28

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" host: "
	.size	.L.str.1, 8

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" device "
	.size	.L.str.2, 9

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Usage: ./matmul_double M N K\n"
	.size	.L.str.3, 30

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13matmul_doublePdS_S_iii"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__matmul_doublePdS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13matmul_doublePdS_S_iii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13matmul_doublePdS_S_iii ; -- Begin function _Z13matmul_doublePdS_S_iii
	.globl	_Z13matmul_doublePdS_S_iii
	.p2align	8
	.type	_Z13matmul_doublePdS_S_iii,@function
_Z13matmul_doublePdS_S_iii:             ; @_Z13matmul_doublePdS_S_iii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v10, v0, 10, 10
	v_and_b32_e32 v11, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v9, s15, 4, v10
	v_lshl_add_u32 v0, s14, 4, v11
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v9
	v_cmp_gt_i32_e64 s0, s5, v0
	s_cmp_lt_i32 s6, -14
	s_cbranch_scc1 .LBB0_14
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v1, 3, v11
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v12, 7, v10
	s_add_i32 s1, s6, -1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v13, 0x800, v1
	s_ashr_i32 s7, s1, 31
	v_mul_lo_u32 v14, v9, s6
	s_lshr_b32 s7, s7, 28
	v_add_nc_u32_e32 v15, v12, v1
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_nc_u32_e32 v16, v13, v12
	s_add_i32 s1, s1, s7
	s_mov_b32 s12, 0
	s_ashr_i32 s7, s1, 4
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v7, s12, 4, v11
	v_mov_b32_e32 v6, 0
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s6, v7
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v5, v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s8, v5
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
	global_load_b64 v[5:6], v[5:6], off
.LBB0_5:                                ; %Flow92
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	s_waitcnt vmcnt(0)
	ds_store_b64 v15, v[5:6]
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v7, 0
	v_lshl_add_u32 v5, s12, 4, v10
	v_mov_b32_e32 v8, 0
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s6, v5
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[6:7], null, v5, s5, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[5:6], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s10, v5
	v_add_co_ci_u32_e64 v6, s1, s11, v6, s1
	global_load_b64 v[7:8], v[5:6], off
.LBB0_9:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_10:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	v_mov_b32_e32 v5, v13
	s_mov_b32 s1, 0
	s_waitcnt vmcnt(0)
	ds_store_b64 v16, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_11:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v8, s1, v12
	s_add_i32 s1, s1, 8
	ds_load_b64 v[6:7], v5
	ds_load_b64 v[17:18], v8
	v_add_nc_u32_e32 v5, 0x80, v5
	s_cmpk_eq_i32 s1, 0x80
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[1:2], v[17:18], v[6:7], v[1:2]
	s_cbranch_scc0 .LBB0_11
; %bb.12:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s1, s12, 1
	s_cmp_eq_u32 s12, s7
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s12, s1
	s_branch .LBB0_2
.LBB0_14:                               ; %Flow94
	v_cmp_gt_i32_e32 vcc_lo, s4, v9
	v_cmp_gt_i32_e64 s0, s5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_mad_u64_u32 v[3:4], null, v9, s5, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off
.LBB0_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matmul_doublePdS_S_iii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13matmul_doublePdS_S_iii, .Lfunc_end0-_Z13matmul_doublePdS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13matmul_doublePdS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13matmul_doublePdS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
