#include "includes.h"

static unsigned int GRID_SIZE_N;
static unsigned int GRID_SIZE_4N;
static unsigned int MAX_STATE_VALUE;

__global__ static void cudaPreTTGammaKernel(double *tipVector, double *l, double *r, double *umpX1, double *umpX2)
{
__shared__ volatile double ump[64];
const int tid = threadIdx.y * 4 + threadIdx.x;
if (blockIdx.y == 0)
{
ump[tid] = tipVector[4 * blockIdx.x + threadIdx.x] * l[tid];
__syncthreads();
if (threadIdx.x <= 1)
{
ump[tid] += ump[tid + 2];
}
__syncthreads();
if (threadIdx.x == 0)
{
ump[tid] += ump[tid + 1];
umpX1[blockIdx.x * 16 + threadIdx.y] = ump[tid];
}
}
else
{
ump[tid] = tipVector[4 * blockIdx.x + threadIdx.x] * r[tid];
__syncthreads();
if (threadIdx.x <= 1)
{
ump[tid] += ump[tid + 2];
}
__syncthreads();
if (threadIdx.x == 0)
{
ump[tid] += ump[tid + 1];
umpX2[blockIdx.x * 16 + threadIdx.y] = ump[tid];
}
}
}
	.file	"tmpxft_002b69d7_00000000-6_cudaPreTTGammaKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL20cudaPreTTGammaKernelPdS_S_S_S_, @function
_ZL20cudaPreTTGammaKernelPdS_S_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_ZL20cudaPreTTGammaKernelPdS_S_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_ZL20cudaPreTTGammaKernelPdS_S_S_S_, .-_ZL20cudaPreTTGammaKernelPdS_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20cudaPreTTGammaKernelPdS_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZL20cudaPreTTGammaKernelPdS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

static unsigned int GRID_SIZE_N;
static unsigned int GRID_SIZE_4N;
static unsigned int MAX_STATE_VALUE;

__global__ static void cudaPreTTGammaKernel(double *tipVector, double *l, double *r, double *umpX1, double *umpX2)
{
__shared__ volatile double ump[64];
const int tid = threadIdx.y * 4 + threadIdx.x;
if (blockIdx.y == 0)
{
ump[tid] = tipVector[4 * blockIdx.x + threadIdx.x] * l[tid];
__syncthreads();
if (threadIdx.x <= 1)
{
ump[tid] += ump[tid + 2];
}
__syncthreads();
if (threadIdx.x == 0)
{
ump[tid] += ump[tid + 1];
umpX1[blockIdx.x * 16 + threadIdx.y] = ump[tid];
}
}
else
{
ump[tid] = tipVector[4 * blockIdx.x + threadIdx.x] * r[tid];
__syncthreads();
if (threadIdx.x <= 1)
{
ump[tid] += ump[tid + 2];
}
__syncthreads();
if (threadIdx.x == 0)
{
ump[tid] += ump[tid + 1];
umpX2[blockIdx.x * 16 + threadIdx.y] = ump[tid];
}
}
}
	.text
	.file	"cudaPreTTGammaKernel.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL20cudaPreTTGammaKernelPdS_S_S_S_,"axG",@progbits,_ZL20cudaPreTTGammaKernelPdS_S_S_S_,comdat
	.globl	_ZL20cudaPreTTGammaKernelPdS_S_S_S_ ; -- Begin function _ZL20cudaPreTTGammaKernelPdS_S_S_S_
	.p2align	8
	.type	_ZL20cudaPreTTGammaKernelPdS_S_S_S_,@function
_ZL20cudaPreTTGammaKernelPdS_S_S_S_:    ; @_ZL20cudaPreTTGammaKernelPdS_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v6, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	v_mov_b32_e32 v2, 0
	s_load_b64 s[2:3], s[0:1], 0x20
	s_mov_b64 s[0:1], src_shared_base
	v_lshl_add_u32 v1, s14, 2, v6
	v_lshlrev_b32_e32 v5, 2, v4
	v_cmp_gt_u32_e64 s0, 2, v6
	s_cmp_lg_u32 s15, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_add_nc_u32_e32 v7, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v8, 3, v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v8
	s_mov_b32 s4, -1
	global_load_b64 v[2:3], v[1:2], off
	v_cndmask_b32_e32 v0, 0, v8, vcc_lo
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, 0
	s_cbranch_scc0 .LBB0_4
; %bb.1:
	global_load_b64 v[9:10], v8, s[8:9]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[9:10], v[2:3], v[9:10]
	flat_store_b64 v[0:1], v[9:10] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_lshl_add_u32 v9, v7, 3, 16
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v9
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cndmask_b32_e64 v10, 0, s5, vcc_lo
	flat_load_b64 v[9:10], v[9:10] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[11:12], v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[9:10], v[9:10], v[11:12]
	flat_store_b64 v[0:1], v[9:10] dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e64 s1, 0, v6
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	s_mov_b32 s4, 0
	buffer_gl0_inv
	s_branch .LBB0_5
.LBB0_4:
                                        ; implicit-def: $sgpr2_sgpr3
.LBB0_5:                                ; %Flow
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_9
; %bb.6:
	global_load_b64 v[8:9], v8, s[6:7]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[2:3], v[2:3], v[8:9]
	flat_store_b64 v[0:1], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_lshl_add_u32 v2, v7, 3, 16
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s3, vcc_lo
	flat_load_b64 v[2:3], v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[7:8], v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[7:8]
	flat_store_b64 v[0:1], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e64 s1, 0, v6
	s_mov_b64 s[2:3], s[10:11]
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_9:                                ; %Flow46
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_11
; %bb.10:                               ; %.sink.split
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v2, v5, 3, 8
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	flat_load_b64 v[2:3], v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b64 v[5:6], v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[5:6]
	flat_store_b64 v[0:1], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	v_mov_b32_e32 v3, 0
	flat_load_b64 v[0:1], v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v2, s14, 4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL20cudaPreTTGammaKernelPdS_S_S_S_
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL20cudaPreTTGammaKernelPdS_S_S_S_,"axG",@progbits,_ZL20cudaPreTTGammaKernelPdS_S_S_S_,comdat
.Lfunc_end0:
	.size	_ZL20cudaPreTTGammaKernelPdS_S_S_S_, .Lfunc_end0-_ZL20cudaPreTTGammaKernelPdS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 656
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 512
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL20cudaPreTTGammaKernelPdS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL20cudaPreTTGammaKernelPdS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
