#include <iostream>
#include <vector>


__global__ void vecadd( int * v0, int * v1, std::size_t size )
{
  auto tid = threadIdx.x;
  v0[ tid ] += v1[ tid ];
}


int main()
{
  cudaError_t err;
  
  std::size_t const size = 100;
  std::size_t const sizeb = size * sizeof( int );
  
  int * v0_h = nullptr;
  int * v1_h = nullptr;
  
  int * v0_d = nullptr;
  int * v1_d = nullptr;
  
  err = cudaMallocHost( &v0_h, sizeb );
  if( err != cudaSuccess ) { std::cerr << "Error" << std::endl; }
  err = cudaMallocHost( &v1_h, sizeb );
  if( err != cudaSuccess ) { std::cerr << "Error" << std::endl; }

  for( std::size_t i = 0 ; i < size ; ++i )
  {
    v0_h[ i ] = v1_h[ i ] = i;
  }

  err = cudaMalloc( &v0_d, sizeb );
  if( err != cudaSuccess ) { std::cerr << "Error" << std::endl; }
  err = cudaMalloc( &v1_d, sizeb );
  if( err != cudaSuccess ) { std::cerr << "Error" << std::endl; }
  
  cudaStream_t streams[ 2 ];

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    cudaStreamCreate( &streams[ i ] );
  }

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    cudaMemcpyAsync( v0_d + i*size/2, v0_h + i*size/2, sizeb/2, cudaMemcpyHostToDevice, streams[ i ] );
    cudaMemcpyAsync( v1_d + i*size/2, v1_h + i*size/2, sizeb/2, cudaMemcpyHostToDevice, streams[ i ] );
  }

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    vecadd<<< 1, size/2, 0, streams[ i ] >>>( v0_d + i*size/2, v1_d + i*size/2, size/2 );
  }
  /*
  cudaDeviceSynchronize();
  err = cudaGetLastError();
  if( err != cudaSuccess )
  {
     std::cout << cudaGetErrorString( err ) << std::endl;
  }
*/

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    cudaMemcpyAsync( v0_h + i*size/2, v0_d + i*size/2, sizeb/2, cudaMemcpyDeviceToHost, streams[ i ] );
  }

  cudaDeviceSynchronize();
  /*
  err = cudaGetLastError();
  if( err != cudaSuccess )
  {
     std::cout << cudaGetErrorString( err ) << std::endl;
  }
*/
  for( std::size_t i = 0 ; i < 2 ; ++i )
  {  
    cudaStreamDestroy( streams[ i ] );
  }

  for( std::size_t i = 0 ; i < size ; ++i )
  {
    std::cout << v0_h[ i ] << std::endl;
  }

  cudaFree( v0_d );
  cudaFree( v1_d );

  cudaFreeHost( v0_h );
  cudaFreeHost( v1_h );

  return 0;
}
	.file	"tmpxft_00222359_00000000-6_07-streams.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4001:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4001:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4657:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4657:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z28__device_stub__Z6vecaddPiS_mPiS_m
	.type	_Z28__device_stub__Z6vecaddPiS_mPiS_m, @function
_Z28__device_stub__Z6vecaddPiS_mPiS_m:
.LFB4023:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6vecaddPiS_m(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L3:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4023:
	.size	_Z28__device_stub__Z6vecaddPiS_mPiS_m, .-_Z28__device_stub__Z6vecaddPiS_mPiS_m
	.globl	_Z6vecaddPiS_m
	.type	_Z6vecaddPiS_m, @function
_Z6vecaddPiS_m:
.LFB4024:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z6vecaddPiS_mPiS_m
	.cfi_endproc
.LFE4024:
	.size	_Z6vecaddPiS_m, .-_Z6vecaddPiS_m
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Error"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3998:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xorl	%edx, %edx
	movl	$400, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	xorl	%eax, %eax
	movq	%rax, (%rsp)
	movq	%rax, 8(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 24(%rsp)
	call	cudaHostAlloc@PLT
	testl	%eax, %eax
	je	.L10
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L10:
	xorl	%edx, %edx
	leaq	8(%rsp), %rdi
	movl	$400, %esi
	call	cudaHostAlloc@PLT
	testl	%eax, %eax
	je	.L11
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L11:
	movq	8(%rsp), %rcx
	movq	(%rsp), %rdx
	xorl	%eax, %eax
.L12:
	movl	%eax, (%rcx,%rax,4)
	movl	%eax, (%rdx,%rax,4)
	incq	%rax
	cmpq	$100, %rax
	jne	.L12
	leaq	16(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L13
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L13:
	leaq	24(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L14
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L14:
	leaq	56(%rsp), %rbx
	movl	$2147483673, %ebp
	xorl	%r12d, %r12d
	movq	%rbx, %rdi
	addq	%rbp, %rbp
	call	cudaStreamCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaStreamCreate@PLT
	movq	56(%rsp), %r8
	movq	(%rsp), %rsi
	movl	$1, %ecx
	movq	16(%rsp), %rdi
	movl	$200, %edx
	call	cudaMemcpyAsync@PLT
	movq	56(%rsp), %r8
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	24(%rsp), %rdi
	movl	$200, %edx
	call	cudaMemcpyAsync@PLT
	movq	(%rsp), %rax
	movq	64(%rsp), %r8
	movl	$1, %ecx
	movl	$200, %edx
	leaq	200(%rax), %rsi
	movq	16(%rsp), %rax
	leaq	200(%rax), %rdi
	call	cudaMemcpyAsync@PLT
	movq	8(%rsp), %rax
	movq	64(%rsp), %r8
	movl	$1, %ecx
	movl	$200, %edx
	leaq	200(%rax), %rsi
	movq	24(%rsp), %rax
	leaq	200(%rax), %rdi
	call	cudaMemcpyAsync@PLT
.L16:
	movq	(%rbx,%r12,8), %r9
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rbp, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	%r12, %rdi
	movq	24(%rsp), %rsi
	movl	$50, %edx
	negq	%rdi
	andl	$100, %edi
	addq	%rdi, %rdi
	addq	%rdi, %rsi
	addq	16(%rsp), %rdi
	call	_Z28__device_stub__Z6vecaddPiS_mPiS_m
.L15:
	testq	%r12, %r12
	jne	.L35
	movl	$1, %r12d
	jmp	.L16
.L35:
	movq	56(%rsp), %r8
	movq	(%rsp), %rdi
	movl	$2, %ecx
	xorl	%ebx, %ebx
	movq	16(%rsp), %rsi
	movl	$200, %edx
	leaq	_ZSt4cout(%rip), %rbp
	call	cudaMemcpyAsync@PLT
	movq	16(%rsp), %rax
	movq	64(%rsp), %r8
	movl	$2, %ecx
	movl	$200, %edx
	leaq	200(%rax), %rsi
	movq	(%rsp), %rax
	leaq	200(%rax), %rdi
	call	cudaMemcpyAsync@PLT
	call	cudaDeviceSynchronize@PLT
	movq	56(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	64(%rsp), %rdi
	call	cudaStreamDestroy@PLT
.L17:
	movq	(%rsp), %rax
	movq	%rbp, %rdi
	movl	(%rax,%rbx), %esi
	addq	$4, %rbx
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpq	$400, %rbx
	jne	.L17
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3998:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z6vecaddPiS_m"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4026:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6vecaddPiS_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4026:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>


__global__ void vecadd( int * v0, int * v1, std::size_t size )
{
  auto tid = threadIdx.x;
  v0[ tid ] += v1[ tid ];
}


int main()
{
  hipError_t err;
  
  std::size_t const size = 100;
  std::size_t const sizeb = size * sizeof( int );
  
  int * v0_h = nullptr;
  int * v1_h = nullptr;
  
  int * v0_d = nullptr;
  int * v1_d = nullptr;
  
  err = hipHostMalloc( &v0_h, sizeb , hipHostMallocDefault);
  if( err != hipSuccess ) { std::cerr << "Error" << std::endl; }
  err = hipHostMalloc( &v1_h, sizeb , hipHostMallocDefault);
  if( err != hipSuccess ) { std::cerr << "Error" << std::endl; }

  for( std::size_t i = 0 ; i < size ; ++i )
  {
    v0_h[ i ] = v1_h[ i ] = i;
  }

  err = hipMalloc( &v0_d, sizeb );
  if( err != hipSuccess ) { std::cerr << "Error" << std::endl; }
  err = hipMalloc( &v1_d, sizeb );
  if( err != hipSuccess ) { std::cerr << "Error" << std::endl; }
  
  hipStream_t streams[ 2 ];

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    hipStreamCreate( &streams[ i ] );
  }

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    hipMemcpyAsync( v0_d + i*size/2, v0_h + i*size/2, sizeb/2, hipMemcpyHostToDevice, streams[ i ] );
    hipMemcpyAsync( v1_d + i*size/2, v1_h + i*size/2, sizeb/2, hipMemcpyHostToDevice, streams[ i ] );
  }

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    vecadd<<< 1, size/2, 0, streams[ i ] >>>( v0_d + i*size/2, v1_d + i*size/2, size/2 );
  }
  /*
  cudaDeviceSynchronize();
  err = cudaGetLastError();
  if( err != cudaSuccess )
  {
     std::cout << cudaGetErrorString( err ) << std::endl;
  }
*/

  for( std::size_t i = 0 ; i < 2 ; ++i )
  {
    hipMemcpyAsync( v0_h + i*size/2, v0_d + i*size/2, sizeb/2, hipMemcpyDeviceToHost, streams[ i ] );
  }

  hipDeviceSynchronize();
  /*
  err = cudaGetLastError();
  if( err != cudaSuccess )
  {
     std::cout << cudaGetErrorString( err ) << std::endl;
  }
*/
  for( std::size_t i = 0 ; i < 2 ; ++i )
  {  
    hipStreamDestroy( streams[ i ] );
  }

  for( std::size_t i = 0 ; i < size ; ++i )
  {
    std::cout << v0_h[ i ] << std::endl;
  }

  hipFree( v0_d );
  hipFree( v1_d );

  hipHostFree( v0_h );
  hipHostFree( v1_h );

  return 0;
}
	.text
	.file	"07-streams.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z21__device_stub__vecaddPiS_m  # -- Begin function _Z21__device_stub__vecaddPiS_m
	.type	_Z21__device_stub__vecaddPiS_m,@function
_Z21__device_stub__vecaddPiS_m:         # @_Z21__device_stub__vecaddPiS_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6vecaddPiS_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__vecaddPiS_m, .Lfunc_end0-_Z21__device_stub__vecaddPiS_m
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movq	%rax, (%rdi)
	movq	%rax, 24(%rsp)
	movq	%rax, (%rsp)
	movq	%rax, 16(%rsp)
	movl	$400, %esi                      # imm = 0x190
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_2:
	leaq	24(%rsp), %rdi
	movl	$400, %esi                      # imm = 0x190
	xorl	%edx, %edx
	callq	hipHostMalloc
	testl	%eax, %eax
	je	.LBB1_4
# %bb.3:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_4:
	movq	24(%rsp), %rax
	movq	8(%rsp), %rcx
	xorl	%edx, %edx
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	movl	%edx, (%rax,%rdx,4)
	movl	%edx, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$100, %rdx
	jne	.LBB1_5
# %bb.6:
	movq	%rsp, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_8
# %bb.7:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_8:
	leaq	16(%rsp), %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_10
# %bb.9:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_10:                               # %.preheader53.preheader.critedge
	leaq	32(%rsp), %rdi
	callq	hipStreamCreate
	leaq	40(%rsp), %rdi
	callq	hipStreamCreate
	movb	$1, %bpl
	xorl	%r14d, %r14d
.LBB1_11:                               # %.preheader53
                                        # =>This Inner Loop Header: Depth=1
	imulq	$200, %r14, %rbx
	movq	(%rsp), %rdi
	addq	%rbx, %rdi
	movq	8(%rsp), %rsi
	addq	%rbx, %rsi
	movq	32(%rsp,%r14,8), %r8
	movl	$200, %edx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	16(%rsp), %rdi
	addq	%rbx, %rdi
	addq	24(%rsp), %rbx
	movq	32(%rsp,%r14,8), %r8
	movl	$200, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movl	$1, %r14d
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB1_11
# %bb.12:                               # %.preheader52.preheader
	movb	$1, %bpl
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	xorl	%r15d, %r15d
	leaq	49(%rbx), %r14
.LBB1_13:                               # %.preheader52
                                        # =>This Inner Loop Header: Depth=1
	movq	32(%rsp,%r15,8), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.14:                               #   in Loop: Header=BB1_13 Depth=1
	imulq	$200, %r15, %rsi
	movq	(%rsp), %rdi
	addq	%rsi, %rdi
	addq	16(%rsp), %rsi
	movl	$50, %edx
	callq	_Z21__device_stub__vecaddPiS_m
.LBB1_15:                               #   in Loop: Header=BB1_13 Depth=1
	movl	$1, %r15d
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB1_13
# %bb.16:                               # %.preheader51
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	32(%rsp), %r8
	movl	$200, %ebx
	movl	$200, %edx
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movq	8(%rsp), %rdi
	addq	%rbx, %rdi
	movq	(%rsp), %rsi
	addq	%rbx, %rsi
	movq	40(%rsp), %r8
	movl	$200, %edx
	movl	$2, %ecx
	callq	hipMemcpyAsync
	callq	hipDeviceSynchronize
	movq	32(%rsp), %rdi
	callq	hipStreamDestroy
	movq	40(%rsp), %rdi
	callq	hipStreamDestroy
	xorl	%r14d, %r14d
.LBB1_17:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rax
	movl	(%rax,%r14,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r14
	cmpq	$100, %r14
	jne	.LBB1_17
# %bb.18:
	movq	(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipHostFree
	movq	24(%rsp), %rdi
	callq	hipHostFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6vecaddPiS_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6vecaddPiS_m,@object          # @_Z6vecaddPiS_m
	.section	.rodata,"a",@progbits
	.globl	_Z6vecaddPiS_m
	.p2align	3, 0x0
_Z6vecaddPiS_m:
	.quad	_Z21__device_stub__vecaddPiS_m
	.size	_Z6vecaddPiS_m, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error"
	.size	.L.str, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6vecaddPiS_m"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__vecaddPiS_m
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6vecaddPiS_m
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6vecaddPiS_m          ; -- Begin function _Z6vecaddPiS_m
	.globl	_Z6vecaddPiS_m
	.p2align	8
	.type	_Z6vecaddPiS_m,@function
_Z6vecaddPiS_m:                         ; @_Z6vecaddPiS_m
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v1, v0, s[2:3]
	global_load_b32 v2, v0, s[0:1]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6vecaddPiS_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 4
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6vecaddPiS_m, .Lfunc_end0-_Z6vecaddPiS_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 64
; NumSgprs: 4
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 4
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6vecaddPiS_m
    .private_segment_fixed_size: 0
    .sgpr_count:     4
    .sgpr_spill_count: 0
    .symbol:         _Z6vecaddPiS_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
