/**
*Developed By Karan Bhagat
*March 2017
**/

#include <stdio.h>
#include <stdlib.h>

//cuda kernel for multiplying two matrices without tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	
	//check if thread directly maps to the dimensions of resulting matrix
	if (row < a_rows && col < b_columns)
	{
		int result = 0;
		int k;
		for (k = 0; k < a_columns; k++)
		{
			result += (a[row * a_columns + k] * b[k * b_columns + col]);
		}
		c[row * b_columns + col] = result;
	}
}

void build_matrix(FILE *file, int* mat, int rows, int columns);

int main(int argc, char **argv)
{
	//check for filenames and matrices' dimensions
	if (argc != 6)
	{
		printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
		exit(1);
	}
	
	char* fileA_name = argv[1];//matrix A filename
	char* fileB_name = argv[2];//matrix B filename

	// a_columns can also be perceived as b_rows
	int a_rows, a_columns, b_columns;
	
	//read matrix A and B's dimensions
	sscanf(argv[3], "%d", &a_rows);
	sscanf(argv[4], "%d", &a_columns);
	sscanf(argv[5], "%d", &b_columns);
	
	FILE *fileA = fopen(fileA_name, "r");
	FILE *fileB = fopen(fileB_name, "r");

	//declare host and device matrices pointers
	int* mat_a;
	int* mat_b;
	int* mat_c;
	int* d_mat_a;
	int* d_mat_b;
	int* d_mat_c;
	
	//allocate memory for host matrices
	mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
	mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
	mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
	
	int i, j;
	
	build_matrix(fileA, mat_a, a_rows, a_columns);
	build_matrix(fileB, mat_b, a_columns, b_columns);
	
	//declare dimensions for the grid and block
	dim3 dimBlock(2,2);
	dim3 dimGrid((int)ceil(b_columns/2),(int)ceil(a_rows/2));
	
	const size_t size_a = a_rows * a_columns * sizeof(int);
	const size_t size_b = a_columns * b_columns * sizeof(int);
	const size_t size_c = a_rows * b_columns * sizeof(int);

	//allocate matrices memeory on device
	cudaMalloc((void **)&d_mat_a, size_a);
	cudaMalloc((void **)&d_mat_b, size_b);
	cudaMalloc((void **)&d_mat_c, size_c);

	//copy A and B matrices from host to device
	cudaMemcpy(d_mat_a, mat_a, size_a, cudaMemcpyHostToDevice);
	cudaMemcpy(d_mat_b, mat_b, size_b, cudaMemcpyHostToDevice);

	//execute cuda kernel
	matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);

	//copy the compute matrix C from device to host
	cudaMemcpy(mat_c, d_mat_c, size_c, cudaMemcpyDeviceToHost);
	
	//free cuda memory
	cudaFree(d_mat_a);
	cudaFree(d_mat_b);
	cudaFree(d_mat_c);

	//print the resulting matrix
	for (i = 0; i < a_rows; i++)
	{
		for (j = 0; j < b_columns; j++)
		{
			printf("%d ", mat_c[i * b_columns + j]);
		}
		printf("\n");
	}
}

//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
	int i, j;
	for (i = 0; i < rows; i++)
	{
		for (j = 0; j < columns; j++) 
		{
			fscanf(file, "%d", &mat[i * columns + j]);
		}
	}
}
	.file	"tmpxft_00381390_00000000-6_matrix_mul_without_tiling.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d"
	.text
	.globl	_Z12build_matrixP8_IO_FILEPiii
	.type	_Z12build_matrixP8_IO_FILEPiii, @function
_Z12build_matrixP8_IO_FILEPiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r9d
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%rdi, (%rsp)
.L3:
	cmpl	%r9d, %r15d
	jge	.L2
	movslq	%r14d, %rax
	xorl	%ebp, %ebp
	leaq	0(%r13,%rax,4), %r12
.L6:
	cmpl	%ebx, %ebp
	jge	.L9
	movq	(%rsp), %rdi
	movq	%r12, %rdx
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	movl	%r9d, 12(%rsp)
	incl	%ebp
	addq	$4, %r12
	call	__isoc23_fscanf@PLT
	movl	12(%rsp), %r9d
	jmp	.L6
.L9:
	incl	%r15d
	addl	%ebx, %r14d
	jmp	.L3
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z12build_matrixP8_IO_FILEPiii, .-_Z12build_matrixP8_IO_FILEPiii
	.globl	_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
	.type	_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii, @function
_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z17matrix_mul_kernelPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii, .-_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
	.globl	_Z17matrix_mul_kernelPiS_S_iii
	.type	_Z17matrix_mul_kernelPiS_S_iii, @function
_Z17matrix_mul_kernelPiS_S_iii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2054:
	.size	_Z17matrix_mul_kernelPiS_S_iii, .-_Z17matrix_mul_kernelPiS_S_iii
	.section	.rodata.str1.1
.LC1:
	.string	"Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>"
.LC2:
	.string	"r"
.LC3:
	.string	"%d "
.LC4:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	cmpl	$6, %edi
	je	.L16
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L16:
	leaq	.LC0(%rip), %rbp
	movq	24(%rsi), %rdi
	movq	%rsi, %rbx
	xorl	%eax, %eax
	movq	8(%rsi), %r12
	movq	16(%rsi), %r13
	leaq	28(%rsp), %rdx
	movq	%rbp, %rsi
	call	__isoc23_sscanf@PLT
	movq	32(%rbx), %rdi
	movq	%rbp, %rsi
	xorl	%eax, %eax
	leaq	32(%rsp), %rdx
	call	__isoc23_sscanf@PLT
	movq	40(%rbx), %rdi
	leaq	36(%rsp), %rdx
	xorl	%eax, %eax
	movq	%rbp, %rsi
	leaq	.LC2(%rip), %rbx
	call	__isoc23_sscanf@PLT
	movq	%rbx, %rsi
	movq	%r12, %rdi
	call	fopen@PLT
	movq	%rbx, %rsi
	movq	%r13, %rdi
	movq	%rax, %r12
	call	fopen@PLT
	movl	28(%rsp), %r15d
	movl	32(%rsp), %ebp
	movq	%rax, 8(%rsp)
	movl	%r15d, %edi
	imull	%ebp, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movl	36(%rsp), %ebx
	movl	%ebp, %edi
	movq	%rax, %r14
	imull	%ebx, %edi
	imull	%r15d, %ebx
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movslq	%ebx, %rdi
	salq	$2, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movl	%ebp, %ecx
	movl	%r15d, %edx
	movq	%r12, %rdi
	movq	%r14, %rsi
	movq	%rax, %rbx
	call	_Z12build_matrixP8_IO_FILEPiii
	movl	36(%rsp), %ecx
	movl	32(%rsp), %edx
	movq	%r13, %rsi
	movq	8(%rsp), %rdi
	call	_Z12build_matrixP8_IO_FILEPiii
	movl	36(%rsp), %esi
	movl	$2, %edi
	movabsq	$8589934594, %rax
	movl	28(%rsp), %ecx
	movq	%rax, 64(%rsp)
	movl	%esi, %eax
	movl	32(%rsp), %r12d
	movl	$1, 72(%rsp)
	cltd
	movl	%ecx, %r15d
	movl	$1, 84(%rsp)
	idivl	%edi
	imull	%r12d, %r15d
	imull	%esi, %r12d
	movslq	%r15d, %r15
	salq	$2, %r15
	movslq	%r12d, %r12
	salq	$2, %r12
	movl	%eax, 76(%rsp)
	movl	%ecx, %eax
	imull	%esi, %ecx
	movq	%r15, %rsi
	cltd
	idivl	%edi
	movslq	%ecx, %rbp
	leaq	40(%rsp), %rdi
	salq	$2, %rbp
	movl	%eax, 80(%rsp)
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movq	%r15, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movq	%r12, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	72(%rsp), %ecx
	movl	84(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	76(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movl	36(%rsp), %r9d
	movl	32(%rsp), %r8d
	movl	28(%rsp), %ecx
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
.L17:
	movq	56(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	leaq	.LC3(%rip), %rbp
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
.L18:
	cmpl	%r12d, 28(%rsp)
	jle	.L24
	xorl	%r13d, %r13d
.L20:
	movl	36(%rsp), %eax
	cmpl	%r13d, %eax
	jle	.L25
	imull	%r12d, %eax
	movq	%rbp, %rsi
	movl	$2, %edi
	addl	%r13d, %eax
	incl	%r13d
	cltq
	movl	(%rbx,%rax,4), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L20
.L25:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%r12d
	call	__printf_chk@PLT
	jmp	.L18
.L24:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z17matrix_mul_kernelPiS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17matrix_mul_kernelPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
*Developed By Karan Bhagat
*March 2017
**/


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

//cuda kernel for multiplying two matrices without tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	int row = blockIdx.y * blockDim.y + threadIdx.y;
	
	//check if thread directly maps to the dimensions of resulting matrix
	if (row < a_rows && col < b_columns)
	{
		int result = 0;
		int k;
		for (k = 0; k < a_columns; k++)
		{
			result += (a[row * a_columns + k] * b[k * b_columns + col]);
		}
		c[row * b_columns + col] = result;
	}
}

void build_matrix(FILE *file, int* mat, int rows, int columns);

int main(int argc, char **argv)
{
	//check for filenames and matrices' dimensions
	if (argc != 6)
	{
		printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
		exit(1);
	}
	
	char* fileA_name = argv[1];//matrix A filename
	char* fileB_name = argv[2];//matrix B filename

	// a_columns can also be perceived as b_rows
	int a_rows, a_columns, b_columns;
	
	//read matrix A and B's dimensions
	sscanf(argv[3], "%d", &a_rows);
	sscanf(argv[4], "%d", &a_columns);
	sscanf(argv[5], "%d", &b_columns);
	
	FILE *fileA = fopen(fileA_name, "r");
	FILE *fileB = fopen(fileB_name, "r");

	//declare host and device matrices pointers
	int* mat_a;
	int* mat_b;
	int* mat_c;
	int* d_mat_a;
	int* d_mat_b;
	int* d_mat_c;
	
	//allocate memory for host matrices
	mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
	mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
	mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
	
	int i, j;
	
	build_matrix(fileA, mat_a, a_rows, a_columns);
	build_matrix(fileB, mat_b, a_columns, b_columns);
	
	//declare dimensions for the grid and block
	dim3 dimBlock(2,2);
	dim3 dimGrid((int)ceil(b_columns/2),(int)ceil(a_rows/2));
	
	const size_t size_a = a_rows * a_columns * sizeof(int);
	const size_t size_b = a_columns * b_columns * sizeof(int);
	const size_t size_c = a_rows * b_columns * sizeof(int);

	//allocate matrices memeory on device
	hipMalloc((void **)&d_mat_a, size_a);
	hipMalloc((void **)&d_mat_b, size_b);
	hipMalloc((void **)&d_mat_c, size_c);

	//copy A and B matrices from host to device
	hipMemcpy(d_mat_a, mat_a, size_a, hipMemcpyHostToDevice);
	hipMemcpy(d_mat_b, mat_b, size_b, hipMemcpyHostToDevice);

	//execute cuda kernel
	matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);

	//copy the compute matrix C from device to host
	hipMemcpy(mat_c, d_mat_c, size_c, hipMemcpyDeviceToHost);
	
	//free cuda memory
	hipFree(d_mat_a);
	hipFree(d_mat_b);
	hipFree(d_mat_c);

	//print the resulting matrix
	for (i = 0; i < a_rows; i++)
	{
		for (j = 0; j < b_columns; j++)
		{
			printf("%d ", mat_c[i * b_columns + j]);
		}
		printf("\n");
	}
}

//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
	int i, j;
	for (i = 0; i < rows; i++)
	{
		for (j = 0; j < columns; j++) 
		{
			fscanf(file, "%d", &mat[i * columns + j]);
		}
	}
}
	.text
	.file	"matrix_mul_without_tiling.hip"
	.globl	_Z32__device_stub__matrix_mul_kernelPiS_S_iii # -- Begin function _Z32__device_stub__matrix_mul_kernelPiS_S_iii
	.type	_Z32__device_stub__matrix_mul_kernelPiS_S_iii,@function
_Z32__device_stub__matrix_mul_kernelPiS_S_iii: # @_Z32__device_stub__matrix_mul_kernelPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17matrix_mul_kernelPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__matrix_mul_kernelPiS_S_iii, .Lfunc_end0-_Z32__device_stub__matrix_mul_kernelPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$6, %edi
	jne	.LBB1_10
# %bb.1:
	movq	%rsi, %r15
	movq	8(%rsi), %r14
	movq	16(%rsi), %rbx
	movq	24(%rsi), %rdi
	leaq	16(%rsp), %rdx
	movl	$.L.str.1, %esi
	movq	%rdx, %r12
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	32(%r15), %rdi
	leaq	20(%rsp), %rdx
	movl	$.L.str.1, %esi
	movq	%rdx, %r13
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	40(%r15), %rdi
	leaq	12(%rsp), %rdx
	movl	$.L.str.1, %esi
	movq	%rdx, %r15
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movl	$.L.str.2, %esi
	movq	%r14, %rdi
	callq	fopen
	movq	%rax, %r14
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	callq	fopen
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	(%r12), %r12d
	movl	(%r13), %r13d
	movl	%r13d, %eax
	imull	%r12d, %eax
	movslq	%eax, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %rbp
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	(%r15), %ebx
	movl	%ebx, %eax
	imull	%r13d, %eax
	movslq	%eax, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	imull	%r12d, %ebx
	movslq	%ebx, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r14, %rdi
	movq	%rbp, %rsi
	movl	%r12d, %edx
	movl	%r13d, %ecx
	callq	_Z12build_matrixP8_IO_FILEPiii
	leaq	20(%rsp), %r14
	movl	(%r14), %edx
	leaq	12(%rsp), %r12
	movl	(%r12), %ecx
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rsi
	callq	_Z12build_matrixP8_IO_FILEPiii
	movl	(%r12), %eax
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	sarl	%ecx
	leaq	16(%rsp), %rdx
	movl	(%rdx), %edx
	movl	%edx, %r15d
	shrl	$31, %r15d
	addl	%edx, %r15d
	sarl	%r15d
	shlq	$32, %r15
	orq	%rcx, %r15
	movl	(%r14), %ecx
	movl	%ecx, %esi
	imull	%edx, %esi
	movslq	%esi, %r12
	shlq	$2, %r12
	imull	%eax, %ecx
	movslq	%ecx, %rbp
	shlq	$2, %rbp
	imull	%eax, %edx
	movslq	%edx, %r14
	shlq	$2, %r14
	leaq	40(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$8589934594, %rdx               # imm = 0x200000002
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	16(%rsp), %ecx
	movl	20(%rsp), %r8d
	movl	12(%rsp), %r9d
	callq	_Z32__device_stub__matrix_mul_kernelPiS_S_iii
.LBB1_3:
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	cmpl	$0, 16(%rsp)
	jle	.LBB1_9
# %bb.4:                                # %.preheader.preheader
	xorl	%ebp, %ebp
.LBB1_5:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_7 Depth 2
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB1_8
# %bb.6:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_5 Depth=1
	xorl	%r14d, %r14d
.LBB1_7:                                # %.lr.ph
                                        #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebp, %eax
	cltq
	addq	%r14, %rax
	movl	(%rbx,%rax,4), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	12(%rsp), %eax
	incq	%r14
	cmpl	%eax, %r14d
	jl	.LBB1_7
.LBB1_8:                                # %._crit_edge
                                        #   in Loop: Header=BB1_5 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incl	%ebp
	cmpl	16(%rsp), %ebp
	jl	.LBB1_5
.LBB1_9:                                # %._crit_edge41
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_10:
	.cfi_def_cfa_offset 128
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z12build_matrixP8_IO_FILEPiii  # -- Begin function _Z12build_matrixP8_IO_FILEPiii
	.type	_Z12build_matrixP8_IO_FILEPiii,@function
_Z12build_matrixP8_IO_FILEPiii:         # @_Z12build_matrixP8_IO_FILEPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, 8(%rsp)                   # 8-byte Spill
	testl	%edx, %edx
	jle	.LBB2_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%ecx, %ebx
	movq	%rdi, %r15
	movl	%edx, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%ecx, %eax
	movq	%rax, (%rsp)                    # 8-byte Spill
	xorl	%r14d, %r14d
	xorl	%ebp, %ebp
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB2_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	movl	%r14d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %r12
	movq	(%rsp), %r13                    # 8-byte Reload
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r12
	decq	%r13
	jne	.LBB2_4
.LBB2_5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%rbp
	addl	%ebx, %r14d
	cmpq	16(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB2_2
.LBB2_6:                                # %._crit_edge14
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z12build_matrixP8_IO_FILEPiii, .Lfunc_end2-_Z12build_matrixP8_IO_FILEPiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17matrix_mul_kernelPiS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17matrix_mul_kernelPiS_S_iii,@object # @_Z17matrix_mul_kernelPiS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z17matrix_mul_kernelPiS_S_iii
	.p2align	3, 0x0
_Z17matrix_mul_kernelPiS_S_iii:
	.quad	_Z32__device_stub__matrix_mul_kernelPiS_S_iii
	.size	_Z17matrix_mul_kernelPiS_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>"
	.size	.L.str, 77

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"r"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d "
	.size	.L.str.3, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17matrix_mul_kernelPiS_S_iii"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__matrix_mul_kernelPiS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17matrix_mul_kernelPiS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17matrix_mul_kernelPiS_S_iii ; -- Begin function _Z17matrix_mul_kernelPiS_S_iii
	.globl	_Z17matrix_mul_kernelPiS_S_iii
	.p2align	8
	.type	_Z17matrix_mul_kernelPiS_S_iii,@function
_Z17matrix_mul_kernelPiS_S_iii:         ; @_Z17matrix_mul_kernelPiS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s6, v1
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v0, s5
	v_mov_b32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_add_i32 s5, s5, -1
	s_cmp_lg_u32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	global_load_b32 v8, v[3:4], off
	global_load_b32 v9, v[6:7], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s6, v5
	s_cbranch_scc1 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v2, 0
.LBB0_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v0, s6, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17matrix_mul_kernelPiS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17matrix_mul_kernelPiS_S_iii, .Lfunc_end0-_Z17matrix_mul_kernelPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17matrix_mul_kernelPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17matrix_mul_kernelPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
