#include <stdlib.h>
#include <math.h>

__global__ void VecEval(float *C)
{
  int i = threadIdx.x;
  int j;
  for (j=0; j<=100; j++)
    C[i] = 1./sqrt(1.+i) + j*sin(2.*sin(0.1*i));
}

int main()
{ const int N=1000000;
  float C[N];
  // Kernel invocation with N threads 
  VecEval<<<1, N>>>(C);
}

	.file	"tmpxft_00235502_00000000-6_helloworld.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z26__device_stub__Z7VecEvalPfPf
	.type	_Z26__device_stub__Z7VecEvalPfPf, @function
_Z26__device_stub__Z7VecEvalPfPf:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z7VecEvalPf(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z26__device_stub__Z7VecEvalPfPf, .-_Z26__device_stub__Z7VecEvalPfPf
	.globl	_Z7VecEvalPf
	.type	_Z7VecEvalPf, @function
_Z7VecEvalPf:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z7VecEvalPfPf
	.cfi_endproc
.LFE2034:
	.size	_Z7VecEvalPf, .-_Z7VecEvalPf
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2008:
	.cfi_startproc
	endbr64
	leaq	-3997696(%rsp), %r11
	.cfi_def_cfa 11, 3997704
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$2344, %rsp
	.cfi_def_cfa_offset 4000048
	movl	$67124489, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%fs:40, %rax
	movq	%rax, 4000024(%rsp)
	xorl	%eax, %eax
	movq	%rdx, 12(%rsp)
	movl	$1, 20(%rsp)
	movq	%rdi, (%rsp)
	movl	$1, 8(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	leaq	24(%rsp), %rdi
	call	_Z26__device_stub__Z7VecEvalPfPf
.L9:
	movq	4000024(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	xorl	%eax, %eax
	addq	$4000040, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7VecEvalPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7VecEvalPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <math.h>

__global__ void VecEval(float *C)
{
  int i = threadIdx.x;
  int j;
  for (j=0; j<=100; j++)
    C[i] = 1./sqrt(1.+i) + j*sin(2.*sin(0.1*i));
}

int main()
{ const int N=1000000;
  float C[N];
  // Kernel invocation with N threads 
  VecEval<<<1, N>>>(C);
}

	.text
	.file	"helloworld.hip"
	.globl	_Z22__device_stub__VecEvalPf    # -- Begin function _Z22__device_stub__VecEvalPf
	.type	_Z22__device_stub__VecEvalPf,@function
_Z22__device_stub__VecEvalPf:           # @_Z22__device_stub__VecEvalPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7VecEvalPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__VecEvalPf, .Lfunc_end0-_Z22__device_stub__VecEvalPf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	subq	$4000008, %rsp                  # imm = 0x3D0908
	.cfi_def_cfa_offset 4000016
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	999999(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	%rsp, %rdi
	callq	_Z22__device_stub__VecEvalPf
.LBB1_2:
	xorl	%eax, %eax
	addq	$4000008, %rsp                  # imm = 0x3D0908
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7VecEvalPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7VecEvalPf,@object            # @_Z7VecEvalPf
	.section	.rodata,"a",@progbits
	.globl	_Z7VecEvalPf
	.p2align	3, 0x0
_Z7VecEvalPf:
	.quad	_Z22__device_stub__VecEvalPf
	.size	_Z7VecEvalPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7VecEvalPf"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__VecEvalPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7VecEvalPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7VecEvalPf            ; -- Begin function _Z7VecEvalPf
	.globl	_Z7VecEvalPf
	.p2align	8
	.type	_Z7VecEvalPf,@function
_Z7VecEvalPf:                           ; @_Z7VecEvalPf
; %bb.0:
	v_cvt_f64_i32_e32 v[1:2], v0
	s_mov_b32 s2, 0x9999999a
	s_mov_b32 s3, 0x3fb99999
	s_mov_b32 s18, 0x6dc9c883
	s_mov_b32 s19, 0x3fe45f30
	s_mov_b32 s16, 0x54442d18
	s_mov_b32 s10, 0x33145c00
	s_mov_b32 s17, 0xbff921fb
	s_mov_b32 s11, 0xbc91a626
	s_mov_b32 s9, 0x3ff921fb
	s_mov_b32 s8, s16
	s_mov_b32 s13, 0x3c91a626
	s_mov_b32 s12, s10
	s_mov_b32 s20, 0x252049c0
	s_mov_b32 s14, 0x33145c07
	s_mov_b32 s15, s13
	s_mov_b32 s21, 0xb97b839a
	s_mov_b32 s4, 0xb42fdfa7
	s_mov_b32 s6, 0xf9a43bb8
	s_mov_b32 s5, 0xbe5ae600
	s_mov_b32 s7, 0x3de5e0b2
	s_mov_b32 s24, 0x9037ab78
	s_mov_b32 s26, 0x46cc5e42
	s_mov_b32 s22, 0x796cde01
	s_mov_b32 s25, 0x3e21eeb6
	s_mov_b32 s27, 0xbda907db
	s_mov_b32 s23, 0x3ec71de3
	s_mov_b32 s34, 0xa17f65f6
	s_mov_b32 s28, 0x19e83e5c
	s_mov_b32 s35, 0xbe927e4f
	s_mov_b32 s29, 0xbf2a01a0
	s_mov_b32 s30, 0x11110bb3
	s_mov_b32 s36, 0x19f4ec90
	s_mov_b32 s31, 0x3f811111
	s_mov_b32 s37, 0x3efa01a0
	s_mov_b32 s42, 0x16c16967
	s_mov_b32 s43, 0xbf56c16c
	s_mov_b32 s38, 0x55555555
	v_mul_f64 v[5:6], v[1:2], s[2:3]
	s_mov_b32 s39, 0xbfc55555
	s_mov_b32 s41, 0x3fa55555
	s_mov_b32 s40, s38
	v_add_f64 v[1:2], v[1:2], 1.0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[3:4], |v[5:6]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[5:6]|
	v_trig_preop_f64 v[7:8], |v[5:6]|, 0
	v_and_b32_e32 v9, 0x7fffffff, v6
	v_trig_preop_f64 v[19:20], |v[5:6]|, 2
	v_cndmask_b32_e32 v10, v9, v4, vcc_lo
	v_cndmask_b32_e32 v9, v5, v3, vcc_lo
	v_trig_preop_f64 v[3:4], |v[5:6]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[11:12], v[7:8], v[9:10]
	v_mul_f64 v[13:14], v[3:4], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[7:8], v[9:10], -v[11:12]
	v_fma_f64 v[27:28], v[3:4], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[13:14], v[7:8]
	v_add_f64 v[17:18], v[15:16], -v[13:14]
	v_add_f64 v[23:24], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], -v[17:18]
	v_add_f64 v[3:4], v[7:8], -v[17:18]
	v_add_f64 v[11:12], v[23:24], -v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[13:14], -v[21:22]
	v_ldexp_f64 v[13:14], v[23:24], -2
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[3:4], v[7:8]
	v_fract_f64_e32 v[3:4], v[13:14]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[13:14]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_mul_f64 v[25:26], v[19:20], v[9:10]
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[15:16], v[3:4], 2
	v_mov_b32_e32 v3, 0
	v_add_f64 v[17:18], v[25:26], v[27:28]
	v_fma_f64 v[9:10], v[19:20], v[9:10], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[17:18], v[7:8]
	v_add_f64 v[21:22], v[11:12], v[13:14]
	v_add_f64 v[29:30], v[13:14], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[21:22], v[15:16]
	v_add_f64 v[35:36], v[13:14], -v[29:30]
	v_add_f64 v[7:8], v[7:8], -v[29:30]
	v_add_f64 v[11:12], v[21:22], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[23:24]
	v_add_f64 v[23:24], v[17:18], -v[25:26]
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	v_cndmask_b32_e64 v4, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[17:18], -v[23:24]
	v_add_f64 v[23:24], v[27:28], -v[23:24]
	v_add_f64 v[17:18], v[17:18], -v[35:36]
	v_add_f64 v[15:16], v[15:16], v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[25:26], -v[33:34]
	v_add_f64 v[7:8], v[7:8], v[17:18]
	v_mul_f64 v[17:18], |v[5:6]|, s[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[31:32], v[21:22], v[15:16]
	v_add_f64 v[23:24], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rndne_f64_e32 v[17:18], v[17:18]
	v_cvt_i32_f64_e32 v4, v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[23:24], v[7:8]
	v_fma_f64 v[13:14], v[17:18], s[16:17], |v[5:6]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[29:30], v4
	v_add_f64 v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	v_add_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[21:22], v[15:16]
	v_add_f64 v[9:10], v[19:20], -v[15:16]
	v_mul_f64 v[15:16], v[17:18], s[10:11]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[21:22], -v[9:10]
	v_add_f64 v[11:12], v[13:14], v[15:16]
	v_add_co_ci_u32_e64 v25, s2, 0, v4, vcc_lo
	v_cndmask_b32_e64 v4, 0, 0x3ff00000, vcc_lo
	v_cmp_gt_f64_e64 vcc_lo, 0x41d00000, |v[5:6]|
	v_cmp_class_f64_e64 s2, v[5:6], 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[19:20], -v[3:4]
	v_cvt_i32_f64_e32 v4, v[17:18]
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_fma_f64 v[9:10], v[17:18], s[10:11], v[13:14]
	v_add_f64 v[13:14], v[13:14], -v[11:12]
	v_cndmask_b32_e32 v4, v25, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[19:20], v[7:8]
	v_add_f64 v[11:12], v[11:12], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	v_fma_f64 v[15:16], v[17:18], s[12:13], v[15:16]
	v_mul_f64 v[23:24], v[21:22], s[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[21:22], -v[19:20]
	v_fma_f64 v[19:20], v[21:22], s[8:9], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[21:22], s[14:15], v[19:20]
	v_fma_f64 v[11:12], v[17:18], s[20:21], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[7:8], s[8:9], v[13:14]
	v_add_f64 v[13:14], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[23:24], v[7:8]
	v_add_f64 v[9:10], v[13:14], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, v16, v14, vcc_lo
	v_add_f64 v[9:10], v[11:12], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v15, v13, vcc_lo
	v_add_f64 v[13:14], v[15:16], -v[23:24]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	v_mul_f64 v[19:20], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_fma_f64 v[21:22], v[19:20], s[6:7], s[4:5]
	v_fma_f64 v[15:16], v[19:20], s[26:27], s[24:25]
	v_mul_f64 v[23:24], v[19:20], 0.5
	v_mul_f64 v[9:10], v[17:18], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[22:23]
	v_fma_f64 v[11:12], v[19:20], v[15:16], s[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], -v[23:24], 1.0
	v_fma_f64 v[15:16], v[19:20], v[21:22], s[28:29]
	v_mul_f64 v[21:22], v[7:8], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[11:12], v[19:20], v[11:12], s[36:37]
	v_add_f64 v[25:26], -v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[19:20], v[15:16], s[30:31]
	v_fma_f64 v[11:12], v[19:20], v[11:12], s[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[25:26], -v[23:24]
	v_fma_f64 v[15:16], v[9:10], v[15:16], v[21:22]
	v_mul_f64 v[21:22], v[19:20], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[11:12], v[19:20], v[11:12], s[40:41]
	v_fma_f64 v[23:24], v[17:18], -v[7:8], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[19:20], v[15:16], -v[7:8]
	v_fma_f64 v[11:12], v[21:22], v[11:12], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[9:10], s[38:39], v[7:8]
	v_add_f64 v[9:10], v[13:14], v[11:12]
	v_and_b32_e32 v11, 1, v4
	v_lshlrev_b32_e32 v4, 30, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_xor_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0x80000000, v4
	v_add_f64 v[7:8], v[17:18], -v[7:8]
	v_cndmask_b32_e32 v7, v9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v10, v8, vcc_lo
	v_xor_b32_e32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, 0, v7, s2
	v_cndmask_b32_e64 v5, 0x7ff80000, v5, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[4:5], v[4:5]
	v_and_b32_e32 v4, 0x7fffffff, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_ldexp_f64 v[7:8], |v[5:6]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[5:6]|
	v_trig_preop_f64 v[9:10], |v[5:6]|, 0
	v_trig_preop_f64 v[11:12], |v[5:6]|, 1
	v_trig_preop_f64 v[21:22], |v[5:6]|, 2
	v_dual_cndmask_b32 v8, v4, v8 :: v_dual_cndmask_b32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[13:14], v[9:10], v[7:8]
	v_mul_f64 v[15:16], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[27:28], v[21:22], v[7:8]
	v_fma_f64 v[9:10], v[9:10], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[11:12], v[7:8], -v[15:16]
	v_fma_f64 v[7:8], v[21:22], v[7:8], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[15:16], v[9:10]
	v_add_f64 v[19:20], v[17:18], -v[15:16]
	v_add_f64 v[25:26], v[13:14], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[17:18], -v[19:20]
	v_add_f64 v[9:10], v[9:10], -v[19:20]
	v_ldexp_f64 v[19:20], v[25:26], -2
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	v_add_f64 v[23:24], v[27:28], v[11:12]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[19:20]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[17:18], -v[13:14]
	v_add_f64 v[9:10], v[9:10], v[15:16]
	v_fract_f64_e32 v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[23:24], v[9:10]
	v_dual_cndmask_b32 v16, 0, v16 :: v_dual_cndmask_b32 v15, 0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[15:16], v[15:16], 2
	v_add_f64 v[19:20], v[13:14], v[17:18]
	v_add_f64 v[29:30], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[19:20], v[15:16]
	v_add_f64 v[35:36], v[17:18], -v[29:30]
	v_add_f64 v[9:10], v[9:10], -v[29:30]
	v_add_f64 v[13:14], v[19:20], -v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[25:26]
	v_add_f64 v[25:26], v[23:24], -v[27:28]
	v_add_f64 v[13:14], v[17:18], -v[13:14]
	v_cndmask_b32_e64 v4, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[33:34], v[23:24], -v[25:26]
	v_add_f64 v[11:12], v[11:12], -v[25:26]
	v_add_f64 v[23:24], v[23:24], -v[35:36]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
	v_add_f64 v[15:16], v[15:16], v[3:4]
	v_add_f64 v[25:26], v[27:28], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[9:10], v[23:24]
	v_cndmask_b32_e64 v23, 0, 1, vcc_lo
	v_add_f64 v[31:32], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[25:26]
	v_lshlrev_b32_e32 v25, 8, v23
	v_mul_f64 v[23:24], |v[5:6]|, s[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v4, v[31:32]
	v_ldexp_f64 v[1:2], v[1:2], v25
	v_add_f64 v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f64_e32 v[21:22], v[23:24]
	v_cvt_f64_i32_e32 v[29:30], v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_fma_f64 v[17:18], v[21:22], s[16:17], |v[5:6]|
	v_mul_f64 v[23:24], v[21:22], s[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	v_add_f64 v[7:8], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[19:20], v[15:16]
	v_add_f64 v[9:10], v[11:12], -v[15:16]
	v_rsq_f64_e32 v[15:16], v[1:2]
	v_cmp_le_f64_e64 s2, 0.5, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[19:20], -v[9:10]
	v_add_f64 v[19:20], v[17:18], v[23:24]
	v_add_co_ci_u32_e64 v29, s3, 0, v4, s2
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[13:14], v[1:2], v[15:16]
	v_mul_f64 v[15:16], v[15:16], 0.5
	v_cndmask_b32_e64 v4, 0, 0x3ff00000, s2
	v_cmp_class_f64_e64 s2, v[1:2], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_f64 v[3:4], v[11:12], -v[3:4]
	v_fma_f64 v[11:12], v[21:22], s[10:11], v[17:18]
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	v_fma_f64 v[9:10], -v[15:16], v[13:14], 0.5
	v_add_f64 v[19:20], v[19:20], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[3:4], v[7:8]
	v_add_f64 v[17:18], v[17:18], v[23:24]
	v_fma_f64 v[23:24], v[21:22], s[12:13], v[23:24]
	v_fma_f64 v[13:14], v[13:14], v[9:10], v[13:14]
	v_fma_f64 v[9:10], v[15:16], v[9:10], v[15:16]
	v_mul_f64 v[27:28], v[25:26], s[8:9]
	v_add_f64 v[17:18], v[19:20], v[17:18]
	v_add_f64 v[3:4], v[25:26], -v[3:4]
	v_fma_f64 v[15:16], -v[13:14], v[13:14], v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[25:26], s[8:9], -v[27:28]
	v_add_f64 v[3:4], v[7:8], -v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], v[15:16], v[9:10], v[13:14]
	v_add_f64 v[15:16], v[17:18], -v[23:24]
	v_fma_f64 v[7:8], v[25:26], s[14:15], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], -v[13:14], v[13:14], v[1:2]
	v_fma_f64 v[15:16], v[21:22], s[20:21], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[3:4], s[8:9], v[7:8]
	v_fma_f64 v[7:8], v[17:18], v[9:10], v[13:14]
	v_cndmask_b32_e64 v17, 0, 0xffffff80, vcc_lo
	v_cvt_i32_f64_e32 v18, v[21:22]
	v_add_f64 v[9:10], v[11:12], v[15:16]
	v_cmp_gt_f64_e64 vcc_lo, 0x41d00000, |v[5:6]|
	v_add_f64 v[13:14], v[27:28], v[3:4]
	v_ldexp_f64 v[7:8], v[7:8], v17
	v_cndmask_b32_e32 v31, v29, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_cndmask_b32 v18, v14, v10 :: v_dual_cndmask_b32 v17, v13, v9
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	v_add_f64 v[11:12], v[13:14], -v[27:28]
	v_cndmask_b32_e64 v2, v8, v2, s2
	v_cndmask_b32_e64 v1, v7, v1, s2
	v_mul_f64 v[7:8], v[17:18], v[17:18]
	v_cmp_class_f64_e64 s2, v[5:6], 0x1f8
	s_delay_alu instid0(VALU_DEP_3)
	v_div_scale_f64 v[19:20], null, v[1:2], v[1:2], 1.0
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	v_add_f64 v[3:4], v[3:4], -v[11:12]
	v_fma_f64 v[21:22], v[7:8], s[6:7], s[4:5]
	v_fma_f64 v[13:14], v[7:8], s[26:27], s[24:25]
	v_mul_f64 v[25:26], v[7:8], 0.5
	v_rcp_f64_e32 v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v3, v3, v9
	v_mul_f64 v[9:10], v[17:18], -v[7:8]
	v_fma_f64 v[21:22], v[7:8], v[21:22], s[22:23]
	v_fma_f64 v[11:12], v[7:8], v[13:14], s[34:35]
	v_add_f64 v[13:14], -v[25:26], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0
	v_fma_f64 v[15:16], v[7:8], v[21:22], s[28:29]
	v_fma_f64 v[11:12], v[7:8], v[11:12], s[36:37]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[21:22], v[23:24], v[27:28], v[23:24]
	v_mul_f64 v[23:24], v[3:4], 0.5
	v_add_f64 v[27:28], -v[13:14], 1.0
	v_fma_f64 v[15:16], v[7:8], v[15:16], s[30:31]
	v_fma_f64 v[11:12], v[7:8], v[11:12], s[42:43]
	v_fma_f64 v[29:30], -v[19:20], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[25:26], v[27:28], -v[25:26]
	v_mul_f64 v[27:28], v[7:8], v[7:8]
	v_fma_f64 v[15:16], v[9:10], v[15:16], v[23:24]
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[1:2], 1.0
	v_fma_f64 v[11:12], v[7:8], v[11:12], s[40:41]
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_fma_f64 v[25:26], v[17:18], -v[3:4], v[25:26]
	v_fma_f64 v[3:4], v[7:8], v[15:16], -v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[7:8], v[23:24], v[21:22]
	v_fma_f64 v[11:12], v[27:28], v[11:12], v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[9:10], s[38:39], v[3:4]
	v_fma_f64 v[9:10], -v[19:20], v[7:8], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[13:14], v[11:12]
	v_add_f64 v[3:4], v[17:18], -v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[7:8], v[9:10], v[21:22], v[7:8]
	v_and_b32_e32 v9, 1, v31
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v4, v12, v4 :: v_dual_lshlrev_b32 v5, 30, v31
	v_cndmask_b32_e32 v3, v11, v3, vcc_lo
	v_div_fixup_f64 v[1:2], v[7:8], v[1:2], 1.0
	v_xor_b32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, 0, v3, s2
	v_and_b32_e32 v5, 0x80000000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v5
	v_cndmask_b32_e64 v4, 0x7ff80000, v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], 0x40590000, v[3:4], v[1:2]
	v_cvt_f32_f64_e32 v1, v[1:2]
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7VecEvalPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7VecEvalPf, .Lfunc_end0-_Z7VecEvalPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2956
; NumSgprs: 46
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7VecEvalPf
    .private_segment_fixed_size: 0
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         _Z7VecEvalPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
