/***************************************************************************//**
 * \file intermediatePressure.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the right hand side of the poission equation
 */

#include "intermediatePressure.h"

/**
 * \namespace kernels
 * \brief Contains all the custom-written CUDA kernels.
 */

namespace kernels
{
__global__
void intermediatePressure(double *rhs2, double *uhat, int *ghostTagsP, int *hybridTagsP, int *ghostTagsUV, double *distance_from_u_to_body, double *distance_from_v_to_body, double *ym, double *yp, double *xm, double *xp, double *dx, double *dy, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= nx*ny)
		return;
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= ip % nx,
		J	= ip / nx,
		iu	= (nx-1)*J + I,
		iv	= (nx-1)*ny  +  nx*J +I;

	double temp = 0;

	//Outside immersed body
	if (hybridTagsP[ip] != -1)
	{
		//EAST
		//check if east pressure node is outside of the body
		if (ghostTagsP[ip+1] == -1)
		{
			if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
			{
				temp -= uhat[iu]/distance_from_u_to_body[ip];
			}
			else
				temp -= uhat[iu]/dx[I];
		}

		//WEST
		//check if west pressure node is outside of the body
		if (ghostTagsP[ip-1] == -1)
		{
			if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
			{
				temp += uhat[iu-1]/distance_from_u_to_body[ip];
			}
			else
				temp += uhat[iu-1]/dx[I];
		}

		//NORTH
		//check if north pressure node is outside of the body
		if (ghostTagsP[ip+nx] == -1)
		{
			if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
			{
				temp -= uhat[iv]/distance_from_v_to_body[ip];
			}
			else
				temp -= uhat[iv]/dy[J];
		}

		//SOUTH
		//check if south velocity node is outside of the body
		if (ghostTagsP[ip-nx] == -1)
		{
			if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
			{
				temp += uhat[iv-nx]/distance_from_v_to_body[ip];
			}
			else
				temp += uhat[iv-nx]/dy[J];
		}


	}
	//end outside immersed body
	//if just inside body
	else if (ghostTagsP[ip] > 0)
	{
		//EAST
		if (ghostTagsP[ip+1] == 0)
			temp -= uhat[iu]/dx[I];

		//WEST
		if (ghostTagsP[ip-1] == 0)
			temp += uhat[iu - 1]/dx[I];

		//NORTH
		if (ghostTagsP[ip+nx] == 0)
			temp -= uhat[iv]/dy[J];

		//SOUTH
		if (ghostTagsP[ip-nx] == 0)
			temp += uhat[iv-nx]/dy[J];

	}
	//end just inside body
	//everywhere else
	else
	{
		//EAST
		//if not on the east wall and east is outside the body, add east term
		if (I != nx-1)//not at east boundry
			temp -= uhat[iu]/dx[I];
		else if (I == nx-1)//at east boundry
			temp -= xp[J]/dx[I];

		//WEST
		//if not on west wall and west is outside the body, add west term
		if (I != 0)//not at west boundary
			temp += uhat[iu - 1]/dx[I];
		else if (I == 0)//at the west boundary
			temp += xm[J]/dx[I];

		//NORTH
		//if not on north wall and north is outside the body, add north term
		if (J != ny-1)//not at north boundry
			temp -= uhat[iv]/dy[J];
		else if (J == ny-1)//at north boundry
			temp -= yp[(nx-1)+I]/dy[J];

		//SOUTH
		//if not on south wall and south is outside the body, add south term
		if (J != 0)//not at south boundry
			temp += uhat[iv-nx]/dy[J];
		else if (J == 0)//at south boundry
			temp += ym[(nx-1)+I]/dy[J];

	}//end everywhere else

	rhs2[ip] = temp;
}
}

	.file	"tmpxft_0030be3a_00000000-6_intermediatePressure.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
	.type	_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii, @function
_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movq	320(%rsp), %rax
	movq	%rdi, 104(%rsp)
	leaq	128(%rsp), %rdi
	movq	%rsi, 96(%rsp)
	leaq	140(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	328(%rsp), %rax
	movq	%rdx, 88(%rsp)
	leaq	112(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	336(%rsp), %rax
	movq	%rcx, 80(%rsp)
	leaq	120(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	344(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 32(%rsp)
	movq	352(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	360(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	368(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	104(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 128(%rsp)
	movl	$1, 136(%rsp)
	movq	%rax, 140(%rsp)
	movl	$1, 148(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	120(%rsp)
	.cfi_def_cfa_offset 328
	leaq	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii(%rip), %rdi
	pushq	120(%rsp)
	.cfi_def_cfa_offset 336
	movq	156(%rsp), %rcx
	movl	164(%rsp), %r8d
	movq	144(%rsp), %rsi
	movl	152(%rsp), %edx
	leaq	192(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L2:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii, .-_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
	.globl	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.type	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, @function
_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z87__device_stub__ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_iiPdS_PiS0_S0_S_S_S_S_S_S_S_S_ii
	.cfi_endproc
.LFE2033:
	.size	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, .-_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/***************************************************************************//**
 * \file intermediatePressure.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the right hand side of the poission equation
 */


#include <hip/hip_runtime.h>
#include "intermediatePressure.h"

/**
 * \namespace kernels
 * \brief Contains all the custom-written CUDA kernels.
 */

namespace kernels
{
__global__
void intermediatePressure(double *rhs2, double *uhat, int *ghostTagsP, int *hybridTagsP, int *ghostTagsUV, double *distance_from_u_to_body, double *distance_from_v_to_body, double *ym, double *yp, double *xm, double *xp, double *dx, double *dy, int nx, int ny)
{
	if (threadIdx.x + blockDim.x * blockIdx.x >= nx*ny)
		return;
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x,
		I	= ip % nx,
		J	= ip / nx,
		iu	= (nx-1)*J + I,
		iv	= (nx-1)*ny  +  nx*J +I;

	double temp = 0;

	//Outside immersed body
	if (hybridTagsP[ip] != -1)
	{
		//EAST
		//check if east pressure node is outside of the body
		if (ghostTagsP[ip+1] == -1)
		{
			if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
			{
				temp -= uhat[iu]/distance_from_u_to_body[ip];
			}
			else
				temp -= uhat[iu]/dx[I];
		}

		//WEST
		//check if west pressure node is outside of the body
		if (ghostTagsP[ip-1] == -1)
		{
			if (distance_from_u_to_body[ip] > dx[I]/2 && distance_from_u_to_body[ip] < dx[I])
			{
				temp += uhat[iu-1]/distance_from_u_to_body[ip];
			}
			else
				temp += uhat[iu-1]/dx[I];
		}

		//NORTH
		//check if north pressure node is outside of the body
		if (ghostTagsP[ip+nx] == -1)
		{
			if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
			{
				temp -= uhat[iv]/distance_from_v_to_body[ip];
			}
			else
				temp -= uhat[iv]/dy[J];
		}

		//SOUTH
		//check if south velocity node is outside of the body
		if (ghostTagsP[ip-nx] == -1)
		{
			if (distance_from_v_to_body[ip] > dy[J]/2 && distance_from_v_to_body[ip] < dy[J])
			{
				temp += uhat[iv-nx]/distance_from_v_to_body[ip];
			}
			else
				temp += uhat[iv-nx]/dy[J];
		}


	}
	//end outside immersed body
	//if just inside body
	else if (ghostTagsP[ip] > 0)
	{
		//EAST
		if (ghostTagsP[ip+1] == 0)
			temp -= uhat[iu]/dx[I];

		//WEST
		if (ghostTagsP[ip-1] == 0)
			temp += uhat[iu - 1]/dx[I];

		//NORTH
		if (ghostTagsP[ip+nx] == 0)
			temp -= uhat[iv]/dy[J];

		//SOUTH
		if (ghostTagsP[ip-nx] == 0)
			temp += uhat[iv-nx]/dy[J];

	}
	//end just inside body
	//everywhere else
	else
	{
		//EAST
		//if not on the east wall and east is outside the body, add east term
		if (I != nx-1)//not at east boundry
			temp -= uhat[iu]/dx[I];
		else if (I == nx-1)//at east boundry
			temp -= xp[J]/dx[I];

		//WEST
		//if not on west wall and west is outside the body, add west term
		if (I != 0)//not at west boundary
			temp += uhat[iu - 1]/dx[I];
		else if (I == 0)//at the west boundary
			temp += xm[J]/dx[I];

		//NORTH
		//if not on north wall and north is outside the body, add north term
		if (J != ny-1)//not at north boundry
			temp -= uhat[iv]/dy[J];
		else if (J == ny-1)//at north boundry
			temp -= yp[(nx-1)+I]/dy[J];

		//SOUTH
		//if not on south wall and south is outside the body, add south term
		if (J != 0)//not at south boundry
			temp += uhat[iv-nx]/dy[J];
		else if (J == 0)//at south boundry
			temp += ym[(nx-1)+I]/dy[J];

	}//end everywhere else

	rhs2[ip] = temp;
}
}

	.text
	.file	"intermediatePressure.hip"
	.globl	_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii # -- Begin function _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.type	_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii,@function
_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii: # @_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, .Lfunc_end0-_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii,@object # @_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.section	.rodata,"a",@progbits
	.globl	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.p2align	3, 0x0
_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii:
	.quad	_ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.size	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii"
	.size	.L__unnamed_1, 74

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN7kernels35__device_stub__intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii ; -- Begin function _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.globl	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
	.p2align	8
	.type	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii,@function
_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii: ; @_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x7c
	s_load_b64 s[2:3], s[0:1], 0x68
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s28, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s28, v1
	s_cbranch_execz .LBB0_54
; %bb.1:
	s_load_b256 s[20:27], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_nc_u32_e32 v5, v1, v2
	v_xor_b32_e32 v5, v5, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s26, v6
	v_add_co_ci_u32_e32 v4, vcc_lo, s27, v7, vcc_lo
	s_ashr_i32 s27, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s2, s27
	global_load_b32 v0, v[3:4], off
	s_xor_b32 s4, s4, s27
	v_cvt_f32_u32_e32 v3, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s5, v3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_hi_u32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s4
	v_sub_nc_u32_e32 v4, v5, v4
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_dual_cndmask_b32 v4, v4, v8 :: v_dual_cndmask_b32 v3, v3, v5
	v_xor_b32_e32 v8, s27, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_add_nc_u32_e32 v5, 1, v3
	s_load_b512 s[4:19], s[0:1], 0x28
	s_sub_i32 s0, s28, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_xor_b32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v3, v8
	v_mul_lo_u32 v3, v5, s2
	v_sub_nc_u32_e32 v13, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v1, v3
	v_add3_u32 v3, v9, s0, v3
	v_add_co_u32 v11, s0, s24, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s0, s25, v7, s0
                                        ; implicit-def: $vgpr7_vgpr8
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v0
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_27
; %bb.2:
	global_load_b32 v0, v[11:12], off offset:4
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	s_mov_b32 s26, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 -1, v0
	s_cbranch_execz .LBB0_8
; %bb.3:
	v_ashrrev_i32_e32 v10, 31, v9
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[9:10]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s16, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v7, vcc_lo
	global_load_b64 v[19:20], v[6:7], off
	v_lshlrev_b64 v[6:7], 3, v[1:2]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[15:16], v[6:7], off
	v_lshlrev_b64 v[6:7], 3, v[13:14]
	v_add_co_u32 v6, vcc_lo, s22, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s23, v7, vcc_lo
	global_load_b64 v[17:18], v[6:7], off
	s_waitcnt vmcnt(2)
	v_mul_f64 v[6:7], v[19:20], 0.5
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f64_e64 s0, v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f64_e32 vcc_lo, v[15:16], v[6:7]
                                        ; implicit-def: $vgpr7_vgpr8
	s_or_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s28, s0
	s_xor_b32 s0, exec_lo, s28
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[6:7], null, v[19:20], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[6:7], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[21:22], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[6:7], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[21:22], v[14:15]
	v_div_scale_f64 v[21:22], vcc_lo, v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[23:24], v[21:22], v[14:15]
	v_fma_f64 v[6:7], -v[6:7], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[23:24]
                                        ; implicit-def: $vgpr15_vgpr16
	v_div_fixup_f64 v[6:7], v[6:7], v[19:20], v[17:18]
                                        ; implicit-def: $vgpr17_vgpr18
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], -v[6:7], 0
.LBB0_5:                                ; %Flow278
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[6:7], null, v[15:16], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[19:20], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[6:7], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[6:7], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_div_scale_f64 v[21:22], vcc_lo, v[17:18], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[23:24], v[21:22], v[19:20]
	v_fma_f64 v[6:7], -v[6:7], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[19:20], v[23:24]
	v_div_fixup_f64 v[6:7], v[6:7], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], -v[6:7], 0
.LBB0_7:                                ; %Flow279
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_8:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s26
	global_load_b32 v0, v[11:12], off offset:-4
	s_mov_b32 s26, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 -1, v0
	s_cbranch_execz .LBB0_14
; %bb.9:
	v_ashrrev_i32_e32 v10, 31, v9
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_lshlrev_b64 v[13:14], 3, v[13:14]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s16, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v10, vcc_lo
	global_load_b64 v[15:16], v[9:10], off
	v_lshlrev_b64 v[9:10], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s22, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v14, vcc_lo
	global_load_b64 v[9:10], v[9:10], off
	global_load_b64 v[13:14], v[13:14], off offset:-8
	s_waitcnt vmcnt(2)
	v_mul_f64 v[17:18], v[15:16], 0.5
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f64_e64 s0, v[9:10], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f64_e32 vcc_lo, v[9:10], v[17:18]
	s_or_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s0
	s_xor_b32 s0, exec_lo, s4
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[9:10], null, v[15:16], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[17:18], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[9:10], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[9:10], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_div_scale_f64 v[19:20], vcc_lo, v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[19:20], v[17:18]
	v_fma_f64 v[9:10], -v[9:10], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[9:10], v[9:10], v[17:18], v[21:22]
	v_div_fixup_f64 v[9:10], v[9:10], v[15:16], v[13:14]
                                        ; implicit-def: $vgpr13_vgpr14
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[9:10]
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_11:                               ; %Flow276
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_13
; %bb.12:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[15:16], null, v[9:10], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_div_scale_f64 v[19:20], vcc_lo, v[13:14], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[19:20], v[17:18]
	v_fma_f64 v[15:16], -v[15:16], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[21:22]
	v_div_fixup_f64 v[9:10], v[15:16], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[9:10]
.LBB0_13:                               ; %Flow277
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_14:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s26
	s_mov_b32 s26, s2
	s_waitcnt lgkmcnt(0)
	s_lshl_b64 s[4:5], s[26:27], 2
	v_add_co_u32 v9, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
	s_mov_b32 s4, exec_lo
	global_load_b32 v0, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 -1, v0
	s_cbranch_execz .LBB0_20
; %bb.15:
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 3, v[5:6]
	v_lshlrev_b64 v[11:12], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s18, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v10, vcc_lo
	global_load_b64 v[13:14], v[9:10], off
	v_lshlrev_b64 v[9:10], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s22, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s23, v12, vcc_lo
	global_load_b64 v[9:10], v[9:10], off
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(2)
	v_mul_f64 v[15:16], v[13:14], 0.5
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f64_e64 s0, v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f64_e32 vcc_lo, v[9:10], v[15:16]
	s_or_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s5, s0
	s_xor_b32 s0, exec_lo, s5
	s_cbranch_execz .LBB0_17
; %bb.16:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[9:10], null, v[13:14], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[9:10], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[9:10], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	v_fma_f64 v[9:10], -v[9:10], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[9:10], v[9:10], v[15:16], v[19:20]
	v_div_fixup_f64 v[9:10], v[9:10], v[13:14], v[11:12]
                                        ; implicit-def: $vgpr11_vgpr12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_17:                               ; %Flow274
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_19
; %bb.18:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
	v_div_fixup_f64 v[9:10], v[13:14], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
.LBB0_19:                               ; %Flow275
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_20:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_subrev_nc_u32_e32 v9, s2, v1
	s_mov_b32 s4, exec_lo
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s24, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s25, v10, vcc_lo
	global_load_b32 v0, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 -1, v0
	s_cbranch_execz .LBB0_26
; %bb.21:
	v_ashrrev_i32_e32 v6, 31, v5
	v_subrev_nc_u32_e32 v9, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[5:6]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v4, vcc_lo, s18, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s19, v5, vcc_lo
	global_load_b64 v[11:12], v[4:5], off
	v_lshlrev_b64 v[4:5], 3, v[1:2]
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v9, vcc_lo, s22, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v10, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	global_load_b64 v[9:10], v[9:10], off
	s_waitcnt vmcnt(2)
	v_mul_f64 v[13:14], v[11:12], 0.5
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f64_e64 s0, v[4:5], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f64_e32 vcc_lo, v[4:5], v[13:14]
	s_or_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s5, s0
	s_xor_b32 s0, exec_lo, s5
	s_cbranch_execz .LBB0_23
; %bb.22:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[3:4], null, v[11:12], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[5:6], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[3:4], v[5:6], 1.0
	v_fma_f64 v[5:6], v[5:6], v[13:14], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[3:4], v[5:6], 1.0
	v_fma_f64 v[5:6], v[5:6], v[13:14], v[5:6]
	v_div_scale_f64 v[13:14], vcc_lo, v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[13:14], v[5:6]
	v_fma_f64 v[3:4], -v[3:4], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[15:16]
	v_div_fixup_f64 v[3:4], v[3:4], v[11:12], v[9:10]
                                        ; implicit-def: $vgpr9_vgpr10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[3:4]
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_23:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_25
; %bb.24:
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[11:12], null, v[4:5], v[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_div_scale_f64 v[15:16], vcc_lo, v[9:10], v[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[15:16], v[13:14]
	v_fma_f64 v[11:12], -v[11:12], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[17:18]
	v_div_fixup_f64 v[3:4], v[11:12], v[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[3:4]
.LBB0_25:                               ; %Flow272
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_26:                               ; %Flow273
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr13
.LBB0_27:                               ; %Flow287
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_53
; %bb.28:
	global_load_b32 v0, v[11:12], off
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v10, 31, v9
                                        ; implicit-def: $vgpr7_vgpr8
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e32 1, v0
	s_waitcnt lgkmcnt(0)
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.29:
	s_add_i32 s0, s2, -1
	v_mov_b32_e32 v4, s14
	v_cmp_eq_u32_e32 vcc_lo, s0, v9
	v_lshlrev_b64 v[11:12], 3, v[9:10]
	v_mov_b32_e32 v0, s15
	s_mov_b32 s0, exec_lo
	v_cndmask_b32_e32 v6, v13, v5, vcc_lo
	v_cndmask_b32_e32 v4, s22, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, s23, v0, vcc_lo
	v_add_co_u32 v11, vcc_lo, s16, v11
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v14, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, v0, v7, vcc_lo
	global_load_b64 v[7:8], v[11:12], off
	global_load_b64 v[11:12], v[14:15], off
                                        ; implicit-def: $vgpr15_vgpr16
	v_cmpx_ne_u32_e32 0, v9
	s_xor_b32 s0, exec_lo, s0
; %bb.30:
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 3, v[13:14]
	v_add_co_u32 v0, vcc_lo, s22, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s23, v14, vcc_lo
	v_add_co_u32 v15, vcc_lo, v0, -8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, -1, v4, vcc_lo
; %bb.31:                               ; %Flow283
	s_or_saveexec_b32 s0, s0
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_33
; %bb.32:
	s_load_b64 s[6:7], s[16:17], 0x0
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 3, v[5:6]
	v_add_co_u32 v15, vcc_lo, s12, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v14, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v13, s6
.LBB0_33:
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b64 v[15:16], v[15:16], off
	s_add_i32 s0, s3, -1
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $vgpr17_vgpr18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s0, v5
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_35
; %bb.34:
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[17:18], 3, v[3:4]
	v_lshlrev_b64 v[19:20], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, s22, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s23, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s18, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v20, vcc_lo
	global_load_b64 v[21:22], v[17:18], off
	global_load_b64 v[17:18], v[19:20], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[19:20], null, v[17:18], v[17:18], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[23:24], v[19:20]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[19:20], v[23:24], 1.0
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], -v[19:20], v[23:24], 1.0
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_div_scale_f64 v[25:26], vcc_lo, v[21:22], v[17:18], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[27:28], v[25:26], v[23:24]
	v_fma_f64 v[19:20], -v[19:20], v[27:28], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[19:20], v[19:20], v[23:24], v[27:28]
	v_div_fixup_f64 v[19:20], v[19:20], v[17:18], v[21:22]
.LBB0_35:                               ; %Flow282
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_37
; %bb.36:
	v_add_co_u32 v17, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v18, vcc_lo, s27, v10, vcc_lo
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[17:18], 3, v[17:18]
	v_lshlrev_b64 v[19:20], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, s10, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s11, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, s18, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v20, vcc_lo
	global_load_b64 v[21:22], v[17:18], off offset:-8
	global_load_b64 v[17:18], v[19:20], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[19:20], null, v[17:18], v[17:18], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[23:24], v[19:20]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[19:20], v[23:24], 1.0
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], -v[19:20], v[23:24], 1.0
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_div_scale_f64 v[25:26], vcc_lo, v[21:22], v[17:18], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[27:28], v[25:26], v[23:24]
	v_fma_f64 v[19:20], -v[19:20], v[27:28], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[19:20], v[19:20], v[23:24], v[27:28]
	v_div_fixup_f64 v[19:20], v[19:20], v[17:18], v[21:22]
.LBB0_37:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[21:22], null, v[7:8], v[7:8], v[11:12]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[25:26], null, v[13:14], v[13:14], v[15:16]
	v_div_scale_f64 v[35:36], s0, v[15:16], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[23:24], v[21:22]
	v_rcp_f64_e32 v[29:30], v[25:26]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[21:22], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[27:28], -v[25:26], v[29:30], 1.0
	v_fma_f64 v[31:32], -v[21:22], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[27:28], v[29:30], v[27:28], v[29:30]
	v_div_scale_f64 v[29:30], vcc_lo, v[11:12], v[7:8], v[11:12]
	v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[31:32], -v[25:26], v[27:28], 1.0
	v_mul_f64 v[33:34], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[27:28], v[31:32], v[27:28]
	v_fma_f64 v[21:22], -v[21:22], v[33:34], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[29:30], v[35:36], v[27:28]
	v_div_fmas_f64 v[21:22], v[21:22], v[23:24], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], -v[25:26], v[29:30], v[35:36]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, exec_lo
	v_div_fixup_f64 v[6:7], v[21:22], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[11:12], v[23:24], v[27:28], v[29:30]
	v_add_f64 v[6:7], -v[6:7], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[11:12], v[11:12], v[13:14], v[15:16]
	v_add_f64 v[6:7], v[6:7], v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[11:12], v[6:7], -v[19:20]
                                        ; implicit-def: $vgpr7_vgpr8
	v_cmpx_ne_u32_e32 0, v5
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_39
; %bb.38:
	v_subrev_nc_u32_e32 v3, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s23, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[5:6], null, v[17:18], v[17:18], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_div_scale_f64 v[9:10], vcc_lo, v[3:4], v[17:18], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[9:10], v[7:8]
	v_fma_f64 v[5:6], -v[5:6], v[13:14], v[9:10]
                                        ; implicit-def: $vgpr9_vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[13:14]
	v_div_fixup_f64 v[3:4], v[5:6], v[17:18], v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[11:12], v[3:4]
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_39:                               ; %Flow280
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_41
; %bb.40:
	v_add_co_u32 v3, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s27, v10, vcc_lo
	s_load_b64 s[6:7], s[18:19], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_add_co_u32 v3, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off offset:-8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f64 v[5:6], null, s[6:7], s[6:7], v[3:4]
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_div_scale_f64 v[9:10], vcc_lo, v[3:4], s[6:7], v[3:4]
	v_mul_f64 v[13:14], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], -v[5:6], v[13:14], v[9:10]
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[5:6], s[6:7], v[3:4]
	v_add_f64 v[7:8], v[11:12], v[3:4]
.LBB0_41:                               ; %Flow281
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr13
.LBB0_42:                               ; %Flow285
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_52
; %bb.43:
	global_load_b32 v0, v[11:12], off offset:4
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	v_ashrrev_i32_e32 v14, 31, v13
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_45
; %bb.44:
	v_lshlrev_b64 v[6:7], 3, v[13:14]
	v_lshlrev_b64 v[15:16], 3, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s22, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s23, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s16, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s17, v16, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	global_load_b64 v[15:16], v[15:16], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[17:18], null, v[15:16], v[15:16], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_div_scale_f64 v[21:22], vcc_lo, v[6:7], v[15:16], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[23:24], v[21:22], v[19:20]
	v_fma_f64 v[17:18], -v[17:18], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[23:24]
	v_div_fixup_f64 v[6:7], v[17:18], v[15:16], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], -v[6:7], 0
.LBB0_45:
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v0, v[11:12], off offset:-4
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_47
; %bb.46:
	v_lshlrev_b64 v[13:14], 3, v[13:14]
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, s22, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s16, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v10, vcc_lo
	global_load_b64 v[13:14], v[13:14], off offset:-8
	global_load_b64 v[9:10], v[9:10], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[15:16], null, v[9:10], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_div_scale_f64 v[19:20], vcc_lo, v[13:14], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[19:20], v[17:18]
	v_fma_f64 v[15:16], -v[15:16], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[21:22]
	v_div_fixup_f64 v[9:10], v[15:16], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[9:10]
.LBB0_47:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, s27
	v_ashrrev_i32_e32 v6, 31, v5
	s_lshl_b64 s[4:5], s[2:3], 2
	s_mov_b32 s3, exec_lo
	v_add_co_u32 v9, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
	global_load_b32 v0, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_49
; %bb.48:
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[9:10], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 3, v[3:4]
	v_add_co_u32 v9, vcc_lo, s18, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, s22, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v12, vcc_lo, s23, v12, vcc_lo
	global_load_b64 v[9:10], v[9:10], off
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[11:12]
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[9:10], v[11:12]
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[9:10], v[13:14], v[9:10], v[11:12]
	v_add_f64 v[7:8], v[7:8], -v[9:10]
.LBB0_49:
	s_or_b32 exec_lo, exec_lo, s3
	v_subrev_nc_u32_e32 v9, s2, v1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s24, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s25, v10, vcc_lo
	global_load_b32 v0, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_51
; %bb.50:
	v_subrev_nc_u32_e32 v3, s2, v3
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v5, vcc_lo, s18, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s23, v4, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[9:10], null, v[5:6], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_div_scale_f64 v[13:14], vcc_lo, v[3:4], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[13:14], v[11:12]
	v_fma_f64 v[9:10], -v[9:10], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[15:16]
	v_div_fixup_f64 v[3:4], v[9:10], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[3:4]
.LBB0_51:                               ; %Flow284
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_52:                               ; %Flow286
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_53:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v0, vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	global_store_b64 v[0:1], v[7:8], off
.LBB0_54:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 368
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 29
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii, .Lfunc_end0-_ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4536
; NumSgprs: 31
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 31
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .offset:         108
        .size:           4
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         116
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         124
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         126
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         128
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         130
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         132
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         134
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         176
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 368
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     31
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels20intermediatePressureEPdS0_PiS1_S1_S0_S0_S0_S0_S0_S0_S0_S0_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
