#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>

using namespace std::chrono;

template<unsigned int blockSize>
__device__ void warpReduce(volatile float *sdata, int tid) {
    if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
    if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
    if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
    if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
    if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
    if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}

template<unsigned int blockSize>
__global__ void reduce6(float *g_idata, float *g_odata) {
    extern __shared__ float sdata[];

    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
    sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
    __syncthreads();
    for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
        if (blockSize >= 512) {
            if (tid < 256) { sdata[tid] += sdata[tid + 256]; }
            __syncthreads();
        }
        if (blockSize >= 256) {
            if (tid < 128) { sdata[tid] += sdata[tid + 128]; }
            __syncthreads();
        }
        if (blockSize >= 128) {
            if (tid < 64) { sdata[tid] += sdata[tid + 64]; }
            __syncthreads();
        }
        if (tid < 32)warpReduce<blockSize>(sdata, tid);
    }
}

int main(void) {
    int N = 100000000;
    float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
    g_indata_host = (float *) malloc(N * sizeof(float));
    g_outdata_host = (float *) malloc(sizeof(float));

    cudaMalloc(&g_indata_device, N * sizeof(float));
    cudaMalloc(&g_outdata_device, sizeof(float));

    for (auto i = 0; i < N; i++) {
        g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
    }

    cudaMemcpy(g_indata_device, g_indata_host, N * sizeof(float), cudaMemcpyHostToDevice);

//    This is where the code is run
    auto dimGrid = 512;
    auto dimBlock = 512;
    auto smemSize = 128 * sizeof(float);
    auto threads = 512;
    auto start = high_resolution_clock::now();
    switch (threads) {
        case 512:
            reduce6<512><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 256:
            reduce6<256><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 128:
            reduce6<128><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 64:
            reduce6<64><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 32:
            reduce6<32><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 16:
            reduce6<16><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 8:
            reduce6<8><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 4:
            reduce6<4><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 2:
            reduce6<2><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 1:
            reduce6<1><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
    }

    auto stop = high_resolution_clock::now();
    auto duration = duration_cast<microseconds>(stop - start);
    std::cout << "Time taken by function: "
              << duration.count() << " microseconds" << std::endl;
    cudaFree(g_indata_device);
    cudaFree(g_outdata_device);
    free(g_indata_host);
    free(g_outdata_host);

}
	.file	"tmpxft_00396540_00000000-6_main.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3743:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3743:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.text._Z7reduce6ILj1EEvPfS0_,"axG",@progbits,_Z7reduce6ILj1EEvPfS0_,comdat
	.weak	_Z7reduce6ILj1EEvPfS0_
	.type	_Z7reduce6ILj1EEvPfS0_, @function
_Z7reduce6ILj1EEvPfS0_:
.LFB4123:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj1EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4123:
	.size	_Z7reduce6ILj1EEvPfS0_, .-_Z7reduce6ILj1EEvPfS0_
	.text
	.type	_ZL38__device_stub__Z7reduce6ILj512EEvPfS0_PfS_, @function
_ZL38__device_stub__Z7reduce6ILj512EEvPfS0_PfS_:
.LFB3765:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj512EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L7:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3765:
	.size	_ZL38__device_stub__Z7reduce6ILj512EEvPfS0_PfS_, .-_ZL38__device_stub__Z7reduce6ILj512EEvPfS0_PfS_
	.section	.text._Z7reduce6ILj512EEvPfS0_,"axG",@progbits,_Z7reduce6ILj512EEvPfS0_,comdat
	.weak	_Z7reduce6ILj512EEvPfS0_
	.type	_Z7reduce6ILj512EEvPfS0_, @function
_Z7reduce6ILj512EEvPfS0_:
.LFB4114:
	.cfi_startproc
	endbr64
	jmp	_ZL38__device_stub__Z7reduce6ILj512EEvPfS0_PfS_
	.cfi_endproc
.LFE4114:
	.size	_Z7reduce6ILj512EEvPfS0_, .-_Z7reduce6ILj512EEvPfS0_
	.section	.text._Z7reduce6ILj256EEvPfS0_,"axG",@progbits,_Z7reduce6ILj256EEvPfS0_,comdat
	.weak	_Z7reduce6ILj256EEvPfS0_
	.type	_Z7reduce6ILj256EEvPfS0_, @function
_Z7reduce6ILj256EEvPfS0_:
.LFB4115:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj256EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L12:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4115:
	.size	_Z7reduce6ILj256EEvPfS0_, .-_Z7reduce6ILj256EEvPfS0_
	.section	.text._Z7reduce6ILj128EEvPfS0_,"axG",@progbits,_Z7reduce6ILj128EEvPfS0_,comdat
	.weak	_Z7reduce6ILj128EEvPfS0_
	.type	_Z7reduce6ILj128EEvPfS0_, @function
_Z7reduce6ILj128EEvPfS0_:
.LFB4116:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj128EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L16:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4116:
	.size	_Z7reduce6ILj128EEvPfS0_, .-_Z7reduce6ILj128EEvPfS0_
	.section	.text._Z7reduce6ILj64EEvPfS0_,"axG",@progbits,_Z7reduce6ILj64EEvPfS0_,comdat
	.weak	_Z7reduce6ILj64EEvPfS0_
	.type	_Z7reduce6ILj64EEvPfS0_, @function
_Z7reduce6ILj64EEvPfS0_:
.LFB4117:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj64EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L20:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4117:
	.size	_Z7reduce6ILj64EEvPfS0_, .-_Z7reduce6ILj64EEvPfS0_
	.section	.text._Z7reduce6ILj32EEvPfS0_,"axG",@progbits,_Z7reduce6ILj32EEvPfS0_,comdat
	.weak	_Z7reduce6ILj32EEvPfS0_
	.type	_Z7reduce6ILj32EEvPfS0_, @function
_Z7reduce6ILj32EEvPfS0_:
.LFB4118:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj32EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L24:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4118:
	.size	_Z7reduce6ILj32EEvPfS0_, .-_Z7reduce6ILj32EEvPfS0_
	.section	.text._Z7reduce6ILj16EEvPfS0_,"axG",@progbits,_Z7reduce6ILj16EEvPfS0_,comdat
	.weak	_Z7reduce6ILj16EEvPfS0_
	.type	_Z7reduce6ILj16EEvPfS0_, @function
_Z7reduce6ILj16EEvPfS0_:
.LFB4119:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj16EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L28:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4119:
	.size	_Z7reduce6ILj16EEvPfS0_, .-_Z7reduce6ILj16EEvPfS0_
	.section	.text._Z7reduce6ILj8EEvPfS0_,"axG",@progbits,_Z7reduce6ILj8EEvPfS0_,comdat
	.weak	_Z7reduce6ILj8EEvPfS0_
	.type	_Z7reduce6ILj8EEvPfS0_, @function
_Z7reduce6ILj8EEvPfS0_:
.LFB4120:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj8EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L32:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4120:
	.size	_Z7reduce6ILj8EEvPfS0_, .-_Z7reduce6ILj8EEvPfS0_
	.section	.text._Z7reduce6ILj4EEvPfS0_,"axG",@progbits,_Z7reduce6ILj4EEvPfS0_,comdat
	.weak	_Z7reduce6ILj4EEvPfS0_
	.type	_Z7reduce6ILj4EEvPfS0_, @function
_Z7reduce6ILj4EEvPfS0_:
.LFB4121:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj4EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L36:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4121:
	.size	_Z7reduce6ILj4EEvPfS0_, .-_Z7reduce6ILj4EEvPfS0_
	.section	.text._Z7reduce6ILj2EEvPfS0_,"axG",@progbits,_Z7reduce6ILj2EEvPfS0_,comdat
	.weak	_Z7reduce6ILj2EEvPfS0_
	.type	_Z7reduce6ILj2EEvPfS0_, @function
_Z7reduce6ILj2EEvPfS0_:
.LFB4122:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6ILj2EEvPfS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L40:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4122:
	.size	_Z7reduce6ILj2EEvPfS0_, .-_Z7reduce6ILj2EEvPfS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Time taken by function: "
.LC2:
	.string	" microseconds"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3737:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$400000000, %edi
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movq	%rsp, %rdi
	movl	$400000000, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
.L45:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	$100000000, %rbp
	jne	.L45
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$400000000, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	movl	$512, %r8d
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rax, %rbp
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_ZL38__device_stub__Z7reduce6ILj512EEvPfS0_PfS_
.L46:
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movl	$1000, %ecx
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	subq	%rbp, %rax
	cqto
	idivq	%rcx
	movq	%rax, %rbp
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3737:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z7reduce6ILj1EEvPfS0_"
.LC4:
	.string	"_Z7reduce6ILj2EEvPfS0_"
.LC5:
	.string	"_Z7reduce6ILj4EEvPfS0_"
.LC6:
	.string	"_Z7reduce6ILj8EEvPfS0_"
.LC7:
	.string	"_Z7reduce6ILj16EEvPfS0_"
.LC8:
	.string	"_Z7reduce6ILj32EEvPfS0_"
.LC9:
	.string	"_Z7reduce6ILj64EEvPfS0_"
.LC10:
	.string	"_Z7reduce6ILj128EEvPfS0_"
.LC11:
	.string	"_Z7reduce6ILj256EEvPfS0_"
.LC12:
	.string	"_Z7reduce6ILj512EEvPfS0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3786:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7reduce6ILj1EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6ILj2EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6ILj4EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6ILj8EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6ILj16EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6ILj32EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6ILj64EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6ILj128EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC11(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6ILj256EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce6ILj512EEvPfS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3786:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>

using namespace std::chrono;

template<unsigned int blockSize>
__device__ void warpReduce(volatile float *sdata, int tid) {
    if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
    if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
    if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
    if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
    if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
    if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}

template<unsigned int blockSize>
__global__ void reduce6(float *g_idata, float *g_odata) {
    extern __shared__ float sdata[];

    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
    sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
    __syncthreads();
    for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
        if (blockSize >= 512) {
            if (tid < 256) { sdata[tid] += sdata[tid + 256]; }
            __syncthreads();
        }
        if (blockSize >= 256) {
            if (tid < 128) { sdata[tid] += sdata[tid + 128]; }
            __syncthreads();
        }
        if (blockSize >= 128) {
            if (tid < 64) { sdata[tid] += sdata[tid + 64]; }
            __syncthreads();
        }
        if (tid < 32)warpReduce<blockSize>(sdata, tid);
    }
}

int main(void) {
    int N = 100000000;
    float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
    g_indata_host = (float *) malloc(N * sizeof(float));
    g_outdata_host = (float *) malloc(sizeof(float));

    hipMalloc(&g_indata_device, N * sizeof(float));
    hipMalloc(&g_outdata_device, sizeof(float));

    for (auto i = 0; i < N; i++) {
        g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
    }

    hipMemcpy(g_indata_device, g_indata_host, N * sizeof(float), hipMemcpyHostToDevice);

//    This is where the code is run
    auto dimGrid = 512;
    auto dimBlock = 512;
    auto smemSize = 128 * sizeof(float);
    auto threads = 512;
    auto start = high_resolution_clock::now();
    switch (threads) {
        case 512:
            reduce6<512><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 256:
            reduce6<256><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 128:
            reduce6<128><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 64:
            reduce6<64><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 32:
            reduce6<32><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 16:
            reduce6<16><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 8:
            reduce6<8><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 4:
            reduce6<4><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 2:
            reduce6<2><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
        case 1:
            reduce6<1><<<dimGrid, dimBlock, smemSize>>>(g_indata_device, g_outdata_device);
            break;
    }

    auto stop = high_resolution_clock::now();
    auto duration = duration_cast<microseconds>(stop - start);
    std::cout << "Time taken by function: "
              << duration.count() << " microseconds" << std::endl;
    hipFree(g_indata_device);
    hipFree(g_outdata_device);
    free(g_indata_host);
    free(g_outdata_host);

}
	.text
	.file	"main.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI0_0:
	.long	0x30000000                      # float 4.65661287E-10
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$400000000, %edi                # imm = 0x17D78400
	callq	malloc
	movq	%rax, %rbx
	leaq	8(%rsp), %rdi
	movl	$400000000, %esi                # imm = 0x17D78400
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	xorl	%r14d, %r14d
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI0_0(%rip), %xmm0
	movss	%xmm0, (%rbx,%r14,4)
	incq	%r14
	cmpq	$100000000, %r14                # imm = 0x5F5E100
	jne	.LBB0_1
# %bb.2:
	movq	8(%rsp), %rdi
	movl	$400000000, %edx                # imm = 0x17D78400
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %r14
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	movl	$512, %r8d                      # imm = 0x200
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z22__device_stub__reduce6ILj512EEvPfS0_
.LBB0_4:
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	subq	%r14, %rax
	movabsq	$2361183241434822607, %rcx      # imm = 0x20C49BA5E353F7CF
	imulq	%rcx
	movq	%rdx, %r14
	shrq	$63, %r14
	sarq	$7, %rdx
	addq	%rdx, %r14
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$24, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%r14, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %r14
	movl	$.L.str.1, %esi
	movl	$13, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj512EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj512EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj512EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj512EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj512EEvPfS0_,@function
_Z22__device_stub__reduce6ILj512EEvPfS0_: # @_Z22__device_stub__reduce6ILj512EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj512EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__reduce6ILj512EEvPfS0_, .Lfunc_end1-_Z22__device_stub__reduce6ILj512EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj256EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj256EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj256EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj256EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj256EEvPfS0_,@function
_Z22__device_stub__reduce6ILj256EEvPfS0_: # @_Z22__device_stub__reduce6ILj256EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj256EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__reduce6ILj256EEvPfS0_, .Lfunc_end2-_Z22__device_stub__reduce6ILj256EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj128EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj128EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj128EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj128EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj128EEvPfS0_,@function
_Z22__device_stub__reduce6ILj128EEvPfS0_: # @_Z22__device_stub__reduce6ILj128EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj128EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__reduce6ILj128EEvPfS0_, .Lfunc_end3-_Z22__device_stub__reduce6ILj128EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj64EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj64EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj64EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj64EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj64EEvPfS0_,@function
_Z22__device_stub__reduce6ILj64EEvPfS0_: # @_Z22__device_stub__reduce6ILj64EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj64EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z22__device_stub__reduce6ILj64EEvPfS0_, .Lfunc_end4-_Z22__device_stub__reduce6ILj64EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj32EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj32EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj32EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj32EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj32EEvPfS0_,@function
_Z22__device_stub__reduce6ILj32EEvPfS0_: # @_Z22__device_stub__reduce6ILj32EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj32EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22__device_stub__reduce6ILj32EEvPfS0_, .Lfunc_end5-_Z22__device_stub__reduce6ILj32EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj16EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj16EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj16EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj16EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj16EEvPfS0_,@function
_Z22__device_stub__reduce6ILj16EEvPfS0_: # @_Z22__device_stub__reduce6ILj16EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj16EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z22__device_stub__reduce6ILj16EEvPfS0_, .Lfunc_end6-_Z22__device_stub__reduce6ILj16EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj8EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj8EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj8EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj8EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj8EEvPfS0_,@function
_Z22__device_stub__reduce6ILj8EEvPfS0_: # @_Z22__device_stub__reduce6ILj8EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj8EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z22__device_stub__reduce6ILj8EEvPfS0_, .Lfunc_end7-_Z22__device_stub__reduce6ILj8EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj4EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj4EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj4EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj4EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj4EEvPfS0_,@function
_Z22__device_stub__reduce6ILj4EEvPfS0_: # @_Z22__device_stub__reduce6ILj4EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj4EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z22__device_stub__reduce6ILj4EEvPfS0_, .Lfunc_end8-_Z22__device_stub__reduce6ILj4EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj2EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj2EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj2EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj2EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj2EEvPfS0_,@function
_Z22__device_stub__reduce6ILj2EEvPfS0_: # @_Z22__device_stub__reduce6ILj2EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj2EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z22__device_stub__reduce6ILj2EEvPfS0_, .Lfunc_end9-_Z22__device_stub__reduce6ILj2EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6ILj1EEvPfS0_,"axG",@progbits,_Z22__device_stub__reduce6ILj1EEvPfS0_,comdat
	.weak	_Z22__device_stub__reduce6ILj1EEvPfS0_ # -- Begin function _Z22__device_stub__reduce6ILj1EEvPfS0_
	.type	_Z22__device_stub__reduce6ILj1EEvPfS0_,@function
_Z22__device_stub__reduce6ILj1EEvPfS0_: # @_Z22__device_stub__reduce6ILj1EEvPfS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6ILj1EEvPfS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z22__device_stub__reduce6ILj1EEvPfS0_, .Lfunc_end10-_Z22__device_stub__reduce6ILj1EEvPfS0_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB11_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB11_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj512EEvPfS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj256EEvPfS0_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj128EEvPfS0_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj64EEvPfS0_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj32EEvPfS0_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj16EEvPfS0_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj8EEvPfS0_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj4EEvPfS0_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj2EEvPfS0_, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6ILj1EEvPfS0_, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end11:
	.size	__hip_module_ctor, .Lfunc_end11-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB12_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB12_2:
	retq
.Lfunc_end12:
	.size	__hip_module_dtor, .Lfunc_end12-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7reduce6ILj512EEvPfS0_,@object # @_Z7reduce6ILj512EEvPfS0_
	.section	.rodata._Z7reduce6ILj512EEvPfS0_,"aG",@progbits,_Z7reduce6ILj512EEvPfS0_,comdat
	.weak	_Z7reduce6ILj512EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj512EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj512EEvPfS0_
	.size	_Z7reduce6ILj512EEvPfS0_, 8

	.type	_Z7reduce6ILj256EEvPfS0_,@object # @_Z7reduce6ILj256EEvPfS0_
	.section	.rodata._Z7reduce6ILj256EEvPfS0_,"aG",@progbits,_Z7reduce6ILj256EEvPfS0_,comdat
	.weak	_Z7reduce6ILj256EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj256EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj256EEvPfS0_
	.size	_Z7reduce6ILj256EEvPfS0_, 8

	.type	_Z7reduce6ILj128EEvPfS0_,@object # @_Z7reduce6ILj128EEvPfS0_
	.section	.rodata._Z7reduce6ILj128EEvPfS0_,"aG",@progbits,_Z7reduce6ILj128EEvPfS0_,comdat
	.weak	_Z7reduce6ILj128EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj128EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj128EEvPfS0_
	.size	_Z7reduce6ILj128EEvPfS0_, 8

	.type	_Z7reduce6ILj64EEvPfS0_,@object # @_Z7reduce6ILj64EEvPfS0_
	.section	.rodata._Z7reduce6ILj64EEvPfS0_,"aG",@progbits,_Z7reduce6ILj64EEvPfS0_,comdat
	.weak	_Z7reduce6ILj64EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj64EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj64EEvPfS0_
	.size	_Z7reduce6ILj64EEvPfS0_, 8

	.type	_Z7reduce6ILj32EEvPfS0_,@object # @_Z7reduce6ILj32EEvPfS0_
	.section	.rodata._Z7reduce6ILj32EEvPfS0_,"aG",@progbits,_Z7reduce6ILj32EEvPfS0_,comdat
	.weak	_Z7reduce6ILj32EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj32EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj32EEvPfS0_
	.size	_Z7reduce6ILj32EEvPfS0_, 8

	.type	_Z7reduce6ILj16EEvPfS0_,@object # @_Z7reduce6ILj16EEvPfS0_
	.section	.rodata._Z7reduce6ILj16EEvPfS0_,"aG",@progbits,_Z7reduce6ILj16EEvPfS0_,comdat
	.weak	_Z7reduce6ILj16EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj16EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj16EEvPfS0_
	.size	_Z7reduce6ILj16EEvPfS0_, 8

	.type	_Z7reduce6ILj8EEvPfS0_,@object  # @_Z7reduce6ILj8EEvPfS0_
	.section	.rodata._Z7reduce6ILj8EEvPfS0_,"aG",@progbits,_Z7reduce6ILj8EEvPfS0_,comdat
	.weak	_Z7reduce6ILj8EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj8EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj8EEvPfS0_
	.size	_Z7reduce6ILj8EEvPfS0_, 8

	.type	_Z7reduce6ILj4EEvPfS0_,@object  # @_Z7reduce6ILj4EEvPfS0_
	.section	.rodata._Z7reduce6ILj4EEvPfS0_,"aG",@progbits,_Z7reduce6ILj4EEvPfS0_,comdat
	.weak	_Z7reduce6ILj4EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj4EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj4EEvPfS0_
	.size	_Z7reduce6ILj4EEvPfS0_, 8

	.type	_Z7reduce6ILj2EEvPfS0_,@object  # @_Z7reduce6ILj2EEvPfS0_
	.section	.rodata._Z7reduce6ILj2EEvPfS0_,"aG",@progbits,_Z7reduce6ILj2EEvPfS0_,comdat
	.weak	_Z7reduce6ILj2EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj2EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj2EEvPfS0_
	.size	_Z7reduce6ILj2EEvPfS0_, 8

	.type	_Z7reduce6ILj1EEvPfS0_,@object  # @_Z7reduce6ILj1EEvPfS0_
	.section	.rodata._Z7reduce6ILj1EEvPfS0_,"aG",@progbits,_Z7reduce6ILj1EEvPfS0_,comdat
	.weak	_Z7reduce6ILj1EEvPfS0_
	.p2align	3, 0x0
_Z7reduce6ILj1EEvPfS0_:
	.quad	_Z22__device_stub__reduce6ILj1EEvPfS0_
	.size	_Z7reduce6ILj1EEvPfS0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Time taken by function: "
	.size	.L.str, 25

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" microseconds"
	.size	.L.str.1, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7reduce6ILj512EEvPfS0_"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7reduce6ILj256EEvPfS0_"
	.size	.L__unnamed_2, 25

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7reduce6ILj128EEvPfS0_"
	.size	.L__unnamed_3, 25

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7reduce6ILj64EEvPfS0_"
	.size	.L__unnamed_4, 24

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z7reduce6ILj32EEvPfS0_"
	.size	.L__unnamed_5, 24

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z7reduce6ILj16EEvPfS0_"
	.size	.L__unnamed_6, 24

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z7reduce6ILj8EEvPfS0_"
	.size	.L__unnamed_7, 23

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z7reduce6ILj4EEvPfS0_"
	.size	.L__unnamed_8, 23

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z7reduce6ILj2EEvPfS0_"
	.size	.L__unnamed_9, 23

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z7reduce6ILj1EEvPfS0_"
	.size	.L__unnamed_10, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__reduce6ILj512EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj256EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj128EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj64EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj32EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj16EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj8EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj4EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj2EEvPfS0_
	.addrsig_sym _Z22__device_stub__reduce6ILj1EEvPfS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7reduce6ILj512EEvPfS0_
	.addrsig_sym _Z7reduce6ILj256EEvPfS0_
	.addrsig_sym _Z7reduce6ILj128EEvPfS0_
	.addrsig_sym _Z7reduce6ILj64EEvPfS0_
	.addrsig_sym _Z7reduce6ILj32EEvPfS0_
	.addrsig_sym _Z7reduce6ILj16EEvPfS0_
	.addrsig_sym _Z7reduce6ILj8EEvPfS0_
	.addrsig_sym _Z7reduce6ILj4EEvPfS0_
	.addrsig_sym _Z7reduce6ILj2EEvPfS0_
	.addrsig_sym _Z7reduce6ILj1EEvPfS0_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z7reduce6ILj512EEvPfS0_,"axG",@progbits,_Z7reduce6ILj512EEvPfS0_,comdat
	.protected	_Z7reduce6ILj512EEvPfS0_ ; -- Begin function _Z7reduce6ILj512EEvPfS0_
	.globl	_Z7reduce6ILj512EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj512EEvPfS0_,@function
_Z7reduce6ILj512EEvPfS0_:               ; @_Z7reduce6ILj512EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v14, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s6
	s_cmpk_lt_u32 s6, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v14, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_11
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v1, 0x80, v14
	v_add_nc_u32_e32 v4, 64, v14
	s_mov_b64 s[8:9], src_shared_base
	v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
	v_cmp_gt_u32_e64 s0, 0x80, v0
	v_cmp_ne_u32_e64 s3, -1, v1
	v_cmp_gt_u32_e64 s1, 64, v0
	v_cmp_gt_u32_e64 s2, 32, v0
	v_add_nc_u32_e32 v6, 32, v14
	v_cmp_ne_u32_e64 s4, -1, v14
	v_cndmask_b32_e64 v0, 0, v1, s3
	v_cndmask_b32_e64 v1, 0, s9, s3
	v_cmp_ne_u32_e64 s3, -1, v4
	v_add_nc_u32_e32 v8, 16, v14
	v_add_nc_u32_e32 v10, 8, v14
	v_add_nc_u32_e32 v12, 4, v14
	v_cndmask_b32_e64 v3, 0, s9, s4
	v_cndmask_b32_e64 v4, 0, v4, s3
	v_cndmask_b32_e64 v5, 0, s9, s3
	v_cmp_ne_u32_e64 s3, -1, v6
	v_cndmask_b32_e64 v2, 0, v14, s4
	v_cmp_ne_u32_e64 s4, -1, v8
	v_cmp_ne_u32_e64 s5, -1, v12
	v_add_nc_u32_e32 v15, 0x400, v14
	v_cndmask_b32_e64 v6, 0, v6, s3
	v_cndmask_b32_e64 v7, 0, s9, s3
	v_cmp_ne_u32_e64 s3, -1, v10
	v_add_nc_u32_e32 v16, 0x200, v14
	v_add_nc_u32_e32 v17, 0x100, v14
	v_cndmask_b32_e64 v8, 0, v8, s4
	v_cndmask_b32_e64 v9, 0, s9, s4
	v_cndmask_b32_e64 v10, 0, v10, s3
	v_cndmask_b32_e64 v11, 0, s9, s3
	v_cndmask_b32_e64 v12, 0, v12, s5
	v_cndmask_b32_e64 v13, 0, s9, s5
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v18, v15
	ds_load_b32 v19, v14
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	ds_store_b32 v14, v18
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v18, v16
	ds_load_b32 v19, v14
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	ds_store_b32 v14, v18
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v18, v17
	ds_load_b32 v19, v14
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	ds_store_b32 v14, v18
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	flat_load_b32 v18, v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v19, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	flat_store_b32 v[2:3], v18 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v18, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v19, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	flat_store_b32 v[2:3], v18 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v18, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v19, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	flat_store_b32 v[2:3], v18 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v18, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v19, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	flat_store_b32 v[2:3], v18 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v18, v[10:11] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v19, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	flat_store_b32 v[2:3], v18 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v18, v[12:13] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v19, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v18, v18, v19
	flat_store_b32 v[2:3], v18 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_10:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_lshr_b32 s3, s6, 1
	s_cmpk_lt_u32 s6, 0x84
	s_mov_b32 s6, s3
	s_cbranch_scc0 .LBB0_2
.LBB0_11:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj512EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj512EEvPfS0_,"axG",@progbits,_Z7reduce6ILj512EEvPfS0_,comdat
.Lfunc_end0:
	.size	_Z7reduce6ILj512EEvPfS0_, .Lfunc_end0-_Z7reduce6ILj512EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 892
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj256EEvPfS0_,"axG",@progbits,_Z7reduce6ILj256EEvPfS0_,comdat
	.protected	_Z7reduce6ILj256EEvPfS0_ ; -- Begin function _Z7reduce6ILj256EEvPfS0_
	.globl	_Z7reduce6ILj256EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj256EEvPfS0_,@function
_Z7reduce6ILj256EEvPfS0_:               ; @_Z7reduce6ILj256EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v14, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s5
	s_cmpk_lt_u32 s5, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v14, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_9
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v1, 0x80, v14
	v_add_nc_u32_e32 v4, 64, v14
	s_mov_b64 s[6:7], src_shared_base
	v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
	v_cmp_gt_u32_e64 s0, 64, v0
	v_cmp_ne_u32_e64 s2, -1, v1
	v_cmp_gt_u32_e64 s1, 32, v0
	v_add_nc_u32_e32 v6, 32, v14
	v_cmp_ne_u32_e64 s3, -1, v14
	v_add_nc_u32_e32 v8, 16, v14
	v_cndmask_b32_e64 v0, 0, v1, s2
	v_cndmask_b32_e64 v1, 0, s7, s2
	v_cmp_ne_u32_e64 s2, -1, v4
	v_add_nc_u32_e32 v10, 8, v14
	v_add_nc_u32_e32 v12, 4, v14
	v_cndmask_b32_e64 v3, 0, s7, s3
	v_cndmask_b32_e64 v2, 0, v14, s3
	v_cndmask_b32_e64 v4, 0, v4, s2
	v_cndmask_b32_e64 v5, 0, s7, s2
	v_cmp_ne_u32_e64 s2, -1, v6
	v_cmp_ne_u32_e64 s3, -1, v8
	v_cmp_ne_u32_e64 s4, -1, v12
	v_add_nc_u32_e32 v15, 0x200, v14
	v_add_nc_u32_e32 v16, 0x100, v14
	v_cndmask_b32_e64 v6, 0, v6, s2
	v_cndmask_b32_e64 v7, 0, s7, s2
	v_cmp_ne_u32_e64 s2, -1, v10
	v_cndmask_b32_e64 v8, 0, v8, s3
	v_cndmask_b32_e64 v9, 0, s7, s3
	v_cndmask_b32_e64 v12, 0, v12, s4
	v_cndmask_b32_e64 v13, 0, s7, s4
	v_cndmask_b32_e64 v10, 0, v10, s2
	v_cndmask_b32_e64 v11, 0, s7, s2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	ds_load_b32 v17, v15
	ds_load_b32 v18, v14
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	ds_store_b32 v14, v17
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	ds_load_b32 v17, v16
	ds_load_b32 v18, v14
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	ds_store_b32 v14, v17
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_2 Depth=1
	flat_load_b32 v17, v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v18, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	flat_store_b32 v[2:3], v17 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v17, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v18, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	flat_store_b32 v[2:3], v17 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v17, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v18, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	flat_store_b32 v[2:3], v17 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v17, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v18, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	flat_store_b32 v[2:3], v17 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v17, v[10:11] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v18, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	flat_store_b32 v[2:3], v17 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v17, v[12:13] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v18, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v17, v17, v18
	flat_store_b32 v[2:3], v17 dlc
	s_waitcnt_vscnt null, 0x0
.LBB1_8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_lshr_b32 s2, s5, 1
	s_cmpk_lt_u32 s5, 0x84
	s_mov_b32 s5, s2
	s_cbranch_scc0 .LBB1_2
.LBB1_9:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj256EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj256EEvPfS0_,"axG",@progbits,_Z7reduce6ILj256EEvPfS0_,comdat
.Lfunc_end1:
	.size	_Z7reduce6ILj256EEvPfS0_, .Lfunc_end1-_Z7reduce6ILj256EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 812
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj128EEvPfS0_,"axG",@progbits,_Z7reduce6ILj128EEvPfS0_,comdat
	.protected	_Z7reduce6ILj128EEvPfS0_ ; -- Begin function _Z7reduce6ILj128EEvPfS0_
	.globl	_Z7reduce6ILj128EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj128EEvPfS0_,@function
_Z7reduce6ILj128EEvPfS0_:               ; @_Z7reduce6ILj128EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v14, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s4
	s_cmpk_lt_u32 s4, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v14, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_7
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v1, 0x80, v14
	v_add_nc_u32_e32 v4, 64, v14
	s_mov_b64 s[6:7], src_shared_base
	v_cmp_gt_u32_e32 vcc_lo, 64, v0
	v_lshlrev_b32_e32 v2, 2, v0
	v_cmp_ne_u32_e64 s1, -1, v1
	v_cmp_gt_u32_e64 s0, 32, v0
	v_add_nc_u32_e32 v6, 32, v14
	v_cmp_ne_u32_e64 s2, -1, v14
	v_add_nc_u32_e32 v8, 16, v14
	v_cndmask_b32_e64 v0, 0, v1, s1
	v_cndmask_b32_e64 v1, 0, s7, s1
	v_cmp_ne_u32_e64 s1, -1, v4
	v_add_nc_u32_e32 v10, 8, v14
	v_add_nc_u32_e32 v12, 4, v14
	v_add3_u32 v15, 0, v2, 0x100
	v_cndmask_b32_e64 v3, 0, s7, s2
	v_cndmask_b32_e64 v4, 0, v4, s1
	v_cndmask_b32_e64 v5, 0, s7, s1
	v_cmp_ne_u32_e64 s1, -1, v6
	v_cndmask_b32_e64 v2, 0, v14, s2
	v_cmp_ne_u32_e64 s2, -1, v8
	v_cmp_ne_u32_e64 s3, -1, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v6, 0, v6, s1
	v_cndmask_b32_e64 v7, 0, s7, s1
	v_cmp_ne_u32_e64 s1, -1, v10
	v_cndmask_b32_e64 v8, 0, v8, s2
	v_cndmask_b32_e64 v9, 0, s7, s2
	v_cndmask_b32_e64 v12, 0, v12, s3
	v_cndmask_b32_e64 v13, 0, s7, s3
	v_cndmask_b32_e64 v10, 0, v10, s1
	v_cndmask_b32_e64 v11, 0, s7, s1
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	ds_load_b32 v16, v15
	ds_load_b32 v17, v14
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v16, v16, v17
	ds_store_b32 v14, v16
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_2 Depth=1
	flat_load_b32 v16, v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v16, v16, v17
	flat_store_b32 v[2:3], v16 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v16, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v16, v16, v17
	flat_store_b32 v[2:3], v16 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v16, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v16, v16, v17
	flat_store_b32 v[2:3], v16 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v16, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v16, v16, v17
	flat_store_b32 v[2:3], v16 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v16, v[10:11] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v16, v16, v17
	flat_store_b32 v[2:3], v16 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v16, v[12:13] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v17, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v16, v16, v17
	flat_store_b32 v[2:3], v16 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_6:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s4, 1
	s_cmpk_lt_u32 s4, 0x84
	s_mov_b32 s4, s1
	s_cbranch_scc0 .LBB2_2
.LBB2_7:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj128EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj128EEvPfS0_,"axG",@progbits,_Z7reduce6ILj128EEvPfS0_,comdat
.Lfunc_end2:
	.size	_Z7reduce6ILj128EEvPfS0_, .Lfunc_end2-_Z7reduce6ILj128EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 744
; NumSgprs: 18
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj64EEvPfS0_,"axG",@progbits,_Z7reduce6ILj64EEvPfS0_,comdat
	.protected	_Z7reduce6ILj64EEvPfS0_ ; -- Begin function _Z7reduce6ILj64EEvPfS0_
	.globl	_Z7reduce6ILj64EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj64EEvPfS0_,@function
_Z7reduce6ILj64EEvPfS0_:                ; @_Z7reduce6ILj64EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v7, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s3
	s_cmpk_lt_u32 s3, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v7, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_5
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, 0x80, v7
	v_add_nc_u32_e32 v4, 64, v7
	v_add_nc_u32_e32 v6, 32, v7
	s_mov_b64 s[4:5], src_shared_base
	v_cmp_ne_u32_e64 s1, -1, v7
	v_cmp_ne_u32_e64 s0, -1, v2
	v_cmp_ne_u32_e64 s2, -1, v4
	v_add_nc_u32_e32 v8, 16, v7
	v_add_nc_u32_e32 v10, 8, v7
	v_add_nc_u32_e32 v12, 4, v7
	v_cndmask_b32_e64 v2, 0, v2, s0
	v_cndmask_b32_e64 v3, 0, s5, s0
	v_cmp_ne_u32_e64 s0, -1, v6
	v_cmp_gt_u32_e32 vcc_lo, 32, v0
	v_cndmask_b32_e64 v1, 0, s5, s1
	v_cndmask_b32_e64 v0, 0, v7, s1
	v_cndmask_b32_e64 v4, 0, v4, s2
	v_cndmask_b32_e64 v5, 0, s5, s2
	v_cndmask_b32_e64 v6, 0, v6, s0
	v_cmp_ne_u32_e64 s1, -1, v8
	v_cndmask_b32_e64 v7, 0, s5, s0
	v_cmp_ne_u32_e64 s0, -1, v10
	v_cmp_ne_u32_e64 s2, -1, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, 0, v8, s1
	v_cndmask_b32_e64 v9, 0, s5, s1
	v_cndmask_b32_e64 v10, 0, v10, s0
	v_cndmask_b32_e64 v11, 0, s5, s0
	v_cndmask_b32_e64 v12, 0, v12, s2
	v_cndmask_b32_e64 v13, 0, s5, s2
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	flat_load_b32 v14, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v14, v14, v15
	flat_store_b32 v[0:1], v14 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v14, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v14, v14, v15
	flat_store_b32 v[0:1], v14 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v14, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v14, v14, v15
	flat_store_b32 v[0:1], v14 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v14, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v14, v14, v15
	flat_store_b32 v[0:1], v14 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v14, v[10:11] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v14, v14, v15
	flat_store_b32 v[0:1], v14 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v14, v[12:13] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v15, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v14, v14, v15
	flat_store_b32 v[0:1], v14 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_4:                                ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_lshr_b32 s0, s3, 1
	s_cmpk_lt_u32 s3, 0x84
	s_mov_b32 s3, s0
	s_cbranch_scc0 .LBB3_2
.LBB3_5:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj64EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj64EEvPfS0_,"axG",@progbits,_Z7reduce6ILj64EEvPfS0_,comdat
.Lfunc_end3:
	.size	_Z7reduce6ILj64EEvPfS0_, .Lfunc_end3-_Z7reduce6ILj64EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 656
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj32EEvPfS0_,"axG",@progbits,_Z7reduce6ILj32EEvPfS0_,comdat
	.protected	_Z7reduce6ILj32EEvPfS0_ ; -- Begin function _Z7reduce6ILj32EEvPfS0_
	.globl	_Z7reduce6ILj32EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj32EEvPfS0_,@function
_Z7reduce6ILj32EEvPfS0_:                ; @_Z7reduce6ILj32EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_add_u32 v5, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s3
	s_cmpk_lt_u32 s3, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v5, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB4_5
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, 64, v5
	v_add_nc_u32_e32 v4, 32, v5
	v_cmp_ne_u32_e64 s0, -1, v5
	s_mov_b64 s[4:5], src_shared_base
	v_cmp_gt_u32_e32 vcc_lo, 32, v0
	v_cmp_ne_u32_e64 s1, -1, v2
	v_add_nc_u32_e32 v6, 16, v5
	v_cndmask_b32_e64 v1, 0, s5, s0
	v_cndmask_b32_e64 v0, 0, v5, s0
	v_cmp_ne_u32_e64 s0, -1, v4
	v_add_nc_u32_e32 v8, 8, v5
	v_add_nc_u32_e32 v10, 4, v5
	v_cndmask_b32_e64 v2, 0, v2, s1
	v_cndmask_b32_e64 v3, 0, s5, s1
	v_cndmask_b32_e64 v4, 0, v4, s0
	v_cmp_ne_u32_e64 s1, -1, v6
	v_cndmask_b32_e64 v5, 0, s5, s0
	v_cmp_ne_u32_e64 s0, -1, v8
	v_cmp_ne_u32_e64 s2, -1, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, 0, v6, s1
	v_cndmask_b32_e64 v7, 0, s5, s1
	v_cndmask_b32_e64 v8, 0, v8, s0
	v_cndmask_b32_e64 v9, 0, s5, s0
	v_cndmask_b32_e64 v10, 0, v10, s2
	v_cndmask_b32_e64 v11, 0, s5, s2
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	flat_load_b32 v12, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v13, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v12, v12, v13
	flat_store_b32 v[0:1], v12 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v12, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v13, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v12, v12, v13
	flat_store_b32 v[0:1], v12 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v12, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v13, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v12, v12, v13
	flat_store_b32 v[0:1], v12 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v12, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v13, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v12, v12, v13
	flat_store_b32 v[0:1], v12 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v12, v[10:11] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v13, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v12, v12, v13
	flat_store_b32 v[0:1], v12 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_lshr_b32 s0, s3, 1
	s_cmpk_lt_u32 s3, 0x84
	s_mov_b32 s3, s0
	s_cbranch_scc0 .LBB4_2
.LBB4_5:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj32EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj32EEvPfS0_,"axG",@progbits,_Z7reduce6ILj32EEvPfS0_,comdat
.Lfunc_end4:
	.size	_Z7reduce6ILj32EEvPfS0_, .Lfunc_end4-_Z7reduce6ILj32EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj16EEvPfS0_,"axG",@progbits,_Z7reduce6ILj16EEvPfS0_,comdat
	.protected	_Z7reduce6ILj16EEvPfS0_ ; -- Begin function _Z7reduce6ILj16EEvPfS0_
	.globl	_Z7reduce6ILj16EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj16EEvPfS0_,@function
_Z7reduce6ILj16EEvPfS0_:                ; @_Z7reduce6ILj16EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s3
	s_cmpk_lt_u32 s3, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB5_5
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, 32, v4
	v_add_nc_u32_e32 v5, 16, v4
	v_add_nc_u32_e32 v6, 8, v4
	v_add_nc_u32_e32 v8, 4, v4
	v_cmp_ne_u32_e64 s1, -1, v4
	v_cmp_ne_u32_e64 s0, -1, v2
	s_mov_b64 s[4:5], src_shared_base
	v_cmp_gt_u32_e32 vcc_lo, 32, v0
	v_cmp_ne_u32_e64 s2, -1, v8
	v_cndmask_b32_e64 v1, 0, s5, s1
	v_cndmask_b32_e64 v2, 0, v2, s0
	v_cndmask_b32_e64 v3, 0, s5, s0
	v_cmp_ne_u32_e64 s0, -1, v5
	v_cndmask_b32_e64 v0, 0, v4, s1
	v_cmp_ne_u32_e64 s1, -1, v6
	v_cndmask_b32_e64 v8, 0, v8, s2
	v_cndmask_b32_e64 v9, 0, s5, s2
	v_cndmask_b32_e64 v4, 0, v5, s0
	v_cndmask_b32_e64 v5, 0, s5, s0
	v_cndmask_b32_e64 v6, 0, v6, s1
	v_cndmask_b32_e64 v7, 0, s5, s1
.LBB5_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB5_4
; %bb.3:                                ;   in Loop: Header=BB5_2 Depth=1
	flat_load_b32 v10, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v11, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v10, v10, v11
	flat_store_b32 v[0:1], v10 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v10, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v11, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v10, v10, v11
	flat_store_b32 v[0:1], v10 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v10, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v11, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v10, v10, v11
	flat_store_b32 v[0:1], v10 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v10, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v11, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v10, v10, v11
	flat_store_b32 v[0:1], v10 dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_4:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_lshr_b32 s0, s3, 1
	s_cmpk_lt_u32 s3, 0x84
	s_mov_b32 s3, s0
	s_cbranch_scc0 .LBB5_2
.LBB5_5:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj16EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj16EEvPfS0_,"axG",@progbits,_Z7reduce6ILj16EEvPfS0_,comdat
.Lfunc_end5:
	.size	_Z7reduce6ILj16EEvPfS0_, .Lfunc_end5-_Z7reduce6ILj16EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj8EEvPfS0_,"axG",@progbits,_Z7reduce6ILj8EEvPfS0_,comdat
	.protected	_Z7reduce6ILj8EEvPfS0_  ; -- Begin function _Z7reduce6ILj8EEvPfS0_
	.globl	_Z7reduce6ILj8EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj8EEvPfS0_,@function
_Z7reduce6ILj8EEvPfS0_:                 ; @_Z7reduce6ILj8EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s3
	s_cmpk_lt_u32 s3, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	v_lshl_add_u32 v4, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_5
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, 16, v4
	v_add_nc_u32_e32 v5, 8, v4
	v_add_nc_u32_e32 v6, 4, v4
	s_mov_b64 s[4:5], src_shared_base
	v_cmp_ne_u32_e64 s1, -1, v4
	v_cmp_ne_u32_e64 s0, -1, v2
	v_cmp_ne_u32_e64 s2, -1, v5
	v_cmp_gt_u32_e32 vcc_lo, 32, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v1, 0, s5, s1
	v_cndmask_b32_e64 v2, 0, v2, s0
	v_cndmask_b32_e64 v3, 0, s5, s0
	v_cmp_ne_u32_e64 s0, -1, v6
	v_cndmask_b32_e64 v0, 0, v4, s1
	v_cndmask_b32_e64 v4, 0, v5, s2
	v_cndmask_b32_e64 v5, 0, s5, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v6, 0, v6, s0
	v_cndmask_b32_e64 v7, 0, s5, s0
.LBB6_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB6_4
; %bb.3:                                ;   in Loop: Header=BB6_2 Depth=1
	flat_load_b32 v8, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v9, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v8, v8, v9
	flat_store_b32 v[0:1], v8 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v8, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v9, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v8, v8, v9
	flat_store_b32 v[0:1], v8 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v8, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v9, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v8, v8, v9
	flat_store_b32 v[0:1], v8 dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_4:                                ;   in Loop: Header=BB6_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_lshr_b32 s0, s3, 1
	s_cmpk_lt_u32 s3, 0x84
	s_mov_b32 s3, s0
	s_cbranch_scc0 .LBB6_2
.LBB6_5:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj8EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj8EEvPfS0_,"axG",@progbits,_Z7reduce6ILj8EEvPfS0_,comdat
.Lfunc_end6:
	.size	_Z7reduce6ILj8EEvPfS0_, .Lfunc_end6-_Z7reduce6ILj8EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 452
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj4EEvPfS0_,"axG",@progbits,_Z7reduce6ILj4EEvPfS0_,comdat
	.protected	_Z7reduce6ILj4EEvPfS0_  ; -- Begin function _Z7reduce6ILj4EEvPfS0_
	.globl	_Z7reduce6ILj4EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj4EEvPfS0_,@function
_Z7reduce6ILj4EEvPfS0_:                 ; @_Z7reduce6ILj4EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s3
	s_cmpk_lt_u32 s3, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[3:4], off
	global_load_b32 v1, v[1:2], off
	v_lshl_add_u32 v3, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v4, v1
	ds_store_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB7_5
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, 8, v3
	v_add_nc_u32_e32 v4, 4, v3
	v_cmp_ne_u32_e64 s0, -1, v3
	s_mov_b64 s[4:5], src_shared_base
	v_cmp_gt_u32_e32 vcc_lo, 32, v0
	v_cmp_ne_u32_e64 s1, -1, v2
	v_cmp_ne_u32_e64 s2, -1, v4
	v_cndmask_b32_e64 v1, 0, s5, s0
	v_cndmask_b32_e64 v0, 0, v3, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v2, 0, v2, s1
	v_cndmask_b32_e64 v3, 0, s5, s1
	v_cndmask_b32_e64 v4, 0, v4, s2
	v_cndmask_b32_e64 v5, 0, s5, s2
.LBB7_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB7_4
; %bb.3:                                ;   in Loop: Header=BB7_2 Depth=1
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v7, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	flat_store_b32 v[0:1], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v6, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v7, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	flat_store_b32 v[0:1], v6 dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_4:                                ;   in Loop: Header=BB7_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_lshr_b32 s0, s3, 1
	s_cmpk_lt_u32 s3, 0x84
	s_mov_b32 s3, s0
	s_cbranch_scc0 .LBB7_2
.LBB7_5:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj4EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj4EEvPfS0_,"axG",@progbits,_Z7reduce6ILj4EEvPfS0_,comdat
.Lfunc_end7:
	.size	_Z7reduce6ILj4EEvPfS0_, .Lfunc_end7-_Z7reduce6ILj4EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 380
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj2EEvPfS0_,"axG",@progbits,_Z7reduce6ILj2EEvPfS0_,comdat
	.protected	_Z7reduce6ILj2EEvPfS0_  ; -- Begin function _Z7reduce6ILj2EEvPfS0_
	.globl	_Z7reduce6ILj2EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj2EEvPfS0_,@function
_Z7reduce6ILj2EEvPfS0_:                 ; @_Z7reduce6ILj2EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s2
	s_cmpk_lt_u32 s2, 0x42
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	v_lshl_add_u32 v2, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB8_5
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v3, 4, v2
	v_cmp_ne_u32_e64 s0, -1, v2
	s_mov_b64 s[4:5], src_shared_base
	v_cmp_gt_u32_e32 vcc_lo, 32, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s1, -1, v3
	v_cndmask_b32_e64 v1, 0, s5, s0
	v_cndmask_b32_e64 v0, 0, v2, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v2, 0, v3, s1
	v_cndmask_b32_e64 v3, 0, s5, s1
.LBB8_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB8_4
; %bb.3:                                ;   in Loop: Header=BB8_2 Depth=1
	flat_load_b32 v4, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v4, v4, v5
	flat_store_b32 v[0:1], v4 dlc
	s_waitcnt_vscnt null, 0x0
.LBB8_4:                                ;   in Loop: Header=BB8_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_lshr_b32 s0, s2, 1
	s_cmpk_lt_u32 s2, 0x84
	s_mov_b32 s2, s0
	s_cbranch_scc0 .LBB8_2
.LBB8_5:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj2EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj2EEvPfS0_,"axG",@progbits,_Z7reduce6ILj2EEvPfS0_,comdat
.Lfunc_end8:
	.size	_Z7reduce6ILj2EEvPfS0_, .Lfunc_end8-_Z7reduce6ILj2EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce6ILj1EEvPfS0_,"axG",@progbits,_Z7reduce6ILj1EEvPfS0_,comdat
	.protected	_Z7reduce6ILj1EEvPfS0_  ; -- Begin function _Z7reduce6ILj1EEvPfS0_
	.globl	_Z7reduce6ILj1EEvPfS0_
	.p2align	8
	.type	_Z7reduce6ILj1EEvPfS0_,@function
_Z7reduce6ILj1EEvPfS0_:                 ; @_Z7reduce6ILj1EEvPfS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s2
	v_lshl_add_u32 v1, s15, 1, v0
	v_mov_b32_e32 v2, 0
	v_lshl_add_u32 v0, v0, 2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	ds_store_b32 v0, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6ILj1EEvPfS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6ILj1EEvPfS0_,"axG",@progbits,_Z7reduce6ILj1EEvPfS0_,comdat
.Lfunc_end9:
	.size	_Z7reduce6ILj1EEvPfS0_, .Lfunc_end9-_Z7reduce6ILj1EEvPfS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym sdata
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
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        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7reduce6ILj1EEvPfS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7reduce6ILj1EEvPfS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
