#include "includes.h"
__global__ void gpuIt3(float *tNew,float *tOld,float *tOrig,int x,int y,int z,float k,float st) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < x*y*z){

if(i == 0){ // front upper left corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 0;
}
else if(i == x-1){ // front upper right corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .1;
}
else if(i == x*y-1){ // front lower right corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .2;
}
else if(i == x*y-x){ // front lower left corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .3;
}
else if(i == x*y*(z-1) ){ // back upper left corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .4;
}
else if(i == x*y*(z-1) + x-1){ // back upper right corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .5;
}
else if(i == x*y*z-1){ // back lower right corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .6;
}
else if(i == x*y*z - x){ // back lower left corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .7;
}

else if(i - x < 0){ // front top edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .8;
}
else if(i%x == x-1 && i<x*y){ // front right edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .9;
}
else if(i+x > x*y && i < (x*y)){ // front bottom edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1;
}
else if(i%x == 0 && i<x*y){ // front left edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 2;
}

else if(i > (x*y*z - x*y) && i < (x*y*z - (x-1)*y)){ // back top edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 3;
}
else if(i%x == x-1 && i > (x*y*(z-1))){ // back right edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 4;
}
else if(i+x > x*y*z){ // back bottom edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 5;
}
else if(i%x == 0 && i > x*y*(z-1)){ // back left edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 6;
}

// the corner sides going front to back
else if(i%(x*y) == 0){ // upper left edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 7;
}
else if(i%(x*y) == x-1){ // upper right edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 8;
}
else if(i%(x*y) == x*y-1){ // lower right edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 9;
}
else if(i%(x*y) == x*y-x){ // lower left edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 9.1;
}

// else ifs here are vague because other options already completed
else if(i < x*y){ // front face
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.1;
}
else if(i > x*y*(z-1)){ // back face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.2;
}
else if(i%(x*y) < x){ // top face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.3;
}
else if(i%(x*y) > x*(y-1)){ // bottom face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.4;
}
else if(i%(x) == x-1){ // right face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 1.5;
}
else if(i%(x) == 0){ // left face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.6;
}
else{ // all in the middle
//                       front        back         top       bottom     left     right
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
}


//tNew[i] = i%(x*y);
// replace heaters
if(tOrig[i] != st){
tNew[i] = tOrig[i];
}

}
}
	.file	"tmpxft_002784c2_00000000-6_gpuIt3.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z34__device_stub__Z6gpuIt3PfS_S_iiiffPfS_S_iiiff
	.type	_Z34__device_stub__Z6gpuIt3PfS_S_iiiffPfS_S_iiiff, @function
_Z34__device_stub__Z6gpuIt3PfS_S_iiiffPfS_S_iiiff:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z6gpuIt3PfS_S_iiiff(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z34__device_stub__Z6gpuIt3PfS_S_iiiffPfS_S_iiiff, .-_Z34__device_stub__Z6gpuIt3PfS_S_iiiffPfS_S_iiiff
	.globl	_Z6gpuIt3PfS_S_iiiff
	.type	_Z6gpuIt3PfS_S_iiiff, @function
_Z6gpuIt3PfS_S_iiiff:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z6gpuIt3PfS_S_iiiffPfS_S_iiiff
	.cfi_endproc
.LFE2033:
	.size	_Z6gpuIt3PfS_S_iiiff, .-_Z6gpuIt3PfS_S_iiiff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6gpuIt3PfS_S_iiiff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6gpuIt3PfS_S_iiiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpuIt3(float *tNew,float *tOld,float *tOrig,int x,int y,int z,float k,float st) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < x*y*z){

if(i == 0){ // front upper left corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 0;
}
else if(i == x-1){ // front upper right corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .1;
}
else if(i == x*y-1){ // front lower right corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .2;
}
else if(i == x*y-x){ // front lower left corner
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .3;
}
else if(i == x*y*(z-1) ){ // back upper left corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .4;
}
else if(i == x*y*(z-1) + x-1){ // back upper right corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .5;
}
else if(i == x*y*z-1){ // back lower right corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .6;
}
else if(i == x*y*z - x){ // back lower left corner
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .7;
}

else if(i - x < 0){ // front top edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = .8;
}
else if(i%x == x-1 && i<x*y){ // front right edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = .9;
}
else if(i+x > x*y && i < (x*y)){ // front bottom edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1;
}
else if(i%x == 0 && i<x*y){ // front left edge
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 2;
}

else if(i > (x*y*z - x*y) && i < (x*y*z - (x-1)*y)){ // back top edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 3;
}
else if(i%x == x-1 && i > (x*y*(z-1))){ // back right edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 4;
}
else if(i+x > x*y*z){ // back bottom edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 5;
}
else if(i%x == 0 && i > x*y*(z-1)){ // back left edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 6;
}

// the corner sides going front to back
else if(i%(x*y) == 0){ // upper left edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 7;
}
else if(i%(x*y) == x-1){ // upper right edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 8;
}
else if(i%(x*y) == x*y-1){ // lower right edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 9;
}
else if(i%(x*y) == x*y-x){ // lower left edge
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 9.1;
}

// else ifs here are vague because other options already completed
else if(i < x*y){ // front face
tNew[i] = tOld[i]+k*(tOld[i]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.1;
}
else if(i > x*y*(z-1)){ // back face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.2;
}
else if(i%(x*y) < x){ // top face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.3;
}
else if(i%(x*y) > x*(y-1)){ // bottom face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.4;
}
else if(i%(x) == x-1){ // right face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i]-6*tOld[i]);
//tNew[i] = 1.5;
}
else if(i%(x) == 0){ // left face
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i]+tOld[i+1]-6*tOld[i]);
//tNew[i] = 1.6;
}
else{ // all in the middle
//                       front        back         top       bottom     left     right
tNew[i] = tOld[i]+k*(tOld[i-(x*y)]+tOld[i+(x*y)]+tOld[i-x]+tOld[i+x]+tOld[i-1]+tOld[i+1]-6*tOld[i]);
}


//tNew[i] = i%(x*y);
// replace heaters
if(tOrig[i] != st){
tNew[i] = tOrig[i];
}

}
}
	.text
	.file	"gpuIt3.hip"
	.globl	_Z21__device_stub__gpuIt3PfS_S_iiiff # -- Begin function _Z21__device_stub__gpuIt3PfS_S_iiiff
	.type	_Z21__device_stub__gpuIt3PfS_S_iiiff,@function
_Z21__device_stub__gpuIt3PfS_S_iiiff:   # @_Z21__device_stub__gpuIt3PfS_S_iiiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	4(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6gpuIt3PfS_S_iiiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__gpuIt3PfS_S_iiiff, .Lfunc_end0-_Z21__device_stub__gpuIt3PfS_S_iiiff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6gpuIt3PfS_S_iiiff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6gpuIt3PfS_S_iiiff,@object    # @_Z6gpuIt3PfS_S_iiiff
	.section	.rodata,"a",@progbits
	.globl	_Z6gpuIt3PfS_S_iiiff
	.p2align	3, 0x0
_Z6gpuIt3PfS_S_iiiff:
	.quad	_Z21__device_stub__gpuIt3PfS_S_iiiff
	.size	_Z6gpuIt3PfS_S_iiiff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6gpuIt3PfS_S_iiiff"
	.size	.L__unnamed_1, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__gpuIt3PfS_S_iiiff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6gpuIt3PfS_S_iiiff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6gpuIt3PfS_S_iiiff    ; -- Begin function _Z6gpuIt3PfS_S_iiiff
	.globl	_Z6gpuIt3PfS_S_iiiff
	.p2align	8
	.type	_Z6gpuIt3PfS_S_iiiff,@function
_Z6gpuIt3PfS_S_iiiff:                   ; @_Z6gpuIt3PfS_S_iiiff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[16:19], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s12, s17, s16
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s13, s12, s18
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s13, v1
	s_cbranch_execz .LBB0_109
; %bb.1:
	s_clause 0x2
	s_load_b32 s14, s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[6:7], s[0:1], 0x10
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s15, exec_lo, s0
	s_cbranch_execz .LBB0_105
; %bb.2:
	s_add_i32 s35, s16, -1
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e64 s35, v1
	s_xor_b32 s18, exec_lo, s0
	s_cbranch_execz .LBB0_102
; %bb.3:
	s_add_i32 s36, s12, -1
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e64 s36, v1
	s_xor_b32 s20, exec_lo, s0
	s_cbranch_execz .LBB0_99
; %bb.4:
	s_sub_i32 s37, s12, s16
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e64 s37, v1
	s_xor_b32 s21, exec_lo, s0
	s_cbranch_execz .LBB0_96
; %bb.5:
	s_sub_i32 s5, s13, s12
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u32_e64 s5, v1
	s_xor_b32 s22, exec_lo, s0
	s_cbranch_execz .LBB0_93
; %bb.6:
	s_add_i32 s0, s35, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s23, exec_lo, s0
	s_cbranch_execz .LBB0_90
; %bb.7:
	s_add_i32 s0, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s24, exec_lo, s0
	s_cbranch_execz .LBB0_87
; %bb.8:
	s_sub_i32 s0, s13, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s25, exec_lo, s0
	s_cbranch_execz .LBB0_84
; %bb.9:
	v_subrev_nc_u32_e32 v3, s16, v1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v3
	s_xor_b32 s26, exec_lo, s0
	s_cbranch_execz .LBB0_81
; %bb.10:
	s_ashr_i32 s27, s16, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s0, s16, s27
	v_cmp_gt_i32_e64 s4, s12, v1
	s_xor_b32 s0, s0, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s0
	s_sub_i32 s1, 0, s0
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v0
	v_mul_lo_u32 v0, s1, v4
	v_cmp_le_i32_e64 s1, s12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v4, v0
	v_add_nc_u32_e32 v0, v1, v2
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v4, v5
	v_mul_hi_u32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v4, s0
	v_sub_nc_u32_e32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v2
	v_sub_nc_u32_e32 v5, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s2, s35, v5
	v_cmp_ne_u32_e32 vcc_lo, s35, v5
	s_and_b32 s0, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s3, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s28, exec_lo, s3
	s_cbranch_execz .LBB0_78
; %bb.11:
	v_add_nc_u32_e32 v4, s16, v1
	s_xor_b32 s3, s4, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, s12, v4
	s_or_b32 s0, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_xor_b32 s29, exec_lo, s3
	s_cbranch_execz .LBB0_75
; %bb.12:
	v_cmp_eq_u32_e64 s3, 0, v5
	v_cmp_ne_u32_e64 s0, 0, v5
	s_mov_b32 s31, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s4, s3
	s_xor_b32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s30, s4
	s_xor_b32 s30, exec_lo, s30
	s_cbranch_execz .LBB0_72
; %bb.13:
	v_cmp_ge_i32_e64 s38, s5, v1
	v_cmp_lt_i32_e64 s4, s5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 s5, s38
	s_and_saveexec_b32 s33, s4
; %bb.14:
	s_mul_i32 s5, s35, s17
	s_and_not1_b32 s34, s38, exec_lo
	s_sub_i32 s5, s13, s5
	s_mov_b32 s31, exec_lo
	v_cmp_le_i32_e64 s5, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, s5, exec_lo
	s_or_b32 s5, s34, s5
; %bb.15:                               ; %Flow826
	s_or_b32 exec_lo, exec_lo, s33
	s_and_saveexec_b32 s33, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s33
	s_cbranch_execz .LBB0_69
; %bb.16:
	s_and_b32 s2, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, -1
	s_and_saveexec_b32 s33, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s33, exec_lo, s33
	s_cbranch_execz .LBB0_66
; %bb.17:
	v_cmp_ge_i32_e64 s2, s13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s13, s2
	s_xor_b32 s34, exec_lo, s13
	s_cbranch_execz .LBB0_63
; %bb.18:
	s_and_b32 s2, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, -1
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_60
; %bb.19:
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s12, s13
	s_xor_b32 s4, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v4, s4
	s_sub_i32 s2, 0, s4
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v5, s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v4, v5
	v_add_nc_u32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v0, v4
	v_mul_lo_u32 v4, v4, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v4
	v_subrev_nc_u32_e32 v4, s4, v0
	v_cmp_le_u32_e64 s2, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v4, s2
	v_subrev_nc_u32_e32 v4, s4, v0
	v_cmp_le_u32_e64 s2, s4, v0
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v4, s2
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v0, v2
	v_cmpx_ne_u32_e32 0, v7
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_57
; %bb.20:
	v_cmp_ne_u32_e64 s2, s35, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s35, s2
	s_xor_b32 s35, exec_lo, s35
	s_cbranch_execz .LBB0_54
; %bb.21:
	v_cmp_ne_u32_e64 s2, s36, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s36, s2
	s_xor_b32 s36, exec_lo, s36
	s_cbranch_execz .LBB0_51
; %bb.22:
	v_cmp_ne_u32_e64 s2, s37, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s37, s2
	s_xor_b32 s2, exec_lo, s37
	s_cbranch_execz .LBB0_48
; %bb.23:
	s_and_saveexec_b32 s37, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s37, exec_lo, s37
	s_cbranch_execz .LBB0_45
; %bb.24:
	s_and_saveexec_b32 s1, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s38, exec_lo, s1
	s_cbranch_execz .LBB0_42
; %bb.25:
	s_mov_b32 s39, exec_lo
	v_cmpx_le_i32_e64 s16, v7
	s_xor_b32 s39, exec_lo, s39
	s_cbranch_execz .LBB0_39
; %bb.26:
	v_subrev_nc_u32_e32 v8, s12, v1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[40:41], s[12:13], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s1, s10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_ci_u32_e64 v4, s1, s11, v6, s1
	v_add_co_u32 v8, s1, s10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, s11, v9, s1
	v_add_co_u32 v12, s1, v3, s40
	v_add_co_ci_u32_e64 v13, s1, s41, v4, s1
	v_add_co_u32 v10, s1, s10, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
	s_clause 0x3
	global_load_b32 v8, v[8:9], off
	global_load_b32 v9, v[12:13], off
	global_load_b32 v10, v[10:11], off
	global_load_b32 v0, v[3:4], off
	s_add_i32 s1, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s16
	v_cmp_ge_i32_e64 s1, s1, v7
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v8, v8, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v7, v8, v10
	s_and_saveexec_b32 s17, s1
	s_xor_b32 s40, exec_lo, s17
	s_cbranch_execz .LBB0_36
; %bb.27:
	s_mov_b32 s17, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[42:43], s[16:17], 2
	v_add_co_u32 v8, s1, v3, s42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v9, s1, s43, v4, s1
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v8
	s_and_saveexec_b32 s1, vcc_lo
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_33
; %bb.28:
	s_and_saveexec_b32 s17, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s17
	s_cbranch_execz .LBB0_30
; %bb.29:
	s_clause 0x1
	global_load_b32 v8, v[3:4], off offset:-4
	global_load_b32 v3, v[3:4], off offset:4
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v7, v8
                                        ; implicit-def: $vgpr7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v4, v3
	v_fmamk_f32 v3, v0, 0xc0c00000, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, s19, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
                                        ; implicit-def: $vgpr5_vgpr6
	global_store_b32 v[3:4], v0, off
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr3_vgpr4
.LBB0_30:                               ; %Flow789
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_32
; %bb.31:
	global_load_b32 v3, v[3:4], off offset:4
	v_add_f32_e32 v4, v0, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v4
	v_fmamk_f32 v3, v0, 0xc0c00000, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, s19, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	global_store_b32 v[3:4], v0, off
.LBB0_32:                               ; %Flow790
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr5_vgpr6
.LBB0_33:                               ; %Flow792
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_35
; %bb.34:
	global_load_b32 v3, v[3:4], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v0, v3
	v_fmamk_f32 v3, v0, 0xc0c00000, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, s19, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	global_store_b32 v[3:4], v0, off
.LBB0_35:                               ; %Flow793
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
.LBB0_36:                               ; %Flow795
	s_and_not1_saveexec_b32 s0, s40
	s_cbranch_execz .LBB0_38
; %bb.37:
	s_clause 0x1
	global_load_b32 v8, v[3:4], off offset:-4
	global_load_b32 v3, v[3:4], off offset:4
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v4, v0, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v8, v4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v0, 0xc0c00000, v3
	v_fmac_f32_e32 v0, s19, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	global_store_b32 v[3:4], v0, off
.LBB0_38:                               ; %Flow796
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_39:                               ; %Flow798
	s_and_not1_saveexec_b32 s0, s39
	s_cbranch_execz .LBB0_41
; %bb.40:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_lshl_b64 s[40:41], s[12:13], 2
	s_mov_b32 s17, s27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v10, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v12, vcc_lo, v8, s40
	v_add_co_ci_u32_e32 v13, vcc_lo, s41, v9, vcc_lo
	s_clause 0x2
	global_load_b96 v[3:5], v[8:9], off offset:-4
	global_load_b32 v0, v[10:11], off
	global_load_b32 v10, v[12:13], off
	s_lshl_b64 s[40:41], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, s40
	v_add_co_ci_u32_e32 v9, vcc_lo, s41, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v0, v10
	v_add_f32_e32 v0, v4, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v8, v0
	v_add_f32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v5, v0
	v_add_co_u32 v5, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_41:                               ; %Flow799
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_42:                               ; %Flow801
	s_and_not1_saveexec_b32 s0, s38
	s_cbranch_execz .LBB0_44
; %bb.43:
	v_subrev_nc_u32_e32 v5, s12, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_mov_b32 s17, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_lshl_b64 s[38:39], s[16:17], 2
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v13, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v4, vcc_lo
	s_clause 0x1
	global_load_b96 v[3:5], v[9:10], off offset:-4
	global_load_b32 v0, v[11:12], off
	v_add_co_u32 v9, vcc_lo, v9, s38
	v_add_co_ci_u32_e32 v10, vcc_lo, s39, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v6, v[13:14], off
	global_load_b32 v9, v[9:10], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v4, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v3
	v_add_f32_e32 v0, v0, v5
	v_add_co_u32 v5, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_44:                               ; %Flow802
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_45:                               ; %Flow804
	s_and_not1_saveexec_b32 s0, s37
	s_cbranch_execz .LBB0_47
; %bb.46:
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[38:39], s[12:13], 2
	s_mov_b32 s17, s27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, s38
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s39, v9, vcc_lo
	s_lshl_b64 s[38:39], s[16:17], 2
	s_clause 0x1
	global_load_b96 v[3:5], v[8:9], off offset:-4
	global_load_b32 v0, v[10:11], off
	v_add_co_u32 v10, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v13, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, s38
	v_add_co_ci_u32_e32 v9, vcc_lo, s39, v9, vcc_lo
	s_clause 0x1
	global_load_b32 v10, v[10:11], off
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v4, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v10
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v3
	v_add_f32_e32 v0, v0, v5
	v_add_co_u32 v5, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_47:                               ; %Flow805
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_48:                               ; %Flow807
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_50
; %bb.49:
	v_subrev_nc_u32_e32 v5, s12, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[38:39], s[12:13], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, v9, s38
	v_add_co_ci_u32_e32 v12, vcc_lo, s39, v10, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x3
	global_load_b32 v0, v[5:6], off
	global_load_b32 v5, v[11:12], off
	global_load_b32 v6, v[3:4], off
	global_load_b64 v[3:4], v[9:10], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v0, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v0, v4, v0
	v_add_co_u32 v4, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v3, 0xc0c00000, v0
	v_fmac_f32_e32 v3, s19, v0
	global_store_b32 v[4:5], v3, off
.LBB0_50:                               ; %Flow808
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_51:                               ; %Flow810
	s_and_not1_saveexec_b32 s0, s36
	s_cbranch_execz .LBB0_53
; %bb.52:
	v_subrev_nc_u32_e32 v5, s12, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[36:37], s[12:13], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, v9, s36
	v_add_co_ci_u32_e32 v12, vcc_lo, s37, v10, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x3
	global_load_b32 v0, v[5:6], off
	global_load_b32 v5, v[11:12], off
	global_load_b32 v6, v[3:4], off
	global_load_b64 v[3:4], v[9:10], off offset:-4
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v0, v5
	v_add_co_u32 v5, vcc_lo, s8, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v0, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_53:                               ; %Flow811
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_54:                               ; %Flow813
	s_and_not1_saveexec_b32 s0, s35
	s_cbranch_execz .LBB0_56
; %bb.55:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_lshl_b64 s[36:37], s[12:13], 2
	s_mov_b32 s17, s27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, v7, s36
	v_add_co_ci_u32_e32 v10, vcc_lo, s37, v8, vcc_lo
	s_clause 0x2
	global_load_b64 v[11:12], v[7:8], off offset:-4
	global_load_b32 v0, v[3:4], off
	global_load_b32 v9, v[9:10], off
	s_lshl_b64 s[36:37], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v7, s36
	v_add_co_ci_u32_e32 v4, vcc_lo, s37, v8, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v0, v9
	v_add_f32_e32 v0, v12, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v3, v0
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	v_add_f32_e32 v0, v11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v12, v0
	v_fmamk_f32 v0, v12, 0xc0c00000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v12, s19, v0
	global_store_b32 v[3:4], v12, off
.LBB0_56:                               ; %Flow814
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_57:                               ; %Flow816
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_59
; %bb.58:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_lshl_b64 s[36:37], s[12:13], 2
	s_mov_b32 s17, s27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, v7, s36
	v_add_co_ci_u32_e32 v10, vcc_lo, s37, v8, vcc_lo
	s_clause 0x2
	global_load_b64 v[11:12], v[7:8], off
	global_load_b32 v0, v[3:4], off
	global_load_b32 v9, v[9:10], off
	s_lshl_b64 s[36:37], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v7, s36
	v_add_co_ci_u32_e32 v4, vcc_lo, s37, v8, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v0, v9
	v_add_f32_e32 v0, v11, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v3, v0
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	v_add_f32_e32 v0, v11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v12, v0
	v_fmamk_f32 v0, v11, 0xc0c00000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v11, s19, v0
	global_store_b32 v[3:4], v11, off
.LBB0_59:                               ; %Flow817
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_60:                               ; %Flow818
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_62
; %bb.61:
	v_subrev_nc_u32_e32 v5, s12, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_mov_b32 s17, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[2:3], s[16:17], 2
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_clause 0x1
	global_load_b64 v[11:12], v[9:10], off
	global_load_b32 v0, v[5:6], off
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[5:6], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v11, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v7
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v11, v0
	v_add_f32_e32 v0, v12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v11, 0xc0c00000, v0
	v_fmac_f32_e32 v11, s19, v0
	global_store_b32 v[3:4], v11, off
.LBB0_62:                               ; %Flow819
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_63:                               ; %Flow821
	s_and_not1_saveexec_b32 s0, s34
	s_cbranch_execz .LBB0_65
; %bb.64:
	v_subrev_nc_u32_e32 v5, s12, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v13, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v4, vcc_lo
	s_clause 0x2
	global_load_b96 v[3:5], v[9:10], off offset:-4
	global_load_b32 v0, v[11:12], off
	global_load_b32 v6, v[13:14], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v4, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v6
	v_add_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v0, v5, v0
	v_add_co_u32 v5, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_65:                               ; %Flow822
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_66:                               ; %Flow823
	s_and_not1_saveexec_b32 s0, s33
	s_cbranch_execz .LBB0_68
; %bb.67:
	v_subrev_nc_u32_e32 v5, s12, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_mov_b32 s17, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_lshl_b64 s[2:3], s[16:17], 2
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[11:12], v[9:10], off offset:-4
	global_load_b32 v0, v[5:6], off
	v_add_co_u32 v5, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[5:6], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v12, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v7
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v11
	v_add_f32_e32 v0, v12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v12, 0xc0c00000, v0
	v_fmac_f32_e32 v12, s19, v0
	global_store_b32 v[3:4], v12, off
.LBB0_68:                               ; %Flow824
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s31, s31, exec_lo
.LBB0_69:                               ; %Flow827
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s0, s31
	s_cbranch_execz .LBB0_71
; %bb.70:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_mov_b32 s17, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[2:3], s[16:17], 2
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v4, vcc_lo
	s_clause 0x1
	global_load_b96 v[3:5], v[8:9], off offset:-4
	global_load_b32 v0, v[10:11], off
	v_add_co_u32 v8, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v4, v0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v0, v5, v0
	v_add_co_u32 v5, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_71:                               ; %Flow828
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_72:                               ; %Flow829
	s_and_not1_saveexec_b32 s0, s30
	s_cbranch_execz .LBB0_74
; %bb.73:
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_ashr_i32 s13, s12, 31
	s_mov_b32 s17, s27
	s_lshl_b64 s[2:3], s[12:13], 2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v9, vcc_lo, v7, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
	s_lshl_b64 s[2:3], s[16:17], 2
	s_clause 0x1
	global_load_b64 v[11:12], v[7:8], off
	global_load_b32 v0, v[9:10], off
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[7:8], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v11, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v11, v0
	v_add_f32_e32 v0, v12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v11, 0xc0c00000, v0
	v_fmac_f32_e32 v11, s19, v0
	global_store_b32 v[3:4], v11, off
.LBB0_74:                               ; %Flow830
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_75:                               ; %Flow831
	s_and_not1_saveexec_b32 s0, s29
	s_cbranch_execz .LBB0_77
; %bb.76:
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[2:3], s[12:13], 2
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v9, vcc_lo
	v_add_co_u32 v12, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v4, vcc_lo
	s_clause 0x2
	global_load_b96 v[3:5], v[8:9], off offset:-4
	global_load_b32 v0, v[10:11], off
	global_load_b32 v8, v[12:13], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v4, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v8
	v_add_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v0, v5, v0
	v_add_co_u32 v5, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_77:                               ; %Flow832
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr3
.LBB0_78:                               ; %Flow833
	s_and_not1_saveexec_b32 s0, s28
	s_cbranch_execz .LBB0_80
; %bb.79:
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_mov_b32_e32 v4, 0
	s_ashr_i32 s13, s12, 31
	s_mov_b32 s17, s27
	s_lshl_b64 s[2:3], s[12:13], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v9, vcc_lo, v7, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_lshl_b64 s[2:3], s[16:17], 2
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[11:12], v[7:8], off offset:-4
	global_load_b32 v0, v[9:10], off
	v_add_co_u32 v7, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[7:8], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v12, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v11
	v_add_f32_e32 v0, v12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v12, 0xc0c00000, v0
	v_fmac_f32_e32 v12, s19, v0
	global_store_b32 v[3:4], v12, off
.LBB0_80:                               ; %Flow834
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_81:                               ; %Flow836
	s_and_not1_saveexec_b32 s0, s26
	s_cbranch_execz .LBB0_83
; %bb.82:
	v_ashrrev_i32_e32 v2, 31, v1
	s_ashr_i32 s13, s12, 31
	s_ashr_i32 s17, s16, 31
	s_lshl_b64 s[2:3], s[12:13], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v9, vcc_lo
	s_lshl_b64 s[2:3], s[16:17], 2
	s_clause 0x1
	global_load_b96 v[3:5], v[8:9], off offset:-4
	global_load_b32 v0, v[10:11], off
	v_add_co_u32 v8, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v4, v0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v0, v5, v0
	v_add_co_u32 v5, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v4, 0xc0c00000, v0
	v_fmac_f32_e32 v4, s19, v0
	global_store_b32 v[5:6], v4, off
.LBB0_83:                               ; %Flow837
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_84:                               ; %Flow839
	s_and_not1_saveexec_b32 s0, s25
	s_cbranch_execz .LBB0_86
; %bb.85:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_ashrrev_i32_e32 v2, 31, v1
	v_subrev_nc_u32_e32 v5, s16, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_clause 0x2
	global_load_b64 v[9:10], v[9:10], off
	global_load_b32 v0, v[3:4], off
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v9, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v8, vcc_lo
	v_add_f32_e32 v0, v9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v0
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v9, 0xc0c00000, v0
	v_fmac_f32_e32 v9, s19, v0
	global_store_b32 v[3:4], v9, off
.LBB0_86:                               ; %Flow840
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_87:                               ; %Flow842
	s_and_not1_saveexec_b32 s0, s24
	s_cbranch_execz .LBB0_89
; %bb.88:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_ashrrev_i32_e32 v2, 31, v1
	v_subrev_nc_u32_e32 v5, s16, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_clause 0x2
	global_load_b64 v[9:10], v[9:10], off offset:-4
	global_load_b32 v0, v[3:4], off
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v10, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v8, vcc_lo
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v0
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v10, 0xc0c00000, v0
	v_fmac_f32_e32 v10, s19, v0
	global_store_b32 v[3:4], v10, off
.LBB0_89:                               ; %Flow843
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_90:                               ; %Flow845
	s_and_not1_saveexec_b32 s0, s23
	s_cbranch_execz .LBB0_92
; %bb.91:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[2:3], s[16:17], 2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[9:10], v[7:8], off offset:-4
	global_load_b32 v0, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v10, v0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v3, v0
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v0
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v10, 0xc0c00000, v0
	v_fmac_f32_e32 v10, s19, v0
	global_store_b32 v[3:4], v10, off
.LBB0_92:                               ; %Flow846
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_93:                               ; %Flow848
	s_and_not1_saveexec_b32 s0, s22
	s_cbranch_execz .LBB0_95
; %bb.94:
	v_subrev_nc_u32_e32 v3, s12, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_ashr_i32 s17, s16, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[2:3], s[16:17], 2
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[9:10], v[7:8], off
	global_load_b32 v0, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v3, v0
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v0
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v9, 0xc0c00000, v0
	v_fmac_f32_e32 v9, s19, v0
	global_store_b32 v[3:4], v9, off
.LBB0_95:                               ; %Flow849
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_96:                               ; %Flow851
	s_and_not1_saveexec_b32 s0, s21
	s_cbranch_execz .LBB0_98
; %bb.97:
	v_ashrrev_i32_e32 v2, 31, v1
	v_subrev_nc_u32_e32 v3, s16, v1
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[2:3], s[12:13], 2
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x2
	global_load_b64 v[7:8], v[7:8], off
	global_load_b32 v0, v[9:10], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v7, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	v_add_f32_e32 v0, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v7, v0
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v7, 0xc0c00000, v0
	v_fmac_f32_e32 v7, s19, v0
	global_store_b32 v[3:4], v7, off
.LBB0_98:                               ; %Flow852
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_99:                               ; %Flow854
	s_and_not1_saveexec_b32 s0, s20
	s_cbranch_execz .LBB0_101
; %bb.100:
	v_ashrrev_i32_e32 v2, 31, v1
	v_subrev_nc_u32_e32 v3, s16, v1
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[2:3], s[12:13], 2
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_clause 0x2
	global_load_b64 v[7:8], v[7:8], off offset:-4
	global_load_b32 v0, v[9:10], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v8, v0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v0, v3
	v_add_co_u32 v3, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v7, v0
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v8, 0xc0c00000, v0
	v_fmac_f32_e32 v8, s19, v0
	global_store_b32 v[3:4], v8, off
.LBB0_101:                              ; %Flow855
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_102:                              ; %Flow857
	s_and_not1_saveexec_b32 s0, s18
	s_cbranch_execz .LBB0_104
; %bb.103:
	v_ashrrev_i32_e32 v2, 31, v1
	s_ashr_i32 s13, s12, 31
	s_ashr_i32 s17, s16, 31
	s_lshl_b64 s[2:3], s[12:13], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, v5, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
	s_lshl_b64 s[2:3], s[16:17], 2
	s_clause 0x1
	global_load_b64 v[9:10], v[5:6], off offset:-4
	global_load_b32 v0, v[7:8], off
	v_add_co_u32 v5, vcc_lo, v5, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v10, v0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v0
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v10, 0xc0c00000, v0
	v_fmac_f32_e32 v10, s19, v0
	global_store_b32 v[3:4], v10, off
.LBB0_104:                              ; %Flow858
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_105:                              ; %Flow860
	s_and_not1_saveexec_b32 s0, s15
	s_cbranch_execz .LBB0_107
; %bb.106:
	v_mov_b32_e32 v3, 0
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[12:13], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s10, s2
	global_load_b64 v[0:1], v3, s[10:11]
	s_addc_u32 s3, s11, s3
	s_ashr_i32 s17, s16, 31
	s_load_b32 s1, s[2:3], 0x0
	s_lshl_b64 s[2:3], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s2, s10, s2
	s_addc_u32 s3, s11, s3
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v2, s1, v0
	v_add_f32_e32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, s2, v2
	v_add_f32_e32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_fmamk_f32 v1, v0, 0xc0c00000, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmac_f32 v0, s19, v1 :: v_dual_mov_b32 v1, 0
	v_mov_b32_e32 v2, 0
	global_store_b32 v3, v0, s[8:9]
.LBB0_107:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e32 vcc_lo, s14, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_109
; %bb.108:
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_109:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6gpuIt3PfS_S_iiiff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6gpuIt3PfS_S_iiiff, .Lfunc_end0-_Z6gpuIt3PfS_S_iiiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6648
; NumSgprs: 46
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6gpuIt3PfS_S_iiiff
    .private_segment_fixed_size: 0
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         _Z6gpuIt3PfS_S_iiiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
