//transform length
#define TLEN 128
#define TILE_DIM 16
#define HEIGHT 8 //1, 2, 4, 8
#define NEG_2PI_BY_TLEN -0.04908738521f //-2*PI/128
#define STRIDE_STAGE_1 0x00000040 //64
#define STRIDE_STAGE_2 0x00000020 //32
#define STRIDE_STAGE_3 0x00000010 //16
#define STRIDE_STAGE_4 0x00000008 //08
#define STRIDE_STAGE_5 0x00000004 //04
#define STRIDE_STAGE_6 0x00000002 //02
#define STRIDE_STAGE_7 0x00000001 //01

#define M12 0x60
#define M34 0x18
#define M35 0x14
#define M46 0x0a
#define M246 0x2a
#define M135 0x54
#define M357 0x15
#define M56 0x06
#define M5 0x04

__device__ int bitreverse(int tid)
{
  int revtid = tid;
  revtid = ((0xf0f0f0f0 & revtid) >> 4) | ((0x0f0f0f0f & revtid) << 4);
  revtid = ((0xcccccccc & revtid) >> 2) | ((0x33333333 & revtid) << 2);
  revtid = ((0xaaaaaaaa & revtid) >> 2) | ((0x55555555 & revtid));
  return revtid;
}

__global__ void FFT1D(float *real, float *img)
{
  float rVal[HEIGHT], iVal[HEIGHT];
  //assuming that thread block size is 128
  __shared__ float shReal[HEIGHT][TLEN];
  __shared__ float shImg[HEIGHT][TLEN];

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
    rVal[I] = real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
    iVal[I] = img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  if((threadIdx.x & STRIDE_STAGE_1) == STRIDE_STAGE_1)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_1] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_1] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_1] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_1] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_1] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_1] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_1] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_1] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_1] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_1] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_1] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_1] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_1] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_1] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_1] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_1] - iVal[7];
#endif
  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_1] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_1] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_1] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_1] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_1] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_1] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_1] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_1] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_1] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_1] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_1] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_1] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_1] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_1] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_1] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_1] + iVal[7];
#endif

  }

  if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
  {
    //calculate Q twiddle factor
    float Q = (float)((threadIdx.x & STRIDE_STAGE_1)>>1);
    Q = Q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 2
  if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_2] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_2] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_2] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_2] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_2] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_2] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_2] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_2] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_2] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_2] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_2] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_2] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_2] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_2] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_2] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_2] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_2] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_2] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_2] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_2] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_2] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_2] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_2] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_2] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_2] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_2] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_2] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_2] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_2] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_2] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_2] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_2] + iVal[7];
#endif

  }

  //end of stage 2
  //multiply with twiddle for beginning of stage 3
  //STRIDE_STAGE_3 16
  if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
  {
    //calculate Q twiddle factor
    float Q = (float)((threadIdx.x & STRIDE_STAGE_2) | ((threadIdx.x & STRIDE_STAGE_1)>>2));
    Q = Q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage3
  if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_3] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_3] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_3] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_3] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_3] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_3] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_3] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_3] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_3] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_3] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_3] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_3] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_3] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_3] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_3] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_3] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_3] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_3] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_3] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_3] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_3] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_3] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_3] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_3] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_3] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_3] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_3] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_3] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_3] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_3] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_3] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_3] + iVal[7];
#endif

  }
  //end of stage 3
  //multiply with twiddle for beginning of stage 4
  //STRIDE_STAGE_4 8
  if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
  {
    //calculate Q twiddle factor
    float Q = (float)(((threadIdx.x & STRIDE_STAGE_1)>>3) |
      ((threadIdx.x & STRIDE_STAGE_2)>>1) | ((threadIdx.x & STRIDE_STAGE_3)<<1));
    Q = Q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 4
  if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_4] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_4] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_4] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_4] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_4] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_4] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_4] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_4] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_4] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_4] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_4] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_4] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_4] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_4] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_4] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_4] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_4] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_4] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_4] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_4] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_4] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_4] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_4] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_4] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_4] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_4] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_4] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_4] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_4] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_4] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_4] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_4] + iVal[7];
#endif

  }
  //end of stage 4
  //multiply with twiddle for beginning of stage 5
  //STRIDE_STAGE_5 4
  if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
  {
    //calculate Q twiddle factor
    int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34);
    q = (q & M35) | ((q & M46)<<2);
    float Q = q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 5
  if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_5] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_5] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_5] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_5] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_5] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_5] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_5] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_5] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_5] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_5] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_5] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_5] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_5] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_5] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_5] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_5] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_5] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_5] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_5] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_5] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_5] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_5] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_5] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_5] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_5] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_5] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_5] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_5] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_5] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_5] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_5] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_5] + iVal[7];
#endif

  }
  //end of stage 5
  //multiply with twiddle for beginning of stage 6
  //STRIDE_STAGE_6 2
  if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
  {
    //calculate Q twiddle factor
    int q = ((threadIdx.x & M12)>>5) | ((threadIdx.x & M34)>>1) |
      ((threadIdx.x & M5)<<3);
    q = (q & M246) | ((q & M357)<<2);
    float Q = q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 6
  if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_6] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_6] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_6] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_6] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_6] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_6] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_6] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_6] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_6] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_6] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_6] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_6] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_6] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_6] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_6] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_6] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_6] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_6] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_6] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_6] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_6] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_6] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_6] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_6] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_6] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_6] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_6] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_6] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_6] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_6] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_6] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_6] + iVal[7];
#endif

  }
  //end of stage 6
  //multiply with twiddle for beginning of stage 7
  //STRIDE_STAGE_7 1
  if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
  {
    //calculate Q twiddle factor
    int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34) |
      ((threadIdx.x & M56)<<4);
    q = ((q & M135)>>2) | (q & M246);
    float Q = q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 7
  if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_7] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_7] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_7] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_7] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_7] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_7] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_7] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_7] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_7] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_7] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_7] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_7] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_7] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_7] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_7] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_7] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_7] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_7] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_7] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_7] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_7] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_7] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_7] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_7] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_7] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_7] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_7] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_7] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_7] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_7] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_7] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_7] + iVal[7];
#endif

  }
  int revtid = bitreverse(threadIdx.x);
/*
  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][revtid] = rVal[I];
  shImg[I][revtid] = iVal[I];
  }
*/
  shReal[0][revtid] = rVal[0];
  shImg[0][revtid] = iVal[0];
#if HEIGHT > 1
  shReal[1][revtid] = rVal[1];
  shImg[1][revtid] = iVal[1];
#endif

#if HEIGHT > 2
  shReal[2][revtid] = rVal[2];
  shImg[2][revtid] = iVal[2];
  shReal[3][revtid] = rVal[3];
  shImg[3][revtid] = iVal[3];
#endif

#if HEIGHT > 4
  shReal[4][revtid] = rVal[4];
  shImg[4][revtid] = iVal[4];
  shReal[5][revtid] = rVal[5];
  shImg[5][revtid] = iVal[5];
  shReal[6][revtid] = rVal[6];
  shImg[6][revtid] = iVal[6];
  shReal[7][revtid] = rVal[7];
  shImg[7][revtid] = iVal[7];
#endif

  __syncthreads();

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
    real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shReal[I][threadIdx.x];
    img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shImg[I][threadIdx.x];
  }
}

__global__ void transposeDiagonal_xy(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_y;

  // do diagonal reordering
  blockIdx_y = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
  int index_in = xIndex + (yIndex + blockIdx.z*width)*width;

  xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
  yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
  int index_out = xIndex + (yIndex + blockIdx.z*width)*width;

  tile[threadIdx.y][threadIdx.x] = idatar[index_in];
  __syncthreads();
  odatar[index_out] = tile[threadIdx.x][threadIdx.y];
  __syncthreads();
  tile[threadIdx.y][threadIdx.x] = idatai[index_in];
  __syncthreads();
  odatai[index_out] = tile[threadIdx.x][threadIdx.y];
}

__global__ void transposeDiagonal_xz(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_z;

  // do diagonal reordering
  blockIdx_z = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
  int index_in = xIndex + (blockIdx.y + zIndex*width)*width;

  xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
  zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
  int index_out = xIndex + (blockIdx.y + zIndex*width)*width;

  tile[threadIdx.z][threadIdx.x] = idatar[index_in];
  __syncthreads();
  odatar[index_out] = tile[threadIdx.x][threadIdx.z];
  __syncthreads();
  tile[threadIdx.z][threadIdx.x] = idatai[index_in];
  __syncthreads();
  odatai[index_out] = tile[threadIdx.x][threadIdx.z];
}

__global__ void transposeDiagonal_xy(float *odata, float *idata, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_y;

  // do diagonal reordering
  blockIdx_y = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
  int index_in = xIndex + (yIndex + blockIdx.z*width)*width;

  xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
  yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
  int index_out = xIndex + (yIndex + blockIdx.z*width)*width;

  tile[threadIdx.y][threadIdx.x] = idata[index_in];
  __syncthreads();
  odata[index_out] = tile[threadIdx.x][threadIdx.y];
}

__global__ void transposeDiagonal_xz(float *odata, float *idata, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_z;

  // do diagonal reordering
  blockIdx_z = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
  int index_in = xIndex + (blockIdx.y + zIndex*width)*width;

  xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
  zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
  int index_out = xIndex + (blockIdx.y + zIndex*width)*width;

  tile[threadIdx.z][threadIdx.x] = idata[index_in];
  __syncthreads();
  odata[index_out] = tile[threadIdx.x][threadIdx.z];
}

	.file	"tmpxft_00250a44_00000000-6_fft.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10bitreversei
	.type	_Z10bitreversei, @function
_Z10bitreversei:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z10bitreversei, .-_Z10bitreversei
	.globl	_Z26__device_stub__Z5FFT1DPfS_PfS_
	.type	_Z26__device_stub__Z5FFT1DPfS_PfS_, @function
_Z26__device_stub__Z5FFT1DPfS_PfS_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5FFT1DPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z26__device_stub__Z5FFT1DPfS_PfS_, .-_Z26__device_stub__Z5FFT1DPfS_PfS_
	.globl	_Z5FFT1DPfS_
	.type	_Z5FFT1DPfS_, @function
_Z5FFT1DPfS_:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z5FFT1DPfS_PfS_
	.cfi_endproc
.LFE2034:
	.size	_Z5FFT1DPfS_, .-_Z5FFT1DPfS_
	.globl	_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
	.type	_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i, @function
_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z20transposeDiagonal_xyPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L10:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i, .-_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
	.globl	_Z20transposeDiagonal_xyPfS_S_S_i
	.type	_Z20transposeDiagonal_xyPfS_S_S_i, @function
_Z20transposeDiagonal_xyPfS_S_S_i:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z20transposeDiagonal_xyPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE2036:
	.size	_Z20transposeDiagonal_xyPfS_S_S_i, .-_Z20transposeDiagonal_xyPfS_S_S_i
	.globl	_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
	.type	_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i, @function
_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z20transposeDiagonal_xzPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L15:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i, .-_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
	.globl	_Z20transposeDiagonal_xzPfS_S_S_i
	.type	_Z20transposeDiagonal_xzPfS_S_S_i, @function
_Z20transposeDiagonal_xzPfS_S_S_i:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z20transposeDiagonal_xzPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE2038:
	.size	_Z20transposeDiagonal_xzPfS_S_S_i, .-_Z20transposeDiagonal_xzPfS_S_S_i
	.globl	_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
	.type	_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i, @function
_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z20transposeDiagonal_xyPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L20:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i, .-_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
	.globl	_Z20transposeDiagonal_xyPfS_i
	.type	_Z20transposeDiagonal_xyPfS_i, @function
_Z20transposeDiagonal_xyPfS_i:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z20transposeDiagonal_xyPfS_iPfS_i
	.cfi_endproc
.LFE2040:
	.size	_Z20transposeDiagonal_xyPfS_i, .-_Z20transposeDiagonal_xyPfS_i
	.globl	_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
	.type	_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i, @function
_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z20transposeDiagonal_xzPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L25:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i, .-_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
	.globl	_Z20transposeDiagonal_xzPfS_i
	.type	_Z20transposeDiagonal_xzPfS_i, @function
_Z20transposeDiagonal_xzPfS_i:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z20transposeDiagonal_xzPfS_iPfS_i
	.cfi_endproc
.LFE2042:
	.size	_Z20transposeDiagonal_xzPfS_i, .-_Z20transposeDiagonal_xzPfS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20transposeDiagonal_xzPfS_i"
.LC1:
	.string	"_Z20transposeDiagonal_xyPfS_i"
.LC2:
	.string	"_Z20transposeDiagonal_xzPfS_S_S_i"
.LC3:
	.string	"_Z20transposeDiagonal_xyPfS_S_S_i"
.LC4:
	.string	"_Z5FFT1DPfS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2044:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20transposeDiagonal_xzPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20transposeDiagonal_xyPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20transposeDiagonal_xzPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20transposeDiagonal_xyPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z5FFT1DPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2044:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//transform length
#define TLEN 128
#define TILE_DIM 16
#define HEIGHT 8 //1, 2, 4, 8
#define NEG_2PI_BY_TLEN -0.04908738521f //-2*PI/128
#define STRIDE_STAGE_1 0x00000040 //64
#define STRIDE_STAGE_2 0x00000020 //32
#define STRIDE_STAGE_3 0x00000010 //16
#define STRIDE_STAGE_4 0x00000008 //08
#define STRIDE_STAGE_5 0x00000004 //04
#define STRIDE_STAGE_6 0x00000002 //02
#define STRIDE_STAGE_7 0x00000001 //01

#define M12 0x60
#define M34 0x18
#define M35 0x14
#define M46 0x0a
#define M246 0x2a
#define M135 0x54
#define M357 0x15
#define M56 0x06
#define M5 0x04

__device__ int bitreverse(int tid)
{
  int revtid = tid;
  revtid = ((0xf0f0f0f0 & revtid) >> 4) | ((0x0f0f0f0f & revtid) << 4);
  revtid = ((0xcccccccc & revtid) >> 2) | ((0x33333333 & revtid) << 2);
  revtid = ((0xaaaaaaaa & revtid) >> 2) | ((0x55555555 & revtid));
  return revtid;
}

__global__ void FFT1D(float *real, float *img)
{
  float rVal[HEIGHT], iVal[HEIGHT];
  //assuming that thread block size is 128
  __shared__ float shReal[HEIGHT][TLEN];
  __shared__ float shImg[HEIGHT][TLEN];

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
    rVal[I] = real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
    iVal[I] = img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x];
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  if((threadIdx.x & STRIDE_STAGE_1) == STRIDE_STAGE_1)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_1] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_1] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_1] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_1] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_1] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_1] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_1] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_1] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_1] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_1] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_1] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_1] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_1] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_1] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_1] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_1] - iVal[7];
#endif
  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_1] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_1] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_1] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_1] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_1] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_1] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_1] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_1] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_1] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_1] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_1] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_1] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_1] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_1] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_1] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_1] + iVal[7];
#endif

  }

  if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
  {
    //calculate Q twiddle factor
    float Q = (float)((threadIdx.x & STRIDE_STAGE_1)>>1);
    Q = Q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 2
  if((threadIdx.x & STRIDE_STAGE_2) == STRIDE_STAGE_2)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_2] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_2] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_2] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_2] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_2] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_2] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_2] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_2] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_2] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_2] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_2] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_2] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_2] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_2] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_2] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_2] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_2] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_2] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_2] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_2] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_2] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_2] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_2] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_2] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_2] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_2] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_2] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_2] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_2] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_2] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_2] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_2] + iVal[7];
#endif

  }

  //end of stage 2
  //multiply with twiddle for beginning of stage 3
  //STRIDE_STAGE_3 16
  if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
  {
    //calculate Q twiddle factor
    float Q = (float)((threadIdx.x & STRIDE_STAGE_2) | ((threadIdx.x & STRIDE_STAGE_1)>>2));
    Q = Q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage3
  if((threadIdx.x & STRIDE_STAGE_3) == STRIDE_STAGE_3)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_3] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_3] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_3] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_3] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_3] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_3] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_3] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_3] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_3] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_3] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_3] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_3] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_3] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_3] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_3] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_3] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_3] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_3] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_3] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_3] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_3] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_3] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_3] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_3] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_3] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_3] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_3] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_3] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_3] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_3] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_3] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_3] + iVal[7];
#endif

  }
  //end of stage 3
  //multiply with twiddle for beginning of stage 4
  //STRIDE_STAGE_4 8
  if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
  {
    //calculate Q twiddle factor
    float Q = (float)(((threadIdx.x & STRIDE_STAGE_1)>>3) |
      ((threadIdx.x & STRIDE_STAGE_2)>>1) | ((threadIdx.x & STRIDE_STAGE_3)<<1));
    Q = Q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 4
  if((threadIdx.x & STRIDE_STAGE_4) == STRIDE_STAGE_4)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_4] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_4] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_4] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_4] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_4] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_4] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_4] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_4] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_4] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_4] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_4] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_4] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_4] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_4] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_4] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_4] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_4] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_4] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_4] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_4] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_4] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_4] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_4] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_4] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_4] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_4] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_4] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_4] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_4] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_4] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_4] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_4] + iVal[7];
#endif

  }
  //end of stage 4
  //multiply with twiddle for beginning of stage 5
  //STRIDE_STAGE_5 4
  if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
  {
    //calculate Q twiddle factor
    int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34);
    q = (q & M35) | ((q & M46)<<2);
    float Q = q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 5
  if((threadIdx.x & STRIDE_STAGE_5) == STRIDE_STAGE_5)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_5] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_5] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_5] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_5] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_5] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_5] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_5] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_5] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_5] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_5] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_5] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_5] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_5] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_5] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_5] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_5] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_5] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_5] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_5] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_5] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_5] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_5] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_5] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_5] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_5] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_5] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_5] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_5] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_5] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_5] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_5] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_5] + iVal[7];
#endif

  }
  //end of stage 5
  //multiply with twiddle for beginning of stage 6
  //STRIDE_STAGE_6 2
  if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
  {
    //calculate Q twiddle factor
    int q = ((threadIdx.x & M12)>>5) | ((threadIdx.x & M34)>>1) |
      ((threadIdx.x & M5)<<3);
    q = (q & M246) | ((q & M357)<<2);
    float Q = q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 6
  if((threadIdx.x & STRIDE_STAGE_6) == STRIDE_STAGE_6)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_6] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_6] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_6] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_6] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_6] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_6] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_6] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_6] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_6] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_6] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_6] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_6] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_6] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_6] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_6] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_6] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_6] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_6] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_6] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_6] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_6] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_6] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_6] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_6] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_6] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_6] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_6] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_6] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_6] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_6] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_6] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_6] + iVal[7];
#endif

  }
  //end of stage 6
  //multiply with twiddle for beginning of stage 7
  //STRIDE_STAGE_7 1
  if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
  {
    //calculate Q twiddle factor
    int q = ((threadIdx.x & M12)>>4) | (threadIdx.x & M34) |
      ((threadIdx.x & M56)<<4);
    q = ((q & M135)>>2) | (q & M246);
    float Q = q*NEG_2PI_BY_TLEN;

    float c, s, T;
    __sincosf(Q, &s, &c);

    #pragma unroll
    for(int I = 0; I < HEIGHT; I++)
    {
      T = rVal[I];
      rVal[I] = rVal[I]*c - iVal[I]*s;
      iVal[I] = T*s + iVal[I]*c;
    }
  }

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][threadIdx.x] = rVal[I];
  shImg[I][threadIdx.x] = iVal[I];
  }
  __syncthreads();

  //stage 7
  if((threadIdx.x & STRIDE_STAGE_7) == STRIDE_STAGE_7)
  {
      rVal[0] = shReal[0][threadIdx.x - STRIDE_STAGE_7] - rVal[0];
      iVal[0] = shImg[0][threadIdx.x - STRIDE_STAGE_7] - iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x - STRIDE_STAGE_7] - rVal[1];
      iVal[1] = shImg[1][threadIdx.x - STRIDE_STAGE_7] - iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x - STRIDE_STAGE_7] - rVal[2];
      iVal[2] = shImg[2][threadIdx.x - STRIDE_STAGE_7] - iVal[2];

      rVal[3] = shReal[3][threadIdx.x - STRIDE_STAGE_7] - rVal[3];
      iVal[3] = shImg[3][threadIdx.x - STRIDE_STAGE_7] - iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x - STRIDE_STAGE_7] - rVal[4];
      iVal[4] = shImg[4][threadIdx.x - STRIDE_STAGE_7] - iVal[4];

      rVal[5] = shReal[5][threadIdx.x - STRIDE_STAGE_7] - rVal[5];
      iVal[5] = shImg[5][threadIdx.x - STRIDE_STAGE_7] - iVal[5];

      rVal[6] = shReal[6][threadIdx.x - STRIDE_STAGE_7] - rVal[6];
      iVal[6] = shImg[6][threadIdx.x - STRIDE_STAGE_7] - iVal[6];

      rVal[7] = shReal[7][threadIdx.x - STRIDE_STAGE_7] - rVal[7];
      iVal[7] = shImg[7][threadIdx.x - STRIDE_STAGE_7] - iVal[7];
#endif

  }
else
  {
      rVal[0] = shReal[0][threadIdx.x + STRIDE_STAGE_7] + rVal[0];
      iVal[0] = shImg[0][threadIdx.x + STRIDE_STAGE_7] + iVal[0];

#if HEIGHT > 1
      rVal[1] = shReal[1][threadIdx.x + STRIDE_STAGE_7] + rVal[1];
      iVal[1] = shImg[1][threadIdx.x + STRIDE_STAGE_7] + iVal[1];
#endif

#if HEIGHT > 2
      rVal[2] = shReal[2][threadIdx.x + STRIDE_STAGE_7] + rVal[2];
      iVal[2] = shImg[2][threadIdx.x + STRIDE_STAGE_7] + iVal[2];

      rVal[3] = shReal[3][threadIdx.x + STRIDE_STAGE_7] + rVal[3];
      iVal[3] = shImg[3][threadIdx.x + STRIDE_STAGE_7] + iVal[3];
#endif

#if HEIGHT > 4
      rVal[4] = shReal[4][threadIdx.x + STRIDE_STAGE_7] + rVal[4];
      iVal[4] = shImg[4][threadIdx.x + STRIDE_STAGE_7] + iVal[4];

      rVal[5] = shReal[5][threadIdx.x + STRIDE_STAGE_7] + rVal[5];
      iVal[5] = shImg[5][threadIdx.x + STRIDE_STAGE_7] + iVal[5];

      rVal[6] = shReal[6][threadIdx.x + STRIDE_STAGE_7] + rVal[6];
      iVal[6] = shImg[6][threadIdx.x + STRIDE_STAGE_7] + iVal[6];

      rVal[7] = shReal[7][threadIdx.x + STRIDE_STAGE_7] + rVal[7];
      iVal[7] = shImg[7][threadIdx.x + STRIDE_STAGE_7] + iVal[7];
#endif

  }
  int revtid = bitreverse(threadIdx.x);
/*
  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
  shReal[I][revtid] = rVal[I];
  shImg[I][revtid] = iVal[I];
  }
*/
  shReal[0][revtid] = rVal[0];
  shImg[0][revtid] = iVal[0];
#if HEIGHT > 1
  shReal[1][revtid] = rVal[1];
  shImg[1][revtid] = iVal[1];
#endif

#if HEIGHT > 2
  shReal[2][revtid] = rVal[2];
  shImg[2][revtid] = iVal[2];
  shReal[3][revtid] = rVal[3];
  shImg[3][revtid] = iVal[3];
#endif

#if HEIGHT > 4
  shReal[4][revtid] = rVal[4];
  shImg[4][revtid] = iVal[4];
  shReal[5][revtid] = rVal[5];
  shImg[5][revtid] = iVal[5];
  shReal[6][revtid] = rVal[6];
  shImg[6][revtid] = iVal[6];
  shReal[7][revtid] = rVal[7];
  shImg[7][revtid] = iVal[7];
#endif

  __syncthreads();

  #pragma unroll
  for(int I = 0; I < HEIGHT; I++)
  {
    real[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shReal[I][threadIdx.x];
    img[((blockIdx.x*HEIGHT) + I)*blockDim.x + threadIdx.x] = shImg[I][threadIdx.x];
  }
}

__global__ void transposeDiagonal_xy(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_y;

  // do diagonal reordering
  blockIdx_y = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
  int index_in = xIndex + (yIndex + blockIdx.z*width)*width;

  xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
  yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
  int index_out = xIndex + (yIndex + blockIdx.z*width)*width;

  tile[threadIdx.y][threadIdx.x] = idatar[index_in];
  __syncthreads();
  odatar[index_out] = tile[threadIdx.x][threadIdx.y];
  __syncthreads();
  tile[threadIdx.y][threadIdx.x] = idatai[index_in];
  __syncthreads();
  odatai[index_out] = tile[threadIdx.x][threadIdx.y];
}

__global__ void transposeDiagonal_xz(float *odatar, float *odatai, float *idatar, float *idatai, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_z;

  // do diagonal reordering
  blockIdx_z = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
  int index_in = xIndex + (blockIdx.y + zIndex*width)*width;

  xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
  zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
  int index_out = xIndex + (blockIdx.y + zIndex*width)*width;

  tile[threadIdx.z][threadIdx.x] = idatar[index_in];
  __syncthreads();
  odatar[index_out] = tile[threadIdx.x][threadIdx.z];
  __syncthreads();
  tile[threadIdx.z][threadIdx.x] = idatai[index_in];
  __syncthreads();
  odatai[index_out] = tile[threadIdx.x][threadIdx.z];
}

__global__ void transposeDiagonal_xy(float *odata, float *idata, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_y;

  // do diagonal reordering
  blockIdx_y = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.y)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int yIndex = blockIdx_y * TILE_DIM + threadIdx.y;
  int index_in = xIndex + (yIndex + blockIdx.z*width)*width;

  xIndex = blockIdx_y * TILE_DIM + threadIdx.x;
  yIndex = blockIdx_x * TILE_DIM + threadIdx.y;
  int index_out = xIndex + (yIndex + blockIdx.z*width)*width;

  tile[threadIdx.y][threadIdx.x] = idata[index_in];
  __syncthreads();
  odata[index_out] = tile[threadIdx.x][threadIdx.y];
}

__global__ void transposeDiagonal_xz(float *odata, float *idata, int width)
{
  __shared__ float tile[TILE_DIM][TILE_DIM+1];

  int blockIdx_x, blockIdx_z;

  // do diagonal reordering
  blockIdx_z = blockIdx.x;
  blockIdx_x = (blockIdx.x+blockIdx.z)%gridDim.x;

  // from here on the code is same as previous kernel except blockIdx_x replaces blockIdx.x
  // and similarly for y

  int xIndex = blockIdx_x * TILE_DIM + threadIdx.x;
  int zIndex = blockIdx_z * TILE_DIM + threadIdx.z;
  int index_in = xIndex + (blockIdx.y + zIndex*width)*width;

  xIndex = blockIdx_z * TILE_DIM + threadIdx.x;
  zIndex = blockIdx_x * TILE_DIM + threadIdx.z;
  int index_out = xIndex + (blockIdx.y + zIndex*width)*width;

  tile[threadIdx.z][threadIdx.x] = idata[index_in];
  __syncthreads();
  odata[index_out] = tile[threadIdx.x][threadIdx.z];
}

	.text
	.file	"fft.hip"
	.globl	_Z20__device_stub__FFT1DPfS_    # -- Begin function _Z20__device_stub__FFT1DPfS_
	.type	_Z20__device_stub__FFT1DPfS_,@function
_Z20__device_stub__FFT1DPfS_:           # @_Z20__device_stub__FFT1DPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5FFT1DPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__FFT1DPfS_, .Lfunc_end0-_Z20__device_stub__FFT1DPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i # -- Begin function _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
	.type	_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i,@function
_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i: # @_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20transposeDiagonal_xyPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i, .Lfunc_end1-_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i # -- Begin function _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
	.type	_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i,@function
_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i: # @_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20transposeDiagonal_xzPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i, .Lfunc_end2-_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__transposeDiagonal_xyPfS_i # -- Begin function _Z35__device_stub__transposeDiagonal_xyPfS_i
	.type	_Z35__device_stub__transposeDiagonal_xyPfS_i,@function
_Z35__device_stub__transposeDiagonal_xyPfS_i: # @_Z35__device_stub__transposeDiagonal_xyPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20transposeDiagonal_xyPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z35__device_stub__transposeDiagonal_xyPfS_i, .Lfunc_end3-_Z35__device_stub__transposeDiagonal_xyPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__transposeDiagonal_xzPfS_i # -- Begin function _Z35__device_stub__transposeDiagonal_xzPfS_i
	.type	_Z35__device_stub__transposeDiagonal_xzPfS_i,@function
_Z35__device_stub__transposeDiagonal_xzPfS_i: # @_Z35__device_stub__transposeDiagonal_xzPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20transposeDiagonal_xzPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z35__device_stub__transposeDiagonal_xzPfS_i, .Lfunc_end4-_Z35__device_stub__transposeDiagonal_xzPfS_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5FFT1DPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20transposeDiagonal_xyPfS_S_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20transposeDiagonal_xzPfS_S_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20transposeDiagonal_xyPfS_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20transposeDiagonal_xzPfS_i, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5FFT1DPfS_,@object            # @_Z5FFT1DPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z5FFT1DPfS_
	.p2align	3, 0x0
_Z5FFT1DPfS_:
	.quad	_Z20__device_stub__FFT1DPfS_
	.size	_Z5FFT1DPfS_, 8

	.type	_Z20transposeDiagonal_xyPfS_S_S_i,@object # @_Z20transposeDiagonal_xyPfS_S_S_i
	.globl	_Z20transposeDiagonal_xyPfS_S_S_i
	.p2align	3, 0x0
_Z20transposeDiagonal_xyPfS_S_S_i:
	.quad	_Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
	.size	_Z20transposeDiagonal_xyPfS_S_S_i, 8

	.type	_Z20transposeDiagonal_xzPfS_S_S_i,@object # @_Z20transposeDiagonal_xzPfS_S_S_i
	.globl	_Z20transposeDiagonal_xzPfS_S_S_i
	.p2align	3, 0x0
_Z20transposeDiagonal_xzPfS_S_S_i:
	.quad	_Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
	.size	_Z20transposeDiagonal_xzPfS_S_S_i, 8

	.type	_Z20transposeDiagonal_xyPfS_i,@object # @_Z20transposeDiagonal_xyPfS_i
	.globl	_Z20transposeDiagonal_xyPfS_i
	.p2align	3, 0x0
_Z20transposeDiagonal_xyPfS_i:
	.quad	_Z35__device_stub__transposeDiagonal_xyPfS_i
	.size	_Z20transposeDiagonal_xyPfS_i, 8

	.type	_Z20transposeDiagonal_xzPfS_i,@object # @_Z20transposeDiagonal_xzPfS_i
	.globl	_Z20transposeDiagonal_xzPfS_i
	.p2align	3, 0x0
_Z20transposeDiagonal_xzPfS_i:
	.quad	_Z35__device_stub__transposeDiagonal_xzPfS_i
	.size	_Z20transposeDiagonal_xzPfS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5FFT1DPfS_"
	.size	.L__unnamed_1, 13

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z20transposeDiagonal_xyPfS_S_S_i"
	.size	.L__unnamed_2, 34

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z20transposeDiagonal_xzPfS_S_S_i"
	.size	.L__unnamed_3, 34

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z20transposeDiagonal_xyPfS_i"
	.size	.L__unnamed_4, 30

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z20transposeDiagonal_xzPfS_i"
	.size	.L__unnamed_5, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__FFT1DPfS_
	.addrsig_sym _Z35__device_stub__transposeDiagonal_xyPfS_S_S_i
	.addrsig_sym _Z35__device_stub__transposeDiagonal_xzPfS_S_S_i
	.addrsig_sym _Z35__device_stub__transposeDiagonal_xyPfS_i
	.addrsig_sym _Z35__device_stub__transposeDiagonal_xzPfS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5FFT1DPfS_
	.addrsig_sym _Z20transposeDiagonal_xyPfS_S_S_i
	.addrsig_sym _Z20transposeDiagonal_xzPfS_S_S_i
	.addrsig_sym _Z20transposeDiagonal_xyPfS_i
	.addrsig_sym _Z20transposeDiagonal_xzPfS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5FFT1DPfS_            ; -- Begin function _Z5FFT1DPfS_
	.globl	_Z5FFT1DPfS_
	.p2align	8
	.type	_Z5FFT1DPfS_,@function
_Z5FFT1DPfS_:                           ; @_Z5FFT1DPfS_
; %bb.0:                                ; %.preheader
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_lshl_b32 s2, s15, 3
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr29
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_co_u32 v7, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v3
	v_add_nc_u32_e32 v1, s3, v1
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v3, v[7:8], off
	global_load_b32 v12, v[9:10], off
	v_lshlrev_b64 v[14:15], 2, v[1:2]
	v_add_co_u32 v7, vcc_lo, s4, v5
	v_add_nc_u32_e32 v1, s3, v1
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_add_co_u32 v6, vcc_lo, s4, v14
	global_load_b32 v13, v[7:8], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v15, vcc_lo
	v_add_nc_u32_e32 v1, s3, v1
	v_add_co_u32 v16, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v15, vcc_lo
	v_add_co_u32 v18, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v14, v[4:5], off
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	global_load_b32 v15, v[6:7], off
	global_load_b32 v16, v[16:17], off
	global_load_b32 v17, v[18:19], off
	v_add_co_u32 v6, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v8, vcc_lo, s4, v4
	v_lshlrev_b64 v[10:11], 2, v[1:2]
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	v_add_nc_u32_e32 v1, s3, v1
	v_add_co_u32 v20, vcc_lo, s4, v10
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v11, vcc_lo
	global_load_b32 v18, v[6:7], off
	global_load_b32 v19, v[8:9], off
	global_load_b32 v25, v[4:5], off
	global_load_b32 v28, v[20:21], off
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_nc_u32_e32 v1, s3, v1
	v_add_co_u32 v6, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s4, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v31, v[6:7], off
	global_load_b32 v32, v[8:9], off
	global_load_b32 v33, v[4:5], off
	global_load_b32 v30, v[10:11], off
	global_load_b32 v34, v[1:2], off
	v_lshlrev_b32_e32 v1, 2, v0
	v_and_b32_e32 v4, 64, v0
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr11
	s_waitcnt vmcnt(13)
	ds_store_2addr_stride64_b32 v1, v3, v13 offset0:16 offset1:18
	s_waitcnt vmcnt(12)
	ds_store_2addr_stride64_b32 v1, v12, v14 offset1:2
	s_waitcnt vmcnt(9)
	ds_store_2addr_stride64_b32 v1, v15, v17 offset0:20 offset1:22
	s_waitcnt vmcnt(8)
	ds_store_2addr_stride64_b32 v1, v16, v18 offset0:4 offset1:6
	s_waitcnt vmcnt(5)
	ds_store_2addr_stride64_b32 v1, v19, v28 offset0:24 offset1:26
	s_waitcnt vmcnt(4)
	ds_store_2addr_stride64_b32 v1, v25, v31 offset0:8 offset1:10
	s_waitcnt vmcnt(1)
	ds_store_2addr_stride64_b32 v1, v32, v30 offset0:28 offset1:30
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v1, v33, v34 offset0:12 offset1:14
	v_or_b32_e32 v2, 0x1000, v1
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	ds_load_2addr_stride64_b32 v[4:5], v2 offset0:1 offset1:3
	ds_load_2addr_stride64_b32 v[6:7], v1 offset0:1 offset1:3
	ds_load_2addr_stride64_b32 v[20:21], v2 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[35:36], v1 offset0:5 offset1:7
	v_add_nc_u32_e32 v8, 0xffffff00, v2
	v_add_nc_u32_e32 v9, 0xffffff00, v1
	s_waitcnt lgkmcnt(2)
	v_dual_sub_f32 v27, v5, v15 :: v_dual_sub_f32 v10, v6, v14
	ds_load_2addr_stride64_b32 v[37:38], v2 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[39:40], v1 offset0:9 offset1:11
	ds_load_b32 v11, v8
	ds_load_b32 v9, v9
	ds_load_b32 v41, v2 offset:3328
	ds_load_b32 v42, v1 offset:3328
	s_waitcnt lgkmcnt(7)
	v_dual_sub_f32 v26, v4, v13 :: v_dual_sub_f32 v23, v21, v19
	s_waitcnt lgkmcnt(6)
	v_dual_sub_f32 v8, v7, v16 :: v_dual_sub_f32 v5, v36, v25
	v_sub_f32_e32 v24, v20, v17
	v_sub_f32_e32 v4, v35, v18
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr25
	s_waitcnt lgkmcnt(5)
	v_sub_f32_e32 v22, v37, v28
	s_waitcnt lgkmcnt(4)
	v_sub_f32_e32 v6, v39, v31
	v_dual_sub_f32 v20, v38, v32 :: v_dual_sub_f32 v7, v40, v33
	s_waitcnt lgkmcnt(1)
	v_sub_f32_e32 v21, v41, v30
	v_sub_f32_e32 v29, v11, v3
	v_sub_f32_e32 v11, v9, v12
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v9, v42, v34
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr34
.LBB0_2:                                ; %Flow1122
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_4
; %bb.3:
	ds_load_2addr_stride64_b32 v[4:5], v1 offset0:17 offset1:19
	ds_load_2addr_stride64_b32 v[6:7], v1 offset0:1 offset1:3
	ds_load_2addr_stride64_b32 v[8:9], v1 offset0:21 offset1:23
	ds_load_2addr_stride64_b32 v[20:21], v1 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[35:36], v1 offset0:25 offset1:27
	ds_load_2addr_stride64_b32 v[37:38], v1 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[39:40], v1 offset0:29 offset1:31
	ds_load_2addr_stride64_b32 v[41:42], v1 offset0:13 offset1:15
	s_waitcnt lgkmcnt(7)
	v_dual_add_f32 v29, v3, v4 :: v_dual_add_f32 v26, v13, v5
	s_waitcnt lgkmcnt(6)
	v_dual_add_f32 v11, v12, v6 :: v_dual_add_f32 v10, v14, v7
	s_waitcnt lgkmcnt(5)
	v_dual_add_f32 v27, v15, v8 :: v_dual_add_f32 v24, v17, v9
	s_waitcnt lgkmcnt(3)
	v_dual_add_f32 v8, v16, v20 :: v_dual_add_f32 v23, v19, v35
	v_add_f32_e32 v4, v18, v21
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v5, v25, v37 :: v_dual_add_f32 v22, v28, v36
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v6, v31, v38 :: v_dual_add_f32 v7, v33, v41
	v_dual_add_f32 v20, v32, v39 :: v_dual_add_f32 v21, v30, v40
	v_add_f32_e32 v9, v34, v42
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s3
	v_and_b32_e32 v31, 32, v0
	v_lshrrev_b32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v31
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:                                ; %.loopexit273.loopexit
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v12, 32, v3
	v_cvt_f32_ubyte0_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, 0xbd490fdb, v12
	v_mul_f32_e32 v12, 0.15915494, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_sin_f32_e32 v13, v12
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v25, v13, v7
	v_cos_f32_e32 v12, v12
	v_mul_f32_e32 v14, v13, v11
	v_mul_f32_e32 v15, v13, v10
	v_mul_f32_e32 v18, v13, v5
	v_mul_f32_e32 v19, v13, v6
	v_mul_f32_e32 v16, v13, v8
	v_mul_f32_e32 v17, v13, v4
	s_delay_alu instid0(TRANS32_DEP_1)
	v_mul_f32_e32 v7, v12, v7
	v_mul_f32_e32 v11, v12, v11
	v_mul_f32_e32 v10, v12, v10
	v_mul_f32_e32 v5, v12, v5
	v_fma_f32 v14, v12, v29, -v14
	v_mul_f32_e32 v28, v13, v9
	v_dual_mul_f32 v8, v12, v8 :: v_dual_fmac_f32 v11, v13, v29
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mul_f32 v4, v12, v4 :: v_dual_fmac_f32 v5, v13, v23
	v_dual_mul_f32 v6, v12, v6 :: v_dual_fmac_f32 v7, v13, v20
	v_dual_mul_f32 v9, v12, v9 :: v_dual_fmac_f32 v10, v13, v26
	v_fma_f32 v15, v12, v26, -v15
	v_fma_f32 v16, v12, v27, -v16
	v_fma_f32 v17, v12, v24, -v17
	v_fma_f32 v18, v12, v23, -v18
	v_fma_f32 v19, v12, v22, -v19
	v_fma_f32 v25, v12, v20, -v25
	v_mov_b32_e32 v29, v14
	v_fma_f32 v12, v12, v21, -v28
	v_dual_fmac_f32 v8, v13, v27 :: v_dual_mov_b32 v27, v16
	v_dual_fmac_f32 v4, v13, v24 :: v_dual_mov_b32 v23, v18
	v_fmac_f32_e32 v6, v13, v22
	v_dual_fmac_f32 v9, v13, v21 :: v_dual_mov_b32 v26, v15
	v_mov_b32_e32 v24, v17
	v_mov_b32_e32 v22, v19
	v_dual_mov_b32 v20, v25 :: v_dual_mov_b32 v21, v12
.LBB0_6:                                ; %.loopexit273
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_2addr_stride64_b32 v2, v29, v26 offset1:2
	ds_store_2addr_stride64_b32 v1, v11, v10 offset1:2
	ds_store_2addr_stride64_b32 v2, v27, v24 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v1, v8, v4 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v2, v23, v22 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v1, v5, v6 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v2, v20, v21 offset0:12 offset1:14
	ds_store_2addr_stride64_b32 v1, v7, v9 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_8
; %bb.7:
	ds_load_2addr_b32 v[13:14], v2 offset0:96 offset1:224
	ds_load_2addr_b32 v[15:16], v1 offset0:96 offset1:224
	v_add_nc_u32_e32 v12, 0xffffff80, v2
	v_add_nc_u32_e32 v17, 0xffffff80, v1
	v_add_nc_u32_e32 v19, 0x80, v2
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v36, v13, v26 :: v_dual_add_nc_u32 v25, 0x80, v1
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v35, v14, v27 :: v_dual_sub_f32 v14, v16, v8
	ds_load_b32 v12, v12
	ds_load_b32 v28, v17
	ds_load_2addr_stride64_b32 v[17:18], v19 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[32:33], v25 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[38:39], v19 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[40:41], v25 offset0:9 offset1:11
	ds_load_b32 v19, v2 offset:3456
	ds_load_b32 v42, v1 offset:3456
	v_sub_f32_e32 v13, v15, v10
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr27
	s_waitcnt lgkmcnt(7)
	v_sub_f32_e32 v37, v12, v29
	s_waitcnt lgkmcnt(6)
	v_sub_f32_e32 v12, v28, v11
	s_waitcnt lgkmcnt(5)
	v_sub_f32_e32 v34, v17, v24
	s_waitcnt lgkmcnt(4)
	v_dual_sub_f32 v15, v32, v4 :: v_dual_sub_f32 v16, v33, v5
	v_sub_f32_e32 v32, v18, v23
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v30, v38, v22 :: v_dual_sub_f32 v25, v19, v21
	v_dual_sub_f32 v17, v40, v6 :: v_dual_sub_f32 v28, v39, v20
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v18, v41, v7 :: v_dual_sub_f32 v19, v42, v9
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
.LBB0_8:                                ; %Flow1121
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_add_nc_u32_e32 v25, 0x80, v1
	ds_load_2addr_b32 v[12:13], v1 offset0:32 offset1:160
	ds_load_2addr_stride64_b32 v[14:15], v25 offset0:16 offset1:18
	ds_load_2addr_stride64_b32 v[16:17], v25 offset0:20 offset1:22
	ds_load_2addr_stride64_b32 v[18:19], v25 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[32:33], v25 offset0:24 offset1:26
	ds_load_2addr_stride64_b32 v[38:39], v25 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[40:41], v25 offset0:28 offset1:30
	ds_load_2addr_stride64_b32 v[42:43], v25 offset0:12 offset1:14
	s_waitcnt lgkmcnt(7)
	v_dual_add_f32 v12, v11, v12 :: v_dual_add_f32 v13, v10, v13
	s_waitcnt lgkmcnt(6)
	v_dual_add_f32 v37, v29, v14 :: v_dual_add_f32 v36, v26, v15
	s_waitcnt lgkmcnt(5)
	v_dual_add_f32 v35, v27, v16 :: v_dual_add_f32 v34, v24, v17
	s_waitcnt lgkmcnt(4)
	v_add_f32_e32 v14, v8, v18
	s_waitcnt lgkmcnt(3)
	v_dual_add_f32 v15, v4, v19 :: v_dual_add_f32 v32, v23, v32
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v16, v5, v38 :: v_dual_add_f32 v17, v6, v39
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v30, v22, v33 :: v_dual_add_f32 v19, v9, v43
	v_dual_add_f32 v28, v20, v40 :: v_dual_add_f32 v25, v21, v41
	v_add_f32_e32 v18, v7, v42
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s3
	v_and_b32_e32 v4, 16, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.11:                               ; %.loopexit272.loopexit
	v_lshrrev_b32_e32 v4, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v4, v4, 16, v31
	v_cvt_f32_ubyte0_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0xbd490fdb, v4
	v_mul_f32_e32 v4, 0.15915494, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_sin_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v5, v15
	v_cos_f32_e32 v4, v4
	v_mul_f32_e32 v6, v5, v12
	v_mul_f32_e32 v7, v5, v13
	v_mul_f32_e32 v8, v5, v14
	v_mul_f32_e32 v10, v5, v16
	v_mul_f32_e32 v20, v5, v18
	v_mul_f32_e32 v11, v5, v17
	v_mul_f32_e32 v21, v5, v19
	s_delay_alu instid0(TRANS32_DEP_1)
	v_mul_f32_e32 v19, v4, v19
	v_mul_f32_e32 v12, v4, v12
	v_mul_f32_e32 v14, v4, v14
	v_mul_f32_e32 v13, v4, v13
	v_mul_f32_e32 v15, v4, v15
	v_mul_f32_e32 v16, v4, v16
	v_mul_f32_e32 v17, v4, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mul_f32 v18, v4, v18 :: v_dual_fmac_f32 v13, v5, v36
	v_fma_f32 v6, v4, v37, -v6
	v_fma_f32 v7, v4, v36, -v7
	v_fma_f32 v8, v4, v35, -v8
	v_fma_f32 v9, v4, v34, -v9
	v_fma_f32 v10, v4, v32, -v10
	v_fma_f32 v11, v4, v30, -v11
	v_fma_f32 v20, v4, v28, -v20
	v_fma_f32 v4, v4, v25, -v21
	v_dual_fmac_f32 v12, v5, v37 :: v_dual_mov_b32 v37, v6
	v_dual_fmac_f32 v14, v5, v35 :: v_dual_mov_b32 v35, v8
	v_fmac_f32_e32 v15, v5, v34
	v_fmac_f32_e32 v16, v5, v32
	v_dual_fmac_f32 v17, v5, v30 :: v_dual_mov_b32 v36, v7
	v_fmac_f32_e32 v18, v5, v28
	v_dual_fmac_f32 v19, v5, v25 :: v_dual_mov_b32 v32, v10
	v_mov_b32_e32 v34, v9
	v_mov_b32_e32 v30, v11
	v_mov_b32_e32 v28, v20
	v_mov_b32_e32 v25, v4
.LBB0_12:                               ; %.loopexit272
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_2addr_stride64_b32 v2, v37, v36 offset1:2
	ds_store_2addr_stride64_b32 v1, v12, v13 offset1:2
	ds_store_2addr_stride64_b32 v2, v35, v34 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v1, v14, v15 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v2, v32, v30 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v1, v16, v17 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v2, v28, v25 offset0:12 offset1:14
	ds_store_2addr_stride64_b32 v1, v18, v19 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_14
; %bb.13:
	ds_load_2addr_b32 v[5:6], v2 offset0:112 offset1:240
	ds_load_2addr_b32 v[7:8], v1 offset0:112 offset1:240
	v_subrev_nc_u32_e32 v4, 64, v2
	v_subrev_nc_u32_e32 v9, 64, v1
	v_add_nc_u32_e32 v11, 0xc0, v2
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v31, v5, v36 :: v_dual_add_nc_u32 v24, 0xc0, v1
	ds_load_b32 v4, v4
	ds_load_b32 v26, v9
	ds_load_2addr_stride64_b32 v[9:10], v11 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[20:21], v24 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[22:23], v11 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[38:39], v24 offset0:9 offset1:11
	ds_load_b32 v11, v2 offset:3520
	ds_load_b32 v40, v1 offset:3520
	s_waitcnt lgkmcnt(8)
	v_sub_f32_e32 v5, v7, v13
	v_dual_sub_f32 v29, v6, v35 :: v_dual_sub_f32 v6, v8, v14
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr35
	s_waitcnt lgkmcnt(6)
	v_dual_sub_f32 v33, v4, v37 :: v_dual_sub_f32 v4, v26, v12
	s_waitcnt lgkmcnt(5)
	v_dual_sub_f32 v26, v10, v32 :: v_dual_sub_f32 v27, v9, v34
	s_waitcnt lgkmcnt(3)
	v_dual_sub_f32 v7, v20, v15 :: v_dual_sub_f32 v24, v22, v30
	s_waitcnt lgkmcnt(2)
	v_dual_sub_f32 v8, v21, v16 :: v_dual_sub_f32 v9, v38, v17
	v_sub_f32_e32 v10, v39, v18
	v_sub_f32_e32 v23, v23, v28
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v22, v11, v25 :: v_dual_sub_f32 v11, v40, v19
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr25
.LBB0_14:                               ; %Flow1120
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_add_nc_u32_e32 v24, 64, v1
	ds_load_2addr_b32 v[4:5], v1 offset0:16 offset1:144
	ds_load_2addr_stride64_b32 v[6:7], v24 offset0:16 offset1:18
	ds_load_2addr_stride64_b32 v[8:9], v24 offset0:20 offset1:22
	ds_load_2addr_stride64_b32 v[10:11], v24 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[20:21], v24 offset0:24 offset1:26
	ds_load_2addr_stride64_b32 v[22:23], v24 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[38:39], v24 offset0:28 offset1:30
	ds_load_2addr_stride64_b32 v[40:41], v24 offset0:12 offset1:14
	s_waitcnt lgkmcnt(7)
	v_dual_add_f32 v4, v12, v4 :: v_dual_add_f32 v5, v13, v5
	s_waitcnt lgkmcnt(6)
	v_add_f32_e32 v33, v37, v6
	s_waitcnt lgkmcnt(4)
	v_dual_add_f32 v31, v36, v7 :: v_dual_add_f32 v6, v14, v10
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v29, v35, v8 :: v_dual_add_f32 v8, v16, v22
	v_dual_add_f32 v27, v34, v9 :: v_dual_add_f32 v26, v32, v20
	v_dual_add_f32 v7, v15, v11 :: v_dual_add_f32 v24, v30, v21
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v9, v17, v23 :: v_dual_add_f32 v10, v18, v40
	v_dual_add_f32 v23, v28, v38 :: v_dual_add_f32 v22, v25, v39
	v_add_f32_e32 v11, v19, v41
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s3
	v_and_b32_e32 v12, 8, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v12
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_18
; %bb.17:                               ; %.loopexit271.loopexit
	v_lshrrev_b32_e32 v12, 3, v0
	v_lshlrev_b32_e32 v13, 1, v0
	v_and_b32_e32 v14, 16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v12, 8, v12
	v_and_b32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, v14, v13
	v_cvt_f32_ubyte0_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, 0xbd490fdb, v12
	v_mul_f32_e32 v12, 0.15915494, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_sin_f32_e32 v13, v12
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v19, v13, v9
	v_cos_f32_e32 v12, v12
	v_mul_f32_e32 v14, v13, v4
	v_mul_f32_e32 v15, v13, v5
	v_mul_f32_e32 v16, v13, v6
	v_mul_f32_e32 v17, v13, v7
	v_mul_f32_e32 v18, v13, v8
	v_mul_f32_e32 v20, v13, v10
	v_mul_f32_e32 v21, v13, v11
	s_delay_alu instid0(TRANS32_DEP_1)
	v_mul_f32_e32 v11, v12, v11
	v_mul_f32_e32 v4, v12, v4
	v_mul_f32_e32 v5, v12, v5
	v_mul_f32_e32 v6, v12, v6
	v_mul_f32_e32 v7, v12, v7
	v_mul_f32_e32 v8, v12, v8
	v_mul_f32_e32 v9, v12, v9
	v_dual_fmac_f32 v5, v13, v31 :: v_dual_mul_f32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v7, v13, v27
	v_fma_f32 v14, v12, v33, -v14
	v_fma_f32 v15, v12, v31, -v15
	v_fma_f32 v16, v12, v29, -v16
	v_fma_f32 v17, v12, v27, -v17
	v_fma_f32 v18, v12, v26, -v18
	v_fma_f32 v19, v12, v24, -v19
	v_fma_f32 v20, v12, v23, -v20
	v_fma_f32 v12, v12, v22, -v21
	v_dual_fmac_f32 v4, v13, v33 :: v_dual_mov_b32 v33, v14
	v_dual_fmac_f32 v6, v13, v29 :: v_dual_mov_b32 v31, v15
	v_dual_fmac_f32 v8, v13, v26 :: v_dual_mov_b32 v29, v16
	v_dual_fmac_f32 v9, v13, v24 :: v_dual_mov_b32 v26, v18
	v_dual_fmac_f32 v10, v13, v23 :: v_dual_mov_b32 v23, v20
	v_dual_fmac_f32 v11, v13, v22 :: v_dual_mov_b32 v24, v19
	v_dual_mov_b32 v27, v17 :: v_dual_mov_b32 v22, v12
.LBB0_18:                               ; %.loopexit271
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_2addr_stride64_b32 v2, v33, v31 offset1:2
	ds_store_2addr_stride64_b32 v1, v4, v5 offset1:2
	ds_store_2addr_stride64_b32 v2, v29, v27 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v1, v6, v7 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v2, v26, v24 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v1, v8, v9 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v2, v23, v22 offset0:12 offset1:14
	ds_store_2addr_stride64_b32 v1, v10, v11 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr14
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_20
; %bb.19:
	ds_load_2addr_b32 v[12:13], v2 offset0:120 offset1:248
	ds_load_2addr_b32 v[15:16], v1 offset0:120 offset1:248
	v_subrev_nc_u32_e32 v14, 32, v2
	v_subrev_nc_u32_e32 v17, 32, v1
	v_add_nc_u32_e32 v21, 0xe0, v2
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v36, v12, v31 :: v_dual_add_nc_u32 v25, 0xe0, v1
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v16, v16, v6
	ds_load_b32 v14, v14
	ds_load_b32 v28, v17
	ds_load_2addr_stride64_b32 v[17:18], v21 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[19:20], v25 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[38:39], v21 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[40:41], v25 offset0:9 offset1:11
	ds_load_b32 v21, v2 offset:3552
	ds_load_b32 v42, v1 offset:3552
	v_sub_f32_e32 v15, v15, v5
	v_sub_f32_e32 v35, v13, v29
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr29
	s_waitcnt lgkmcnt(6)
	v_dual_sub_f32 v37, v14, v33 :: v_dual_sub_f32 v14, v28, v4
	s_waitcnt lgkmcnt(5)
	v_sub_f32_e32 v34, v17, v27
	s_waitcnt lgkmcnt(4)
	v_dual_sub_f32 v17, v19, v7 :: v_dual_sub_f32 v32, v18, v26
	v_sub_f32_e32 v18, v20, v8
	s_waitcnt lgkmcnt(2)
	v_dual_sub_f32 v30, v38, v24 :: v_dual_sub_f32 v19, v40, v9
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v28, v39, v23 :: v_dual_sub_f32 v25, v21, v22
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v20, v41, v10 :: v_dual_sub_f32 v21, v42, v11
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
.LBB0_20:                               ; %Flow1119
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_add_nc_u32_e32 v14, 32, v1
	ds_load_2addr_b32 v[12:13], v1 offset0:8 offset1:136
	ds_load_2addr_stride64_b32 v[16:17], v14 offset0:16 offset1:18
	ds_load_2addr_stride64_b32 v[18:19], v14 offset0:20 offset1:22
	ds_load_2addr_stride64_b32 v[20:21], v14 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[38:39], v14 offset0:24 offset1:26
	ds_load_2addr_stride64_b32 v[40:41], v14 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[42:43], v14 offset0:28 offset1:30
	ds_load_2addr_stride64_b32 v[44:45], v14 offset0:12 offset1:14
	s_waitcnt lgkmcnt(7)
	v_dual_add_f32 v14, v4, v12 :: v_dual_add_f32 v15, v5, v13
	s_waitcnt lgkmcnt(6)
	v_dual_add_f32 v37, v33, v16 :: v_dual_add_f32 v36, v31, v17
	s_waitcnt lgkmcnt(4)
	v_dual_add_f32 v35, v29, v18 :: v_dual_add_f32 v16, v6, v20
	v_add_f32_e32 v17, v7, v21
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v34, v27, v19 :: v_dual_add_f32 v19, v9, v41
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v32, v26, v38 :: v_dual_add_f32 v21, v11, v45
	v_dual_add_f32 v18, v8, v40 :: v_dual_add_f32 v25, v22, v43
	v_add_f32_e32 v30, v24, v39
	v_add_f32_e32 v28, v23, v42
	v_add_f32_e32 v20, v10, v44
.LBB0_22:
	s_or_b32 exec_lo, exec_lo, s3
	v_and_b32_e32 v5, 4, v0
	v_lshrrev_b32_e32 v4, 4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	v_and_b32_e32 v5, 24, v0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_24
; %bb.23:                               ; %.loopexit270.loopexit
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v6, v4, 6, v5
	v_and_b32_e32 v7, 20, v6
	v_lshlrev_b32_e32 v6, 2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v6, v6, 40, v7
	v_cvt_f32_ubyte0_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, 0xbd490fdb, v6
	v_mul_f32_e32 v6, 0.15915494, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_sin_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v13, v7, v19
	v_cos_f32_e32 v6, v6
	v_mul_f32_e32 v8, v7, v14
	v_mul_f32_e32 v9, v7, v15
	v_mul_f32_e32 v10, v7, v16
	v_mul_f32_e32 v11, v7, v17
	v_mul_f32_e32 v12, v7, v18
	v_mul_f32_e32 v22, v7, v20
	v_mul_f32_e32 v23, v7, v21
	s_delay_alu instid0(TRANS32_DEP_1)
	v_mul_f32_e32 v21, v6, v21
	v_mul_f32_e32 v14, v6, v14
	v_mul_f32_e32 v15, v6, v15
	v_mul_f32_e32 v16, v6, v16
	v_mul_f32_e32 v17, v6, v17
	v_mul_f32_e32 v18, v6, v18
	v_mul_f32_e32 v19, v6, v19
	v_fmac_f32_e32 v15, v7, v36
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mul_f32 v20, v6, v20 :: v_dual_fmac_f32 v17, v7, v34
	v_fma_f32 v8, v6, v37, -v8
	v_fma_f32 v9, v6, v36, -v9
	v_fma_f32 v10, v6, v35, -v10
	v_fma_f32 v11, v6, v34, -v11
	v_fma_f32 v12, v6, v32, -v12
	v_fma_f32 v13, v6, v30, -v13
	v_fma_f32 v22, v6, v28, -v22
	v_fma_f32 v6, v6, v25, -v23
	v_dual_fmac_f32 v14, v7, v37 :: v_dual_mov_b32 v37, v8
	v_dual_fmac_f32 v16, v7, v35 :: v_dual_mov_b32 v35, v10
	v_fmac_f32_e32 v18, v7, v32
	v_dual_fmac_f32 v19, v7, v30 :: v_dual_mov_b32 v36, v9
	v_fmac_f32_e32 v20, v7, v28
	v_dual_fmac_f32 v21, v7, v25 :: v_dual_mov_b32 v32, v12
	v_mov_b32_e32 v34, v11
	v_mov_b32_e32 v30, v13
	v_mov_b32_e32 v28, v22
	v_mov_b32_e32 v25, v6
.LBB0_24:                               ; %.loopexit270
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_2addr_stride64_b32 v2, v37, v36 offset1:2
	ds_store_2addr_stride64_b32 v1, v14, v15 offset1:2
	ds_store_2addr_stride64_b32 v2, v35, v34 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v1, v16, v17 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v2, v32, v30 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v1, v18, v19 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v2, v28, v25 offset0:12 offset1:14
	ds_store_2addr_stride64_b32 v1, v20, v21 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_26
; %bb.25:
	ds_load_2addr_b32 v[7:8], v2 offset0:124 offset1:252
	ds_load_2addr_b32 v[9:10], v1 offset0:124 offset1:252
	v_add_nc_u32_e32 v6, -16, v2
	v_add_nc_u32_e32 v11, -16, v1
	v_add_nc_u32_e32 v13, 0xf0, v2
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v31, v7, v36 :: v_dual_add_nc_u32 v24, 0xf0, v1
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v7, v9, v15
	v_dual_sub_f32 v29, v8, v35 :: v_dual_sub_f32 v8, v10, v16
	ds_load_b32 v6, v6
	ds_load_b32 v26, v11
	ds_load_2addr_stride64_b32 v[11:12], v13 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[22:23], v24 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[38:39], v13 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[40:41], v24 offset0:9 offset1:11
	ds_load_b32 v13, v2 offset:3568
	ds_load_b32 v42, v1 offset:3568
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr35
	s_waitcnt lgkmcnt(7)
	v_sub_f32_e32 v33, v6, v37
	s_waitcnt lgkmcnt(6)
	v_sub_f32_e32 v6, v26, v14
	s_waitcnt lgkmcnt(5)
	v_sub_f32_e32 v27, v11, v34
	s_waitcnt lgkmcnt(4)
	v_dual_sub_f32 v9, v22, v17 :: v_dual_sub_f32 v26, v12, v32
	s_waitcnt lgkmcnt(2)
	v_sub_f32_e32 v12, v41, v20
	v_sub_f32_e32 v10, v23, v18
	v_dual_sub_f32 v24, v38, v30 :: v_dual_sub_f32 v11, v40, v19
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v23, v39, v28 :: v_dual_sub_f32 v22, v13, v25
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v13, v42, v21
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr25
.LBB0_26:                               ; %Flow1118
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_add_nc_u32_e32 v24, 16, v1
	ds_load_2addr_b32 v[6:7], v1 offset0:4 offset1:132
	ds_load_2addr_stride64_b32 v[8:9], v24 offset0:16 offset1:18
	ds_load_2addr_stride64_b32 v[10:11], v24 offset0:20 offset1:22
	ds_load_2addr_stride64_b32 v[12:13], v24 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[22:23], v24 offset0:24 offset1:26
	ds_load_2addr_stride64_b32 v[38:39], v24 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[40:41], v24 offset0:28 offset1:30
	ds_load_2addr_stride64_b32 v[42:43], v24 offset0:12 offset1:14
	s_waitcnt lgkmcnt(7)
	v_dual_add_f32 v7, v15, v7 :: v_dual_add_f32 v6, v14, v6
	s_waitcnt lgkmcnt(6)
	v_add_f32_e32 v33, v37, v8
	v_add_f32_e32 v31, v36, v9
	s_waitcnt lgkmcnt(4)
	v_dual_add_f32 v29, v35, v10 :: v_dual_add_f32 v8, v16, v12
	s_waitcnt lgkmcnt(3)
	v_dual_add_f32 v27, v34, v11 :: v_dual_add_f32 v26, v32, v22
	v_dual_add_f32 v9, v17, v13 :: v_dual_add_f32 v24, v30, v23
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v10, v18, v38 :: v_dual_add_f32 v11, v19, v39
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v12, v20, v42
	v_dual_add_f32 v23, v28, v40 :: v_dual_add_f32 v22, v25, v41
	v_add_f32_e32 v13, v21, v43
.LBB0_28:
	s_or_b32 exec_lo, exec_lo, s3
	v_and_b32_e32 v14, 2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v14
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_30
; %bb.29:                               ; %.loopexit269.loopexit
	v_lshrrev_b32_e32 v14, 5, v0
	v_and_b32_e32 v3, 12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v3, v14, 3, v3
	v_lshlrev_b32_e32 v14, 3, v0
	v_lshlrev_b32_e32 v15, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v14, 32, v14
	v_and_b32_e32 v3, 10, v3
	v_and_b32_e32 v15, 20, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v3, v3, v14, v15
	v_cvt_f32_ubyte0_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0xbd490fdb, v3
	v_mul_f32_e32 v3, 0.15915494, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_sin_f32_e32 v14, v3
	v_cos_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v20, v14, v11
	v_mul_f32_e32 v17, v14, v8
	v_mul_f32_e32 v25, v14, v13
	v_mul_f32_e32 v13, v3, v13
	v_mul_f32_e32 v15, v14, v6
	v_fma_f32 v20, v3, v24, -v20
	v_mul_f32_e32 v19, v14, v10
	v_mul_f32_e32 v10, v3, v10
	v_mul_f32_e32 v11, v3, v11
	v_mul_f32_e32 v16, v14, v7
	v_mul_f32_e32 v18, v14, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v9, v3, v9 :: v_dual_fmac_f32 v10, v14, v26
	v_dual_fmac_f32 v11, v14, v24 :: v_dual_mov_b32 v24, v20
	v_fma_f32 v19, v3, v26, -v19
	v_dual_mul_f32 v21, v14, v12 :: v_dual_mul_f32 v6, v3, v6
	v_mul_f32_e32 v8, v3, v8
	v_mul_f32_e32 v7, v3, v7
	v_mul_f32_e32 v12, v3, v12
	v_fma_f32 v15, v3, v33, -v15
	v_fma_f32 v16, v3, v31, -v16
	v_fmac_f32_e32 v8, v14, v29
	v_fma_f32 v17, v3, v29, -v17
	v_fma_f32 v18, v3, v27, -v18
	v_mov_b32_e32 v26, v19
	v_fma_f32 v21, v3, v23, -v21
	v_fma_f32 v3, v3, v22, -v25
	v_fmac_f32_e32 v6, v14, v33
	v_fmac_f32_e32 v7, v14, v31
	v_fmac_f32_e32 v9, v14, v27
	v_dual_fmac_f32 v12, v14, v23 :: v_dual_mov_b32 v33, v15
	v_fmac_f32_e32 v13, v14, v22
	v_mov_b32_e32 v31, v16
	v_mov_b32_e32 v29, v17
	v_mov_b32_e32 v27, v18
	v_dual_mov_b32 v23, v21 :: v_dual_mov_b32 v22, v3
.LBB0_30:                               ; %.loopexit269
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_2addr_stride64_b32 v2, v33, v31 offset1:2
	ds_store_2addr_stride64_b32 v1, v6, v7 offset1:2
	ds_store_2addr_stride64_b32 v2, v29, v27 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v1, v8, v9 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v2, v26, v24 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v1, v10, v11 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v2, v23, v22 offset0:12 offset1:14
	ds_store_2addr_stride64_b32 v1, v12, v13 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_32
; %bb.31:
	ds_load_2addr_b32 v[14:15], v2 offset0:126 offset1:254
	ds_load_2addr_b32 v[16:17], v1 offset0:126 offset1:254
	v_add_nc_u32_e32 v3, -8, v2
	v_add_nc_u32_e32 v18, -8, v1
	v_add_nc_u32_e32 v25, 0xf8, v2
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v35, v14, v31 :: v_dual_add_nc_u32 v28, 0xf8, v1
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v14, v16, v7
	v_dual_sub_f32 v34, v15, v29 :: v_dual_sub_f32 v15, v17, v8
	ds_load_b32 v3, v3
	ds_load_b32 v30, v18
	ds_load_2addr_stride64_b32 v[18:19], v25 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[20:21], v28 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[37:38], v25 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[39:40], v28 offset0:9 offset1:11
	ds_load_b32 v41, v2 offset:3576
	ds_load_b32 v42, v1 offset:3576
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr29
	s_waitcnt lgkmcnt(6)
	v_dual_sub_f32 v36, v3, v33 :: v_dual_sub_f32 v3, v30, v6
	s_waitcnt lgkmcnt(4)
	v_dual_sub_f32 v32, v18, v27 :: v_dual_sub_f32 v17, v21, v10
	s_waitcnt lgkmcnt(3)
	v_dual_sub_f32 v16, v20, v9 :: v_dual_sub_f32 v25, v38, v23
	s_waitcnt lgkmcnt(2)
	v_dual_sub_f32 v30, v19, v26 :: v_dual_sub_f32 v19, v40, v12
	v_sub_f32_e32 v28, v37, v24
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v18, v39, v11 :: v_dual_sub_f32 v21, v41, v22
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v20, v42, v13
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
.LBB0_32:                               ; %Flow1117
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_34
; %bb.33:
	v_add_nc_u32_e32 v3, 8, v1
	ds_load_2addr_b32 v[14:15], v1 offset0:2 offset1:130
	ds_load_2addr_stride64_b32 v[16:17], v3 offset0:16 offset1:18
	ds_load_2addr_stride64_b32 v[18:19], v3 offset0:20 offset1:22
	ds_load_2addr_stride64_b32 v[20:21], v3 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[37:38], v3 offset0:24 offset1:26
	ds_load_2addr_stride64_b32 v[39:40], v3 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[41:42], v3 offset0:28 offset1:30
	ds_load_2addr_stride64_b32 v[43:44], v3 offset0:12 offset1:14
	s_waitcnt lgkmcnt(6)
	v_dual_add_f32 v3, v6, v14 :: v_dual_add_f32 v36, v33, v16
	v_add_f32_e32 v14, v7, v15
	s_waitcnt lgkmcnt(5)
	v_dual_add_f32 v35, v31, v17 :: v_dual_add_f32 v34, v29, v18
	s_waitcnt lgkmcnt(4)
	v_dual_add_f32 v15, v8, v20 :: v_dual_add_f32 v32, v27, v19
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v16, v9, v21 :: v_dual_add_f32 v17, v10, v39
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v30, v26, v37 :: v_dual_add_f32 v19, v12, v43
	v_dual_add_f32 v28, v24, v38 :: v_dual_add_f32 v25, v23, v41
	v_dual_add_f32 v18, v11, v40 :: v_dual_add_f32 v21, v22, v42
	v_add_f32_e32 v20, v13, v44
.LBB0_34:
	s_or_b32 exec_lo, exec_lo, s3
	v_and_b32_e32 v6, 1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v6
	v_lshlrev_b32_e32 v6, 4, v0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_36
; %bb.35:                               ; %.loopexit.loopexit
	v_and_b32_e32 v7, 6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, 0x60, v6
	v_or3_b32 v5, v7, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 2, v5
	v_and_b32_e32 v5, 42, v5
	v_and_or_b32 v5, v7, 21, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_ubyte0_e32 v5, v5
	v_mul_f32_e32 v5, 0xbd490fdb, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0.15915494, v5
	v_sin_f32_e32 v7, v5
	v_cos_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, v7, v15
	v_mul_f32_e32 v8, v7, v3
	v_dual_mul_f32 v3, v5, v3 :: v_dual_mul_f32 v12, v7, v17
	v_mul_f32_e32 v9, v7, v14
	v_mul_f32_e32 v11, v7, v16
	v_dual_mul_f32 v17, v5, v17 :: v_dual_mul_f32 v22, v7, v19
	v_mul_f32_e32 v13, v7, v18
	v_fma_f32 v8, v5, v36, -v8
	v_dual_mul_f32 v23, v7, v20 :: v_dual_mul_f32 v14, v5, v14
	v_mul_f32_e32 v16, v5, v16
	v_mul_f32_e32 v15, v5, v15
	v_mul_f32_e32 v18, v5, v18
	v_mul_f32_e32 v19, v5, v19
	v_mul_f32_e32 v20, v5, v20
	v_fma_f32 v9, v5, v35, -v9
	v_fma_f32 v10, v5, v34, -v10
	v_fmac_f32_e32 v18, v7, v28
	v_fmac_f32_e32 v3, v7, v36
	v_fma_f32 v11, v5, v32, -v11
	v_fma_f32 v12, v5, v30, -v12
	v_fma_f32 v13, v5, v28, -v13
	v_fma_f32 v22, v5, v25, -v22
	v_mov_b32_e32 v36, v8
	v_fma_f32 v5, v5, v21, -v23
	v_dual_fmac_f32 v14, v7, v35 :: v_dual_mov_b32 v35, v9
	v_fmac_f32_e32 v16, v7, v32
	v_fmac_f32_e32 v15, v7, v34
	v_dual_fmac_f32 v17, v7, v30 :: v_dual_mov_b32 v28, v13
	v_fmac_f32_e32 v19, v7, v25
	v_dual_fmac_f32 v20, v7, v21 :: v_dual_mov_b32 v25, v22
	v_mov_b32_e32 v34, v10
	v_dual_mov_b32 v32, v11 :: v_dual_mov_b32 v21, v5
	v_mov_b32_e32 v30, v12
.LBB0_36:                               ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_2addr_stride64_b32 v2, v36, v35 offset1:2
	ds_store_2addr_stride64_b32 v1, v3, v14 offset1:2
	ds_store_2addr_stride64_b32 v2, v34, v32 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v1, v15, v16 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v2, v30, v28 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v1, v17, v18 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v2, v25, v21 offset0:12 offset1:14
	ds_store_2addr_stride64_b32 v1, v19, v20 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr22
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_38
; %bb.37:
	ds_load_2addr_b32 v[7:8], v2 offset0:127 offset1:255
	ds_load_2addr_b32 v[10:11], v1 offset0:127 offset1:255
	v_add_nc_u32_e32 v5, -4, v2
	v_add_nc_u32_e32 v9, -4, v1
	v_add_nc_u32_e32 v12, 0xfc, v2
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v10, v10, v14 :: v_dual_add_nc_u32 v13, 0xfc, v1
	ds_load_b32 v22, v5
	ds_load_b32 v9, v9
	ds_load_2addr_stride64_b32 v[23:24], v12 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[26:27], v13 offset0:5 offset1:7
	ds_load_2addr_stride64_b32 v[37:38], v12 offset0:9 offset1:11
	ds_load_2addr_stride64_b32 v[39:40], v13 offset0:9 offset1:11
	ds_load_b32 v33, v2 offset:3580
	ds_load_b32 v41, v1 offset:3580
	v_sub_f32_e32 v5, v7, v35
	v_dual_sub_f32 v7, v8, v34 :: v_dual_sub_f32 v12, v11, v15
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr34
	s_waitcnt lgkmcnt(7)
	v_sub_f32_e32 v8, v22, v36
	s_waitcnt lgkmcnt(5)
	v_dual_sub_f32 v22, v9, v3 :: v_dual_sub_f32 v9, v23, v32
	s_waitcnt lgkmcnt(4)
	v_dual_sub_f32 v26, v26, v16 :: v_dual_sub_f32 v11, v24, v30
	v_sub_f32_e32 v27, v27, v17
	s_waitcnt lgkmcnt(3)
	v_sub_f32_e32 v13, v37, v28
	s_waitcnt lgkmcnt(2)
	v_sub_f32_e32 v29, v39, v18
	v_sub_f32_e32 v23, v38, v25
	s_waitcnt lgkmcnt(1)
	v_dual_sub_f32 v31, v40, v19 :: v_dual_sub_f32 v24, v33, v21
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v33, v41, v20
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr21
.LBB0_38:                               ; %Flow
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_40
; %bb.39:
	v_add_nc_u32_e32 v5, 4, v1
	ds_load_2addr_b32 v[7:8], v1 offset0:1 offset1:129
	ds_load_2addr_stride64_b32 v[11:12], v5 offset0:16 offset1:18
	ds_load_2addr_stride64_b32 v[23:24], v5 offset0:20 offset1:22
	ds_load_2addr_stride64_b32 v[26:27], v5 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[37:38], v5 offset0:24 offset1:26
	ds_load_2addr_stride64_b32 v[39:40], v5 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[41:42], v5 offset0:28 offset1:30
	ds_load_2addr_stride64_b32 v[43:44], v5 offset0:12 offset1:14
	s_waitcnt lgkmcnt(7)
	v_add_f32_e32 v22, v3, v7
	v_add_f32_e32 v10, v14, v8
	s_waitcnt lgkmcnt(6)
	v_dual_add_f32 v8, v36, v11 :: v_dual_add_f32 v5, v35, v12
	s_waitcnt lgkmcnt(4)
	v_dual_add_f32 v7, v34, v23 :: v_dual_add_f32 v12, v15, v26
	s_waitcnt lgkmcnt(1)
	v_dual_add_f32 v9, v32, v24 :: v_dual_add_f32 v24, v21, v42
	v_dual_add_f32 v26, v16, v27 :: v_dual_add_f32 v11, v30, v37
	v_add_f32_e32 v27, v17, v39
	v_add_f32_e32 v13, v28, v38
	v_add_f32_e32 v29, v18, v40
	v_add_f32_e32 v23, v25, v41
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v31, v19, v43
	v_add_f32_e32 v33, v20, v44
.LBB0_40:
	s_or_b32 exec_lo, exec_lo, s3
	v_and_b32_e32 v3, 0x30f0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v3, v4, 15, v3
	v_lshlrev_b32_e32 v4, 2, v3
	v_lshrrev_b32_e32 v3, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, 0xc0cc, v4
	v_and_or_b32 v3, v3, 51, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v4, 2, v3
	v_and_b32_e32 v3, 0x4055, v3
	v_and_or_b32 v3, 0x202a, v4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_store_2addr_stride64_b32 v3, v8, v5 offset0:16 offset1:18
	ds_store_2addr_stride64_b32 v3, v22, v10 offset1:2
	ds_store_2addr_stride64_b32 v3, v7, v9 offset0:20 offset1:22
	ds_store_2addr_stride64_b32 v3, v12, v26 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v3, v11, v13 offset0:24 offset1:26
	ds_store_2addr_stride64_b32 v3, v27, v29 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v3, v23, v24 offset0:28 offset1:30
	ds_store_2addr_stride64_b32 v3, v31, v33 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b32 s0, s[0:1], 0xc
	ds_load_2addr_stride64_b32 v[5:6], v2 offset1:2
	ds_load_2addr_stride64_b32 v[7:8], v1 offset1:2
	ds_load_2addr_stride64_b32 v[9:10], v2 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[13:14], v1 offset0:4 offset1:6
	ds_load_2addr_stride64_b32 v[15:16], v2 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[17:18], v1 offset0:8 offset1:10
	ds_load_2addr_stride64_b32 v[19:20], v2 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s2, s0, v[0:1]
	v_mov_b32_e32 v4, 0
	ds_load_2addr_stride64_b32 v[0:1], v1 offset0:12 offset1:14
	v_lshlrev_b64 v[11:12], 2, v[3:4]
	v_add_nc_u32_e32 v3, s0, v3
	v_add_co_u32 v23, vcc_lo, s4, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v12, vcc_lo
	v_lshlrev_b64 v[21:22], 2, v[3:4]
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_nc_u32_e32 v3, s0, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_store_b32 v[23:24], v5, off
	global_store_b32 v[11:12], v7, off
	v_lshlrev_b64 v[25:26], 2, v[3:4]
	v_add_co_u32 v11, vcc_lo, s4, v21
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v22, vcc_lo
	v_add_co_u32 v21, vcc_lo, s6, v21
	v_add_nc_u32_e32 v3, s0, v3
	v_add_co_ci_u32_e32 v22, vcc_lo, s7, v22, vcc_lo
	v_add_co_u32 v5, vcc_lo, s4, v25
	global_store_b32 v[11:12], v6, off
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v26, vcc_lo
	v_lshlrev_b64 v[23:24], 2, v[3:4]
	v_add_co_u32 v11, vcc_lo, s6, v25
	v_add_nc_u32_e32 v3, s0, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v26, vcc_lo
	global_store_b32 v[21:22], v8, off
	global_store_b32 v[5:6], v9, off
	global_store_b32 v[11:12], v13, off
	v_add_co_u32 v5, vcc_lo, s4, v23
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v24, vcc_lo
	v_add_co_u32 v11, vcc_lo, s6, v23
	v_add_nc_u32_e32 v3, s0, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v24, vcc_lo
	global_store_b32 v[5:6], v10, off
	v_add_co_u32 v5, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
	v_lshlrev_b64 v[21:22], 2, v[3:4]
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_nc_u32_e32 v3, s0, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_store_b32 v[11:12], v14, off
	global_store_b32 v[5:6], v15, off
	global_store_b32 v[7:8], v17, off
	v_add_co_u32 v5, vcc_lo, s4, v21
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_add_nc_u32_e32 v3, s0, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v22, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v21
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v22, vcc_lo
	global_store_b32 v[5:6], v16, off
	v_add_co_u32 v5, vcc_lo, s4, v9
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_store_b32 v[7:8], v18, off
	global_store_b32 v[5:6], v19, off
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[9:10], v0, off
	global_store_b32 v[11:12], v20, off
	global_store_b32 v[2:3], v1, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5FFT1DPfS_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5FFT1DPfS_, .Lfunc_end0-_Z5FFT1DPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6232
; NumSgprs: 18
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20transposeDiagonal_xyPfS_S_S_i ; -- Begin function _Z20transposeDiagonal_xyPfS_S_S_i
	.globl	_Z20transposeDiagonal_xyPfS_S_S_i
	.p2align	8
	.type	_Z20transposeDiagonal_xyPfS_S_S_i,@function
_Z20transposeDiagonal_xyPfS_S_S_i:      ; @_Z20transposeDiagonal_xyPfS_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x28
	s_load_b32 s8, s[0:1], 0x20
	s_add_i32 s5, s13, s14
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s4, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s3, v1
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s4, s4, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
	s_mul_hi_u32 s4, s3, s4
	v_lshlrev_b32_e32 v7, 2, v1
	s_add_i32 s3, s3, s4
	s_mul_hi_u32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s3, s3, s2
	v_mad_u32_u24 v7, 0x44, v0, v7
	s_sub_i32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s4, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s3, s4, s3
	s_sub_i32 s4, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s9, s4, s3
	s_lshl_b32 s10, s13, 4
	s_load_b256 s[0:7], s[0:1], 0x0
	v_add_nc_u32_e32 v3, s10, v2
	s_lshl_b32 s9, s9, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, s9, v2
	v_mul_lo_u32 v3, v3, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, s8
	v_add3_u32 v3, v3, v0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v5, v[5:6], off
	v_lshlrev_b32_e32 v6, 2, v0
	v_add3_u32 v0, s10, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u32_u24 v8, 0x44, v1, v6
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v9, v7
	v_add_co_u32 v5, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[5:6], v9, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v7
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20transposeDiagonal_xyPfS_S_S_i
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z20transposeDiagonal_xyPfS_S_S_i, .Lfunc_end1-_Z20transposeDiagonal_xyPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20transposeDiagonal_xzPfS_S_S_i ; -- Begin function _Z20transposeDiagonal_xzPfS_S_S_i
	.globl	_Z20transposeDiagonal_xzPfS_S_S_i
	.p2align	8
	.type	_Z20transposeDiagonal_xzPfS_S_S_i,@function
_Z20transposeDiagonal_xzPfS_S_S_i:      ; @_Z20transposeDiagonal_xzPfS_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x28
	s_load_b32 s8, s[0:1], 0x20
	s_add_i32 s5, s13, s15
	v_bfe_u32 v4, v0, 20, 10
	v_and_b32_e32 v5, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s4, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s4, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s4, s3, s4
	s_add_i32 s3, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s5, s3
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s3, s5, s3
	s_sub_i32 s4, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s3, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s4, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s9, s4, s3
	s_lshl_b32 s10, s13, 4
	s_load_b256 s[0:7], s[0:1], 0x0
	v_add_nc_u32_e32 v3, s10, v4
	s_lshl_b32 s9, s9, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, s9, v4
	v_mad_u64_u32 v[1:2], null, v3, s8, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s8
	v_add3_u32 v0, v1, v5, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	v_mad_u64_u32 v[2:3], null, v7, s8, s[14:15]
	v_lshlrev_b32_e32 v3, 2, v5
	v_lshlrev_b32_e32 v7, 2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u32_u24 v8, 0x44, v4, v3
	v_mul_lo_u32 v2, v2, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u32_u24 v7, 0x44, v5, v7
	v_add3_u32 v2, s10, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v6, v7
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[4:5], v6, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v4, v7
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20transposeDiagonal_xzPfS_S_S_i
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z20transposeDiagonal_xzPfS_S_S_i, .Lfunc_end2-_Z20transposeDiagonal_xzPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z20transposeDiagonal_xyPfS_i ; -- Begin function _Z20transposeDiagonal_xyPfS_i
	.globl	_Z20transposeDiagonal_xyPfS_i
	.p2align	8
	.type	_Z20transposeDiagonal_xyPfS_i,@function
_Z20transposeDiagonal_xyPfS_i:          ; @_Z20transposeDiagonal_xyPfS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s4, s[0:1], 0x10
	s_add_i32 s6, s13, s14
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s5, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s3, v1
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s5, s5, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_mul_hi_u32 s5, s3, s5
	v_lshlrev_b32_e32 v5, 2, v1
	s_add_i32 s3, s3, s5
	s_mul_hi_u32 s3, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s2
	s_sub_i32 s3, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s5, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s3, s5, s3
	s_sub_i32 s5, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s5, s5, s3
	s_lshl_b32 s6, s13, 4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_add_nc_u32_e32 v3, s6, v2
	s_lshl_b32 s5, s5, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, s5, v2
	v_mul_lo_u32 v3, v3, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, s4
	v_add3_u32 v3, v3, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshlrev_b32_e32 v4, 2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v1, 0x44, v1, v4
	v_mad_u32_u24 v4, 0x44, v0, v5
	v_add3_u32 v0, s6, v0, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20transposeDiagonal_xyPfS_i
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z20transposeDiagonal_xyPfS_i, .Lfunc_end3-_Z20transposeDiagonal_xyPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 388
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20transposeDiagonal_xzPfS_i ; -- Begin function _Z20transposeDiagonal_xzPfS_i
	.globl	_Z20transposeDiagonal_xzPfS_i
	.p2align	8
	.type	_Z20transposeDiagonal_xzPfS_i,@function
_Z20transposeDiagonal_xzPfS_i:          ; @_Z20transposeDiagonal_xzPfS_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v3, v0, 20, 10
	s_add_i32 s5, s13, s15
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s4, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s4, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s4, s3, s4
	s_add_i32 s3, s3, s4
	s_load_b32 s4, s[0:1], 0x10
	s_mul_hi_u32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s2
	s_sub_i32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s5, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s3, s5, s3
	s_sub_i32 s5, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s5, s5, s3
	s_lshl_b32 s6, s13, 4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_add_nc_u32_e32 v4, s6, v3
	s_lshl_b32 s5, s5, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s5, v3
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, v4, s4, s[14:15]
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s4
	v_add3_u32 v0, v1, v2, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v4, v[0:1], off
	v_mad_u64_u32 v[0:1], null, v5, s4, s[14:15]
	v_lshlrev_b32_e32 v1, 2, v2
	v_lshlrev_b32_e32 v5, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u32_u24 v1, 0x44, v3, v1
	v_mul_lo_u32 v0, v0, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u32_u24 v3, 0x44, v2, v5
	v_add3_u32 v0, s6, v2, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v3
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20transposeDiagonal_xzPfS_i
		.amdhsa_group_segment_fixed_size 1088
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z20transposeDiagonal_xzPfS_i, .Lfunc_end4-_Z20transposeDiagonal_xzPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 396
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5FFT1DPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5FFT1DPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1088
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20transposeDiagonal_xyPfS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20transposeDiagonal_xyPfS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1088
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20transposeDiagonal_xzPfS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20transposeDiagonal_xzPfS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1088
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20transposeDiagonal_xyPfS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20transposeDiagonal_xyPfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1088
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20transposeDiagonal_xzPfS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20transposeDiagonal_xzPfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
