#pragma once
#ifndef BLOCK_MATCHING_KERNEL
#define BLOCK_MATCHING_KERNEL
#define INDXs(s,i,j)   ((s) * (i) + (j) + 0)

__device__ double computeMatchKernel(unsigned char *im,
		    int im_step,
		    unsigned char *bl,
		    int bl_step,
		    int bl_cols,
		    int bl_rows,
		    int oi, 
		    int oj, 
		    int stride){
  
  if (!im || !bl) return 0.0;

  double nb = (bl_cols*bl_rows);
  double x = 0;
  for(int i = 0;i < bl_rows-stride+1;i+= stride){
    for(int j = 0;j < bl_cols-stride+1;j+= stride){
      unsigned char v1 = im[INDXs(im_step,oi+i,oj+j)];
      unsigned char v2 = bl[INDXs(bl_step,i,j)];
      x += (v2-v1)*(v2-v1);
      //im[INDXs(im_step,oi+i,oj+j)] = ABS(v2-v1);
    }
  }
  x = x / nb;
  //  printf("%f\n",x);
  return x;
}

struct DataOut{
	double minVal;
	int coord_i_min;
	int coord_j_min;
};

__global__ void blockMatching_kernel(int jend,int stride,unsigned char* im, int im_step, unsigned char *bl, int bl_step,int bl_cols,int bl_rows, DataOut* result){
		
	__shared__ DataOut tab_data_out[1024];
	
	DataOut temp;
	temp.minVal=1000000000000000;// a changer	
	int tid = blockDim.x * blockIdx.x + threadIdx.x;
	
	for(int j = 0;j < jend-stride+1;j+=stride){
	  double x = computeMatchKernel(im,im_step,
				  bl,bl_step,bl_cols,bl_rows,
				  tid,j,stride);
	  
		 if(x<temp.minVal){
			 temp.minVal=x;
			 temp.coord_i_min=tid;
			 temp.coord_j_min=j;
		}
	}
			
	tab_data_out[tid]=temp;
	__syncthreads();
	
	for (unsigned int s = 1; s<blockDim.x * blockDim.y; s *=2){
		int index = 2 * s * threadIdx.x;
		
		if (index < blockDim.x * blockDim.y){

			if (tab_data_out[index].minVal > tab_data_out[index + s].minVal){
				if((index + s) < blockDim.x * blockDim.y){
					tab_data_out[index] = tab_data_out[index + s];			
				}	
			}
		}
		__syncthreads();
	}

	if(threadIdx.x==0){
		result[blockIdx.x] = tab_data_out[0];
	}


	
	  
}
#endif

	.file	"tmpxft_0028a431_00000000-6_blockMatching_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z18computeMatchKernelPhiS_iiiiii
	.type	_Z18computeMatchKernelPhiS_iiiiii, @function
_Z18computeMatchKernelPhiS_iiiiii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z18computeMatchKernelPhiS_iiiiii, .-_Z18computeMatchKernelPhiS_iiiiii
	.globl	_Z57__device_stub__Z20blockMatching_kerneliiPhiS_iiiP7DataOutiiPhiS_iiiP7DataOut
	.type	_Z57__device_stub__Z20blockMatching_kerneliiPhiS_iiiP7DataOutiiPhiS_iiiP7DataOut, @function
_Z57__device_stub__Z20blockMatching_kerneliiPhiS_iiiP7DataOutiiPhiS_iiiP7DataOut:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	224(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L4:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z57__device_stub__Z20blockMatching_kerneliiPhiS_iiiP7DataOutiiPhiS_iiiP7DataOut, .-_Z57__device_stub__Z20blockMatching_kerneliiPhiS_iiiP7DataOutiiPhiS_iiiP7DataOut
	.globl	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut
	.type	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut, @function
_Z20blockMatching_kerneliiPhiS_iiiP7DataOut:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z20blockMatching_kerneliiPhiS_iiiP7DataOutiiPhiS_iiiP7DataOut
	.cfi_endproc
.LFE2034:
	.size	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut, .-_Z20blockMatching_kerneliiPhiS_iiiP7DataOut
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20blockMatching_kerneliiPhiS_iiiP7DataOut"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#pragma once
#include <hip/hip_runtime.h>

#ifndef BLOCK_MATCHING_KERNEL
#define BLOCK_MATCHING_KERNEL
#define INDXs(s,i,j)   ((s) * (i) + (j) + 0)

__device__ double computeMatchKernel(unsigned char *im,
		    int im_step,
		    unsigned char *bl,
		    int bl_step,
		    int bl_cols,
		    int bl_rows,
		    int oi, 
		    int oj, 
		    int stride){
  
  if (!im || !bl) return 0.0;

  double nb = (bl_cols*bl_rows);
  double x = 0;
  for(int i = 0;i < bl_rows-stride+1;i+= stride){
    for(int j = 0;j < bl_cols-stride+1;j+= stride){
      unsigned char v1 = im[INDXs(im_step,oi+i,oj+j)];
      unsigned char v2 = bl[INDXs(bl_step,i,j)];
      x += (v2-v1)*(v2-v1);
      //im[INDXs(im_step,oi+i,oj+j)] = ABS(v2-v1);
    }
  }
  x = x / nb;
  //  printf("%f\n",x);
  return x;
}

struct DataOut{
	double minVal;
	int coord_i_min;
	int coord_j_min;
};

__global__ void blockMatching_kernel(int jend,int stride,unsigned char* im, int im_step, unsigned char *bl, int bl_step,int bl_cols,int bl_rows, DataOut* result){
		
	__shared__ DataOut tab_data_out[1024];
	
	DataOut temp;
	temp.minVal=1000000000000000;// a changer	
	int tid = blockDim.x * blockIdx.x + threadIdx.x;
	
	for(int j = 0;j < jend-stride+1;j+=stride){
	  double x = computeMatchKernel(im,im_step,
				  bl,bl_step,bl_cols,bl_rows,
				  tid,j,stride);
	  
		 if(x<temp.minVal){
			 temp.minVal=x;
			 temp.coord_i_min=tid;
			 temp.coord_j_min=j;
		}
	}
			
	tab_data_out[tid]=temp;
	__syncthreads();
	
	for (unsigned int s = 1; s<blockDim.x * blockDim.y; s *=2){
		int index = 2 * s * threadIdx.x;
		
		if (index < blockDim.x * blockDim.y){

			if (tab_data_out[index].minVal > tab_data_out[index + s].minVal){
				if((index + s) < blockDim.x * blockDim.y){
					tab_data_out[index] = tab_data_out[index + s];			
				}	
			}
		}
		__syncthreads();
	}

	if(threadIdx.x==0){
		result[blockIdx.x] = tab_data_out[0];
	}


	
	  
}
#endif

	.text
	.file	"blockMatching_kernel.hip"
	.globl	_Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut # -- Begin function _Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut
	.type	_Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut,@function
_Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut: # @_Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20blockMatching_kerneliiPhiS_iiiP7DataOut, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut, .Lfunc_end0-_Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20blockMatching_kerneliiPhiS_iiiP7DataOut, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut,@object # @_Z20blockMatching_kerneliiPhiS_iiiP7DataOut
	.section	.rodata,"a",@progbits
	.globl	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut
	.p2align	3, 0x0
_Z20blockMatching_kerneliiPhiS_iiiP7DataOut:
	.quad	_Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut
	.size	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20blockMatching_kerneliiPhiS_iiiP7DataOut"
	.size	.L__unnamed_1, 44

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__blockMatching_kerneliiPhiS_iiiP7DataOut
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20blockMatching_kerneliiPhiS_iiiP7DataOut
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut ; -- Begin function _Z20blockMatching_kerneliiPhiS_iiiP7DataOut
	.globl	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut
	.p2align	8
	.type	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut,@function
_Z20blockMatching_kerneliiPhiS_iiiP7DataOut: ; @_Z20blockMatching_kerneliiPhiS_iiiP7DataOut
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x44
	s_load_b64 s[6:7], s[0:1], 0x0
	s_add_u32 s2, s0, 56
	s_mov_b32 s4, s15
	s_addc_u32 s3, s1, 0
	s_mov_b32 s12, 0x26340000
	s_mov_b32 s13, 0x430c6bf5
	s_mov_b32 s14, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_sub_i32 s6, s6, s7
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	s_cmp_lt_i32 s6, 0
	s_cbranch_scc1 .LBB0_11
; %bb.1:                                ; %.lr.ph
	s_clause 0x2
	s_load_b128 s[24:27], s[0:1], 0x20
	s_load_b64 s[8:9], s[0:1], 0x8
	s_load_b64 s[10:11], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_load_b32 s27, s[0:1], 0x10
	v_mov_b32_e32 v8, 0
	s_mov_b32 s21, s7
	s_mov_b32 s23, s7
	s_mul_i32 s15, s26, s25
	s_cmp_lg_u64 s[8:9], 0
	v_cvt_f64_i32_e32 v[2:3], s15
	s_cselect_b32 s16, -1, 0
	s_cmp_lg_u64 s[10:11], 0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v7, s27, v1
	s_cselect_b32 s17, -1, 0
	s_sub_i32 s15, s26, s7
	s_and_b32 s16, s16, s17
	s_cmp_gt_i32 s15, -1
	v_mov_b32_e32 v4, s12
	s_cselect_b32 s17, -1, 0
	s_sub_i32 s18, s25, s7
	v_dual_mov_b32 v5, s13 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v7
	s_cmp_gt_i32 s18, -1
	s_mul_i32 s22, s24, s7
	s_cselect_b32 s19, -1, 0
	s_ashr_i32 s20, s7, 31
	s_mul_i32 s24, s27, s7
                                        ; implicit-def: $vgpr7
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_10
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_and_not1_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB0_9
; %bb.4:                                ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v14, v10
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, v9
	s_mov_b32 s25, 0
	s_mov_b32 s26, 0
.LBB0_5:                                ; %.preheader.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_8
; %bb.6:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_ashr_i32 s12, s25, 31
	s_add_u32 s27, s10, s25
	s_addc_u32 s28, s11, s12
	s_mov_b64 s[12:13], 0
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v15, s12, v13
	s_add_u32 s30, s27, s12
	s_addc_u32 s31, s28, s13
	s_add_u32 s12, s12, s21
	s_addc_u32 s13, s13, s20
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_co_u32 v15, vcc_lo, s8, v15
	s_cmp_gt_i32 s12, s18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
	global_load_u8 v17, v8, s[30:31]
	global_load_u8 v15, v[15:16], off
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v15, v17, v15
	v_mul_i32_i24_e32 v15, v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[15:16], v15
	v_add_f64 v[11:12], v[11:12], v[15:16]
	s_cbranch_scc0 .LBB0_7
.LBB0_8:                                ; %._crit_edge.i
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_co_u32 v13, vcc_lo, v13, s24
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_add_i32 s26, s26, s7
	s_add_i32 s25, s25, s22
	s_cmp_gt_i32 s26, s15
	s_cbranch_scc0 .LBB0_5
.LBB0_9:                                ; %._crit_edge45.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[13:14], null, v[2:3], v[2:3], v[11:12]
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[2:3], v[11:12]
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[11:12], v[13:14], v[2:3], v[11:12]
.LBB0_10:                               ; %_Z18computeMatchKernelPhiS_iiiiii.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[11:12], v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_cndmask_b32_e32 v6, v6, v1, vcc_lo
	v_cndmask_b32_e64 v7, v7, s14, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, s23
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_add_i32 s14, s14, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s14, s6
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_12
.LBB0_11:
	v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
                                        ; implicit-def: $vgpr7
.LBB0_12:                               ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v1, 4, v1
	ds_store_2addr_b64 v1, v[4:5], v[6:7] offset1:1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b32 s2, s[2:3], 0xc
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s5
	s_cmp_lt_u32 s3, 2
	s_cbranch_scc1 .LBB0_18
; %bb.13:                               ; %.lr.ph53.preheader
	s_mov_b32 s5, 1
.LBB0_14:                               ; %.lr.ph53
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mov_b32 s2, s5
	s_lshl_b32 s5, s5, 1
	s_mov_b32 s6, exec_lo
	v_mul_lo_u32 v2, s5, v0
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB0_17
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=1
	v_lshlrev_b32_e32 v1, 4, v2
	v_add_nc_u32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v3, s2, 4, v1
	v_cmp_gt_u32_e64 s2, s3, v2
	ds_load_b64 v[4:5], v1
	ds_load_b64 v[6:7], v3
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[6:7]
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_14 Depth=1
	ds_load_b128 v[2:5], v3
	s_waitcnt lgkmcnt(0)
	ds_store_b128 v1, v[2:5]
.LBB0_17:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s5, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_14
.LBB0_18:                               ; %._crit_edge54
	s_mov_b32 s5, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_mov_b32_e32 v4, 0
	s_load_b64 s[0:1], s[0:1], 0x30
	s_lshl_b64 s[2:3], s[4:5], 4
	ds_load_b128 v[0:3], v4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_store_b128 v4, v[0:3], s[0:1]
.LBB0_20:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20blockMatching_kerneliiPhiS_iiiP7DataOut
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20blockMatching_kerneliiPhiS_iiiP7DataOut, .Lfunc_end0-_Z20blockMatching_kerneliiPhiS_iiiP7DataOut
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 900
; NumSgprs: 34
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20blockMatching_kerneliiPhiS_iiiP7DataOut
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z20blockMatching_kerneliiPhiS_iiiP7DataOut.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
