// NAME: Jose Torres
#include <stdio.h>
#include <iostream>
#include <assert.h>

__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){

    // Code from HW slide
    __shared__ float smem_c[64][64];
    __shared__ float smem_a[64][8];
    __shared__ float smem_b[8][64];

    int c = blockIdx.x * 64;
    int r = blockIdx.y * 64;

    for(int kk = 0; kk < size; kk += 8){
        for(int i = threadIdx.x + blockDim.x * threadIdx.y;
                i < 64 * 8;
                i += blockDim.x * blockDim.y){
            
            // load into shared memory
            int k = kk + i / 64;
            int rt = r + i % 64;
            int ct = c + i % 64;
            smem_a[i%64][i/64] = A[rt*size+k];
            smem_b[i/64][i%64] = B[k*size+ct];
        
        }
        __syncthreads();
        for(int i=0; i < 2; ++i){
            for(int j=0; j < 2; ++j){

                int rowIdx = threadIdx.y * 2 + j;
                int colIdx = threadIdx.x * 2 + i;

                for(int k=0; k < 8; ++k){
                    // Store / Compute results in shared C
                    smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
                }
                // Store back into global memory
                C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
            }
        }
    }
}

int main() {
    
    const int N = 8192; 

    // Declare host memory for Matrices A and B
    float *hostA, *hostB, *hostC, *hostSumTemp;

    // Declare device memory
    float *deviceA, *deviceB, *deviceC;

    // Allocate host memory for all Matrices
    size_t memSize = sizeof(float) * N * N;
    hostA = (float*) malloc(memSize);
    hostB = (float*) malloc(memSize);
    hostC = (float*) malloc(memSize);
    hostSumTemp = (float*) malloc(memSize);
    
    // init host memory

    // A = 2, 2, 2, 2 . . .
    // B = 3, 3, 3, 3 . . .
    // C = 0, 0, 0, 0 . . .
    // hostSumTemp = 6, 6, 6, 6, ...
    // hostSumTemp is just temp variable to compare to
    // values are chosen to be really easy
    for(int i=0; i < N; ++i){
        for(int j=0; j < N; ++j){
            hostA[i*N+j] = 2;
            hostB[i*N+j] = 3;
            hostC[i*N+j] = 0;
            hostSumTemp[i*N+j] = 6;
        }
    }

    // Allocate device memory
    cudaMalloc((void**) &deviceA, memSize);
    cudaMalloc((void**) &deviceB, memSize);
    cudaMalloc((void**) &deviceC, memSize);

    // Copy Matrix A and B from host to device
    cudaMemcpy(deviceA, hostA, memSize, cudaMemcpyHostToDevice);
    cudaMemcpy(deviceB, hostB, memSize, cudaMemcpyHostToDevice);

    // Invoke Kernel
    dim3 nblocks(N / 64, N / 64);
    dim3 nthreads(32, 32);

    // Init Kernel
    matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
    
    // Transfer from result matrix from device to host
    cudaMemcpy(hostC, deviceC, memSize, cudaMemcpyDeviceToHost);

    // Check results
    bool isSame = true;
    int row, col;
    for(row=0; row < N; ++row){
        for(col=0; col < N; ++col){
            if(hostC[row*N+col] != hostSumTemp[row*N+col]){
                isSame = false;
                break;
            }
        }
    }

    // Print comparasion
    if(!isSame){
        std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
    } else {
        std::cout << "Results matched.\n";
    }

    // free memory
    free(hostA);
    free(hostB);
    free(hostC);
    free(hostSumTemp);

    cudaFree(deviceA);
    cudaFree(deviceB);
    cudaFree(deviceC);

    return 0;
}
	.file	"tmpxft_003188b8_00000000-6_matrixMul.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
	.type	_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13matrixMulCUDAPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
	.globl	_Z13matrixMulCUDAPfS_S_i
	.type	_Z13matrixMulCUDAPfS_S_i, @function
_Z13matrixMulCUDAPfS_S_i:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3661:
	.size	_Z13matrixMulCUDAPfS_S_i, .-_Z13matrixMulCUDAPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"Did not match at \n\trow = "
.LC4:
	.string	"\n\tcol = "
.LC5:
	.string	"Results matched.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$268435456, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$268435456, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$268435456, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$268435456, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movss	.LC0(%rip), %xmm0
	movss	.LC1(%rip), %xmm1
	xorl	%edx, %edx
	movss	.LC2(%rip), %xmm2
	movq	%rax, %rbp
.L10:
	movq	%rdx, %rax
	xorl	%ecx, %ecx
.L9:
	incl	%ecx
	movss	%xmm0, 0(%r13,%rax)
	movss	%xmm1, (%r12,%rax)
	movss	%xmm2, 0(%rbp,%rax)
	addq	$4, %rax
	cmpl	$8192, %ecx
	jne	.L9
	addq	$32768, %rdx
	cmpq	$268435456, %rdx
	jne	.L10
	xorl	%eax, %eax
	movl	$67108864, %ecx
	movq	%rbx, %rdi
	movl	$268435456, %esi
	rep stosl
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$268435456, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$268435456, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$268435456, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$268435456, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdx
	movl	$1, %esi
	movabsq	$549755814016, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$8192, %ecx
	movq	8(%rsp), %rdi
	call	_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
.L13:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$268435456, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	xorl	%edx, %edx
	movb	$1, %cl
.L14:
	movq	%rdx, %rax
	xorl	%r14d, %r14d
.L17:
	movss	(%rbx,%rax), %xmm0
	ucomiss	0(%rbp,%rax), %xmm0
	jp	.L22
	jne	.L22
	incl	%r14d
	addq	$4, %rax
	cmpl	$8192, %r14d
	jne	.L17
	jmp	.L15
.L22:
	xorl	%ecx, %ecx
.L15:
	addq	$32768, %rdx
	cmpq	$268435456, %rdx
	jne	.L14
	testb	%cl, %cl
	leaq	_ZSt4cout(%rip), %rdi
	jne	.L19
	leaq	.LC3(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$8192, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	jmp	.L20
.L19:
	leaq	.LC5(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L20:
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z13matrixMulCUDAPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13matrixMulCUDAPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1073741824
	.align 4
.LC1:
	.long	1077936128
	.align 4
.LC2:
	.long	1086324736
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// NAME: Jose Torres

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <assert.h>

__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){

    // Code from HW slide
    __shared__ float smem_c[64][64];
    __shared__ float smem_a[64][8];
    __shared__ float smem_b[8][64];

    int c = blockIdx.x * 64;
    int r = blockIdx.y * 64;

    for(int kk = 0; kk < size; kk += 8){
        for(int i = threadIdx.x + blockDim.x * threadIdx.y;
                i < 64 * 8;
                i += blockDim.x * blockDim.y){
            
            // load into shared memory
            int k = kk + i / 64;
            int rt = r + i % 64;
            int ct = c + i % 64;
            smem_a[i%64][i/64] = A[rt*size+k];
            smem_b[i/64][i%64] = B[k*size+ct];
        
        }
        __syncthreads();
        for(int i=0; i < 2; ++i){
            for(int j=0; j < 2; ++j){

                int rowIdx = threadIdx.y * 2 + j;
                int colIdx = threadIdx.x * 2 + i;

                for(int k=0; k < 8; ++k){
                    // Store / Compute results in shared C
                    smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
                }
                // Store back into global memory
                C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
            }
        }
    }
}

int main() {
    
    const int N = 8192; 

    // Declare host memory for Matrices A and B
    float *hostA, *hostB, *hostC, *hostSumTemp;

    // Declare device memory
    float *deviceA, *deviceB, *deviceC;

    // Allocate host memory for all Matrices
    size_t memSize = sizeof(float) * N * N;
    hostA = (float*) malloc(memSize);
    hostB = (float*) malloc(memSize);
    hostC = (float*) malloc(memSize);
    hostSumTemp = (float*) malloc(memSize);
    
    // init host memory

    // A = 2, 2, 2, 2 . . .
    // B = 3, 3, 3, 3 . . .
    // C = 0, 0, 0, 0 . . .
    // hostSumTemp = 6, 6, 6, 6, ...
    // hostSumTemp is just temp variable to compare to
    // values are chosen to be really easy
    for(int i=0; i < N; ++i){
        for(int j=0; j < N; ++j){
            hostA[i*N+j] = 2;
            hostB[i*N+j] = 3;
            hostC[i*N+j] = 0;
            hostSumTemp[i*N+j] = 6;
        }
    }

    // Allocate device memory
    hipMalloc((void**) &deviceA, memSize);
    hipMalloc((void**) &deviceB, memSize);
    hipMalloc((void**) &deviceC, memSize);

    // Copy Matrix A and B from host to device
    hipMemcpy(deviceA, hostA, memSize, hipMemcpyHostToDevice);
    hipMemcpy(deviceB, hostB, memSize, hipMemcpyHostToDevice);

    // Invoke Kernel
    dim3 nblocks(N / 64, N / 64);
    dim3 nthreads(32, 32);

    // Init Kernel
    matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
    
    // Transfer from result matrix from device to host
    hipMemcpy(hostC, deviceC, memSize, hipMemcpyDeviceToHost);

    // Check results
    bool isSame = true;
    int row, col;
    for(row=0; row < N; ++row){
        for(col=0; col < N; ++col){
            if(hostC[row*N+col] != hostSumTemp[row*N+col]){
                isSame = false;
                break;
            }
        }
    }

    // Print comparasion
    if(!isSame){
        std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
    } else {
        std::cout << "Results matched.\n";
    }

    // free memory
    free(hostA);
    free(hostB);
    free(hostC);
    free(hostSumTemp);

    hipFree(deviceA);
    hipFree(deviceB);
    hipFree(deviceC);

    return 0;
}
	.text
	.file	"matrixMul.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z28__device_stub__matrixMulCUDAPfS_S_i # -- Begin function _Z28__device_stub__matrixMulCUDAPfS_S_i
	.type	_Z28__device_stub__matrixMulCUDAPfS_S_i,@function
_Z28__device_stub__matrixMulCUDAPfS_S_i: # @_Z28__device_stub__matrixMulCUDAPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matrixMulCUDAPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__matrixMulCUDAPfS_S_i, .Lfunc_end0-_Z28__device_stub__matrixMulCUDAPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$268435456, %edi                # imm = 0x10000000
	callq	malloc
	movq	%rax, %rbx
	movl	$268435456, %edi                # imm = 0x10000000
	callq	malloc
	movq	%rax, %r14
	movl	$1, %edi
	movl	$268435456, %esi                # imm = 0x10000000
	callq	calloc@PLT
	movq	%rax, %r15
	movl	$268435456, %edi                # imm = 0x10000000
	callq	malloc
	movq	%rax, %r12
	xorl	%eax, %eax
	movl	$32768, %ecx                    # imm = 0x8000
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movq	%r12, %rdi
.LBB1_1:                                # %.preheader60
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%r8d, %r8d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1073741824, (%rdx,%r8,4)       # imm = 0x40000000
	movl	$1077936128, (%rsi,%r8,4)       # imm = 0x40400000
	movl	$1086324736, (%rdi,%r8,4)       # imm = 0x40C00000
	incq	%r8
	cmpq	$8192, %r8                      # imm = 0x2000
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rax
	addq	%rcx, %rdi
	addq	%rcx, %rsi
	addq	%rcx, %rdx
	cmpq	$8192, %rax                     # imm = 0x2000
	jne	.LBB1_1
# %bb.4:
	leaq	16(%rsp), %r13
	movl	$268435456, %esi                # imm = 0x10000000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movl	$268435456, %esi                # imm = 0x10000000
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$268435456, %esi                # imm = 0x10000000
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$268435456, %edx                # imm = 0x10000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$268435456, %edx                # imm = 0x10000000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$549755814016, %rdi             # imm = 0x8000000080
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	$8192, %ecx                     # imm = 0x2000
	callq	_Z28__device_stub__matrixMulCUDAPfS_S_i
.LBB1_6:
	movq	(%rsp), %rsi
	movl	$268435456, %edx                # imm = 0x10000000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movb	$1, %al
	xorl	%ecx, %ecx
	movl	$32768, %edx                    # imm = 0x8000
	movq	%r15, %rsi
	movq	%r12, %rdi
.LBB1_7:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_8 Depth 2
	xorl	%r13d, %r13d
.LBB1_8:                                #   Parent Loop BB1_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rsi,%r13,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%rdi,%r13,4), %xmm0
	jne	.LBB1_11
	jp	.LBB1_11
# %bb.9:                                #   in Loop: Header=BB1_8 Depth=2
	incq	%r13
	cmpq	$8192, %r13                     # imm = 0x2000
	jne	.LBB1_8
# %bb.10:                               #   in Loop: Header=BB1_7 Depth=1
	movl	$8192, %r13d                    # imm = 0x2000
	jmp	.LBB1_12
.LBB1_11:                               # %.split.loop.exit
                                        #   in Loop: Header=BB1_7 Depth=1
	xorl	%eax, %eax
.LBB1_12:                               # %.split.loop.exit76
                                        #   in Loop: Header=BB1_7 Depth=1
	incq	%rcx
	addq	%rdx, %rdi
	addq	%rdx, %rsi
	cmpq	$8192, %rcx                     # imm = 0x2000
	jne	.LBB1_7
# %bb.13:
	movl	$_ZSt4cout, %edi
	testb	$1, %al
	jne	.LBB1_15
# %bb.14:
	movl	$.L.str, %esi
	movl	$25, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$8192, %esi                     # imm = 0x2000
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movl	$.L.str.1, %esi
	movl	$8, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbp, %rdi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r13
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r13, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	jmp	.LBB1_16
.LBB1_15:
	movl	$.L.str.2, %esi
	movl	$17, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_16:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matrixMulCUDAPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13matrixMulCUDAPfS_S_i,@object # @_Z13matrixMulCUDAPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z13matrixMulCUDAPfS_S_i
	.p2align	3, 0x0
_Z13matrixMulCUDAPfS_S_i:
	.quad	_Z28__device_stub__matrixMulCUDAPfS_S_i
	.size	_Z13matrixMulCUDAPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Did not match at \n\trow = "
	.size	.L.str, 26

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n\tcol = "
	.size	.L.str.1, 9

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Results matched.\n"
	.size	.L.str.2, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13matrixMulCUDAPfS_S_i"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__matrixMulCUDAPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13matrixMulCUDAPfS_S_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13matrixMulCUDAPfS_S_i ; -- Begin function _Z13matrixMulCUDAPfS_S_i
	.globl	_Z13matrixMulCUDAPfS_S_i
	.p2align	8
	.type	_Z13matrixMulCUDAPfS_S_i,@function
_Z13matrixMulCUDAPfS_S_i:               ; @_Z13matrixMulCUDAPfS_S_i
; %bb.0:
	s_load_b32 s10, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s10, 1
	s_cbranch_scc1 .LBB0_12
; %bb.1:                                ; %.lr.ph60
	s_clause 0x2
	s_load_b32 s13, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_lshl_b32 s11, s14, 6
	s_lshl_b32 s12, s15, 6
	s_add_u32 s8, s0, 32
	s_addc_u32 s9, s1, 0
	v_lshlrev_b32_e32 v2, 1, v0
	v_lshlrev_b32_e32 v3, 1, v5
	v_lshl_add_u32 v4, v0, 6, 0x4000
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s13, 0xffff
	s_mov_b32 s13, 0
	v_mad_u32_u24 v1, v0, s1, v5
	v_lshl_add_u32 v5, v5, 3, 0x4800
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_u32_e64 s0, 0x200, v1
	v_lshl_add_u32 v6, v1, 5, 0x4000
	v_lshl_add_u32 v7, v1, 2, 0x4800
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_load_b32 s15, s[8:9], 0xc
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v1
	v_mov_b32_e32 v0, v6
	s_mov_b32 s18, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s15, s15, 16
	s_mul_i32 s15, s15, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s16, s15, 5
	s_lshl_b32 s17, s15, 2
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_nc_u32_e32 v11, s11, v9
	v_add_nc_u32_e32 v12, s12, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v10, 26, v10
	v_add_nc_u32_e32 v10, v9, v10
	v_add_nc_u32_e32 v9, s15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v16, 6, v10
	v_and_b32_e32 v13, 0xffffffc0, v10
	v_add_nc_u32_e32 v10, s13, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v13
	v_sub_nc_u32_e32 v17, v12, v13
	v_mad_u64_u32 v[12:13], null, s10, v10, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, v17, s10, v[10:11]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[14:15]
	v_add_co_u32 v10, vcc_lo, s6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	global_load_b32 v14, v[10:11], off
	global_load_b32 v12, v[12:13], off
	v_mad_u64_u32 v[10:11], null, 0xfffff804, v16, v[0:1]
	v_cmp_lt_i32_e32 vcc_lo, 0x1ff, v9
	v_add_nc_u32_e32 v0, s16, v0
	s_or_b32 s18, vcc_lo, s18
	s_waitcnt vmcnt(1)
	ds_store_b32 v8, v14
	v_add_nc_u32_e32 v8, s17, v8
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v12
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_4
.LBB0_5:                                ; %Flow90
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_mov_b32 s15, 0
	s_mov_b32 s14, -1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_6:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	v_or_b32_e32 v9, s15, v3
	v_lshl_add_u32 v8, s15, 2, v5
	s_xor_b32 s14, s14, -1
	s_mov_b32 s16, -1
	s_mov_b32 s17, 0
	v_add_nc_u32_e32 v0, s11, v9
	v_lshlrev_b32_e32 v9, 2, v9
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_8 Depth 4
	v_or_b32_e32 v12, s17, v2
	v_lshl_add_u32 v13, s17, 5, v4
	v_mov_b32_e32 v14, v8
	s_xor_b32 s15, s16, -1
	s_mov_b32 s16, 0
	v_lshl_add_u32 v11, v12, 8, v9
	ds_load_b32 v10, v11
.LBB0_8:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_add_nc_u32_e32 v15, s16, v13
	s_add_i32 s16, s16, 4
	ds_load_b32 v16, v14
	ds_load_b32 v15, v15
	v_add_nc_u32_e32 v14, 0x100, v14
	s_cmp_eq_u32 s16, 32
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v15, v16
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=3
	v_add_nc_u32_e32 v14, s12, v12
	s_mov_b32 s17, 1
	s_mov_b32 s16, 0
	ds_store_b32 v11, v10
	v_mad_u64_u32 v[12:13], null, v14, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s15
	global_store_b32 v[12:13], v10, off
	s_cbranch_vccz .LBB0_7
; %bb.10:                               ;   in Loop: Header=BB0_6 Depth=2
	s_mov_b32 s15, 1
	s_and_b32 vcc_lo, exec_lo, s14
	s_mov_b32 s14, 0
	s_cbranch_vccz .LBB0_6
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s13, s13, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s13, s10
	s_cbranch_scc0 .LBB0_2
.LBB0_12:                               ; %._crit_edge61
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matrixMulCUDAPfS_S_i
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13matrixMulCUDAPfS_S_i, .Lfunc_end0-_Z13matrixMulCUDAPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 736
; NumSgprs: 21
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13matrixMulCUDAPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z13matrixMulCUDAPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
