#include<stdio.h>
#include<cuda.h>

__global__ void update(int *matrix,int *query,int *row,int *row_ele,int *no_query,int *prev_array,int n,int m,int q)
{
	int id=blockIdx.x*blockDim.x+threadIdx.x;
	if(id<(m*q))
	{

	int query_no = id/m;
	int row_no = id%m;
	if(matrix[row_no*n+row[query_no]-1]==row_ele[query_no])   // Updating if the row element matches
	{	
		for(int i=0;i<no_query[query_no];i++)
		{
			if(query[prev_array[query_no]+i*3+2]==0)
			{
				atomicSub(&matrix[row_no*n+query[prev_array[query_no]+i*3]-1] , query[prev_array[query_no]+i*3+1]);
			}
			else
			{
				atomicAdd(&matrix[row_no*n+query[prev_array[query_no]+i*3]-1] , query[prev_array[query_no]+i*3+1]);
			}	
		}
	}
	}	
}

int main(int argc,char **argv)
{
  int M,N,q;
  FILE *fpi,*fpo;
  fpi=fopen(argv[1],"r");
  fpo=fopen(argv[2],"w");
  fscanf(fpi,"%d %d", &M,&N);
  int *matrix, *hmatrix;
  char character;int *row,*row_ele,*drow,*drow_ele;
  int *query,*no_query,*prev_array,*dquery,*dno_query,*dprev_array;
  cudaMalloc(&matrix, (M) * (N) * sizeof(int));
  hmatrix = (int *)malloc(M * N * sizeof(int));
  for (int ii = 0; ii < M; ++ii) 
  {
    for (int jj = 0; jj < N; ++jj) 
    {
      fscanf(fpi,"%d",&hmatrix[ii*N+jj]);
    }
  }
  cudaMemcpy(matrix, hmatrix, M * N * sizeof(int), cudaMemcpyHostToDevice);
  fscanf(fpi,"%d", &q);
  cudaMalloc(&dquery, 90 * q * sizeof(int));
  cudaMalloc(&drow, q * sizeof(int));
  cudaMalloc(&drow_ele, q * sizeof(int));
  cudaMalloc(&dno_query, q * sizeof(int));
  cudaMalloc(&dprev_array, q * sizeof(int));
  query = (int *)malloc(90 * q * sizeof(int));
  row = (int *)malloc(q * sizeof(int));
  row_ele = (int *)malloc(q * sizeof(int));
  no_query = (int *)malloc(q * sizeof(int));
  prev_array = (int *)malloc(q * sizeof(int));
  int prev=0;char c1[50];

  // Parsing Queries
  for (int i = 0; i < q; i++)
  {
  	fscanf(fpi,"%[^U]s",c1);
  	fscanf(fpi,"%c",&character);
  	fscanf(fpi," %c",&character);
  	fscanf(fpi,"%d %d %d",&row[i],&row_ele[i],&no_query[i]);
  	for(int j=0;j<no_query[i];j++)
  	{
  		fscanf(fpi," %c %d %d %c",&character,&query[prev+(j*3)],&query[prev+(j*3)+1],&character);
  		if(character=='+')
  			query[prev+(j*3)+2]=1;
  		else
  			query[prev+(j*3)+2]=0;
  	}
  	prev_array[i]=prev;
  	prev += no_query[i]*3;
  }
  cudaMemcpy(dquery, query, 90 * q * sizeof(int), cudaMemcpyHostToDevice);
  cudaMemcpy(drow, row,  q * sizeof(int), cudaMemcpyHostToDevice);
  cudaMemcpy(drow_ele, row_ele, q * sizeof(int), cudaMemcpyHostToDevice);
  cudaMemcpy(dno_query, no_query, q * sizeof(int), cudaMemcpyHostToDevice);
  cudaMemcpy(dprev_array, prev_array, q * sizeof(int), cudaMemcpyHostToDevice);
  update<<<3000,1024>>>(matrix,dquery,drow,drow_ele,dno_query,dprev_array,N,M,q);
  cudaMemcpy(hmatrix, matrix, M * N * sizeof(int), cudaMemcpyDeviceToHost);
  cudaDeviceSynchronize();
  for (int ii = 0; ii < M; ++ii) 
  {
    for (int jj = 0; jj < N; ++jj) 
    {
    	if(jj==N-1)
    		fprintf(fpo,"%d ",hmatrix[ii*N+jj]);
    	else
      		fprintf(fpo,"%d ",hmatrix[ii*N+jj]);
    }
    fprintf(fpo,"\n");
  }
  return 0;
}
	.file	"tmpxft_00276791_00000000-6_Assignment3_GPU.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z6updatePiS_S_S_S_S_iiiPiS_S_S_S_S_iii
	.type	_Z38__device_stub__Z6updatePiS_S_S_S_S_iiiPiS_S_S_S_S_iii, @function
_Z38__device_stub__Z6updatePiS_S_S_S_S_iiiPiS_S_S_S_S_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z6updatePiS_S_S_S_S_iii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z38__device_stub__Z6updatePiS_S_S_S_S_iiiPiS_S_S_S_S_iii, .-_Z38__device_stub__Z6updatePiS_S_S_S_S_iiiPiS_S_S_S_S_iii
	.globl	_Z6updatePiS_S_S_S_S_iii
	.type	_Z6updatePiS_S_S_S_S_iii, @function
_Z6updatePiS_S_S_S_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z6updatePiS_S_S_S_S_iiiPiS_S_S_S_S_iii
	.cfi_endproc
.LFE2053:
	.size	_Z6updatePiS_S_S_S_S_iii, .-_Z6updatePiS_S_S_S_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"w"
.LC2:
	.string	"%d %d"
.LC3:
	.string	"%d"
.LC4:
	.string	"%[^U]s"
.LC5:
	.string	"%c"
.LC6:
	.string	" %c"
.LC7:
	.string	"%d %d %d"
.LC8:
	.string	" %c %d %d %c"
.LC9:
	.string	"%d "
.LC10:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC3(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$232, %rsp
	.cfi_def_cfa_offset 288
	movq	8(%rsi), %rdi
	leaq	.LC0(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	movq	16(%rbx), %rdi
	leaq	.LC1(%rip), %rsi
	movq	%rax, 8(%rsp)
	call	fopen@PLT
	movq	8(%rsp), %rdi
	leaq	80(%rsp), %rcx
	leaq	76(%rsp), %rdx
	movq	%rax, 16(%rsp)
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	76(%rsp), %esi
	imull	80(%rsp), %esi
	leaq	88(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	76(%rsp), %edi
	imull	80(%rsp), %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, %rbx
.L9:
	movl	76(%rsp), %edx
	cmpl	%r12d, %edx
	jle	.L24
	xorl	%r13d, %r13d
.L11:
	movl	80(%rsp), %eax
	cmpl	%r13d, %eax
	jle	.L25
	imull	%r12d, %eax
	movq	8(%rsp), %rdi
	movq	%rbp, %rsi
	addl	%r13d, %eax
	incl	%r13d
	cltq
	leaq	(%rbx,%rax,4), %rdx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	jmp	.L11
.L25:
	incl	%r12d
	jmp	.L9
.L24:
	imull	80(%rsp), %edx
	movq	88(%rsp), %rdi
	movq	%rbx, %rsi
	xorl	%r14d, %r14d
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	leaq	84(%rsp), %rdx
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	call	__isoc23_fscanf@PLT
	imull	$90, 84(%rsp), %esi
	leaq	112(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	84(%rsp), %rsi
	leaq	96(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	84(%rsp), %rsi
	leaq	104(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	84(%rsp), %rsi
	leaq	120(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	84(%rsp), %rsi
	leaq	128(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	84(%rsp), %rbp
	imull	$90, %ebp, %edi
	salq	$2, %rbp
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movq	%rbp, %rdi
	xorl	%ebp, %ebp
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	movq	32(%rsp), %r15
	movq	%rax, 40(%rsp)
.L12:
	movl	84(%rsp), %edx
	cmpl	%ebp, %edx
	jle	.L26
	movq	8(%rsp), %rdi
	leaq	166(%rsp), %rdx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movq	8(%rsp), %rdi
	leaq	75(%rsp), %rdx
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rsi
	movq	%rdx, 48(%rsp)
	call	__isoc23_fscanf@PLT
	movq	48(%rsp), %rdx
	movq	8(%rsp), %rdi
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rsi
	call	__isoc23_fscanf@PLT
	movq	24(%rsp), %rax
	movq	8(%rsp), %rdi
	movq	%r15, %r8
	leaq	0(,%rbp,4), %rdx
	leaq	.LC7(%rip), %rsi
	leaq	(%rax,%rdx), %rcx
	addq	%r12, %rdx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movslq	%r14d, %rax
	xorl	%r10d, %r10d
	leaq	0(%r13,%rax,4), %rcx
.L13:
	movl	(%r15), %eax
	cmpl	%r10d, %eax
	jle	.L27
	leaq	75(%rsp), %rdx
	movq	8(%rsp), %rdi
	leaq	4(%rcx), %r8
	xorl	%eax, %eax
	movq	%rdx, %r9
	leaq	.LC8(%rip), %rsi
	movl	%r10d, 60(%rsp)
	movq	%rcx, 48(%rsp)
	call	__isoc23_fscanf@PLT
	movq	48(%rsp), %rcx
	xorl	%eax, %eax
	movl	60(%rsp), %r10d
	cmpb	$43, 75(%rsp)
	sete	%al
	incl	%r10d
	addq	$12, %rcx
	movl	%eax, -4(%rcx)
	jmp	.L13
.L27:
	movq	40(%rsp), %rcx
	leal	(%rax,%rax,2), %eax
	addq	$4, %r15
	movl	%r14d, (%rcx,%rbp,4)
	addl	%eax, %r14d
	incq	%rbp
	jmp	.L12
.L26:
	imull	$90, %edx, %edx
	movq	112(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	84(%rsp), %rdx
	movq	96(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	84(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	104(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	84(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	120(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	84(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	128(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536871287, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	%rax
	.cfi_def_cfa_offset 296
	movl	92(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 304
	movl	92(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 312
	movl	104(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 320
	movq	160(%rsp), %r9
	movq	152(%rsp), %r8
	movq	136(%rsp), %rcx
	movq	128(%rsp), %rdx
	movq	144(%rsp), %rsi
	movq	120(%rsp), %rdi
	call	_Z38__device_stub__Z6updatePiS_S_S_S_S_iiiPiS_S_S_S_S_iii
	addq	$32, %rsp
	.cfi_def_cfa_offset 288
.L16:
	movl	76(%rsp), %edx
	imull	80(%rsp), %edx
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	movq	88(%rsp), %rsi
	movl	$2, %ecx
	leaq	.LC9(%rip), %rbp
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
.L17:
	cmpl	%r12d, 76(%rsp)
	jle	.L28
	xorl	%r13d, %r13d
.L19:
	movl	80(%rsp), %eax
	cmpl	%r13d, %eax
	jle	.L29
	imull	%r12d, %eax
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$2, %esi
	addl	%r13d, %eax
	incl	%r13d
	cltq
	movl	(%rbx,%rax,4), %ecx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L19
.L29:
	movq	16(%rsp), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	incl	%r12d
	leaq	.LC10(%rip), %rdx
	call	__fprintf_chk@PLT
	jmp	.L17
.L28:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$232, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z6updatePiS_S_S_S_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6updatePiS_S_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include<hip/hip_runtime.h>

__global__ void update(int *matrix,int *query,int *row,int *row_ele,int *no_query,int *prev_array,int n,int m,int q)
{
	int id=blockIdx.x*blockDim.x+threadIdx.x;
	if(id<(m*q))
	{

	int query_no = id/m;
	int row_no = id%m;
	if(matrix[row_no*n+row[query_no]-1]==row_ele[query_no])   // Updating if the row element matches
	{	
		for(int i=0;i<no_query[query_no];i++)
		{
			if(query[prev_array[query_no]+i*3+2]==0)
			{
				atomicSub(&matrix[row_no*n+query[prev_array[query_no]+i*3]-1] , query[prev_array[query_no]+i*3+1]);
			}
			else
			{
				atomicAdd(&matrix[row_no*n+query[prev_array[query_no]+i*3]-1] , query[prev_array[query_no]+i*3+1]);
			}	
		}
	}
	}	
}

int main(int argc,char **argv)
{
  int M,N,q;
  FILE *fpi,*fpo;
  fpi=fopen(argv[1],"r");
  fpo=fopen(argv[2],"w");
  fscanf(fpi,"%d %d", &M,&N);
  int *matrix, *hmatrix;
  char character;int *row,*row_ele,*drow,*drow_ele;
  int *query,*no_query,*prev_array,*dquery,*dno_query,*dprev_array;
  hipMalloc(&matrix, (M) * (N) * sizeof(int));
  hmatrix = (int *)malloc(M * N * sizeof(int));
  for (int ii = 0; ii < M; ++ii) 
  {
    for (int jj = 0; jj < N; ++jj) 
    {
      fscanf(fpi,"%d",&hmatrix[ii*N+jj]);
    }
  }
  hipMemcpy(matrix, hmatrix, M * N * sizeof(int), hipMemcpyHostToDevice);
  fscanf(fpi,"%d", &q);
  hipMalloc(&dquery, 90 * q * sizeof(int));
  hipMalloc(&drow, q * sizeof(int));
  hipMalloc(&drow_ele, q * sizeof(int));
  hipMalloc(&dno_query, q * sizeof(int));
  hipMalloc(&dprev_array, q * sizeof(int));
  query = (int *)malloc(90 * q * sizeof(int));
  row = (int *)malloc(q * sizeof(int));
  row_ele = (int *)malloc(q * sizeof(int));
  no_query = (int *)malloc(q * sizeof(int));
  prev_array = (int *)malloc(q * sizeof(int));
  int prev=0;char c1[50];

  // Parsing Queries
  for (int i = 0; i < q; i++)
  {
  	fscanf(fpi,"%[^U]s",c1);
  	fscanf(fpi,"%c",&character);
  	fscanf(fpi," %c",&character);
  	fscanf(fpi,"%d %d %d",&row[i],&row_ele[i],&no_query[i]);
  	for(int j=0;j<no_query[i];j++)
  	{
  		fscanf(fpi," %c %d %d %c",&character,&query[prev+(j*3)],&query[prev+(j*3)+1],&character);
  		if(character=='+')
  			query[prev+(j*3)+2]=1;
  		else
  			query[prev+(j*3)+2]=0;
  	}
  	prev_array[i]=prev;
  	prev += no_query[i]*3;
  }
  hipMemcpy(dquery, query, 90 * q * sizeof(int), hipMemcpyHostToDevice);
  hipMemcpy(drow, row,  q * sizeof(int), hipMemcpyHostToDevice);
  hipMemcpy(drow_ele, row_ele, q * sizeof(int), hipMemcpyHostToDevice);
  hipMemcpy(dno_query, no_query, q * sizeof(int), hipMemcpyHostToDevice);
  hipMemcpy(dprev_array, prev_array, q * sizeof(int), hipMemcpyHostToDevice);
  update<<<3000,1024>>>(matrix,dquery,drow,drow_ele,dno_query,dprev_array,N,M,q);
  hipMemcpy(hmatrix, matrix, M * N * sizeof(int), hipMemcpyDeviceToHost);
  hipDeviceSynchronize();
  for (int ii = 0; ii < M; ++ii) 
  {
    for (int jj = 0; jj < N; ++jj) 
    {
    	if(jj==N-1)
    		fprintf(fpo,"%d ",hmatrix[ii*N+jj]);
    	else
      		fprintf(fpo,"%d ",hmatrix[ii*N+jj]);
    }
    fprintf(fpo,"\n");
  }
  return 0;
}
	.text
	.file	"Assignment3_GPU.hip"
	.globl	_Z21__device_stub__updatePiS_S_S_S_S_iii # -- Begin function _Z21__device_stub__updatePiS_S_S_S_S_iii
	.type	_Z21__device_stub__updatePiS_S_S_S_S_iii,@function
_Z21__device_stub__updatePiS_S_S_S_S_iii: # @_Z21__device_stub__updatePiS_S_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6updatePiS_S_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__updatePiS_S_S_S_S_iii, .Lfunc_end0-_Z21__device_stub__updatePiS_S_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %r15
	movq	16(%rbx), %rdi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	leaq	20(%rsp), %r14
	leaq	16(%rsp), %r12
	movl	$.L.str.2, %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	movq	%r12, %rcx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	(%r14), %rax
	movslq	(%r12), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movl	(%r14), %r13d
	movl	(%r12), %ebx
	movl	%ebx, %eax
	imull	%r13d, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	testl	%r13d, %r13d
	jle	.LBB1_8
# %bb.1:                                # %.preheader83.preheader
	xorl	%ebp, %ebp
	movq	24(%rsp), %r12                  # 8-byte Reload
.LBB1_2:                                # %.preheader83
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB1_6
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_2 Depth=1
	xorl	%r14d, %r14d
.LBB1_4:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebp, %ebx
	movslq	%ebx, %rax
	addq	%r14, %rax
	leaq	(%r12,%rax,4), %rdx
	movl	$.L.str.3, %esi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	16(%rsp), %ebx
	incq	%r14
	cmpl	%ebx, %r14d
	jl	.LBB1_4
# %bb.5:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	20(%rsp), %r13d
.LBB1_6:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incl	%ebp
	cmpl	%r13d, %ebp
	jl	.LBB1_2
# %bb.7:                                # %._crit_edge88.loopexit
	imull	%r13d, %ebx
	movslq	%ebx, %r12
	shlq	$2, %r12
.LBB1_8:                                # %._crit_edge88
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	12(%rsp), %r12
	movl	$.L.str.3, %esi
	movq	%r15, %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	(%r12), %rax
	imulq	$360, %rax, %rsi                # imm = 0x168
	leaq	96(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rsi
	shlq	$2, %rsi
	leaq	112(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rsi
	shlq	$2, %rsi
	leaq	104(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rsi
	shlq	$2, %rsi
	leaq	88(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rsi
	shlq	$2, %rsi
	leaq	80(%rsp), %rdi
	callq	hipMalloc
	movslq	(%r12), %rbx
	imulq	$360, %rbx, %r12                # imm = 0x168
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r14
	leaq	(,%rbx,4), %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	testq	%rbx, %rbx
	jle	.LBB1_16
# %bb.9:                                # %.lr.ph97.preheader
	movq	%r14, 120(%rsp)                 # 8-byte Spill
	addq	$4, %r14
	movq	%r14, 136(%rsp)                 # 8-byte Spill
	leaq	11(%rsp), %rbp
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
.LBB1_10:                               # %.lr.ph97
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_12 Depth 2
	movl	$.L.str.4, %esi
	movq	%r15, %rdi
	leaq	144(%rsp), %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	$.L.str.5, %esi
	movq	%r15, %rdi
	movq	%rbp, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	$.L.str.6, %esi
	movq	%r15, %rdi
	movq	%rbp, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	48(%rsp), %rax                  # 8-byte Reload
	leaq	(%rax,%rbx,4), %rdx
	movq	56(%rsp), %rax                  # 8-byte Reload
	leaq	(%rax,%rbx,4), %rcx
	movq	64(%rsp), %r14                  # 8-byte Reload
	leaq	(%r14,%rbx,4), %r12
	movl	$.L.str.7, %esi
	movq	%r15, %rdi
	movq	%r12, %r8
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	(%r14,%rbx,4), %eax
	testl	%eax, %eax
	jle	.LBB1_14
# %bb.11:                               # %.lr.ph91.preheader
                                        #   in Loop: Header=BB1_10 Depth=1
	movl	%r13d, 44(%rsp)                 # 4-byte Spill
	movslq	%r13d, %rax
	movq	136(%rsp), %rcx                 # 8-byte Reload
	leaq	(%rcx,%rax,4), %r13
	xorl	%r14d, %r14d
.LBB1_12:                               # %.lr.ph91
                                        #   Parent Loop BB1_10 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	-4(%r13), %rcx
	movl	$.L.str.8, %esi
	movq	%r15, %rdi
	movq	%rbp, %rdx
	movq	%r13, %r8
	movq	%rbp, %r9
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	xorl	%eax, %eax
	cmpb	$43, 11(%rsp)
	sete	%al
	movl	%eax, 4(%r13)
	incq	%r14
	movslq	(%r12), %rax
	addq	$12, %r13
	cmpq	%rax, %r14
	jl	.LBB1_12
# %bb.13:                               #   in Loop: Header=BB1_10 Depth=1
	movl	44(%rsp), %r13d                 # 4-byte Reload
.LBB1_14:                               # %._crit_edge92
                                        #   in Loop: Header=BB1_10 Depth=1
	movq	72(%rsp), %rcx                  # 8-byte Reload
	movl	%r13d, (%rcx,%rbx,4)
	leal	(%rax,%rax,2), %eax
	addl	%eax, %r13d
	incq	%rbx
	movslq	12(%rsp), %rax
	cmpq	%rax, %rbx
	jl	.LBB1_10
# %bb.15:                               # %._crit_edge98.loopexit
	imulq	$360, %rax, %r12                # imm = 0x168
	movq	120(%rsp), %r14                 # 8-byte Reload
.LBB1_16:                               # %._crit_edge98
	movq	96(%rsp), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	112(%rsp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	104(%rsp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	88(%rsp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	80(%rsp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	1976(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_18
# %bb.17:
	movq	32(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	112(%rsp), %rdx
	movq	104(%rsp), %rcx
	movq	88(%rsp), %r8
	movq	80(%rsp), %r9
	movl	16(%rsp), %eax
	movl	20(%rsp), %r10d
	movl	12(%rsp), %r11d
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z21__device_stub__updatePiS_S_S_S_S_iii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_18:
	movq	32(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	24(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	cmpl	$0, 20(%rsp)
	movq	128(%rsp), %r15                 # 8-byte Reload
	jle	.LBB1_24
# %bb.19:                               # %.preheader.preheader
	xorl	%ebx, %ebx
.LBB1_20:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_22 Depth 2
	movl	16(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB1_23
# %bb.21:                               # %.lr.ph101.preheader
                                        #   in Loop: Header=BB1_20 Depth=1
	xorl	%r14d, %r14d
.LBB1_22:                               # %.lr.ph101
                                        #   Parent Loop BB1_20 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebx, %eax
	cltq
	addq	%r14, %rax
	movl	(%r12,%rax,4), %edx
	movl	$.L.str.9, %esi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movl	16(%rsp), %eax
	incq	%r14
	cmpl	%eax, %r14d
	jl	.LBB1_22
.LBB1_23:                               # %._crit_edge102
                                        #   in Loop: Header=BB1_20 Depth=1
	movl	$10, %edi
	movq	%r15, %rsi
	callq	fputc@PLT
	incl	%ebx
	cmpl	20(%rsp), %ebx
	jl	.LBB1_20
.LBB1_24:                               # %._crit_edge104
	xorl	%eax, %eax
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6updatePiS_S_S_S_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6updatePiS_S_S_S_S_iii,@object # @_Z6updatePiS_S_S_S_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z6updatePiS_S_S_S_S_iii
	.p2align	3, 0x0
_Z6updatePiS_S_S_S_S_iii:
	.quad	_Z21__device_stub__updatePiS_S_S_S_S_iii
	.size	_Z6updatePiS_S_S_S_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"w"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d %d"
	.size	.L.str.2, 6

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%[^U]s"
	.size	.L.str.4, 7

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%c"
	.size	.L.str.5, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	" %c"
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%d %d %d"
	.size	.L.str.7, 9

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	" %c %d %d %c"
	.size	.L.str.8, 13

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"%d "
	.size	.L.str.9, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6updatePiS_S_S_S_S_iii"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__updatePiS_S_S_S_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6updatePiS_S_S_S_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6updatePiS_S_S_S_S_iii ; -- Begin function _Z6updatePiS_S_S_S_S_iii
	.globl	_Z6updatePiS_S_S_S_S_iii
	.p2align	8
	.type	_Z6updatePiS_S_S_S_S_iii,@function
_Z6updatePiS_S_S_S_S_iii:               ; @_Z6updatePiS_S_S_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s18, s17
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.1:
	s_ashr_i32 s2, s17, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s3, s17, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s3, s3, s2
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v3
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s2, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s4, v0
	s_load_b256 s[4:11], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v2, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v3
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_mul_lo_u32 v4, v4, s17
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v3, vcc_lo
	v_sub_nc_u32_e32 v1, v1, v4
	global_load_b32 v0, v[5:6], off
	v_mul_lo_u32 v4, v1, s16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v4, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v0, v[0:1], off offset:-4
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.preheader
	s_load_b128 s[0:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, 0, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.3:                                ; %.lr.ph
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_add_u32 s2, s4, -4
	s_addc_u32 s3, s5, -1
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[2:3], off
	s_add_i32 s5, s5, 1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_add_u32 s0, s0, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_addc_u32 s1, s1, 0
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b96 v[5:7], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_add_nc_u32_e32 v8, v5, v4
	v_sub_nc_u32_e32 v5, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v6, v5, vcc_lo
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v5, vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v9, vcc_lo
	global_atomic_add_u32 v[5:6], v7, off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, s5, v5
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_4
.LBB0_5:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6updatePiS_S_S_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6updatePiS_S_S_S_S_iii, .Lfunc_end0-_Z6updatePiS_S_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 664
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6updatePiS_S_S_S_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z6updatePiS_S_S_S_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
