
#include "CUDAdrr.cuh"

#include <cuda.h>
#include <cuda_runtime_api.h>
#include <algorithm> 
#include <iostream>
#include <vector>

#define KERNEL                      __global__
#define HOST                        __host__
#define DEVICE                      __device__
#define HOST_AND_DEVICE             __host__ __device__
#define DEVICE_CONST                __device__ __constant__

// This variable contains the DICOM set
float* d_object3D;

// This variable contains the 2D output from CUDA
float *d_object2D;

// This variable contains the mask output 
unsigned *d_mask2D;

// Constants depending on the DICOM
DEVICE_CONST int d_sizeCT[3];
DEVICE_CONST  float ctPixelSpacing[3];

// Constant depending on image output
DEVICE_CONST int DRRImageSize[2];

// Constants dependion on the specific DRR
DEVICE_CONST  float d_DRR_Parameters[12];

DEVICE_CONST  bool d_useMask;

// This variable contains the DICOM loaded as a Texture ( read-only, fast-cached memory)
cudaTextureObject_t tex_object3D = 0;

// This variable contains the output Mask loaded as a Texture ( read-only, fast-cached memory)
cudaTextureObject_t tex_mask2D = 0;

cudaStream_t stream1;

void loadDICOMInGPUMemory(float *cpp_object3D, int *sizeCT, float *pixelSpacing)
{
	long int object3Dsize = sizeCT[0] * sizeCT[1] * sizeCT[2];
	cudaStreamCreateWithFlags(&stream1, cudaStreamNonBlocking);


	cudaMalloc((void**)&d_object3D, object3Dsize * sizeof(float));
	cudaMemcpyAsync(d_object3D, cpp_object3D, object3Dsize * sizeof(float), cudaMemcpyHostToDevice, stream1);

	cudaMemcpyToSymbol(ctPixelSpacing, pixelSpacing, 3 * sizeof(float), 0, cudaMemcpyHostToDevice);
	cudaMemcpyToSymbol(d_sizeCT, sizeCT, 3 * sizeof(int), 0, cudaMemcpyHostToDevice);
	

	// create texture object
	cudaResourceDesc resDesc;
	memset(&resDesc, 0, sizeof(resDesc));
	resDesc.resType = cudaResourceTypeLinear;
	resDesc.res.linear.devPtr = d_object3D;
	resDesc.res.linear.desc.f = cudaChannelFormatKindFloat;
	resDesc.res.linear.desc.x = 32; // bits per channel
	resDesc.res.linear.sizeInBytes = object3Dsize * sizeof(float);

	cudaTextureDesc texDesc;
	memset(&texDesc, 0, sizeof(texDesc));
	texDesc.readMode = cudaReadModeElementType;

	// create CUDA texture object
	cudaDestroyTextureObject(tex_object3D);
	cudaCreateTextureObject(&tex_object3D, &resDesc, &texDesc, NULL);

	cudaStreamDestroy(stream1);

}


void updateMaskFlagInGPUMemory(bool useMask)
{	
	cudaMemcpyToSymbol(d_useMask, &useMask, 1 * sizeof(bool), 0, cudaMemcpyHostToDevice);
}

void loadMaskInGPUMemory(unsigned char* mask_2D, int dimX, int dimZ, bool useMask)
{
	long int mask2DSize = dimX * dimZ;
	cudaStreamCreateWithFlags(&stream1, cudaStreamNonBlocking);		

	cudaMalloc((void**)&d_mask2D, mask2DSize * sizeof(unsigned char));
	cudaMemcpyAsync(d_mask2D, mask_2D, mask2DSize * sizeof(unsigned char), cudaMemcpyHostToDevice, stream1);

	cudaTextureDesc texDesc;
	memset(&texDesc, 0, sizeof(texDesc));
	texDesc.readMode = cudaReadModeElementType;

	// create texture object
	cudaResourceDesc resDesc;
	memset(&resDesc, 0, sizeof(resDesc));
	resDesc.res.linear.devPtr = d_mask2D;
	resDesc.resType = cudaResourceTypeLinear;	
	resDesc.res.linear.desc.f = cudaChannelFormatKindUnsigned;
	resDesc.res.linear.desc.x = 8; // bits per channel
	resDesc.res.linear.sizeInBytes = mask2DSize * sizeof(unsigned char);	

	// create CUDA texture object
	cudaDestroyTextureObject(tex_mask2D);
	cudaCreateTextureObject(&tex_mask2D, &resDesc, &texDesc, NULL);

	updateMaskFlagInGPUMemory(useMask);

	cudaStreamDestroy(stream1);
}

void loadOuputVariablesInGPUMemory(int dimX, int dimZ)
{
	long int vectorSize = dimX* dimZ;
	int OutputImageSize[2] = { dimX, dimZ };

	cudaMalloc((void**)&d_object2D, vectorSize * sizeof(float));

	cudaMemcpyToSymbol(DRRImageSize, OutputImageSize, 2 * sizeof(int), 0, cudaMemcpyHostToDevice);
}


void freeDICOMFromGPUMemory()
{
	cudaFree(d_object3D);
}

void freeAuxiliaryVariablesInGPUMemory()
{
	cudaFree(d_object2D);
}

							


__global__ void drrCUDA(float* object2D, cudaTextureObject_t tex_object3D, cudaTextureObject_t tex_mask2D)
{

	float stepInX[3] = { d_DRR_Parameters[0],d_DRR_Parameters[1],d_DRR_Parameters[2] };
	float stepInY[3] = { d_DRR_Parameters[3],d_DRR_Parameters[4],d_DRR_Parameters[5] };
	float corner00[3] = { d_DRR_Parameters[6],d_DRR_Parameters[7],d_DRR_Parameters[8] };
	float SourceWorld[3] = { d_DRR_Parameters[9],d_DRR_Parameters[10],d_DRR_Parameters[11] };
	 
	int total_dx = DRRImageSize[0];
	int total_dz = DRRImageSize[1];
	
	//Every thread calculates its own id number
	long int idx = (blockIdx.x*blockDim.x) + threadIdx.x;	

	// This checks if the thread number is bigger than the amount of pixels
	if (idx >= total_dx * total_dz)
		return;

	// Converting number of pixels to rows and columns
	int dz = idx / total_dx;
	int dx = idx - dz*total_dx;


	if (d_useMask)
	{
		//unsigned char maskValue = 0;
		unsigned char maskValue = tex1Dfetch<unsigned char>(tex_mask2D, idx);
		if (maskValue == 0)
		{
			object2D[idx] = 0;
			return;
		}			
	}

	//Calculate the spatial position of the pixel
	//drrPixelWorld_0[idx] = *corner00_0 + ((*stepInX_0)*(threadIdx.x)) + ((*stepInY_0)*(blockIdx.x));
	//drrPixelWorld_1[idx] = *corner00_1 + ((*stepInX_1)*(threadIdx.x)) + ((*stepInY_1)*(blockIdx.x));
	//drrPixelWorld_2[idx] = *corner00_2 + ((*stepInX_2)*(threadIdx.x)) + ((*stepInY_2)*(blockIdx.x));
	float drrPixelWorld[3] = { 0 };
	drrPixelWorld[0] = corner00[0] + ((stepInX[0])*dx) + ((stepInY[0])*dz);
	drrPixelWorld[1] = corner00[1] + ((stepInX[1])*dx) + ((stepInY[1])*dz);
	drrPixelWorld[2] = corner00[2] + ((stepInX[2])*dx) + ((stepInY[2])*dz);

	//Calculate the ray vector
	float rayVector[3] = { 0 };
	rayVector[0] = drrPixelWorld[0] - SourceWorld[0];
	rayVector[1] = drrPixelWorld[1] - SourceWorld[1];
	rayVector[2] = drrPixelWorld[2] - SourceWorld[2];

	float alpha1[3];
	float alphaN[3];
	float auxalphaMin[3] = {-2, -2, -2};
	float auxalphaMax[3] = {2 , 2 , 2};


	//Calculate alphaMin and alphaMax 
	if (rayVector[2] != 0)
	{
		alpha1[0] = (0.0 - (SourceWorld[2])) / rayVector[2];
		alphaN[0] = ((d_sizeCT[2]) * (ctPixelSpacing[2]) - (SourceWorld[2])) / rayVector[2];
		auxalphaMin[0] = alphaN[0];
		auxalphaMax[0] = alpha1[0];

		if (alpha1[0] < alphaN[0]) 
		{
			auxalphaMin[0] = alpha1[0];
			auxalphaMax[0] = alphaN[0];
		}
	}

	if (rayVector[1] != 0)
	{
		alpha1[1] = (0.0 - (SourceWorld[1])) / rayVector[1];
		alphaN[1] = ((d_sizeCT[1]) * (ctPixelSpacing[1]) - (SourceWorld[1])) / rayVector[1];
		auxalphaMin[1] = alphaN[1];
		auxalphaMax[1] = alpha1[1];

		if (alpha1[1] < alphaN[1]) 
		{
			auxalphaMin[1] = alpha1[1];
			auxalphaMax[1] = alphaN[1];
		}
	}


	if (rayVector[0] != 0)
	{
		alpha1[2] = (0.0 - (SourceWorld[0])) / rayVector[0];
		alphaN[2] = ((d_sizeCT[0]) * (ctPixelSpacing[0]) - (SourceWorld[0])) / rayVector[0];
		auxalphaMin[2] = alphaN[2];
		auxalphaMax[2] = alpha1[2];

		if (alpha1[2] < alphaN[2]) 
		{
			auxalphaMin[2] = alpha1[2];
			auxalphaMax[2] = alphaN[2];
		}
	}

	
	float alphaMin;

	if (auxalphaMin[0] > auxalphaMin[1]) //x > y
	{ 
		alphaMin = auxalphaMin[2];
		if (auxalphaMin[0] > alphaMin) { //x > y, x > z
			alphaMin = auxalphaMin[0];
		}
	}
	else //y > x
	{ 
		alphaMin = auxalphaMin[2];
		if (auxalphaMin[1] > alphaMin)  //y > x, y > z
			alphaMin = auxalphaMin[1];
	}

	float alphaMax;

	if (auxalphaMax[0] < auxalphaMax[1])  // x < y
	{
		alphaMax = auxalphaMax[2];
		if (auxalphaMax[0] < alphaMax)  // x < y, x < z
			alphaMax = auxalphaMax[0];	
	}
	else // y < x
	{ 
		alphaMax = auxalphaMax[2];
		if (auxalphaMax[1] < alphaMax)  // y < x, y < z
			alphaMax = auxalphaMax[1];
	}

	float firstIntersection[3], firstIntersectionIndex[3], firstIntersectionIndexUp[3], firstIntersectionIndexDown[3];

	//Calculate the first intersection of the ray with the planes (alphaX, alphaY and alphaZ)
	firstIntersection[0] = (SourceWorld[0]) + (alphaMin * rayVector[0]);
	firstIntersection[1] = (SourceWorld[1]) + (alphaMin * rayVector[1]);
	firstIntersection[2] = (SourceWorld[2]) + (alphaMin * rayVector[2]);
	
	firstIntersectionIndex[0] = firstIntersection[0] / (ctPixelSpacing[0]);
	firstIntersectionIndex[1] = firstIntersection[1] / (ctPixelSpacing[1]);
	firstIntersectionIndex[2] = firstIntersection[2] / (ctPixelSpacing[2]);


	firstIntersectionIndexUp[0] = (int)ceil(firstIntersectionIndex[0]);
	firstIntersectionIndexUp[1] = (int)ceil(firstIntersectionIndex[1]);
	firstIntersectionIndexUp[2] = (int)ceil(firstIntersectionIndex[2]);

	firstIntersectionIndexDown[0] = (int)floor(firstIntersectionIndex[0]);
	firstIntersectionIndexDown[1] = (int)floor(firstIntersectionIndex[1]);
	firstIntersectionIndexDown[2] = (int)floor(firstIntersectionIndex[2]);

	float alpha[3] = {2,2,2}, alphaIntersectionUp[3], alphaIntersectionDown[3];

	if (rayVector[2] != 0)
	{
		alphaIntersectionUp[2] = (firstIntersectionIndexUp[2] * (ctPixelSpacing[2]) - (SourceWorld[2])) / rayVector[2];
		alphaIntersectionDown[2] = (firstIntersectionIndexDown[2] * (ctPixelSpacing[2]) - (SourceWorld[2])) / rayVector[2];
		alpha[0] = alphaIntersectionDown[2];
		if (alphaIntersectionUp[2] > alpha[0])
			alpha[0] = alphaIntersectionUp[2];							
	}

	if (rayVector[1] != 0)
	{
		alphaIntersectionUp[1] = (firstIntersectionIndexUp[1] * (ctPixelSpacing[1]) - (SourceWorld[1])) / rayVector[1];
		alphaIntersectionDown[1] = (firstIntersectionIndexDown[1] * (ctPixelSpacing[1]) - (SourceWorld[1])) / rayVector[1];
		alpha[1] = alphaIntersectionDown[1];
		if (alphaIntersectionUp[1] > alpha[1])
			alpha[1] = alphaIntersectionUp[1];					
	}

	if (rayVector[0] != 0)
	{
		alphaIntersectionUp[0] = (firstIntersectionIndexUp[0] * (ctPixelSpacing[0]) - (SourceWorld[0])) / rayVector[0];
		alphaIntersectionDown[0] = (firstIntersectionIndexDown[0] * (ctPixelSpacing[0]) - (SourceWorld[0])) / rayVector[0];
		alpha[2] = alphaIntersectionDown[0];
		if (alphaIntersectionUp[0] > alpha[2])
			alpha[2] = alphaIntersectionUp[0];					
	}

	float alphaU[3] = { 999,999,999 };
	//Calculate incremental values (alphaUx, alphaUx, alphaUz) when the ray intercepts the planes
	if (rayVector[2] != 0)
		alphaU[0] = (ctPixelSpacing[2]) / fabs(rayVector[2]);	

	if (rayVector[1] != 0)
		alphaU[1] = (ctPixelSpacing[1]) / fabs(rayVector[1]);	

	if (rayVector[0] != 0)
		alphaU[2] = (ctPixelSpacing[0]) / fabs(rayVector[0]);
	

	float U[3] = { -1,-1,-1 };
	// Calculate voxel index incremental values along the ray path
	if ((SourceWorld[2]) < drrPixelWorld[2])
		U[0] = 1;	

	if ((SourceWorld[1]) < drrPixelWorld[1])
		U[1] = 1;

	if ((SourceWorld[0]) < drrPixelWorld[0])
		U[2] = 1;	


	//Initialize the weighted sum to zero
	float d12 = 0.0, alphaCmin, alphaCminPrev;

	//Initialize the current ray position (alphaCmin)
	if (alpha[0] < alpha[1]) //x < y
	{ 
		alphaCmin = alpha[2];
		if (alpha[0] < alphaCmin)  //x < y, x < z
			alphaCmin = alpha[0];
	}
	else //y < x
	{ 
		alphaCmin = alpha[2];
		if (alpha[1] < alphaCmin)  //y < x, y < z
			alphaCmin = alpha[1];
	}

	// Initialize the current voxel index.
	float cIndexNumber[3] = { firstIntersectionIndexDown[0] , firstIntersectionIndexDown[1] , firstIntersectionIndexDown[2] };

	//The while loop represents when the ray is inside the volume
	while (alphaCmin < alphaMax)
	{
		// Store the current ray position 
		alphaCminPrev = alphaCmin;
	
		if ((alpha[0] <= alpha[1]) && (alpha[0] <= alpha[2])) //Ray front intercepts with x-plane. Update alphaX
		{
			alphaCmin = alpha[0];
			cIndexNumber[2] = cIndexNumber[2] + U[0];
			alpha[0] = alpha[0] + alphaU[0];
		}
		else if ((alpha[1] <= alpha[0]) && (alpha[1] <= alpha[2])) //Ray front intercepts with y-plane. Update alphaY
		{ 
			alphaCmin = alpha[1];
			cIndexNumber[1] = cIndexNumber[1] + U[1];
			alpha[1] = alpha[1] + alphaU[1];
		}
		else                                                                //Ray front intercepts with z-plane. Update alphaZ
		{
			alphaCmin = alpha[2];
			cIndexNumber[0] = cIndexNumber[0] + U[2];
			alpha[2] = alpha[2] + alphaU[2];
		}
	
	
		if ((cIndexNumber[0] >= 0) && (cIndexNumber[0] < (d_sizeCT[0])) &&
			(cIndexNumber[1] >= 0) && (cIndexNumber[1] < (d_sizeCT[1])) &&
			(cIndexNumber[2] >= 0) && (cIndexNumber[2] < (d_sizeCT[2])))
		{
			//If it is a valid index, get the voxel intensity
		
			int cIndexCoordinate[3] = { static_cast<int> (cIndexNumber[2]) ,static_cast<int> (cIndexNumber[1]) ,static_cast<int> (cIndexNumber[0]) };

			//Get current position from flat object
			long int currentPos3D  = cIndexCoordinate[0] + (cIndexCoordinate[1] *(d_sizeCT[2])) + (cIndexCoordinate[2] * (d_sizeCT[2])*(d_sizeCT[1]));
	
			//Retrieve intensity value from flat object
			float value = tex1Dfetch<float>(tex_object3D,currentPos3D);
	
			//Ignore voxels whose intensities are below the desired threshold
			if (value > 0)
				d12 += value * (alphaCmin - alphaCminPrev) ;//weighted sum				
		}
	} //end of the while-loop

	float pixval = d12;
	if (pixval < 0)
		pixval = 0;	

	if (pixval >255)
		pixval = 255;

	//Assign the calculated value for the pixel to its corresponding position in the output array
	object2D[idx] = pixval; 

}

void calculateDRRwithCUDA(Image3D cpp_object3D, Image2D cpp_object2D, CUDAParamerters CUDA_Parameters, DRRParameters DRR_Parameters)
{
		
	cudaMemcpyToSymbol(d_DRR_Parameters, DRR_Parameters.stepInX, 12 * sizeof(float), 0, cudaMemcpyHostToDevice);

	//Block 6
	int num_Threads = CUDA_Parameters.numThreads;
	int num_Blocks = CUDA_Parameters.numBlocks;
	
	//------------------------------------------------------------
	//Launching the threads
	drrCUDA <<< num_Blocks, num_Threads >>> (d_object2D, tex_object3D, tex_mask2D);
	//------------------------------------------------------------

	//Copying the result from the calculations from device to host
	long int vectorSize = cpp_object2D.size[0] * cpp_object2D.size[1];
	float *h_object2D = cpp_object2D.image;
	cudaMemcpy(h_object2D, d_object2D, vectorSize * sizeof(float), cudaMemcpyDeviceToHost);

	return;
}


void HandleCudaKernelError(const cudaError_t CudaError, const char* pName /*= ""*/)
{
	if (CudaError == cudaSuccess)
		return;

	std::cerr << "The '" << pName << " kernel caused the following CUDA runtime error: " << cudaGetErrorString(CudaError) << std::endl;
}

	.file	"tmpxft_0037f360_00000000-6_CUDAdrr.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4262:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4262:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z20loadDICOMInGPUMemoryPfPiS_
	.type	_Z20loadDICOMInGPUMemoryPfPiS_, @function
_Z20loadDICOMInGPUMemoryPfPiS_:
.LFB4252:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	leaq	stream1(%rip), %rdi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$152, %rsp
	.cfi_def_cfa_offset 192
	movl	(%rsi), %ebx
	imull	4(%rsi), %ebx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	imull	8(%rsi), %ebx
	movl	$1, %esi
	call	cudaStreamCreateWithFlags@PLT
	leaq	d_object3D(%rip), %rdi
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r12, %rsi
	movq	stream1(%rip), %r8
	movq	d_object3D(%rip), %rdi
	call	cudaMemcpyAsync@PLT
	xorl	%ecx, %ecx
	movq	%rbp, %rsi
	movl	$1, %r8d
	movl	$12, %edx
	leaq	_ZL14ctPixelSpacing(%rip), %rdi
	movq	%rsp, %rbp
	call	cudaMemcpyToSymbol@PLT
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%r13, %rsi
	movl	$12, %edx
	leaq	_ZL8d_sizeCT(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	leaq	4(%rsp), %rdx
	xorl	%eax, %eax
	movl	$15, %ecx
	movq	%rdx, %rdi
	movq	d_object3D(%rip), %rdx
	movl	$2, (%rsp)
	rep stosl
	movq	%rbx, 40(%rsp)
	leaq	64(%rsp), %rbx
	movl	$18, %ecx
	movq	%rbx, %rdi
	movq	%rdx, 8(%rsp)
	rep stosl
	movq	tex_object3D(%rip), %rdi
	movl	$2, 32(%rsp)
	movl	$32, 16(%rsp)
	call	cudaDestroyTextureObject@PLT
	xorl	%ecx, %ecx
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	leaq	tex_object3D(%rip), %rdi
	call	cudaCreateTextureObject@PLT
	movq	stream1(%rip), %rdi
	call	cudaStreamDestroy@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L3
	call	__stack_chk_fail@PLT
.L3:
	addq	$152, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4252:
	.size	_Z20loadDICOMInGPUMemoryPfPiS_, .-_Z20loadDICOMInGPUMemoryPfPiS_
	.globl	_Z25updateMaskFlagInGPUMemoryb
	.type	_Z25updateMaskFlagInGPUMemoryb, @function
_Z25updateMaskFlagInGPUMemoryb:
.LFB4253:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movl	$1, %edx
	movb	%dil, 12(%rsp)
	leaq	12(%rsp), %rsi
	leaq	_ZL9d_useMask(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4253:
	.size	_Z25updateMaskFlagInGPUMemoryb, .-_Z25updateMaskFlagInGPUMemoryb
	.globl	_Z19loadMaskInGPUMemoryPhiib
	.type	_Z19loadMaskInGPUMemoryPhiib, @function
_Z19loadMaskInGPUMemoryPhiib:
.LFB4254:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	leaq	stream1(%rip), %rdi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%esi, %ebx
	movl	$1, %esi
	imull	%edx, %ebx
	subq	$152, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	movslq	%ebx, %rbx
	movq	%rsp, %r13
	call	cudaStreamCreateWithFlags@PLT
	movq	%rbx, %rsi
	leaq	d_mask2D(%rip), %rdi
	call	cudaMalloc@PLT
	movq	%r12, %rsi
	movl	$1, %ecx
	movq	%rbx, %rdx
	movq	stream1(%rip), %r8
	movq	d_mask2D(%rip), %rdi
	leaq	64(%rsp), %r12
	call	cudaMemcpyAsync@PLT
	xorl	%eax, %eax
	leaq	4(%rsp), %rdx
	movq	%r12, %rdi
	movl	$18, %ecx
	movl	$2, (%rsp)
	rep stosl
	movq	%rdx, %rdi
	movl	$15, %ecx
	rep stosl
	movq	d_mask2D(%rip), %rax
	movq	%rbx, 40(%rsp)
	movq	tex_mask2D(%rip), %rdi
	movl	$1, 32(%rsp)
	movq	%rax, 8(%rsp)
	movl	$8, 16(%rsp)
	call	cudaDestroyTextureObject@PLT
	xorl	%ecx, %ecx
	movq	%r12, %rdx
	movq	%r13, %rsi
	leaq	tex_mask2D(%rip), %rdi
	call	cudaCreateTextureObject@PLT
	movzbl	%bpl, %edi
	call	_Z25updateMaskFlagInGPUMemoryb
	movq	stream1(%rip), %rdi
	call	cudaStreamDestroy@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$152, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4254:
	.size	_Z19loadMaskInGPUMemoryPhiib, .-_Z19loadMaskInGPUMemoryPhiib
	.globl	_Z29loadOuputVariablesInGPUMemoryii
	.type	_Z29loadOuputVariablesInGPUMemoryii, @function
_Z29loadOuputVariablesInGPUMemoryii:
.LFB4255:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movl	%edi, (%rsp)
	imull	%esi, %edi
	movl	%esi, 4(%rsp)
	movslq	%edi, %rsi
	leaq	d_object2D(%rip), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	xorl	%ecx, %ecx
	movq	%rsp, %rsi
	movl	$1, %r8d
	movl	$8, %edx
	leaq	_ZL12DRRImageSize(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4255:
	.size	_Z29loadOuputVariablesInGPUMemoryii, .-_Z29loadOuputVariablesInGPUMemoryii
	.globl	_Z22freeDICOMFromGPUMemoryv
	.type	_Z22freeDICOMFromGPUMemoryv, @function
_Z22freeDICOMFromGPUMemoryv:
.LFB4256:
	.cfi_startproc
	endbr64
	movq	d_object3D(%rip), %rdi
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE4256:
	.size	_Z22freeDICOMFromGPUMemoryv, .-_Z22freeDICOMFromGPUMemoryv
	.globl	_Z33freeAuxiliaryVariablesInGPUMemoryv
	.type	_Z33freeAuxiliaryVariablesInGPUMemoryv, @function
_Z33freeAuxiliaryVariablesInGPUMemoryv:
.LFB4257:
	.cfi_startproc
	endbr64
	movq	d_object2D(%rip), %rdi
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE4257:
	.size	_Z33freeAuxiliaryVariablesInGPUMemoryv, .-_Z33freeAuxiliaryVariablesInGPUMemoryv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"The '"
.LC1:
	.string	" kernel caused the following CUDA runtime error: "
	.text
	.globl	_Z21HandleCudaKernelError9cudaErrorPKc
	.type	_Z21HandleCudaKernelError9cudaErrorPKc, @function
_Z21HandleCudaKernelError9cudaErrorPKc:
.LFB4259:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L16
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	leaq	.LC0(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	popq	%rdx
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_restore 3
	.cfi_def_cfa_offset 16
	movq	%rax, %rdi
	popq	%rbp
	.cfi_restore 6
	.cfi_def_cfa_offset 8
	jmp	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L16:
	ret
	.cfi_endproc
.LFE4259:
	.size	_Z21HandleCudaKernelError9cudaErrorPKc, .-_Z21HandleCudaKernelError9cudaErrorPKc
	.globl	_Z28__device_stub__Z7drrCUDAPfyyPfyy
	.type	_Z28__device_stub__Z7drrCUDAPfyyPfyy, @function
_Z28__device_stub__Z7drrCUDAPfyyPfyy:
.LFB4284:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7drrCUDAPfyy(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L21:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4284:
	.size	_Z28__device_stub__Z7drrCUDAPfyyPfyy, .-_Z28__device_stub__Z7drrCUDAPfyyPfyy
	.globl	_Z7drrCUDAPfyy
	.type	_Z7drrCUDAPfyy, @function
_Z7drrCUDAPfyy:
.LFB4285:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7drrCUDAPfyyPfyy
	.cfi_endproc
.LFE4285:
	.size	_Z7drrCUDAPfyy, .-_Z7drrCUDAPfyy
	.globl	_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters
	.type	_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters, @function
_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters:
.LFB4258:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	leaq	_ZL16d_DRR_Parameters(%rip), %rdi
	movq	%rdx, %rbp
	movl	$48, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rsi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	leaq	112(%rsp), %rsi
	call	cudaMemcpyToSymbol@PLT
	movq	%rbp, %rdx
	movl	%ebp, 20(%rsp)
	xorl	%r9d, %r9d
	sarq	$32, %rdx
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movl	28(%rsp), %ecx
	movl	%edx, 8(%rsp)
	movq	20(%rsp), %rdx
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	tex_mask2D(%rip), %rdx
	movq	tex_object3D(%rip), %rsi
	movq	d_object2D(%rip), %rdi
	call	_Z28__device_stub__Z7drrCUDAPfyyPfyy
.L27:
	movq	%rbx, %rax
	movq	d_object2D(%rip), %rsi
	movq	%r12, %rdi
	movl	$2, %ecx
	sarq	$32, %rax
	imull	%eax, %ebx
	movslq	%ebx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4258:
	.size	_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters, .-_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters
	.section	.rodata.str1.1
.LC2:
	.string	"_Z7drrCUDAPfyy"
.LC3:
	.string	"d_sizeCT"
.LC4:
	.string	"ctPixelSpacing"
.LC5:
	.string	"DRRImageSize"
.LC6:
	.string	"d_DRR_Parameters"
.LC7:
	.string	"d_useMask"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4287:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7drrCUDAPfyy(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$12, %r9d
	leaq	_ZL8d_sizeCT(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$12, %r9d
	leaq	_ZL14ctPixelSpacing(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL12DRRImageSize(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$48, %r9d
	leaq	_ZL16d_DRR_Parameters(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZL9d_useMask(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4287:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	stream1
	.bss
	.align 8
	.type	stream1, @object
	.size	stream1, 8
stream1:
	.zero	8
	.globl	tex_mask2D
	.align 8
	.type	tex_mask2D, @object
	.size	tex_mask2D, 8
tex_mask2D:
	.zero	8
	.globl	tex_object3D
	.align 8
	.type	tex_object3D, @object
	.size	tex_object3D, 8
tex_object3D:
	.zero	8
	.local	_ZL9d_useMask
	.comm	_ZL9d_useMask,1,1
	.local	_ZL16d_DRR_Parameters
	.comm	_ZL16d_DRR_Parameters,48,32
	.local	_ZL12DRRImageSize
	.comm	_ZL12DRRImageSize,8,8
	.local	_ZL14ctPixelSpacing
	.comm	_ZL14ctPixelSpacing,12,8
	.local	_ZL8d_sizeCT
	.comm	_ZL8d_sizeCT,12,8
	.globl	d_mask2D
	.align 8
	.type	d_mask2D, @object
	.size	d_mask2D, 8
d_mask2D:
	.zero	8
	.globl	d_object2D
	.align 8
	.type	d_object2D, @object
	.size	d_object2D, 8
d_object2D:
	.zero	8
	.globl	d_object3D
	.align 8
	.type	d_object3D, @object
	.size	d_object3D, 8
d_object3D:
	.zero	8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "CUDAdrr.cuh"

#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <algorithm> 
#include <iostream>
#include <vector>

#define KERNEL                      __global__
#define HOST                        __host__
#define DEVICE                      __device__
#define HOST_AND_DEVICE             __host__ __device__
#define DEVICE_CONST                __device__ __constant__

// This variable contains the DICOM set
float* d_object3D;

// This variable contains the 2D output from CUDA
float *d_object2D;

// This variable contains the mask output 
unsigned *d_mask2D;

// Constants depending on the DICOM
DEVICE_CONST int d_sizeCT[3];
DEVICE_CONST  float ctPixelSpacing[3];

// Constant depending on image output
DEVICE_CONST int DRRImageSize[2];

// Constants dependion on the specific DRR
DEVICE_CONST  float d_DRR_Parameters[12];

DEVICE_CONST  bool d_useMask;

// This variable contains the DICOM loaded as a Texture ( read-only, fast-cached memory)
hipTextureObject_t tex_object3D = 0;

// This variable contains the output Mask loaded as a Texture ( read-only, fast-cached memory)
hipTextureObject_t tex_mask2D = 0;

hipStream_t stream1;

void loadDICOMInGPUMemory(float *cpp_object3D, int *sizeCT, float *pixelSpacing)
{
	long int object3Dsize = sizeCT[0] * sizeCT[1] * sizeCT[2];
	hipStreamCreateWithFlags(&stream1, hipStreamNonBlocking);


	hipMalloc((void**)&d_object3D, object3Dsize * sizeof(float));
	hipMemcpyAsync(d_object3D, cpp_object3D, object3Dsize * sizeof(float), hipMemcpyHostToDevice, stream1);

	hipMemcpyToSymbol(HIP_SYMBOL(ctPixelSpacing), pixelSpacing, 3 * sizeof(float), 0, hipMemcpyHostToDevice);
	hipMemcpyToSymbol(HIP_SYMBOL(d_sizeCT), sizeCT, 3 * sizeof(int), 0, hipMemcpyHostToDevice);
	

	// create texture object
	hipResourceDesc resDesc;
	memset(&resDesc, 0, sizeof(resDesc));
	resDesc.resType = hipResourceTypeLinear;
	resDesc.res.linear.devPtr = d_object3D;
	resDesc.res.linear.desc.f = hipChannelFormatKindFloat;
	resDesc.res.linear.desc.x = 32; // bits per channel
	resDesc.res.linear.sizeInBytes = object3Dsize * sizeof(float);

	hipTextureDesc texDesc;
	memset(&texDesc, 0, sizeof(texDesc));
	texDesc.readMode = hipReadModeElementType;

	// create CUDA texture object
	hipDestroyTextureObject(tex_object3D);
	hipCreateTextureObject(&tex_object3D, &resDesc, &texDesc, NULL);

	hipStreamDestroy(stream1);

}


void updateMaskFlagInGPUMemory(bool useMask)
{	
	hipMemcpyToSymbol(HIP_SYMBOL(d_useMask), &useMask, 1 * sizeof(bool), 0, hipMemcpyHostToDevice);
}

void loadMaskInGPUMemory(unsigned char* mask_2D, int dimX, int dimZ, bool useMask)
{
	long int mask2DSize = dimX * dimZ;
	hipStreamCreateWithFlags(&stream1, hipStreamNonBlocking);		

	hipMalloc((void**)&d_mask2D, mask2DSize * sizeof(unsigned char));
	hipMemcpyAsync(d_mask2D, mask_2D, mask2DSize * sizeof(unsigned char), hipMemcpyHostToDevice, stream1);

	hipTextureDesc texDesc;
	memset(&texDesc, 0, sizeof(texDesc));
	texDesc.readMode = hipReadModeElementType;

	// create texture object
	hipResourceDesc resDesc;
	memset(&resDesc, 0, sizeof(resDesc));
	resDesc.res.linear.devPtr = d_mask2D;
	resDesc.resType = hipResourceTypeLinear;	
	resDesc.res.linear.desc.f = hipChannelFormatKindUnsigned;
	resDesc.res.linear.desc.x = 8; // bits per channel
	resDesc.res.linear.sizeInBytes = mask2DSize * sizeof(unsigned char);	

	// create CUDA texture object
	hipDestroyTextureObject(tex_mask2D);
	hipCreateTextureObject(&tex_mask2D, &resDesc, &texDesc, NULL);

	updateMaskFlagInGPUMemory(useMask);

	hipStreamDestroy(stream1);
}

void loadOuputVariablesInGPUMemory(int dimX, int dimZ)
{
	long int vectorSize = dimX* dimZ;
	int OutputImageSize[2] = { dimX, dimZ };

	hipMalloc((void**)&d_object2D, vectorSize * sizeof(float));

	hipMemcpyToSymbol(HIP_SYMBOL(DRRImageSize), OutputImageSize, 2 * sizeof(int), 0, hipMemcpyHostToDevice);
}


void freeDICOMFromGPUMemory()
{
	hipFree(d_object3D);
}

void freeAuxiliaryVariablesInGPUMemory()
{
	hipFree(d_object2D);
}

							


__global__ void drrCUDA(float* object2D, hipTextureObject_t tex_object3D, hipTextureObject_t tex_mask2D)
{

	float stepInX[3] = { d_DRR_Parameters[0],d_DRR_Parameters[1],d_DRR_Parameters[2] };
	float stepInY[3] = { d_DRR_Parameters[3],d_DRR_Parameters[4],d_DRR_Parameters[5] };
	float corner00[3] = { d_DRR_Parameters[6],d_DRR_Parameters[7],d_DRR_Parameters[8] };
	float SourceWorld[3] = { d_DRR_Parameters[9],d_DRR_Parameters[10],d_DRR_Parameters[11] };
	 
	int total_dx = DRRImageSize[0];
	int total_dz = DRRImageSize[1];
	
	//Every thread calculates its own id number
	long int idx = (blockIdx.x*blockDim.x) + threadIdx.x;	

	// This checks if the thread number is bigger than the amount of pixels
	if (idx >= total_dx * total_dz)
		return;

	// Converting number of pixels to rows and columns
	int dz = idx / total_dx;
	int dx = idx - dz*total_dx;


	if (d_useMask)
	{
		//unsigned char maskValue = 0;
		unsigned char maskValue = tex1Dfetch<unsigned char>(tex_mask2D, idx);
		if (maskValue == 0)
		{
			object2D[idx] = 0;
			return;
		}			
	}

	//Calculate the spatial position of the pixel
	//drrPixelWorld_0[idx] = *corner00_0 + ((*stepInX_0)*(threadIdx.x)) + ((*stepInY_0)*(blockIdx.x));
	//drrPixelWorld_1[idx] = *corner00_1 + ((*stepInX_1)*(threadIdx.x)) + ((*stepInY_1)*(blockIdx.x));
	//drrPixelWorld_2[idx] = *corner00_2 + ((*stepInX_2)*(threadIdx.x)) + ((*stepInY_2)*(blockIdx.x));
	float drrPixelWorld[3] = { 0 };
	drrPixelWorld[0] = corner00[0] + ((stepInX[0])*dx) + ((stepInY[0])*dz);
	drrPixelWorld[1] = corner00[1] + ((stepInX[1])*dx) + ((stepInY[1])*dz);
	drrPixelWorld[2] = corner00[2] + ((stepInX[2])*dx) + ((stepInY[2])*dz);

	//Calculate the ray vector
	float rayVector[3] = { 0 };
	rayVector[0] = drrPixelWorld[0] - SourceWorld[0];
	rayVector[1] = drrPixelWorld[1] - SourceWorld[1];
	rayVector[2] = drrPixelWorld[2] - SourceWorld[2];

	float alpha1[3];
	float alphaN[3];
	float auxalphaMin[3] = {-2, -2, -2};
	float auxalphaMax[3] = {2 , 2 , 2};


	//Calculate alphaMin and alphaMax 
	if (rayVector[2] != 0)
	{
		alpha1[0] = (0.0 - (SourceWorld[2])) / rayVector[2];
		alphaN[0] = ((d_sizeCT[2]) * (ctPixelSpacing[2]) - (SourceWorld[2])) / rayVector[2];
		auxalphaMin[0] = alphaN[0];
		auxalphaMax[0] = alpha1[0];

		if (alpha1[0] < alphaN[0]) 
		{
			auxalphaMin[0] = alpha1[0];
			auxalphaMax[0] = alphaN[0];
		}
	}

	if (rayVector[1] != 0)
	{
		alpha1[1] = (0.0 - (SourceWorld[1])) / rayVector[1];
		alphaN[1] = ((d_sizeCT[1]) * (ctPixelSpacing[1]) - (SourceWorld[1])) / rayVector[1];
		auxalphaMin[1] = alphaN[1];
		auxalphaMax[1] = alpha1[1];

		if (alpha1[1] < alphaN[1]) 
		{
			auxalphaMin[1] = alpha1[1];
			auxalphaMax[1] = alphaN[1];
		}
	}


	if (rayVector[0] != 0)
	{
		alpha1[2] = (0.0 - (SourceWorld[0])) / rayVector[0];
		alphaN[2] = ((d_sizeCT[0]) * (ctPixelSpacing[0]) - (SourceWorld[0])) / rayVector[0];
		auxalphaMin[2] = alphaN[2];
		auxalphaMax[2] = alpha1[2];

		if (alpha1[2] < alphaN[2]) 
		{
			auxalphaMin[2] = alpha1[2];
			auxalphaMax[2] = alphaN[2];
		}
	}

	
	float alphaMin;

	if (auxalphaMin[0] > auxalphaMin[1]) //x > y
	{ 
		alphaMin = auxalphaMin[2];
		if (auxalphaMin[0] > alphaMin) { //x > y, x > z
			alphaMin = auxalphaMin[0];
		}
	}
	else //y > x
	{ 
		alphaMin = auxalphaMin[2];
		if (auxalphaMin[1] > alphaMin)  //y > x, y > z
			alphaMin = auxalphaMin[1];
	}

	float alphaMax;

	if (auxalphaMax[0] < auxalphaMax[1])  // x < y
	{
		alphaMax = auxalphaMax[2];
		if (auxalphaMax[0] < alphaMax)  // x < y, x < z
			alphaMax = auxalphaMax[0];	
	}
	else // y < x
	{ 
		alphaMax = auxalphaMax[2];
		if (auxalphaMax[1] < alphaMax)  // y < x, y < z
			alphaMax = auxalphaMax[1];
	}

	float firstIntersection[3], firstIntersectionIndex[3], firstIntersectionIndexUp[3], firstIntersectionIndexDown[3];

	//Calculate the first intersection of the ray with the planes (alphaX, alphaY and alphaZ)
	firstIntersection[0] = (SourceWorld[0]) + (alphaMin * rayVector[0]);
	firstIntersection[1] = (SourceWorld[1]) + (alphaMin * rayVector[1]);
	firstIntersection[2] = (SourceWorld[2]) + (alphaMin * rayVector[2]);
	
	firstIntersectionIndex[0] = firstIntersection[0] / (ctPixelSpacing[0]);
	firstIntersectionIndex[1] = firstIntersection[1] / (ctPixelSpacing[1]);
	firstIntersectionIndex[2] = firstIntersection[2] / (ctPixelSpacing[2]);


	firstIntersectionIndexUp[0] = (int)ceil(firstIntersectionIndex[0]);
	firstIntersectionIndexUp[1] = (int)ceil(firstIntersectionIndex[1]);
	firstIntersectionIndexUp[2] = (int)ceil(firstIntersectionIndex[2]);

	firstIntersectionIndexDown[0] = (int)floor(firstIntersectionIndex[0]);
	firstIntersectionIndexDown[1] = (int)floor(firstIntersectionIndex[1]);
	firstIntersectionIndexDown[2] = (int)floor(firstIntersectionIndex[2]);

	float alpha[3] = {2,2,2}, alphaIntersectionUp[3], alphaIntersectionDown[3];

	if (rayVector[2] != 0)
	{
		alphaIntersectionUp[2] = (firstIntersectionIndexUp[2] * (ctPixelSpacing[2]) - (SourceWorld[2])) / rayVector[2];
		alphaIntersectionDown[2] = (firstIntersectionIndexDown[2] * (ctPixelSpacing[2]) - (SourceWorld[2])) / rayVector[2];
		alpha[0] = alphaIntersectionDown[2];
		if (alphaIntersectionUp[2] > alpha[0])
			alpha[0] = alphaIntersectionUp[2];							
	}

	if (rayVector[1] != 0)
	{
		alphaIntersectionUp[1] = (firstIntersectionIndexUp[1] * (ctPixelSpacing[1]) - (SourceWorld[1])) / rayVector[1];
		alphaIntersectionDown[1] = (firstIntersectionIndexDown[1] * (ctPixelSpacing[1]) - (SourceWorld[1])) / rayVector[1];
		alpha[1] = alphaIntersectionDown[1];
		if (alphaIntersectionUp[1] > alpha[1])
			alpha[1] = alphaIntersectionUp[1];					
	}

	if (rayVector[0] != 0)
	{
		alphaIntersectionUp[0] = (firstIntersectionIndexUp[0] * (ctPixelSpacing[0]) - (SourceWorld[0])) / rayVector[0];
		alphaIntersectionDown[0] = (firstIntersectionIndexDown[0] * (ctPixelSpacing[0]) - (SourceWorld[0])) / rayVector[0];
		alpha[2] = alphaIntersectionDown[0];
		if (alphaIntersectionUp[0] > alpha[2])
			alpha[2] = alphaIntersectionUp[0];					
	}

	float alphaU[3] = { 999,999,999 };
	//Calculate incremental values (alphaUx, alphaUx, alphaUz) when the ray intercepts the planes
	if (rayVector[2] != 0)
		alphaU[0] = (ctPixelSpacing[2]) / fabs(rayVector[2]);	

	if (rayVector[1] != 0)
		alphaU[1] = (ctPixelSpacing[1]) / fabs(rayVector[1]);	

	if (rayVector[0] != 0)
		alphaU[2] = (ctPixelSpacing[0]) / fabs(rayVector[0]);
	

	float U[3] = { -1,-1,-1 };
	// Calculate voxel index incremental values along the ray path
	if ((SourceWorld[2]) < drrPixelWorld[2])
		U[0] = 1;	

	if ((SourceWorld[1]) < drrPixelWorld[1])
		U[1] = 1;

	if ((SourceWorld[0]) < drrPixelWorld[0])
		U[2] = 1;	


	//Initialize the weighted sum to zero
	float d12 = 0.0, alphaCmin, alphaCminPrev;

	//Initialize the current ray position (alphaCmin)
	if (alpha[0] < alpha[1]) //x < y
	{ 
		alphaCmin = alpha[2];
		if (alpha[0] < alphaCmin)  //x < y, x < z
			alphaCmin = alpha[0];
	}
	else //y < x
	{ 
		alphaCmin = alpha[2];
		if (alpha[1] < alphaCmin)  //y < x, y < z
			alphaCmin = alpha[1];
	}

	// Initialize the current voxel index.
	float cIndexNumber[3] = { firstIntersectionIndexDown[0] , firstIntersectionIndexDown[1] , firstIntersectionIndexDown[2] };

	//The while loop represents when the ray is inside the volume
	while (alphaCmin < alphaMax)
	{
		// Store the current ray position 
		alphaCminPrev = alphaCmin;
	
		if ((alpha[0] <= alpha[1]) && (alpha[0] <= alpha[2])) //Ray front intercepts with x-plane. Update alphaX
		{
			alphaCmin = alpha[0];
			cIndexNumber[2] = cIndexNumber[2] + U[0];
			alpha[0] = alpha[0] + alphaU[0];
		}
		else if ((alpha[1] <= alpha[0]) && (alpha[1] <= alpha[2])) //Ray front intercepts with y-plane. Update alphaY
		{ 
			alphaCmin = alpha[1];
			cIndexNumber[1] = cIndexNumber[1] + U[1];
			alpha[1] = alpha[1] + alphaU[1];
		}
		else                                                                //Ray front intercepts with z-plane. Update alphaZ
		{
			alphaCmin = alpha[2];
			cIndexNumber[0] = cIndexNumber[0] + U[2];
			alpha[2] = alpha[2] + alphaU[2];
		}
	
	
		if ((cIndexNumber[0] >= 0) && (cIndexNumber[0] < (d_sizeCT[0])) &&
			(cIndexNumber[1] >= 0) && (cIndexNumber[1] < (d_sizeCT[1])) &&
			(cIndexNumber[2] >= 0) && (cIndexNumber[2] < (d_sizeCT[2])))
		{
			//If it is a valid index, get the voxel intensity
		
			int cIndexCoordinate[3] = { static_cast<int> (cIndexNumber[2]) ,static_cast<int> (cIndexNumber[1]) ,static_cast<int> (cIndexNumber[0]) };

			//Get current position from flat object
			long int currentPos3D  = cIndexCoordinate[0] + (cIndexCoordinate[1] *(d_sizeCT[2])) + (cIndexCoordinate[2] * (d_sizeCT[2])*(d_sizeCT[1]));
	
			//Retrieve intensity value from flat object
			float value = tex1Dfetch<float>(tex_object3D,currentPos3D);
	
			//Ignore voxels whose intensities are below the desired threshold
			if (value > 0)
				d12 += value * (alphaCmin - alphaCminPrev) ;//weighted sum				
		}
	} //end of the while-loop

	float pixval = d12;
	if (pixval < 0)
		pixval = 0;	

	if (pixval >255)
		pixval = 255;

	//Assign the calculated value for the pixel to its corresponding position in the output array
	object2D[idx] = pixval; 

}

void calculateDRRwithCUDA(Image3D cpp_object3D, Image2D cpp_object2D, CUDAParamerters CUDA_Parameters, DRRParameters DRR_Parameters)
{
		
	hipMemcpyToSymbol(HIP_SYMBOL(d_DRR_Parameters), DRR_Parameters.stepInX, 12 * sizeof(float), 0, hipMemcpyHostToDevice);

	//Block 6
	int num_Threads = CUDA_Parameters.numThreads;
	int num_Blocks = CUDA_Parameters.numBlocks;
	
	//------------------------------------------------------------
	//Launching the threads
	drrCUDA <<< num_Blocks, num_Threads >>> (d_object2D, tex_object3D, tex_mask2D);
	//------------------------------------------------------------

	//Copying the result from the calculations from device to host
	long int vectorSize = cpp_object2D.size[0] * cpp_object2D.size[1];
	float *h_object2D = cpp_object2D.image;
	hipMemcpy(h_object2D, d_object2D, vectorSize * sizeof(float), hipMemcpyDeviceToHost);

	return;
}


void HandleCudaKernelError(const hipError_t CudaError, const char* pName /*= ""*/)
{
	if (CudaError == hipSuccess)
		return;

	std::cerr << "The '" << pName << " kernel caused the following CUDA runtime error: " << hipGetErrorString(CudaError) << std::endl;
}

	.text
	.file	"CUDAdrr.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z20loadDICOMInGPUMemoryPfPiS_  # -- Begin function _Z20loadDICOMInGPUMemoryPfPiS_
	.type	_Z20loadDICOMInGPUMemoryPfPiS_,@function
_Z20loadDICOMInGPUMemoryPfPiS_:         # @_Z20loadDICOMInGPUMemoryPfPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$136, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %r15
	movq	%rsi, %r14
	movq	%rdi, %r12
	movslq	(%rsi), %rax
	movslq	4(%rsi), %rcx
	imulq	%rax, %rcx
	movslq	8(%rsi), %rbx
	imulq	%rcx, %rbx
	movl	$stream1, %edi
	movl	$1, %esi
	callq	hipStreamCreateWithFlags
	shlq	$2, %rbx
	movl	$d_object3D, %edi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	d_object3D(%rip), %rdi
	movq	stream1(%rip), %r8
	movq	%r12, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movl	$ctPixelSpacing, %edi
	movl	$12, %edx
	movq	%r15, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$d_sizeCT, %edi
	movl	$12, %edx
	movq	%r14, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	xorps	%xmm0, %xmm0
	leaq	64(%rsp), %r14
	movaps	%xmm0, (%r14)
	movaps	%xmm0, 32(%r14)
	movaps	%xmm0, 16(%r14)
	movaps	%xmm0, 48(%r14)
	movl	$2, %eax
	movl	%eax, (%r14)
	movq	d_object3D(%rip), %rcx
	movq	%rcx, 8(%r14)
	movl	%eax, 32(%r14)
	movl	$32, 16(%r14)
	movq	%rbx, 40(%r14)
	movq	%rsp, %rbx
	movaps	%xmm0, 48(%rbx)
	movaps	%xmm0, 32(%rbx)
	movaps	%xmm0, 16(%rbx)
	movaps	%xmm0, (%rbx)
	movq	tex_object3D(%rip), %rdi
	callq	hipDestroyTextureObject
	movl	$tex_object3D, %edi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	xorl	%ecx, %ecx
	callq	hipCreateTextureObject
	movq	stream1(%rip), %rdi
	callq	hipStreamDestroy
	addq	$136, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20loadDICOMInGPUMemoryPfPiS_, .Lfunc_end0-_Z20loadDICOMInGPUMemoryPfPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25updateMaskFlagInGPUMemoryb  # -- Begin function _Z25updateMaskFlagInGPUMemoryb
	.type	_Z25updateMaskFlagInGPUMemoryb,@function
_Z25updateMaskFlagInGPUMemoryb:         # @_Z25updateMaskFlagInGPUMemoryb
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	7(%rsp), %rsi
	movb	%dil, (%rsi)
	movl	$d_useMask, %edi
	movl	$1, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25updateMaskFlagInGPUMemoryb, .Lfunc_end1-_Z25updateMaskFlagInGPUMemoryb
	.cfi_endproc
                                        # -- End function
	.globl	_Z19loadMaskInGPUMemoryPhiib    # -- Begin function _Z19loadMaskInGPUMemoryPhiib
	.type	_Z19loadMaskInGPUMemoryPhiib,@function
_Z19loadMaskInGPUMemoryPhiib:           # @_Z19loadMaskInGPUMemoryPhiib
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$152, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %ebx
	movq	%rdi, %r15
	imull	%edx, %esi
	movslq	%esi, %r14
	movl	$stream1, %edi
	movl	$1, %esi
	callq	hipStreamCreateWithFlags
	movl	$d_mask2D, %edi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	d_mask2D(%rip), %rdi
	movq	stream1(%rip), %r8
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpyAsync
	xorps	%xmm0, %xmm0
	leaq	80(%rsp), %r15
	movaps	%xmm0, 48(%r15)
	movaps	%xmm0, 32(%r15)
	movaps	%xmm0, 16(%r15)
	movaps	%xmm0, (%r15)
	leaq	16(%rsp), %r12
	movaps	%xmm0, (%r12)
	movaps	%xmm0, 32(%r12)
	movaps	%xmm0, 16(%r12)
	movaps	%xmm0, 48(%r12)
	movq	d_mask2D(%rip), %rax
	movq	%rax, 8(%r12)
	movl	$2, (%r12)
	movl	$1, 32(%r12)
	movl	$8, 16(%r12)
	movq	%r14, 40(%r12)
	movq	tex_mask2D(%rip), %rdi
	callq	hipDestroyTextureObject
	movl	$tex_mask2D, %edi
	movq	%r12, %rsi
	movq	%r15, %rdx
	xorl	%ecx, %ecx
	callq	hipCreateTextureObject
	leaq	15(%rsp), %rsi
	movb	%bl, (%rsi)
	movl	$d_useMask, %edi
	movl	$1, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movq	stream1(%rip), %rdi
	callq	hipStreamDestroy
	addq	$152, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z19loadMaskInGPUMemoryPhiib, .Lfunc_end2-_Z19loadMaskInGPUMemoryPhiib
	.cfi_endproc
                                        # -- End function
	.globl	_Z29loadOuputVariablesInGPUMemoryii # -- Begin function _Z29loadOuputVariablesInGPUMemoryii
	.type	_Z29loadOuputVariablesInGPUMemoryii,@function
_Z29loadOuputVariablesInGPUMemoryii:    # @_Z29loadOuputVariablesInGPUMemoryii
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	8(%rsp), %rbx
	movl	%edi, (%rbx)
	movl	%esi, 4(%rbx)
	imull	%edi, %esi
	movslq	%esi, %rsi
	shlq	$2, %rsi
	movl	$d_object2D, %edi
	callq	hipMalloc
	movl	$DRRImageSize, %edi
	movl	$8, %edx
	movq	%rbx, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z29loadOuputVariablesInGPUMemoryii, .Lfunc_end3-_Z29loadOuputVariablesInGPUMemoryii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22freeDICOMFromGPUMemoryv     # -- Begin function _Z22freeDICOMFromGPUMemoryv
	.type	_Z22freeDICOMFromGPUMemoryv,@function
_Z22freeDICOMFromGPUMemoryv:            # @_Z22freeDICOMFromGPUMemoryv
	.cfi_startproc
# %bb.0:
	movq	d_object3D(%rip), %rdi
	jmp	hipFree                         # TAILCALL
.Lfunc_end4:
	.size	_Z22freeDICOMFromGPUMemoryv, .Lfunc_end4-_Z22freeDICOMFromGPUMemoryv
	.cfi_endproc
                                        # -- End function
	.globl	_Z33freeAuxiliaryVariablesInGPUMemoryv # -- Begin function _Z33freeAuxiliaryVariablesInGPUMemoryv
	.type	_Z33freeAuxiliaryVariablesInGPUMemoryv,@function
_Z33freeAuxiliaryVariablesInGPUMemoryv: # @_Z33freeAuxiliaryVariablesInGPUMemoryv
	.cfi_startproc
# %bb.0:
	movq	d_object2D(%rip), %rdi
	jmp	hipFree                         # TAILCALL
.Lfunc_end5:
	.size	_Z33freeAuxiliaryVariablesInGPUMemoryv, .Lfunc_end5-_Z33freeAuxiliaryVariablesInGPUMemoryv
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__drrCUDAPfP13__hip_textureS1_ # -- Begin function _Z22__device_stub__drrCUDAPfP13__hip_textureS1_
	.type	_Z22__device_stub__drrCUDAPfP13__hip_textureS1_,@function
_Z22__device_stub__drrCUDAPfP13__hip_textureS1_: # @_Z22__device_stub__drrCUDAPfP13__hip_textureS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7drrCUDAPfP13__hip_textureS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z22__device_stub__drrCUDAPfP13__hip_textureS1_, .Lfunc_end6-_Z22__device_stub__drrCUDAPfP13__hip_textureS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters # -- Begin function _Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters
	.type	_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters,@function
_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters: # @_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %r15
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movq	%rdx, %r12
	shrq	$32, %r12
	leaq	96(%rsp), %rsi
	movl	$d_DRR_Parameters, %edi
	movl	$48, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	btsq	$32, %r12
	movl	%r15d, %edx
	btsq	$32, %rdx
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_2
# %bb.1:
	movq	d_object2D(%rip), %rdi
	movq	tex_object3D(%rip), %rsi
	movq	tex_mask2D(%rip), %rdx
	callq	_Z22__device_stub__drrCUDAPfP13__hip_textureS1_
.LBB7_2:
	movq	%r14, %rax
	shrq	$32, %rax
	imull	%r14d, %eax
	movq	d_object2D(%rip), %rsi
	movslq	%eax, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters, .Lfunc_end7-_Z20calculateDRRwithCUDA7Image3D7Image2D15CUDAParamerters13DRRParameters
	.cfi_endproc
                                        # -- End function
	.globl	_Z21HandleCudaKernelError10hipError_tPKc # -- Begin function _Z21HandleCudaKernelError10hipError_tPKc
	.type	_Z21HandleCudaKernelError10hipError_tPKc,@function
_Z21HandleCudaKernelError10hipError_tPKc: # @_Z21HandleCudaKernelError10hipError_tPKc
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	je	.LBB8_8
# %bb.1:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	testq	%r14, %r14
	je	.LBB8_2
# %bb.3:
	movq	%r14, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%r14, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB8_4
.LBB8_8:
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	retq
.LBB8_2:
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB8_4:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$49, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB8_5
# %bb.6:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB8_7
.LBB8_5:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB8_7:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end8:
	.size	_Z21HandleCudaKernelError10hipError_tPKc, .Lfunc_end8-_Z21HandleCudaKernelError10hipError_tPKc
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7drrCUDAPfP13__hip_textureS1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$d_sizeCT, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ctPixelSpacing, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$DRRImageSize, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$d_DRR_Parameters, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$48, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$d_useMask, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$1, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_object3D,@object              # @d_object3D
	.bss
	.globl	d_object3D
	.p2align	3, 0x0
d_object3D:
	.quad	0
	.size	d_object3D, 8

	.type	d_object2D,@object              # @d_object2D
	.globl	d_object2D
	.p2align	3, 0x0
d_object2D:
	.quad	0
	.size	d_object2D, 8

	.type	d_mask2D,@object                # @d_mask2D
	.globl	d_mask2D
	.p2align	3, 0x0
d_mask2D:
	.quad	0
	.size	d_mask2D, 8

	.type	d_sizeCT,@object                # @d_sizeCT
	.local	d_sizeCT
	.comm	d_sizeCT,12,4
	.type	ctPixelSpacing,@object          # @ctPixelSpacing
	.local	ctPixelSpacing
	.comm	ctPixelSpacing,12,4
	.type	DRRImageSize,@object            # @DRRImageSize
	.local	DRRImageSize
	.comm	DRRImageSize,8,4
	.type	d_DRR_Parameters,@object        # @d_DRR_Parameters
	.local	d_DRR_Parameters
	.comm	d_DRR_Parameters,48,16
	.type	d_useMask,@object               # @d_useMask
	.local	d_useMask
	.comm	d_useMask,1,1
	.type	tex_object3D,@object            # @tex_object3D
	.globl	tex_object3D
	.p2align	3, 0x0
tex_object3D:
	.quad	0
	.size	tex_object3D, 8

	.type	tex_mask2D,@object              # @tex_mask2D
	.globl	tex_mask2D
	.p2align	3, 0x0
tex_mask2D:
	.quad	0
	.size	tex_mask2D, 8

	.type	stream1,@object                 # @stream1
	.globl	stream1
	.p2align	3, 0x0
stream1:
	.quad	0
	.size	stream1, 8

	.type	_Z7drrCUDAPfP13__hip_textureS1_,@object # @_Z7drrCUDAPfP13__hip_textureS1_
	.section	.rodata,"a",@progbits
	.globl	_Z7drrCUDAPfP13__hip_textureS1_
	.p2align	3, 0x0
_Z7drrCUDAPfP13__hip_textureS1_:
	.quad	_Z22__device_stub__drrCUDAPfP13__hip_textureS1_
	.size	_Z7drrCUDAPfP13__hip_textureS1_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"The '"
	.size	.L.str, 6

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" kernel caused the following CUDA runtime error: "
	.size	.L.str.1, 50

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7drrCUDAPfP13__hip_textureS1_"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"d_sizeCT"
	.size	.L__unnamed_2, 9

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"ctPixelSpacing"
	.size	.L__unnamed_3, 15

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"DRRImageSize"
	.size	.L__unnamed_4, 13

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"d_DRR_Parameters"
	.size	.L__unnamed_5, 17

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"d_useMask"
	.size	.L__unnamed_6, 10

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__drrCUDAPfP13__hip_textureS1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_object3D
	.addrsig_sym d_object2D
	.addrsig_sym d_mask2D
	.addrsig_sym d_sizeCT
	.addrsig_sym ctPixelSpacing
	.addrsig_sym DRRImageSize
	.addrsig_sym d_DRR_Parameters
	.addrsig_sym d_useMask
	.addrsig_sym tex_object3D
	.addrsig_sym tex_mask2D
	.addrsig_sym stream1
	.addrsig_sym _Z7drrCUDAPfP13__hip_textureS1_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7drrCUDAPfP13__hip_textureS1_ ; -- Begin function _Z7drrCUDAPfP13__hip_textureS1_
	.globl	_Z7drrCUDAPfP13__hip_textureS1_
	.p2align	8
	.type	_Z7drrCUDAPfP13__hip_textureS1_,@function
_Z7drrCUDAPfP13__hip_textureS1_:        ; @_Z7drrCUDAPfP13__hip_textureS1_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x24
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, DRRImageSize@rel32@lo+4
	s_addc_u32 s3, s3, DRRImageSize@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_mov_b32_e32 v2, 0
	s_mul_i32 s4, s3, s2
	s_mov_b32 s3, exec_lo
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_i64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB0_79
; %bb.1:
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_useMask@rel32@lo+4
	s_addc_u32 s5, s5, d_useMask@rel32@hi+12
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	global_load_u8 v0, v2, s[4:5]
	s_mov_b32 s4, 0
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e64 s3, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_3
; %bb.2:
	s_waitcnt lgkmcnt(0)
	s_load_b128 s[8:11], s[0:1], 0x0
	s_and_not1_b32 s0, s3, exec_lo
	s_waitcnt lgkmcnt(0)
	buffer_load_format_x v0, v1, s[8:11], 0 idxen
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0xff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_and_b32 s1, vcc_lo, exec_lo
	s_or_b32 s3, s0, s1
	s_branch .LBB0_4
.LBB0_3:
                                        ; implicit-def: $sgpr4
.LBB0_4:                                ; %Flow289
	v_mov_b32_e32 v0, s4
	s_and_saveexec_b32 s20, s3
	s_cbranch_execz .LBB0_78
; %bb.5:                                ; %.critedge
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s0, s2, 31
	v_ashrrev_i32_e32 v4, 31, v1
	s_add_i32 s1, s2, s0
	v_mov_b32_e32 v11, -2.0
	s_xor_b32 s1, s1, s0
	v_mov_b32_e32 v8, 2.0
	v_cvt_f32_u32_e32 v0, s1
	s_sub_i32 s3, 0, s1
	v_add_nc_u32_e32 v5, v1, v4
	v_mov_b32_e32 v9, -2.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v5, v5, v4
	v_xor_b32_e32 v4, s0, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v5, v0
	v_mul_lo_u32 v3, v0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v5, v3
	v_add_nc_u32_e32 v5, 1, v0
	v_subrev_nc_u32_e32 v6, s1, v3
	v_cmp_le_u32_e32 vcc_lo, s1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v0, v5 :: v_dual_cndmask_b32 v3, v3, v6
	v_add_nc_u32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s1, v3
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_DRR_Parameters@rel32@lo+4
	s_addc_u32 s1, s1, d_DRR_Parameters@rel32@hi+12
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	v_dual_cndmask_b32 v0, v0, v5 :: v_dual_mov_b32 v5, 2.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v4
	v_sub_nc_u32_e32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v0, s2
	v_cvt_f32_i32_e32 v0, v0
	v_sub_nc_u32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v7, v3
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v3, s6, v7, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, s9, v0
	v_subrev_f32_e32 v6, s19, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e64 s0, 0, v6
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_9
; %bb.6:
	v_cvt_f64_f32_e32 v[4:5], s19
	v_cvt_f64_f32_e32 v[9:10], v6
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_sizeCT@rel32@lo+12
	s_addc_u32 s3, s3, d_sizeCT@rel32@hi+20
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, ctPixelSpacing@rel32@lo+12
	s_addc_u32 s23, s23, ctPixelSpacing@rel32@hi+20
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s3, s[22:23], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], -v[4:5], 0
	v_div_scale_f64 v[12:13], null, v[9:10], v[9:10], v[4:5]
	v_div_scale_f64 v[18:19], vcc_lo, v[4:5], v[9:10], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17]
	v_div_fixup_f64 v[4:5], v[12:13], v[9:10], v[4:5]
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v9, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, s3, v9, -s19
	v_div_scale_f32 v10, null, v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v10, v12, 1.0
	v_fmac_f32_e32 v12, v13, v12
	v_cvt_f32_f64_e32 v5, v[4:5]
	v_div_scale_f32 v4, vcc_lo, v9, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v4, v12
	v_fma_f32 v14, -v10, v13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v14, v12
	v_fma_f32 v4, -v10, v13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v12, v13
	v_div_fixup_f32 v4, v4, v6, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v9, v4
	v_cmpx_gt_f32_e32 v4, v5
; %bb.7:
	v_mov_b32_e32 v9, v5
	v_mov_b32_e32 v5, v4
; %bb.8:                                ; %Flow288
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_9:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_fma_f32 v4, s5, v7, s11
	v_fmac_f32_e32 v4, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_f32_e32 v10, s18, v4
	v_cmp_neq_f32_e64 s1, 0, v10
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_13
; %bb.10:
	v_cvt_f64_f32_e32 v[11:12], s18
	v_cvt_f64_f32_e32 v[13:14], v10
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, d_sizeCT@rel32@lo+8
	s_addc_u32 s9, s9, d_sizeCT@rel32@hi+16
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, ctPixelSpacing@rel32@lo+8
	s_addc_u32 s23, s23, ctPixelSpacing@rel32@hi+16
	s_load_b32 s3, s[8:9], 0x0
	s_load_b32 s5, s[22:23], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v8, s3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], -v[11:12], 0
	v_div_scale_f64 v[15:16], null, v[13:14], v[13:14], v[11:12]
	v_div_scale_f64 v[21:22], vcc_lo, v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
	v_div_fixup_f64 v[11:12], v[15:16], v[13:14], v[11:12]
	v_fma_f32 v13, s5, v8, -s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v14, null, v10, v10, v13
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v16, v15
	v_cvt_f32_f64_e32 v8, v[11:12]
	v_div_scale_f32 v11, vcc_lo, v13, v10, v13
	v_mul_f32_e32 v12, v11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v14, v12, v11
	v_fmac_f32_e32 v12, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v14, v12, v11
	v_div_fmas_f32 v11, v11, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v12, v11, v10, v13
	v_mov_b32_e32 v11, v12
	v_cmpx_gt_f32_e32 v12, v8
; %bb.11:
	v_mov_b32_e32 v11, v8
	v_mov_b32_e32 v8, v12
; %bb.12:                               ; %Flow287
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_13:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s2
	v_fma_f32 v7, s4, v7, s10
	v_mov_b32_e32 v13, -2.0
	v_dual_fmac_f32 v7, s7, v0 :: v_dual_mov_b32 v0, 2.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_f32_e32 v12, s17, v7
	v_cmp_neq_f32_e64 s2, 0, v12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_17
; %bb.14:
	v_cvt_f64_f32_e32 v[13:14], s17
	v_cvt_f64_f32_e32 v[15:16], v12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_sizeCT@rel32@lo+4
	s_addc_u32 s5, s5, d_sizeCT@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, ctPixelSpacing@rel32@lo+4
	s_addc_u32 s7, s7, ctPixelSpacing@rel32@hi+12
	s_load_b32 s4, s[4:5], 0x0
	s_load_b32 s5, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v0, s4
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], -v[13:14], 0
	v_div_scale_f64 v[17:18], null, v[15:16], v[15:16], v[13:14]
	v_div_scale_f64 v[23:24], vcc_lo, v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[23:24], v[19:20]
	v_fma_f64 v[17:18], -v[17:18], v[21:22], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[21:22]
	v_div_fixup_f64 v[13:14], v[17:18], v[15:16], v[13:14]
	v_fma_f32 v15, s5, v0, -s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v16, null, v12, v12, v15
	v_rcp_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v16, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v17
	v_cvt_f32_f64_e32 v0, v[13:14]
	v_div_scale_f32 v13, vcc_lo, v15, v12, v15
	v_mul_f32_e32 v14, v13, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v16, v14, v13
	v_fmac_f32_e32 v14, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v16, v14, v13
	v_div_fmas_f32 v13, v13, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v14, v13, v12, v15
	v_mov_b32_e32 v13, v14
	v_cmpx_gt_f32_e32 v14, v0
; %bb.15:
	v_dual_mov_b32 v13, v0 :: v_dual_mov_b32 v0, v14
; %bb.16:                               ; %Flow286
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_17:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, exec_lo
	v_cmpx_ngt_f32_e32 v9, v11
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_21
; %bb.18:
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_f32_e32 v11, v13
; %bb.19:
	v_mov_b32_e32 v13, v11
; %bb.20:                               ; %Flow283
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr9
.LBB0_21:                               ; %Flow285
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_25
; %bb.22:
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_f32_e32 v9, v13
; %bb.23:
	v_mov_b32_e32 v13, v9
; %bb.24:                               ; %Flow284
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_25:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, exec_lo
	v_cmpx_nlt_f32_e32 v5, v8
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_29
; %bb.26:
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_f32_e32 v8, v0
; %bb.27:
	v_mov_b32_e32 v0, v8
; %bb.28:                               ; %Flow280
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr5
.LBB0_29:                               ; %Flow282
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_33
; %bb.30:
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_f32_e32 v5, v0
; %bb.31:
	v_mov_b32_e32 v0, v5
; %bb.32:                               ; %Flow281
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_33:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, ctPixelSpacing@rel32@lo+4
	s_addc_u32 s5, s5, ctPixelSpacing@rel32@hi+12
	v_fma_f32 v5, v6, v13, s19
	s_clause 0x1
	s_load_b32 s6, s[4:5], 0x8
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v8, null, s6, s6, v5
	v_div_scale_f32 v14, vcc_lo, v5, s6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v8, v9, 1.0
	v_fmac_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v14, v9
	v_fma_f32 v15, -v8, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v15, v9
	v_fma_f32 v8, -v8, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v8, v8, v9, v11
	v_mov_b32_e32 v9, 2.0
	v_div_fixup_f32 v11, v8, s6, v5
	v_mov_b32_e32 v8, 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v5, v11
	v_cvt_i32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_i32_e32 v5, v5
	s_and_saveexec_b32 s7, s0
	s_cbranch_execz .LBB0_37
; %bb.34:
	v_ceil_f32_e32 v8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, s6, v5, -s19
	v_cvt_i32_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v15, null, v6, v6, v14
	v_cvt_f32_i32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v15
	v_fma_f32 v8, s6, v8, -s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_div_scale_f32 v11, null, v6, v6, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v15, v17, 1.0
	v_div_scale_f32 v20, vcc_lo, v8, v6, v8
	v_rcp_f32_e32 v16, v11
	v_fmac_f32_e32 v17, v19, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v11, v16, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, v18, v16
	v_div_scale_f32 v18, s3, v14, v6, v14
	v_mul_f32_e32 v19, v20, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v18, v17
	v_fma_f32 v22, -v11, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, -v15, v21, v18
	v_fmac_f32_e32 v19, v22, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, v23, v17
	v_fma_f32 v11, -v11, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v15, v21, v18
	v_div_fmas_f32 v11, v11, v16, v19
	s_mov_b32 vcc_lo, s3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v15, v15, v17, v21
	v_div_fixup_f32 v11, v11, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v8, v15, v6, v14
	v_cmpx_gt_f32_e32 v11, v8
; %bb.35:
	v_mov_b32_e32 v8, v11
; %bb.36:                               ; %Flow279
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_37:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s7
	v_fma_f32 v11, v10, v13, s18
	v_div_scale_f32 v14, null, s5, s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	v_fmac_f32_e32 v15, v16, v15
	v_div_scale_f32 v16, vcc_lo, v11, s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v16, v15
	v_fma_f32 v18, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v15
	v_fma_f32 v14, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v14, v14, v15, v17
	v_div_fixup_f32 v14, v14, s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v11, v14
	v_cvt_i32_f32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_i32_e32 v11, v11
	s_and_saveexec_b32 s7, s1
	s_cbranch_execz .LBB0_41
; %bb.38:
	v_ceil_f32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, s5, v11, -s18
	v_cvt_i32_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v16, null, v10, v10, v15
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v18, v16
	v_fma_f32 v9, s5, v9, -s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_div_scale_f32 v14, null, v10, v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v16, v18, 1.0
	v_div_scale_f32 v21, vcc_lo, v9, v10, v9
	v_rcp_f32_e32 v17, v14
	v_fmac_f32_e32 v18, v20, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v14, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v19, v17
	v_div_scale_f32 v19, s3, v15, v10, v15
	v_mul_f32_e32 v20, v21, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, v19, v18
	v_fma_f32 v23, -v14, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v16, v22, v19
	v_fmac_f32_e32 v20, v23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, v24, v18
	v_fma_f32 v14, -v14, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, -v16, v22, v19
	v_div_fmas_f32 v14, v14, v17, v20
	s_mov_b32 vcc_lo, s3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v16, v16, v18, v22
	v_div_fixup_f32 v14, v14, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v9, v16, v10, v15
	v_cmpx_gt_f32_e32 v14, v9
; %bb.39:
	v_mov_b32_e32 v9, v14
; %bb.40:                               ; %Flow278
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_41:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s7
	v_fma_f32 v13, v12, v13, s17
	v_div_scale_f32 v14, null, s4, s4, v13
	v_div_scale_f32 v17, vcc_lo, v13, s4, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	v_fmac_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, v17, v15
	v_fma_f32 v18, -v14, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v18, v15
	v_fma_f32 v14, -v14, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v14, v14, v15, v16
	v_div_fixup_f32 v15, v14, s4, v13
	v_mov_b32_e32 v14, 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v13, v15
	v_cvt_i32_f32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_i32_e32 v13, v13
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_45
; %bb.42:
	v_ceil_f32_e32 v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, s4, v13, -s17
	v_cvt_i32_f32_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v17, null, v12, v12, v16
	v_cvt_f32_i32_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v17
	v_fma_f32 v14, s4, v14, -s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_div_scale_f32 v15, null, v12, v12, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v17, v19, 1.0
	v_div_scale_f32 v22, vcc_lo, v14, v12, v14
	v_rcp_f32_e32 v18, v15
	v_fmac_f32_e32 v19, v21, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v15, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v20, v18
	v_div_scale_f32 v20, s3, v16, v12, v16
	v_mul_f32_e32 v21, v22, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, v20, v19
	v_fma_f32 v24, -v15, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v17, v23, v20
	v_fmac_f32_e32 v21, v24, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, v25, v19
	v_fma_f32 v15, -v15, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, -v17, v23, v20
	v_div_fmas_f32 v15, v15, v18, v21
	s_mov_b32 vcc_lo, s3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v17, v17, v19, v23
	v_div_fixup_f32 v15, v15, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v14, v17, v12, v16
	v_cmpx_gt_f32_e32 v15, v14
; %bb.43:
	v_mov_b32_e32 v14, v15
; %bb.44:                               ; %Flow277
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_45:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	v_dual_mov_b32 v15, 0x4479c000 :: v_dual_mov_b32 v16, 0x4479c000
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_47
; %bb.46:
	v_and_b32_e32 v16, 0x7fffffff, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v17, null, v16, v16, s6
	v_div_scale_f32 v16, vcc_lo, s6, v16, s6
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v18
	v_mul_f32_e32 v19, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v17, v19, v16
	v_fmac_f32_e32 v19, v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v17, v19, v16
	v_div_fmas_f32 v16, v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v16, v16, |v6|, s6
.LBB0_47:
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_49
; %bb.48:
	v_and_b32_e32 v6, 0x7fffffff, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v15, null, v6, v6, s5
	v_rcp_f32_e32 v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v15, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v17
	v_div_scale_f32 v6, vcc_lo, s5, v6, s5
	v_mul_f32_e32 v18, v6, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v15, v18, v6
	v_fmac_f32_e32 v18, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v15, v18, v6
	v_div_fmas_f32 v6, v6, v17, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v15, v6, |v10|, s5
.LBB0_49:
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v6, 0x4479c000
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_51
; %bb.50:
	v_and_b32_e32 v6, 0x7fffffff, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v10, null, v6, v6, s4
	v_rcp_f32_e32 v17, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v10, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v17
	v_div_scale_f32 v6, vcc_lo, s4, v6, s4
	v_mul_f32_e32 v18, v6, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v10, v18, v6
	v_fmac_f32_e32 v18, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v10, v18, v6
	v_div_fmas_f32 v6, v6, v17, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v6, v6, |v12|, s4
.LBB0_51:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr10
	v_cmpx_nlt_f32_e32 v8, v9
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_55
; %bb.52:
	v_mov_b32_e32 v10, v14
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_f32_e32 v9, v14
; %bb.53:
	v_mov_b32_e32 v10, v9
; %bb.54:                               ; %Flow274
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_55:                               ; %Flow276
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_59
; %bb.56:
	v_mov_b32_e32 v10, v14
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_f32_e32 v8, v14
; %bb.57:
	v_mov_b32_e32 v10, v8
; %bb.58:                               ; %Flow275
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_59:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v12, 0
	s_mov_b32 s4, exec_lo
	v_cmpx_lt_f32_e32 v10, v0
	s_cbranch_execz .LBB0_77
; %bb.60:                               ; %.lr.ph
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_sizeCT@rel32@lo+4
	s_addc_u32 s1, s1, d_sizeCT@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, d_sizeCT@rel32@lo+12
	s_addc_u32 s7, s7, d_sizeCT@rel32@hi+20
	v_cmp_lt_f32_e32 vcc_lo, s19, v3
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s5, s[6:7], 0x0
	v_mov_b32_e32 v12, 0
	v_cndmask_b32_e64 v3, -1.0, 1.0, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, s18, v4
	v_cndmask_b32_e64 v4, -1.0, 1.0, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, s17, v7
	v_cndmask_b32_e64 v7, -1.0, 1.0, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v17, s2
	v_cvt_f32_i32_e32 v18, s3
	v_cvt_f32_i32_e32 v19, s5
	s_mov_b32 s2, 0
.LBB0_61:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_f32_e32 vcc_lo, v8, v9
	v_cmp_le_f32_e64 s0, v8, v14
                                        ; implicit-def: $vgpr20
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
; %bb.62:                               ;   in Loop: Header=BB0_61 Depth=1
	v_dual_add_f32 v5, v3, v5 :: v_dual_add_f32 v20, v16, v8
; %bb.63:                               ; %Flow271
                                        ;   in Loop: Header=BB0_61 Depth=1
	s_and_not1_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_69
; %bb.64:                               ;   in Loop: Header=BB0_61 Depth=1
	v_cmp_le_f32_e32 vcc_lo, v9, v8
	v_cmp_le_f32_e64 s0, v9, v14
                                        ; implicit-def: $vgpr20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s6, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s6
; %bb.65:                               ;   in Loop: Header=BB0_61 Depth=1
	v_dual_add_f32 v11, v4, v11 :: v_dual_add_f32 v20, v15, v9
; %bb.66:                               ; %Flow269
                                        ;   in Loop: Header=BB0_61 Depth=1
	s_or_saveexec_b32 s0, s0
	v_mov_b32_e32 v21, v9
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.67:                               ;   in Loop: Header=BB0_61 Depth=1
	v_dual_add_f32 v22, v6, v14 :: v_dual_add_f32 v13, v7, v13
	v_dual_mov_b32 v21, v14 :: v_dual_mov_b32 v20, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v14, v22
; %bb.68:                               ; %Flow270
                                        ;   in Loop: Header=BB0_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v9, v20
	v_mov_b32_e32 v20, v8
	v_mov_b32_e32 v8, v21
.LBB0_69:                               ;   in Loop: Header=BB0_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s6, exec_lo
	v_cmpx_le_f32_e32 0, v13
	s_cbranch_execz .LBB0_75
; %bb.70:                               ;   in Loop: Header=BB0_61 Depth=1
	v_cmp_lt_f32_e32 vcc_lo, v13, v17
	v_cmp_le_f32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s7, s0
	s_cbranch_execz .LBB0_74
; %bb.71:                               ;   in Loop: Header=BB0_61 Depth=1
	v_cmp_lt_f32_e32 vcc_lo, v11, v18
	v_cmp_lt_f32_e64 s0, v5, v19
	v_cmp_le_f32_e64 s1, 0, v5
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_73
; %bb.72:                               ;   in Loop: Header=BB0_61 Depth=1
	v_cvt_i32_f32_e32 v21, v11
	v_cvt_i32_f32_e32 v24, v13
	s_load_b128 s[8:11], s[14:15], 0x0
	v_sub_f32_e32 v10, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, s3, v24, v[21:22]
	v_cvt_i32_f32_e32 v21, v5
	v_mad_u64_u32 v[23:24], null, v22, s5, v[21:22]
	s_waitcnt lgkmcnt(0)
	buffer_load_format_x v21, v23, s[8:11], 0 idxen
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v10, v10, v21
	v_cmp_lt_f32_e32 vcc_lo, 0, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, 0x80000000, v10, vcc_lo
	v_add_f32_e32 v12, v12, v10
.LBB0_73:                               ; %Flow
                                        ;   in Loop: Header=BB0_61 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_74:                               ; %Flow268
                                        ;   in Loop: Header=BB0_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_75:                               ;   in Loop: Header=BB0_61 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_cmp_nlt_f32_e32 vcc_lo, v8, v0
	v_mov_b32_e32 v10, v8
	v_mov_b32_e32 v8, v20
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_61
; %bb.76:                               ; %Flow272
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_77:                               ; %Flow273
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_cmp_ngt_f32_e32 vcc_lo, 0, v12
	v_cndmask_b32_e32 v0, 0, v12, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v0
	v_cndmask_b32_e32 v0, 0x437f0000, v0, vcc_lo
.LBB0_78:                               ; %Flow290
	s_or_b32 exec_lo, exec_lo, s20
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_79:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7drrCUDAPfP13__hip_textureS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7drrCUDAPfP13__hip_textureS1_, .Lfunc_end0-_Z7drrCUDAPfP13__hip_textureS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3976
; NumSgprs: 26
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_sizeCT                ; @d_sizeCT
	.type	d_sizeCT,@object
	.section	.bss,"aw",@nobits
	.globl	d_sizeCT
	.p2align	2, 0x0
d_sizeCT:
	.zero	12
	.size	d_sizeCT, 12

	.protected	ctPixelSpacing          ; @ctPixelSpacing
	.type	ctPixelSpacing,@object
	.globl	ctPixelSpacing
	.p2align	2, 0x0
ctPixelSpacing:
	.zero	12
	.size	ctPixelSpacing, 12

	.protected	DRRImageSize            ; @DRRImageSize
	.type	DRRImageSize,@object
	.globl	DRRImageSize
	.p2align	2, 0x0
DRRImageSize:
	.zero	8
	.size	DRRImageSize, 8

	.protected	d_DRR_Parameters        ; @d_DRR_Parameters
	.type	d_DRR_Parameters,@object
	.globl	d_DRR_Parameters
	.p2align	4, 0x0
d_DRR_Parameters:
	.zero	48
	.size	d_DRR_Parameters, 48

	.protected	d_useMask               ; @d_useMask
	.type	d_useMask,@object
	.globl	d_useMask
d_useMask:
	.byte	0                               ; 0x0
	.size	d_useMask, 1

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_sizeCT
	.addrsig_sym ctPixelSpacing
	.addrsig_sym DRRImageSize
	.addrsig_sym d_DRR_Parameters
	.addrsig_sym d_useMask
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7drrCUDAPfP13__hip_textureS1_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z7drrCUDAPfP13__hip_textureS1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
