#include <iostream>
#include <fstream>
#include <string.h>
#include <sys/time.h>
#include <math.h>
#include <random>

#include <cuda_runtime.h>
#include <device_launch_parameters.h>

using namespace std;

#define BLOCKSIZE 1024
#define FLOAT_MIN 10
#define FLOAT_MAX 100

#define GPU_ERR_CHK(ans)                      \
    {                                         \
        gpuAssert((ans), __FILE__, __LINE__); \
    }

/**
 * @brief Comprueba el codigo de error de una llamada Cuda
 * @param code Codigo del error
 * @param file Archivo donde se produjo el error
 * @param line Linea que ha dado el error
 * @param abort Indica si debe abortar el programa ante el error. True por defecto
*/
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
    if (code != cudaSuccess)
    {
        fprintf(stderr, "GPU assert: %s %s %d\n", cudaGetErrorString(code), file, line);
        if (abort)
            exit(code);
    }
}

/**
 * @brief Desenrrollado de bucle del ultimo warp de cada bloque
 * @param sdata Puntero a memoria compartida de device
 * @param tid Identificador de hebra de GPU
 * @post sdata es modificado
*/
__device__ void warpReduce(volatile float *sdata, int tid)
{
    sdata[tid] = (sdata[tid] > sdata[tid + 32]) ? sdata[tid] : sdata[tid + 32];
    sdata[tid] = (sdata[tid] > sdata[tid + 16]) ? sdata[tid] : sdata[tid + 16];
    sdata[tid] = (sdata[tid] > sdata[tid + 8]) ? sdata[tid] : sdata[tid + 8];
    sdata[tid] = (sdata[tid] > sdata[tid + 4]) ? sdata[tid] : sdata[tid + 4];
    sdata[tid] = (sdata[tid] > sdata[tid + 2]) ? sdata[tid] : sdata[tid + 2];
    sdata[tid] = (sdata[tid] > sdata[tid + 1]) ? sdata[tid] : sdata[tid + 1];
}

/**
 * @brief Kernel para la reduccion
 * @param Min Vector a reducir
 * @param Mout Resultado de la reduccion
 * @note La reduccion se hace por bloques usando memoria compartida
 * por lo que el vector de salida no esta reducido completamente
*/
__global__ void reduce_max(float *Min, float *Mout, const int nverts)
{
    extern __shared__ float sdata[];

    // Cada hebra carga un elemento a memoria compartida
    int tid = threadIdx.x;
    int i = blockIdx.x * blockDim.x + threadIdx.x;

    // Primera reduccion antes de cargar en memoria compartida
    sdata[tid] = (Min[i] > Min[i + blockDim.x]) ? Min[i] : Min[i + blockDim.x];
    __syncthreads();

    // Hacer reduccion en memoria compartida
    for (int s = blockDim.x / 2; s > 32; s >>= 1)
    {
        if (tid < s)
            sdata[tid] = (sdata[tid] > sdata[tid + s]) ? sdata[tid] : sdata[tid + s];
        __syncthreads();
    }

    if (tid < 32)
        warpReduce(sdata, tid);

    if (tid == 0)
        Mout[blockIdx.x] = sdata[0];
}

/**
 * @brief Kernel que calcula el vector B del problema
 * @param B_in Vector con los datos de entrada
 * @param N Tamaño del vector
 * @note Esta version hace uso de memoria compartida
*/
__global__ void calcula_B_shared(float *B_in, int N)
{
    extern __shared__ float sdata[];

    float A_im2, A_im1, A_i, A_ip1, A_ip2;
    int tid = threadIdx.x;
    int i = blockIdx.x * blockDim.x + threadIdx.x;

    if (i < N)
    {
        sdata[tid] = B_in[i];
        //__syncthreads(); // Esperar a que las hebras carguen en memoria compartida

        A_im2 = (i - 2 < 0) ? 0.0 : B_in[i - 2];
        A_im1 = (i - 1 < 0) ? 0.0 : B_in[i - 1];
        A_i = B_in[i];
        A_ip1 = (i + 1 > N) ? 0.0 : B_in[i + 1];
        A_ip2 = (i + 2 > N) ? 0.0 : B_in[i + 2];

        sdata[tid] = (pow(A_im2, 2) + 2 * pow(A_im1, 2) + pow(A_i, 2) - 3 * pow(A_ip1, 2) + 5 * pow(A_ip2, 2)) / 24.0;
    }

    // Copiar de memoria compartida a salida
    if (tid == 0)
    {
        int offset = blockIdx.x * blockDim.x;
        int posicion;

        for (int i = 0; i < blockDim.x; i++)
        {
            posicion = offset + i;

            if (posicion < N) // Necesario por las hebras que sobran
                B_in[posicion] = sdata[i];
        }
    }
}

/**
 * @brief Kernel que calcula el vector B del problema
 * @param B_in Vector con los datos de entrada
 * @param B_out Vector con los datos de salida
 * @param N Tamaño del vector
 * @note Esta version no hace uso de memoria compartida
*/
__global__ void calcula_B(float *B_in, float *B_out, int N)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    float A_im2, A_im1, A_i, A_ip1, A_ip2;

    if (i < N)
    {
        A_im2 = (i - 2 < 0) ? 0.0 : B_in[i - 2];
        A_im1 = (i - 1 < 0) ? 0.0 : B_in[i - 1];
        A_i = B_in[i];
        A_ip1 = (i + 1 > N) ? 0.0 : B_in[i + 1];
        A_ip2 = (i + 2 > N) ? 0.0 : B_in[i + 2];

        B_out[i] = (pow(A_im2, 2) + 2 * pow(A_im1, 2) + pow(A_i, 2) - 3 * pow(A_ip1, 2) + 5 * pow(A_ip2, 2)) / 24.0;
    }
}

/**
 * @brief Genera número aleatorio
 * @note cambiar valores de macros 
 * para mayor o menor rango
*/
float generate_random_float()
{
    static default_random_engine generador;
    static uniform_real_distribution<float> distribucion_uniforme(FLOAT_MIN, FLOAT_MAX);
    return distribucion_uniforme(generador);
}

/**
 * @brief Calcula un instante de tiempo
 * @return Instante de tiempo
*/
double cpuSecond()
{
    struct timeval tp;
    gettimeofday(&tp, NULL);
    return ((double)tp.tv_sec + (double)tp.tv_usec * 1e-6);
}

int main(int argc, char const *argv[])
{
    // Get GPU information
    int dev_id;
    int num_val;
    cudaDeviceProp props;

    GPU_ERR_CHK(cudaGetDevice(&dev_id));

    cudaGetDeviceProperties(&props, dev_id);

    printf("Device %d: \"%s\" with Compute %d.%d capability\n",
           dev_id, props.name, props.major, props.minor);

    cout << "Introduce numero de valores: ";
    cin >> num_val;

    //****************************
    // Inicializamos vector A
    //****************************
    float *A = new float[num_val]; //  Vector de entrada A

    for (int i = 0; i < num_val; i++)
        A[i] = generate_random_float();

    //****************************
    // Calculamos vector B en CPU
    //****************************
    float *B = new float[num_val];

    float A_im2, A_im1, A_i, A_ip1, A_ip2;

    double t_cpu_inicial = cpuSecond();

    for (int i = 0; i < num_val; i++)
    {
        A_im2 = (i - 2 < 0) ? 0.0 : A[i - 2];
        A_im1 = (i - 1 < 0) ? 0.0 : A[i - 1];
        A_i = A[i];
        A_ip1 = (i + 1 > num_val) ? 0.0 : A[i + 1];
        A_ip2 = (i + 2 > num_val) ? 0.0 : A[i + 2];
        B[i] = (pow(A_im2, 2) + 2 * pow(A_im1, 2) + pow(A_i, 2) - 3 * pow(A_ip1, 2) + 5 * pow(A_ip2, 2)) / 24.0;
    }

    double t_cpu_final = cpuSecond();
    double t_cpu = t_cpu_final - t_cpu_inicial;

    //*****************************************************
    // Calculamos vector B en GPU (sin memoria compartida)
    //*****************************************************
    float *d_A, *d_b;
    float *h_b = new float[num_val];

    GPU_ERR_CHK(cudaMalloc((void **)&d_A, num_val * sizeof(float)));
    GPU_ERR_CHK(cudaMalloc((void **)&d_b, num_val * sizeof(float)));
    GPU_ERR_CHK(cudaMemcpy(d_A, A, num_val * sizeof(float), cudaMemcpyHostToDevice));

    int blocks_per_grid = ceil((float)num_val / (float)BLOCKSIZE);

    double t_gpu_inicial_1 = cpuSecond();
    calcula_B<<<blocks_per_grid, BLOCKSIZE>>>(d_A, d_b, num_val);
    GPU_ERR_CHK(cudaDeviceSynchronize());
    double t_gpu_final_1 = cpuSecond();

    GPU_ERR_CHK(cudaGetLastError());
    GPU_ERR_CHK(cudaMemcpy(h_b, d_b, num_val * sizeof(float), cudaMemcpyDeviceToHost));
    GPU_ERR_CHK(cudaDeviceSynchronize());

    double t_gpu_1 = t_gpu_final_1 - t_gpu_inicial_1;

    //*****************************************************
    // Calculamos vector B en GPU (con memoria compartida)
    //*****************************************************
    float *d_c;
    float *h_c = new float[num_val];
    int shared_mem_size = BLOCKSIZE * sizeof(float);

    GPU_ERR_CHK(cudaMalloc((void **)&d_c, num_val * sizeof(float)));
    GPU_ERR_CHK(cudaMemcpy(d_c, A, num_val * sizeof(float), cudaMemcpyHostToDevice));

    double t_gpu_inicial_2 = cpuSecond();
    calcula_B_shared<<<blocks_per_grid, BLOCKSIZE, shared_mem_size>>>(d_c, num_val);
    GPU_ERR_CHK(cudaDeviceSynchronize());
    double t_gpu_final_2 = cpuSecond();

    GPU_ERR_CHK(cudaGetLastError());
    GPU_ERR_CHK(cudaMemcpy(h_c, d_c, num_val * sizeof(float), cudaMemcpyDeviceToHost));
    GPU_ERR_CHK(cudaDeviceSynchronize());

    double t_gpu_2 = t_gpu_final_2 - t_gpu_inicial_2;

    //******************
    // Reduccion en CPU
    //******************
    double t_red_cpu_ini = cpuSecond();

    float mayor_cpu = B[0];

    for (int i = 1; i < num_val; i++)
    {
        mayor_cpu = (B[i] > mayor_cpu) ? B[i] : mayor_cpu;
    }

    double t_red_cpu_fin = cpuSecond();
    double t_red_cpu = t_red_cpu_fin - t_red_cpu_ini;

    //******************
    // Reduccion en GPU
    //******************
    float *d_d, *d_e;                        // Parametros de entrada del kernel
    float *h_d = new float[blocks_per_grid]; // Salida del kernel en el host

    GPU_ERR_CHK(cudaMalloc((void **)&d_d, num_val * sizeof(float)));
    GPU_ERR_CHK(cudaMalloc((void **)&d_e, blocks_per_grid * sizeof(float)));
    GPU_ERR_CHK(cudaMemcpy(d_d, B, num_val * sizeof(float), cudaMemcpyHostToDevice));

    double t_gpu_inicial_3 = cpuSecond();
    reduce_max<<<blocks_per_grid, BLOCKSIZE, shared_mem_size>>>(d_d, d_e, num_val);
    GPU_ERR_CHK(cudaDeviceSynchronize());
    double t_gpu_final_3 = cpuSecond();

    GPU_ERR_CHK(cudaGetLastError());
    GPU_ERR_CHK(cudaMemcpy(h_d, d_e, blocks_per_grid * sizeof(float), cudaMemcpyDeviceToHost));
    GPU_ERR_CHK(cudaDeviceSynchronize());

    float mayor_gpu = h_d[0];

    for (int i = 1; i < blocks_per_grid; i++)
    {
        mayor_gpu = (h_d[i] > mayor_gpu) ? h_d[i] : mayor_gpu;
    }

    double t_red_gpu = t_gpu_final_3 - t_gpu_inicial_3;

    //****************************
    // Comprobacion CPU-GPU
    //****************************
    bool passed = true;
    int i = 0;

    while (passed && i < num_val)
    {
        if (B[i] != h_b[i] && B[i] != h_c[i])
        {
            cout << "ERR B[" << i << "] = " << B[i]
                 << " h_b[" << i << "] = " << h_b[i]
                 << " h_c[" << i << "] = " << h_c[i]
                 << endl;
            passed = false;
        }
        i++;
    }

    if (passed)
        cout << "PASSED TEST" << endl;
    else
        cout << "ERROR IN TEST" << endl;

    //********************
    // Mostrar resultados
    //********************
    cout << "Tiempo en CPU = " << t_cpu << endl
         << "Tiempo en GPU (sin memoria compartida) = " << t_gpu_1 << endl
         << "Tiempo en GPU (con memoria compartida) = " << t_gpu_2 << endl
         << "Ganancia (sin memoria compartida) = " << t_cpu / t_gpu_1 << endl
         << "Ganancia (con memoria compartida) = " << t_cpu / t_gpu_2 << endl
         << "Tiempo de reduccion en CPU = " << t_red_cpu << endl
         << "Tiempo de reduccion en GPU = " << t_red_gpu << endl
         << "Valor de reduccion en CPU = " << mayor_cpu << endl
         << "Valor de reduccion en GPU = " << mayor_gpu << endl;

    // Liberar memoria host
    delete (A);
    delete (B);
    delete (h_b);
    delete (h_c);
    delete (h_d);

    // Liberar memoria device
    cudaFree(d_A);
    cudaFree(d_b);
    cudaFree(d_c);
    cudaFree(d_d);
    cudaFree(d_e);

    return 0;
}

	.file	"tmpxft_002e091c_00000000-6_op_vectorial.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4857:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4857:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPU assert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4850:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE4850:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z10warpReducePVfi
	.type	_Z10warpReducePVfi, @function
_Z10warpReducePVfi:
.LFB4851:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4851:
	.size	_Z10warpReducePVfi, .-_Z10warpReducePVfi
	.globl	_Z21generate_random_floatv
	.type	_Z21generate_random_floatv, @function
_Z21generate_random_floatv:
.LFB4852:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movb	_ZGVZ21generate_random_floatvE9generador(%rip), %al
	testb	%al, %al
	jne	.L16
	leaq	_ZGVZ21generate_random_floatvE9generador(%rip), %rbx
	movq	%rbx, %rdi
	call	__cxa_guard_acquire@PLT
	testl	%eax, %eax
	je	.L16
	movq	$1, _ZZ21generate_random_floatvE9generador(%rip)
	movq	%rbx, %rdi
	call	__cxa_guard_release@PLT
.L16:
	movb	_ZGVZ21generate_random_floatvE21distribucion_uniforme(%rip), %al
	testb	%al, %al
	jne	.L19
	leaq	_ZGVZ21generate_random_floatvE21distribucion_uniforme(%rip), %rbx
	movq	%rbx, %rdi
	call	__cxa_guard_acquire@PLT
	testl	%eax, %eax
	je	.L19
	movabsq	$4812096202937991168, %rax
	movq	%rbx, %rdi
	movq	%rax, _ZZ21generate_random_floatvE21distribucion_uniforme(%rip)
	call	__cxa_guard_release@PLT
.L19:
	movl	$2147483647, %ecx
	xorl	%edx, %edx
	movss	_ZZ21generate_random_floatvE21distribucion_uniforme(%rip), %xmm2
	movss	4+_ZZ21generate_random_floatvE21distribucion_uniforme(%rip), %xmm0
	imulq	$16807, _ZZ21generate_random_floatvE9generador(%rip), %rax
	divq	%rcx
	movq	%rdx, _ZZ21generate_random_floatvE9generador(%rip)
	decq	%rdx
	js	.L21
	cvtsi2ssq	%rdx, %xmm1
	jmp	.L22
.L21:
	movq	%rdx, %rax
	andl	$1, %edx
	shrq	%rax
	orq	%rdx, %rax
	cvtsi2ssq	%rax, %xmm1
	addss	%xmm1, %xmm1
.L22:
	xorps	%xmm3, %xmm3
	addss	%xmm3, %xmm1
	mulss	.LC3(%rip), %xmm1
	comiss	.LC4(%rip), %xmm1
	jb	.L23
	movss	.LC1(%rip), %xmm1
.L23:
	subss	%xmm2, %xmm0
	popq	%rbx
	.cfi_def_cfa_offset 8
	mulss	%xmm1, %xmm0
	addss	%xmm2, %xmm0
	ret
	.cfi_endproc
.LFE4852:
	.size	_Z21generate_random_floatv, .-_Z21generate_random_floatv
	.globl	_Z9cpuSecondv
	.type	_Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB4853:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	xorl	%esi, %esi
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	cvtsi2sdq	16(%rsp), %xmm0
	mulsd	.LC5(%rip), %xmm0
	cvtsi2sdq	8(%rsp), %xmm1
	addsd	%xmm1, %xmm0
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4853:
	.size	_Z9cpuSecondv, .-_Z9cpuSecondv
	.globl	_Z33__device_stub__Z10reduce_maxPfS_iPfS_i
	.type	_Z33__device_stub__Z10reduce_maxPfS_iPfS_i, @function
_Z33__device_stub__Z10reduce_maxPfS_iPfS_i:
.LFB4879:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10reduce_maxPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L35:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4879:
	.size	_Z33__device_stub__Z10reduce_maxPfS_iPfS_i, .-_Z33__device_stub__Z10reduce_maxPfS_iPfS_i
	.globl	_Z10reduce_maxPfS_i
	.type	_Z10reduce_maxPfS_i, @function
_Z10reduce_maxPfS_i:
.LFB4880:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10reduce_maxPfS_iPfS_i
	.cfi_endproc
.LFE4880:
	.size	_Z10reduce_maxPfS_i, .-_Z10reduce_maxPfS_i
	.globl	_Z37__device_stub__Z16calcula_B_sharedPfiPfi
	.type	_Z37__device_stub__Z16calcula_B_sharedPfiPfi, @function
_Z37__device_stub__Z16calcula_B_sharedPfiPfi:
.LFB4881:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z16calcula_B_sharedPfi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L40:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4881:
	.size	_Z37__device_stub__Z16calcula_B_sharedPfiPfi, .-_Z37__device_stub__Z16calcula_B_sharedPfiPfi
	.globl	_Z16calcula_B_sharedPfi
	.type	_Z16calcula_B_sharedPfi, @function
_Z16calcula_B_sharedPfi:
.LFB4882:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z16calcula_B_sharedPfiPfi
	.cfi_endproc
.LFE4882:
	.size	_Z16calcula_B_sharedPfi, .-_Z16calcula_B_sharedPfi
	.globl	_Z31__device_stub__Z9calcula_BPfS_iPfS_i
	.type	_Z31__device_stub__Z9calcula_BPfS_iPfS_i, @function
_Z31__device_stub__Z9calcula_BPfS_iPfS_i:
.LFB4883:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9calcula_BPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L45:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4883:
	.size	_Z31__device_stub__Z9calcula_BPfS_iPfS_i, .-_Z31__device_stub__Z9calcula_BPfS_iPfS_i
	.globl	_Z9calcula_BPfS_i
	.type	_Z9calcula_BPfS_i, @function
_Z9calcula_BPfS_i:
.LFB4884:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9calcula_BPfS_iPfS_i
	.cfi_endproc
.LFE4884:
	.size	_Z9calcula_BPfS_i, .-_Z9calcula_BPfS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC6:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/pakejo/Practicas_PPR_UGR/main/P1/advection1d_code/op_vectorial.cu"
.LC7:
	.string	"Device %d: \"%s\" with Compute %d.%d capability\n"
.LC8:
	.string	"Introduce numero de valores: "
.LC13:
	.string	"ERR B["
.LC14:
	.string	"] = "
.LC15:
	.string	" h_b["
.LC16:
	.string	" h_c["
.LC17:
	.string	"ERROR IN TEST"
.LC18:
	.string	"PASSED TEST"
.LC19:
	.string	"Tiempo en CPU = "
.LC20:
	.string	"Tiempo en GPU (sin memoria compartida) = "
.LC21:
	.string	"Tiempo en GPU (con memoria compartida) = "
.LC22:
	.string	"Ganancia (sin memoria compartida) = "
.LC23:
	.string	"Ganancia (con memoria compartida) = "
.LC24:
	.string	"Tiempo de reduccion en CPU = "
.LC25:
	.string	"Tiempo de reduccion en GPU = "
.LC26:
	.string	"Valor de reduccion en CPU = "
.LC27:
	.string	"Valor de reduccion en GPU = "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4854:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC6(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$1208, %rsp
	.cfi_def_cfa_offset 1264
	movq	%fs:40, %rax
	movq	%rax, 1192(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rdi
	leaq	160(%rsp), %rbx
	call	cudaGetDevice@PLT
	movl	$1, %ecx
	movl	$187, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	88(%rsp), %esi
	movq	%rbx, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	88(%rsp), %edx
	movq	%rbx, %rcx
	xorl	%eax, %eax
	movl	524(%rsp), %r9d
	movl	520(%rsp), %r8d
	movl	$2, %edi
	leaq	.LC7(%rip), %rsi
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	_ZSt3cin(%rip), %rdi
	leaq	92(%rsp), %rsi
	call	_ZNSirsERi@PLT
	movslq	92(%rsp), %rdi
	movabsq	$2305843009213693950, %rax
	cmpq	%rdi, %rax
	jb	.L51
	salq	$2, %rdi
	xorl	%ebp, %ebp
	call	_Znam@PLT
	movq	%rax, %rbx
	jmp	.L52
.L85:
	movabsq	$2305843009213693950, %rax
	cmpq	%rdi, %rax
	jb	.L51
	salq	$2, %rdi
	call	_Znam@PLT
	movq	%rax, %rbp
	call	_Z9cpuSecondv
	movl	92(%rsp), %edx
	xorl	%eax, %eax
	movsd	.LC9(%rip), %xmm3
	movsd	.LC10(%rip), %xmm4
	movsd	.LC11(%rip), %xmm5
	movsd	%xmm0, 8(%rsp)
.L55:
	cmpl	%eax, %edx
	jg	.L60
	call	_Z9cpuSecondv
	subsd	8(%rsp), %xmm0
	movslq	92(%rsp), %rdi
	movabsq	$2305843009213693950, %rax
	movsd	%xmm0, 32(%rsp)
	cmpq	%rdi, %rax
	jnb	.L84
.L51:
	movq	1192(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L83
	call	__cxa_throw_bad_array_new_length@PLT
.L52:
	movslq	92(%rsp), %rdi
	cmpl	%ebp, %edi
	jle	.L85
	call	_Z21generate_random_floatv
	movss	%xmm0, (%rbx,%rbp,4)
	incq	%rbp
	jmp	.L52
.L60:
	cmpq	$1, %rax
	jbe	.L56
	movss	-8(%rbx,%rax,4), %xmm6
	jmp	.L57
.L56:
	xorps	%xmm6, %xmm6
	movaps	%xmm6, %xmm0
	testq	%rax, %rax
	je	.L58
.L57:
	movss	-4(%rbx,%rax,4), %xmm0
.L58:
	leal	1(%rax), %ecx
	movss	(%rbx,%rax,4), %xmm7
	movss	4(%rbx,%rax,4), %xmm2
	xorps	%xmm1, %xmm1
	cmpl	%edx, %ecx
	jge	.L59
	movss	8(%rbx,%rax,4), %xmm1
.L59:
	cvtss2sd	%xmm0, %xmm0
	mulsd	%xmm0, %xmm0
	cvtss2sd	%xmm6, %xmm6
	cvtss2sd	%xmm2, %xmm2
	mulsd	%xmm6, %xmm6
	cvtss2sd	%xmm7, %xmm7
	cvtss2sd	%xmm1, %xmm1
	mulsd	%xmm2, %xmm2
	mulsd	%xmm7, %xmm7
	mulsd	%xmm1, %xmm1
	addsd	%xmm0, %xmm0
	mulsd	%xmm3, %xmm2
	addsd	%xmm6, %xmm0
	mulsd	%xmm4, %xmm1
	addsd	%xmm7, %xmm0
	subsd	%xmm2, %xmm0
	addsd	%xmm1, %xmm0
	divsd	%xmm5, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	jmp	.L55
.L84:
	salq	$2, %rdi
	call	_Znam@PLT
	movslq	92(%rsp), %rsi
	leaq	96(%rsp), %rdi
	movq	%rax, %r12
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$233, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	92(%rsp), %rsi
	leaq	104(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$234, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	92(%rsp), %rdx
	movq	96(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$235, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	cvtsi2ssl	92(%rsp), %xmm0
	mulss	.LC12(%rip), %xmm0
	call	ceilf@PLT
	cvttss2sil	%xmm0, %r13d
	call	_Z9cpuSecondv
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	movl	$1, 156(%rsp)
	movq	%rax, 140(%rsp)
	movl	144(%rsp), %esi
	movl	%r13d, 136(%rsp)
	movq	136(%rsp), %rdi
	movq	%rdx, 148(%rsp)
	movsd	%xmm0, 8(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	movl	92(%rsp), %edx
	movq	104(%rsp), %rsi
	movq	96(%rsp), %rdi
	call	_Z31__device_stub__Z9calcula_BPfS_iPfS_i
.L61:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$241, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	_Z9cpuSecondv
	movsd	%xmm0, 16(%rsp)
	call	cudaGetLastError@PLT
	movl	$1, %ecx
	movl	$244, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	92(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	%r12, %rdi
	movl	$2, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$245, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$246, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movsd	16(%rsp), %xmm0
	movslq	92(%rsp), %rdi
	movabsq	$2305843009213693950, %rax
	subsd	8(%rsp), %xmm0
	movsd	%xmm0, 40(%rsp)
	cmpq	%rdi, %rax
	jb	.L51
	salq	$2, %rdi
	call	_Znam@PLT
	movslq	92(%rsp), %rsi
	leaq	112(%rsp), %rdi
	movq	%rax, 8(%rsp)
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$257, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	92(%rsp), %rdx
	movq	112(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$258, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	_Z9cpuSecondv
	movl	%r13d, 136(%rsp)
	movl	$4194305, %edx
	movabsq	$4294967297, %rax
	movq	%rax, 140(%rsp)
	movl	144(%rsp), %esi
	salq	$10, %rdx
	xorl	%r9d, %r9d
	movq	136(%rsp), %rdi
	movl	$4096, %r8d
	movl	$1, %ecx
	movq	%rdx, 148(%rsp)
	movl	$1, 156(%rsp)
	movsd	%xmm0, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movl	92(%rsp), %esi
	movq	112(%rsp), %rdi
	call	_Z37__device_stub__Z16calcula_B_sharedPfiPfi
.L62:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$262, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	_Z9cpuSecondv
	movsd	%xmm0, 24(%rsp)
	call	cudaGetLastError@PLT
	movl	$1, %ecx
	movl	$265, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	92(%rsp), %rdx
	movq	112(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$266, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$267, %edx
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movsd	24(%rsp), %xmm0
	subsd	16(%rsp), %xmm0
	movsd	%xmm0, 48(%rsp)
	call	_Z9cpuSecondv
	movss	0(%rbp), %xmm3
	movl	92(%rsp), %edx
	movl	$1, %eax
	movsd	%xmm0, 24(%rsp)
	movss	%xmm3, 16(%rsp)
.L63:
	cmpl	%eax, %edx
	jle	.L86
	movss	0(%rbp,%rax,4), %xmm0
	maxss	16(%rsp), %xmm0
	incq	%rax
	movss	%xmm0, 16(%rsp)
	jmp	.L63
.L86:
	call	_Z9cpuSecondv
	subsd	24(%rsp), %xmm0
	movslq	%r13d, %rax
	movabsq	$2305843009213693950, %rdx
	movsd	%xmm0, 56(%rsp)
	cmpq	%rax, %rdx
	jb	.L51
	salq	$2, %rax
	leaq	.LC6(%rip), %r14
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
	call	_Znam@PLT
	movslq	92(%rsp), %rsi
	leaq	120(%rsp), %rdi
	movq	%rax, %r15
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$292, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	24(%rsp), %rsi
	leaq	128(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$293, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	92(%rsp), %rdx
	movq	120(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$294, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	_Z9cpuSecondv
	movl	%r13d, 136(%rsp)
	movl	$4194305, %edx
	movabsq	$4294967297, %rax
	movq	%rax, 140(%rsp)
	movl	144(%rsp), %esi
	salq	$10, %rdx
	xorl	%r9d, %r9d
	movq	136(%rsp), %rdi
	movl	$4096, %r8d
	movl	$1, %ecx
	movq	%rdx, 148(%rsp)
	movl	$1, 156(%rsp)
	movsd	%xmm0, 64(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	movl	92(%rsp), %edx
	movq	128(%rsp), %rsi
	movq	120(%rsp), %rdi
	call	_Z33__device_stub__Z10reduce_maxPfS_iPfS_i
.L66:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$298, %edx
	leaq	.LC6(%rip), %r14
	movl	%eax, %edi
	movq	%r14, %rsi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	_Z9cpuSecondv
	movsd	%xmm0, 72(%rsp)
	call	cudaGetLastError@PLT
	movl	$1, %ecx
	movl	$301, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	24(%rsp), %rdx
	movl	$2, %ecx
	movq	%r15, %rdi
	movq	128(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$302, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$303, %edx
	movq	%r14, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movss	(%r15), %xmm3
	movsd	72(%rsp), %xmm0
	movl	$1, %eax
	movss	%xmm3, 24(%rsp)
.L67:
	cmpl	%eax, %r13d
	jle	.L87
	movss	(%r15,%rax,4), %xmm1
	maxss	24(%rsp), %xmm1
	incq	%rax
	movss	%xmm1, 24(%rsp)
	jmp	.L67
.L87:
	subsd	64(%rsp), %xmm0
	movl	92(%rsp), %eax
	xorl	%r14d, %r14d
	xorl	%r13d, %r13d
	movsd	%xmm0, 64(%rsp)
.L70:
	cmpl	%r13d, %eax
	jle	.L88
	movss	0(%rbp,%r14), %xmm0
	ucomiss	(%r12,%r14), %xmm0
	jp	.L79
	je	.L71
.L79:
	movq	8(%rsp), %rcx
	ucomiss	(%rcx,%r14), %xmm0
	jp	.L80
	je	.L71
.L80:
	leaq	.LC13(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	0(%rbp,%r14), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC15(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	(%r12,%r14), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC16(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	8(%rsp), %rax
	cvtss2sd	(%rax,%r14), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC17(%rip), %rsi
	jmp	.L82
.L71:
	incl	%r13d
	addq	$4, %r14
	jmp	.L70
.L88:
	leaq	.LC18(%rip), %rsi
.L82:
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC19(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	32(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC20(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	40(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC21(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	48(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC22(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	32(%rsp), %xmm0
	divsd	40(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC23(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	32(%rsp), %xmm0
	divsd	48(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC24(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	56(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC25(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	64(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC26(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	16(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC27(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	24(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movl	$4, %esi
	movq	%rbx, %rdi
	call	_ZdlPvm@PLT
	movl	$4, %esi
	movq	%rbp, %rdi
	call	_ZdlPvm@PLT
	movl	$4, %esi
	movq	%r12, %rdi
	call	_ZdlPvm@PLT
	movq	8(%rsp), %rdi
	movl	$4, %esi
	call	_ZdlPvm@PLT
	movl	$4, %esi
	movq	%r15, %rdi
	call	_ZdlPvm@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	1192(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
.L83:
	call	__stack_chk_fail@PLT
.L76:
	addq	$1208, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4854:
	.size	main, .-main
	.section	.rodata.str1.1
.LC28:
	.string	"_Z9calcula_BPfS_i"
.LC29:
	.string	"_Z16calcula_B_sharedPfi"
.LC30:
	.string	"_Z10reduce_maxPfS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4886:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC28(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9calcula_BPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16calcula_B_sharedPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10reduce_maxPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4886:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZGVZ21generate_random_floatvE21distribucion_uniforme
	.comm	_ZGVZ21generate_random_floatvE21distribucion_uniforme,8,8
	.local	_ZZ21generate_random_floatvE21distribucion_uniforme
	.comm	_ZZ21generate_random_floatvE21distribucion_uniforme,8,8
	.local	_ZGVZ21generate_random_floatvE9generador
	.comm	_ZGVZ21generate_random_floatvE9generador,8,8
	.local	_ZZ21generate_random_floatvE9generador
	.comm	_ZZ21generate_random_floatvE9generador,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353215
	.align 4
.LC3:
	.long	805306368
	.align 4
.LC4:
	.long	1065353216
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC5:
	.long	-1598689907
	.long	1051772663
	.align 8
.LC9:
	.long	0
	.long	1074266112
	.align 8
.LC10:
	.long	0
	.long	1075052544
	.align 8
.LC11:
	.long	0
	.long	1077411840
	.section	.rodata.cst4
	.align 4
.LC12:
	.long	981467136
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <fstream>
#include <string.h>
#include <sys/time.h>
#include <math.h>
#include <random>

#include <hip/hip_runtime.h>


using namespace std;

#define BLOCKSIZE 1024
#define FLOAT_MIN 10
#define FLOAT_MAX 100

#define GPU_ERR_CHK(ans)                      \
    {                                         \
        gpuAssert((ans), __FILE__, __LINE__); \
    }

/**
 * @brief Comprueba el codigo de error de una llamada Cuda
 * @param code Codigo del error
 * @param file Archivo donde se produjo el error
 * @param line Linea que ha dado el error
 * @param abort Indica si debe abortar el programa ante el error. True por defecto
*/
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
    if (code != hipSuccess)
    {
        fprintf(stderr, "GPU assert: %s %s %d\n", hipGetErrorString(code), file, line);
        if (abort)
            exit(code);
    }
}

/**
 * @brief Desenrrollado de bucle del ultimo warp de cada bloque
 * @param sdata Puntero a memoria compartida de device
 * @param tid Identificador de hebra de GPU
 * @post sdata es modificado
*/
__device__ void warpReduce(volatile float *sdata, int tid)
{
    sdata[tid] = (sdata[tid] > sdata[tid + 32]) ? sdata[tid] : sdata[tid + 32];
    sdata[tid] = (sdata[tid] > sdata[tid + 16]) ? sdata[tid] : sdata[tid + 16];
    sdata[tid] = (sdata[tid] > sdata[tid + 8]) ? sdata[tid] : sdata[tid + 8];
    sdata[tid] = (sdata[tid] > sdata[tid + 4]) ? sdata[tid] : sdata[tid + 4];
    sdata[tid] = (sdata[tid] > sdata[tid + 2]) ? sdata[tid] : sdata[tid + 2];
    sdata[tid] = (sdata[tid] > sdata[tid + 1]) ? sdata[tid] : sdata[tid + 1];
}

/**
 * @brief Kernel para la reduccion
 * @param Min Vector a reducir
 * @param Mout Resultado de la reduccion
 * @note La reduccion se hace por bloques usando memoria compartida
 * por lo que el vector de salida no esta reducido completamente
*/
__global__ void reduce_max(float *Min, float *Mout, const int nverts)
{
    extern __shared__ float sdata[];

    // Cada hebra carga un elemento a memoria compartida
    int tid = threadIdx.x;
    int i = blockIdx.x * blockDim.x + threadIdx.x;

    // Primera reduccion antes de cargar en memoria compartida
    sdata[tid] = (Min[i] > Min[i + blockDim.x]) ? Min[i] : Min[i + blockDim.x];
    __syncthreads();

    // Hacer reduccion en memoria compartida
    for (int s = blockDim.x / 2; s > 32; s >>= 1)
    {
        if (tid < s)
            sdata[tid] = (sdata[tid] > sdata[tid + s]) ? sdata[tid] : sdata[tid + s];
        __syncthreads();
    }

    if (tid < 32)
        warpReduce(sdata, tid);

    if (tid == 0)
        Mout[blockIdx.x] = sdata[0];
}

/**
 * @brief Kernel que calcula el vector B del problema
 * @param B_in Vector con los datos de entrada
 * @param N Tamaño del vector
 * @note Esta version hace uso de memoria compartida
*/
__global__ void calcula_B_shared(float *B_in, int N)
{
    extern __shared__ float sdata[];

    float A_im2, A_im1, A_i, A_ip1, A_ip2;
    int tid = threadIdx.x;
    int i = blockIdx.x * blockDim.x + threadIdx.x;

    if (i < N)
    {
        sdata[tid] = B_in[i];
        //__syncthreads(); // Esperar a que las hebras carguen en memoria compartida

        A_im2 = (i - 2 < 0) ? 0.0 : B_in[i - 2];
        A_im1 = (i - 1 < 0) ? 0.0 : B_in[i - 1];
        A_i = B_in[i];
        A_ip1 = (i + 1 > N) ? 0.0 : B_in[i + 1];
        A_ip2 = (i + 2 > N) ? 0.0 : B_in[i + 2];

        sdata[tid] = (pow(A_im2, 2) + 2 * pow(A_im1, 2) + pow(A_i, 2) - 3 * pow(A_ip1, 2) + 5 * pow(A_ip2, 2)) / 24.0;
    }

    // Copiar de memoria compartida a salida
    if (tid == 0)
    {
        int offset = blockIdx.x * blockDim.x;
        int posicion;

        for (int i = 0; i < blockDim.x; i++)
        {
            posicion = offset + i;

            if (posicion < N) // Necesario por las hebras que sobran
                B_in[posicion] = sdata[i];
        }
    }
}

/**
 * @brief Kernel que calcula el vector B del problema
 * @param B_in Vector con los datos de entrada
 * @param B_out Vector con los datos de salida
 * @param N Tamaño del vector
 * @note Esta version no hace uso de memoria compartida
*/
__global__ void calcula_B(float *B_in, float *B_out, int N)
{
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    float A_im2, A_im1, A_i, A_ip1, A_ip2;

    if (i < N)
    {
        A_im2 = (i - 2 < 0) ? 0.0 : B_in[i - 2];
        A_im1 = (i - 1 < 0) ? 0.0 : B_in[i - 1];
        A_i = B_in[i];
        A_ip1 = (i + 1 > N) ? 0.0 : B_in[i + 1];
        A_ip2 = (i + 2 > N) ? 0.0 : B_in[i + 2];

        B_out[i] = (pow(A_im2, 2) + 2 * pow(A_im1, 2) + pow(A_i, 2) - 3 * pow(A_ip1, 2) + 5 * pow(A_ip2, 2)) / 24.0;
    }
}

/**
 * @brief Genera número aleatorio
 * @note cambiar valores de macros 
 * para mayor o menor rango
*/
float generate_random_float()
{
    static default_random_engine generador;
    static uniform_real_distribution<float> distribucion_uniforme(FLOAT_MIN, FLOAT_MAX);
    return distribucion_uniforme(generador);
}

/**
 * @brief Calcula un instante de tiempo
 * @return Instante de tiempo
*/
double cpuSecond()
{
    struct timeval tp;
    gettimeofday(&tp, NULL);
    return ((double)tp.tv_sec + (double)tp.tv_usec * 1e-6);
}

int main(int argc, char const *argv[])
{
    // Get GPU information
    int dev_id;
    int num_val;
    hipDeviceProp_t props;

    GPU_ERR_CHK(hipGetDevice(&dev_id));

    hipGetDeviceProperties(&props, dev_id);

    printf("Device %d: \"%s\" with Compute %d.%d capability\n",
           dev_id, props.name, props.major, props.minor);

    cout << "Introduce numero de valores: ";
    cin >> num_val;

    //****************************
    // Inicializamos vector A
    //****************************
    float *A = new float[num_val]; //  Vector de entrada A

    for (int i = 0; i < num_val; i++)
        A[i] = generate_random_float();

    //****************************
    // Calculamos vector B en CPU
    //****************************
    float *B = new float[num_val];

    float A_im2, A_im1, A_i, A_ip1, A_ip2;

    double t_cpu_inicial = cpuSecond();

    for (int i = 0; i < num_val; i++)
    {
        A_im2 = (i - 2 < 0) ? 0.0 : A[i - 2];
        A_im1 = (i - 1 < 0) ? 0.0 : A[i - 1];
        A_i = A[i];
        A_ip1 = (i + 1 > num_val) ? 0.0 : A[i + 1];
        A_ip2 = (i + 2 > num_val) ? 0.0 : A[i + 2];
        B[i] = (pow(A_im2, 2) + 2 * pow(A_im1, 2) + pow(A_i, 2) - 3 * pow(A_ip1, 2) + 5 * pow(A_ip2, 2)) / 24.0;
    }

    double t_cpu_final = cpuSecond();
    double t_cpu = t_cpu_final - t_cpu_inicial;

    //*****************************************************
    // Calculamos vector B en GPU (sin memoria compartida)
    //*****************************************************
    float *d_A, *d_b;
    float *h_b = new float[num_val];

    GPU_ERR_CHK(hipMalloc((void **)&d_A, num_val * sizeof(float)));
    GPU_ERR_CHK(hipMalloc((void **)&d_b, num_val * sizeof(float)));
    GPU_ERR_CHK(hipMemcpy(d_A, A, num_val * sizeof(float), hipMemcpyHostToDevice));

    int blocks_per_grid = ceil((float)num_val / (float)BLOCKSIZE);

    double t_gpu_inicial_1 = cpuSecond();
    calcula_B<<<blocks_per_grid, BLOCKSIZE>>>(d_A, d_b, num_val);
    GPU_ERR_CHK(hipDeviceSynchronize());
    double t_gpu_final_1 = cpuSecond();

    GPU_ERR_CHK(hipGetLastError());
    GPU_ERR_CHK(hipMemcpy(h_b, d_b, num_val * sizeof(float), hipMemcpyDeviceToHost));
    GPU_ERR_CHK(hipDeviceSynchronize());

    double t_gpu_1 = t_gpu_final_1 - t_gpu_inicial_1;

    //*****************************************************
    // Calculamos vector B en GPU (con memoria compartida)
    //*****************************************************
    float *d_c;
    float *h_c = new float[num_val];
    int shared_mem_size = BLOCKSIZE * sizeof(float);

    GPU_ERR_CHK(hipMalloc((void **)&d_c, num_val * sizeof(float)));
    GPU_ERR_CHK(hipMemcpy(d_c, A, num_val * sizeof(float), hipMemcpyHostToDevice));

    double t_gpu_inicial_2 = cpuSecond();
    calcula_B_shared<<<blocks_per_grid, BLOCKSIZE, shared_mem_size>>>(d_c, num_val);
    GPU_ERR_CHK(hipDeviceSynchronize());
    double t_gpu_final_2 = cpuSecond();

    GPU_ERR_CHK(hipGetLastError());
    GPU_ERR_CHK(hipMemcpy(h_c, d_c, num_val * sizeof(float), hipMemcpyDeviceToHost));
    GPU_ERR_CHK(hipDeviceSynchronize());

    double t_gpu_2 = t_gpu_final_2 - t_gpu_inicial_2;

    //******************
    // Reduccion en CPU
    //******************
    double t_red_cpu_ini = cpuSecond();

    float mayor_cpu = B[0];

    for (int i = 1; i < num_val; i++)
    {
        mayor_cpu = (B[i] > mayor_cpu) ? B[i] : mayor_cpu;
    }

    double t_red_cpu_fin = cpuSecond();
    double t_red_cpu = t_red_cpu_fin - t_red_cpu_ini;

    //******************
    // Reduccion en GPU
    //******************
    float *d_d, *d_e;                        // Parametros de entrada del kernel
    float *h_d = new float[blocks_per_grid]; // Salida del kernel en el host

    GPU_ERR_CHK(hipMalloc((void **)&d_d, num_val * sizeof(float)));
    GPU_ERR_CHK(hipMalloc((void **)&d_e, blocks_per_grid * sizeof(float)));
    GPU_ERR_CHK(hipMemcpy(d_d, B, num_val * sizeof(float), hipMemcpyHostToDevice));

    double t_gpu_inicial_3 = cpuSecond();
    reduce_max<<<blocks_per_grid, BLOCKSIZE, shared_mem_size>>>(d_d, d_e, num_val);
    GPU_ERR_CHK(hipDeviceSynchronize());
    double t_gpu_final_3 = cpuSecond();

    GPU_ERR_CHK(hipGetLastError());
    GPU_ERR_CHK(hipMemcpy(h_d, d_e, blocks_per_grid * sizeof(float), hipMemcpyDeviceToHost));
    GPU_ERR_CHK(hipDeviceSynchronize());

    float mayor_gpu = h_d[0];

    for (int i = 1; i < blocks_per_grid; i++)
    {
        mayor_gpu = (h_d[i] > mayor_gpu) ? h_d[i] : mayor_gpu;
    }

    double t_red_gpu = t_gpu_final_3 - t_gpu_inicial_3;

    //****************************
    // Comprobacion CPU-GPU
    //****************************
    bool passed = true;
    int i = 0;

    while (passed && i < num_val)
    {
        if (B[i] != h_b[i] && B[i] != h_c[i])
        {
            cout << "ERR B[" << i << "] = " << B[i]
                 << " h_b[" << i << "] = " << h_b[i]
                 << " h_c[" << i << "] = " << h_c[i]
                 << endl;
            passed = false;
        }
        i++;
    }

    if (passed)
        cout << "PASSED TEST" << endl;
    else
        cout << "ERROR IN TEST" << endl;

    //********************
    // Mostrar resultados
    //********************
    cout << "Tiempo en CPU = " << t_cpu << endl
         << "Tiempo en GPU (sin memoria compartida) = " << t_gpu_1 << endl
         << "Tiempo en GPU (con memoria compartida) = " << t_gpu_2 << endl
         << "Ganancia (sin memoria compartida) = " << t_cpu / t_gpu_1 << endl
         << "Ganancia (con memoria compartida) = " << t_cpu / t_gpu_2 << endl
         << "Tiempo de reduccion en CPU = " << t_red_cpu << endl
         << "Tiempo de reduccion en GPU = " << t_red_gpu << endl
         << "Valor de reduccion en CPU = " << mayor_cpu << endl
         << "Valor de reduccion en GPU = " << mayor_gpu << endl;

    // Liberar memoria host
    delete (A);
    delete (B);
    delete (h_b);
    delete (h_c);
    delete (h_d);

    // Liberar memoria device
    hipFree(d_A);
    hipFree(d_b);
    hipFree(d_c);
    hipFree(d_d);
    hipFree(d_e);

    return 0;
}

	.text
	.file	"op_vectorial.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__reduce_maxPfS_i # -- Begin function _Z25__device_stub__reduce_maxPfS_i
	.type	_Z25__device_stub__reduce_maxPfS_i,@function
_Z25__device_stub__reduce_maxPfS_i:     # @_Z25__device_stub__reduce_maxPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10reduce_maxPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__reduce_maxPfS_i, .Lfunc_end0-_Z25__device_stub__reduce_maxPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__calcula_B_sharedPfi # -- Begin function _Z31__device_stub__calcula_B_sharedPfi
	.type	_Z31__device_stub__calcula_B_sharedPfi,@function
_Z31__device_stub__calcula_B_sharedPfi: # @_Z31__device_stub__calcula_B_sharedPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16calcula_B_sharedPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__calcula_B_sharedPfi, .Lfunc_end1-_Z31__device_stub__calcula_B_sharedPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__calcula_BPfS_i # -- Begin function _Z24__device_stub__calcula_BPfS_i
	.type	_Z24__device_stub__calcula_BPfS_i,@function
_Z24__device_stub__calcula_BPfS_i:      # @_Z24__device_stub__calcula_BPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9calcula_BPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__calcula_BPfS_i, .Lfunc_end2-_Z24__device_stub__calcula_BPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z21generate_random_floatv      # -- Begin function _Z21generate_random_floatv
	.type	_Z21generate_random_floatv,@function
_Z21generate_random_floatv:             # @_Z21generate_random_floatv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movb	_ZGVZ21generate_random_floatvE9generador(%rip), %al
	testb	%al, %al
	je	.LBB3_1
.LBB3_3:
	movb	_ZGVZ21generate_random_floatvE21distribucion_uniforme(%rip), %al
	testb	%al, %al
	je	.LBB3_4
.LBB3_6:
	movl	$_ZZ21generate_random_floatvE9generador, %edi
	callq	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
	movss	_ZZ21generate_random_floatvE21distribucion_uniforme.1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
	movss	_ZZ21generate_random_floatvE21distribucion_uniforme.0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
	subss	%xmm2, %xmm1
	mulss	%xmm1, %xmm0
	addss	%xmm2, %xmm0
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.LBB3_1:
	.cfi_def_cfa_offset 16
	movl	$_ZGVZ21generate_random_floatvE9generador, %edi
	callq	__cxa_guard_acquire
	testl	%eax, %eax
	je	.LBB3_3
# %bb.2:
	movq	$1, _ZZ21generate_random_floatvE9generador(%rip)
	movl	$_ZGVZ21generate_random_floatvE9generador, %edi
	callq	__cxa_guard_release
	jmp	.LBB3_3
.LBB3_4:
	movl	$_ZGVZ21generate_random_floatvE21distribucion_uniforme, %edi
	callq	__cxa_guard_acquire
	testl	%eax, %eax
	je	.LBB3_6
# %bb.5:
	movl	$1092616192, _ZZ21generate_random_floatvE21distribucion_uniforme.0(%rip) # imm = 0x41200000
	movl	$1120403456, _ZZ21generate_random_floatvE21distribucion_uniforme.1(%rip) # imm = 0x42C80000
	movl	$_ZGVZ21generate_random_floatvE21distribucion_uniforme, %edi
	callq	__cxa_guard_release
	jmp	.LBB3_6
.Lfunc_end3:
	.size	_Z21generate_random_floatv, .Lfunc_end3-_Z21generate_random_floatv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9cpuSecondv
.LCPI4_0:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.text
	.globl	_Z9cpuSecondv
	.type	_Z9cpuSecondv,@function
_Z9cpuSecondv:                          # @_Z9cpuSecondv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movq	%rsp, %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cvtsi2sdq	(%rbx), %xmm1
	cvtsi2sdq	8(%rbx), %xmm0
	mulsd	.LCPI4_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z9cpuSecondv, .Lfunc_end4-_Z9cpuSecondv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0xc008000000000000              # double -3
.LCPI5_1:
	.quad	0x4014000000000000              # double 5
.LCPI5_2:
	.quad	0x4038000000000000              # double 24
.LCPI5_4:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI5_3:
	.long	0x3a800000                      # float 9.765625E-4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1736, %rsp                     # imm = 0x6C8
	.cfi_def_cfa_offset 1792
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	36(%rsp), %rdi
	callq	hipGetDevice
	testl	%eax, %eax
	jne	.LBB5_78
# %bb.1:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movl	36(%rsp), %esi
	leaq	264(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDevicePropertiesR0600
	movl	36(%rsp), %esi
	movl	360(%rbx), %ecx
	movl	364(%rbx), %r8d
	movl	$.L.str.1, %edi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$29, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	12(%rsp), %rbx
	movl	$_ZSt3cin, %edi
	movq	%rbx, %rsi
	callq	_ZNSirsERi
	movslq	(%rbx), %r12
	leaq	(,%r12,4), %r14
	testq	%r12, %r12
	movq	$-1, %r15
	movq	%r14, %rdi
	cmovsq	%r15, %rdi
	callq	_Znam
	movq	%rax, %rbx
	testq	%r12, %r12
	jle	.LBB5_5
# %bb.2:                                # %.lr.ph.preheader
	xorl	%r13d, %r13d
.LBB5_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	_Z21generate_random_floatv
	movss	%xmm0, (%rbx,%r13,4)
	incq	%r13
	movl	12(%rsp), %r12d
	movslq	%r12d, %r14
	cmpq	%r14, %r13
	jl	.LBB5_3
# %bb.4:                                # %._crit_edge.loopexit
	shlq	$2, %r14
.LBB5_5:                                # %._crit_edge
	testl	%r12d, %r12d
	cmovsq	%r15, %r14
	movq	%r14, %rdi
	callq	_Znam
	movq	%rax, %r14
	leaq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	12(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB5_9
# %bb.6:                                # %.lr.ph199.preheader
	xorl	%ecx, %ecx
	movsd	.LCPI5_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	.LCPI5_1(%rip), %xmm1           # xmm1 = mem[0],zero
	movsd	.LCPI5_2(%rip), %xmm2           # xmm2 = mem[0],zero
.LBB5_7:                                # %.lr.ph199
                                        # =>This Inner Loop Header: Depth=1
	cmpq	$2, %rcx
	jae	.LBB5_8
# %bb.16:                               #   in Loop: Header=BB5_7 Depth=1
	xorps	%xmm3, %xmm3
	xorps	%xmm5, %xmm5
	testq	%rcx, %rcx
	jne	.LBB5_17
	jmp	.LBB5_18
.LBB5_8:                                # %.thread
                                        #   in Loop: Header=BB5_7 Depth=1
	movss	-8(%rbx,%rcx,4), %xmm3          # xmm3 = mem[0],zero,zero,zero
.LBB5_17:                               #   in Loop: Header=BB5_7 Depth=1
	movss	-4(%rbx,%rcx,4), %xmm5          # xmm5 = mem[0],zero,zero,zero
.LBB5_18:                               #   in Loop: Header=BB5_7 Depth=1
	leal	2(%rcx), %edx
	xorps	%xmm4, %xmm4
	cmpl	%edx, %eax
	jl	.LBB5_20
# %bb.19:                               #   in Loop: Header=BB5_7 Depth=1
	movss	8(%rbx,%rcx,4), %xmm4           # xmm4 = mem[0],zero,zero,zero
.LBB5_20:                               #   in Loop: Header=BB5_7 Depth=1
	cvtss2sd	%xmm3, %xmm3
	mulsd	%xmm3, %xmm3
	cvtss2sd	%xmm5, %xmm5
	mulsd	%xmm5, %xmm5
	addsd	%xmm5, %xmm5
	addsd	%xmm3, %xmm5
	xorps	%xmm3, %xmm3
	cvtss2sd	(%rbx,%rcx,4), %xmm3
	mulsd	%xmm3, %xmm3
	addsd	%xmm5, %xmm3
	xorps	%xmm5, %xmm5
	cvtss2sd	4(%rbx,%rcx,4), %xmm5
	mulsd	%xmm5, %xmm5
	mulsd	%xmm0, %xmm5
	addsd	%xmm3, %xmm5
	xorps	%xmm3, %xmm3
	cvtss2sd	%xmm4, %xmm3
	mulsd	%xmm3, %xmm3
	mulsd	%xmm1, %xmm3
	addsd	%xmm5, %xmm3
	divsd	%xmm2, %xmm3
	cvtsd2ss	%xmm3, %xmm3
	movss	%xmm3, (%r14,%rcx,4)
	leaq	1(%rcx), %rdx
	movq	%rdx, %rcx
	cmpq	%rdx, %rax
	jne	.LBB5_7
.LBB5_9:                                # %._crit_edge200
	leaq	56(%rsp), %r15
	movq	(%r15), %r13
	movq	8(%r15), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r15), %rax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	8(%r15), %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movslq	12(%rsp), %rax
	leaq	(,%rax,4), %r12
	testq	%rax, %rax
	movq	$-1, %rdi
	cmovnsq	%r12, %rdi
	callq	_Znam
	movq	%rax, %r15
	leaq	112(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.12:                               # %_Z9gpuAssert10hipError_tPKcib.exit135
	movslq	12(%rsp), %rsi
	shlq	$2, %rsi
	leaq	104(%rsp), %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_13
# %bb.14:                               # %_Z9gpuAssert10hipError_tPKcib.exit137
	movq	%r15, 128(%rsp)                 # 8-byte Spill
	movq	112(%rsp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_15
# %bb.21:                               # %_Z9gpuAssert10hipError_tPKcib.exit139
	xorps	%xmm0, %xmm0
	cvtsi2ssl	12(%rsp), %xmm0
	movabsq	$4294968320, %rbp               # imm = 0x100000400
	mulss	.LCPI5_3(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r15d
	leaq	56(%rsp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r12), %rax
	movq	%rax, 256(%rsp)                 # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 248(%rsp)                 # 8-byte Spill
	leaq	-1024(%r15,%rbp), %rdi
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_23
# %bb.22:
	movq	112(%rsp), %rdi
	movq	104(%rsp), %rsi
	movl	12(%rsp), %edx
	callq	_Z24__device_stub__calcula_BPfS_i
.LBB5_23:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_24
# %bb.26:                               # %_Z9gpuAssert10hipError_tPKcib.exit141
	leaq	56(%rsp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r12), %rax
	movq	%rax, 240(%rsp)                 # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 232(%rsp)                 # 8-byte Spill
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB5_27
# %bb.28:                               # %_Z9gpuAssert10hipError_tPKcib.exit143
	movq	104(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	128(%rsp), %rdi                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_29
# %bb.30:                               # %_Z9gpuAssert10hipError_tPKcib.exit145
	movq	%r13, 224(%rsp)                 # 8-byte Spill
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_31
# %bb.32:                               # %_Z9gpuAssert10hipError_tPKcib.exit147
	movslq	12(%rsp), %rax
	leaq	(,%rax,4), %r12
	testq	%rax, %rax
	movq	$-1, %rdi
	cmovnsq	%r12, %rdi
	callq	_Znam
	movq	%rax, %r13
	leaq	48(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_33
# %bb.34:                               # %_Z9gpuAssert10hipError_tPKcib.exit149
	movq	48(%rsp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_35
# %bb.36:                               # %_Z9gpuAssert10hipError_tPKcib.exit151
	leaq	56(%rsp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r12), %rax
	movq	%rax, 216(%rsp)                 # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 208(%rsp)                 # 8-byte Spill
	movl	$4096, %r8d                     # imm = 0x1000
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_38
# %bb.37:
	movq	48(%rsp), %rdi
	movl	12(%rsp), %esi
	callq	_Z31__device_stub__calcula_B_sharedPfi
.LBB5_38:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_39
# %bb.40:                               # %_Z9gpuAssert10hipError_tPKcib.exit153
	leaq	56(%rsp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r12), %rax
	movq	%rax, 200(%rsp)                 # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 192(%rsp)                 # 8-byte Spill
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB5_41
# %bb.42:                               # %_Z9gpuAssert10hipError_tPKcib.exit155
	movq	48(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_43
# %bb.44:                               # %_Z9gpuAssert10hipError_tPKcib.exit157
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_45
# %bb.46:                               # %_Z9gpuAssert10hipError_tPKcib.exit159
	leaq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movss	(%r14), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movl	12(%rsp), %eax
	cmpl	$2, %eax
	movq	%r13, 24(%rsp)                  # 8-byte Spill
	jl	.LBB5_47
# %bb.54:                               # %.lr.ph203.preheader
	movl	$1, %ecx
.LBB5_55:                               # %.lr.ph203
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r14,%rcx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	maxss	%xmm0, %xmm1
	incq	%rcx
	movaps	%xmm1, %xmm0
	cmpq	%rcx, %rax
	jne	.LBB5_55
	jmp	.LBB5_48
.LBB5_47:
	movaps	%xmm0, %xmm1
.LBB5_48:                               # %._crit_edge204
	movss	%xmm1, 124(%rsp)                # 4-byte Spill
	leaq	56(%rsp), %r12
	movq	(%r12), %rax
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 176(%rsp)                 # 8-byte Spill
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r12), %rax
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	movslq	%r15d, %rax
	leaq	(,%rax,4), %r12
	testl	%eax, %eax
	movq	$-1, %rdi
	cmovnsq	%r12, %rdi
	callq	_Znam
	movq	%rax, %r13
	movslq	12(%rsp), %rsi
	shlq	$2, %rsi
	leaq	96(%rsp), %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_49
# %bb.50:                               # %_Z9gpuAssert10hipError_tPKcib.exit161
	leaq	88(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_51
# %bb.52:                               # %_Z9gpuAssert10hipError_tPKcib.exit163
	movq	96(%rsp), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_53
# %bb.56:                               # %_Z9gpuAssert10hipError_tPKcib.exit165
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%rbp), %rax
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	movq	8(%rbp), %rax
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movl	$4096, %r8d                     # imm = 0x1000
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_58
# %bb.57:
	movq	96(%rsp), %rdi
	movq	88(%rsp), %rsi
	movl	12(%rsp), %edx
	callq	_Z25__device_stub__reduce_maxPfS_i
.LBB5_58:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_59
# %bb.60:                               # %_Z9gpuAssert10hipError_tPKcib.exit167
	leaq	56(%rsp), %rbp
	movq	%rbp, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%rbp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	8(%rbp), %rax
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB5_61
# %bb.62:                               # %_Z9gpuAssert10hipError_tPKcib.exit169
	movq	88(%rsp), %rsi
	movq	%r13, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB5_63
# %bb.64:                               # %_Z9gpuAssert10hipError_tPKcib.exit171
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_65
# %bb.66:                               # %_Z9gpuAssert10hipError_tPKcib.exit173
	movss	(%r13), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	cmpl	$2, %r15d
	jl	.LBB5_67
# %bb.73:                               # %.lr.ph208.preheader
	movl	$1, %eax
	movq	24(%rsp), %rbp                  # 8-byte Reload
.LBB5_74:                               # %.lr.ph208
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r13,%rax,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	maxss	%xmm0, %xmm1
	incq	%rax
	movaps	%xmm1, %xmm0
	cmpq	%rax, %r15
	jne	.LBB5_74
	jmp	.LBB5_68
.LBB5_67:
	movaps	%xmm0, %xmm1
	movq	24(%rsp), %rbp                  # 8-byte Reload
.LBB5_68:                               # %.preheader
	movl	12(%rsp), %eax
	testl	%eax, %eax
	movq	128(%rsp), %r15                 # 8-byte Reload
	movss	%xmm1, 120(%rsp)                # 4-byte Spill
	jle	.LBB5_76
# %bb.69:                               # %.lr.ph212.preheader
	xorl	%r12d, %r12d
.LBB5_70:                               # %.lr.ph212
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r14,%r12,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%r15,%r12,4), %xmm0
	jne	.LBB5_71
	jnp	.LBB5_75
.LBB5_71:                               #   in Loop: Header=BB5_70 Depth=1
	ucomiss	(%rbp,%r12,4), %xmm0
	jne	.LBB5_72
	jp	.LBB5_72
.LBB5_75:                               #   in Loop: Header=BB5_70 Depth=1
	incq	%r12
	cmpq	%rax, %r12
	jb	.LBB5_70
.LBB5_76:                               # %.critedge
	movl	$_ZSt4cout, %edi
	movl	$.L.str.7, %esi
	movl	$11, %edx
	jmp	.LBB5_77
.LBB5_72:                               # %._crit_edge213.thread
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$6, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movl	$.L.str.4, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r12,4), %xmm0
	movq	%rbp, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbp
	movl	$.L.str.5, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbp, %rdi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movl	$.L.str.4, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r12,4), %xmm0
	movq	%rbp, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbp
	movl	$.L.str.6, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbp, %rdi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movl	$.L.str.4, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	24(%rsp), %rax                  # 8-byte Reload
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r12,4), %xmm0
	movq	%rbp, %rdi
	movq	24(%rsp), %rbp                  # 8-byte Reload
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.8, %esi
	movl	$13, %edx
.LBB5_77:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorps	%xmm0, %xmm0
	cvtsi2sdq	136(%rsp), %xmm0        # 8-byte Folded Reload
	cvtsi2sdq	16(%rsp), %xmm13        # 8-byte Folded Reload
	xorps	%xmm1, %xmm1
	cvtsi2sdq	144(%rsp), %xmm1        # 8-byte Folded Reload
	cvtsi2sdq	152(%rsp), %xmm2        # 8-byte Folded Reload
	cvtsi2sdq	160(%rsp), %xmm3        # 8-byte Folded Reload
	cvtsi2sdq	168(%rsp), %xmm14       # 8-byte Folded Reload
	cvtsi2sdq	176(%rsp), %xmm5        # 8-byte Folded Reload
	cvtsi2sdq	184(%rsp), %xmm4        # 8-byte Folded Reload
	cvtsi2sdq	192(%rsp), %xmm6        # 8-byte Folded Reload
	cvtsi2sdq	200(%rsp), %xmm15       # 8-byte Folded Reload
	cvtsi2sdq	208(%rsp), %xmm7        # 8-byte Folded Reload
	cvtsi2sdq	216(%rsp), %xmm8        # 8-byte Folded Reload
	cvtsi2sdq	232(%rsp), %xmm9        # 8-byte Folded Reload
	cvtsi2sdq	240(%rsp), %xmm10       # 8-byte Folded Reload
	movsd	%xmm10, 16(%rsp)                # 8-byte Spill
	cvtsi2sdq	248(%rsp), %xmm11       # 8-byte Folded Reload
	movsd	.LCPI5_4(%rip), %xmm10          # xmm10 = mem[0],zero
	mulsd	%xmm10, %xmm0
	cvtsi2sdq	256(%rsp), %xmm12       # 8-byte Folded Reload
	addsd	%xmm0, %xmm13
	mulsd	%xmm10, %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2sdq	72(%rsp), %xmm0         # 8-byte Folded Reload
	addsd	%xmm1, %xmm2
	subsd	%xmm2, %xmm13
	movsd	%xmm13, 72(%rsp)                # 8-byte Spill
	xorps	%xmm13, %xmm13
	cvtsi2sdq	80(%rsp), %xmm13        # 8-byte Folded Reload
	mulsd	%xmm10, %xmm3
	addsd	%xmm3, %xmm14
	xorps	%xmm1, %xmm1
	cvtsi2sdq	40(%rsp), %xmm1         # 8-byte Folded Reload
	mulsd	%xmm10, %xmm5
	addsd	%xmm5, %xmm4
	xorps	%xmm2, %xmm2
	cvtsi2sdq	224(%rsp), %xmm2        # 8-byte Folded Reload
	subsd	%xmm4, %xmm14
	movsd	%xmm14, 80(%rsp)                # 8-byte Spill
	mulsd	%xmm10, %xmm6
	addsd	%xmm6, %xmm15
	mulsd	%xmm10, %xmm7
	addsd	%xmm7, %xmm8
	subsd	%xmm8, %xmm15
	movsd	%xmm15, 40(%rsp)                # 8-byte Spill
	mulsd	%xmm10, %xmm9
	movsd	16(%rsp), %xmm3                 # 8-byte Reload
                                        # xmm3 = mem[0],zero
	addsd	%xmm9, %xmm3
	mulsd	%xmm10, %xmm11
	addsd	%xmm11, %xmm12
	subsd	%xmm12, %xmm3
	movsd	%xmm3, 16(%rsp)                 # 8-byte Spill
	mulsd	%xmm10, %xmm0
	addsd	%xmm0, %xmm13
	mulsd	%xmm10, %xmm1
	addsd	%xmm1, %xmm2
	subsd	%xmm2, %xmm13
	movsd	%xmm13, 24(%rsp)                # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$16, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.10, %esi
	movl	$41, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.11, %esi
	movl	$41, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movsd	40(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.12, %esi
	movl	$36, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	16(%rsp), %xmm0                 # 8-byte Folded Reload
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.13, %esi
	movl	$36, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	40(%rsp), %xmm0                 # 8-byte Folded Reload
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.14, %esi
	movl	$29, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movsd	80(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.15, %esi
	movl	$29, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movsd	72(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.16, %esi
	movl	$28, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	124(%rsp), %xmm0                # 4-byte Folded Reload
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.17, %esi
	movl	$28, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	120(%rsp), %xmm0                # 4-byte Folded Reload
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rbx, %rdi
	callq	_ZdlPv
	movq	%r14, %rdi
	callq	_ZdlPv
	movq	%r15, %rdi
	callq	_ZdlPv
	movq	%rbp, %rdi
	callq	_ZdlPv
	movq	%r13, %rdi
	callq	_ZdlPv
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$1736, %rsp                     # imm = 0x6C8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_78:
	.cfi_def_cfa_offset 1792
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$187, %r8d
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.LBB5_10:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$233, %r8d
	jmp	.LBB5_11
.LBB5_13:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$234, %r8d
	jmp	.LBB5_11
.LBB5_15:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$235, %r8d
	jmp	.LBB5_11
.LBB5_24:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$241, %r8d
	jmp	.LBB5_25
.LBB5_27:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$244, %r8d
	jmp	.LBB5_25
.LBB5_29:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$245, %r8d
	jmp	.LBB5_25
.LBB5_31:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$246, %r8d
	jmp	.LBB5_25
.LBB5_33:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$257, %r8d                      # imm = 0x101
	jmp	.LBB5_25
.LBB5_35:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$258, %r8d                      # imm = 0x102
	jmp	.LBB5_25
.LBB5_39:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$262, %r8d                      # imm = 0x106
	jmp	.LBB5_25
.LBB5_41:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$265, %r8d                      # imm = 0x109
	jmp	.LBB5_25
.LBB5_43:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$266, %r8d                      # imm = 0x10A
	jmp	.LBB5_25
.LBB5_45:
	movl	%eax, %r12d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$267, %r8d                      # imm = 0x10B
.LBB5_25:
	xorl	%eax, %eax
	callq	fprintf
	movl	%r12d, %edi
	callq	exit
.LBB5_49:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$292, %r8d                      # imm = 0x124
	jmp	.LBB5_11
.LBB5_51:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$293, %r8d                      # imm = 0x125
	jmp	.LBB5_11
.LBB5_53:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$294, %r8d                      # imm = 0x126
	jmp	.LBB5_11
.LBB5_59:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$298, %r8d                      # imm = 0x12A
	jmp	.LBB5_11
.LBB5_61:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$301, %r8d                      # imm = 0x12D
	jmp	.LBB5_11
.LBB5_63:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$302, %r8d                      # imm = 0x12E
	jmp	.LBB5_11
.LBB5_65:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.18, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$303, %r8d                      # imm = 0x12F
.LBB5_11:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
.LCPI6_0:
	.quad	0x41dfffffff800000              # double 2147483646
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI6_1:
	.long	0x40000000                      # float 2
.LCPI6_2:
	.long	0x5f000000                      # float 9.22337203E+18
.LCPI6_3:
	.long	0x3f800000                      # float 1
	.section	.text._ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,"axG",@progbits,_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,comdat
	.weak	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
	.type	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,@function
_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_: # @_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$64, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	fldl	.LCPI6_0(%rip)
	fstpt	(%rsp)
	callq	logl
	fstpt	52(%rsp)                        # 10-byte Folded Spill
	flds	.LCPI6_1(%rip)
	fstpt	(%rsp)
	callq	logl
	fldt	52(%rsp)                        # 10-byte Folded Reload
	fdivp	%st, %st(1)
	flds	.LCPI6_2(%rip)
	xorl	%ecx, %ecx
	fxch	%st(1)
	fucomi	%st(1), %st
	fldz
	fcmovnb	%st(2), %st
	fstp	%st(2)
	fsubp	%st, %st(1)
	setae	%cl
	fnstcw	28(%rsp)
	movzwl	28(%rsp), %eax
	orl	$3072, %eax                     # imm = 0xC00
	movw	%ax, 30(%rsp)
	fldcw	30(%rsp)
	fistpll	40(%rsp)
	fldcw	28(%rsp)
	shlq	$63, %rcx
	xorq	40(%rsp), %rcx
	leaq	23(%rcx), %rax
	xorl	%edx, %edx
	divq	%rcx
	movq	%rax, %rcx
	cmpq	$1, %rax
	adcq	$0, %rcx
	movq	(%rbx), %rsi
	xorps	%xmm0, %xmm0
	movss	.LCPI6_3(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movabsq	$8589934597, %rdi               # imm = 0x200000005
.LBB6_1:                                # %select.unfold
                                        # =>This Inner Loop Header: Depth=1
	imulq	$16807, %rsi, %rsi              # imm = 0x41A7
	movq	%rsi, %rax
	mulq	%rdi
	movq	%rsi, %rax
	subq	%rdx, %rax
	shrq	%rax
	addq	%rdx, %rax
	shrq	$30, %rax
	movq	%rax, %rdx
	shlq	$31, %rdx
	subq	%rdx, %rax
	leaq	(%rsi,%rax), %rdx
	decq	%rdx
	testq	%rdx, %rdx
	js	.LBB6_2
# %bb.3:                                # %select.unfold
                                        #   in Loop: Header=BB6_1 Depth=1
	xorps	%xmm2, %xmm2
	cvtsi2ss	%rdx, %xmm2
	jmp	.LBB6_4
.LBB6_2:                                #   in Loop: Header=BB6_1 Depth=1
	movq	%rdx, %r8
	shrq	%r8
	andl	$1, %edx
	orq	%r8, %rdx
	xorps	%xmm2, %xmm2
	cvtsi2ss	%rdx, %xmm2
	addss	%xmm2, %xmm2
.LBB6_4:                                # %select.unfold
                                        #   in Loop: Header=BB6_1 Depth=1
	addq	%rax, %rsi
	mulss	%xmm1, %xmm2
	movss	%xmm1, 36(%rsp)
	flds	36(%rsp)
	fmull	.LCPI6_0(%rip)
	addss	%xmm2, %xmm0
	fstps	32(%rsp)
	movss	32(%rsp), %xmm1                 # xmm1 = mem[0],zero,zero,zero
	decq	%rcx
	jne	.LBB6_1
# %bb.5:
	movq	%rsi, (%rbx)
	divss	%xmm1, %xmm0
	ucomiss	.LCPI6_3(%rip), %xmm0
	jae	.LBB6_7
# %bb.6:
	addq	$64, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB6_7:
	.cfi_def_cfa_offset 80
	movss	.LCPI6_3(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	xorps	%xmm1, %xmm1
	addq	$64, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	nextafterf                      # TAILCALL
.Lfunc_end6:
	.size	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_, .Lfunc_end6-_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10reduce_maxPfS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16calcula_B_sharedPfi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9calcula_BPfS_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10reduce_maxPfS_i,@object     # @_Z10reduce_maxPfS_i
	.section	.rodata,"a",@progbits
	.globl	_Z10reduce_maxPfS_i
	.p2align	3, 0x0
_Z10reduce_maxPfS_i:
	.quad	_Z25__device_stub__reduce_maxPfS_i
	.size	_Z10reduce_maxPfS_i, 8

	.type	_Z16calcula_B_sharedPfi,@object # @_Z16calcula_B_sharedPfi
	.globl	_Z16calcula_B_sharedPfi
	.p2align	3, 0x0
_Z16calcula_B_sharedPfi:
	.quad	_Z31__device_stub__calcula_B_sharedPfi
	.size	_Z16calcula_B_sharedPfi, 8

	.type	_Z9calcula_BPfS_i,@object       # @_Z9calcula_BPfS_i
	.globl	_Z9calcula_BPfS_i
	.p2align	3, 0x0
_Z9calcula_BPfS_i:
	.quad	_Z24__device_stub__calcula_BPfS_i
	.size	_Z9calcula_BPfS_i, 8

	.type	_ZZ21generate_random_floatvE9generador,@object # @_ZZ21generate_random_floatvE9generador
	.local	_ZZ21generate_random_floatvE9generador
	.comm	_ZZ21generate_random_floatvE9generador,8,8
	.type	_ZGVZ21generate_random_floatvE9generador,@object # @_ZGVZ21generate_random_floatvE9generador
	.local	_ZGVZ21generate_random_floatvE9generador
	.comm	_ZGVZ21generate_random_floatvE9generador,8,8
	.type	_ZZ21generate_random_floatvE21distribucion_uniforme.0,@object # @_ZZ21generate_random_floatvE21distribucion_uniforme.0
	.local	_ZZ21generate_random_floatvE21distribucion_uniforme.0
	.comm	_ZZ21generate_random_floatvE21distribucion_uniforme.0,4,4
	.type	_ZZ21generate_random_floatvE21distribucion_uniforme.1,@object # @_ZZ21generate_random_floatvE21distribucion_uniforme.1
	.local	_ZZ21generate_random_floatvE21distribucion_uniforme.1
	.comm	_ZZ21generate_random_floatvE21distribucion_uniforme.1,4,4
	.type	_ZGVZ21generate_random_floatvE21distribucion_uniforme,@object # @_ZGVZ21generate_random_floatvE21distribucion_uniforme
	.local	_ZGVZ21generate_random_floatvE21distribucion_uniforme
	.comm	_ZGVZ21generate_random_floatvE21distribucion_uniforme,8,8
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/pakejo/Practicas_PPR_UGR/main/P1/advection1d_code/op_vectorial.hip"
	.size	.L.str, 129

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Device %d: \"%s\" with Compute %d.%d capability\n"
	.size	.L.str.1, 47

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Introduce numero de valores: "
	.size	.L.str.2, 30

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"ERR B["
	.size	.L.str.3, 7

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"] = "
	.size	.L.str.4, 5

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	" h_b["
	.size	.L.str.5, 6

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	" h_c["
	.size	.L.str.6, 6

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"PASSED TEST"
	.size	.L.str.7, 12

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"ERROR IN TEST"
	.size	.L.str.8, 14

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Tiempo en CPU = "
	.size	.L.str.9, 17

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Tiempo en GPU (sin memoria compartida) = "
	.size	.L.str.10, 42

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Tiempo en GPU (con memoria compartida) = "
	.size	.L.str.11, 42

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Ganancia (sin memoria compartida) = "
	.size	.L.str.12, 37

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Ganancia (con memoria compartida) = "
	.size	.L.str.13, 37

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"Tiempo de reduccion en CPU = "
	.size	.L.str.14, 30

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"Tiempo de reduccion en GPU = "
	.size	.L.str.15, 30

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Valor de reduccion en CPU = "
	.size	.L.str.16, 29

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"Valor de reduccion en GPU = "
	.size	.L.str.17, 29

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"GPU assert: %s %s %d\n"
	.size	.L.str.18, 22

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10reduce_maxPfS_i"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16calcula_B_sharedPfi"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9calcula_BPfS_i"
	.size	.L__unnamed_3, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__reduce_maxPfS_i
	.addrsig_sym _Z31__device_stub__calcula_B_sharedPfi
	.addrsig_sym _Z24__device_stub__calcula_BPfS_i
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10reduce_maxPfS_i
	.addrsig_sym _Z16calcula_B_sharedPfi
	.addrsig_sym _Z9calcula_BPfS_i
	.addrsig_sym _ZZ21generate_random_floatvE9generador
	.addrsig_sym _ZGVZ21generate_random_floatvE9generador
	.addrsig_sym _ZGVZ21generate_random_floatvE21distribucion_uniforme
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10reduce_maxPfS_i     ; -- Begin function _Z10reduce_maxPfS_i
	.globl	_Z10reduce_maxPfS_i
	.p2align	8
	.type	_Z10reduce_maxPfS_i,@function
_Z10reduce_maxPfS_i:                    ; @_Z10reduce_maxPfS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x24
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v4, 0
	s_cmpk_lt_u32 s5, 0x42
	v_add_nc_u32_e32 v3, s5, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[1:2], off
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v1, v0, 2, 0
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v2, v3
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v3, v1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v3, v2
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	ds_store_b32 v1, v2
.LBB0_4:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmpk_lt_u32 s5, 0x84
	s_mov_b32 s5, s0
	s_branch .LBB0_1
.LBB0_5:                                ; %._crit_edge
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_add_nc_u32_e32 v6, 0x80, v1
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s0, -1, v6
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
	v_cndmask_b32_e64 v4, 0, v6, s0
	v_cndmask_b32_e64 v5, 0, s1, s0
	flat_load_b32 v7, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v7, v4
	v_add_nc_u32_e32 v7, 64, v1
	v_cndmask_b32_e32 v4, v6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	flat_load_b32 v6, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v6, v4
	v_cndmask_b32_e32 v4, v7, v1, vcc_lo
	v_add_nc_u32_e32 v7, 32, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	flat_load_b32 v6, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v6, v4
	v_cndmask_b32_e32 v4, v7, v1, vcc_lo
	v_add_nc_u32_e32 v7, 16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	flat_load_b32 v6, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v6, v4
	v_cndmask_b32_e32 v4, v7, v1, vcc_lo
	v_add_nc_u32_e32 v7, 8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	flat_load_b32 v6, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v6, v4
	v_cndmask_b32_e32 v4, v7, v1, vcc_lo
	v_add_nc_u32_e32 v7, 4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	flat_load_b32 v6, v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	s_waitcnt lgkmcnt(0)
	flat_store_b32 v[2:3], v6 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v6, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v6, v4
	v_cndmask_b32_e32 v1, v7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	v_cndmask_b32_e64 v5, 0, s1, vcc_lo
	flat_load_b32 v1, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_7:
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_9:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10reduce_maxPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10reduce_maxPfS_i, .Lfunc_end0-_Z10reduce_maxPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 980
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16calcula_B_sharedPfi ; -- Begin function _Z16calcula_B_sharedPfi
	.globl	_Z16calcula_B_sharedPfi
	.p2align	8
	.type	_Z16calcula_B_sharedPfi,@function
_Z16calcula_B_sharedPfi:                ; @_Z16calcula_B_sharedPfi
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s8, s[0:1], 0x8
	s_load_b64 s[6:7], s[0:1], 0x0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s15, s9
	v_add_nc_u32_e32 v1, s4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB1_8
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v5, v[3:4], off
	v_cmpx_lt_i32_e32 1, v1
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v7, v[7:8], off offset:-8
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 0, v1
	s_cbranch_execz .LBB1_5
; %bb.4:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[1:2]
	v_add_co_u32 v8, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b32 v6, v[8:9], off offset:-4
.LBB1_5:
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v2, v[3:4], off offset:4
	v_add_nc_u32_e32 v1, 2, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, s8, v1
	v_mov_b32_e32 v1, 0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_7
; %bb.6:
	global_load_b32 v1, v[3:4], off offset:8
.LBB1_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(1)
	v_frexp_mant_f32_e64 v3, |v7|
	v_frexp_mant_f32_e64 v10, |v5|
	s_waitcnt vmcnt(0)
	v_frexp_mant_f32_e64 v13, |v2|
	v_frexp_mant_f32_e64 v14, |v1|
	v_frexp_exp_i32_f32_e32 v4, v7
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
	v_cmp_gt_f32_e64 s3, 0x3f2aaaab, v10
	v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v13
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v14
	v_frexp_exp_i32_f32_e32 v11, v5
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_cndmask_b32_e64 v17, 0, 1, s3
	v_cndmask_b32_e64 v18, 0, 1, s1
	v_cndmask_b32_e64 v20, 0, 1, s0
	v_frexp_exp_i32_f32_e32 v9, v6
	v_ldexp_f32 v3, v3, v8
	v_frexp_mant_f32_e64 v8, |v6|
	v_ldexp_f32 v10, v10, v17
	v_ldexp_f32 v13, v13, v18
	v_ldexp_f32 v14, v14, v20
	v_add_f32_e32 v19, -1.0, v3
	v_add_f32_e32 v12, 1.0, v3
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v8
	v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_subrev_co_ci_u32_e64 v11, vcc_lo, 0, v11, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v16, v12
	v_cndmask_b32_e64 v15, 0, 1, s2
	v_subrev_co_ci_u32_e64 v9, vcc_lo, 0, v9, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v11, v11
	v_cvt_f32_i32_e32 v4, v4
	v_ldexp_f32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_f32_i32_e32 v9, v9
	v_add_f32_e32 v25, -1.0, v14
	s_mov_b32 s10, 0x3e76c4e1
	v_mul_f32_e32 v28, 0x3f317218, v4
	v_mul_f32_e32 v21, v19, v16
	v_dual_add_f32 v15, -1.0, v12 :: v_dual_add_f32 v18, 1.0, v10
	v_add_f32_e32 v24, 1.0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v36, 0x3f317218, v4, -v28
	v_dual_mul_f32 v22, v12, v21 :: v_dual_sub_f32 v3, v3, v15
	v_add_f32_e32 v15, -1.0, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v34, v24
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v7|
	v_fma_f32 v12, v21, v12, -v22
	v_add_f32_e32 v32, -1.0, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v21, v3 :: v_dual_add_f32 v17, -1.0, v10
	v_dual_add_f32 v20, v22, v12 :: v_dual_add_f32 v23, -1.0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v3, 1.0, v8 :: v_dual_sub_f32 v22, v20, v22
	v_dual_sub_f32 v26, v19, v20 :: v_dual_add_f32 v27, 1.0, v14
	v_add_f32_e32 v29, -1.0, v3
	v_rcp_f32_e32 v30, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v22, v12 :: v_dual_sub_f32 v19, v19, v26
	v_mul_f32_e32 v22, 0x3f317218, v11
	v_sub_f32_e32 v8, v8, v29
	v_sub_f32_e32 v10, v10, v32
	v_fmac_f32_e32 v36, 0xb102e308, v4
	v_sub_f32_e32 v19, v19, v20
	v_mul_f32_e32 v31, 0x3f317218, v9
	v_rcp_f32_e32 v20, v18
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v15, v30
	v_rcp_f32_e32 v35, v27
	v_add_f32_e32 v12, v12, v19
	v_dual_add_f32 v19, -1.0, v27 :: v_dual_add_f32 v12, v26, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v33, -1.0, v24 :: v_dual_sub_f32 v14, v14, v19
	v_fma_f32 v26, 0x3f317218, v9, -v31
	v_dual_mul_f32 v19, v23, v34 :: v_dual_mul_f32 v12, v16, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v13, v13, v33
	v_mul_f32_e32 v4, v3, v29
	v_dual_fmac_f32 v26, 0xb102e308, v9 :: v_dual_add_f32 v33, v28, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v9, v21, v12 :: v_dual_mul_f32 v38, v24, v19
	v_fma_f32 v3, v29, v3, -v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v16, v17, v20 :: v_dual_add_f32 v37, v31, v26
	v_sub_f32_e32 v21, v9, v21
	v_mul_f32_e32 v32, v25, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v3, v29, v8
	v_fma_f32 v24, v19, v24, -v38
	v_dual_sub_f32 v31, v37, v31 :: v_dual_sub_f32 v12, v12, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v8, v9, v9 :: v_dual_add_f32 v39, v4, v3
	v_mul_f32_e32 v21, v18, v16
	v_mul_f32_e32 v42, v27, v32
	v_sub_f32_e32 v28, v33, v28
	v_fma_f32 v40, v9, v9, -v8
	v_sub_f32_e32 v43, v15, v39
	v_fma_f32 v18, v16, v18, -v21
	v_fma_f32 v27, v32, v27, -v42
	v_sub_f32_e32 v4, v39, v4
	v_fmac_f32_e32 v24, v19, v13
	v_sub_f32_e32 v15, v15, v43
	v_add_f32_e32 v41, v12, v12
	v_fmac_f32_e32 v27, v32, v14
	v_sub_f32_e32 v3, v4, v3
	v_sub_f32_e32 v26, v26, v31
	v_sub_f32_e32 v4, v15, v39
	v_dual_fmac_f32 v40, v9, v41 :: v_dual_sub_f32 v15, v36, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v18, v16, v10 :: v_dual_add_f32 v3, v3, v4
	v_add_f32_e32 v41, v8, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v43, v3 :: v_dual_fmaak_f32 v28, s10, v41, 0x3e91f4c4
	v_dual_add_f32 v10, v21, v18 :: v_dual_mul_f32 v3, v30, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v4, v41, v28, 0x3ecccdef
	v_dual_sub_f32 v8, v41, v8 :: v_dual_sub_f32 v21, v10, v21
	v_dual_add_f32 v14, v38, v24 :: v_dual_sub_f32 v31, v17, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v13, v41, v4 :: v_dual_add_f32 v28, v42, v27
	v_dual_sub_f32 v36, v14, v38 :: v_dual_sub_f32 v17, v17, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, v41, v4, -v13
	v_dual_add_f32 v38, v29, v3 :: v_dual_sub_f32 v39, v28, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v8, v40, v8 :: v_dual_sub_f32 v29, v38, v29
	v_sub_f32_e32 v40, v25, v28
	v_fmac_f32_e32 v30, v8, v4
	v_sub_f32_e32 v18, v21, v18
	v_mul_f32_e32 v21, v38, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v3, v3, v29 :: v_dual_add_f32 v42, v13, v30
	v_fma_f32 v44, v38, v38, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v45, v3, v3
	v_dual_sub_f32 v4, v23, v14 :: v_dual_sub_f32 v13, v42, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v29, 0x3f2aaaaa, v42 :: v_dual_fmac_f32 v44, v38, v45
	v_sub_f32_e32 v23, v23, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v13, v30, v13
	v_add_f32_e32 v30, 0xbf2aaaaa, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v43, v9, v41 :: v_dual_sub_f32 v14, v23, v14
	v_sub_f32_e32 v30, v42, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v46, v41, v9, -v43
	v_dual_add_f32 v13, 0x31739010, v13 :: v_dual_fmac_f32 v46, v41, v12
	v_sub_f32_e32 v25, v25, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v24, v36, v24 :: v_dual_add_f32 v13, v13, v30
	v_ldexp_f32 v12, v12, 1
	v_dual_fmac_f32 v46, v8, v9 :: v_dual_sub_f32 v25, v25, v28
	v_ldexp_f32 v9, v9, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v30, v43, v46
	v_add_f32_e32 v36, v21, v44
	v_sub_f32_e32 v8, v39, v27
	v_sub_f32_e32 v39, v30, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v27, s10, v36, 0x3e91f4c4 :: v_dual_sub_f32 v10, v17, v10
	v_add_f32_e32 v17, v29, v13
	v_dual_add_f32 v8, v8, v25 :: v_dual_sub_f32 v39, v46, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v23, v36, v27, 0x3ecccdef :: v_dual_add_f32 v10, v18, v10
	v_sub_f32_e32 v27, v29, v17
	v_mul_f32_e32 v28, v30, v17
	v_sub_f32_e32 v21, v36, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v29, v36, v23 :: v_dual_add_f32 v10, v31, v10
	v_add_f32_e32 v13, v13, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v27, v30, v17, -v28
	v_sub_f32_e32 v18, v44, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v21, v36, v23, -v29
	v_dual_mul_f32 v10, v20, v10 :: v_dual_mul_f32 v25, v38, v36
	v_fmac_f32_e32 v27, v30, v13
	v_add_f32_e32 v13, v24, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v21, v18, v23 :: v_dual_add_f32 v8, v40, v8
	v_fmac_f32_e32 v27, v39, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v4, v13
	v_dual_add_f32 v13, v29, v21 :: v_dual_mul_f32 v8, v35, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v28, v27
	v_mul_f32_e32 v4, v34, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v20, 0x3f2aaaaa, v13 :: v_dual_add_f32 v23, v9, v14
	v_dual_sub_f32 v24, v14, v28 :: v_dual_sub_f32 v17, v13, v29
	v_sub_f32_e32 v9, v23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v24, v27, v24 :: v_dual_sub_f32 v17, v21, v17
	v_dual_sub_f32 v9, v14, v9 :: v_dual_add_f32 v12, v12, v24
	v_add_f32_e32 v14, v16, v10
	v_fma_f32 v27, v36, v38, -v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v12, v9
	v_add_f32_e32 v21, 0xbf2aaaaa, v20
	v_dual_sub_f32 v16, v14, v16 :: v_dual_fmac_f32 v27, v36, v3
	v_mul_f32_e32 v28, v14, v14
	v_ldexp_f32 v12, v38, 1
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v10, v16
	v_fmac_f32_e32 v27, v18, v38
	v_add_f32_e32 v17, 0x31739010, v17
	v_add_f32_e32 v18, v23, v9
	v_dual_sub_f32 v13, v13, v21 :: v_dual_add_f32 v34, v10, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v24, v25, v27
	v_fma_f32 v30, v14, v14, -v28
	v_sub_f32_e32 v23, v18, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v17, v13 :: v_dual_fmac_f32 v30, v14, v34
	v_add_f32_e32 v17, v20, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v21, v19, v4 :: v_dual_sub_f32 v16, v20, v17
	v_dual_add_f32 v20, v33, v18 :: v_dual_mul_f32 v29, v24, v17
	v_sub_f32_e32 v25, v24, v25
	v_sub_f32_e32 v19, v21, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v13, v13, v16 :: v_dual_sub_f32 v16, v20, v33
	v_fma_f32 v31, v24, v17, -v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v19
	v_fmac_f32_e32 v31, v24, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v18, v16 :: v_dual_add_f32 v18, v28, v30
	v_dual_fmaak_f32 v24, s10, v18, 0x3e91f4c4 :: v_dual_sub_f32 v25, v27, v25
	v_sub_f32_e32 v27, v20, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v24, v18, v24, 0x3ecccdef
	v_sub_f32_e32 v16, v33, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v31, v25, v17
	v_ldexp_f32 v17, v14, 1
	v_add_f32_e32 v13, v13, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v29, v31
	v_add_f32_e32 v27, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v29, v16, v29 :: v_dual_sub_f32 v12, v27, v12
	v_dual_sub_f32 v9, v9, v23 :: v_dual_sub_f32 v12, v16, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v16, v18, v28 :: v_dual_add_f32 v23, v15, v9
	v_sub_f32_e32 v29, v31, v29
	v_mul_f32_e32 v28, v21, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v16, v30, v16 :: v_dual_add_f32 v13, v23, v13
	v_add_f32_e32 v3, v3, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v33, v20, v13
	v_dual_add_f32 v3, v3, v12 :: v_dual_mul_f32 v12, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v20, v33, v20
	v_dual_sub_f32 v13, v13, v20 :: v_dual_add_f32 v20, v27, v3
	v_sub_f32_e32 v25, v23, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v23, v25
	v_sub_f32_e32 v9, v9, v25
	v_sub_f32_e32 v15, v15, v23
	v_fma_f32 v23, v18, v14, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v9, v15
	v_mul_f32_e32 v15, v18, v24
	v_add_f32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v18, v24, -v15
	v_add_f32_e32 v25, v33, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v13, v16, v24
	v_dual_add_f32 v24, v37, v20 :: v_dual_fmac_f32 v23, v18, v10
	v_ldexp_f32 v10, v10, 1
	v_sub_f32_e32 v18, v25, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v29, v15, v13
	v_sub_f32_e32 v30, v24, v37
	v_mul_f32_e32 v33, 0, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v9, v9, v18 :: v_dual_sub_f32 v18, v20, v27
	v_sub_f32_e32 v27, v24, v30
	v_sub_f32_e32 v15, v29, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v33, 2.0, v9
	v_sub_f32_e32 v3, v3, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v9, v20, v30 :: v_dual_sub_f32 v18, v37, v27
	v_dual_add_f32 v20, 0x3f2aaaaa, v29 :: v_dual_sub_f32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v26, v3
	v_dual_add_f32 v9, v9, v18 :: v_dual_add_f32 v18, 0xbf2aaaaa, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v13, 0x31739010, v13 :: v_dual_sub_f32 v30, v15, v26
	v_dual_add_f32 v9, v15, v9 :: v_dual_sub_f32 v18, v29, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v15, v30
	v_sub_f32_e32 v3, v3, v30
	v_add_f32_e32 v29, v24, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, v13, v18
	v_dual_sub_f32 v15, v26, v15 :: v_dual_sub_f32 v24, v29, v24
	v_fmac_f32_e32 v23, v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v16, v20, v13 :: v_dual_add_f32 v3, v3, v15
	v_sub_f32_e32 v9, v9, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v12, v23
	v_add_f32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, v15, v16
	v_sub_f32_e32 v9, v15, v12
	v_sub_f32_e32 v12, v20, v16
	v_dual_add_f32 v24, v29, v3 :: v_dual_sub_f32 v9, v23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v13, v12
	v_dual_add_f32 v34, v24, v24 :: v_dual_add_f32 v31, v25, v25
	v_mul_f32_e32 v36, 0, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v25, v25, 2.0, -v31
	v_cmp_class_f32_e64 vcc_lo, v31, 0x204
	v_add_f32_e32 v25, v25, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v27, v31, v25
	v_cndmask_b32_e32 v33, v27, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v33
	v_cndmask_b32_e64 v30, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v33|
	v_sub_f32_e32 v14, v33, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, 0x3fb8aa3b, v14
	v_rndne_f32_e32 v20, v18
	v_fma_f32 v19, 0x3fb8aa3b, v14, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v13, v18, v20 :: v_dual_sub_f32 v18, v24, v29
	v_fma_f32 v29, v15, v16, -v26
	v_fmac_f32_e32 v19, 0x32a5705f, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v3, v18
	v_fmac_f32_e32 v29, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v13, v13, v19
	v_sub_f32_e32 v15, v27, v31
	v_fma_f32 v12, v24, 2.0, -v34
	v_dual_fmac_f32 v36, 2.0, v3 :: v_dual_fmac_f32 v29, v9, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_exp_f32_e32 v13, v13
	v_cvt_i32_f32_e32 v9, v20
	v_fma_f32 v3, v21, v21, -v28
	v_add_f32_e32 v12, v12, v36
	v_dual_add_f32 v16, v26, v29 :: v_dual_add_f32 v19, v4, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_sub_f32 v20, v16, v26 :: v_dual_sub_f32 v15, v25, v15
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v9, v13, v9
	v_add_f32_e32 v13, v34, v12
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v15, v30, v15
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v34, 0x204
	v_cndmask_b32_e32 v18, v13, v34, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_sub_f32_e32 v13, v13, v34
	v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v18
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v15, v9, v15, v9
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v9
	v_sub_f32_e32 v13, v18, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v15, v9, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v18|
	v_dual_add_f32 v18, v17, v16 :: v_dual_mul_f32 v15, 0x3fb8aa3b, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0x7f800000, |v9|, s2
	v_cndmask_b32_e32 v12, 0, v12, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v7
	v_dual_add_f32 v12, v14, v12 :: v_dual_cndmask_b32 v7, 0, v9
	v_sub_f32_e32 v9, v18, v17
	v_sub_f32_e32 v17, v29, v20
	v_fma_f32 v14, 0x3fb8aa3b, v13, -v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v16, v9
	v_dual_add_f32 v10, v10, v17 :: v_dual_add_f32 v17, v32, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, 0x32a5705f, v13
	v_dual_add_f32 v9, v10, v9 :: v_dual_sub_f32 v24, v17, v32
	v_rndne_f32_e32 v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v23, v18, v9 :: v_dual_sub_f32 v8, v8, v24
	v_fmac_f32_e32 v3, v21, v19
	v_fma_f32 v19, 0x3f317218, v11, -v22
	v_sub_f32_e32 v15, v15, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v23, v18
	v_cvt_i32_f32_e32 v10, v10
	v_add_f32_e32 v16, v28, v3
	v_dual_fmac_f32 v19, 0xb102e308, v11 :: v_dual_add_f32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v9, v18
	v_fmaak_f32 v11, s10, v16, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v31, v21, v16 :: v_dual_add_f32 v20, v22, v19
	v_dual_sub_f32 v25, v16, v28 :: v_dual_mul_f32 v28, v17, v17
	v_fmaak_f32 v11, v16, v11, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v33, v16, v21, -v31
	v_add_f32_e32 v27, v20, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v15, v17, v17, -v28
	v_mul_f32_e32 v26, v16, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v33, v16, v4
	v_ldexp_f32 v4, v4, 1
	v_sub_f32_e32 v3, v3, v25
	v_add_f32_e32 v25, v8, v8
	v_fma_f32 v24, v16, v11, -v26
	v_sub_f32_e32 v29, v27, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v33, v3, v21
	v_dual_fmac_f32 v15, v17, v25 :: v_dual_fmac_f32 v24, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v20, v22 :: v_dual_sub_f32 v22, v27, v29
	v_dual_sub_f32 v23, v23, v29 :: v_dual_add_f32 v18, v28, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v25, v26, v24
	v_sub_f32_e32 v11, v19, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v19, v20, v22
	v_fmaak_f32 v30, s10, v18, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v20, v25, v26
	v_add_f32_e32 v22, 0x3f2aaaaa, v25
	v_add_f32_e32 v26, v11, v9
	v_dual_add_f32 v19, v23, v19 :: v_dual_fmaak_f32 v30, v18, v30, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v20, v24, v20
	v_add_f32_e32 v24, 0xbf2aaaaa, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v32, v26, v11
	v_add_f32_e32 v20, 0x31739010, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v25, v24
	v_sub_f32_e32 v34, v26, v32
	v_sub_f32_e32 v25, v18, v28
	v_dual_mul_f32 v28, v18, v30 :: v_dual_sub_f32 v9, v9, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v16, v20, v24 :: v_dual_sub_f32 v3, v11, v34
	v_add_f32_e32 v24, v31, v33
	v_sub_f32_e32 v15, v15, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v20, v18, v30, -v28
	v_add_f32_e32 v11, v22, v16
	v_add_f32_e32 v3, v9, v3
	v_sub_f32_e32 v9, v24, v31
	v_frexp_exp_i32_f32_e32 v31, v2
	v_fmac_f32_e32 v20, v15, v30
	v_sub_f32_e32 v22, v22, v11
	v_mul_f32_e32 v25, v24, v11
	v_sub_f32_e32 v9, v33, v9
	v_subrev_co_ci_u32_e64 v31, vcc_lo, 0, v31, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v16, v16, v22
	v_fma_f32 v30, v24, v11, -v25
	v_add_f32_e32 v23, v28, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v30, v24, v16
	v_sub_f32_e32 v22, v23, v28
	v_add_f32_e32 v28, 0x3f2aaaaa, v23
	v_cvt_f32_i32_e32 v16, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v30, v9, v11
	v_mul_f32_e32 v29, v17, v18
	v_sub_f32_e32 v20, v20, v22
	v_add_f32_e32 v22, 0xbf2aaaaa, v28
	v_mul_f32_e32 v9, 0x3f317218, v16
	v_fma_f32 v32, v18, v17, -v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v20, 0x31739010, v20
	v_sub_f32_e32 v22, v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v32, v18, v8
	v_ldexp_f32 v8, v8, 1
	v_add_f32_e32 v18, v20, v22
	v_ldexp_f32 v20, v21, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v21, v25, v30 :: v_dual_fmac_f32 v32, v15, v17
	v_add_f32_e32 v15, v26, v19
	v_add_f32_e32 v11, v28, v18
	v_fma_f32 v26, 0x3f317218, v16, -v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v25, v21, v25
	v_add_f32_e32 v19, v29, v32
	v_sub_f32_e32 v23, v28, v11
	v_add_f32_e32 v28, v20, v21
	v_fmac_f32_e32 v26, 0xb102e308, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v24, v19, v11
	v_dual_sub_f32 v29, v19, v29 :: v_dual_add_f32 v18, v18, v23
	v_frexp_exp_i32_f32_e32 v16, v1
	v_sub_f32_e32 v20, v28, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, v19, v11, -v24
	v_dual_sub_f32 v29, v32, v29 :: v_dual_add_f32 v22, v27, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v23, v19, v18 :: v_dual_sub_f32 v18, v30, v25
	v_sub_f32_e32 v19, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v23, v29, v11
	v_subrev_co_ci_u32_e64 v11, vcc_lo, 0, v16, s0
	v_add_f32_e32 v4, v4, v18
	v_ldexp_f32 v16, v17, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v17, v24, v23
	v_cvt_f32_i32_e32 v11, v11
	v_sub_f32_e32 v18, v22, v27
	v_dual_add_f32 v4, v4, v19 :: v_dual_add_f32 v19, v9, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v21, v17, v24
	v_dual_mul_f32 v25, 0x3f317218, v11 :: v_dual_add_f32 v20, v16, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v24, v28, v4 :: v_dual_sub_f32 v9, v19, v9
	v_sub_f32_e32 v21, v23, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, 0x3f317218, v11, -v25
	v_sub_f32_e32 v16, v20, v16
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	v_sub_f32_e32 v9, v26, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_add_f32 v8, v8, v21 :: v_dual_fmac_f32 v23, 0xb102e308, v11
	v_sub_f32_e32 v11, v24, v28
	v_sub_f32_e32 v16, v17, v16
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v5|
	v_add_f32_e32 v17, v25, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v4, v11
	v_add_f32_e32 v8, v8, v16
	v_exp_f32_e32 v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v26, v9, v4
	v_add_f32_e32 v21, v20, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_sub_f32 v27, v26, v9 :: v_dual_sub_f32 v20, v21, v20
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v11, v10
	v_sub_f32_e32 v28, v26, v27
	v_sub_f32_e32 v4, v4, v27
	v_sub_f32_e32 v8, v8, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v10, 0, v10 :: v_dual_sub_f32 v9, v9, v28
	v_dual_add_f32 v4, v4, v9 :: v_dual_sub_f32 v15, v15, v18
	v_add_f32_e32 v18, v19, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v15
	v_sub_f32_e32 v15, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v22, v3
	v_sub_f32_e32 v16, v18, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v15, v24, v15 :: v_dual_sub_f32 v22, v14, v22
	v_dual_sub_f32 v16, v19, v16 :: v_dual_add_f32 v19, v17, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v22
	v_add_f32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v19, v17
	v_dual_sub_f32 v16, v17, v25 :: v_dual_add_f32 v15, v26, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v20, v21, v24
	v_dual_sub_f32 v16, v23, v16 :: v_dual_add_f32 v23, v14, v14
	v_sub_f32_e32 v25, v19, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v21, v18, v15 :: v_dual_add_f32 v22, v16, v8
	v_cmp_class_f32_e64 vcc_lo, v23, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v18, v21, v18
	v_sub_f32_e32 v9, v15, v18
	v_fma_f32 v18, v14, 2.0, -v23
	v_mul_f32_e32 v14, 0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v9
	v_dual_fmac_f32 v14, 2.0, v3 :: v_dual_add_f32 v3, v21, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v18, v14 :: v_dual_sub_f32 v14, v3, v21
	v_sub_f32_e32 v4, v4, v14
	v_dual_add_f32 v14, v3, v3 :: v_dual_sub_f32 v17, v17, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v17, v20, v17 :: v_dual_sub_f32 v20, v22, v16
	v_add_f32_e32 v17, v22, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v22, v20
	v_sub_f32_e32 v8, v8, v20
	v_dual_add_f32 v22, v19, v17 :: v_dual_sub_f32 v9, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v22, v19 :: v_dual_add_f32 v8, v8, v9
	v_sub_f32_e32 v9, v17, v15
	v_mul_f32_e32 v15, 0, v3
	v_fma_f32 v3, v3, 2.0, -v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v8, v8, v9 :: v_dual_add_f32 v9, v23, v11
	v_fmac_f32_e32 v15, 2.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v16, v22, v8 :: v_dual_cndmask_b32 v17, v9, v23
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	v_add_f32_e32 v3, v3, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v9, v9, v23 :: v_dual_sub_f32 v4, v16, v22
	v_dual_mul_f32 v15, 0, v16 :: v_dual_cndmask_b32 v10, 0x7f800000, v10
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v17
	v_add_f32_e32 v18, v14, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v4, v8, v4
	v_add_f32_e32 v8, v16, v16
	v_fma_f32 v12, v10, v12, v10
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v14, 0x204
	v_fmac_f32_e32 v15, 2.0, v4
	v_fma_f32 v16, v16, 2.0, -v8
	v_sub_f32_e32 v9, v11, v9
	v_dual_sub_f32 v19, v17, v13 :: v_dual_cndmask_b32 v4, v18, v14
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v10
	v_sub_f32_e32 v14, v18, v14
	v_cndmask_b32_e32 v10, v12, v10, vcc_lo
	v_add_f32_e32 v12, v16, v15
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_mul_f32_e32 v15, 0x3fb8aa3b, v19
	v_sub_f32_e32 v3, v3, v14
	v_add_f32_e64 v10, |v10|, |v10|
	v_add_f32_e32 v20, v8, v12
	v_cndmask_b32_e64 v16, 0, 0x37000000, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x204
	v_fma_f32 v21, 0x3fb8aa3b, v19, -v15
	v_rndne_f32_e32 v22, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v24, v4, v16
	v_cndmask_b32_e32 v25, v20, v8, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	v_fmac_f32_e32 v21, 0x32a5705f, v19
	v_dual_sub_f32 v15, v15, v22 :: v_dual_mul_f32 v26, 0x3fb8aa3b, v24
	v_cndmask_b32_e32 v10, 0x7f800000, v10, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v25
	s_delay_alu instid0(VALU_DEP_3)
	v_rndne_f32_e32 v23, v26
	v_cndmask_b32_e64 v27, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v6
	v_cndmask_b32_e32 v6, 0, v10, vcc_lo
	v_add_f32_e32 v10, v15, v21
	v_fma_f32 v15, 0x3fb8aa3b, v24, -v26
	v_sub_f32_e32 v21, v25, v27
	v_sub_f32_e32 v26, v26, v23
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v17|
	v_exp_f32_e32 v10, v10
	v_fmac_f32_e32 v15, 0x32a5705f, v24
	v_mul_f32_e32 v11, 0x3fb8aa3b, v21
	v_cvt_i32_f32_e32 v17, v22
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v19
	v_add_f32_e32 v15, v26, v15
	v_fma_f32 v22, 0x3fb8aa3b, v21, -v11
	v_rndne_f32_e32 v28, v11
	v_add_f32_e32 v9, v13, v9
	v_ldexp_f32 v10, v10, v17
	v_exp_f32_e32 v13, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v22, 0x32a5705f, v21 :: v_dual_sub_f32 v11, v11, v28
	v_cvt_i32_f32_e32 v15, v23
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v19
	v_add_f32_e32 v6, v7, v6
	v_add_f32_e32 v11, v11, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, 0x7f800000, v10, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_exp_f32_e32 v11, v11
	v_ldexp_f32 v13, v13, v15
	v_sub_f32_e32 v4, v20, v8
	v_cvt_i32_f32_e32 v8, v28
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v24
	v_fma_f32 v9, v10, v9, v10
	v_sub_f32_e32 v4, v12, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f32_e32 v3, v16, v3
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v24
	v_ldexp_f32 v8, v11, v8
	v_cndmask_b32_e32 v11, 0x7f800000, v13, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v25|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v11, v3, v11
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v21
	v_add_f32_e32 v4, v27, v4
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v10
	v_fma_f32 v4, v8, v4, v8
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x7f800000, |v9|, s0
	v_cndmask_b32_e32 v3, v3, v11, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8
	v_mul_f32_e64 v3, 0x40400000, |v3|
	v_cndmask_b32_e32 v4, v4, v8, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v4, 0x40a00000, |v4|
	v_cndmask_b32_e32 v5, 0, v7, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v2|
	v_add_f32_e32 v5, v5, v6
	v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v3, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v1|
	v_dual_sub_f32 v2, v5, v2 :: v_dual_cndmask_b32 v3, 0x7f800000, v4
	v_cmp_neq_f32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0, v3, vcc_lo
	v_add_f32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v2, null, 0x41c00000, 0x41c00000, v1
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v3
	v_div_scale_f32 v4, vcc_lo, v1, 0x41c00000, v1
	v_mul_f32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v2, v5, v4
	v_fmac_f32_e32 v5, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v5, v4
	v_div_fmas_f32 v2, v2, v3, v5
	v_lshl_add_u32 v3, v0, 2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v1, v2, 0x41c00000, v1
	ds_store_b32 v3, v1
.LBB1_8:                                ; %Flow55
	s_or_b32 exec_lo, exec_lo, s5
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_cmp_lg_u32 s9, 0
	s_mov_b32 s2, 0
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_13
; %bb.9:                                ; %.lr.ph.preheader
	s_ashr_i32 s5, s4, 31
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
.LBB1_10:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_cmp_ge_i32 s4, s8
	s_cbranch_scc1 .LBB1_12
; %bb.11:                               ;   in Loop: Header=BB1_10 Depth=1
	v_mov_b32_e32 v1, s2
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_12:                               ;   in Loop: Header=BB1_10 Depth=1
	s_add_i32 s9, s9, -1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_add_i32 s4, s4, 1
	s_add_i32 s2, s2, 4
	s_cmp_lg_u32 s9, 0
	s_cbranch_scc1 .LBB1_10
.LBB1_13:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16calcula_B_sharedPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 47
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16calcula_B_sharedPfi, .Lfunc_end1-_Z16calcula_B_sharedPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4816
; NumSgprs: 18
; NumVgprs: 47
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 47
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9calcula_BPfS_i       ; -- Begin function _Z9calcula_BPfS_i
	.globl	_Z9calcula_BPfS_i
	.p2align	8
	.type	_Z9calcula_BPfS_i,@function
_Z9calcula_BPfS_i:                      ; @_Z9calcula_BPfS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v4
	s_cbranch_execz .LBB2_8
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 1, v4
	s_cbranch_execz .LBB2_3
; %bb.2:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v8, v[0:1], off offset:-8
.LBB2_3:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 0, v4
	s_cbranch_execz .LBB2_5
; %bb.4:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v7, v[0:1], off offset:-4
.LBB2_5:
	s_or_b32 exec_lo, exec_lo, s0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_nc_u32_e32 v4, 2, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, s2, v4
	v_mov_b32_e32 v4, 0
	global_load_b64 v[2:3], v[5:6], off
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB2_7
; %bb.6:
	global_load_b32 v4, v[5:6], off offset:8
.LBB2_7:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(1)
	v_frexp_mant_f32_e64 v5, |v8|
	s_waitcnt vmcnt(0)
	v_frexp_mant_f32_e64 v11, |v2|
	v_frexp_mant_f32_e64 v14, |v3|
	v_frexp_mant_f32_e64 v15, |v4|
	v_frexp_exp_i32_f32_e32 v6, v8
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
	v_cmp_gt_f32_e64 s3, 0x3f2aaaab, v11
	v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v14
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v15
	v_frexp_exp_i32_f32_e32 v10, v7
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_cndmask_b32_e64 v18, 0, 1, s3
	v_cndmask_b32_e64 v19, 0, 1, s1
	v_cndmask_b32_e64 v21, 0, 1, s0
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_ldexp_f32 v5, v5, v9
	v_frexp_mant_f32_e64 v9, |v7|
	v_ldexp_f32 v11, v11, v18
	v_ldexp_f32 v14, v14, v19
	v_ldexp_f32 v15, v15, v21
	v_add_f32_e32 v13, 1.0, v5
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v9
	v_add_f32_e32 v18, -1.0, v11
	v_add_f32_e32 v20, -1.0, v5
	v_frexp_exp_i32_f32_e32 v12, v2
	v_rcp_f32_e32 v17, v13
	v_cndmask_b32_e64 v16, 0, 1, s2
	v_subrev_co_ci_u32_e64 v10, vcc_lo, 0, v10, s2
	v_add_f32_e32 v19, 1.0, v11
	v_subrev_co_ci_u32_e64 v12, vcc_lo, 0, v12, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
	v_ldexp_f32 v9, v9, v16
	v_add_f32_e32 v16, -1.0, v13
	v_cvt_f32_i32_e32 v10, v10
	v_mul_f32_e32 v22, v20, v17
	v_cvt_f32_i32_e32 v6, v6
	v_add_f32_e32 v25, 1.0, v14
	v_dual_sub_f32 v5, v5, v16 :: v_dual_add_f32 v16, -1.0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v23, v13, v22
	v_cvt_f32_i32_e32 v12, v12
	v_dual_add_f32 v33, -1.0, v19 :: v_dual_add_f32 v34, -1.0, v25
	v_rcp_f32_e32 v35, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v13, v22, v13, -v23
	s_mov_b32 s4, 0x3e76c4e1
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v8|
	v_add_f32_e32 v24, -1.0, v14
	v_dual_add_f32 v26, -1.0, v15 :: v_dual_fmac_f32 v13, v22, v5
	v_add_f32_e32 v5, 1.0, v9
	v_mul_f32_e32 v29, 0x3f317218, v6
	v_dual_sub_f32 v11, v11, v33 :: v_dual_add_f32 v28, 1.0, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v21, v23, v13
	v_rcp_f32_e32 v31, v5
	v_add_f32_e32 v30, -1.0, v5
	v_fma_f32 v37, 0x3f317218, v6, -v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v32, 0x3f317218, v10 :: v_dual_sub_f32 v27, v20, v21
	v_rcp_f32_e32 v36, v28
	v_sub_f32_e32 v9, v9, v30
	v_sub_f32_e32 v14, v14, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_sub_f32_e32 v20, v20, v27
	v_sub_f32_e32 v23, v21, v23
	v_mul_f32_e32 v30, v16, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v20, v21
	v_sub_f32_e32 v13, v23, v13
	v_mul_f32_e32 v23, 0x3f317218, v12
	v_rcp_f32_e32 v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v13, v20
	v_dual_add_f32 v20, -1.0, v28 :: v_dual_add_f32 v13, v27, v13
	v_fma_f32 v27, 0x3f317218, v10, -v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, 0xb102e308, v10
	v_fmac_f32_e32 v37, 0xb102e308, v6
	v_mul_f32_e32 v6, v5, v30
	v_mul_f32_e32 v13, v17, v13
	v_dual_sub_f32 v15, v15, v20 :: v_dual_add_f32 v38, v32, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v34, v29, v37
	v_fma_f32 v5, v30, v5, -v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v10, v22, v13
	v_mul_f32_e32 v20, v24, v35
	v_sub_f32_e32 v32, v38, v32
	v_fmac_f32_e32 v5, v30, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v22, v10, v22 :: v_dual_sub_f32 v27, v27, v32
	v_dual_add_f32 v40, v6, v5 :: v_dual_sub_f32 v13, v13, v22
	v_mul_f32_e32 v9, v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v17, v18, v21 :: v_dual_sub_f32 v44, v16, v40
	v_dual_mul_f32 v33, v26, v36 :: v_dual_add_f32 v42, v13, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v22, v19, v17
	v_fma_f32 v41, v10, v10, -v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v29, v34, v29 :: v_dual_sub_f32 v16, v16, v44
	v_mul_f32_e32 v43, v28, v33
	v_sub_f32_e32 v6, v40, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v41, v10, v42
	v_fma_f32 v19, v17, v19, -v22
	v_fma_f32 v28, v33, v28, -v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v16, v40
	v_add_f32_e32 v42, v9, v41
	v_sub_f32_e32 v16, v37, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v28, v33, v15
	v_add_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v29, s4, v42, 0x3e91f4c4
	v_dual_mul_f32 v39, v25, v20 :: v_dual_fmaak_f32 v6, v42, v29, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v25, v20, v25, -v39
	v_fmac_f32_e32 v19, v17, v11
	v_add_f32_e32 v29, v43, v28
	v_fmac_f32_e32 v25, v20, v14
	v_mul_f32_e32 v14, v42, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v40, v29, v43
	v_add_f32_e32 v11, v22, v19
	v_dual_sub_f32 v32, v18, v11 :: v_dual_add_f32 v5, v44, v5
	v_dual_add_f32 v15, v39, v25 :: v_dual_mul_f32 v44, v10, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v18, v18, v32 :: v_dual_mul_f32 v5, v31, v5
	v_sub_f32_e32 v9, v42, v9
	v_sub_f32_e32 v37, v15, v39
	v_fma_f32 v31, v42, v6, -v14
	v_fma_f32 v47, v42, v10, -v44
	v_add_f32_e32 v39, v30, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v41, v9 :: v_dual_sub_f32 v30, v39, v30
	v_dual_sub_f32 v22, v11, v22 :: v_dual_sub_f32 v11, v18, v11
	v_sub_f32_e32 v5, v5, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v19, v22, v19
	v_dual_mul_f32 v22, v39, v39 :: v_dual_fmac_f32 v31, v9, v6
	v_sub_f32_e32 v6, v24, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v43, v14, v31 :: v_dual_sub_f32 v24, v24, v6
	v_sub_f32_e32 v14, v43, v14
	v_dual_add_f32 v30, 0x3f2aaaaa, v43 :: v_dual_sub_f32 v41, v26, v29
	v_fma_f32 v45, v39, v39, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v26, v26, v41
	v_sub_f32_e32 v14, v31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v31, 0xbf2aaaaa, v30 :: v_dual_sub_f32 v26, v26, v29
	v_dual_add_f32 v14, 0x31739010, v14 :: v_dual_sub_f32 v31, v43, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v14, v31
	v_add_f32_e32 v46, v5, v5
	v_add_f32_e32 v18, v30, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v45, v39, v46
	v_sub_f32_e32 v25, v37, v25
	v_add_f32_e32 v37, v22, v45
	v_fmac_f32_e32 v47, v42, v13
	v_ldexp_f32 v13, v13, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v47, v9, v10
	v_sub_f32_e32 v9, v40, v28
	v_ldexp_f32 v10, v10, 1
	v_add_f32_e32 v31, v44, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v15, v24, v15 :: v_dual_sub_f32 v40, v31, v44
	v_fmaak_f32 v28, s4, v37, 0x3e91f4c4
	v_sub_f32_e32 v22, v37, v22
	v_dual_add_f32 v9, v9, v26 :: v_dual_mul_f32 v26, v39, v37
	v_fmaak_f32 v24, v37, v28, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v28, v30, v18 :: v_dual_add_f32 v9, v41, v9
	v_mul_f32_e32 v30, v37, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v14, v28
	v_sub_f32_e32 v40, v47, v40
	v_mul_f32_e32 v29, v31, v18
	v_mul_f32_e32 v9, v36, v9
	v_fma_f32 v28, v31, v18, -v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, v31, v14
	v_add_f32_e32 v14, v25, v15
	v_dual_add_f32 v11, v19, v11 :: v_dual_fmac_f32 v28, v40, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v29, v28
	v_sub_f32_e32 v19, v45, v22
	v_fma_f32 v22, v37, v24, -v30
	v_dual_add_f32 v11, v32, v11 :: v_dual_fmac_f32 v22, v19, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v6, v14 :: v_dual_mul_f32 v11, v21, v11
	v_mul_f32_e32 v6, v35, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v30, v22 :: v_dual_sub_f32 v25, v15, v29
	v_add_f32_e32 v24, v10, v15
	v_dual_sub_f32 v18, v14, v30 :: v_dual_sub_f32 v25, v28, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v24, v10
	v_fma_f32 v28, v37, v39, -v26
	v_add_f32_e32 v21, 0x3f2aaaaa, v14
	v_dual_sub_f32 v18, v22, v18 :: v_dual_add_f32 v13, v13, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v15, v10
	v_fmac_f32_e32 v28, v37, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v22, 0xbf2aaaaa, v21 :: v_dual_add_f32 v15, v17, v11
	v_ldexp_f32 v5, v5, 1
	v_fmac_f32_e32 v28, v19, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v18, 0x31739010, v18 :: v_dual_sub_f32 v17, v15, v17
	v_dual_sub_f32 v14, v14, v22 :: v_dual_mul_f32 v29, v15, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v22, v20, v6 :: v_dual_add_f32 v25, v26, v28
	v_dual_sub_f32 v11, v11, v17 :: v_dual_add_f32 v14, v18, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v31, v15, v15, -v29
	v_dual_add_f32 v35, v11, v11 :: v_dual_add_f32 v10, v13, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v18, v21, v14
	v_ldexp_f32 v13, v39, 1
	v_fmac_f32_e32 v31, v15, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v19, v24, v10
	v_sub_f32_e32 v17, v21, v18
	v_mul_f32_e32 v30, v25, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v26, v25, v26 :: v_dual_add_f32 v21, v34, v19
	v_sub_f32_e32 v24, v19, v24
	v_add_f32_e32 v14, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v32, v25, v18, -v30
	v_sub_f32_e32 v26, v28, v26
	v_sub_f32_e32 v17, v21, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v25, v14
	v_dual_sub_f32 v14, v19, v17 :: v_dual_add_f32 v19, v29, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v28, v21, v17 :: v_dual_fmaak_f32 v25, s4, v19, 0x3e91f4c4
	v_sub_f32_e32 v17, v34, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v25, v19, v25, 0x3ecccdef :: v_dual_fmac_f32 v32, v26, v18
	v_add_f32_e32 v14, v14, v17
	v_ldexp_f32 v18, v15, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v30, v32
	v_add_f32_e32 v28, v13, v17
	v_sub_f32_e32 v10, v10, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v30, v17, v30 :: v_dual_sub_f32 v13, v28, v13
	v_dual_add_f32 v24, v16, v10 :: v_dual_sub_f32 v13, v17, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v30, v32, v30 :: v_dual_sub_f32 v17, v19, v29
	v_mul_f32_e32 v29, v22, v22
	v_add_f32_e32 v5, v5, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v24, v14 :: v_dual_sub_f32 v17, v31, v17
	v_add_f32_e32 v5, v5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v34, v21, v14 :: v_dual_mul_f32 v13, v15, v19
	v_dual_sub_f32 v21, v34, v21 :: v_dual_sub_f32 v26, v24, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v14, v21
	v_add_f32_e32 v21, v28, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v24, v26
	v_sub_f32_e32 v10, v10, v26
	v_sub_f32_e32 v16, v16, v24
	v_fma_f32 v24, v19, v15, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v16
	v_mul_f32_e32 v16, v19, v25
	v_add_f32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, v19, v25, -v16
	v_add_f32_e32 v26, v34, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v14, v17, v25
	v_dual_add_f32 v25, v38, v21 :: v_dual_fmac_f32 v24, v19, v11
	v_ldexp_f32 v11, v11, 1
	v_sub_f32_e32 v19, v26, v34
	v_mul_f32_e32 v34, 0, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v31, v25, v38 :: v_dual_sub_f32 v10, v10, v19
	v_sub_f32_e32 v19, v21, v28
	v_sub_f32_e32 v28, v25, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v34, 2.0, v10 :: v_dual_sub_f32 v5, v5, v19
	v_dual_sub_f32 v19, v38, v28 :: v_dual_add_f32 v30, v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v10, v21, v31 :: v_dual_add_f32 v21, 0x3f2aaaaa, v30
	v_sub_f32_e32 v16, v30, v16
	v_dual_add_f32 v10, v10, v19 :: v_dual_add_f32 v19, 0xbf2aaaaa, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v30, v19
	v_sub_f32_e32 v14, v14, v16
	v_add_f32_e32 v16, v27, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v14, 0x31739010, v14 :: v_dual_sub_f32 v31, v16, v27
	v_add_f32_e32 v10, v16, v10
	v_sub_f32_e32 v20, v22, v20
	v_add_f32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v16, v31
	v_add_f32_e32 v30, v25, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v5, v5, v31 :: v_dual_sub_f32 v6, v6, v20
	v_dual_sub_f32 v16, v27, v16 :: v_dual_sub_f32 v25, v30, v25
	v_fmac_f32_e32 v24, v17, v15
	v_add_f32_e32 v17, v21, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v5, v5, v16 :: v_dual_add_f32 v32, v26, v26
	v_sub_f32_e32 v10, v10, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v13, v24
	v_fma_f32 v26, v26, 2.0, -v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v5, v10
	v_mul_f32_e32 v27, v16, v17
	v_cmp_class_f32_e64 vcc_lo, v32, 0x204
	v_sub_f32_e32 v10, v16, v13
	v_sub_f32_e32 v13, v21, v17
	v_add_f32_e32 v25, v30, v5
	v_add_f32_e32 v26, v26, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v14, v13
	v_add_f32_e32 v35, v25, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v37, 0, v25 :: v_dual_add_f32 v28, v32, v26
	v_cndmask_b32_e32 v34, v28, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v34
	v_cndmask_b32_e64 v31, 0, 0x37000000, vcc_lo
	v_sub_f32_e32 v15, v34, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, 0x3fb8aa3b, v15
	v_rndne_f32_e32 v21, v19
	v_fma_f32 v20, 0x3fb8aa3b, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v19, v21 :: v_dual_sub_f32 v19, v25, v30
	v_fmac_f32_e32 v20, 0x32a5705f, v15
	v_fma_f32 v30, v16, v17, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v5, v5, v19 :: v_dual_add_f32 v14, v14, v20
	v_add_f32_e32 v20, v6, v6
	v_fmac_f32_e32 v30, v16, v13
	v_fma_f32 v13, v25, 2.0, -v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v37, 2.0, v5
	v_fma_f32 v5, v22, v22, -v29
	v_exp_f32_e32 v14, v14
	v_dual_sub_f32 v16, v28, v32 :: v_dual_add_f32 v13, v13, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v5, v22, v20
	v_fma_f32 v20, 0x3f317218, v12, -v23
	v_sub_f32_e32 v16, v26, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0xb102e308, v12
	v_sub_f32_e32 v10, v24, v10
	v_fmac_f32_e32 v30, v10, v17
	v_cvt_i32_f32_e32 v10, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v17, v27, v30
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v34|
	v_ldexp_f32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v35, v13 :: v_dual_sub_f32 v21, v17, v27
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	v_add_f32_e32 v16, v31, v16
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v35, 0x204
	v_cndmask_b32_e32 v19, v14, v35, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	v_sub_f32_e32 v14, v14, v35
	v_cndmask_b32_e32 v10, 0x7f800000, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v19
	v_sub_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v16, v10, v16, v10
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v10
	v_sub_f32_e32 v14, v19, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v16, v10, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v19|
	v_add_f32_e32 v19, v18, v17
	v_cndmask_b32_e64 v10, 0x7f800000, |v10|, s2
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v15, v13 :: v_dual_cndmask_b32 v8, 0, v10
	v_sub_f32_e32 v10, v19, v18
	v_sub_f32_e32 v10, v17, v10
	v_add_f32_e32 v17, v29, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v32, v22, v17
	v_sub_f32_e32 v26, v17, v29
	v_fmaak_f32 v12, s4, v17, 0x3e91f4c4
	v_fma_f32 v34, v17, v22, -v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v5, v5, v26 :: v_dual_sub_f32 v18, v30, v21
	v_fmaak_f32 v12, v17, v12, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v21, v23, v20 :: v_dual_fmac_f32 v34, v17, v6
	v_ldexp_f32 v6, v6, 1
	v_dual_add_f32 v11, v11, v18 :: v_dual_add_f32 v18, v33, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v27, v17, v12 :: v_dual_add_f32 v10, v11, v10
	v_sub_f32_e32 v25, v18, v33
	v_mul_f32_e32 v29, v18, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v24, v19, v10 :: v_dual_sub_f32 v9, v9, v25
	v_fma_f32 v25, v17, v12, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v28, v21, v24
	v_add_f32_e32 v26, v9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v25, v5, v12 :: v_dual_mul_f32 v16, 0x3fb8aa3b, v14
	v_sub_f32_e32 v12, v21, v23
	v_sub_f32_e32 v30, v28, v21
	v_dual_sub_f32 v19, v24, v19 :: v_dual_fmac_f32 v34, v5, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v15, 0x3fb8aa3b, v14, -v16
	v_rndne_f32_e32 v11, v16
	v_sub_f32_e32 v23, v28, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v20, v12 :: v_dual_fmac_f32 v15, 0x32a5705f, v14
	v_sub_f32_e32 v16, v16, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v21, v23
	v_cvt_i32_f32_e32 v11, v11
	v_add_f32_e32 v15, v16, v15
	v_fma_f32 v16, v18, v18, -v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v18, v26
	v_add_f32_e32 v26, v27, v25
	v_sub_f32_e32 v21, v26, v27
	v_add_f32_e32 v23, 0x3f2aaaaa, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v25, v21
	v_add_f32_e32 v25, 0xbf2aaaaa, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, 0x31739010, v21
	v_sub_f32_e32 v25, v26, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v17, v21, v25 :: v_dual_sub_f32 v10, v10, v19
	v_add_f32_e32 v19, v29, v16
	v_add_f32_e32 v27, v12, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v31, s4, v19, 0x3e91f4c4
	v_sub_f32_e32 v33, v27, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v31, v19, v31, 0x3ecccdef
	v_sub_f32_e32 v35, v27, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v5, v12, v35 :: v_dual_add_f32 v12, v23, v17
	v_sub_f32_e32 v26, v19, v29
	v_mul_f32_e32 v29, v19, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v23, v12
	v_fma_f32 v21, v19, v31, -v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v17, v17, v23 :: v_dual_sub_f32 v16, v16, v26
	v_fmac_f32_e32 v21, v16, v31
	v_sub_f32_e32 v24, v24, v30
	v_mul_f32_e32 v30, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v20, v24, v20
	v_add_f32_e32 v24, v29, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v24, v29
	v_add_f32_e32 v29, 0x3f2aaaaa, v24
	v_sub_f32_e32 v21, v21, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v23, 0xbf2aaaaa, v29
	v_add_f32_e32 v21, 0x31739010, v21
	v_sub_f32_e32 v10, v10, v33
	v_fma_f32 v33, v19, v18, -v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v23, v24, v23
	v_add_f32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v33, v19, v9
	v_add_f32_e32 v19, v21, v23
	v_add_f32_e32 v25, v32, v34
	v_ldexp_f32 v9, v9, 1
	v_ldexp_f32 v21, v22, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v26, v25, v12
	v_sub_f32_e32 v10, v25, v32
	v_frexp_exp_i32_f32_e32 v32, v3
	v_fma_f32 v31, v25, v12, -v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e64 v32, vcc_lo, 0, v32, s1
	v_fmac_f32_e32 v31, v25, v17
	v_dual_fmac_f32 v33, v16, v18 :: v_dual_add_f32 v16, v27, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v17, v32
	v_dual_add_f32 v23, v28, v16 :: v_dual_sub_f32 v10, v34, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v31, v10, v12 :: v_dual_add_f32 v12, v29, v19
	v_add_f32_e32 v22, v26, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v29, v12
	v_add_f32_e32 v29, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v19, v19, v24 :: v_dual_add_f32 v20, v30, v33
	v_dual_sub_f32 v26, v22, v26 :: v_dual_sub_f32 v21, v29, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, v20, v12
	v_sub_f32_e32 v30, v20, v30
	v_fma_f32 v24, v20, v12, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v30, v33, v30
	v_dual_fmac_f32 v24, v20, v19 :: v_dual_sub_f32 v19, v31, v26
	v_sub_f32_e32 v20, v22, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v24, v30, v12
	v_dual_add_f32 v6, v6, v19 :: v_dual_sub_f32 v19, v23, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v20
	v_mul_f32_e32 v10, 0x3f317218, v17
	v_fma_f32 v27, 0x3f317218, v17, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, 0xb102e308, v17
	v_frexp_exp_i32_f32_e32 v17, v4
	v_subrev_co_ci_u32_e64 v12, vcc_lo, 0, v17, s0
	v_ldexp_f32 v17, v18, 1
	v_add_f32_e32 v18, v25, v24
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v12, v12
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
	v_dual_add_f32 v21, v17, v18 :: v_dual_sub_f32 v16, v16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v21, v17
	v_dual_add_f32 v5, v5, v16 :: v_dual_sub_f32 v22, v18, v25
	v_add_f32_e32 v25, v29, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v18, v17 :: v_dual_sub_f32 v22, v24, v22
	v_add_f32_e32 v9, v9, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v17
	v_add_f32_e32 v22, v21, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v26, 0x3f317218, v12 :: v_dual_sub_f32 v21, v22, v21
	v_add_f32_e32 v20, v10, v27
	v_fma_f32 v24, 0x3f317218, v12, -v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v9, v21
	v_dual_add_f32 v19, v20, v25 :: v_dual_fmac_f32 v24, 0xb102e308, v12
	v_sub_f32_e32 v10, v20, v10
	v_sub_f32_e32 v12, v25, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v19, v20
	v_add_f32_e32 v18, v26, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v19, v16
	v_dual_sub_f32 v16, v25, v16 :: v_dual_sub_f32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v20, v18, v22
	v_add_f32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v25, v20, v18
	v_sub_f32_e32 v21, v22, v25
	v_dual_sub_f32 v17, v18, v26 :: v_dual_sub_f32 v26, v20, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v24, v17 :: v_dual_sub_f32 v6, v6, v12
	v_exp_f32_e32 v12, v15
	v_dual_add_f32 v15, v23, v5 :: v_dual_sub_f32 v18, v18, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_sub_f32 v23, v15, v23 :: v_dual_add_f32 v18, v21, v18
	v_add_f32_e32 v24, v15, v15
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v11, v12, v11
	v_sub_f32_e32 v5, v5, v23
	v_add_f32_e32 v23, v17, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v24, 0x204
	v_sub_f32_e32 v21, v23, v17
	v_sub_f32_e32 v10, v27, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v18, v23, v18 :: v_dual_sub_f32 v9, v9, v21
	v_add_f32_e32 v27, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v28, v27, v10
	v_add_f32_e32 v16, v27, v16
	v_sub_f32_e32 v29, v27, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v22, v19, v16
	v_sub_f32_e32 v6, v6, v28
	v_sub_f32_e32 v10, v10, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v22, v19
	v_add_f32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v16, v19
	v_fma_f32 v19, v15, 2.0, -v24
	v_dual_mul_f32 v15, 0, v15 :: v_dual_sub_f32 v16, v23, v21
	v_dual_add_f32 v6, v6, v10 :: v_dual_fmac_f32 v15, 2.0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v17, v16 :: v_dual_add_f32 v5, v22, v6
	v_dual_add_f32 v12, v19, v15 :: v_dual_add_f32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v5, v22
	v_dual_sub_f32 v6, v6, v15 :: v_dual_add_f32 v15, v5, v5
	v_add_f32_e32 v23, v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v23, v20
	v_sub_f32_e32 v10, v18, v16
	v_mul_f32_e32 v16, 0, v5
	v_fma_f32 v5, v5, 2.0, -v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v9, v10 :: v_dual_add_f32 v10, v24, v12
	v_dual_fmac_f32 v16, 2.0, v6 :: v_dual_add_f32 v17, v23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v18, v10, v24, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_add_f32_e32 v5, v5, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v17, v23
	v_dual_mul_f32 v16, 0, v17 :: v_dual_cndmask_b32 v11, 0x7f800000, v11
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v18
	v_dual_add_f32 v19, v15, v5 :: v_dual_sub_f32 v6, v9, v6
	v_add_f32_e32 v9, v17, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f32 v13, v11, v13, v11
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v15, 0x204
	v_fmac_f32_e32 v16, 2.0, v6
	v_fma_f32 v17, v17, 2.0, -v9
	v_sub_f32_e32 v20, v18, v14
	v_cndmask_b32_e32 v6, v19, v15, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v11
	v_sub_f32_e32 v15, v19, v15
	v_cndmask_b32_e32 v11, v13, v11, vcc_lo
	v_add_f32_e32 v13, v17, v16
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
	v_mul_f32_e32 v16, 0x3fb8aa3b, v20
	v_sub_f32_e32 v10, v10, v24
	v_add_f32_e64 v11, |v11|, |v11|
	v_add_f32_e32 v21, v9, v13
	v_cndmask_b32_e64 v17, 0, 0x37000000, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	v_fma_f32 v22, 0x3fb8aa3b, v20, -v16
	v_rndne_f32_e32 v23, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v10, v12, v10 :: v_dual_sub_f32 v25, v6, v17
	v_cndmask_b32_e32 v26, v21, v9, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
	v_fmac_f32_e32 v22, 0x32a5705f, v20
	v_dual_sub_f32 v16, v16, v23 :: v_dual_mul_f32 v27, 0x3fb8aa3b, v25
	v_sub_f32_e32 v5, v5, v15
	v_cndmask_b32_e32 v11, 0x7f800000, v11, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v26
	s_delay_alu instid0(VALU_DEP_4)
	v_rndne_f32_e32 v24, v27
	v_cndmask_b32_e64 v28, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e32 v7, 0, v11, vcc_lo
	v_add_f32_e32 v11, v16, v22
	v_fma_f32 v16, 0x3fb8aa3b, v25, -v27
	v_sub_f32_e32 v22, v26, v28
	v_sub_f32_e32 v27, v27, v24
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v18|
	v_exp_f32_e32 v11, v11
	v_fmac_f32_e32 v16, 0x32a5705f, v25
	v_mul_f32_e32 v12, 0x3fb8aa3b, v22
	v_cvt_i32_f32_e32 v18, v23
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
	v_add_f32_e32 v16, v27, v16
	v_fma_f32 v23, 0x3fb8aa3b, v22, -v12
	v_rndne_f32_e32 v29, v12
	v_add_f32_e32 v10, v14, v10
	v_ldexp_f32 v11, v11, v18
	v_exp_f32_e32 v14, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v23, 0x32a5705f, v22 :: v_dual_sub_f32 v12, v12, v29
	v_cvt_i32_f32_e32 v16, v24
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
	v_add_f32_e32 v7, v8, v7
	v_add_f32_e32 v12, v12, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, 0x7f800000, v11, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	v_exp_f32_e32 v12, v12
	v_ldexp_f32 v14, v14, v16
	v_sub_f32_e32 v6, v21, v9
	v_cvt_i32_f32_e32 v9, v29
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v25
	v_fma_f32 v10, v11, v10, v11
	v_sub_f32_e32 v6, v13, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v5, v17, v5 :: v_dual_cndmask_b32 v14, 0, v14
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v25
	v_ldexp_f32 v9, v12, v9
	v_cndmask_b32_e32 v12, 0x7f800000, v14, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v26|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v12, v5, v12
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v22
	v_dual_add_f32 v6, v28, v6 :: v_dual_cndmask_b32 v9, 0, v9
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v11
	v_fma_f32 v6, v9, v6, v9
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0x7f800000, |v10|, s0
	v_cndmask_b32_e32 v5, v5, v12, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v9
	v_mul_f32_e64 v5, 0x40400000, |v5|
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v6, 0x40a00000, |v6|
	v_cndmask_b32_e32 v2, 0, v8, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v3|
	v_dual_add_f32 v2, v2, v7 :: v_dual_cndmask_b32 v5, 0x7f800000, v5
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0, v5, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_dual_sub_f32 v2, v2, v3 :: v_dual_cndmask_b32 v5, 0x7f800000, v6
	v_cmp_neq_f32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0, v5, vcc_lo
	v_add_f32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, 0x41c00000, 0x41c00000, v2
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v2, 0x41c00000, v2
	v_mul_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v6, v5
	v_fmac_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v6, v5
	v_div_fmas_f32 v3, v3, v4, v6
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v2, v3, 0x41c00000, v2
	global_store_b32 v[0:1], v2, off
.LBB2_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9calcula_BPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 48
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9calcula_BPfS_i, .Lfunc_end2-_Z9calcula_BPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4708
; NumSgprs: 18
; NumVgprs: 48
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 48
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym sdata
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .offset:         0
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      - .address_space:  global
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    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10reduce_maxPfS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10reduce_maxPfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16calcula_B_sharedPfi
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _Z16calcula_B_sharedPfi.kd
    .uniform_work_group_size: 1
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    .vgpr_count:     47
    .vgpr_spill_count: 0
    .wavefront_size: 32
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    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9calcula_BPfS_i
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    .sgpr_spill_count: 0
    .symbol:         _Z9calcula_BPfS_i.kd
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    .vgpr_count:     48
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
