/*
 * Université Pierre et Marie Curie
 * Calcul de transport de neutrons
 * Version séquentielle
 */

#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>

#define OUTPUT_FILE "/tmp/absorbed.dat"


#define NB_BLOCK 256
#define NB_THREAD 256




#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
    printf("Error at %s:%d\n",__FILE__,__LINE__); \
    return EXIT_FAILURE;}} while(0)


// Déclaration dans le mémoire RAM du GPU
__device__ int device_r;
__device__ int device_b;
__device__ int device_t;


char info[] = "\
Usage:\n\
    neutron-seq H Nb C_c C_s\n\
\n\
    H  : épaisseur de la plaque\n\
    Nb : nombre d'échantillons\n\
    C_c: composante absorbante\n\
    C_s: componente diffusante\n\
\n\
Exemple d'execution : \n\
    neutron-seq 1.0 500000000 0.5 0.5\n\
";

__global__ void setup_kernel(curandState *state){

  int idx = threadIdx.x+blockDim.x*blockIdx.x;

  // On initialise chaque générateur avec une graine différente
  curand_init(idx, 0, 0, &state[idx]);

  /*On initialise chaque générateur avec la même graine mais avec une séquence différente
  Les générateur donneront pas les mêmes chiffres car chaque séquence est séparé de 2^67 nombres*/
  // curand_init(666, idx, 0, &state[idx]);
}

/*
 * notre gettimeofday()
 */
double my_gettimeofday(){
  struct timeval tmp_time;
  gettimeofday(&tmp_time, NULL);
  return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}


__global__ void neutron_gpu(curandState *state, float h, int n, float c_c, float c_s, float *result)
{

  // nombre de neutrons refléchis, absorbés et transmis
  int r, b, t;
  r = b = t = 0;

  // Tableau pour l'écriture de chaque thread
  __shared__ int R[NB_THREAD];
  __shared__ int B[NB_THREAD];
  __shared__ int T[NB_THREAD];


  float c;
  c = c_c + c_s;

  // distance parcourue par le neutron avant la collision
  float L;
  // direction du neutron (0 <= d <= PI)
  float d;
  // variable aléatoire uniforme
  float u;
  // position de la particule (0 <= x <= h)
  float x;

  int idx;
  idx = threadIdx.x + blockIdx.x * blockDim.x;
  // On copie le générateur sur le registre pour plus d'efficacité
  curandState localState = state[idx];

  /* code GPU */
  while(idx < n)
  {
    d = 0.0;
    x = 0.0;

    while(1)
    {
      u = curand_uniform(&localState);
      L = -(1 / c) * log(u);
      x = x + L * cos(d);
      if (x < 0)
      {
        r++;
        break;
      }
      else if (x >= h)
      {
        t++;
        break;
      }
      else if ((u = curand_uniform(&localState)) < c_c / c)
      {
        b++;
        result[idx] = x;
        break;
      }
      else
      {
        u = curand_uniform(&localState);
        d = u * M_PI;
      }
    }

    idx+= blockDim.x * gridDim.x;
  }


  // On stock r,b,t dans le tableau
  R[threadIdx.x] = r;
  B[threadIdx.x] = b;
  T[threadIdx.x] = t;

  // Synchronisation avant qu'un thread calcule la somme totale
  __syncthreads();

  // Reduction des tableaux
  for(unsigned int s = blockDim.x/2; s > 0; s = s/2)
  {
    if(threadIdx.x < s)
    {
      R[threadIdx.x] += R[threadIdx.x + s];
      B[threadIdx.x] += B[threadIdx.x + s];
      T[threadIdx.x] += T[threadIdx.x + s];
    }
    __syncthreads();
  }


  // Seul le thread 0 d'une bloc va additionner l'ensemble des valeurs
  if(threadIdx.x == 0)
  {
    atomicAdd(&device_r,R[0]);
    atomicAdd(&device_b,B[0]);
    atomicAdd(&device_t,T[0]);
  }
}

/*
 * main()
 */
int main(int argc, char *argv[]) {

  // La distance moyenne entre les interactions neutron/atome est 1/c. 
  // c_c et c_s sont les composantes absorbantes et diffusantes de c. 
  float c_c, c_s;
  // épaisseur de la plaque
  float h;
  // nombre d'échantillons
  int n;
  // chronometrage
  cudaEvent_t start, finish;
  cudaEventCreate(&start);
  cudaEventCreate(&finish);
  if( argc == 1)
    fprintf( stderr, "%s\n", info);

  // valeurs par defaut
  h = 1.0;
  n = 500000000;
  c_c = 0.5;
  c_s = 0.5;

  // recuperation des parametres
  if (argc > 1)
    h = atof(argv[1]);
  if (argc > 2)
    n = atoi(argv[2]);
  if (argc > 3)
    c_c = atof(argv[3]);
  if (argc > 4)
    c_s = atof(argv[4]);

  // affichage des parametres pour verificatrion
  printf("Épaisseur de la plaque : %4.g\n", h);
  printf("Nombre d'échantillons  : %d\n", n);
  printf("C_c : %g\n", c_c);
  printf("C_s : %g\n", c_s);

  //Allocation mémoire du résultat côté CPU
  float *host_absorbed;
  host_absorbed = (float *) calloc(n, sizeof(float));

  int r,b,t;

  //Allocation mémoire du résultat côté GPU
  float *device_absorbed;
  cudaMalloc((void **)&device_absorbed, n*sizeof(float));
  cudaMemset(device_absorbed,0,n*sizeof(float));

  // Allocation mémoire par le CPU du tableau de générateur pseudo-aléatoire
  curandState *d_state;
  CUDA_CALL(cudaMalloc((void **)&d_state, NB_BLOCK*NB_THREAD*sizeof(curandState)));

  // debut du chronometrage
  cudaEventRecord(start, 0);


  // On initialise les générateurs
  setup_kernel<<<NB_BLOCK,NB_THREAD>>>(d_state);

  neutron_gpu<<<NB_BLOCK,NB_THREAD>>>(d_state, h, n, c_c, c_s, device_absorbed);

  cudaMemcpy(host_absorbed,device_absorbed,n*sizeof(float),cudaMemcpyDeviceToHost);

  cudaMemcpyFromSymbol(&r, device_r, sizeof(int),0);  
  cudaMemcpyFromSymbol(&b, device_b, sizeof(int),0); 
  cudaMemcpyFromSymbol(&t, device_t, sizeof(int),0); 

  // fin du chronometrage
  cudaEventRecord(finish, 0);
  cudaEventSynchronize(finish);
  float elapsedTime;
  cudaEventElapsedTime(&elapsedTime, start, finish);

  printf("r=%d, b=%d, t=%d\n",r,b,t);
  printf("\nPourcentage des neutrons refléchis : %4.2g\n", (float) r / (float) n);
  printf("Pourcentage des neutrons absorbés : %4.2g\n", (float) b / (float) n);
  printf("Pourcentage des neutrons transmis : %4.2g\n", (float) t / (float) n);

  printf("\nTemps total de calcul: %.8g sec\n", elapsedTime/1000.0);
  printf("Millions de neutrons /s: %.2g\n", (double) n / ((elapsedTime/1000.0)*1e6));

  // ouverture du fichier pour ecrire les positions des neutrons absorbés
  FILE *f_handle = fopen(OUTPUT_FILE, "w");
  if (!f_handle) {
    fprintf(stderr, "Cannot open " OUTPUT_FILE "\n");
    exit(EXIT_FAILURE);
  }

  for (int j = 0; j < b; j++)
    fprintf(f_handle, "%f\n", host_absorbed[j]);

  // fermeture du fichier
  fclose(f_handle);
  printf("Result written in " OUTPUT_FILE "\n"); 

  cudaFree(d_state);
  cudaFree(device_absorbed);
  free(host_absorbed);

  return EXIT_SUCCESS;
}


	.file	"tmpxft_00345426_00000000-6_neutron_GPU.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2245:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2245:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15my_gettimeofdayv
	.type	_Z15my_gettimeofdayv, @function
_Z15my_gettimeofdayv:
.LFB2241:
	.cfi_startproc
	endbr64
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	xorl	%esi, %esi
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	gettimeofday@PLT
	fildq	32(%rsp)
	fldt	.LC0(%rip)
	fmulp	%st, %st(1)
	fildq	24(%rsp)
	faddp	%st, %st(1)
	fstpl	8(%rsp)
	movsd	8(%rsp), %xmm0
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L3
	call	__stack_chk_fail@PLT
.L3:
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2241:
	.size	_Z15my_gettimeofdayv, .-_Z15my_gettimeofdayv
	.globl	_Z50__device_stub__Z12setup_kernelP17curandStateXORWOWP17curandStateXORWOW
	.type	_Z50__device_stub__Z12setup_kernelP17curandStateXORWOWP17curandStateXORWOW, @function
_Z50__device_stub__Z12setup_kernelP17curandStateXORWOWP17curandStateXORWOW:
.LFB2267:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z12setup_kernelP17curandStateXORWOW(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L6:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2267:
	.size	_Z50__device_stub__Z12setup_kernelP17curandStateXORWOWP17curandStateXORWOW, .-_Z50__device_stub__Z12setup_kernelP17curandStateXORWOWP17curandStateXORWOW
	.globl	_Z12setup_kernelP17curandStateXORWOW
	.type	_Z12setup_kernelP17curandStateXORWOW, @function
_Z12setup_kernelP17curandStateXORWOW:
.LFB2268:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z12setup_kernelP17curandStateXORWOWP17curandStateXORWOW
	.cfi_endproc
.LFE2268:
	.size	_Z12setup_kernelP17curandStateXORWOW, .-_Z12setup_kernelP17curandStateXORWOW
	.globl	_Z55__device_stub__Z11neutron_gpuP17curandStateXORWOWfiffPfP17curandStateXORWOWfiffPf
	.type	_Z55__device_stub__Z11neutron_gpuP17curandStateXORWOWfiffPfP17curandStateXORWOWfiffPf, @function
_Z55__device_stub__Z11neutron_gpuP17curandStateXORWOWfiffPfP17curandStateXORWOWfiffPf:
.LFB2269:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movl	%esi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	40(%rsp), %rdx
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 12(%rsp)
	movss	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z11neutron_gpuP17curandStateXORWOWfiffPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L11:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2269:
	.size	_Z55__device_stub__Z11neutron_gpuP17curandStateXORWOWfiffPfP17curandStateXORWOWfiffPf, .-_Z55__device_stub__Z11neutron_gpuP17curandStateXORWOWfiffPfP17curandStateXORWOWfiffPf
	.globl	_Z11neutron_gpuP17curandStateXORWOWfiffPf
	.type	_Z11neutron_gpuP17curandStateXORWOWfiffPf, @function
_Z11neutron_gpuP17curandStateXORWOWfiffPf:
.LFB2270:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z11neutron_gpuP17curandStateXORWOWfiffPfP17curandStateXORWOWfiffPf
	.cfi_endproc
.LFE2270:
	.size	_Z11neutron_gpuP17curandStateXORWOWfiffPf, .-_Z11neutron_gpuP17curandStateXORWOWfiffPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"%s\n"
.LC5:
	.string	"\303\211paisseur de la plaque : %4.g\n"
.LC6:
	.string	"Nombre d'\303\251chantillons  : %d\n"
.LC7:
	.string	"C_c : %g\n"
.LC8:
	.string	"C_s : %g\n"
.LC9:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/RenGeng/GPU_Neutron/master/GPU/neutron_GPU.cu"
.LC10:
	.string	"Error at %s:%d\n"
.LC11:
	.string	"r=%d, b=%d, t=%d\n"
.LC12:
	.string	"\nPourcentage des neutrons refl\303\251chis : %4.2g\n"
.LC13:
	.string	"Pourcentage des neutrons absorb\303\251s : %4.2g\n"
.LC14:
	.string	"Pourcentage des neutrons transmis : %4.2g\n"
.LC16:
	.string	"\nTemps total de calcul: %.8g sec\n"
.LC18:
	.string	"Millions de neutrons /s: %.2g\n"
.LC19:
	.string	"w"
.LC20:
	.string	"/tmp/absorbed.dat"
.LC21:
	.string	"Cannot open /tmp/absorbed.dat\n"
.LC22:
	.string	"%f\n"
.LC23:
	.string	"Result written in /tmp/absorbed.dat\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2242:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%edi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$104, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	cmpl	$1, %r12d
	jne	.L17
	movq	stderr(%rip), %rdi
	leaq	info(%rip), %rcx
	leaq	.LC4(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	jmp	.L18
.L17:
	jle	.L18
	movq	8(%rbp), %rdi
	call	atof@PLT
	cvtsd2ss	%xmm0, %xmm3
	movd	%xmm3, %r13d
	cmpl	$2, %r12d
	je	.L27
	movq	16(%rbp), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
	cmpl	$3, %r12d
	je	.L28
	movq	24(%rbp), %rdi
	call	atof@PLT
	movss	.LC2(%rip), %xmm2
	cvtsd2ss	%xmm0, %xmm1
	cmpl	$4, %r12d
	je	.L19
	movq	32(%rbp), %rdi
	movss	%xmm1, 4(%rsp)
	call	atof@PLT
	movss	4(%rsp), %xmm1
	cvtsd2ss	%xmm0, %xmm2
	jmp	.L19
.L27:
	movl	$500000000, %ebx
.L28:
	movss	.LC2(%rip), %xmm1
	movaps	%xmm1, %xmm2
.L19:
	movd	%r13d, %xmm4
	movl	$2, %edi
	movb	$1, %al
	movslq	%ebx, %rbp
	leaq	.LC5(%rip), %rsi
	cvtss2sd	%xmm4, %xmm0
	movss	%xmm2, 12(%rsp)
	movss	%xmm1, 4(%rsp)
	call	__printf_chk@PLT
	movl	%ebx, %edx
	leaq	.LC6(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movss	4(%rsp), %xmm1
	leaq	.LC7(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm1, %xmm0
	movss	%xmm1, 8(%rsp)
	call	__printf_chk@PLT
	movss	12(%rsp), %xmm2
	leaq	.LC8(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	movss	%xmm2, 4(%rsp)
	cvtss2sd	%xmm2, %xmm0
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	movl	$4, %esi
	salq	$2, %rbp
	call	calloc@PLT
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	movq	%rax, %r12
	call	cudaMalloc@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rbp, %rdx
	call	cudaMemset@PLT
	leaq	56(%rsp), %rdi
	movl	$3145728, %esi
	call	cudaMalloc@PLT
	movss	4(%rsp), %xmm2
	movss	8(%rsp), %xmm1
	testl	%eax, %eax
	je	.L20
	movl	$223, %ecx
	leaq	.LC9(%rip), %rdx
	leaq	.LC10(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L16
.L20:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	movss	%xmm2, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	call	cudaEventRecord@PLT
	movl	$16777217, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 84(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 76(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	4(%rsp), %xmm1
	movss	8(%rsp), %xmm2
	testl	%eax, %eax
	jne	.L22
	movq	56(%rsp), %rdi
	call	_Z50__device_stub__Z12setup_kernelP17curandStateXORWOWP17curandStateXORWOW
	movss	8(%rsp), %xmm2
	movss	4(%rsp), %xmm1
.L22:
	movl	$16777217, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$8, %rdi
	movl	$1, %esi
	movss	%xmm2, 8(%rsp)
	movq	%rdi, %rdx
	movss	%xmm1, 4(%rsp)
	movq	%rdi, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	4(%rsp), %xmm1
	movss	8(%rsp), %xmm2
	testl	%eax, %eax
	jne	.L23
	movq	48(%rsp), %rdx
	movq	56(%rsp), %rdi
	movl	%ebx, %esi
	movd	%r13d, %xmm0
	call	_Z55__device_stub__Z11neutron_gpuP17curandStateXORWOWfiffPfP17curandStateXORWOWfiffPf
.L23:
	movq	48(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%ebp, %ebp
	leaq	.LC22(%rip), %r13
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	movl	$2, %r8d
	xorl	%ecx, %ecx
	movl	$4, %edx
	leaq	_ZL8device_r(%rip), %rsi
	call	cudaMemcpyFromSymbol@PLT
	leaq	28(%rsp), %rdi
	movl	$2, %r8d
	xorl	%ecx, %ecx
	movl	$4, %edx
	leaq	_ZL8device_b(%rip), %rsi
	call	cudaMemcpyFromSymbol@PLT
	movl	$2, %r8d
	xorl	%ecx, %ecx
	movl	$4, %edx
	leaq	64(%rsp), %rdi
	leaq	_ZL8device_t(%rip), %rsi
	call	cudaMemcpyFromSymbol@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	76(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	64(%rsp), %r8d
	movl	28(%rsp), %ecx
	xorl	%eax, %eax
	movl	24(%rsp), %edx
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	cvtsi2ssl	%ebx, %xmm4
	movl	$2, %edi
	movb	$1, %al
	cvtsi2ssl	24(%rsp), %xmm0
	leaq	.LC12(%rip), %rsi
	movss	%xmm4, 4(%rsp)
	divss	%xmm4, %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	leaq	.LC13(%rip), %rsi
	movb	$1, %al
	cvtsi2ssl	28(%rsp), %xmm0
	divss	4(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2ssl	64(%rsp), %xmm0
	divss	4(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	76(%rsp), %xmm0
	divsd	.LC15(%rip), %xmm0
	call	__printf_chk@PLT
	movb	$1, %al
	cvtss2sd	76(%rsp), %xmm1
	cvtsi2sdl	%ebx, %xmm0
	movl	$2, %edi
	divsd	.LC15(%rip), %xmm1
	mulsd	.LC17(%rip), %xmm1
	leaq	.LC18(%rip), %rsi
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	leaq	.LC19(%rip), %rsi
	leaq	.LC20(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	.L24
	movq	stderr(%rip), %rdi
	leaq	.LC21(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L24:
	cmpl	%ebp, 28(%rsp)
	jle	.L33
	movq	%r13, %rdx
	movl	$2, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	cvtss2sd	(%r12,%rbp,4), %xmm0
	call	__fprintf_chk@PLT
	incq	%rbp
	jmp	.L24
.L33:
	movq	%rbx, %rdi
	call	fclose@PLT
	leaq	.LC23(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	xorl	%eax, %eax
	jmp	.L16
.L18:
	movss	.LC3(%rip), %xmm3
	movl	$500000000, %ebx
	movd	%xmm3, %r13d
	jmp	.L28
.L16:
	movq	88(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$104, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2242:
	.size	main, .-main
	.section	.rodata.str1.1
.LC24:
	.string	"_Z11neutron_gpuP17curandStateXORWOWfiffPf"
.LC25:
	.string	"_Z12setup_kernelP17curandStateXORWOW"
.LC26:
	.string	"precalc_xorwow_matrix"
.LC27:
	.string	"precalc_xorwow_offset_matrix"
.LC28:
	.string	"mrg32k3aM1"
.LC29:
	.string	"mrg32k3aM2"
.LC30:
	.string	"mrg32k3aM1SubSeq"
.LC31:
	.string	"mrg32k3aM2SubSeq"
.LC32:
	.string	"mrg32k3aM1Seq"
.LC33:
	.string	"mrg32k3aM2Seq"
.LC34:
	.string	"__cr_lgamma_table"
.LC35:
	.string	"device_r"
.LC36:
	.string	"device_b"
.LC37:
	.string	"device_t"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2272:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11neutron_gpuP17curandStateXORWOWfiffPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12setup_kernelP17curandStateXORWOW(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC28(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC29(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC30(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC31(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC33(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC34(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC35(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL8device_r(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC36(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL8device_b(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL8device_t(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2272:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	info
	.data
	.align 32
	.type	info, @object
	.size	info, 227
info:
	.string	"Usage:\n    neutron-seq H Nb C_c C_s\n\n    H  : \303\251paisseur de la plaque\n    Nb : nombre d'\303\251chantillons\n    C_c: composante absorbante\n    C_s: componente diffusante\n\nExemple d'execution : \n    neutron-seq 1.0 500000000 0.5 0.5\n"
	.local	_ZL8device_t
	.comm	_ZL8device_t,4,4
	.local	_ZL8device_b
	.comm	_ZL8device_b,4,4
	.local	_ZL8device_r
	.comm	_ZL8device_r,4,4
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC0:
	.long	-1351849546
	.long	-2043167483
	.long	16363
	.long	0
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	1056964608
	.align 4
.LC3:
	.long	1065353216
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC15:
	.long	0
	.long	1083129856
	.align 8
.LC17:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * Université Pierre et Marie Curie
 * Calcul de transport de neutrons
 * Version séquentielle
 */

#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>

#define OUTPUT_FILE "/tmp/absorbed.dat"


#define NB_BLOCK 256
#define NB_THREAD 256




#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
    printf("Error at %s:%d\n",__FILE__,__LINE__); \
    return EXIT_FAILURE;}} while(0)


// Déclaration dans le mémoire RAM du GPU
__device__ int device_r;
__device__ int device_b;
__device__ int device_t;


char info[] = "\
Usage:\n\
    neutron-seq H Nb C_c C_s\n\
\n\
    H  : épaisseur de la plaque\n\
    Nb : nombre d'échantillons\n\
    C_c: composante absorbante\n\
    C_s: componente diffusante\n\
\n\
Exemple d'execution : \n\
    neutron-seq 1.0 500000000 0.5 0.5\n\
";

__global__ void setup_kernel(hiprandState *state){

  int idx = threadIdx.x+blockDim.x*blockIdx.x;

  // On initialise chaque générateur avec une graine différente
  hiprand_init(idx, 0, 0, &state[idx]);

  /*On initialise chaque générateur avec la même graine mais avec une séquence différente
  Les générateur donneront pas les mêmes chiffres car chaque séquence est séparé de 2^67 nombres*/
  // curand_init(666, idx, 0, &state[idx]);
}

/*
 * notre gettimeofday()
 */
double my_gettimeofday(){
  struct timeval tmp_time;
  gettimeofday(&tmp_time, NULL);
  return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}


__global__ void neutron_gpu(hiprandState *state, float h, int n, float c_c, float c_s, float *result)
{

  // nombre de neutrons refléchis, absorbés et transmis
  int r, b, t;
  r = b = t = 0;

  // Tableau pour l'écriture de chaque thread
  __shared__ int R[NB_THREAD];
  __shared__ int B[NB_THREAD];
  __shared__ int T[NB_THREAD];


  float c;
  c = c_c + c_s;

  // distance parcourue par le neutron avant la collision
  float L;
  // direction du neutron (0 <= d <= PI)
  float d;
  // variable aléatoire uniforme
  float u;
  // position de la particule (0 <= x <= h)
  float x;

  int idx;
  idx = threadIdx.x + blockIdx.x * blockDim.x;
  // On copie le générateur sur le registre pour plus d'efficacité
  hiprandState localState = state[idx];

  /* code GPU */
  while(idx < n)
  {
    d = 0.0;
    x = 0.0;

    while(1)
    {
      u = hiprand_uniform(&localState);
      L = -(1 / c) * log(u);
      x = x + L * cos(d);
      if (x < 0)
      {
        r++;
        break;
      }
      else if (x >= h)
      {
        t++;
        break;
      }
      else if ((u = hiprand_uniform(&localState)) < c_c / c)
      {
        b++;
        result[idx] = x;
        break;
      }
      else
      {
        u = hiprand_uniform(&localState);
        d = u * M_PI;
      }
    }

    idx+= blockDim.x * gridDim.x;
  }


  // On stock r,b,t dans le tableau
  R[threadIdx.x] = r;
  B[threadIdx.x] = b;
  T[threadIdx.x] = t;

  // Synchronisation avant qu'un thread calcule la somme totale
  __syncthreads();

  // Reduction des tableaux
  for(unsigned int s = blockDim.x/2; s > 0; s = s/2)
  {
    if(threadIdx.x < s)
    {
      R[threadIdx.x] += R[threadIdx.x + s];
      B[threadIdx.x] += B[threadIdx.x + s];
      T[threadIdx.x] += T[threadIdx.x + s];
    }
    __syncthreads();
  }


  // Seul le thread 0 d'une bloc va additionner l'ensemble des valeurs
  if(threadIdx.x == 0)
  {
    atomicAdd(&device_r,R[0]);
    atomicAdd(&device_b,B[0]);
    atomicAdd(&device_t,T[0]);
  }
}

/*
 * main()
 */
int main(int argc, char *argv[]) {

  // La distance moyenne entre les interactions neutron/atome est 1/c. 
  // c_c et c_s sont les composantes absorbantes et diffusantes de c. 
  float c_c, c_s;
  // épaisseur de la plaque
  float h;
  // nombre d'échantillons
  int n;
  // chronometrage
  hipEvent_t start, finish;
  hipEventCreate(&start);
  hipEventCreate(&finish);
  if( argc == 1)
    fprintf( stderr, "%s\n", info);

  // valeurs par defaut
  h = 1.0;
  n = 500000000;
  c_c = 0.5;
  c_s = 0.5;

  // recuperation des parametres
  if (argc > 1)
    h = atof(argv[1]);
  if (argc > 2)
    n = atoi(argv[2]);
  if (argc > 3)
    c_c = atof(argv[3]);
  if (argc > 4)
    c_s = atof(argv[4]);

  // affichage des parametres pour verificatrion
  printf("Épaisseur de la plaque : %4.g\n", h);
  printf("Nombre d'échantillons  : %d\n", n);
  printf("C_c : %g\n", c_c);
  printf("C_s : %g\n", c_s);

  //Allocation mémoire du résultat côté CPU
  float *host_absorbed;
  host_absorbed = (float *) calloc(n, sizeof(float));

  int r,b,t;

  //Allocation mémoire du résultat côté GPU
  float *device_absorbed;
  hipMalloc((void **)&device_absorbed, n*sizeof(float));
  hipMemset(device_absorbed,0,n*sizeof(float));

  // Allocation mémoire par le CPU du tableau de générateur pseudo-aléatoire
  hiprandState *d_state;
  CUDA_CALL(hipMalloc((void **)&d_state, NB_BLOCK*NB_THREAD*sizeof(hiprandState)));

  // debut du chronometrage
  hipEventRecord(start, 0);


  // On initialise les générateurs
  setup_kernel<<<NB_BLOCK,NB_THREAD>>>(d_state);

  neutron_gpu<<<NB_BLOCK,NB_THREAD>>>(d_state, h, n, c_c, c_s, device_absorbed);

  hipMemcpy(host_absorbed,device_absorbed,n*sizeof(float),hipMemcpyDeviceToHost);

  hipMemcpyFromSymbol(&r, HIP_SYMBOL(device_r), sizeof(int),0);  
  hipMemcpyFromSymbol(&b, HIP_SYMBOL(device_b), sizeof(int),0); 
  hipMemcpyFromSymbol(&t, HIP_SYMBOL(device_t), sizeof(int),0); 

  // fin du chronometrage
  hipEventRecord(finish, 0);
  hipEventSynchronize(finish);
  float elapsedTime;
  hipEventElapsedTime(&elapsedTime, start, finish);

  printf("r=%d, b=%d, t=%d\n",r,b,t);
  printf("\nPourcentage des neutrons refléchis : %4.2g\n", (float) r / (float) n);
  printf("Pourcentage des neutrons absorbés : %4.2g\n", (float) b / (float) n);
  printf("Pourcentage des neutrons transmis : %4.2g\n", (float) t / (float) n);

  printf("\nTemps total de calcul: %.8g sec\n", elapsedTime/1000.0);
  printf("Millions de neutrons /s: %.2g\n", (double) n / ((elapsedTime/1000.0)*1e6));

  // ouverture du fichier pour ecrire les positions des neutrons absorbés
  FILE *f_handle = fopen(OUTPUT_FILE, "w");
  if (!f_handle) {
    fprintf(stderr, "Cannot open " OUTPUT_FILE "\n");
    exit(EXIT_FAILURE);
  }

  for (int j = 0; j < b; j++)
    fprintf(f_handle, "%f\n", host_absorbed[j]);

  // fermeture du fichier
  fclose(f_handle);
  printf("Result written in " OUTPUT_FILE "\n"); 

  hipFree(d_state);
  hipFree(device_absorbed);
  free(host_absorbed);

  return EXIT_SUCCESS;
}


	.text
	.file	"neutron_GPU.hip"
	.globl	_Z27__device_stub__setup_kernelP12hiprandState # -- Begin function _Z27__device_stub__setup_kernelP12hiprandState
	.type	_Z27__device_stub__setup_kernelP12hiprandState,@function
_Z27__device_stub__setup_kernelP12hiprandState: # @_Z27__device_stub__setup_kernelP12hiprandState
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12setup_kernelP12hiprandState, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__setup_kernelP12hiprandState, .Lfunc_end0-_Z27__device_stub__setup_kernelP12hiprandState
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z15my_gettimeofdayv
.LCPI1_0:
	.quad	0x8637bd05af6c69b6              # x86_fp80 1.00000000000000000004E-6
	.short	0x3feb
	.zero	6
	.text
	.globl	_Z15my_gettimeofdayv
	.type	_Z15my_gettimeofdayv,@function
_Z15my_gettimeofdayv:                   # @_Z15my_gettimeofdayv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -16
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%rbx), %rax
	movq	8(%rbx), %rcx
	movq	%rax, 16(%rsp)
	fildll	16(%rsp)
	movq	%rcx, 24(%rsp)
	fildll	24(%rsp)
	fldt	.LCPI1_0(%rip)
	fmulp	%st, %st(1)
	faddp	%st, %st(1)
	fstpl	8(%rsp)
	movsd	8(%rsp), %xmm0                  # xmm0 = mem[0],zero
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z15my_gettimeofdayv, .Lfunc_end1-_Z15my_gettimeofdayv
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf # -- Begin function _Z26__device_stub__neutron_gpuP12hiprandStatefiffPf
	.type	_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf,@function
_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf: # @_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movss	%xmm1, (%rsi)
	movq	%rsp, %r8
	movss	%xmm2, (%r8)
	leaq	32(%rsp), %r9
	movq	%rdx, (%r9)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%r8, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11neutron_gpuP12hiprandStatefiffPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf, .Lfunc_end2-_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x3f800000                      # float 1
.LCPI3_1:
	.long	0x3f000000                      # float 0.5
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI3_2:
	.quad	0x408f400000000000              # double 1000
.LCPI3_3:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movl	%edi, %ebp
	leaq	48(%rsp), %rdi
	callq	hipEventCreate
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	cmpl	$1, %ebp
	je	.LBB3_23
# %bb.1:
	movl	$500000000, %ebx                # imm = 0x1DCD6500
	movss	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	jle	.LBB3_4
# %bb.2:
	movq	8(%r14), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm1
	cmpl	$2, %ebp
	jne	.LBB3_6
# %bb.3:
	movss	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	jmp	.LBB3_5
.LBB3_4:
	movss	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
.LBB3_5:                                # %.thread68
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	jmp	.LBB3_11
.LBB3_6:
	movss	%xmm1, 16(%rsp)                 # 4-byte Spill
	movq	16(%r14), %rdi
	callq	atoi
	movl	%eax, %ebx
	cmpl	$4, %ebp
	jb	.LBB3_9
# %bb.7:
	movq	24(%r14), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	cmpl	$4, %ebp
	je	.LBB3_10
# %bb.8:
	movq	32(%r14), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	jmp	.LBB3_10
.LBB3_9:
	movss	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
.LBB3_10:                               # %.thread68
	movss	16(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
.LBB3_11:                               # %.thread68
	movss	%xmm1, 16(%rsp)                 # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.2, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	movslq	%ebx, %r15
	movl	$4, %esi
	movq	%r15, %rdi
	callq	calloc
	movq	%rax, %r14
	shlq	$2, %r15
	leaq	32(%rsp), %r12
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	xorl	%esi, %esi
	movq	%r15, %rdx
	callq	hipMemset
	leaq	24(%rsp), %rdi
	movl	$3145728, %esi                  # imm = 0x300000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB3_13
# %bb.12:
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %esi
	movl	$223, %edx
	xorl	%eax, %eax
	callq	printf
	movl	$1, %eax
	jmp	.LBB3_22
.LBB3_13:
	movabsq	$4294967552, %r12               # imm = 0x100000100
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_15
# %bb.14:
	movq	24(%rsp), %rdi
	callq	_Z27__device_stub__setup_kernelP12hiprandState
.LBB3_15:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_17
# %bb.16:
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rdx
	movss	16(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%ebx, %esi
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	8(%rsp), %xmm2                  # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	callq	_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf
.LBB3_17:
	movq	32(%rsp), %rsi
	movq	%r14, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	68(%rsp), %rbp
	movl	$device_r, %esi
	movl	$4, %edx
	movq	%rbp, %rdi
	xorl	%ecx, %ecx
	movl	$2, %r8d
	callq	hipMemcpyFromSymbol
	leaq	20(%rsp), %r15
	movl	$device_b, %esi
	movl	$4, %edx
	movq	%r15, %rdi
	xorl	%ecx, %ecx
	movl	$2, %r8d
	callq	hipMemcpyFromSymbol
	leaq	64(%rsp), %r12
	movl	$device_t, %esi
	movl	$4, %edx
	movq	%r12, %rdi
	xorl	%ecx, %ecx
	movl	$2, %r8d
	callq	hipMemcpyFromSymbol
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	40(%rsp), %rdi
	callq	hipEventSynchronize
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	leaq	60(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventElapsedTime
	movl	(%rbp), %esi
	movl	(%r15), %edx
	movl	(%r12), %ecx
	movl	$.L.str.7, %edi
	xorl	%eax, %eax
	callq	printf
	xorps	%xmm0, %xmm0
	cvtsi2ssl	(%rbp), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ss	%ebx, %xmm1
	movss	%xmm1, 8(%rsp)                  # 4-byte Spill
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.8, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtsi2ssl	(%r15), %xmm0
	divss	8(%rsp), %xmm0                  # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtsi2ssl	(%r12), %xmm0
	divss	8(%rsp), %xmm0                  # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13), %xmm0
	divsd	.LCPI3_2(%rip), %xmm0
	movl	$.L.str.11, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ebx, %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	(%r13), %xmm1
	divsd	.LCPI3_2(%rip), %xmm1
	mulsd	.LCPI3_3(%rip), %xmm1
	divsd	%xmm1, %xmm0
	movl	$.L.str.12, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.13, %edi
	movl	$.L.str.14, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB3_24
# %bb.18:                               # %.preheader
	movq	%rax, %rbx
	cmpl	$0, 20(%rsp)
	jle	.LBB3_21
# %bb.19:                               # %.lr.ph.preheader
	xorl	%r15d, %r15d
.LBB3_20:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r15,4), %xmm0
	movl	$.L.str.16, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	movslq	20(%rsp), %rax
	cmpq	%rax, %r15
	jl	.LBB3_20
.LBB3_21:                               # %._crit_edge
	movq	%rbx, %rdi
	callq	fclose
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
.LBB3_22:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_23:                               # %.thread
	.cfi_def_cfa_offset 128
	movq	stderr(%rip), %rdi
	movl	$.L.str, %esi
	movl	$info, %edx
	xorl	%eax, %eax
	callq	fprintf
	movl	$500000000, %ebx                # imm = 0x1DCD6500
	movss	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movss	.LCPI3_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	jmp	.LBB3_11
.LBB3_24:
	movq	stderr(%rip), %rcx
	movl	$.L.str.15, %edi
	movl	$30, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$1, %edi
	callq	exit
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12setup_kernelP12hiprandState, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11neutron_gpuP12hiprandStatefiffPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$device_r, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$device_b, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$device_t, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	device_r,@object                # @device_r
	.local	device_r
	.comm	device_r,4,4
	.type	device_b,@object                # @device_b
	.local	device_b
	.comm	device_b,4,4
	.type	device_t,@object                # @device_t
	.local	device_t
	.comm	device_t,4,4
	.type	info,@object                    # @info
	.data
	.globl	info
	.p2align	4, 0x0
info:
	.asciz	"Usage:\n    neutron-seq H Nb C_c C_s\n\n    H  : \303\251paisseur de la plaque\n    Nb : nombre d'\303\251chantillons\n    C_c: composante absorbante\n    C_s: componente diffusante\n\nExemple d'execution : \n    neutron-seq 1.0 500000000 0.5 0.5\n"
	.size	info, 227

	.type	_Z12setup_kernelP12hiprandState,@object # @_Z12setup_kernelP12hiprandState
	.section	.rodata,"a",@progbits
	.globl	_Z12setup_kernelP12hiprandState
	.p2align	3, 0x0
_Z12setup_kernelP12hiprandState:
	.quad	_Z27__device_stub__setup_kernelP12hiprandState
	.size	_Z12setup_kernelP12hiprandState, 8

	.type	_Z11neutron_gpuP12hiprandStatefiffPf,@object # @_Z11neutron_gpuP12hiprandStatefiffPf
	.globl	_Z11neutron_gpuP12hiprandStatefiffPf
	.p2align	3, 0x0
_Z11neutron_gpuP12hiprandStatefiffPf:
	.quad	_Z26__device_stub__neutron_gpuP12hiprandStatefiffPf
	.size	_Z11neutron_gpuP12hiprandStatefiffPf, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%s\n"
	.size	.L.str, 4

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\303\211paisseur de la plaque : %4.g\n"
	.size	.L.str.1, 32

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Nombre d'\303\251chantillons  : %d\n"
	.size	.L.str.2, 30

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"C_c : %g\n"
	.size	.L.str.3, 10

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"C_s : %g\n"
	.size	.L.str.4, 10

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Error at %s:%d\n"
	.size	.L.str.5, 16

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/RenGeng/GPU_Neutron/master/GPU/neutron_GPU.hip"
	.size	.L.str.6, 109

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"r=%d, b=%d, t=%d\n"
	.size	.L.str.7, 18

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"\nPourcentage des neutrons refl\303\251chis : %4.2g\n"
	.size	.L.str.8, 46

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Pourcentage des neutrons absorb\303\251s : %4.2g\n"
	.size	.L.str.9, 44

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Pourcentage des neutrons transmis : %4.2g\n"
	.size	.L.str.10, 43

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"\nTemps total de calcul: %.8g sec\n"
	.size	.L.str.11, 34

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Millions de neutrons /s: %.2g\n"
	.size	.L.str.12, 31

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"/tmp/absorbed.dat"
	.size	.L.str.13, 18

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"w"
	.size	.L.str.14, 2

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"Cannot open /tmp/absorbed.dat\n"
	.size	.L.str.15, 31

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"%f\n"
	.size	.L.str.16, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12setup_kernelP12hiprandState"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11neutron_gpuP12hiprandStatefiffPf"
	.size	.L__unnamed_2, 37

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"device_r"
	.size	.L__unnamed_3, 9

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"device_b"
	.size	.L__unnamed_4, 9

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"device_t"
	.size	.L__unnamed_5, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Result written in /tmp/absorbed.dat"
	.size	.Lstr, 36

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__setup_kernelP12hiprandState
	.addrsig_sym _Z26__device_stub__neutron_gpuP12hiprandStatefiffPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym device_r
	.addrsig_sym device_b
	.addrsig_sym device_t
	.addrsig_sym info
	.addrsig_sym _Z12setup_kernelP12hiprandState
	.addrsig_sym _Z11neutron_gpuP12hiprandStatefiffPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12setup_kernelP12hiprandState ; -- Begin function _Z12setup_kernelP12hiprandState
	.globl	_Z12setup_kernelP12hiprandState
	.p2align	8
	.type	_Z12setup_kernelP12hiprandState,@function
_Z12setup_kernelP12hiprandState:        ; @_Z12setup_kernelP12hiprandState
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x14
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v2, 0x8a5d614f
	v_xor_b32_e32 v0, 0x2c7f967f, v1
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	v_mad_i64_i32 v[7:8], null, v1, 48, s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, 0x493c4aa1, v0
	v_cndmask_b32_e32 v4, 0xfa091aa4, v2, vcc_lo
	v_mov_b32_e32 v6, v5
	v_add_nc_u32_e32 v2, 0x1f123bb5, v4
	v_xor_b32_e32 v3, 0x5491333, v4
	v_add3_u32 v4, v9, v4, 0x64f0c9
	v_add_nc_u32_e32 v0, 0x75bcd15, v9
	v_xor_b32_e32 v1, 0x159a55e5, v9
	v_add_nc_u32_e32 v9, 0x583f19, v9
	s_clause 0x2
	global_store_b96 v[7:8], v[4:6], off
	global_store_b128 v[7:8], v[0:3], off offset:24
	global_store_b32 v[7:8], v9, off offset:40
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12setup_kernelP12hiprandState
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12setup_kernelP12hiprandState, .Lfunc_end0-_Z12setup_kernelP12hiprandState
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11neutron_gpuP12hiprandStatefiffPf ; -- Begin function _Z11neutron_gpuP12hiprandStatefiffPf
	.globl	_Z11neutron_gpuP12hiprandStatefiffPf
	.p2align	8
	.type	_Z11neutron_gpuP12hiprandStatefiffPf,@function
_Z11neutron_gpuP12hiprandStatefiffPf:   ; @_Z11neutron_gpuP12hiprandStatefiffPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_add_u32 s8, s0, 32
	s_addc_u32 s9, s1, 0
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s12, 0
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s15, s10, v[0:1]
	v_cmpx_gt_i32_e64 s5, v5
	s_cbranch_execz .LBB1_24
; %bb.1:                                ; %.preheader.lr.ph
	s_clause 0x1
	s_load_b64 s[14:15], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x18
	s_mov_b32 s13, 0xb94c1982
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[6:7], null, v5, 48, s[14:15]
	s_mov_b32 s14, 0x37d75334
	s_clause 0x2
	global_load_b32 v14, v[6:7], off offset:40
	global_load_b128 v[1:4], v[6:7], off offset:24
	global_load_b32 v8, v[6:7], off
	v_add_f32_e64 v6, s6, s7
	s_load_b32 s8, s[8:9], 0x0
	s_mov_b32 s9, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v7, null, v6, v6, 1.0
	v_div_scale_f32 v9, null, v6, v6, s6
	v_rcp_f32_e32 v10, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_f32_e32 v11, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v7, v10, 1.0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s8, s10
	v_fma_f32 v13, -v9, v11, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v12, v10
	v_div_scale_f32 v12, vcc_lo, 1.0, v6, 1.0
	v_fmac_f32_e32 v11, v13, v11
	v_div_scale_f32 v13, s0, s6, v6, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v15, v12, v10 :: v_dual_mul_f32 v16, v13, v11
	v_fma_f32 v17, -v7, v15, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v9, v16, v13
	v_dual_fmac_f32 v15, v17, v10 :: v_dual_fmac_f32 v16, v18, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v7, v15, v12
	v_fma_f32 v9, -v9, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v7, v7, v10, v15
	s_mov_b32 vcc_lo, s0
	v_mov_b32_e32 v10, 0
	v_div_fmas_f32 v9, v9, v11, v16
	v_mov_b32_e32 v11, 0
	v_div_fixup_f32 v12, v7, v6, 1.0
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_div_fixup_f32 v13, v9, v6, s6
	v_mov_b32_e32 v9, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x400921fb
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v15, v7 :: v_dual_add_nc_u32 v8, 0xb0f8a, v8
	v_mov_b32_e32 v16, v7
	s_mov_b32 s15, 0
                                        ; implicit-def: $sgpr18
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr17
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr6
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e64 0x48000000, |v16|
	s_xor_b32 s20, exec_lo, s1
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=2
	v_and_b32_e32 v22, 0x7fffffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v25, v22, s9, 0x800000
	v_lshrrev_b32_e32 v22, 23, v22
	v_mad_u64_u32 v[17:18], null, 0xfe5163ab, v25, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v23, 0xffffff88, v22
	v_cmp_lt_u32_e32 vcc_lo, 63, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v6, v18
	v_cndmask_b32_e64 v24, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v25, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v24, v24, v23
	v_mov_b32_e32 v6, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v24
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v25, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v26, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v26, v26, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v6, v20 :: v_dual_cndmask_b32 v17, v19, v17
	v_cmp_lt_u32_e64 s1, 31, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v25, v[6:7]
	v_mov_b32_e32 v6, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, v20, v18, vcc_lo
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v25, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v18, v17, s0
	v_mov_b32_e32 v6, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[6:7]
	v_mov_b32_e32 v6, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[6:7]
	v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v25, v22, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_add_nc_u32 v6, v6, v26
	v_dual_cndmask_b32 v22, v24, v22 :: v_dual_cndmask_b32 v21, v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v24, 32, v6
	v_cndmask_b32_e64 v20, v23, v25, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v22, v23, s0
	v_cndmask_b32_e64 v23, v25, v21, s0
	v_cndmask_b32_e64 v21, v21, v18, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v22, v20, s1
	v_cndmask_b32_e64 v20, v20, v23, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v23, v23, v21, s1
	v_cndmask_b32_e64 v17, v21, v17, s1
	v_alignbit_b32 v25, v22, v20, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v19, v20, v23, v24
	v_cndmask_b32_e32 v6, v25, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v18, v19, v20, vcc_lo
	v_alignbit_b32 v22, v23, v17, v24
	v_bfe_u32 v19, v6, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v6, v18, 30
	v_cndmask_b32_e32 v22, v22, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, 0, v19
	v_alignbit_b32 v18, v18, v22, 30
	v_alignbit_b32 v17, v22, v17, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v20, v20, v21
	v_xor_b32_e32 v18, v18, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v17, v17, v21
	v_lshrrev_b32_e32 v21, 29, v6
	v_clz_i32_u32_e32 v23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v21, 31, v21
	v_min_u32_e32 v23, 32, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, 0.5, v21
	v_sub_nc_u32_e32 v22, 31, v23
	v_lshlrev_b32_e32 v25, 23, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v20, v18, v22
	v_alignbit_b32 v17, v18, v17, v22
	v_sub_nc_u32_e32 v24, v24, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v20, v17, 9
	v_lshrrev_b32_e32 v20, 9, v20
	v_clz_i32_u32_e32 v22, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v22, 32, v22
	v_sub_nc_u32_e32 v26, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v18, v17, v26
	v_or_b32_e32 v18, v20, v24
	v_add_lshl_u32 v20, v22, v23, 23
	v_lshrrev_b32_e32 v17, 9, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, 0x3fc90fda, v18
	v_sub_nc_u32_e32 v17, v17, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0x3fc90fda, v18, -v22
	v_add_nc_u32_e32 v17, 0x33000000, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, 0x33a22168, v18
	v_or_b32_e32 v17, v17, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0x3fc90fda, v17
	v_lshrrev_b32_e32 v17, 30, v6
	v_dual_add_f32 v6, v22, v20 :: v_dual_add_nc_u32 v19, v19, v17
.LBB1_5:                                ; %Flow232
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_and_not1_saveexec_b32 s0, s20
; %bb.6:                                ;   in Loop: Header=BB1_3 Depth=2
	v_mul_f32_e64 v6, 0x3f22f983, |v16|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v17, v6
	v_fma_f32 v6, 0xbfc90fda, v17, |v16|
	v_cvt_i32_f32_e32 v19, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0xb3a22168, v17
	v_fmac_f32_e32 v6, 0xa7c234c4, v17
; %bb.7:                                ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_lshrrev_b32_e32 v17, 2, v1
	s_mov_b32 s1, -1
	s_and_not1_b32 s17, s17, exec_lo
	s_or_b32 s16, s16, exec_lo
	s_mov_b32 s0, exec_lo
	v_xor_b32_e32 v1, v17, v1
	v_lshlrev_b32_e32 v17, 4, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v18, 1, v1
	v_xor_b32_e32 v17, v17, v18
	v_add_nc_u32_e32 v18, 0xfffa783b, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v17, v17, v14, v1
	v_add_nc_u32_e32 v1, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, v1
	v_fmaak_f32 v1, 0x2f800000, v1, 0x2f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1
	v_cndmask_b32_e64 v20, 1.0, 0x4f800000, vcc_lo
	v_dual_mul_f32 v1, v1, v20 :: v_dual_mul_f32 v20, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_log_f32_e32 v1, v1
	v_fmaak_f32 v22, s13, v20, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v21, 0x3f317217, v1 :: v_dual_mul_f32 v22, v20, v22
	v_fmaak_f32 v23, s14, v20, 0xbab64f3b
	v_fma_f32 v24, 0x3f317217, v1, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v6, v6, v22 :: v_dual_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	v_lshlrev_b32_e32 v25, 30, v19
	v_dual_fmac_f32 v24, 0x3377d1cf, v1 :: v_dual_and_b32 v19, 1, v19
	v_cndmask_b32_e64 v22, 0, 0x41b17218, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmaak_f32 v23, v20, v23, 0xbf000004
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
	v_and_b32_e32 v25, 0x80000000, v25
	v_add_f32_e32 v21, v21, v24
                                        ; implicit-def: $vgpr24
	v_fma_f32 v20, v20, v23, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v21, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	v_sub_f32_e32 v1, v1, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, -v6, v20, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v16, 0x1f8
                                        ; implicit-def: $vgpr16
	v_mul_f32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v25, v6
	v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, -v1, v6, v15
                                        ; implicit-def: $vgpr6
	v_cmpx_ngt_f32_e32 0, v15
	s_cbranch_execz .LBB1_13
; %bb.8:                                ;   in Loop: Header=BB1_3 Depth=2
	s_mov_b32 s20, -1
	s_mov_b32 s21, -1
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr6
	v_cmpx_nle_f32_e32 s4, v15
	s_cbranch_execz .LBB1_12
; %bb.9:                                ;   in Loop: Header=BB1_3 Depth=2
	v_lshrrev_b32_e32 v1, 2, v2
	v_lshlrev_b32_e32 v6, 4, v17
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v2
	v_lshlrev_b32_e32 v16, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v16, v6
                                        ; implicit-def: $vgpr16
	v_xor3_b32 v19, v6, v1, v17
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v8, v19
	v_cvt_f32_u32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v1, 0x2f800000, v1, 0x2f800000
	v_cmpx_nlt_f32_e32 v1, v13
	s_cbranch_execz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_3 Depth=2
	v_lshrrev_b32_e32 v1, 2, v3
	v_lshlrev_b32_e32 v2, 4, v19
	s_xor_b32 s20, exec_lo, -1
                                        ; implicit-def: $vgpr18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v3
	v_lshlrev_b32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v3, v2
	v_xor3_b32 v6, v2, v1, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v8, v6, 0x587c5
	v_add_nc_u32_e32 v8, 0x10974f, v8
	v_cvt_f32_u32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v1, 0x2f800000, v1, 0x2f800000
	v_cvt_f64_f32_e32 v[1:2], v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[1:2], v[1:2], s[6:7]
	v_cvt_f32_f64_e32 v16, v[1:2]
.LBB1_11:                               ; %Flow236
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v24, v14
	s_xor_b32 s21, exec_lo, -1
	s_or_not1_b32 s20, s20, exec_lo
.LBB1_12:                               ; %Flow235
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s17, exec_lo
	s_and_b32 s17, s21, exec_lo
	s_and_not1_b32 s16, s16, exec_lo
	s_or_b32 s17, s1, s17
	s_or_not1_b32 s1, s20, exec_lo
.LBB1_13:                               ; %Flow234
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s1
	v_dual_mov_b32 v20, v2 :: v_dual_mov_b32 v21, v3
	v_dual_mov_b32 v22, v4 :: v_dual_mov_b32 v23, v14
	s_or_b32 s15, s0, s15
	v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v3, v17
	v_mov_b32_e32 v4, v19
	v_mov_b32_e32 v2, v24
	s_and_not1_b32 s0, s19, exec_lo
	s_and_b32 s1, s17, exec_lo
	s_and_not1_b32 s18, s18, exec_lo
	s_and_b32 s20, s16, exec_lo
	s_or_b32 s19, s0, s1
	s_or_b32 s18, s18, s20
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_3
; %bb.14:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_xor_b32 s0, s18, -1
	s_xor_b32 s1, s19, -1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr14
	s_and_saveexec_b32 s15, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s15
	s_cbranch_execz .LBB1_20
; %bb.15:                               ; %loop.exit.guard221
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_saveexec_b32 s15, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s15
	s_cbranch_execz .LBB1_17
; %bb.16:                               ;   in Loop: Header=BB1_2 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_nc_u32_e32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[5:6]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[1:2], v15, off
.LBB1_17:                               ; %Flow229
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_saveexec_b32 s1, s1
	v_dual_mov_b32 v1, v21 :: v_dual_mov_b32 v2, v22
	v_dual_mov_b32 v3, v23 :: v_dual_mov_b32 v4, v17
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.18:                               ;   in Loop: Header=BB1_2 Depth=1
	v_dual_mov_b32 v8, v18 :: v_dual_add_nc_u32 v11, 1, v11
	v_dual_mov_b32 v1, v20 :: v_dual_mov_b32 v2, v21
	v_dual_mov_b32 v3, v22 :: v_dual_mov_b32 v4, v23
	v_mov_b32_e32 v19, v17
; %bb.19:                               ; %Flow230
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v14, v19
.LBB1_20:                               ; %Flow231
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_saveexec_b32 s0, s0
; %bb.21:                               ;   in Loop: Header=BB1_2 Depth=1
	v_dual_mov_b32 v14, v17 :: v_dual_add_nc_u32 v9, 1, v9
	v_dual_mov_b32 v4, v23 :: v_dual_mov_b32 v3, v22
	v_dual_mov_b32 v2, v21 :: v_dual_mov_b32 v1, v20
	v_mov_b32_e32 v8, v18
; %bb.22:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v5, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s5, v5
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_2
; %bb.23:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s12
.LBB1_24:                               ; %Flow238
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
	v_lshlrev_b32_e32 v1, 2, v0
	s_cmp_lt_u32 s10, 2
	ds_store_2addr_stride64_b32 v1, v10, v9 offset1:4
	ds_store_b32 v1, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_29
; %bb.25:
	v_add_nc_u32_e32 v2, 0x400, v1
	v_add_nc_u32_e32 v3, 0x800, v1
.LBB1_26:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s0, s10, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB1_28
; %bb.27:                               ;   in Loop: Header=BB1_26 Depth=1
	s_lshl_b32 s2, s0, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s2, v2
	v_add_nc_u32_e32 v5, s2, v1
	v_add_nc_u32_e32 v6, s2, v3
	ds_load_b32 v7, v2
	ds_load_b32 v8, v1
	ds_load_b32 v4, v4
	ds_load_b32 v5, v5
	ds_load_b32 v6, v6
	ds_load_b32 v9, v3
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v4, v7, v4
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v5, v8, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v9, v6
	ds_store_b32 v2, v4
	ds_store_b32 v1, v5
	ds_store_b32 v3, v6
.LBB1_28:                               ;   in Loop: Header=BB1_26 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_lt_u32 s10, 4
	s_mov_b32 s10, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_26
.LBB1_29:                               ; %._crit_edge91
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_36
; %bb.30:
	s_mov_b32 s1, exec_lo
	s_mov_b32 s0, exec_lo
	v_mbcnt_lo_u32_b32 v0, s1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_32
; %bb.31:
	v_mov_b32_e32 v0, 0
	s_bcnt1_i32_b32 s1, s1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, device_r@rel32@lo+4
	s_addc_u32 s3, s3, device_r@rel32@hi+12
	ds_load_b32 v1, v0 offset:1024
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v1, s1
	global_atomic_add_u32 v0, v1, s[2:3]
.LBB1_32:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 s1, exec_lo
	s_mov_b32 s0, exec_lo
	v_mbcnt_lo_u32_b32 v0, s1, 0
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_34
; %bb.33:
	v_mov_b32_e32 v0, 0
	s_bcnt1_i32_b32 s1, s1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, device_b@rel32@lo+4
	s_addc_u32 s3, s3, device_b@rel32@hi+12
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v1, s1
	global_atomic_add_u32 v0, v1, s[2:3]
.LBB1_34:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_mbcnt_lo_u32_b32 v0, s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s1, exec_lo, vcc_lo
	s_mov_b32 exec_lo, s1
	s_cbranch_execz .LBB1_36
; %bb.35:
	v_mov_b32_e32 v0, 0
	s_bcnt1_i32_b32 s0, s0
	ds_load_b32 v1, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v1, s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, device_t@rel32@lo+4
	s_addc_u32 s1, s1, device_t@rel32@hi+12
	global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_36:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11neutron_gpuP12hiprandStatefiffPf
		.amdhsa_group_segment_fixed_size 3072
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11neutron_gpuP12hiprandStatefiffPf, .Lfunc_end1-_Z11neutron_gpuP12hiprandStatefiffPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2624
; NumSgprs: 24
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3072 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	device_r                ; @device_r
	.type	device_r,@object
	.section	.bss,"aw",@nobits
	.globl	device_r
	.p2align	2, 0x0
device_r:
	.long	0                               ; 0x0
	.size	device_r, 4

	.protected	device_b                ; @device_b
	.type	device_b,@object
	.globl	device_b
	.p2align	2, 0x0
device_b:
	.long	0                               ; 0x0
	.size	device_b, 4

	.protected	device_t                ; @device_t
	.type	device_t,@object
	.globl	device_t
	.p2align	2, 0x0
device_t:
	.long	0                               ; 0x0
	.size	device_t, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym device_r
	.addrsig_sym device_b
	.addrsig_sym device_t
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12setup_kernelP12hiprandState
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12setup_kernelP12hiprandState.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 3072
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11neutron_gpuP12hiprandStatefiffPf
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z11neutron_gpuP12hiprandStatefiffPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
