#include <cuda_runtime_api.h>
#include <stdint.h>

#define OFFSET_BANK(idx) ({ __typeof__ (idx) _idx = idx; ((_idx) + ((_idx) / 32)); })

__global__ void softmax_lr_loss_fwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *loss)
{
  uint32_t idx = threadIdx.x + blockDim.x * blockIdx.x;
  uint32_t j = idx % dim;
  uint32_t batch_idx = idx / dim;
  if (j < dim && batch_idx < batch_sz) {
    uint32_t label = labels[batch_idx];
    float ratio = ys[label + dim * batch_idx] / targets[batch_idx];
    // FIXME(20170130): also check for inf, nan, negative.
    if (cutoff < ratio) {
      ratio = cutoff;
    }
    loss[batch_idx] = weights[batch_idx] * ratio;
  }
}

extern "C" void neuralops_cuda_softmax_lr_loss_fwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *loss,
    cudaStream_t stream)
{
  softmax_lr_loss_fwd_kernel<<<(batch_sz+1024-1)/1024, 1024, 0, stream>>>(
      ys, dim, batch_sz, labels, targets, weights, cutoff, loss);
}

__global__ void softmax_lr_loss_bwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *grad)
{
  uint32_t idx = threadIdx.x + blockDim.x * blockIdx.x;
  uint32_t j = idx % dim;
  uint32_t batch_idx = idx / dim;
  if (j < dim && batch_idx < batch_sz) {
    uint32_t label = labels[batch_idx];
    float y_label = ys[label + dim * batch_idx];
    float ratio = y_label / targets[batch_idx];
    // FIXME(20170130): also check for inf, nan, negative.
    if (cutoff < ratio) {
      grad[idx] = 0.0f;
    } else {
      float w = weights[batch_idx];
      float y_j = ys[idx];
      if (label == j) {
        grad[idx] = w * ratio * (1.0f - y_j);
      } else {
        grad[idx] = -w * ratio * y_j;
      }
    }
  }
}

extern "C" void neuralops_cuda_softmax_lr_loss_bwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *grad,
    cudaStream_t stream)
{
  softmax_lr_loss_bwd_kernel<<<(batch_sz+1024-1)/1024, 1024, 0, stream>>>(
      ys, dim, batch_sz, labels, targets, weights, cutoff, grad);
}

__global__ void softmax_kl_loss_fwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float epsilon,
    float *loss)
{
  __shared__ float cache[1024 + 32];
  uint32_t j = threadIdx.x;
  uint32_t batch_idx = blockIdx.x;
  uint32_t idx = j + dim * batch_idx;
  if (j < dim && batch_idx < batch_sz) {
    float t = targets[idx];
    float y = ys[idx];
    t += epsilon * (1.0f - t);
    y += epsilon * (1.0f - y);
    float kl;
    if (t > 0.0f) {
      kl = t * (logf(t) - logf(y));
    } else {
      kl = -t * logf(y);
    }
    cache[OFFSET_BANK(j)] = kl;
  } else {
    cache[OFFSET_BANK(j)] = 0.0f;
  }
  __syncthreads();
  for (uint32_t s = 1; s < blockDim.x; s *= 2) {
    if (j < dim && batch_idx < batch_sz) {
      if (j % (2*s) == 0 && (j + s) < dim) {
        cache[OFFSET_BANK(j)] += cache[OFFSET_BANK(j + s)];
      }
    }
    __syncthreads();
  }
  if (j < dim && batch_idx < batch_sz) {
    if (j == 0) {
      loss[batch_idx] = cache[0];
    }
  }
}

extern "C" void neuralops_cuda_softmax_kl_loss_fwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float epsilon,
    float *loss,
    cudaStream_t stream)
{
  //assert(dim <= 1024);
  softmax_kl_loss_fwd_kernel<<<batch_sz, 1024, 0, stream>>>(
      ys, dim, batch_sz, targets, epsilon, loss);
}

__global__ void softmax_kl_loss_bwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float *grad)
{
  uint32_t idx = threadIdx.x + blockIdx.x * blockDim.x;
  uint32_t j = idx % dim;
  uint32_t batch_idx = idx / dim;
  if (j < dim && batch_idx < batch_sz) {
    float t = targets[idx];
    float y = ys[idx];
    grad[idx] = y - t;
  }
}

extern "C" void neuralops_cuda_softmax_kl_loss_bwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float *grad,
    cudaStream_t stream)
{
  uint32_t n = dim * batch_sz;
  softmax_kl_loss_bwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      ys, dim, batch_sz, targets, grad);
}

__global__ void softmax_kl_loss_rfwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *r_xs,
    const float *r_mean,
    const float *targets,
    float *r_loss,
    float *r_grad)
{
  __shared__ float cache[1024 + 32];
  uint32_t j = threadIdx.x;
  uint32_t batch_idx = blockIdx.x;
  uint32_t idx = j + dim * batch_idx;
  if (j < dim && batch_idx < batch_sz) {
    float r_yp_j = r_xs[idx] - r_mean[batch_idx];
    r_grad[idx] = ys[idx] * r_yp_j;
    cache[OFFSET_BANK(j)] = -targets[idx] * r_yp_j;
  } else {
    cache[OFFSET_BANK(j)] = 0.0f;
  }
  __syncthreads();
  for (uint32_t s = 1; s < blockDim.x; s *= 2) {
    if (j < dim && batch_idx < batch_sz) {
      if (j % (2*s) == 0 && (j + s) < dim) {
        cache[OFFSET_BANK(j)] += cache[OFFSET_BANK(j + s)];
      }
    }
    __syncthreads();
  }
  if (j < dim && batch_idx < batch_sz) {
    if (j == 0) {
      r_loss[batch_idx] = cache[0];
    }
  }
}

extern "C" void neuralops_cuda_softmax_kl_loss_rfwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *r_xs,
    const float *r_mean,
    const float *targets,
    float *r_loss,
    float *r_grad,
    cudaStream_t stream)
{
  //assert(dim <= 1024);
  softmax_kl_loss_rfwd_kernel<<<batch_sz, 1024, 0, stream>>>(
      ys, dim, batch_sz, r_xs, r_mean, targets, r_loss, r_grad);
}

__global__ void softmax_nll_loss_fwd_kernel(
    const float *out_act,
    int dim,
    int batch_size,
    const uint32_t *label_cats,
    const float *weights,
    //const float *targets,
    float *out_loss)
{
  int batch_idx = threadIdx.x + blockIdx.x * blockDim.x;
  if (batch_idx < batch_size) {
    int cat_i = label_cats[batch_idx];
    int idx = cat_i + batch_idx * dim;
    float x = -logf(out_act[idx]) * weights[batch_idx];
    out_loss[batch_idx] = x;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_fwd(
    const float *out_act,
    size_t dim,
    size_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    float *out_loss,
    cudaStream_t stream)
{
  int n = batch_size;
  softmax_nll_loss_fwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_act, dim, batch_size,
      label_cats,
      weights,
      out_loss);
}

__global__ void softmax_nll_loss_bwd_kernel(
    const float *out_act,
    int dim,
    int batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int i = idx % dim;
  int batch_idx = idx / dim;
  if ((i < dim) && (batch_idx < batch_size)) {
    int cat_i = label_cats[batch_idx];
    float dx = out_act[idx];
    if ((uint32_t)(i) == cat_i) {
      dx -= 1.0f;
    }
    dx *= weights[batch_idx] * jac_targ[batch_idx];
    in_delta[idx] = dx;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_bwd(
    const float *out_act,
    size_t dim,
    size_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta,
    cudaStream_t stream)
{
  int n = dim * batch_size;
  softmax_nll_loss_bwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_act, dim, batch_size,
      label_cats,
      weights,
      jac_targ,
      in_delta);
}

__global__ void softmax_nll_loss_bwd2_kernel(
    const float *out_act,
    uint32_t dim,
    uint32_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta2)
{
  uint32_t idx = threadIdx.x + blockIdx.x * blockDim.x;
  uint32_t i = idx % dim;
  uint32_t batch_idx = idx / dim;
  if ((i < dim) && (batch_idx < batch_size)) {
    uint32_t cat_i = label_cats[batch_idx];
    float y = out_act[idx];
    float dx2 = y;
    if ((uint32_t)(i) == cat_i) {
      dx2 -= 1.0f;
    }
    dx2 *= (1.0f - 2.0f * y) * weights[batch_idx] * jac_targ[batch_idx];
    in_delta2[idx] = dx2;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_bwd2(
    const float *out_act,
    size_t dim,
    size_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta2,
    cudaStream_t stream)
{
  int n = dim * batch_size;
  softmax_nll_loss_bwd2_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_act,
      dim,
      batch_size,
      label_cats,
      weights,
      jac_targ,
      in_delta2);
}

__global__ void softmax_nll_loss_rfwd_kernel(
    const float *out_r_val,
    uint32_t dim,
    uint32_t batch_size,
    const float *r_mean,
    const uint32_t *labels,
    float *r_loss)
{
  uint32_t batch_idx = threadIdx.x + blockIdx.x * blockDim.x;
  if (batch_idx < batch_size) {
    uint32_t cat_i = labels[batch_idx];
    uint32_t idx = cat_i + batch_idx * dim;
    float r_y_i = out_r_val[idx] - r_mean[batch_idx];
    r_loss[batch_idx] = -r_y_i;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_rfwd(
    const float *out_r_val,
    size_t dim,
    size_t batch_size,
    const float *r_mean,
    const uint32_t *labels,
    float *r_loss,
    cudaStream_t stream)
{
  uint32_t n = batch_size;
  softmax_nll_loss_rfwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_r_val,
      dim,
      batch_size,
      r_mean,
      labels,
      r_loss);
}

	.file	"tmpxft_002bf448_00000000-6_softmax.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2019:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2019:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z61__device_stub__Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
	.type	_Z61__device_stub__Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf, @function
_Z61__device_stub__Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 48(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z61__device_stub__Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf, .-_Z61__device_stub__Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
	.globl	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.type	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf, @function
_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
	.cfi_endproc
.LFE2042:
	.size	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf, .-_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.globl	neuralops_cuda_softmax_lr_loss_fwd
	.type	neuralops_cuda_softmax_lr_loss_fwd, @function
neuralops_cuda_softmax_lr_loss_fwd:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leal	1023(%rdx), %eax
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	shrl	$10, %eax
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	movl	$4194305, %edx
	salq	$10, %rdx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	120(%rsp), %r9
	movq	112(%rsp), %rbp
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movl	32(%rsp), %esi
	movq	%rdi, (%rsp)
	movq	24(%rsp), %rdi
	movss	%xmm0, 12(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L8
	movq	%rbp, 112(%rsp)
	movq	(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%ebx, %edx
	movl	%r12d, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z61__device_stub__Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
.L8:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	neuralops_cuda_softmax_lr_loss_fwd, .-neuralops_cuda_softmax_lr_loss_fwd
	.globl	_Z61__device_stub__Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
	.type	_Z61__device_stub__Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf, @function
_Z61__device_stub__Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf:
.LFB2043:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 48(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L11:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z61__device_stub__Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf, .-_Z61__device_stub__Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
	.globl	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.type	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf, @function
_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf:
.LFB2044:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
	.cfi_endproc
.LFE2044:
	.size	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf, .-_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.globl	neuralops_cuda_softmax_lr_loss_bwd
	.type	neuralops_cuda_softmax_lr_loss_bwd, @function
neuralops_cuda_softmax_lr_loss_bwd:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leal	1023(%rdx), %eax
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	shrl	$10, %eax
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	movl	$4194305, %edx
	salq	$10, %rdx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	120(%rsp), %r9
	movq	112(%rsp), %rbp
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movl	32(%rsp), %esi
	movq	%rdi, (%rsp)
	movq	24(%rsp), %rdi
	movss	%xmm0, 12(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L16
	movq	%rbp, 112(%rsp)
	movq	(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%ebx, %edx
	movl	%r12d, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z61__device_stub__Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPfPKfjjPKjS0_S0_fPf
.L16:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	neuralops_cuda_softmax_lr_loss_bwd, .-neuralops_cuda_softmax_lr_loss_bwd
	.globl	_Z55__device_stub__Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPfPKfjjS0_fPf
	.type	_Z55__device_stub__Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPfPKfjjS0_fPf, @function
_Z55__device_stub__Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPfPKfjjS0_fPf:
.LFB2045:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_Z55__device_stub__Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPfPKfjjS0_fPf, .-_Z55__device_stub__Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPfPKfjjS0_fPf
	.globl	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.type	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf, @function
_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf:
.LFB2046:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPfPKfjjS0_fPf
	.cfi_endproc
.LFE2046:
	.size	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf, .-_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.globl	neuralops_cuda_softmax_kl_loss_fwd
	.type	neuralops_cuda_softmax_kl_loss_fwd, @function
neuralops_cuda_softmax_kl_loss_fwd:
.LFB2010:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edx, %ebx
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movl	%edx, 24(%rsp)
	movl	$4194305, %edx
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	salq	$10, %rdx
	movl	32(%rsp), %esi
	movss	%xmm0, 12(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L24
	addq	$48, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%ebx, %edx
	movl	%r12d, %esi
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z55__device_stub__Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPfPKfjjS0_fPf
.L24:
	.cfi_restore_state
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2010:
	.size	neuralops_cuda_softmax_kl_loss_fwd, .-neuralops_cuda_softmax_kl_loss_fwd
	.globl	_Z54__device_stub__Z26softmax_kl_loss_bwd_kernelPKfjjS0_PfPKfjjS0_Pf
	.type	_Z54__device_stub__Z26softmax_kl_loss_bwd_kernelPKfjjS0_PfPKfjjS0_Pf, @function
_Z54__device_stub__Z26softmax_kl_loss_bwd_kernelPKfjjS0_PfPKfjjS0_Pf:
.LFB2047:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L27:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2047:
	.size	_Z54__device_stub__Z26softmax_kl_loss_bwd_kernelPKfjjS0_PfPKfjjS0_Pf, .-_Z54__device_stub__Z26softmax_kl_loss_bwd_kernelPKfjjS0_PfPKfjjS0_Pf
	.globl	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.type	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf, @function
_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf:
.LFB2048:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z26softmax_kl_loss_bwd_kernelPKfjjS0_PfPKfjjS0_Pf
	.cfi_endproc
.LFE2048:
	.size	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf, .-_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.globl	neuralops_cuda_softmax_kl_loss_bwd
	.type	neuralops_cuda_softmax_kl_loss_bwd, @function
neuralops_cuda_softmax_kl_loss_bwd:
.LFB2011:
	.cfi_startproc
	endbr64
	movl	%esi, %eax
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%edx, %r14d
	imull	%edx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	$4194305, %edx
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	salq	$10, %rdx
	movq	%r8, %r12
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rcx, %rbp
	movl	$1, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	addl	$1023, %eax
	movq	%rdi, %rbx
	shrl	$10, %eax
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	movq	%r12, %r8
	movq	%rbp, %rcx
	movl	%r14d, %edx
	movl	%r13d, %esi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z54__device_stub__Z26softmax_kl_loss_bwd_kernelPKfjjS0_PfPKfjjS0_Pf
.L32:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2011:
	.size	neuralops_cuda_softmax_kl_loss_bwd, .-neuralops_cuda_softmax_kl_loss_bwd
	.globl	_Z64__device_stub__Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_PKfjjS0_S0_S0_PfS1_
	.type	_Z64__device_stub__Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_PKfjjS0_S0_S0_PfS1_, @function
_Z64__device_stub__Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_PKfjjS0_S0_S0_PfS1_:
.LFB2049:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 48(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L35:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2049:
	.size	_Z64__device_stub__Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_PKfjjS0_S0_S0_PfS1_, .-_Z64__device_stub__Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_PKfjjS0_S0_S0_PfS1_
	.globl	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.type	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_, @function
_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_:
.LFB2050:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_PKfjjS0_S0_S0_PfS1_
	.cfi_endproc
.LFE2050:
	.size	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_, .-_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.globl	neuralops_cuda_softmax_kl_loss_rfwd
	.type	neuralops_cuda_softmax_kl_loss_rfwd, @function
neuralops_cuda_softmax_kl_loss_rfwd:
.LFB2012:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%edx, 24(%rsp)
	movl	$4194305, %edx
	movq	112(%rsp), %rbp
	movq	%rax, 28(%rsp)
	movq	128(%rsp), %r9
	salq	$10, %rdx
	movq	%rdi, (%rsp)
	movq	24(%rsp), %rdi
	movl	%esi, 12(%rsp)
	movl	32(%rsp), %esi
	movq	120(%rsp), %r12
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	%r12, 120(%rsp)
	movl	12(%rsp), %esi
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%rbp, 112(%rsp)
	movq	(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r13, %rcx
	movl	%ebx, %edx
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z64__device_stub__Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_PKfjjS0_S0_S0_PfS1_
.L40:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2012:
	.size	neuralops_cuda_softmax_kl_loss_rfwd, .-neuralops_cuda_softmax_kl_loss_rfwd
	.globl	_Z58__device_stub__Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_PfPKfiiPKjS0_Pf
	.type	_Z58__device_stub__Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_PfPKfiiPKjS0_Pf, @function
_Z58__device_stub__Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_PfPKfiiPKjS0_Pf:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L43:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z58__device_stub__Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_PfPKfiiPKjS0_Pf, .-_Z58__device_stub__Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_PfPKfiiPKjS0_Pf
	.globl	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.type	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf, @function
_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_PfPKfiiPKjS0_Pf
	.cfi_endproc
.LFE2052:
	.size	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf, .-_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.globl	neuralops_cuda_softmax_nll_loss_fwd
	.type	neuralops_cuda_softmax_nll_loss_fwd, @function
neuralops_cuda_softmax_nll_loss_fwd:
.LFB2013:
	.cfi_startproc
	endbr64
	leal	1023(%rdx), %eax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	cltd
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	movl	$1024, %ecx
	idivl	%ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, %rbp
	movq	%rsi, %rbx
	movl	$4194305, %edx
	movq	96(%rsp), %r9
	salq	$10, %rdx
	movl	$1, %ecx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r14, %r9
	movq	%r13, %r8
	movq	%r12, %rcx
	movl	%r15d, %edx
	movl	%ebx, %esi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z58__device_stub__Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_PfPKfiiPKjS0_Pf
.L48:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2013:
	.size	neuralops_cuda_softmax_nll_loss_fwd, .-neuralops_cuda_softmax_nll_loss_fwd
	.globl	_Z61__device_stub__Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_PfPKfiiPKjS0_S0_Pf
	.type	_Z61__device_stub__Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_PfPKfiiPKjS0_S0_Pf, @function
_Z61__device_stub__Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_PfPKfiiPKjS0_S0_Pf:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L51:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z61__device_stub__Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_PfPKfiiPKjS0_S0_Pf, .-_Z61__device_stub__Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_PfPKfiiPKjS0_S0_Pf
	.globl	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.type	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf, @function
_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_PfPKfiiPKjS0_S0_Pf
	.cfi_endproc
.LFE2054:
	.size	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf, .-_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.globl	neuralops_cuda_softmax_nll_loss_bwd
	.type	neuralops_cuda_softmax_nll_loss_bwd, @function
neuralops_cuda_softmax_nll_loss_bwd:
.LFB2014:
	.cfi_startproc
	endbr64
	movl	%esi, %eax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	imull	%edx, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	movl	$1024, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	addl	$1023, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	cltd
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	idivl	%ecx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	$4194305, %edx
	movl	$1, %ecx
	movq	%rdi, 8(%rsp)
	movq	120(%rsp), %r9
	salq	$10, %rdx
	movq	112(%rsp), %r12
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	movq	%r12, 112(%rsp)
	movq	8(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%ebp, %edx
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%ebx, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z61__device_stub__Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_PfPKfiiPKjS0_S0_Pf
.L56:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2014:
	.size	neuralops_cuda_softmax_nll_loss_bwd, .-neuralops_cuda_softmax_nll_loss_bwd
	.globl	_Z62__device_stub__Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_PfPKfjjPKjS0_S0_Pf
	.type	_Z62__device_stub__Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_PfPKfjjPKjS0_S0_Pf, @function
_Z62__device_stub__Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_PfPKfjjPKjS0_S0_Pf:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L59:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z62__device_stub__Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_PfPKfjjPKjS0_S0_Pf, .-_Z62__device_stub__Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_PfPKfjjPKjS0_S0_Pf
	.globl	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.type	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf, @function
_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_PfPKfjjPKjS0_S0_Pf
	.cfi_endproc
.LFE2056:
	.size	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf, .-_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.globl	neuralops_cuda_softmax_nll_loss_bwd2
	.type	neuralops_cuda_softmax_nll_loss_bwd2, @function
neuralops_cuda_softmax_nll_loss_bwd2:
.LFB2015:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	imull	%esi, %edx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%esi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	leal	1023(%rdx), %eax
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	cltd
	movq	%rcx, %rbp
	movl	$1024, %ecx
	idivl	%ecx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	$4194305, %edx
	movl	$1, %ecx
	movq	%rdi, 8(%rsp)
	movq	120(%rsp), %r9
	salq	$10, %rdx
	movq	112(%rsp), %rbx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	movq	%rbx, 112(%rsp)
	movq	8(%rsp), %rdi
	movq	%r13, %r9
	movq	%r12, %r8
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%rbp, %rcx
	movl	%r15d, %edx
	movl	%r14d, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z62__device_stub__Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_PfPKfjjPKjS0_S0_Pf
.L64:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2015:
	.size	neuralops_cuda_softmax_nll_loss_bwd2, .-neuralops_cuda_softmax_nll_loss_bwd2
	.globl	_Z59__device_stub__Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPfPKfjjS0_PKjPf
	.type	_Z59__device_stub__Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPfPKfjjS0_PKjPf, @function
_Z59__device_stub__Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPfPKfjjS0_PKjPf:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L67:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L69
	call	__stack_chk_fail@PLT
.L69:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z59__device_stub__Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPfPKfjjS0_PKjPf, .-_Z59__device_stub__Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPfPKfjjS0_PKjPf
	.globl	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.type	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf, @function
_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPfPKfjjS0_PKjPf
	.cfi_endproc
.LFE2058:
	.size	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf, .-_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.globl	neuralops_cuda_softmax_nll_loss_rfwd
	.type	neuralops_cuda_softmax_nll_loss_rfwd, @function
neuralops_cuda_softmax_nll_loss_rfwd:
.LFB2016:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %r15d
	addl	$1023, %edx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	shrl	$10, %edx
	movq	%r9, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	movl	$1, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	%edx, 8(%rsp)
	movq	96(%rsp), %r9
	movl	$4194305, %edx
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	salq	$10, %rdx
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r14, %r9
	movq	%r13, %r8
	movq	%r12, %rcx
	movl	%r15d, %edx
	movl	%ebx, %esi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z59__device_stub__Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPfPKfjjS0_PKjPf
.L72:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2016:
	.size	neuralops_cuda_softmax_nll_loss_rfwd, .-neuralops_cuda_softmax_nll_loss_rfwd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf"
.LC1:
	.string	"_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf"
.LC2:
	.string	"_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf"
.LC3:
	.string	"_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf"
.LC4:
	.string	"_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_"
.LC5:
	.string	"_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf"
.LC6:
	.string	"_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf"
.LC7:
	.string	"_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf"
.LC8:
	.string	"_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdint.h>

#define OFFSET_BANK(idx) ({ __typeof__ (idx) _idx = idx; ((_idx) + ((_idx) / 32)); })

__global__ void softmax_lr_loss_fwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *loss)
{
  uint32_t idx = threadIdx.x + blockDim.x * blockIdx.x;
  uint32_t j = idx % dim;
  uint32_t batch_idx = idx / dim;
  if (j < dim && batch_idx < batch_sz) {
    uint32_t label = labels[batch_idx];
    float ratio = ys[label + dim * batch_idx] / targets[batch_idx];
    // FIXME(20170130): also check for inf, nan, negative.
    if (cutoff < ratio) {
      ratio = cutoff;
    }
    loss[batch_idx] = weights[batch_idx] * ratio;
  }
}

extern "C" void neuralops_cuda_softmax_lr_loss_fwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *loss,
    hipStream_t stream)
{
  softmax_lr_loss_fwd_kernel<<<(batch_sz+1024-1)/1024, 1024, 0, stream>>>(
      ys, dim, batch_sz, labels, targets, weights, cutoff, loss);
}

__global__ void softmax_lr_loss_bwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *grad)
{
  uint32_t idx = threadIdx.x + blockDim.x * blockIdx.x;
  uint32_t j = idx % dim;
  uint32_t batch_idx = idx / dim;
  if (j < dim && batch_idx < batch_sz) {
    uint32_t label = labels[batch_idx];
    float y_label = ys[label + dim * batch_idx];
    float ratio = y_label / targets[batch_idx];
    // FIXME(20170130): also check for inf, nan, negative.
    if (cutoff < ratio) {
      grad[idx] = 0.0f;
    } else {
      float w = weights[batch_idx];
      float y_j = ys[idx];
      if (label == j) {
        grad[idx] = w * ratio * (1.0f - y_j);
      } else {
        grad[idx] = -w * ratio * y_j;
      }
    }
  }
}

extern "C" void neuralops_cuda_softmax_lr_loss_bwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const uint32_t *labels,
    const float *targets,
    const float *weights,
    float cutoff,
    float *grad,
    hipStream_t stream)
{
  softmax_lr_loss_bwd_kernel<<<(batch_sz+1024-1)/1024, 1024, 0, stream>>>(
      ys, dim, batch_sz, labels, targets, weights, cutoff, grad);
}

__global__ void softmax_kl_loss_fwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float epsilon,
    float *loss)
{
  __shared__ float cache[1024 + 32];
  uint32_t j = threadIdx.x;
  uint32_t batch_idx = blockIdx.x;
  uint32_t idx = j + dim * batch_idx;
  if (j < dim && batch_idx < batch_sz) {
    float t = targets[idx];
    float y = ys[idx];
    t += epsilon * (1.0f - t);
    y += epsilon * (1.0f - y);
    float kl;
    if (t > 0.0f) {
      kl = t * (logf(t) - logf(y));
    } else {
      kl = -t * logf(y);
    }
    cache[OFFSET_BANK(j)] = kl;
  } else {
    cache[OFFSET_BANK(j)] = 0.0f;
  }
  __syncthreads();
  for (uint32_t s = 1; s < blockDim.x; s *= 2) {
    if (j < dim && batch_idx < batch_sz) {
      if (j % (2*s) == 0 && (j + s) < dim) {
        cache[OFFSET_BANK(j)] += cache[OFFSET_BANK(j + s)];
      }
    }
    __syncthreads();
  }
  if (j < dim && batch_idx < batch_sz) {
    if (j == 0) {
      loss[batch_idx] = cache[0];
    }
  }
}

extern "C" void neuralops_cuda_softmax_kl_loss_fwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float epsilon,
    float *loss,
    hipStream_t stream)
{
  //assert(dim <= 1024);
  softmax_kl_loss_fwd_kernel<<<batch_sz, 1024, 0, stream>>>(
      ys, dim, batch_sz, targets, epsilon, loss);
}

__global__ void softmax_kl_loss_bwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float *grad)
{
  uint32_t idx = threadIdx.x + blockIdx.x * blockDim.x;
  uint32_t j = idx % dim;
  uint32_t batch_idx = idx / dim;
  if (j < dim && batch_idx < batch_sz) {
    float t = targets[idx];
    float y = ys[idx];
    grad[idx] = y - t;
  }
}

extern "C" void neuralops_cuda_softmax_kl_loss_bwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *targets,
    float *grad,
    hipStream_t stream)
{
  uint32_t n = dim * batch_sz;
  softmax_kl_loss_bwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      ys, dim, batch_sz, targets, grad);
}

__global__ void softmax_kl_loss_rfwd_kernel(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *r_xs,
    const float *r_mean,
    const float *targets,
    float *r_loss,
    float *r_grad)
{
  __shared__ float cache[1024 + 32];
  uint32_t j = threadIdx.x;
  uint32_t batch_idx = blockIdx.x;
  uint32_t idx = j + dim * batch_idx;
  if (j < dim && batch_idx < batch_sz) {
    float r_yp_j = r_xs[idx] - r_mean[batch_idx];
    r_grad[idx] = ys[idx] * r_yp_j;
    cache[OFFSET_BANK(j)] = -targets[idx] * r_yp_j;
  } else {
    cache[OFFSET_BANK(j)] = 0.0f;
  }
  __syncthreads();
  for (uint32_t s = 1; s < blockDim.x; s *= 2) {
    if (j < dim && batch_idx < batch_sz) {
      if (j % (2*s) == 0 && (j + s) < dim) {
        cache[OFFSET_BANK(j)] += cache[OFFSET_BANK(j + s)];
      }
    }
    __syncthreads();
  }
  if (j < dim && batch_idx < batch_sz) {
    if (j == 0) {
      r_loss[batch_idx] = cache[0];
    }
  }
}

extern "C" void neuralops_cuda_softmax_kl_loss_rfwd(
    const float *ys,
    uint32_t dim,
    uint32_t batch_sz,
    const float *r_xs,
    const float *r_mean,
    const float *targets,
    float *r_loss,
    float *r_grad,
    hipStream_t stream)
{
  //assert(dim <= 1024);
  softmax_kl_loss_rfwd_kernel<<<batch_sz, 1024, 0, stream>>>(
      ys, dim, batch_sz, r_xs, r_mean, targets, r_loss, r_grad);
}

__global__ void softmax_nll_loss_fwd_kernel(
    const float *out_act,
    int dim,
    int batch_size,
    const uint32_t *label_cats,
    const float *weights,
    //const float *targets,
    float *out_loss)
{
  int batch_idx = threadIdx.x + blockIdx.x * blockDim.x;
  if (batch_idx < batch_size) {
    int cat_i = label_cats[batch_idx];
    int idx = cat_i + batch_idx * dim;
    float x = -logf(out_act[idx]) * weights[batch_idx];
    out_loss[batch_idx] = x;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_fwd(
    const float *out_act,
    size_t dim,
    size_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    float *out_loss,
    hipStream_t stream)
{
  int n = batch_size;
  softmax_nll_loss_fwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_act, dim, batch_size,
      label_cats,
      weights,
      out_loss);
}

__global__ void softmax_nll_loss_bwd_kernel(
    const float *out_act,
    int dim,
    int batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta)
{
  int idx = threadIdx.x + blockIdx.x * blockDim.x;
  int i = idx % dim;
  int batch_idx = idx / dim;
  if ((i < dim) && (batch_idx < batch_size)) {
    int cat_i = label_cats[batch_idx];
    float dx = out_act[idx];
    if ((uint32_t)(i) == cat_i) {
      dx -= 1.0f;
    }
    dx *= weights[batch_idx] * jac_targ[batch_idx];
    in_delta[idx] = dx;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_bwd(
    const float *out_act,
    size_t dim,
    size_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta,
    hipStream_t stream)
{
  int n = dim * batch_size;
  softmax_nll_loss_bwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_act, dim, batch_size,
      label_cats,
      weights,
      jac_targ,
      in_delta);
}

__global__ void softmax_nll_loss_bwd2_kernel(
    const float *out_act,
    uint32_t dim,
    uint32_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta2)
{
  uint32_t idx = threadIdx.x + blockIdx.x * blockDim.x;
  uint32_t i = idx % dim;
  uint32_t batch_idx = idx / dim;
  if ((i < dim) && (batch_idx < batch_size)) {
    uint32_t cat_i = label_cats[batch_idx];
    float y = out_act[idx];
    float dx2 = y;
    if ((uint32_t)(i) == cat_i) {
      dx2 -= 1.0f;
    }
    dx2 *= (1.0f - 2.0f * y) * weights[batch_idx] * jac_targ[batch_idx];
    in_delta2[idx] = dx2;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_bwd2(
    const float *out_act,
    size_t dim,
    size_t batch_size,
    const uint32_t *label_cats,
    const float *weights,
    const float *jac_targ,
    float *in_delta2,
    hipStream_t stream)
{
  int n = dim * batch_size;
  softmax_nll_loss_bwd2_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_act,
      dim,
      batch_size,
      label_cats,
      weights,
      jac_targ,
      in_delta2);
}

__global__ void softmax_nll_loss_rfwd_kernel(
    const float *out_r_val,
    uint32_t dim,
    uint32_t batch_size,
    const float *r_mean,
    const uint32_t *labels,
    float *r_loss)
{
  uint32_t batch_idx = threadIdx.x + blockIdx.x * blockDim.x;
  if (batch_idx < batch_size) {
    uint32_t cat_i = labels[batch_idx];
    uint32_t idx = cat_i + batch_idx * dim;
    float r_y_i = out_r_val[idx] - r_mean[batch_idx];
    r_loss[batch_idx] = -r_y_i;
  }
}

extern "C" void neuralops_cuda_softmax_nll_loss_rfwd(
    const float *out_r_val,
    size_t dim,
    size_t batch_size,
    const float *r_mean,
    const uint32_t *labels,
    float *r_loss,
    hipStream_t stream)
{
  uint32_t n = batch_size;
  softmax_nll_loss_rfwd_kernel<<<(n+1024-1)/1024, 1024, 0, stream>>>(
      out_r_val,
      dim,
      batch_size,
      r_mean,
      labels,
      r_loss);
}

	.text
	.file	"softmax.hip"
	.globl	_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf # -- Begin function _Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.type	_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf,@function
_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf: # @_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf, .Lfunc_end0-_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_lr_loss_fwd # -- Begin function neuralops_cuda_softmax_lr_loss_fwd
	.type	neuralops_cuda_softmax_lr_loss_fwd,@function
neuralops_cuda_softmax_lr_loss_fwd:     # @neuralops_cuda_softmax_lr_loss_fwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %r12d
	movl	%esi, %ebp
	movq	%rdi, %r13
	movq	72(%rsp), %r9
	leal	1023(%r12), %edi
	shrl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 64
	movq	%r13, %rdi
	movl	%ebp, %esi
	movl	%r12d, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf # TAILCALL
.Lfunc_end1:
	.size	neuralops_cuda_softmax_lr_loss_fwd, .Lfunc_end1-neuralops_cuda_softmax_lr_loss_fwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf # -- Begin function _Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.type	_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf,@function
_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf: # @_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf, .Lfunc_end2-_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_lr_loss_bwd # -- Begin function neuralops_cuda_softmax_lr_loss_bwd
	.type	neuralops_cuda_softmax_lr_loss_bwd,@function
neuralops_cuda_softmax_lr_loss_bwd:     # @neuralops_cuda_softmax_lr_loss_bwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %r12d
	movl	%esi, %ebp
	movq	%rdi, %r13
	movq	72(%rsp), %r9
	leal	1023(%r12), %edi
	shrl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB3_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_2:
	.cfi_def_cfa_offset 64
	movq	%r13, %rdi
	movl	%ebp, %esi
	movl	%r12d, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf # TAILCALL
.Lfunc_end3:
	.size	neuralops_cuda_softmax_lr_loss_bwd, .Lfunc_end3-neuralops_cuda_softmax_lr_loss_bwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf # -- Begin function _Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.type	_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf,@function
_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf: # @_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %r9
	movq	%r8, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf, .Lfunc_end4-_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_kl_loss_fwd # -- Begin function neuralops_cuda_softmax_kl_loss_fwd
	.type	neuralops_cuda_softmax_kl_loss_fwd,@function
neuralops_cuda_softmax_kl_loss_fwd:     # @neuralops_cuda_softmax_kl_loss_fwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %rbx
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%rcx, %r14
	movl	%edx, %ebp
	movl	%esi, %r15d
	movq	%rdi, %r12
	movl	%edx, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 64
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%ebp, %edx
	movq	%r14, %rcx
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	%rbx, %r8
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf # TAILCALL
.Lfunc_end5:
	.size	neuralops_cuda_softmax_kl_loss_fwd, .Lfunc_end5-neuralops_cuda_softmax_kl_loss_fwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf # -- Begin function _Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.type	_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf,@function
_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf: # @_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rdi
	movl	%esi, (%rdi)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf, .Lfunc_end6-_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_kl_loss_bwd # -- Begin function neuralops_cuda_softmax_kl_loss_bwd
	.type	neuralops_cuda_softmax_kl_loss_bwd,@function
neuralops_cuda_softmax_kl_loss_bwd:     # @neuralops_cuda_softmax_kl_loss_bwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %rbx
	movq	%rcx, %r14
	movl	%edx, %ebp
	movl	%esi, %r15d
	movq	%rdi, %r12
	movl	%edx, %edi
	imull	%esi, %edi
	addl	$1023, %edi                     # imm = 0x3FF
	shrl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB7_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_2:
	.cfi_def_cfa_offset 48
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%ebp, %edx
	movq	%r14, %rcx
	movq	%rbx, %r8
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf # TAILCALL
.Lfunc_end7:
	.size	neuralops_cuda_softmax_kl_loss_bwd, .Lfunc_end7-neuralops_cuda_softmax_kl_loss_bwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_ # -- Begin function _Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.type	_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_,@function
_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_: # @_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_, .Lfunc_end8-_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_kl_loss_rfwd # -- Begin function neuralops_cuda_softmax_kl_loss_rfwd
	.type	neuralops_cuda_softmax_kl_loss_rfwd,@function
neuralops_cuda_softmax_kl_loss_rfwd:    # @neuralops_cuda_softmax_kl_loss_rfwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movl	%edx, %ebp
	movl	%esi, %r12d
	movq	%rdi, %r13
	movq	80(%rsp), %r9
	movl	%edx, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB9_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB9_2:
	.cfi_def_cfa_offset 64
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebp, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_ # TAILCALL
.Lfunc_end9:
	.size	neuralops_cuda_softmax_kl_loss_rfwd, .Lfunc_end9-neuralops_cuda_softmax_kl_loss_rfwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf # -- Begin function _Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.type	_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf,@function
_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf: # @_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf, .Lfunc_end10-_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_nll_loss_fwd # -- Begin function neuralops_cuda_softmax_nll_loss_fwd
	.type	neuralops_cuda_softmax_nll_loss_fwd,@function
neuralops_cuda_softmax_nll_loss_fwd:    # @neuralops_cuda_softmax_nll_loss_fwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	64(%rsp), %r9
	leal	1023(%rdx), %eax
	leal	2046(%rdx), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB11_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB11_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf # TAILCALL
.Lfunc_end11:
	.size	neuralops_cuda_softmax_nll_loss_fwd, .Lfunc_end11-neuralops_cuda_softmax_nll_loss_fwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf # -- Begin function _Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.type	_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf,@function
_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf: # @_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf, .Lfunc_end12-_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_nll_loss_bwd # -- Begin function neuralops_cuda_softmax_nll_loss_bwd
	.type	neuralops_cuda_softmax_nll_loss_bwd,@function
neuralops_cuda_softmax_nll_loss_bwd:    # @neuralops_cuda_softmax_nll_loss_bwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	72(%rsp), %r9
	movl	%r12d, %edi
	imull	%r13d, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB13_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB13_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf # TAILCALL
.Lfunc_end13:
	.size	neuralops_cuda_softmax_nll_loss_bwd, .Lfunc_end13-neuralops_cuda_softmax_nll_loss_bwd
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf # -- Begin function _Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.type	_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf,@function
_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf: # @_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf, .Lfunc_end14-_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_nll_loss_bwd2 # -- Begin function neuralops_cuda_softmax_nll_loss_bwd2
	.type	neuralops_cuda_softmax_nll_loss_bwd2,@function
neuralops_cuda_softmax_nll_loss_bwd2:   # @neuralops_cuda_softmax_nll_loss_bwd2
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	72(%rsp), %r9
	movl	%r12d, %edi
	imull	%r13d, %edi
	leal	1023(%rdi), %eax
	addl	$2046, %edi                     # imm = 0x7FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB15_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB15_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf # TAILCALL
.Lfunc_end15:
	.size	neuralops_cuda_softmax_nll_loss_bwd2, .Lfunc_end15-neuralops_cuda_softmax_nll_loss_bwd2
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf # -- Begin function _Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.type	_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf,@function
_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf: # @_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf, .Lfunc_end16-_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.cfi_endproc
                                        # -- End function
	.globl	neuralops_cuda_softmax_nll_loss_rfwd # -- Begin function neuralops_cuda_softmax_nll_loss_rfwd
	.type	neuralops_cuda_softmax_nll_loss_rfwd,@function
neuralops_cuda_softmax_nll_loss_rfwd:   # @neuralops_cuda_softmax_nll_loss_rfwd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %r12
	movq	%rsi, %r13
	movq	%rdi, %rbp
	movq	64(%rsp), %r9
	leal	1023(%rdx), %edi
	shrl	$10, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB17_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB17_2:
	.cfi_def_cfa_offset 64
	movq	%rbp, %rdi
	movl	%r13d, %esi
	movl	%r12d, %edx
	movq	%r15, %rcx
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf # TAILCALL
.Lfunc_end17:
	.size	neuralops_cuda_softmax_nll_loss_rfwd, .Lfunc_end17-neuralops_cuda_softmax_nll_loss_rfwd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB18_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB18_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end18:
	.size	__hip_module_ctor, .Lfunc_end18-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB19_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB19_2:
	retq
.Lfunc_end19:
	.size	__hip_module_dtor, .Lfunc_end19-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf,@object # @_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.section	.rodata,"a",@progbits
	.globl	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.p2align	3, 0x0
_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf:
	.quad	_Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.size	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf, 8

	.type	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf,@object # @_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.globl	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.p2align	3, 0x0
_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf:
	.quad	_Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.size	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf, 8

	.type	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf,@object # @_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.globl	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.p2align	3, 0x0
_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf:
	.quad	_Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.size	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf, 8

	.type	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf,@object # @_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.globl	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.p2align	3, 0x0
_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf:
	.quad	_Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.size	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf, 8

	.type	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_,@object # @_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.globl	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.p2align	3, 0x0
_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_:
	.quad	_Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.size	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_, 8

	.type	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf,@object # @_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.globl	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.p2align	3, 0x0
_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf:
	.quad	_Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.size	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf, 8

	.type	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf,@object # @_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.globl	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.p2align	3, 0x0
_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf:
	.quad	_Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.size	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf, 8

	.type	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf,@object # @_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.globl	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.p2align	3, 0x0
_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf:
	.quad	_Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.size	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf, 8

	.type	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf,@object # @_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.globl	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.p2align	3, 0x0
_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf:
	.quad	_Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.size	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf"
	.size	.L__unnamed_1, 48

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf"
	.size	.L__unnamed_2, 48

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf"
	.size	.L__unnamed_3, 42

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf"
	.size	.L__unnamed_4, 41

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_"
	.size	.L__unnamed_5, 51

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf"
	.size	.L__unnamed_6, 45

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf"
	.size	.L__unnamed_7, 48

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf"
	.size	.L__unnamed_8, 49

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf"
	.size	.L__unnamed_9, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.addrsig_sym _Z41__device_stub__softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.addrsig_sym _Z41__device_stub__softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.addrsig_sym _Z41__device_stub__softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.addrsig_sym _Z42__device_stub__softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.addrsig_sym _Z42__device_stub__softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.addrsig_sym _Z42__device_stub__softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.addrsig_sym _Z43__device_stub__softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.addrsig_sym _Z43__device_stub__softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.addrsig_sym _Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.addrsig_sym _Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.addrsig_sym _Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.addrsig_sym _Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.addrsig_sym _Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.addrsig_sym _Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.addrsig_sym _Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.addrsig_sym _Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf ; -- Begin function _Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.globl	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
	.p2align	8
	.type	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf,@function
_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf: ; @_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s5, 0, s2
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s5, v3
	v_mul_hi_u32 v4, v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v4
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v0, s2
	v_sub_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s2, v1
	v_cmp_le_u32_e32 vcc_lo, s2, v1
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_add_nc_u32 v2, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, 1, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x10
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_load_b64 s[4:5], s[0:1], 0x0
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v0, s2, v[4:5]
	v_mov_b32_e32 v6, v1
	v_add_co_u32 v4, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[0:1], off
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b32 s4, s[0:1], 0x28
	s_load_b64 s[0:1], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v1, null, v4, v4, v5
	v_div_scale_f32 v8, vcc_lo, v5, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v1, v6, 1.0
	v_fmac_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v8, v6
	v_fma_f32 v9, -v1, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v9, v6
	v_fma_f32 v1, -v1, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v6, v7
	v_div_fixup_f32 v1, v1, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, s4, v1
	v_cndmask_b32_e64 v1, v1, s4, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v0, v1
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf, .Lfunc_end0-_Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf ; -- Begin function _Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.globl	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
	.p2align	8
	.type	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf,@function
_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf: ; @_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s5, 0, s2
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s5, v3
	v_mul_hi_u32 v4, v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v4
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v0, s2
	v_add_nc_u32_e32 v3, 1, v0
	v_sub_nc_u32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v4, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_cndmask_b32_e32 v2, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB1_9
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x10
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
	s_load_b64 s[4:5], s[0:1], 0x0
	v_add_co_u32 v9, vcc_lo, s6, v4
	global_load_b32 v0, v[6:7], off
	v_mul_lo_u32 v6, v2, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v0, v6
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v2, v[9:10], off
	global_load_b32 v7, v[7:8], off
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x28
	s_load_b64 s[2:3], s[0:1], 0x30
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v8, null, v2, v2, v7
	v_div_scale_f32 v11, vcc_lo, v7, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	v_fmac_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v11, v9
	v_fma_f32 v12, -v8, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v12, v9
	v_fma_f32 v8, -v8, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v9, v10
	v_div_fixup_f32 v7, v8, v2, v7
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f32_e32 vcc_lo, s6, v7
	s_and_saveexec_b32 s6, vcc_lo
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB1_7
; %bb.2:
	s_load_b64 s[0:1], s[0:1], 0x20
	v_mov_b32_e32 v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[1:2]
	v_sub_nc_u32_e32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, v0, v1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_u32 v0, s0, s2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, s3, v9, s0
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_4
; %bb.3:
	s_waitcnt vmcnt(1)
	v_mul_f32_e64 v2, v7, -v2
                                        ; implicit-def: $vgpr7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
                                        ; implicit-def: $vgpr3
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0_vgpr1
.LBB1_4:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_6
; %bb.5:
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v2, v7, v2 :: v_dual_sub_f32 v3, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB1_6:                                ; %Flow62
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr1_vgpr2
.LBB1_7:                                ; %Flow63
	s_and_not1_saveexec_b32 s0, s6
	s_cbranch_execz .LBB1_9
; %bb.8:
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf, .Lfunc_end1-_Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 704
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf ; -- Begin function _Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.globl	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
	.p2align	8
	.type	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf,@function
_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf: ; @_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
; %bb.0:
	s_load_b64 s[6:7], s[0:1], 0x8
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s6, v0
	s_cmp_lt_u32 s15, s7
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, vcc_lo, s5
	s_and_saveexec_b32 s8, s7
	s_cbranch_execz .LBB2_6
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, s4, s6, v[0:1]
	v_mov_b32_e32 v2, 0
	s_clause 0x1
	s_load_b64 s[10:11], s[0:1], 0x10
	s_load_b32 s9, s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s2, s3, v2, s2
	v_add_co_u32 v1, s2, s10, v1
	v_add_co_ci_u32_e64 v2, s2, s11, v2, s2
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v2, 1.0, v3 :: v_dual_sub_f32 v5, 1.0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v3, s9, v2
	v_fmac_f32_e32 v1, s9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s2, 0x800000, v3
	v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v3, v2
	v_log_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x3f317217, v2
	v_cmp_gt_f32_e64 s3, 0x7f800000, |v2|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, 0x3f317217, v2, -v3
	v_fmamk_f32 v4, v2, 0x3377d1cf, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v4
	v_cndmask_b32_e64 v2, v2, v3, s3
	v_cndmask_b32_e64 v3, 0, 0x41b17218, s2
	v_cmp_nlt_f32_e64 s2, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v2, v3
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e64 v2, v3, -v1
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr3
; %bb.3:                                ; %Flow93
	s_and_not1_saveexec_b32 s9, s2
	s_cbranch_execz .LBB2_5
; %bb.4:
	v_cmp_gt_f32_e64 s2, 0x800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s2
	v_mul_f32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_log_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x3f317217, v2
	v_cmp_gt_f32_e64 s3, 0x7f800000, |v2|
	v_fma_f32 v5, 0x3f317217, v2, -v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v5, v2, 0x3377d1cf, v5
	v_add_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v2, v4, s3
	v_cndmask_b32_e64 v4, 0, 0x41b17218, s2
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v3
	v_mul_f32_e32 v2, v1, v2
.LBB2_5:                                ; %Flow94
	s_or_b32 exec_lo, exec_lo, s9
.LBB2_6:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s8
	v_lshrrev_b32_e32 v1, 5, v0
	v_add_lshl_u32 v1, v1, v0, 2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s3, 2
	s_cbranch_scc1 .LBB2_13
; %bb.7:                                ; %.lr.ph
	s_mov_b32 s8, 1
.LBB2_8:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s10, s8
	s_lshl_b32 s8, s8, 1
	s_and_saveexec_b32 s9, s7
	s_cbranch_execz .LBB2_12
; %bb.9:                                ;   in Loop: Header=BB2_8 Depth=1
	s_add_i32 s2, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, s2, v0
	v_cmp_eq_u32_e64 s2, 0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_12
; %bb.10:                               ;   in Loop: Header=BB2_8 Depth=1
	v_add_nc_u32_e32 v2, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s6, v2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_12
; %bb.11:                               ;   in Loop: Header=BB2_8 Depth=1
	v_lshrrev_b32_e32 v3, 5, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v2, v3, v2, 2
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB2_12:                               ; %._crit_edge73
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_cmp_ge_u32 s8, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_8
.LBB2_13:                               ; %._crit_edge
	v_cmp_eq_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s5
	s_mov_b32 s5, 0
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_15
; %bb.14:
	v_mov_b32_e32 v0, 0
	s_load_b64 s[0:1], s[0:1], 0x20
	s_lshl_b64 s[2:3], s[4:5], 2
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_store_b32 v0, v1, s[0:1]
.LBB2_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf, .Lfunc_end2-_Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 800
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf ; -- Begin function _Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.globl	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
	.p2align	8
	.type	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf,@function
_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf: ; @_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s5, 0, s2
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s5, v3
	v_mul_hi_u32 v4, v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v4
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v0, s2
	v_add_nc_u32_e32 v3, 1, v0
	v_sub_nc_u32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v4, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_mov_b32 s2, exec_lo
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v0
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf, .Lfunc_end3-_Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_ ; -- Begin function _Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.globl	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
	.p2align	8
	.type	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_,@function
_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_: ; @_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
; %bb.0:
	s_mov_b32 s12, s15
	s_clause 0x2
	s_load_b64 s[14:15], s[0:1], 0x8
	s_load_b256 s[4:11], s[0:1], 0x10
	s_load_b64 s[16:17], s[0:1], 0x30
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u32_e32 vcc_lo, s14, v0
	s_cmp_lt_u32 s12, s15
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s15, vcc_lo, s3
	s_and_saveexec_b32 s18, s15
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_mad_u64_u32 v[1:2], null, s12, s14, v[0:1]
	s_load_b64 s[20:21], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v4, s2, s5, v2, s2
	s_lshl_b64 s[4:5], s[12:13], 2
	s_add_u32 s4, s6, s4
	global_load_b32 v5, v[3:4], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s2, s20, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s2, s21, v2, s2
	s_addc_u32 s5, s7, s5
	s_load_b32 s2, s[4:5], 0x0
	global_load_b32 v6, v[3:4], off
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_subrev_f32_e32 v5, s2, v5
	v_add_co_u32 v3, s2, s16, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s2, s17, v2, s2
	v_add_co_u32 v1, s2, s8, v1
	v_add_co_ci_u32_e64 v2, s2, s9, v2, s2
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v6, v6, v5
	global_store_b32 v[3:4], v6, off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e64 v2, v5, -v1
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s18
	v_lshrrev_b32_e32 v1, 5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_load_b32 s0, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s1, 2
	s_cbranch_scc1 .LBB4_9
; %bb.3:                                ; %.lr.ph
	s_mov_b32 s2, 1
.LBB4_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, s2
	s_lshl_b32 s2, s2, 1
	s_and_saveexec_b32 s4, s15
	s_cbranch_execz .LBB4_8
; %bb.5:                                ;   in Loop: Header=BB4_4 Depth=1
	s_add_i32 s0, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, s0, v0
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_8
; %bb.6:                                ;   in Loop: Header=BB4_4 Depth=1
	v_add_nc_u32_e32 v2, s5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s0, s14, v2
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_8
; %bb.7:                                ;   in Loop: Header=BB4_4 Depth=1
	v_lshrrev_b32_e32 v3, 5, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v2, v3, v2, 2
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB4_8:                                ; %._crit_edge69
                                        ;   in Loop: Header=BB4_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_cmp_ge_u32 s2, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB4_4
.LBB4_9:                                ; %._crit_edge
	v_cmp_eq_u32_e64 s0, 0, v0
	s_mov_b32 s13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s3
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_11
; %bb.10:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s10, s0
	s_addc_u32 s1, s11, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB4_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_, .Lfunc_end4-_Z27softmax_kl_loss_rfwd_kernelPKfjjS0_S0_S0_PfS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 24
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf ; -- Begin function _Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.globl	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
	.p2align	8
	.type	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf,@function
_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf: ; @_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB5_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v4, v[0:1], off
	v_add_co_u32 v0, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
	v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v4, v1
	v_log_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x3f317217, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0x3f317217, v1, -v4
	v_fmamk_f32 v5, v1, 0x3377d1cf, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v4, v5
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v5
	s_waitcnt vmcnt(0)
	v_mul_f32_e64 v4, v0, -v1
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf, .Lfunc_end5-_Z27softmax_nll_loss_fwd_kernelPKfiiPKjS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 364
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf ; -- Begin function _Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.globl	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
	.p2align	8
	.type	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf,@function
_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf: ; @_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s8, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s4, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, s3
	v_cvt_f32_u32_e32 v1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s4
	s_cmp_gt_i32 s8, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, s2, v3
	s_cselect_b32 s2, -1, 0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v3, v0
	v_add_nc_u32_e32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v2
	v_add_nc_u32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v3, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s9, v3
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_clause 0x1
	s_load_b64 s[10:11], s[0:1], 0x0
	s_load_b256 s[0:7], s[0:1], 0x10
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_mul_lo_u32 v3, v3, s8
	v_sub_nc_u32_e32 v1, v1, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v13, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	global_load_b32 v0, v[9:10], off
	global_load_b32 v2, v[11:12], off
	global_load_b32 v4, v[13:14], off
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v2, v2, v4
	v_add_f32_e32 v3, -1.0, v0
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_mul_f32_e32 v2, v0, v2
	v_add_co_u32 v0, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v6, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf, .Lfunc_end6-_Z27softmax_nll_loss_bwd_kernelPKfiiPKjS0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 452
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf ; -- Begin function _Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.globl	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
	.p2align	8
	.type	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf,@function
_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf: ; @_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s5, 0, s2
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s5, v3
	v_mul_hi_u32 v4, v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v4
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v0, s2
	v_add_nc_u32_e32 v3, 1, v0
	v_sub_nc_u32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_subrev_nc_u32_e32 v4, s2, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, 1, v0
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_cndmask_b32_e32 v3, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v3
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v2, v4
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_mul_lo_u32 v3, v3, s2
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v1, v1, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v12, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v0, v[10:11], off
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v2, v[12:13], off
	global_load_b32 v8, v[8:9], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(3)
	v_add_f32_e32 v3, -1.0, v0
	v_fma_f32 v5, v0, -2.0, 1.0
	s_waitcnt vmcnt(1)
	v_cmp_eq_u32_e32 vcc_lo, v1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, v2, v5
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v1, v4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v0, v1
	v_add_co_u32 v0, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v7, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf, .Lfunc_end7-_Z28softmax_nll_loss_bwd2_kernelPKfjjPKjS0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 420
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf ; -- Begin function _Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.globl	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
	.p2align	8
	.type	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf,@function
_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf: ; @_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB8_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	global_load_b32 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v1, s2, v[0:1]
	v_mov_b32_e32 v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[5:6], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v0, v2
	v_xor_b32_e32 v2, 0x80000000, v0
	v_add_co_u32 v0, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB8_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf, .Lfunc_end8-_Z28softmax_nll_loss_rfwd_kernelPKfjjS0_PKjPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26softmax_lr_loss_fwd_kernelPKfjjPKjS0_S0_fPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26softmax_lr_loss_bwd_kernelPKfjjPKjS0_S0_fPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4224
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26softmax_kl_loss_fwd_kernelPKfjjS0_fPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
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        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26softmax_kl_loss_bwd_kernelPKfjjS0_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
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amdhsa.version:
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...

	.end_amdgpu_metadata
