#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>

#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
 
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];

__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int row_o = blockIdx.y * TILE_SIZE + ty;
    int col_o = blockIdx.x * TILE_SIZE + tx;
    int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
    int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
    int i=0;
    int j=0;
    float output = 0.0f;
    __shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];

    if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
        Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
    }  
    else{
        Ms[ty][tx] = 0.0f;
    }
    if(ty < TILE_SIZE && tx < TILE_SIZE){
        for(i = 0; i < KERNEL_SIZE; i++){
            for(j = 0; j < KERNEL_SIZE; j++){
                output += Mc[i][j] * Ms[i+ty][j+tx];
                //printf("Mc[%d][%d]:%f  Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
            }
        }
        // some threads do not write output
        if(row_o < P_Width_row && col_o < P_Width_col){
            d_P[row_o * P_Width_col + col_o] = output;
        }   
    }
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
    float *d_M,*d_N,*d_P;
    float *h_M,*h_N,*h_P;
    // cudaEvent_t start,end;
    // float time_ms=0;
    // cudaEventCreate(&start);
    // cudaEventCreate(&end);

    h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
    h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
    h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
    memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));

    for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
        h_M[i]=i+1;
    }
    for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
        h_N[i]=100+i;
    }
    
    cudaMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
    cudaMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
    cudaMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);

   
    cudaMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
    cudaMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
    cudaMemcpyToSymbol(Mc, h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,cudaMemcpyHostToDevice);

    dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
    
    // cudaEventRecord(start,0);
    Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
    // cudaEventRecord(end,0);
    //printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);

    cudaMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyDeviceToHost);
    
    verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
    free(h_P);
    free(h_M);
    free(h_N);
    cudaFree(d_P);
    cudaFree(d_M);
    cudaFree(d_N);
   
    return 0;
}

void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
	int r, c, h, w;
	int row_i, col_i;
	bool equal;
	float* results;
	results = (float*)malloc(Rows * Columns * sizeof(float));
	memset(results, 0, Rows * Columns * sizeof(float));
  
	for (r = 0; r < Rows; r++) {
       
		for (c = 0; c < Columns; c++) {
            
			for (h = 0; h < KERNEL_SIZE; h++) {
                
				for (w = 0; w < KERNEL_SIZE; w++) {
					row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
					col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
					if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
						results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
					}
				}
			}
		}
	}

	equal = true;
	for (int i = 0; i < Rows * Columns && equal; i++) {
        //printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
		if (abs(results[i] - P[i]) >= 0.001f) {
			equal = false;
			printf("NOT EQUAL!\n");
		}
	}

	if (equal) {
		printf("Results are equal!\n");
	}
	else {
		printf("Results are NOT equal!\n");
	}

	free(results);
	return;
}




#include <iostream>

#define     MASK_WIDTH      3
#define     MASK_RADIUS     MASK_WIDTH / 2
#define     TILE_WIDTH      8
#define         W           (TILE_WIDTH + MASK_WIDTH - 1)

/**
 * GPU 2D Convolution using shared memory
 */



	.file	"tmpxft_002c1146_00000000-6_lab6.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3652:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3652:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"NOT EQUAL!\n"
.LC3:
	.string	"Results are equal!\n"
.LC4:
	.string	"Results are NOT equal!\n"
	.text
	.globl	_Z12verificationPKfS0_S0_ii
	.type	_Z12verificationPKfS0_S0_ii, @function
_Z12verificationPKfS0_S0_ii:
.LFB2041:
	.cfi_startproc
	endbr64
	movl	%ecx, %eax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	imull	%r8d, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movslq	%eax, %r13
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	salq	$2, %r13
	movl	%r8d, %ebx
	imull	$-2, %ebx, %r14d
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 16(%rsp)
	movq	%r13, %rdi
	movq	%rsi, 24(%rsp)
	movq	%rdx, 32(%rsp)
	movl	%eax, 12(%rsp)
	call	malloc@PLT
	movq	%r13, %rcx
	movq	%r13, %rdx
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, %rbp
	call	__memset_chk@PLT
	movl	%r14d, %r8d
	movl	$-2, %ecx
.L3:
	leal	2(%rcx), %eax
	cmpl	%eax, %r12d
	jle	.L17
	movl	%r8d, %eax
	subl	%r14d, %eax
	movl	%eax, 40(%rsp)
	xorl	%eax, %eax
.L10:
	cmpl	%ebx, %eax
	jge	.L7
	movl	40(%rsp), %edi
	movl	%r8d, %r9d
	xorl	%esi, %esi
	leal	(%rdi,%rax), %edx
	movl	%ecx, %edi
	movslq	%edx, %rdx
	leaq	0(%rbp,%rdx,4), %r15
	leal	3(%rax), %edx
	movl	%edx, 44(%rsp)
.L8:
	leal	-2(%rax), %edx
	movl	%esi, %r10d
.L5:
	cmpl	%edi, %r12d
	jle	.L4
	movl	%edx, %r11d
	orl	%edi, %r11d
	js	.L4
	cmpl	%edx, %ebx
	jle	.L4
	movq	16(%rsp), %r11
	leal	(%rdx,%r9), %r13d
	movslq	%r13d, %r13
	movss	(%r11,%r13,4), %xmm0
	movq	24(%rsp), %r13
	movslq	%r10d, %r11
	mulss	0(%r13,%r11,4), %xmm0
	addss	(%r15), %xmm0
	movss	%xmm0, (%r15)
.L4:
	movl	44(%rsp), %r11d
	incl	%edx
	incl	%r10d
	cmpl	%r11d, %edx
	jne	.L5
	addl	$5, %esi
	addl	%ebx, %r9d
	incl	%edi
	cmpl	$25, %esi
	jne	.L8
	incl	%eax
	jmp	.L10
.L7:
	movl	40(%rsp), %r8d
	incl	%ecx
	subl	%ebx, %r8d
	jmp	.L3
.L17:
	xorl	%ebx, %ebx
	movb	$1, %al
.L9:
	cmpl	%ebx, 12(%rsp)
	jle	.L13
	testb	%al, %al
	je	.L15
	movq	32(%rsp), %rcx
	movss	0(%rbp,%rbx,4), %xmm0
	subss	(%rcx,%rbx,4), %xmm0
	andps	.LC0(%rip), %xmm0
	comiss	.LC1(%rip), %xmm0
	jb	.L11
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L11:
	incq	%rbx
	jmp	.L9
.L13:
	leaq	.LC3(%rip), %rsi
	testb	%al, %al
	jne	.L27
.L15:
	leaq	.LC4(%rip), %rsi
.L27:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2041:
	.size	_Z12verificationPKfS0_S0_ii, .-_Z12verificationPKfS0_S0_ii
	.globl	_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
	.type	_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii, @function
_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii:
.LFB3674:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z13Convolution2DPfS_S_iiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L29:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3674:
	.size	_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii, .-_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
	.globl	_Z13Convolution2DPfS_S_iiii
	.type	_Z13Convolution2DPfS_S_iiii, @function
_Z13Convolution2DPfS_S_iiii:
.LFB3675:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
	.cfi_endproc
.LFE3675:
	.size	_Z13Convolution2DPfS_S_iiii, .-_Z13Convolution2DPfS_S_iiii
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$784, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$100, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$784, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$196, %ecx
	movq	%rax, %rbx
	xorl	%eax, %eax
	movq	%rbx, %rdi
	rep stosl
	movl	$1, %eax
.L35:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, -4(%r12,%rax,4)
	incq	%rax
	cmpq	$197, %rax
	jne	.L35
	xorl	%eax, %eax
.L36:
	leal	100(%rax), %edx
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$25, %rax
	jne	.L36
	leaq	8(%rsp), %rdi
	movl	$784, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$100, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$784, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$784, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$784, %edx
	call	cudaMemcpy@PLT
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbp, %rsi
	movl	$100, %edx
	leaq	_ZL2Mc(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$77309411346, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	pushq	%rax
	.cfi_def_cfa_offset 104
	movl	$14, %ecx
	movl	$14, %r9d
	movl	$14, %r8d
	pushq	$14
	.cfi_def_cfa_offset 112
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
	popq	%rdx
	.cfi_def_cfa_offset 104
	popq	%rcx
	.cfi_def_cfa_offset 96
.L37:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$784, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	$14, %ecx
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$14, %r8d
	movq	%r12, %rdi
	call	_Z12verificationPKfS0_S0_ii
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z13Convolution2DPfS_S_iiii"
.LC6:
	.string	"Mc"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3677:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13Convolution2DPfS_S_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movl	$100, %r9d
	leaq	_ZL2Mc(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3677:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL2Mc
	.comm	_ZL2Mc,100,32
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC0:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	981668463
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>

#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
 
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];

__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int row_o = blockIdx.y * TILE_SIZE + ty;
    int col_o = blockIdx.x * TILE_SIZE + tx;
    int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
    int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
    int i=0;
    int j=0;
    float output = 0.0f;
    __shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];

    if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
        Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
    }  
    else{
        Ms[ty][tx] = 0.0f;
    }
    if(ty < TILE_SIZE && tx < TILE_SIZE){
        for(i = 0; i < KERNEL_SIZE; i++){
            for(j = 0; j < KERNEL_SIZE; j++){
                output += Mc[i][j] * Ms[i+ty][j+tx];
                //printf("Mc[%d][%d]:%f  Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
            }
        }
        // some threads do not write output
        if(row_o < P_Width_row && col_o < P_Width_col){
            d_P[row_o * P_Width_col + col_o] = output;
        }   
    }
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
    float *d_M,*d_N,*d_P;
    float *h_M,*h_N,*h_P;
    // cudaEvent_t start,end;
    // float time_ms=0;
    // cudaEventCreate(&start);
    // cudaEventCreate(&end);

    h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
    h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
    h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
    memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));

    for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
        h_M[i]=i+1;
    }
    for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
        h_N[i]=100+i;
    }
    
    hipMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
    hipMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
    hipMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);

   
    hipMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
    hipMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
    hipMemcpyToSymbol(HIP_SYMBOL(Mc), h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,hipMemcpyHostToDevice);

    dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
    
    // cudaEventRecord(start,0);
    Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
    // cudaEventRecord(end,0);
    //printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);

    hipMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyDeviceToHost);
    
    verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
    free(h_P);
    free(h_M);
    free(h_N);
    hipFree(d_P);
    hipFree(d_M);
    hipFree(d_N);
   
    return 0;
}

void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
	int r, c, h, w;
	int row_i, col_i;
	bool equal;
	float* results;
	results = (float*)malloc(Rows * Columns * sizeof(float));
	memset(results, 0, Rows * Columns * sizeof(float));
  
	for (r = 0; r < Rows; r++) {
       
		for (c = 0; c < Columns; c++) {
            
			for (h = 0; h < KERNEL_SIZE; h++) {
                
				for (w = 0; w < KERNEL_SIZE; w++) {
					row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
					col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
					if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
						results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
					}
				}
			}
		}
	}

	equal = true;
	for (int i = 0; i < Rows * Columns && equal; i++) {
        //printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
		if (abs(results[i] - P[i]) >= 0.001f) {
			equal = false;
			printf("NOT EQUAL!\n");
		}
	}

	if (equal) {
		printf("Results are equal!\n");
	}
	else {
		printf("Results are NOT equal!\n");
	}

	free(results);
	return;
}




#include <iostream>

#define     MASK_WIDTH      3
#define     MASK_RADIUS     MASK_WIDTH / 2
#define     TILE_WIDTH      8
#define         W           (TILE_WIDTH + MASK_WIDTH - 1)

/**
 * GPU 2D Convolution using shared memory
 */



	.text
	.file	"lab6.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z28__device_stub__Convolution2DPfS_S_iiii # -- Begin function _Z28__device_stub__Convolution2DPfS_S_iiii
	.type	_Z28__device_stub__Convolution2DPfS_S_iiii,@function
_Z28__device_stub__Convolution2DPfS_S_iiii: # @_Z28__device_stub__Convolution2DPfS_S_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13Convolution2DPfS_S_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__Convolution2DPfS_S_iiii, .Lfunc_end0-_Z28__device_stub__Convolution2DPfS_S_iiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$784, %edi                      # imm = 0x310
	callq	malloc
	movq	%rax, %rbx
	movl	$100, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$1, %edi
	movl	$784, %esi                      # imm = 0x310
	callq	calloc@PLT
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%rax), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	movq	%rcx, %rax
	cmpq	$196, %rcx
	jne	.LBB1_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	leal	100(%rax), %ecx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	cmpq	$25, %rax
	jne	.LBB1_3
# %bb.4:
	leaq	24(%rsp), %r12
	movl	$784, %esi                      # imm = 0x310
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$100, %esi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$784, %esi                      # imm = 0x310
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$784, %edx                      # imm = 0x310
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$784, %edx                      # imm = 0x310
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$Mc, %edi
	movl	$100, %edx
	movq	%r14, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$77309411346, %rdx              # imm = 0x1200000012
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$14, (%rsp)
	movl	$14, %ecx
	movl	$14, %r8d
	movl	$14, %r9d
	callq	_Z28__device_stub__Convolution2DPfS_S_iiii
.LBB1_6:
	movq	8(%rsp), %rsi
	movl	$784, %edx                      # imm = 0x310
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$14, %ecx
	movl	$14, %r8d
	callq	_Z12verificationPKfS0_S0_ii
	movq	%r15, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z12verificationPKfS0_S0_ii
.LCPI2_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI2_1:
	.long	0x3a83126f                      # float 0.00100000005
	.text
	.globl	_Z12verificationPKfS0_S0_ii
	.type	_Z12verificationPKfS0_S0_ii,@function
_Z12verificationPKfS0_S0_ii:            # @_Z12verificationPKfS0_S0_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r13d
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, %r14
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movl	%r8d, 4(%rsp)                   # 4-byte Spill
	imull	%ecx, %r8d
	movl	%r8d, 36(%rsp)                  # 4-byte Spill
	movslq	%r8d, %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	leaq	(,%rax,4), %rsi
	movl	$1, %edi
	callq	calloc@PLT
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	testl	%r13d, %r13d
	jle	.LBB2_15
# %bb.1:                                # %.preheader61.lr.ph
	movslq	4(%rsp), %rax                   # 4-byte Folded Reload
	movl	%r13d, %ecx
	movl	%eax, %edx
	leaq	(,%rax,8), %rsi
	subq	%rsi, 16(%rsp)                  # 8-byte Folded Spill
	leaq	(,%rax,4), %rsi
	xorl	%edi, %edi
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
.LBB2_2:                                # %.preheader61
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
                                        #       Child Loop BB2_5 Depth 3
                                        #         Child Loop BB2_6 Depth 4
	cmpl	$0, 4(%rsp)                     # 4-byte Folded Reload
	jle	.LBB2_14
# %bb.3:                                # %.preheader60.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	movq	24(%rsp), %rdi                  # 8-byte Reload
	leaq	-2(%rdi), %r8
	imulq	%rax, %rdi
	movq	8(%rsp), %r9                    # 8-byte Reload
	leaq	(%r9,%rdi,4), %r9
	movq	16(%rsp), %r10                  # 8-byte Reload
	xorl	%edi, %edi
.LBB2_4:                                # %.preheader60
                                        #   Parent Loop BB2_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_5 Depth 3
                                        #         Child Loop BB2_6 Depth 4
	movq	%r10, %r13
	movq	%r14, %r15
	xorl	%ebx, %ebx
.LBB2_5:                                # %.preheader59
                                        #   Parent Loop BB2_2 Depth=1
                                        #     Parent Loop BB2_4 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB2_6 Depth 4
	leaq	(%r8,%rbx), %rbp
	movq	$-2, %r12
.LBB2_6:                                #   Parent Loop BB2_2 Depth=1
                                        #     Parent Loop BB2_4 Depth=2
                                        #       Parent Loop BB2_5 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	testq	%rbp, %rbp
	js	.LBB2_11
# %bb.7:                                #   in Loop: Header=BB2_6 Depth=4
	cmpq	%rcx, %rbp
	jge	.LBB2_11
# %bb.8:                                #   in Loop: Header=BB2_6 Depth=4
	movq	%rdi, %r11
	addq	%r12, %r11
	js	.LBB2_11
# %bb.9:                                #   in Loop: Header=BB2_6 Depth=4
	cmpq	%rax, %r11
	jge	.LBB2_11
# %bb.10:                               #   in Loop: Header=BB2_6 Depth=4
	movss	8(%r15,%r12,4), %xmm0           # xmm0 = mem[0],zero,zero,zero
	mulss	(%r13,%r12,4), %xmm0
	addss	(%r9,%rdi,4), %xmm0
	movss	%xmm0, (%r9,%rdi,4)
.LBB2_11:                               #   in Loop: Header=BB2_6 Depth=4
	incq	%r12
	cmpq	$3, %r12
	jne	.LBB2_6
# %bb.12:                               #   in Loop: Header=BB2_5 Depth=3
	incq	%rbx
	addq	$20, %r15
	addq	%rsi, %r13
	cmpq	$5, %rbx
	jne	.LBB2_5
# %bb.13:                               #   in Loop: Header=BB2_4 Depth=2
	incq	%rdi
	addq	$4, %r10
	cmpq	%rdx, %rdi
	jne	.LBB2_4
.LBB2_14:                               # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	movq	24(%rsp), %r8                   # 8-byte Reload
	incq	%r8
	addq	%rsi, 16(%rsp)                  # 8-byte Folded Spill
	movq	%r8, %rdi
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	cmpq	%rcx, %r8
	jne	.LBB2_2
.LBB2_15:                               # %.preheader
	movl	$.Lstr.1, %edi
	cmpl	$0, 36(%rsp)                    # 4-byte Folded Reload
	jle	.LBB2_20
# %bb.16:                               # %.lr.ph.preheader
	xorl	%eax, %eax
	movaps	.LCPI2_0(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	8(%rsp), %rcx                   # 8-byte Reload
.LBB2_17:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rcx,%rax,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	(%rdx,%rax,4), %xmm2
	andps	%xmm0, %xmm2
	ucomiss	%xmm1, %xmm2
	jae	.LBB2_18
# %bb.19:                               #   in Loop: Header=BB2_17 Depth=1
	incq	%rax
	cmpq	%rsi, %rax
	jl	.LBB2_17
	jmp	.LBB2_20
.LBB2_18:                               # %._crit_edge68.thread
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$.Lstr, %edi
.LBB2_20:                               # %.critedge
	callq	puts@PLT
	movq	8(%rsp), %rdi                   # 8-byte Reload
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	free                            # TAILCALL
.Lfunc_end2:
	.size	_Z12verificationPKfS0_S0_ii, .Lfunc_end2-_Z12verificationPKfS0_S0_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13Convolution2DPfS_S_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$Mc, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$100, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	Mc,@object                      # @Mc
	.local	Mc
	.comm	Mc,100,16
	.type	_Z13Convolution2DPfS_S_iiii,@object # @_Z13Convolution2DPfS_S_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z13Convolution2DPfS_S_iiii
	.p2align	3, 0x0
_Z13Convolution2DPfS_S_iiii:
	.quad	_Z28__device_stub__Convolution2DPfS_S_iiii
	.size	_Z13Convolution2DPfS_S_iiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13Convolution2DPfS_S_iiii"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"Mc"
	.size	.L__unnamed_2, 3

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Results are NOT equal!"
	.size	.Lstr, 23

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Results are equal!"
	.size	.Lstr.1, 19

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"NOT EQUAL!"
	.size	.Lstr.2, 11

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__Convolution2DPfS_S_iiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym Mc
	.addrsig_sym _Z13Convolution2DPfS_S_iiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13Convolution2DPfS_S_iiii ; -- Begin function _Z13Convolution2DPfS_S_iiii
	.globl	_Z13Convolution2DPfS_S_iiii
	.p2align	8
	.type	_Z13Convolution2DPfS_S_iiii,@function
_Z13Convolution2DPfS_S_iiii:            ; @_Z13Convolution2DPfS_S_iiii
; %bb.0:
	v_bfe_u32 v4, v0, 10, 10
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, 14, v[4:5]
	v_mov_b32_e32 v5, 0
	v_mad_u64_u32 v[2:3], null, s14, 14, v[0:1]
	v_cmpx_lt_i32_e32 1, v1
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_add_nc_u32_e32 v3, -2, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, -2, v2
	v_cmp_lt_i32_e64 s3, 1, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s2, s5, v5
	v_mov_b32_e32 v5, 0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s3
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mul_lo_u32 v3, v3, s5
	s_load_b64 s[4:5], s[0:1], 0x0
	v_ashrrev_i32_e32 v6, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v3
	v_add_co_u32 v5, vcc_lo, v3, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v5, v[5:6], off offset:-8
.LBB0_3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s8
	v_lshlrev_b32_e32 v3, 2, v0
	v_max_u32_e32 v0, v4, v0
	s_mov_b32 s2, exec_lo
	v_mad_u32_u24 v3, 0x48, v4, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v5
	v_cmpx_gt_u32_e32 14, v0
	s_cbranch_execz .LBB0_11
; %bb.5:                                ; %.preheader.preheader
	v_mov_b32_e32 v0, 0
	s_mov_b32 s8, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Mc@rel32@lo+4
	s_addc_u32 s3, s3, Mc@rel32@hi+12
.LBB0_6:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[4:5], s[2:3]
	s_mov_b32 s9, 0
.LBB0_7:                                ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s9, v3
	s_load_b32 s10, s[4:5], 0x0
	s_add_i32 s9, s9, 4
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	ds_load_b32 v4, v4
	s_cmp_lg_u32 s9, 20
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v0, s10, v4
	s_cbranch_scc1 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v3, 0x48, v3
	s_add_u32 s2, s2, 20
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s8, 5
	s_cbranch_scc1 .LBB0_6
; %bb.9:
	v_cmp_gt_i32_e32 vcc_lo, s6, v1
	v_cmp_gt_i32_e64 s2, s7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mad_u64_u32 v[3:4], null, v1, s7, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13Convolution2DPfS_S_iiii
		.amdhsa_group_segment_fixed_size 1296
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13Convolution2DPfS_S_iiii, .Lfunc_end0-_Z13Convolution2DPfS_S_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1296 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	Mc                      ; @Mc
	.type	Mc,@object
	.section	.bss,"aw",@nobits
	.globl	Mc
	.p2align	4, 0x0
Mc:
	.zero	100
	.size	Mc, 100

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym Mc
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1296
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13Convolution2DPfS_S_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13Convolution2DPfS_S_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
