#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define BLOCK_SIZE 16

// CPU Implementation
void cpu_matrix_mult(int *h_a, int *h_b, int *h_result, int m, int n, int k) {
  for (int i = 0; i < m; ++i) {
      for (int j = 0; j < k; ++j) {
          int tmp = 0.0;
          for (int h = 0; h < n; ++h) {
              tmp += h_a[i * n + h] * h_b[h * k + j];
          }
          h_result[i * k + j] = tmp;
      }
  }
}

// GPU Implementation

__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
    __shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
 
    int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
    int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
    int tmp = 0;
    int idx;

for (int sub = 0; sub < gridDim.x; ++sub) {
    idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
    if(idx >= n*n) {
        // n may not divisible by BLOCK_SIZE
        tile_a[threadIdx.y][threadIdx.x] = 0;
    } else {
        tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
    }

    idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
    if(idx >= n*n) {
        tile_b[threadIdx.y][threadIdx.x] = 0;
    } else {
        tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
    }
    __syncthreads();

    for (int k = 0; k < BLOCK_SIZE; ++k) {
		 tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
    }
    __syncthreads();
  }
  if(row < n && col < n) {
    d_result[row * n + col] = tmp;
  }
}
// Main Function

int main(int argc, char const *argv[])
{
    int m, n, k; // m x n matrix multiplied with n x k matrix
    float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
 
    srand(time(NULL));
 
    printf("Enter square matrix size (nxn): ");
    scanf("%d", &n);
 
    // We consider only square matrices.
    m = k = n;
 
    // allocate memory in host RAM, h_cc is used to store CPU result
    int *h_a, *h_b, *h_c, *h_cc;
    cudaMallocHost((void **) &h_a,  sizeof(int) * m * n);
    cudaMallocHost((void **) &h_b,  sizeof(int) * n * k);
    cudaMallocHost((void **) &h_c,  sizeof(int) * m * k);
    cudaMallocHost((void **) &h_cc, sizeof(int) * m * k);
 
printf("Filling matrices A and B with random values...\n");
 
// random initialize matrix A
for (int i = 0; i < m; ++i) {
    for (int j = 0; j < n; ++j) {
        h_a[i * n + j] = rand() % 1024;
    }
}
// random initialize matrix B
for (int i = 0; i < n; ++i) {
    for (int j = 0; j < k; ++j) {
        h_b[i * k + j] = rand() % 1024;
    }
}
// some events to count the execution time
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
 
printf("Running GPU Algorithm...\n");
// start to count execution time of GPU version
cudaEventRecord(start, 0);
 
// Allocate memory space on the device
int *d_a, *d_b, *d_c;
cudaMalloc((void **) &d_a, sizeof(int)*m*n);
cudaMalloc((void **) &d_b, sizeof(int)*n*k);
cudaMalloc((void **) &d_c, sizeof(int)*m*k);
 
// copy matrix A and B from host to device memory
cudaMemcpy(d_a, h_a, sizeof(int)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sizeof(int)*n*k, cudaMemcpyHostToDevice);
 
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
 
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
 
// Launch kernel
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
 
// Transfer results from device to host
cudaMemcpy(h_c, d_c, sizeof(int)*m*k, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();

// time counting terminate
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);

// compute time elapse on GPU computing
cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("GPU Time: %f ms.\n\n", gpu_elapsed_time_ms);

printf("Running CPU Algorithm...\n");

cudaEventRecord(start, 0);

cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("CPU Time: %f ms.\n\n", cpu_elapsed_time_ms);

// validate results computed by GPU

int all_ok = 1;

for (int i = 0; i < m; ++i) {
	for (int j = 0; j < k; ++j) {
		if(h_cc[i*k + j] != h_c[i*k + j]) {
			all_ok = 0;
		}
	}
}

// roughly compute speedup
if(all_ok) {
	printf("Results cross-verified as correct, speedup = %f\n", 
			cpu_elapsed_time_ms / gpu_elapsed_time_ms);
} else {
	printf("Incorrect results. \n");
}

// free memeory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFreeHost(h_cc);

printf("Exiting.\n");
return 0;
}

	.file	"tmpxft_002ab91d_00000000-6_matmul.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15cpu_matrix_multPiS_S_iii
	.type	_Z15cpu_matrix_multPiS_S_iii, @function
_Z15cpu_matrix_multPiS_S_iii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%r9d, %rax
	movq	%rsi, %r11
	xorl	%r10d, %r10d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	salq	$2, %rax
	xorl	%esi, %esi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	xorl	%ecx, %ecx
	movq	%rdx, -8(%rsp)
	movq	%rax, -16(%rsp)
.L3:
	cmpl	%ebx, %r10d
	jge	.L2
	movq	-8(%rsp), %rdx
	movslq	%esi, %rax
	leaq	(%rdx,%rax,4), %r15
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,4), %r14
	xorl	%eax, %eax
.L8:
	cmpl	%eax, %r9d
	jle	.L5
	leaq	(%r11,%rax,4), %r12
	xorl	%edx, %edx
	xorl	%ebp, %ebp
.L6:
	cmpl	%edx, %r8d
	jle	.L11
	movl	(%r14,%rdx,4), %r13d
	imull	(%r12), %r13d
	incq	%rdx
	addl	%r13d, %ebp
	movq	-16(%rsp), %r13
	addq	%r13, %r12
	jmp	.L6
.L11:
	movl	%ebp, (%r15,%rax,4)
	incq	%rax
	jmp	.L8
.L5:
	incl	%r10d
	addl	%r9d, %esi
	addl	%r8d, %ecx
	jmp	.L3
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z15cpu_matrix_multPiS_S_iii, .-_Z15cpu_matrix_multPiS_S_iii
	.globl	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
	.type	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, @function
_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22gpu_square_matrix_multPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, .-_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
	.globl	_Z22gpu_square_matrix_multPiS_S_i
	.type	_Z22gpu_square_matrix_multPiS_S_i, @function
_Z22gpu_square_matrix_multPiS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z22gpu_square_matrix_multPiS_S_i, .-_Z22gpu_square_matrix_multPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter square matrix size (nxn): "
.LC1:
	.string	"%d"
.LC2:
	.string	"Filling matrices A and B with random values...\n"
.LC3:
	.string	"Running GPU Algorithm...\n"
.LC4:
	.string	"GPU Time: %f ms.\n\n"
.LC5:
	.string	"Running CPU Algorithm...\n"
.LC6:
	.string	"CPU Time: %f ms.\n\n"
.LC7:
	.string	"Results cross-verified as correct, speedup = %f\n"
.LC8:
	.string	"Incorrect results. \n"
.LC9:
	.string	"Exiting.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$1024, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	28(%rsp), %rsi
	leaq	.LC1(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	28(%rsp), %rbx
	leaq	40(%rsp), %rdi
	movq	%rbx, %r12
	movq	%rbx, %rbp
	imulq	%rbx, %r12
	leaq	0(,%r12,4), %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMallocHost@PLT
	movslq	28(%rsp), %rsi
	leaq	48(%rsp), %rdi
	imulq	%rbx, %rsi
	salq	$2, %rsi
	call	cudaMallocHost@PLT
	movq	8(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMallocHost@PLT
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMallocHost@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L18:
	cmpl	%ebp, %r14d
	jge	.L37
	xorl	%r15d, %r15d
.L20:
	cmpl	%r15d, 28(%rsp)
	jle	.L38
	call	rand@PLT
	movl	28(%rsp), %ecx
	cltd
	idivl	%r13d
	movq	40(%rsp), %rax
	imull	%r14d, %ecx
	addl	%r15d, %ecx
	incl	%r15d
	movslq	%ecx, %rcx
	movl	%edx, (%rax,%rcx,4)
	jmp	.L20
.L38:
	incl	%r14d
	jmp	.L18
.L37:
	xorl	%r12d, %r12d
	xorl	%r14d, %r14d
.L21:
	cmpl	%r14d, 28(%rsp)
	jle	.L23
	movslq	%r12d, %r13
	xorl	%r15d, %r15d
	salq	$2, %r13
.L24:
	cmpl	%ebp, %r15d
	jge	.L39
	call	rand@PLT
	movl	$1024, %ecx
	incl	%r15d
	cltd
	idivl	%ecx
	movq	48(%rsp), %rax
	movl	%edx, (%rax,%r13)
	addq	$4, %r13
	jmp	.L24
.L39:
	incl	%r14d
	addl	%ebp, %r12d
	jmp	.L21
.L23:
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movslq	28(%rsp), %rsi
	leaq	88(%rsp), %rdi
	imulq	%rbx, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	28(%rsp), %rsi
	leaq	96(%rsp), %rdi
	imulq	%rbx, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	104(%rsp), %rdi
	call	cudaMalloc@PLT
	movslq	28(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	88(%rsp), %rdi
	imulq	%rbx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	28(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	96(%rsp), %rdi
	imulq	%rbx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leal	15(%rbp), %eax
	movl	$16, %ecx
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	$1, 120(%rsp)
	idivl	%ecx
	movl	$1, 132(%rsp)
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movq	%rdx, 124(%rsp)
	movl	%eax, 112(%rsp)
	movl	%eax, 116(%rsp)
	movq	112(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movl	28(%rsp), %ecx
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	movq	88(%rsp), %rdi
	call	_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
.L25:
	movq	8(%rsp), %rdx
	movq	104(%rsp), %rsi
	movl	$2, %ecx
	salq	$2, %rbx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	80(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	leaq	32(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	32(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rsi
	call	__printf_chk@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	28(%rsp), %r8d
	movl	%ebp, %r9d
	movl	%ebp, %ecx
	movq	64(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z15cpu_matrix_multPiS_S_iii
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	80(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	leaq	36(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movq	64(%rsp), %r8
	movq	56(%rsp), %r9
	movl	$1, %edx
	xorl	%r10d, %r10d
.L26:
	cmpl	%ebp, %ecx
	jge	.L40
	movq	%rsi, %rax
	xorl	%edi, %edi
.L28:
	movl	(%r9,%rax), %r11d
	cmpl	%r11d, (%r8,%rax)
	cmovne	%r10d, %edx
	incl	%edi
	addq	$4, %rax
	cmpl	%edi, %ebp
	jne	.L28
	incl	%ecx
	addq	%rbx, %rsi
	jmp	.L26
.L40:
	testl	%edx, %edx
	je	.L29
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	36(%rsp), %xmm0
	divss	32(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	jmp	.L30
.L29:
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L30:
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	48(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	56(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	64(%rsp), %rdi
	call	cudaFreeHost@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC9(%rip), %rsi
	call	__printf_chk@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z22gpu_square_matrix_multPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z22gpu_square_matrix_multPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#define BLOCK_SIZE 16

// CPU Implementation
void cpu_matrix_mult(int *h_a, int *h_b, int *h_result, int m, int n, int k) {
  for (int i = 0; i < m; ++i) {
      for (int j = 0; j < k; ++j) {
          int tmp = 0.0;
          for (int h = 0; h < n; ++h) {
              tmp += h_a[i * n + h] * h_b[h * k + j];
          }
          h_result[i * k + j] = tmp;
      }
  }
}

// GPU Implementation

__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
    __shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
    __shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
 
    int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
    int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
    int tmp = 0;
    int idx;

for (int sub = 0; sub < gridDim.x; ++sub) {
    idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
    if(idx >= n*n) {
        // n may not divisible by BLOCK_SIZE
        tile_a[threadIdx.y][threadIdx.x] = 0;
    } else {
        tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
    }

    idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
    if(idx >= n*n) {
        tile_b[threadIdx.y][threadIdx.x] = 0;
    } else {
        tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
    }
    __syncthreads();

    for (int k = 0; k < BLOCK_SIZE; ++k) {
		 tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
    }
    __syncthreads();
  }
  if(row < n && col < n) {
    d_result[row * n + col] = tmp;
  }
}
// Main Function

int main(int argc, char const *argv[])
{
    int m, n, k; // m x n matrix multiplied with n x k matrix
    float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
 
    srand(time(NULL));
 
    printf("Enter square matrix size (nxn): ");
    scanf("%d", &n);
 
    // We consider only square matrices.
    m = k = n;
 
    // allocate memory in host RAM, h_cc is used to store CPU result
    int *h_a, *h_b, *h_c, *h_cc;
    hipHostMalloc((void **) &h_a,  sizeof(int) * m * n, hipHostMallocDefault);
    hipHostMalloc((void **) &h_b,  sizeof(int) * n * k, hipHostMallocDefault);
    hipHostMalloc((void **) &h_c,  sizeof(int) * m * k, hipHostMallocDefault);
    hipHostMalloc((void **) &h_cc, sizeof(int) * m * k, hipHostMallocDefault);
 
printf("Filling matrices A and B with random values...\n");
 
// random initialize matrix A
for (int i = 0; i < m; ++i) {
    for (int j = 0; j < n; ++j) {
        h_a[i * n + j] = rand() % 1024;
    }
}
// random initialize matrix B
for (int i = 0; i < n; ++i) {
    for (int j = 0; j < k; ++j) {
        h_b[i * k + j] = rand() % 1024;
    }
}
// some events to count the execution time
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
 
printf("Running GPU Algorithm...\n");
// start to count execution time of GPU version
hipEventRecord(start, 0);
 
// Allocate memory space on the device
int *d_a, *d_b, *d_c;
hipMalloc((void **) &d_a, sizeof(int)*m*n);
hipMalloc((void **) &d_b, sizeof(int)*n*k);
hipMalloc((void **) &d_c, sizeof(int)*m*k);
 
// copy matrix A and B from host to device memory
hipMemcpy(d_a, h_a, sizeof(int)*m*n, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sizeof(int)*n*k, hipMemcpyHostToDevice);
 
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
 
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
 
// Launch kernel
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
 
// Transfer results from device to host
hipMemcpy(h_c, d_c, sizeof(int)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();

// time counting terminate
hipEventRecord(stop, 0);
hipEventSynchronize(stop);

// compute time elapse on GPU computing
hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("GPU Time: %f ms.\n\n", gpu_elapsed_time_ms);

printf("Running CPU Algorithm...\n");

hipEventRecord(start, 0);

cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("CPU Time: %f ms.\n\n", cpu_elapsed_time_ms);

// validate results computed by GPU

int all_ok = 1;

for (int i = 0; i < m; ++i) {
	for (int j = 0; j < k; ++j) {
		if(h_cc[i*k + j] != h_c[i*k + j]) {
			all_ok = 0;
		}
	}
}

// roughly compute speedup
if(all_ok) {
	printf("Results cross-verified as correct, speedup = %f\n", 
			cpu_elapsed_time_ms / gpu_elapsed_time_ms);
} else {
	printf("Incorrect results. \n");
}

// free memeory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipHostFree(h_cc);

printf("Exiting.\n");
return 0;
}

	.text
	.file	"matmul.hip"
	.globl	_Z15cpu_matrix_multPiS_S_iii    # -- Begin function _Z15cpu_matrix_multPiS_S_iii
	.type	_Z15cpu_matrix_multPiS_S_iii,@function
_Z15cpu_matrix_multPiS_S_iii:           # @_Z15cpu_matrix_multPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, -36(%rsp)                 # 4-byte Spill
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB0_7
# %bb.1:                                # %.preheader27.lr.ph
	movslq	-36(%rsp), %rax                 # 4-byte Folded Reload
	movl	%ecx, %r9d
	movl	%eax, %r10d
	movl	%r8d, %r11d
	movq	%rax, -32(%rsp)                 # 8-byte Spill
	leaq	(,%rax,4), %rbx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB0_2:                                # %.preheader27
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #       Child Loop BB0_9 Depth 3
	cmpl	$0, -36(%rsp)                   # 4-byte Folded Reload
	jle	.LBB0_6
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	%r14d, %eax
	movq	-24(%rsp), %rcx                 # 8-byte Reload
	leaq	(%rcx,%rax,4), %r12
	movq	%r15, %rax
	imulq	-32(%rsp), %rax                 # 8-byte Folded Reload
	movq	-8(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %r13
	movq	-16(%rsp), %rdi                 # 8-byte Reload
	xorl	%eax, %eax
.LBB0_4:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_9 Depth 3
	testl	%r8d, %r8d
	jle	.LBB0_5
# %bb.8:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB0_4 Depth=2
	xorl	%esi, %esi
	movq	%rdi, %rbp
	xorl	%edx, %edx
.LBB0_9:                                # %.lr.ph
                                        #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%rbp), %ecx
	imull	(%r12,%rsi,4), %ecx
	addl	%ecx, %edx
	incq	%rsi
	addq	%rbx, %rbp
	cmpq	%rsi, %r11
	jne	.LBB0_9
	jmp	.LBB0_10
.LBB0_5:                                #   in Loop: Header=BB0_4 Depth=2
	xorl	%edx, %edx
.LBB0_10:                               # %._crit_edge
                                        #   in Loop: Header=BB0_4 Depth=2
	movl	%edx, (%r13,%rax,4)
	incq	%rax
	addq	$4, %rdi
	cmpq	%r10, %rax
	jne	.LBB0_4
.LBB0_6:                                # %._crit_edge31
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r15
	addl	%r8d, %r14d
	cmpq	%r9, %r15
	jne	.LBB0_2
.LBB0_7:                                # %._crit_edge33
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z15cpu_matrix_multPiS_S_iii, .Lfunc_end0-_Z15cpu_matrix_multPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__gpu_square_matrix_multPiS_S_i # -- Begin function _Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.type	_Z37__device_stub__gpu_square_matrix_multPiS_S_i,@function
_Z37__device_stub__gpu_square_matrix_multPiS_S_i: # @_Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22gpu_square_matrix_multPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z37__device_stub__gpu_square_matrix_multPiS_S_i, .Lfunc_end1-_Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%r12d, %r12d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	12(%rsp), %r15
	movl	$.L.str.1, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%r15), %rbp
	leaq	(,%rbp,4), %r13
	movq	%r13, %r14
	imulq	%rbp, %r14
	leaq	32(%rsp), %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movslq	(%r15), %rsi
	imulq	%r13, %rsi
	leaq	24(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	64(%rsp), %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	56(%rsp), %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	%ebp, %ebx
	movl	(%r15), %eax
	testq	%rbp, %rbp
	movq	%r14, 96(%rsp)                  # 8-byte Spill
	jle	.LBB2_5
.LBB2_1:                                # %.preheader72
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_3 Depth 2
	testl	%eax, %eax
	jle	.LBB2_4
# %bb.2:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB2_1 Depth=1
	movslq	%r12d, %r15
	xorl	%ebp, %ebp
.LBB2_3:                                # %.lr.ph
                                        #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	movq	32(%rsp), %rcx
	movslq	12(%rsp), %rdx
	imulq	%r15, %rdx
	addq	%rbp, %rdx
	movl	%eax, (%rcx,%rdx,4)
	movl	12(%rsp), %eax
	incq	%rbp
	cmpl	%eax, %ebp
	jl	.LBB2_3
.LBB2_4:                                # %._crit_edge
                                        #   in Loop: Header=BB2_1 Depth=1
	incl	%r12d
	cmpl	%ebx, %r12d
	jne	.LBB2_1
.LBB2_5:                                # %.preheader71
	testl	%eax, %eax
	jle	.LBB2_11
# %bb.6:                                # %.preheader70.lr.ph
	xorl	%r14d, %r14d
	xorl	%r12d, %r12d
.LBB2_7:                                # %.preheader70
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_8 Depth 2
	movl	%r14d, %r14d
	movq	%rbx, %rbp
	movq	%r14, %r15
	testl	%ebx, %ebx
	jle	.LBB2_10
.LBB2_8:                                #   Parent Loop BB2_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	movq	24(%rsp), %rcx
	movl	%eax, (%rcx,%r15,4)
	incq	%r15
	decq	%rbp
	jne	.LBB2_8
# %bb.9:                                # %._crit_edge77.loopexit
                                        #   in Loop: Header=BB2_7 Depth=1
	movl	12(%rsp), %eax
.LBB2_10:                               # %._crit_edge77
                                        #   in Loop: Header=BB2_7 Depth=1
	incq	%r12
	movslq	%eax, %rcx
	addl	%ebx, %r14d
	cmpq	%rcx, %r12
	jl	.LBB2_7
.LBB2_11:                               # %._crit_edge79
	leaq	48(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movslq	12(%rsp), %rsi
	imulq	%r13, %rsi
	leaq	88(%rsp), %r15
	movq	%r15, %rdi
	callq	hipMalloc
	movslq	12(%rsp), %rsi
	imulq	%r13, %rsi
	leaq	80(%rsp), %r12
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	96(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	32(%rsp), %rsi
	movslq	12(%rsp), %rdx
	imulq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	24(%rsp), %rsi
	movslq	12(%rsp), %rdx
	imulq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%rbx), %eax
	leal	30(%rbx), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$4, %ecx
	movq	%rcx, %rdi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_13
# %bb.12:
	movq	88(%rsp), %rdi
	movq	80(%rsp), %rsi
	movq	40(%rsp), %rdx
	movl	12(%rsp), %ecx
	callq	_Z37__device_stub__gpu_square_matrix_multPiS_S_i
.LBB2_13:
	movq	64(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	48(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	76(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	56(%rsp), %rdx
	movl	12(%rsp), %r8d
	movl	%ebx, %ecx
	movl	%ebx, %r9d
	callq	_Z15cpu_matrix_multPiS_S_iii
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	48(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	72(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	testl	%ebx, %ebx
	jle	.LBB2_19
# %bb.14:                               # %.preheader.lr.ph
	movq	56(%rsp), %rcx
	movl	$1, %eax
	movq	64(%rsp), %rdx
	xorl	%esi, %esi
	xorl	%edi, %edi
.LBB2_15:                               # %.lr.ph82
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_16 Depth 2
	movl	%esi, %r9d
	leaq	(%rdx,%r9,4), %r8
	leaq	(%rcx,%r9,4), %r9
	xorl	%r10d, %r10d
.LBB2_16:                               #   Parent Loop BB2_15 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r9,%r10,4), %r11d
	cmpl	(%r8,%r10,4), %r11d
	cmovnel	%r15d, %eax
	incq	%r10
	cmpq	%r10, %rbx
	jne	.LBB2_16
# %bb.17:                               # %._crit_edge83
                                        #   in Loop: Header=BB2_15 Depth=1
	incq	%rdi
	addl	%ebx, %esi
	cmpq	%rbx, %rdi
	jne	.LBB2_15
# %bb.18:                               # %._crit_edge86
	testl	%eax, %eax
	je	.LBB2_20
.LBB2_19:                               # %._crit_edge86.thread
	movss	72(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	divss	76(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	jmp	.LBB2_21
.LBB2_20:
	movl	$.Lstr.3, %edi
	callq	puts@PLT
.LBB2_21:
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipHostFree
	movq	24(%rsp), %rdi
	callq	hipHostFree
	movq	64(%rsp), %rdi
	callq	hipHostFree
	movq	56(%rsp), %rdi
	callq	hipHostFree
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22gpu_square_matrix_multPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22gpu_square_matrix_multPiS_S_i,@object # @_Z22gpu_square_matrix_multPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z22gpu_square_matrix_multPiS_S_i
	.p2align	3, 0x0
_Z22gpu_square_matrix_multPiS_S_i:
	.quad	_Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.size	_Z22gpu_square_matrix_multPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Enter square matrix size (nxn): "
	.size	.L.str, 33

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"GPU Time: %f ms.\n\n"
	.size	.L.str.4, 19

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"CPU Time: %f ms.\n\n"
	.size	.L.str.6, 19

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Results cross-verified as correct, speedup = %f\n"
	.size	.L.str.7, 49

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22gpu_square_matrix_multPiS_S_i"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Filling matrices A and B with random values..."
	.size	.Lstr, 47

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Running GPU Algorithm..."
	.size	.Lstr.1, 25

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Running CPU Algorithm..."
	.size	.Lstr.2, 25

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Incorrect results. "
	.size	.Lstr.3, 20

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"Exiting."
	.size	.Lstr.4, 9

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__gpu_square_matrix_multPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22gpu_square_matrix_multPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22gpu_square_matrix_multPiS_S_i ; -- Begin function _Z22gpu_square_matrix_multPiS_S_i
	.globl	_Z22gpu_square_matrix_multPiS_S_i
	.p2align	8
	.type	_Z22gpu_square_matrix_multPiS_S_i,@function
_Z22gpu_square_matrix_multPiS_S_i:      ; @_Z22gpu_square_matrix_multPiS_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s3, s[0:1], 0x20
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_bfe_u32 v6, v0, 10, 10
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v5, s15, 4, v6
	v_lshl_add_u32 v0, s14, 4, v4
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v1, 2, v4
	v_lshlrev_b32_e32 v7, 6, v6
	v_mad_u64_u32 v[2:3], null, v5, s2, v[4:5]
	s_mul_i32 s9, s2, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, 0x400, v1
	v_add_nc_u32_e32 v9, v7, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v10, v8, v7
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_lshl_b32 s10, s8, 4
	v_mov_b32_e32 v11, 0
	v_add_nc_u32_e32 v3, s10, v2
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s9, v3
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v11, v[3:4], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v12, s10, v6
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v11
	v_mad_u64_u32 v[3:4], null, v12, s2, v[0:1]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s9, v3
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_mov_b32_e32 v3, v8
	s_mov_b32 s10, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v4, s10, v7
	s_add_i32 s10, s10, 4
	ds_load_b32 v13, v3
	ds_load_b32 v4, v4
	v_add_nc_u32_e32 v3, 64, v3
	s_cmp_eq_u32 s10, 64
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[11:12], null, v13, v4, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v11
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_9:                                ; %Flow63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v5, v0
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_mad_u64_u32 v[2:3], null, v5, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22gpu_square_matrix_multPiS_S_i
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z22gpu_square_matrix_multPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22gpu_square_matrix_multPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22gpu_square_matrix_multPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
