
// compile with: nvcc -arch sm_60 -o reduction reduction.cu
// run: ./reduction

#include <stdio.h>
#include <stdlib.h>
#include "cuda.h"

// use this later to define number of threads in thread block
#define BSIZE 256

__global__ void partialReduction_v0(int N, 
				    float *c_a,
				    float *c_result){

  // shared memory array
  __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  if(n<N)
    a = c_a[n];
  
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}

__global__ void partialReduction_v1(const int N, 
				    const float * __restrict__ c_a,
				    float * __restrict__ c_result){
  
  // shared memory array
  __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  if(n<N)
    a = c_a[n];
  
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}

// use "warp synchronization"
__global__ void partialReduction_v2(const int N, 
				    const float * __restrict__ c_a,
				    float * __restrict__ c_result){
  
  // shared memory array
  __volatile__ __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  if(n<N)
    a = c_a[n];
  
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  //  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  //  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  //  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  //  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  //  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}

// issue more loads per thread, and use threads
__global__ void partialReduction(const int N, 
				 const float * __restrict__ c_a,
				 float * __restrict__ c_result){
  
  // shared memory array
  __volatile__ __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  while(n<N){
    a += c_a[n];
    n += blockDim.x*gridDim.x;
  }
    
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  //  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  //  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  //  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  //  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  //  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}


int main(int argc, char **argv){

  int N = atoi(argv[argc-1]);

  // host array
  float *h_a = (float*) malloc(N*sizeof(float));
  float *h_result = (float*) malloc(N*sizeof(float));

  int n;
  for(n=0;n<N;++n){
    h_a[n] = 1;
    h_result[n] = 0;
  }

  // allocate device array
  float *c_a, *c_result;

  cudaMalloc(&c_a, N*sizeof(float));
  cudaMalloc(&c_result, N*sizeof(float));

  // copy data from host to device
  cudaMemcpy(c_a, h_a, N*sizeof(float), cudaMemcpyHostToDevice);

  // must zero
  cudaMemcpy(c_result, h_result, N*sizeof(float), cudaMemcpyHostToDevice);

  // choose number of threads in thread-block
  dim3 B(BSIZE,1,1);

  // choose number of thread-blocks
  int Nblocks = (N+BSIZE-1)/BSIZE;

  int Nblocks1 = (Nblocks+11)/12;
  dim3 G1(Nblocks1,1,1);
  
  printf("Nblocks1 = %d\n", Nblocks1);

  // launch reduction kernel
  partialReduction <<< G1, B >>> (N, c_a, c_result);
  
  cudaMemcpy(h_result, c_result,  Nblocks1*sizeof(float), cudaMemcpyDeviceToHost);
  
  // print out partial sums
  float res = 0;
  for(n=0;n<Nblocks1;++n){
    printf("%f\n", h_result[n]);
    res += h_result[n];
  }

  printf("res = %f\n", res);
  
  return 0;
}

	.file	"tmpxft_0022c663_00000000-6_reduction.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z19partialReduction_v0iPfS_iPfS_
	.type	_Z42__device_stub__Z19partialReduction_v0iPfS_iPfS_, @function
_Z42__device_stub__Z19partialReduction_v0iPfS_iPfS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19partialReduction_v0iPfS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z42__device_stub__Z19partialReduction_v0iPfS_iPfS_, .-_Z42__device_stub__Z19partialReduction_v0iPfS_iPfS_
	.globl	_Z19partialReduction_v0iPfS_
	.type	_Z19partialReduction_v0iPfS_, @function
_Z19partialReduction_v0iPfS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z19partialReduction_v0iPfS_iPfS_
	.cfi_endproc
.LFE2053:
	.size	_Z19partialReduction_v0iPfS_, .-_Z19partialReduction_v0iPfS_
	.globl	_Z43__device_stub__Z19partialReduction_v1iPKfPfiPKfPf
	.type	_Z43__device_stub__Z19partialReduction_v1iPKfPfiPKfPf, @function
_Z43__device_stub__Z19partialReduction_v1iPKfPfiPKfPf:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 12(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19partialReduction_v1iPKfPf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z43__device_stub__Z19partialReduction_v1iPKfPfiPKfPf, .-_Z43__device_stub__Z19partialReduction_v1iPKfPfiPKfPf
	.globl	_Z19partialReduction_v1iPKfPf
	.type	_Z19partialReduction_v1iPKfPf, @function
_Z19partialReduction_v1iPKfPf:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19partialReduction_v1iPKfPfiPKfPf
	.cfi_endproc
.LFE2055:
	.size	_Z19partialReduction_v1iPKfPf, .-_Z19partialReduction_v1iPKfPf
	.globl	_Z43__device_stub__Z19partialReduction_v2iPKfPfiPKfPf
	.type	_Z43__device_stub__Z19partialReduction_v2iPKfPfiPKfPf, @function
_Z43__device_stub__Z19partialReduction_v2iPKfPfiPKfPf:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 12(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19partialReduction_v2iPKfPf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z43__device_stub__Z19partialReduction_v2iPKfPfiPKfPf, .-_Z43__device_stub__Z19partialReduction_v2iPKfPfiPKfPf
	.globl	_Z19partialReduction_v2iPKfPf
	.type	_Z19partialReduction_v2iPKfPf, @function
_Z19partialReduction_v2iPKfPf:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19partialReduction_v2iPKfPfiPKfPf
	.cfi_endproc
.LFE2057:
	.size	_Z19partialReduction_v2iPKfPf, .-_Z19partialReduction_v2iPKfPf
	.globl	_Z40__device_stub__Z16partialReductioniPKfPfiPKfPf
	.type	_Z40__device_stub__Z16partialReductioniPKfPfiPKfPf, @function
_Z40__device_stub__Z16partialReductioniPKfPfiPKfPf:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 12(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z16partialReductioniPKfPf(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L18:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z40__device_stub__Z16partialReductioniPKfPfiPKfPf, .-_Z40__device_stub__Z16partialReductioniPKfPfiPKfPf
	.globl	_Z16partialReductioniPKfPf
	.type	_Z16partialReductioniPKfPf, @function
_Z16partialReductioniPKfPf:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z16partialReductioniPKfPfiPKfPf
	.cfi_endproc
.LFE2059:
	.size	_Z16partialReductioniPKfPf, .-_Z16partialReductioniPKfPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"Nblocks1 = %d\n"
.LC3:
	.string	"%f\n"
.LC4:
	.string	"res = %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movslq	%edi, %rdi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	-8(%rsi,%rdi,8), %rdi
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	atoi@PLT
	movslq	%eax, %rbx
	movq	%rbx, %r12
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movss	.LC1(%rip), %xmm0
	movq	%rax, %rbp
	xorl	%eax, %eax
.L24:
	cmpl	%eax, %r12d
	jle	.L31
	movl	$0x00000000, 0(%rbp,%rax,4)
	movss	%xmm0, 0(%r13,%rax,4)
	incq	%rax
	jmp	.L24
.L31:
	movq	%rbx, %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$16777217, %eax
	movl	$256, %ecx
	leaq	.LC2(%rip), %rsi
	salq	$8, %rax
	movl	$2, %edi
	movl	$1, 40(%rsp)
	movq	%rax, 32(%rsp)
	leal	255(%r12), %eax
	cltd
	idivl	%ecx
	movl	$12, %ecx
	addl	$11, %eax
	cltd
	idivl	%ecx
	movl	%eax, 44(%rsp)
	movl	%eax, %ebx
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	%ebx, %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	movq	32(%rsp), %rdx
	movq	44(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%r12d, %edi
	call	_Z40__device_stub__Z16partialReductioniPKfPfiPKfPf
.L26:
	movq	24(%rsp), %rsi
	movslq	%ebx, %rdx
	movl	$2, %ecx
	movq	%rbp, %rdi
	salq	$2, %rdx
	xorl	%r12d, %r12d
	leaq	.LC3(%rip), %r13
	call	cudaMemcpy@PLT
	xorps	%xmm1, %xmm1
.L27:
	cmpl	%r12d, %ebx
	jle	.L32
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	%xmm1, 12(%rsp)
	cvtss2sd	0(%rbp,%r12,4), %xmm0
	call	__printf_chk@PLT
	movss	12(%rsp), %xmm1
	addss	0(%rbp,%r12,4), %xmm1
	incq	%r12
	jmp	.L27
.L32:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z16partialReductioniPKfPf"
.LC6:
	.string	"_Z19partialReduction_v2iPKfPf"
.LC7:
	.string	"_Z19partialReduction_v1iPKfPf"
.LC8:
	.string	"_Z19partialReduction_v0iPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16partialReductioniPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19partialReduction_v2iPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19partialReduction_v1iPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19partialReduction_v0iPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


// compile with: nvcc -arch sm_60 -o reduction reduction.cu
// run: ./reduction

#include <stdio.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"

// use this later to define number of threads in thread block
#define BSIZE 256

__global__ void partialReduction_v0(int N, 
				    float *c_a,
				    float *c_result){

  // shared memory array
  __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  if(n<N)
    a = c_a[n];
  
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}

__global__ void partialReduction_v1(const int N, 
				    const float * __restrict__ c_a,
				    float * __restrict__ c_result){
  
  // shared memory array
  __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  if(n<N)
    a = c_a[n];
  
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}

// use "warp synchronization"
__global__ void partialReduction_v2(const int N, 
				    const float * __restrict__ c_a,
				    float * __restrict__ c_result){
  
  // shared memory array
  __volatile__ __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  if(n<N)
    a = c_a[n];
  
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  //  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  //  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  //  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  //  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  //  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}

// issue more loads per thread, and use threads
__global__ void partialReduction(const int N, 
				 const float * __restrict__ c_a,
				 float * __restrict__ c_result){
  
  // shared memory array
  __volatile__ __shared__ float s_a[BSIZE];

  // find thread number in thread-block
  int t = threadIdx.x;
  
  // find block number
  int b = blockIdx.x;

  // choose an array index for this thread to read
  int n = t + b*blockDim.x;

  // check is this index in bounds
  float a = 0;
  while(n<N){
    a += c_a[n];
    n += blockDim.x*gridDim.x;
  }
    
  // store the entry in shared memory
  s_a[t] = a;

  // block until all threads have written to the shared memory
  __syncthreads();
  if(t<BSIZE/2) s_a[t] = s_a[t] + s_a[t+(BSIZE/2)];

  __syncthreads();
  if(t<BSIZE/4) s_a[t] = s_a[t] + s_a[t+(BSIZE/4)];

  __syncthreads();
  if(t<BSIZE/8) s_a[t] = s_a[t] + s_a[t+(BSIZE/8)];

  //  __syncthreads();
  if(t<BSIZE/16) s_a[t] = s_a[t] + s_a[t+(BSIZE/16)];

  //  __syncthreads();
  if(t<BSIZE/32) s_a[t] = s_a[t] + s_a[t+(BSIZE/32)];

  //  __syncthreads();
  if(t<BSIZE/64) s_a[t] = s_a[t] + s_a[t+(BSIZE/64)];

  //  __syncthreads();
  if(t<BSIZE/128) s_a[t] = s_a[t] + s_a[t+(BSIZE/128)];

  //  __syncthreads();
  if(t<BSIZE/256) s_a[t] = s_a[t] + s_a[t+(BSIZE/256)];

  if(t==0)
    c_result[b] = s_a[0];
}


int main(int argc, char **argv){

  int N = atoi(argv[argc-1]);

  // host array
  float *h_a = (float*) malloc(N*sizeof(float));
  float *h_result = (float*) malloc(N*sizeof(float));

  int n;
  for(n=0;n<N;++n){
    h_a[n] = 1;
    h_result[n] = 0;
  }

  // allocate device array
  float *c_a, *c_result;

  hipMalloc(&c_a, N*sizeof(float));
  hipMalloc(&c_result, N*sizeof(float));

  // copy data from host to device
  hipMemcpy(c_a, h_a, N*sizeof(float), hipMemcpyHostToDevice);

  // must zero
  hipMemcpy(c_result, h_result, N*sizeof(float), hipMemcpyHostToDevice);

  // choose number of threads in thread-block
  dim3 B(BSIZE,1,1);

  // choose number of thread-blocks
  int Nblocks = (N+BSIZE-1)/BSIZE;

  int Nblocks1 = (Nblocks+11)/12;
  dim3 G1(Nblocks1,1,1);
  
  printf("Nblocks1 = %d\n", Nblocks1);

  // launch reduction kernel
  partialReduction <<< G1, B >>> (N, c_a, c_result);
  
  hipMemcpy(h_result, c_result,  Nblocks1*sizeof(float), hipMemcpyDeviceToHost);
  
  // print out partial sums
  float res = 0;
  for(n=0;n<Nblocks1;++n){
    printf("%f\n", h_result[n]);
    res += h_result[n];
  }

  printf("res = %f\n", res);
  
  return 0;
}

	.text
	.file	"reduction.hip"
	.globl	_Z34__device_stub__partialReduction_v0iPfS_ # -- Begin function _Z34__device_stub__partialReduction_v0iPfS_
	.type	_Z34__device_stub__partialReduction_v0iPfS_,@function
_Z34__device_stub__partialReduction_v0iPfS_: # @_Z34__device_stub__partialReduction_v0iPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19partialReduction_v0iPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__partialReduction_v0iPfS_, .Lfunc_end0-_Z34__device_stub__partialReduction_v0iPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__partialReduction_v1iPKfPf # -- Begin function _Z34__device_stub__partialReduction_v1iPKfPf
	.type	_Z34__device_stub__partialReduction_v1iPKfPf,@function
_Z34__device_stub__partialReduction_v1iPKfPf: # @_Z34__device_stub__partialReduction_v1iPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19partialReduction_v1iPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__partialReduction_v1iPKfPf, .Lfunc_end1-_Z34__device_stub__partialReduction_v1iPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__partialReduction_v2iPKfPf # -- Begin function _Z34__device_stub__partialReduction_v2iPKfPf
	.type	_Z34__device_stub__partialReduction_v2iPKfPf,@function
_Z34__device_stub__partialReduction_v2iPKfPf: # @_Z34__device_stub__partialReduction_v2iPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19partialReduction_v2iPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z34__device_stub__partialReduction_v2iPKfPf, .Lfunc_end2-_Z34__device_stub__partialReduction_v2iPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__partialReductioniPKfPf # -- Begin function _Z31__device_stub__partialReductioniPKfPf
	.type	_Z31__device_stub__partialReductioniPKfPf,@function
_Z31__device_stub__partialReductioniPKfPf: # @_Z31__device_stub__partialReductioniPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16partialReductioniPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z31__device_stub__partialReductioniPKfPf, .Lfunc_end3-_Z31__device_stub__partialReductioniPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movslq	%edi, %rax
	movq	-8(%rsi,%rax,8), %rdi
	callq	atoi
	movl	%eax, %r14d
	movslq	%eax, %r15
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %rbx
	testl	%r14d, %r14d
	jle	.LBB4_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%r14d, %r13d
	leaq	(,%r13,4), %rdx
	xorl	%ebp, %ebp
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r12,%rbp,4)      # imm = 0x3F800000
	incq	%rbp
	cmpq	%rbp, %r13
	jne	.LBB4_2
.LBB4_3:                                # %._crit_edge
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	255(%r14), %eax
	leal	510(%r14), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$8, %ecx
	addl	$11, %ecx
	movslq	%ecx, %rax
	imulq	$715827883, %rax, %r15          # imm = 0x2AAAAAAB
	movq	%r15, %rax
	shrq	$63, %rax
	sarq	$33, %r15
	addl	%eax, %r15d
	movq	%r15, %r12
	btsq	$32, %r12
	movl	$.L.str, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_5
# %bb.4:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%r14d, %edi
	callq	_Z31__device_stub__partialReductioniPKfPf
.LBB4_5:
	movq	8(%rsp), %rsi
	movslq	%r15d, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%r14d, %r14d
	jle	.LBB4_6
# %bb.7:                                # %.lr.ph46.preheader
	cmpl	$2, %r15d
	movl	$1, %r14d
	cmovgel	%r15d, %r14d
	xorps	%xmm0, %xmm0
	xorl	%r15d, %r15d
.LBB4_8:                                # %.lr.ph46
                                        # =>This Inner Loop Header: Depth=1
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	(%rbx,%r15,4), %xmm0
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB4_8
# %bb.9:                                # %._crit_edge47.loopexit
	cvtss2sd	%xmm0, %xmm0
	jmp	.LBB4_10
.LBB4_6:
	xorps	%xmm0, %xmm0
.LBB4_10:                               # %._crit_edge47
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19partialReduction_v0iPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19partialReduction_v1iPKfPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19partialReduction_v2iPKfPf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16partialReductioniPKfPf, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19partialReduction_v0iPfS_,@object # @_Z19partialReduction_v0iPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z19partialReduction_v0iPfS_
	.p2align	3, 0x0
_Z19partialReduction_v0iPfS_:
	.quad	_Z34__device_stub__partialReduction_v0iPfS_
	.size	_Z19partialReduction_v0iPfS_, 8

	.type	_Z19partialReduction_v1iPKfPf,@object # @_Z19partialReduction_v1iPKfPf
	.globl	_Z19partialReduction_v1iPKfPf
	.p2align	3, 0x0
_Z19partialReduction_v1iPKfPf:
	.quad	_Z34__device_stub__partialReduction_v1iPKfPf
	.size	_Z19partialReduction_v1iPKfPf, 8

	.type	_Z19partialReduction_v2iPKfPf,@object # @_Z19partialReduction_v2iPKfPf
	.globl	_Z19partialReduction_v2iPKfPf
	.p2align	3, 0x0
_Z19partialReduction_v2iPKfPf:
	.quad	_Z34__device_stub__partialReduction_v2iPKfPf
	.size	_Z19partialReduction_v2iPKfPf, 8

	.type	_Z16partialReductioniPKfPf,@object # @_Z16partialReductioniPKfPf
	.globl	_Z16partialReductioniPKfPf
	.p2align	3, 0x0
_Z16partialReductioniPKfPf:
	.quad	_Z31__device_stub__partialReductioniPKfPf
	.size	_Z16partialReductioniPKfPf, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Nblocks1 = %d\n"
	.size	.L.str, 15

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%f\n"
	.size	.L.str.1, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"res = %f\n"
	.size	.L.str.2, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19partialReduction_v0iPfS_"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19partialReduction_v1iPKfPf"
	.size	.L__unnamed_2, 30

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z19partialReduction_v2iPKfPf"
	.size	.L__unnamed_3, 30

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z16partialReductioniPKfPf"
	.size	.L__unnamed_4, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__partialReduction_v0iPfS_
	.addrsig_sym _Z34__device_stub__partialReduction_v1iPKfPf
	.addrsig_sym _Z34__device_stub__partialReduction_v2iPKfPf
	.addrsig_sym _Z31__device_stub__partialReductioniPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19partialReduction_v0iPfS_
	.addrsig_sym _Z19partialReduction_v1iPKfPf
	.addrsig_sym _Z19partialReduction_v2iPKfPf
	.addrsig_sym _Z16partialReductioniPKfPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19partialReduction_v0iPfS_ ; -- Begin function _Z19partialReduction_v0iPfS_
	.globl	_Z19partialReduction_v0iPfS_
	.p2align	8
	.type	_Z19partialReduction_v0iPfS_,@function
_Z19partialReduction_v0iPfS_:           ; @_Z19partialReduction_v0iPfS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x8
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshlrev_b32_e32 v1, 2, v0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_4
; %bb.3:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_6
; %bb.5:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_8
; %bb.7:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:64
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB0_12
; %bb.11:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:32
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB0_14
; %bb.13:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB0_16
; %bb.15:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_18
; %bb.17:
	v_mov_b32_e32 v0, 0
	s_ashr_i32 s5, s4, 31
	ds_load_b32 v2, v1
	ds_load_b32 v3, v0 offset:4
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19partialReduction_v0iPfS_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19partialReduction_v0iPfS_, .Lfunc_end0-_Z19partialReduction_v0iPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 720
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19partialReduction_v1iPKfPf ; -- Begin function _Z19partialReduction_v1iPKfPf
	.globl	_Z19partialReduction_v1iPKfPf
	.p2align	8
	.type	_Z19partialReduction_v1iPKfPf,@function
_Z19partialReduction_v1iPKfPf:          ; @_Z19partialReduction_v1iPKfPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x0
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b64 s[4:5], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b32_e32 v1, 2, v0
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB1_4
; %bb.3:
	ds_load_2addr_stride64_b32 v[2:3], v1 offset1:2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB1_6
; %bb.5:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB1_8
; %bb.7:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB1_10
; %bb.9:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:64
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_10:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB1_12
; %bb.11:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:32
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_12:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB1_14
; %bb.13:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:16
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_14:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB1_16
; %bb.15:
	ds_load_b32 v2, v1
	ds_load_b32 v3, v1 offset:8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB1_16:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_18
; %bb.17:
	v_mov_b32_e32 v0, 0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_ashr_i32 s3, s2, 31
	ds_load_b32 v2, v1
	ds_load_b32 v3, v0 offset:4
	s_lshl_b64 s[2:3], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19partialReduction_v1iPKfPf
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19partialReduction_v1iPKfPf, .Lfunc_end1-_Z19partialReduction_v1iPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 728
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19partialReduction_v2iPKfPf ; -- Begin function _Z19partialReduction_v2iPKfPf
	.globl	_Z19partialReduction_v2iPKfPf
	.p2align	8
	.type	_Z19partialReduction_v2iPKfPf,@function
_Z19partialReduction_v2iPKfPf:          ; @_Z19partialReduction_v2iPKfPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[4:5], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b32_e32 v1, 2, v0
	s_mov_b64 s[4:5], src_shared_base
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cndmask_b32_e64 v2, 0, s5, vcc_lo
	s_waitcnt vmcnt(0)
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB2_4
; %bb.3:
	v_lshl_add_u32 v3, v0, 2, 0x200
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB2_6
; %bb.5:
	v_lshl_add_u32 v3, v0, 2, 0x100
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_6:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB2_8
; %bb.7:
	v_lshl_add_u32 v3, v0, 2, 0x80
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_8:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB2_10
; %bb.9:
	v_lshl_add_u32 v3, v0, 2, 64
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB2_12
; %bb.11:
	v_lshl_add_u32 v3, v0, 2, 32
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_12:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB2_14
; %bb.13:
	v_lshl_add_u32 v3, v0, 2, 16
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_14:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB2_16
; %bb.15:
	v_lshl_add_u32 v3, v0, 2, 8
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_16:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_18
; %bb.17:
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 4 :: v_dual_mov_b32 v4, s5
	s_load_b64 s[0:1], s[0:1], 0x10
	s_ashr_i32 s3, s2, 31
	flat_load_b32 v0, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	v_dual_add_f32 v0, v0, v3 :: v_dual_mov_b32 v3, 0
	flat_store_b32 v[1:2], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b32 v3, v0, s[0:1]
.LBB2_18:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19partialReduction_v2iPKfPf
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z19partialReduction_v2iPKfPf, .Lfunc_end2-_Z19partialReduction_v2iPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16partialReductioniPKfPf ; -- Begin function _Z16partialReductioniPKfPf
	.globl	_Z16partialReductioniPKfPf
	.p2align	8
	.type	_Z16partialReductioniPKfPf,@function
_Z16partialReductioniPKfPf:             ; @_Z16partialReductioniPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x10
	s_add_u32 s6, s0, 24
	s_mov_b32 s2, s15
	s_addc_u32 s7, s1, 0
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s8, 0xffff
	s_mov_b32 s8, exec_lo
	v_mad_u64_u32 v[1:2], null, s2, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB3_4
; %bb.1:                                ; %.lr.ph
	s_load_b32 s7, s[6:7], 0x0
	s_load_b64 s[0:1], s[0:1], 0x8
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s7, s9
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_nc_u32_e32 v1, s7, v1
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s3, v1
	global_load_b32 v2, v[4:5], off
	s_or_b32 s6, vcc_lo, s6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v2
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB3_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_4:                                ; %Flow51
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s8
	v_lshlrev_b32_e32 v1, 2, v0
	s_mov_b64 s[0:1], src_shared_base
	s_mov_b32 s0, exec_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB3_6
; %bb.5:
	v_lshl_add_u32 v3, v0, 2, 0x200
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s1, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB3_8
; %bb.7:
	v_lshl_add_u32 v3, v0, 2, 0x100
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB3_10
; %bb.9:
	v_lshl_add_u32 v3, v0, 2, 0x80
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB3_12
; %bb.11:
	v_lshl_add_u32 v3, v0, 2, 64
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB3_14
; %bb.13:
	v_lshl_add_u32 v3, v0, 2, 32
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB3_16
; %bb.15:
	v_lshl_add_u32 v3, v0, 2, 16
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_16:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB3_18
; %bb.17:
	v_lshl_add_u32 v3, v0, 2, 8
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v5, v3
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_18:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_20
; %bb.19:
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 4 :: v_dual_mov_b32 v4, s1
	s_ashr_i32 s3, s2, 31
	flat_load_b32 v0, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v0, v0, v3 :: v_dual_mov_b32 v3, 0
	flat_store_b32 v[1:2], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b32 v3, v0, s[0:1]
.LBB3_20:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16partialReductioniPKfPf
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z16partialReductioniPKfPf, .Lfunc_end3-_Z16partialReductioniPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1064
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
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        .value_kind:     hidden_block_count_z
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        .size:           2
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        .size:           2
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        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19partialReduction_v0iPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19partialReduction_v0iPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
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        .value_kind:     global_buffer
      - .actual_access:  write_only
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        .value_kind:     hidden_block_count_x
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        .value_kind:     hidden_global_offset_z
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        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19partialReduction_v1iPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19partialReduction_v1iPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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      - .actual_access:  read_only
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    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19partialReduction_v2iPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19partialReduction_v2iPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
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        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
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        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .value_kind:     hidden_group_size_x
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        .size:           2
        .value_kind:     hidden_group_size_y
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        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .value_kind:     hidden_remainder_z
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        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16partialReductioniPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16partialReductioniPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
