#include <stdio.h>
#include <cuda.h>

__global__ void calculate_g_image_gpu(float* in, float* out, int w, int h){
    int x = blockDim.x * blockIdx.x + threadIdx.x;
    int j = x % w;
    int i = x / w;
    if (1 <= i && i < h && 1 <= j && j < w) {
        float val = pow((in[(i+1)*w+j]-in[(i-1)*w+j])/2, 2) + pow((in[i*w+j+1]-in[i*w+j-1])/2, 2);
        float lambda = 3.5;
        out[i*w+j] = exp(-pow(val, 2)/2/pow(lambda, 2));
    }
}

__global__ void copy_gpu(float* src, float* dest, int w, int h) {
    int x = blockDim.x * blockIdx.x + threadIdx.x;
    int j = x % w;
    int i = x / w;
    dest[i*w+j] = src[i*w+j];
}

__device__ float arithmetic_mean_gpu(float n1, float n2) {
    return (n1+n2)/2.0;
}

__global__ void apply_stencil_gpu(float* in, float* out, float* g, int w, int h, float time_step) {
    int x = blockDim.x * blockIdx.x + threadIdx.x;
    int j = x % w;
    int i = x / w;
    if (1 <= i && i < h && 1 <= j && j < w) {
        float val = in[i*w+j]*(1-time_step*(arithmetic_mean_gpu(g[i*w+j], g[(i+1)*w+j]) +
	          		                        arithmetic_mean_gpu(g[i*w+j], g[i*w+j+1]) +
	          		                        arithmetic_mean_gpu(g[i*w+j], g[i*w+j-1])));
        val += in[(i+1)*w+j]*time_step*arithmetic_mean_gpu(g[i*w+j], g[(i+1)*w+j]);
        val += in[(i-1)*w+j]*time_step*arithmetic_mean_gpu(g[i*w+j], g[(i-1)*w+j]);
        val += in[i*w+j+1]*time_step*arithmetic_mean_gpu(g[i*w+j], g[i*w+j+1]);
        val += in[i*w+j-1]*time_step*arithmetic_mean_gpu(g[i*w+j], g[i*w+j-1]);
        val = (val < 0   ? 0   : val);
        val = (val > 255 ? 255 : val);
        out[i*w+j] = val;
    }
}


void gpu_func(float* in, float* out, float* g_img, int w, int h, int n_iters){

    int device = 0;
    int n = w*h;
   
    cudaSetDevice(device);
    float* in_dev;
    float* out_dev;
    float* g_dev;

    cudaMallocManaged(&in_dev, n * sizeof(float));
    cudaMallocManaged(&out_dev, n * sizeof(float));
    cudaMallocManaged(&g_dev, n * sizeof(float));
    for (int i = 0; i < n; i++) in_dev[i] = in[i];

    dim3 blockDim(16);

    dim3 gridDim((n % blockDim.x) ? n / blockDim.x : n / blockDim.x + 1);
    for (int t=0; t<n_iters; t++) {
        calculate_g_image_gpu<<<gridDim, blockDim>>>(in_dev, g_dev, w, h);
        apply_stencil_gpu<<<gridDim, blockDim>>>(in_dev, out_dev, g_dev, w, h, t);
        copy_gpu<<<gridDim, blockDim>>>(out_dev, in_dev, w, h);
    }
    cudaDeviceSynchronize(); 
    printf("Done executing CUDA kernel\n");
    for (int i = 0; i < n; i++) out[i] = out_dev[i];
    for (int i = 0; i < n; i++) g_img[i] = g_dev[i];
    
        
    cudaFree(in_dev);
    cudaFree(out_dev);
    cudaFree(g_dev);
}

	.file	"tmpxft_003b006f_00000000-6_main_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z19arithmetic_mean_gpuff
	.type	_Z19arithmetic_mean_gpuff, @function
_Z19arithmetic_mean_gpuff:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z19arithmetic_mean_gpuff, .-_Z19arithmetic_mean_gpuff
	.globl	_Z45__device_stub__Z21calculate_g_image_gpuPfS_iiPfS_ii
	.type	_Z45__device_stub__Z21calculate_g_image_gpuPfS_iiPfS_ii, @function
_Z45__device_stub__Z21calculate_g_image_gpuPfS_iiPfS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21calculate_g_image_gpuPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z45__device_stub__Z21calculate_g_image_gpuPfS_iiPfS_ii, .-_Z45__device_stub__Z21calculate_g_image_gpuPfS_iiPfS_ii
	.globl	_Z21calculate_g_image_gpuPfS_ii
	.type	_Z21calculate_g_image_gpuPfS_ii, @function
_Z21calculate_g_image_gpuPfS_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z21calculate_g_image_gpuPfS_iiPfS_ii
	.cfi_endproc
.LFE2054:
	.size	_Z21calculate_g_image_gpuPfS_ii, .-_Z21calculate_g_image_gpuPfS_ii
	.globl	_Z31__device_stub__Z8copy_gpuPfS_iiPfS_ii
	.type	_Z31__device_stub__Z8copy_gpuPfS_iiPfS_ii, @function
_Z31__device_stub__Z8copy_gpuPfS_iiPfS_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8copy_gpuPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z31__device_stub__Z8copy_gpuPfS_iiPfS_ii, .-_Z31__device_stub__Z8copy_gpuPfS_iiPfS_ii
	.globl	_Z8copy_gpuPfS_ii
	.type	_Z8copy_gpuPfS_ii, @function
_Z8copy_gpuPfS_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z8copy_gpuPfS_iiPfS_ii
	.cfi_endproc
.LFE2056:
	.size	_Z8copy_gpuPfS_ii, .-_Z8copy_gpuPfS_ii
	.globl	_Z44__device_stub__Z17apply_stencil_gpuPfS_S_iifPfS_S_iif
	.type	_Z44__device_stub__Z17apply_stencil_gpuPfS_S_iifPfS_S_iif, @function
_Z44__device_stub__Z17apply_stencil_gpuPfS_S_iifPfS_S_iif:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z17apply_stencil_gpuPfS_S_iif(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L15:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z44__device_stub__Z17apply_stencil_gpuPfS_S_iifPfS_S_iif, .-_Z44__device_stub__Z17apply_stencil_gpuPfS_S_iifPfS_S_iif
	.globl	_Z17apply_stencil_gpuPfS_S_iif
	.type	_Z17apply_stencil_gpuPfS_S_iif, @function
_Z17apply_stencil_gpuPfS_S_iif:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17apply_stencil_gpuPfS_S_iifPfS_S_iif
	.cfi_endproc
.LFE2058:
	.size	_Z17apply_stencil_gpuPfS_S_iif, .-_Z17apply_stencil_gpuPfS_S_iif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Done executing CUDA kernel\n"
	.text
	.globl	_Z8gpu_funcPfS_S_iii
	.type	_Z8gpu_funcPfS_S_iii, @function
_Z8gpu_funcPfS_S_iii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r9d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	xorl	%edi, %edi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	imull	%r8d, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdx, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	movslq	%ebx, %rax
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rsi
	movl	$1, %edx
	leaq	40(%rsp), %rdi
	call	cudaMallocManaged@PLT
	movq	24(%rsp), %rdx
	xorl	%eax, %eax
.L21:
	cmpl	%eax, %ebx
	jle	.L35
	movss	0(%r13,%rax,4), %xmm0
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	jmp	.L21
.L35:
	movabsq	$4294967297, %rdx
	movl	%ebx, %ecx
	movl	%ebx, %eax
	andl	$15, %ecx
	shrl	$4, %eax
	movq	%rdx, 52(%rsp)
	cmpl	$1, %ecx
	movq	%rdx, 64(%rsp)
	adcl	$0, %eax
	xorl	%r13d, %r13d
	movl	%eax, 60(%rsp)
.L24:
	cmpl	%r15d, %r13d
	jge	.L36
	movl	56(%rsp), %ecx
	movq	60(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16, 48(%rsp)
	movl	68(%rsp), %esi
	movq	48(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z45__device_stub__Z21calculate_g_image_gpuPfS_iiPfS_ii
.L25:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	cvtsi2ssl	%r13d, %xmm0
	movq	40(%rsp), %rdx
	movl	%r12d, %r8d
	movl	%ebp, %ecx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z44__device_stub__Z17apply_stencil_gpuPfS_S_iifPfS_S_iif
.L26:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z31__device_stub__Z8copy_gpuPfS_iiPfS_ii
.L27:
	incl	%r13d
	jmp	.L24
.L36:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	32(%rsp), %rdx
	xorl	%eax, %eax
.L29:
	cmpl	%eax, %ebx
	jle	.L37
	movss	(%rdx,%rax,4), %xmm0
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	jmp	.L29
.L37:
	movq	40(%rsp), %rdx
	xorl	%eax, %eax
.L31:
	cmpl	%eax, %ebx
	jle	.L38
	movss	(%rdx,%rax,4), %xmm0
	movq	8(%rsp), %rsi
	movss	%xmm0, (%rsi,%rax,4)
	incq	%rax
	jmp	.L31
.L38:
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z8gpu_funcPfS_S_iii, .-_Z8gpu_funcPfS_S_iii
	.section	.rodata.str1.1
.LC1:
	.string	"_Z17apply_stencil_gpuPfS_S_iif"
.LC2:
	.string	"_Z8copy_gpuPfS_ii"
.LC3:
	.string	"_Z21calculate_g_image_gpuPfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17apply_stencil_gpuPfS_S_iif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8copy_gpuPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21calculate_g_image_gpuPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

__global__ void calculate_g_image_gpu(float* in, float* out, int w, int h){
    int x = blockDim.x * blockIdx.x + threadIdx.x;
    int j = x % w;
    int i = x / w;
    if (1 <= i && i < h && 1 <= j && j < w) {
        float val = pow((in[(i+1)*w+j]-in[(i-1)*w+j])/2, 2) + pow((in[i*w+j+1]-in[i*w+j-1])/2, 2);
        float lambda = 3.5;
        out[i*w+j] = exp(-pow(val, 2)/2/pow(lambda, 2));
    }
}

__global__ void copy_gpu(float* src, float* dest, int w, int h) {
    int x = blockDim.x * blockIdx.x + threadIdx.x;
    int j = x % w;
    int i = x / w;
    dest[i*w+j] = src[i*w+j];
}

__device__ float arithmetic_mean_gpu(float n1, float n2) {
    return (n1+n2)/2.0;
}

__global__ void apply_stencil_gpu(float* in, float* out, float* g, int w, int h, float time_step) {
    int x = blockDim.x * blockIdx.x + threadIdx.x;
    int j = x % w;
    int i = x / w;
    if (1 <= i && i < h && 1 <= j && j < w) {
        float val = in[i*w+j]*(1-time_step*(arithmetic_mean_gpu(g[i*w+j], g[(i+1)*w+j]) +
	          		                        arithmetic_mean_gpu(g[i*w+j], g[i*w+j+1]) +
	          		                        arithmetic_mean_gpu(g[i*w+j], g[i*w+j-1])));
        val += in[(i+1)*w+j]*time_step*arithmetic_mean_gpu(g[i*w+j], g[(i+1)*w+j]);
        val += in[(i-1)*w+j]*time_step*arithmetic_mean_gpu(g[i*w+j], g[(i-1)*w+j]);
        val += in[i*w+j+1]*time_step*arithmetic_mean_gpu(g[i*w+j], g[i*w+j+1]);
        val += in[i*w+j-1]*time_step*arithmetic_mean_gpu(g[i*w+j], g[i*w+j-1]);
        val = (val < 0   ? 0   : val);
        val = (val > 255 ? 255 : val);
        out[i*w+j] = val;
    }
}


void gpu_func(float* in, float* out, float* g_img, int w, int h, int n_iters){

    int device = 0;
    int n = w*h;
   
    hipSetDevice(device);
    float* in_dev;
    float* out_dev;
    float* g_dev;

    hipMallocManaged(&in_dev, n * sizeof(float));
    hipMallocManaged(&out_dev, n * sizeof(float));
    hipMallocManaged(&g_dev, n * sizeof(float));
    for (int i = 0; i < n; i++) in_dev[i] = in[i];

    dim3 blockDim(16);

    dim3 gridDim((n % blockDim.x) ? n / blockDim.x : n / blockDim.x + 1);
    for (int t=0; t<n_iters; t++) {
        calculate_g_image_gpu<<<gridDim, blockDim>>>(in_dev, g_dev, w, h);
        apply_stencil_gpu<<<gridDim, blockDim>>>(in_dev, out_dev, g_dev, w, h, t);
        copy_gpu<<<gridDim, blockDim>>>(out_dev, in_dev, w, h);
    }
    hipDeviceSynchronize(); 
    printf("Done executing CUDA kernel\n");
    for (int i = 0; i < n; i++) out[i] = out_dev[i];
    for (int i = 0; i < n; i++) g_img[i] = g_dev[i];
    
        
    hipFree(in_dev);
    hipFree(out_dev);
    hipFree(g_dev);
}

	.text
	.file	"main_cuda.hip"
	.globl	_Z36__device_stub__calculate_g_image_gpuPfS_ii # -- Begin function _Z36__device_stub__calculate_g_image_gpuPfS_ii
	.type	_Z36__device_stub__calculate_g_image_gpuPfS_ii,@function
_Z36__device_stub__calculate_g_image_gpuPfS_ii: # @_Z36__device_stub__calculate_g_image_gpuPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21calculate_g_image_gpuPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__calculate_g_image_gpuPfS_ii, .Lfunc_end0-_Z36__device_stub__calculate_g_image_gpuPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__copy_gpuPfS_ii # -- Begin function _Z23__device_stub__copy_gpuPfS_ii
	.type	_Z23__device_stub__copy_gpuPfS_ii,@function
_Z23__device_stub__copy_gpuPfS_ii:      # @_Z23__device_stub__copy_gpuPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8copy_gpuPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__copy_gpuPfS_ii, .Lfunc_end1-_Z23__device_stub__copy_gpuPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__apply_stencil_gpuPfS_S_iif # -- Begin function _Z32__device_stub__apply_stencil_gpuPfS_S_iif
	.type	_Z32__device_stub__apply_stencil_gpuPfS_S_iif,@function
_Z32__device_stub__apply_stencil_gpuPfS_S_iif: # @_Z32__device_stub__apply_stencil_gpuPfS_S_iif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17apply_stencil_gpuPfS_S_iif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__apply_stencil_gpuPfS_S_iif, .Lfunc_end2-_Z32__device_stub__apply_stencil_gpuPfS_S_iif
	.cfi_endproc
                                        # -- End function
	.globl	_Z8gpu_funcPfS_S_iii            # -- Begin function _Z8gpu_funcPfS_S_iii
	.type	_Z8gpu_funcPfS_S_iii,@function
_Z8gpu_funcPfS_S_iii:                   # @_Z8gpu_funcPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, 12(%rsp)                  # 4-byte Spill
	movl	%r8d, %r15d
	movl	%ecx, %r12d
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbx
	movl	%r8d, %r14d
	imull	%ecx, %r14d
	xorl	%edi, %edi
	callq	hipSetDevice
	movslq	%r14d, %rbp
	leaq	(,%rbp,4), %r13
	movq	%rsp, %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	%r14d, %edx
	movl	%r14d, %r14d
	testl	%ebp, %ebp
	jle	.LBB3_3
# %bb.1:                                # %.lr.ph
	movq	(%rsp), %rax
	xorl	%ecx, %ecx
.LBB3_2:                                # =>This Inner Loop Header: Depth=1
	movss	(%rbx,%rcx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rax,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %r14
	jne	.LBB3_2
.LBB3_3:                                # %._crit_edge
	movl	%edx, %ecx
	andl	$15, %ecx
	movl	%edx, 36(%rsp)                  # 4-byte Spill
	movl	%edx, %eax
	shrl	$4, %eax
	cmpl	$1, %ecx
	adcl	$0, %eax
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	jle	.LBB3_12
# %bb.4:                                # %.lr.ph78.preheader
	movabsq	$4294967312, %r13               # imm = 0x100000010
	leaq	(%rax,%r13), %rbx
	addq	$-16, %rbx
	xorl	%ebp, %ebp
.LBB3_5:                                # %.lr.ph78
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_7
# %bb.6:                                #   in Loop: Header=BB3_5 Depth=1
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	callq	_Z36__device_stub__calculate_g_image_gpuPfS_ii
.LBB3_7:                                #   in Loop: Header=BB3_5 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.8:                                #   in Loop: Header=BB3_5 Depth=1
	movq	(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebp, %xmm0
	movl	%r12d, %ecx
	movl	%r15d, %r8d
	callq	_Z32__device_stub__apply_stencil_gpuPfS_S_iif
.LBB3_9:                                #   in Loop: Header=BB3_5 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_11
# %bb.10:                               #   in Loop: Header=BB3_5 Depth=1
	movq	24(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	callq	_Z23__device_stub__copy_gpuPfS_ii
.LBB3_11:                               #   in Loop: Header=BB3_5 Depth=1
	incl	%ebp
	cmpl	%ebp, 12(%rsp)                  # 4-byte Folded Reload
	jne	.LBB3_5
.LBB3_12:                               # %._crit_edge79
	callq	hipDeviceSynchronize
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	36(%rsp), %edi                  # 4-byte Reload
	testl	%edi, %edi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	jle	.LBB3_18
# %bb.13:                               # %.lr.ph82
	movq	24(%rsp), %rax
	xorl	%ecx, %ecx
	movq	40(%rsp), %rsi                  # 8-byte Reload
.LBB3_14:                               # =>This Inner Loop Header: Depth=1
	movss	(%rax,%rcx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rsi,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %r14
	jne	.LBB3_14
# %bb.15:                               # %.preheader
	testl	%edi, %edi
	jle	.LBB3_18
# %bb.16:                               # %.lr.ph84
	movq	16(%rsp), %rax
	xorl	%ecx, %ecx
.LBB3_17:                               # =>This Inner Loop Header: Depth=1
	movss	(%rax,%rcx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rdx,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %r14
	jne	.LBB3_17
.LBB3_18:                               # %._crit_edge85
	movq	(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z8gpu_funcPfS_S_iii, .Lfunc_end3-_Z8gpu_funcPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21calculate_g_image_gpuPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8copy_gpuPfS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17apply_stencil_gpuPfS_S_iif, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21calculate_g_image_gpuPfS_ii,@object # @_Z21calculate_g_image_gpuPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z21calculate_g_image_gpuPfS_ii
	.p2align	3, 0x0
_Z21calculate_g_image_gpuPfS_ii:
	.quad	_Z36__device_stub__calculate_g_image_gpuPfS_ii
	.size	_Z21calculate_g_image_gpuPfS_ii, 8

	.type	_Z8copy_gpuPfS_ii,@object       # @_Z8copy_gpuPfS_ii
	.globl	_Z8copy_gpuPfS_ii
	.p2align	3, 0x0
_Z8copy_gpuPfS_ii:
	.quad	_Z23__device_stub__copy_gpuPfS_ii
	.size	_Z8copy_gpuPfS_ii, 8

	.type	_Z17apply_stencil_gpuPfS_S_iif,@object # @_Z17apply_stencil_gpuPfS_S_iif
	.globl	_Z17apply_stencil_gpuPfS_S_iif
	.p2align	3, 0x0
_Z17apply_stencil_gpuPfS_S_iif:
	.quad	_Z32__device_stub__apply_stencil_gpuPfS_S_iif
	.size	_Z17apply_stencil_gpuPfS_S_iif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21calculate_g_image_gpuPfS_ii"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8copy_gpuPfS_ii"
	.size	.L__unnamed_2, 18

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z17apply_stencil_gpuPfS_S_iif"
	.size	.L__unnamed_3, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Done executing CUDA kernel"
	.size	.Lstr, 27

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__calculate_g_image_gpuPfS_ii
	.addrsig_sym _Z23__device_stub__copy_gpuPfS_ii
	.addrsig_sym _Z32__device_stub__apply_stencil_gpuPfS_S_iif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21calculate_g_image_gpuPfS_ii
	.addrsig_sym _Z8copy_gpuPfS_ii
	.addrsig_sym _Z17apply_stencil_gpuPfS_S_iif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21calculate_g_image_gpuPfS_ii ; -- Begin function _Z21calculate_g_image_gpuPfS_ii
	.globl	_Z21calculate_g_image_gpuPfS_ii
	.p2align	8
	.type	_Z21calculate_g_image_gpuPfS_ii,@function
_Z21calculate_g_image_gpuPfS_ii:        ; @_Z21calculate_g_image_gpuPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s4, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s6, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s3
	v_cvt_f32_u32_e32 v1, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s6
	s_cmp_gt_i32 s4, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, s2, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v3, v0
	v_add_nc_u32_e32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v2
	v_add_nc_u32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s6, v3
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v4, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v3, v4, s4
	v_cmp_gt_i32_e64 s2, s5, v4
	s_cselect_b32 s5, -1, 0
	v_cmp_lt_i32_e64 s3, 0, v4
	v_sub_nc_u32_e32 v0, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	s_and_b32 s5, vcc_lo, s5
	s_and_b32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_add_nc_u32_e32 v3, s4, v3
	s_load_b128 s[0:3], s[0:1], 0x0
	s_lshl_b32 s4, s4, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_subrev_nc_u32_e32 v4, s4, v3
	v_add_nc_u32_e32 v3, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v4, v0
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	s_clause 0x3
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	global_load_b32 v4, v[6:7], off offset:4
	global_load_b32 v5, v[6:7], off offset:-4
	s_mov_b32 s1, 0x3e76c4e1
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v2, v2, v3 :: v_dual_sub_f32 v3, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0.5, v2
	v_frexp_mant_f32_e64 v4, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_ldexp_f32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v6, 1.0, v4 :: v_dual_mul_f32 v3, 0.5, v3
	v_add_f32_e32 v10, -1.0, v4
	v_rcp_f32_e32 v8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v5, |v3|
	v_add_f32_e32 v14, -1.0, v6
	v_frexp_exp_i32_f32_e32 v19, v3
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v14
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v12, v10, v8
	v_cndmask_b32_e64 v7, 0, 1, s0
	v_ldexp_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, 1.0, v5
	v_dual_add_f32 v11, -1.0, v5 :: v_dual_add_f32 v16, -1.0, v7
	v_rcp_f32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v13, v11, v9
	v_mul_f32_e32 v17, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v13, v7, -v17
	v_fmac_f32_e32 v7, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v17, v7
	v_dual_mul_f32 v15, v6, v12 :: v_dual_sub_f32 v16, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v12, v6, -v15
	v_fmac_f32_e32 v6, v12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v15, v6
	v_sub_f32_e32 v14, v10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v14 :: v_dual_sub_f32 v15, v4, v15
	v_dual_sub_f32 v4, v10, v4 :: v_dual_sub_f32 v17, v5, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v15, v6 :: v_dual_sub_f32 v7, v17, v7
	v_add_f32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v14, v4
	v_mul_f32_e32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v12, v4
	v_dual_sub_f32 v11, v11, v16 :: v_dual_mul_f32 v10, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v11, v5 :: v_dual_sub_f32 v8, v6, v12
	v_dual_add_f32 v5, v7, v5 :: v_dual_sub_f32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v16, v5
	v_mul_f32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v13, v5
	v_sub_f32_e32 v9, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v8, v7, v7 :: v_dual_sub_f32 v5, v5, v9
	v_fma_f32 v9, v6, v6, -v10
	v_fma_f32 v12, v7, v7, -v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v5, v5
	v_dual_add_f32 v11, v4, v4 :: v_dual_fmac_f32 v12, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, v6, v11
	v_add_f32_e32 v13, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v10, v9 :: v_dual_sub_f32 v8, v13, v8
	v_fmaak_f32 v14, s1, v11, 0x3e91f4c4
	v_sub_f32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v12, v8
	v_fmaak_f32 v14, v11, v14, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v9, v10
	v_dual_mul_f32 v16, v11, v14 :: v_dual_fmaak_f32 v15, s1, v13, 0x3e91f4c4
	v_mul_f32_e32 v20, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v11, v14, -v16
	v_fma_f32 v24, v13, v7, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v9, v14
	v_fmaak_f32 v15, v13, v15, 0x3ecccdef
	v_frexp_exp_i32_f32_e32 v14, v2
	v_dual_add_f32 v18, v16, v10 :: v_dual_mul_f32 v17, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v18, v16 :: v_dual_add_f32 v23, 0x3f2aaaaa, v18
	v_fma_f32 v12, v13, v15, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v12, v8, v15
	v_mul_f32_e32 v15, v6, v11
	v_sub_f32_e32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v16, 0xbf2aaaaa, v23 :: v_dual_add_f32 v21, v17, v12
	v_fma_f32 v22, v11, v6, -v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v18, v16 :: v_dual_sub_f32 v17, v21, v17
	v_dual_fmac_f32 v22, v11, v4 :: v_dual_add_f32 v25, 0x3f2aaaaa, v21
	v_ldexp_f32 v4, v4, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v11, v12, v17 :: v_dual_add_f32 v10, 0x31739010, v10
	v_fmac_f32_e32 v22, v9, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v12, 0xbf2aaaaa, v25
	v_ldexp_f32 v6, v6, 1
	v_dual_add_f32 v9, 0x31739010, v11 :: v_dual_add_f32 v10, v10, v16
	v_fmac_f32_e32 v24, v13, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v21, v12
	v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v14, vcc_lo
	v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v19, s0
	v_fmac_f32_e32 v24, v8, v7
	v_ldexp_f32 v7, v7, 1
	v_ldexp_f32 v5, v5, 1
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v20, v24
	v_dual_add_f32 v8, v9, v11 :: v_dual_add_f32 v11, v23, v10
	v_sub_f32_e32 v17, v23, v11
	v_add_f32_e32 v9, v15, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v9, v15
	v_dual_add_f32 v14, v25, v8 :: v_dual_sub_f32 v15, v22, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v25, v14
	v_dual_mul_f32 v21, v16, v14 :: v_dual_add_f32 v10, v10, v17
	v_add_f32_e32 v8, v8, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v16, v14, -v21
	v_dual_mul_f32 v18, v9, v11 :: v_dual_fmac_f32 v19, v16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v17, v9, v11, -v18
	v_sub_f32_e32 v20, v16, v20
	v_cvt_f32_i32_e32 v8, v13
	v_dual_fmac_f32 v17, v9, v10 :: v_dual_sub_f32 v10, v24, v20
	v_cvt_f32_i32_e32 v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v12, 0x3f317218, v8 :: v_dual_fmac_f32 v17, v15, v11
	v_fmac_f32_e32 v19, v10, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3f317218, v9
	v_add_f32_e32 v13, v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, 0x3f317218, v9, -v11
	v_sub_f32_e32 v20, v13, v21
	v_add_f32_e32 v10, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v10, v18
	v_add_f32_e32 v18, v7, v13
	v_sub_f32_e32 v16, v17, v16
	v_sub_f32_e32 v17, v19, v20
	v_add_f32_e32 v15, v6, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v7, v18, v7 :: v_dual_fmac_f32 v14, 0xb102e308, v9
	v_dual_add_f32 v5, v5, v17 :: v_dual_sub_f32 v6, v15, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v13, v7 :: v_dual_sub_f32 v6, v10, v6
	v_add_f32_e32 v5, v5, v7
	v_fma_f32 v10, 0x3f317218, v8, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v18, v5 :: v_dual_add_f32 v4, v4, v16
	v_sub_f32_e32 v18, v9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v6
	v_sub_f32_e32 v5, v5, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v15, v4
	v_add_f32_e32 v6, v11, v14
	v_sub_f32_e32 v11, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v14, v11
	v_dual_add_f32 v13, v6, v7 :: v_dual_fmac_f32 v10, 0xb102e308, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v13, v6
	v_add_f32_e32 v8, v12, v10
	v_sub_f32_e32 v14, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v7, v7, v17
	v_add_f32_e32 v16, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v16, v8
	v_sub_f32_e32 v12, v8, v12
	v_dual_sub_f32 v4, v4, v14 :: v_dual_sub_f32 v9, v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v12
	v_sub_f32_e32 v12, v13, v17
	v_sub_f32_e32 v6, v6, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v11, v4
	v_add_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v12, v6
	v_dual_sub_f32 v14, v16, v15 :: v_dual_add_f32 v15, v13, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v14
	v_dual_add_f32 v8, v9, v8 :: v_dual_sub_f32 v9, v12, v11
	v_add_f32_e32 v7, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v7, v10
	v_add_f32_e32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v14
	v_sub_f32_e32 v5, v5, v14
	v_sub_f32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v12, v12, v9
	v_dual_sub_f32 v11, v11, v12 :: v_dual_sub_f32 v4, v4, v9
	v_add_f32_e32 v9, v16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v9, v16
	v_dual_sub_f32 v12, v15, v13 :: v_dual_sub_f32 v7, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v6, v6, v12
	v_add_f32_e32 v7, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v7, v9 :: v_dual_add_f32 v4, v4, v11
	v_dual_sub_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v15, v4
	v_dual_sub_f32 v8, v6, v15 :: v_dual_mul_f32 v11, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v8
	v_add_f32_e32 v8, v7, v7
	v_dual_mul_f32 v12, 0, v7 :: v_dual_fmac_f32 v11, 2.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v7, 2.0, -v8
	v_fmac_f32_e32 v12, 2.0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v12
	v_dual_add_f32 v10, v6, v6 :: v_dual_add_f32 v7, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v6, 2.0, -v10
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_add_f32_e32 v5, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v10, v5
	v_cndmask_b32_e32 v9, v6, v10, vcc_lo
	v_sub_f32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v5, v5, v6
	v_cmp_class_f32_e64 vcc_lo, v8, 0x204
	v_cndmask_b32_e32 v11, v7, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
	v_sub_f32_e32 v7, v7, v8
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
	v_sub_f32_e32 v15, v11, v13
	v_dual_cndmask_b32 v5, 0, v5 :: v_dual_sub_f32 v14, v9, v12
	v_sub_f32_e32 v4, v4, v7
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v11|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v17, 0x3fb8aa3b, v15
	v_dual_add_f32 v5, v12, v5 :: v_dual_mul_f32 v16, 0x3fb8aa3b, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_fma_f32 v20, 0x3fb8aa3b, v15, -v17
	v_rndne_f32_e32 v21, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v18, 0x3fb8aa3b, v14, -v16
	v_rndne_f32_e32 v19, v16
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	v_dual_fmac_f32 v20, 0x32a5705f, v15 :: v_dual_sub_f32 v17, v17, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v18, 0x32a5705f, v14
	v_sub_f32_e32 v16, v16, v19
	v_cvt_i32_f32_e32 v6, v19
	v_cvt_i32_f32_e32 v7, v21
	v_add_f32_e32 v17, v17, v20
	v_add_f32_e32 v4, v13, v4
	v_add_f32_e32 v16, v16, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v8, v17
	v_exp_f32_e32 v10, v16
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v8, v7
	v_ldexp_f32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	v_fma_f32 v5, v6, v5, v6
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v4, v7, v4, v7
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v3|
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, 0x7f800000, |v4|, s0
	v_cndmask_b32_e32 v2, 0, v5, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v3
	v_frexp_mant_f32_e32 v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	v_ldexp_f32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, 1.0, v3
	v_add_f32_e32 v6, -1.0, v3
	v_rcp_f32_e32 v5, v4
	v_add_f32_e32 v8, -1.0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, v6, v5
	v_mul_f32_e32 v9, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v7, v4, -v9
	v_fmac_f32_e32 v4, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v9, v4
	v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v8
	v_dual_sub_f32 v4, v9, v4 :: v_dual_sub_f32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v4, v3
	v_add_f32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v5, v3
	v_add_f32_e32 v4, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v4, v7
	v_dual_mul_f32 v6, v4, v4 :: v_dual_sub_f32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v4, v4, -v6
	v_add_f32_e32 v7, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v4, v7
	v_add_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v7, v6 :: v_dual_mul_f32 v11, v4, v7
	v_sub_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v7, v4, -v11
	v_fmac_f32_e32 v12, v7, v3
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v5, v4
	v_fmaak_f32 v8, s1, v7, 0x3e91f4c4
	v_fmaak_f32 v8, v7, v8, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v7, v8
	v_fma_f32 v6, v7, v8, -v9
	v_add_f32_e32 v7, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v5, v8
	v_add_f32_e32 v8, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v8, v9 :: v_dual_add_f32 v10, 0x3f2aaaaa, v8
	v_dual_sub_f32 v6, v6, v9 :: v_dual_add_f32 v9, 0xbf2aaaaa, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, 0x31739010, v6
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v8
	v_add_f32_e32 v5, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v10, v5
	v_mul_f32_e32 v9, v7, v5
	v_sub_f32_e32 v10, v7, v11
	v_add_f32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v8, v7, v5, -v9
	v_sub_f32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v7, v6
	v_frexp_exp_i32_f32_e32 v6, v2
	v_fmac_f32_e32 v8, v10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	v_add_f32_e32 v6, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v5, v5
	v_sub_f32_e32 v9, v6, v9
	v_ldexp_f32 v4, v4, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, 0x3f317218, v5
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, v4, v6
	v_fma_f32 v9, 0x3f317218, v5, -v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v8
	v_dual_sub_f32 v4, v7, v4 :: v_dual_fmac_f32 v9, 0xb102e308, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v6, v4
	v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v7, v3 :: v_dual_sub_f32 v10, v4, v10
	v_dual_add_f32 v6, v4, v5 :: v_dual_sub_f32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v9, v10 :: v_dual_sub_f32 v8, v6, v4
	v_sub_f32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v6, v8
	v_sub_f32_e32 v5, v5, v8
	v_add_f32_e32 v7, v9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v11
	v_dual_add_f32 v4, v5, v4 :: v_dual_sub_f32 v5, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v7, v4
	v_sub_f32_e32 v7, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v3, v5 :: v_dual_add_f32 v8, v6, v4
	v_dual_sub_f32 v5, v9, v7 :: v_dual_sub_f32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v4, v4, v6
	v_add_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v8, v3
	v_sub_f32_e32 v5, v4, v8
	v_add_f32_e32 v6, v4, v4
	v_mul_f32_e32 v7, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v3, v5
	v_fma_f32 v4, v4, 2.0, -v6
	v_cmp_class_f32_e64 vcc_lo, v6, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, 2.0, v3
	v_add_f32_e32 v3, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v6, v3
	v_cndmask_b32_e32 v5, v4, v6, vcc_lo
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v5
	v_sub_f32_e32 v3, v3, v4
	v_cndmask_b32_e64 v7, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v5|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v5, v7
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v9, 0x3fb8aa3b, v8
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v8
	v_add_f32_e32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v10, 0x3fb8aa3b, v8, -v9
	v_rndne_f32_e32 v11, v9
	v_dual_fmac_f32 v10, 0x32a5705f, v8 :: v_dual_sub_f32 v9, v9, v11
	v_cvt_i32_f32_e32 v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v10
	v_exp_f32_e32 v9, v9
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v8
	v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v3, v4, v3, v4
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v4
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e64 v3, |v3|, -0.5
	v_div_scale_f32 v4, null, 0x41440000, 0x41440000, v3
	v_div_scale_f32 v7, vcc_lo, v3, 0x41440000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v5
	v_fma_f32 v8, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v5
	v_fma_f32 v4, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v4, v4, v5, v6
	v_cmp_neq_f32_e32 vcc_lo, 0x7f800000, v2
	v_div_fixup_f32 v3, v4, 0x41440000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0xff800000, v3, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e32 v2, 0x80000000, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x3fb8aa3b, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	v_fma_f32 v4, 0x3fb8aa3b, v2, -v3
	v_rndne_f32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v4, 0x32a5705f, v2 :: v_dual_sub_f32 v3, v3, v5
	v_add_f32_e32 v3, v3, v4
	v_cvt_i32_f32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v3, v3, v4
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21calculate_g_image_gpuPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21calculate_g_image_gpuPfS_ii, .Lfunc_end0-_Z21calculate_g_image_gpuPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3408
; NumSgprs: 18
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8copy_gpuPfS_ii       ; -- Begin function _Z8copy_gpuPfS_ii
	.globl	_Z8copy_gpuPfS_ii
	.p2align	8
	.type	_Z8copy_gpuPfS_ii,@function
_Z8copy_gpuPfS_ii:                      ; @_Z8copy_gpuPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8copy_gpuPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8copy_gpuPfS_ii, .Lfunc_end1-_Z8copy_gpuPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 120
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17apply_stencil_gpuPfS_S_iif ; -- Begin function _Z17apply_stencil_gpuPfS_S_iif
	.globl	_Z17apply_stencil_gpuPfS_S_iif
	.p2align	8
	.type	_Z17apply_stencil_gpuPfS_S_iif,@function
_Z17apply_stencil_gpuPfS_S_iif:         ; @_Z17apply_stencil_gpuPfS_S_iif
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s4, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s7, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s7, s3
	v_cvt_f32_u32_e32 v1, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s7
	s_cmp_gt_i32 s4, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, s2, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v3, v0
	v_add_nc_u32_e32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v2
	v_add_nc_u32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s7, v3
	v_cmp_le_u32_e32 vcc_lo, s7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s7, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v4, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v3, v4, s4
	v_cmp_gt_i32_e64 s2, s5, v4
	s_cselect_b32 s5, -1, 0
	v_cmp_lt_i32_e64 s3, 0, v4
	v_sub_nc_u32_e32 v0, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	s_and_b32 s5, vcc_lo, s5
	s_and_b32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[8:9], s[0:1], 0x10
	v_add_nc_u32_e32 v4, s4, v3
	s_lshl_b32 s2, s4, 1
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s2, v4
	v_add_nc_u32_e32 v3, v4, v0
	s_load_b128 s[0:3], s[0:1], 0x0
	v_add_nc_u32_e32 v8, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v9, 31, v8
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	global_load_b96 v[0:2], v[0:1], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v1, v2
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v10, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v12, v[10:11], off
	v_add_co_u32 v10, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v7, vcc_lo
	global_load_b32 v13, v[3:4], off
	v_add_co_u32 v3, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v14, v[3:4], off
	s_clause 0x1
	global_load_b96 v[3:5], v[10:11], off offset:-4
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(4)
	v_dual_add_f32 v9, v1, v12 :: v_dual_mul_f32 v2, 0.5, v2
	s_waitcnt vmcnt(3)
	v_mul_f32_e32 v11, s6, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v10, 0.5, v9, v2
	v_mul_f32_e32 v9, 0.5, v9
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v1, v1, v14
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v5, s6, v5 :: v_dual_mul_f32 v8, s6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v1, 0.5, v1 :: v_dual_fmac_f32 v10, 0.5, v0
	v_mul_f32_e32 v0, 0.5, v0
	v_fma_f32 v10, -v10, s6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v4, v10
	v_fmac_f32_e32 v4, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v4, v8, v1 :: v_dual_mul_f32 v1, s6, v3
	v_fmac_f32_e32 v4, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v0, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v0, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v0
	v_cndmask_b32_e32 v2, 0x437f0000, v0, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17apply_stencil_gpuPfS_S_iif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z17apply_stencil_gpuPfS_S_iif, .Lfunc_end2-_Z17apply_stencil_gpuPfS_S_iif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 688
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21calculate_g_image_gpuPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21calculate_g_image_gpuPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8copy_gpuPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8copy_gpuPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17apply_stencil_gpuPfS_S_iif
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17apply_stencil_gpuPfS_S_iif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
