#include <stdio.h>

#define BLOCKDIM 512
#define RSIZE 10
#define JFACTOR 1


__device__ double NonOrtho_dist(double a0, double a1, double a2,
				double b0, double b1, double b2,
				double *ucell);

//------------------------------------------------------------------------------------------------------------------------------------------------
//try thread coarsening 

__global__ void Action_noImage_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, int Nmols , int NAtoms, int active_size)
{

	//__shared__ double dist_array[BLOCKDIM];



	//int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	//int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	int mol = blockIdx.x*BLOCKDIM + threadIdx.x;

	//advantage of register
	double a0 = maskCenter[0];
	double a1 = maskCenter[1];
	double a2 = maskCenter[2];



	if ( mol < Nmols )
	{



		int sIndex =  mol*NAtoms*3;
		double min_val  = maxD;
		for(int offset  = 0 ; offset < NAtoms*3 ; offset+=3 )
		{

			//double x = a0 - SolventMols_[sIndex++];
			//double y = a1 - SolventMols_[sIndex++];
			//double z = a2 - SolventMols_[sIndex++];

			double x = a0 - SolventMols_[sIndex+ offset + 0 ];
			double y = a1 - SolventMols_[sIndex+offset + 1];
			double z = a2 - SolventMols_[sIndex+offset + 2];

			min_val  =  min(min_val, x*x + y*y + z*z);

		}

		D_[mol] = min_val;






	}
}


//------------------------------------------------------------------------------------------------------------------------------------------------

__global__ void Action_noImage_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, int Nmols , int NAtoms,int NSAtoms , int active_size)
{

	__shared__ double dist_array[BLOCKDIM];
	//__shared__ double sAtom_shared[RSIZE];




	int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	

	//handling the chunks for  solute_atoms
	int chunksize,start,end, NChunks,i,j;

	if(NSAtoms*3 > RSIZE)
	{
		chunksize = (RSIZE/3)*3;
		NChunks = ceil(double(NSAtoms*3)/chunksize);
		start = 0;
		end = chunksize;
	}
	else
	{
		chunksize = NSAtoms*3;
		NChunks = 1;
		start = 0;
		end = NSAtoms*3;
	}

	// if(threadIdx.x == 0 && blockIdx.x == 0 )
	// 	printf("chunkszize = %d ; Nchunk =  %d; start = %d; end = %d\n ",
	// 		chunksize,NChunks,start,end);



	if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
	{

		// if(atom == 0 )
		// 	D_[mol] = maxD;
		//__syncthreads(); 
		double min_val  = maxD;
		double dist;
		int sIndex =  mol*NAtoms*3 + atom*3;
		double a0 = SolventMols_[sIndex + 0];
		double a1 = SolventMols_[sIndex + 1];
		double a2 = SolventMols_[sIndex + 2];


		for(i  = 0 ; i  < NChunks ; i++)
		{
			//copying to shared
			//if (threadIdx.x < (end - start))
			//	sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];

			//__syncthreads();

			//TODO - add skew per thread 
			for (j = start ; j < end; j+=3 )
			{
				//int offset = start + (j + threadIdx.x)%(end - start);
				double x = Solute_atoms[j + 0]  - a0;
				double y = Solute_atoms[j + 1]  - a1;
				double z = Solute_atoms[j + 2]  - a2;
				dist =  x*x + y*y + z*z;
				//if (mol ==  11)
				//	printf("min  = %f\n",min_val);
				min_val = min(min_val,dist);


			}

			start = end;
			end = min(end + chunksize, NSAtoms*3);


		}

		dist_array[threadIdx.x] = min_val;
		//if (threadIdx.x == 0)
		//	printf("min_val  = %f\n",min_val);
	//printf(" dist  =  %f\n", Dist);

		__syncthreads();

	//first thread
	//naive approach to a reduction algorithm
	//this works if NAtoms is small other wise you need split
	//and do some of log(n) parallel reduction 
		//min_val  = maxD;
		if( atom ==0 )
		{
			for(i  = 0 ; i < NAtoms ; i++ ){
				//sIndex = mol*NAtoms*3 + i*3;
				//if (dist_array[threadIdx.x + i]  < min_val) 
				//	min_val = dist_array[threadIdx.x + i] ;
				min_val =  min(min_val, dist_array[threadIdx.x + i]);
			}
			D_[mol] = min_val;
		}

	//if(tx == 0 && bx == 0 )
	//	printf("end of kernel");
	}
}





//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageOrtho_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, double *box, int Nmols , int NAtoms, int active_size)
{

	//__shared__ double dist_array[BLOCKDIM];



	//int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	//int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	int mol = blockIdx.x*BLOCKDIM + threadIdx.x;

	//advantage of register
	double a0 = maskCenter[0];
	double a1 = maskCenter[1];
	double a2 = maskCenter[2];



	if ( mol < Nmols )
	{



		int sIndex =  mol*NAtoms*3;
		double min_val  = maxD;
		double dist;
		for(int offset  = 0 ; offset < NAtoms ; offset++ )
		{

			double x = a0 - SolventMols_[sIndex++];
			double y = a1 - SolventMols_[sIndex++];
			double z = a2 - SolventMols_[sIndex++];

					// Get rid of sign info
			if (x<0) x=-x;
			if (y<0) y=-y;
			if (z<0) z=-z;
		  	// Get rid of multiples of box lengths 
			//TODO  WIERD that should be a way to simplify it
			while (x > box[0]) x = x - box[0];
			while (y > box[1]) y = y - box[1];
			while (z > box[2]) z = z - box[2];
		  	// Find shortest distance in periodic reference
			double D = box[0] - x;
			if (D < x) x = D;
			D = box[1] - y;
			if (D < y) y = D;  
			D = box[2] - z;
			if (D < z) z = D;




			//Dist = x*x + y*y + z*z;
			dist = x*x + y*y + z*z;
			if (box[0]==0.0 || box[1]==0.0 || box[2]==0.0)
				dist= -1.0;

			min_val  =  min(min_val, dist);

		}

		D_[mol] = min_val;






	}
}

//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageOrtho_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, double *box, int Nmols , int NAtoms,int NSAtoms , int active_size)
{

	__shared__ double dist_array[BLOCKDIM];
	//__shared__ double sAtom_shared[RSIZE];




	int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	

	//handling the chunks for  solute_atoms
	int chunksize,start,end, NChunks,i,j;

	if(NSAtoms*3 > RSIZE)
	{
		chunksize = (RSIZE/3)*3;
		NChunks = ceil(double(NSAtoms*3)/chunksize);
		start = 0;
		end = chunksize;
	}
	else
	{
		chunksize = NSAtoms*3;
		NChunks = 1;
		start = 0;
		end = NSAtoms*3;
	}

	// if(threadIdx.x == 0 && blockIdx.x == 0 )
	// 	printf("chunkszize = %d ; Nchunk =  %d; start = %d; end = %d\n ",
	// 		chunksize,NChunks,start,end);



	if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
	{

		// if(atom == 0 )
		// 	D_[mol] = maxD;
		//__syncthreads(); 
		double min_val  = maxD;
		double dist;
		int sIndex =  mol*NAtoms*3 + atom*3;
		double a0 = SolventMols_[sIndex + 0];
		double a1 = SolventMols_[sIndex + 1];
		double a2 = SolventMols_[sIndex + 2];


		for(i  = 0 ; i  < NChunks ; i++)
		{
			//copying to shared
			//if (threadIdx.x < (end - start))
			//	sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];

			//__syncthreads();

			//TODO - add skew per thread 
			for (j = start ; j < end; j+=3 )
			{
				//int offset = start + (j + threadIdx.x)%(end - start);
				double x = Solute_atoms[j + 0]  - a0;
				double y = Solute_atoms[j + 1]  - a1;
				double z = Solute_atoms[j + 2]  - a2;


				// Get rid of sign info
				if (x<0) x=-x;
				if (y<0) y=-y;
				if (z<0) z=-z;
		  		// Get rid of multiples of box lengths 
				//TODO  WIERD that should be a way to simplify it
				while (x > box[0]) x = x - box[0];
				while (y > box[1]) y = y - box[1];
				while (z > box[2]) z = z - box[2];

				//below is actually slower! 
				//x = x - box[0]*((int)x/box[0]);
				//y = y - box[0]*((int)y/box[1]);
				//z = z - box[0]*((int)z/box[2]);
		  	// Find shortest distance in periodic reference
				double D = box[0] - x;
				if (D < x) x = D;
				D = box[1] - y;
				if (D < y) y = D;  
				D = box[2] - z;
				if (D < z) z = D;


				//Dist = x*x + y*y + z*z;
				dist =  x*x + y*y + z*z;
				if (box[0]==0.0 || box[1]==0.0 || box[2]==0.0)
					dist = -1.0;





				//if (mol ==  11)
				//	printf("min  = %f\n",min_val);
				min_val = min(min_val,dist);


			}

			start = end;
			end = min(end + chunksize, NSAtoms*3);


		}

		dist_array[threadIdx.x] = min_val;
		//if (threadIdx.x == 0)
		//	printf("min_val  = %f\n",min_val);
	//printf(" dist  =  %f\n", Dist);

		__syncthreads();

	//first thread
	//naive approach to a reduction algorithm
	//this works if NAtoms is small other wise you need split
	//and do some of log(n) parallel reduction 
		//min_val  = maxD;
		if( atom ==0 )
		{
			for(i  = 0 ; i < NAtoms ; i++ ){
				//sIndex = mol*NAtoms*3 + i*3;
				//if (dist_array[threadIdx.x + i]  < min_val) 
				//	min_val = dist_array[threadIdx.x + i] ;
				min_val =  min(min_val, dist_array[threadIdx.x + i]);
			}
			D_[mol] = min_val;
		}

	//if(tx == 0 && bx == 0 )
	//	printf("end of kernel");
	}
}

//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageNonOrtho_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, double *ucell, double *recip, int Nmols , int NAtoms, int active_size)
{

	//__shared__ double dist_array[BLOCKDIM];



	//int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	//int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	int mol = blockIdx.x*BLOCKDIM + threadIdx.x;

	//advantage of register
	double a0 = recip[0]*maskCenter[0] + recip[1]*maskCenter[1] + recip[2]*maskCenter[2];
	double a1 = recip[3]*maskCenter[0] + recip[4]*maskCenter[1] + recip[5]*maskCenter[2];
	double a2 = recip[6]*maskCenter[0] + recip[7]*maskCenter[1] + recip[8]*maskCenter[2];



	if ( mol < Nmols )
	{



		int sIndex =  mol*NAtoms*3;
		double min_val  = maxD;
		for(int offset  = 0 ; offset < NAtoms*3 ; offset+=3 )
		{


			double x =  recip[0]*SolventMols_[sIndex + offset + 0] + recip[1]*SolventMols_[sIndex + offset + 1] + recip[2]*SolventMols_[sIndex + offset + 2];
			double y =  recip[3]*SolventMols_[sIndex + offset + 0] + recip[4]*SolventMols_[sIndex + offset + 1] + recip[5]*SolventMols_[sIndex + offset + 2];
			double z =  recip[6]*SolventMols_[sIndex + offset + 0] + recip[7]*SolventMols_[sIndex + offset + 1] + recip[8]*SolventMols_[sIndex + offset + 2];
			double dist  = NonOrtho_dist(x,y,z,a0,a1,a2,ucell);
			// if (mol ==  0)
			// 	printf("dist  = %f\n",dist);

			min_val  =  min(min_val, dist);

		}

		D_[mol] = min_val;






	}
}

//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageNonOrtho_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, double *ucell, double *recip, int Nmols , int NAtoms,int NSAtoms , int active_size)
{

	__shared__ double dist_array[BLOCKDIM];
	//__shared__ double sAtom_shared[RSIZE];




	int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	

	//handling the chunks for  solute_atoms
	int chunksize,start,end, NChunks,i,j;

	if(NSAtoms*3 > RSIZE)
	{
		chunksize = (RSIZE/3)*3;
		NChunks = ceil(double(NSAtoms*3)/chunksize);
		start = 0;
		end = chunksize;
	}
	else
	{
		chunksize = NSAtoms*3;
		NChunks = 1;
		start = 0;
		end = NSAtoms*3;
	}

	// if(threadIdx.x == 0 && blockIdx.x == 0 )
	// 	printf("chunkszize = %d ; Nchunk =  %d; start = %d; end = %d\n ",
	// 		chunksize,NChunks,start,end);



	if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
	{

		// if(atom == 0 )
		// 	D_[mol] = maxD;
		//__syncthreads(); 
		double min_val  = maxD;
		double dist;
		int sIndex =  mol*NAtoms*3 + atom*3;

		double a0 = recip[0]*SolventMols_[sIndex + 0] + recip[1]*SolventMols_[sIndex + 1] + recip[2]*SolventMols_[sIndex + 2];
		double a1 = recip[3]*SolventMols_[sIndex + 0] + recip[4]*SolventMols_[sIndex + 1] + recip[5]*SolventMols_[sIndex + 2];
		double a2 = recip[6]*SolventMols_[sIndex + 0] + recip[7]*SolventMols_[sIndex + 1] + recip[8]*SolventMols_[sIndex + 2];


		for(i  = 0 ; i  < NChunks ; i++)
		{
			//copying to shared
			//if (threadIdx.x < (end - start))
			//	sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];

			//__syncthreads();

			//TODO - add skew per thread 
			for (j = start ; j < end; j+=3 )
			{
				//int offset = start + (j + threadIdx.x)%(end - start);

				double x = recip[0]*Solute_atoms[j + 0]  + recip[1]*Solute_atoms[j + 1]  + recip[2]*Solute_atoms[j + 2] ;
				double y = recip[3]*Solute_atoms[j + 0]  + recip[4]*Solute_atoms[j + 1]  + recip[5]*Solute_atoms[j + 2] ;
				double z = recip[6]*Solute_atoms[j + 0]  + recip[7]*Solute_atoms[j + 1]  + recip[8]*Solute_atoms[j + 2] ;

				dist =  NonOrtho_dist(x,y,z,a0,a1,a2,ucell);
				//if (mol ==  11)
				//	printf("min  = %f\n",min_val);
				min_val = min(min_val,dist);


			}

			start = end;
			end = min(end + chunksize, NSAtoms*3);


		}

		dist_array[threadIdx.x] = min_val;
		//if (threadIdx.x == 0)
		//	printf("min_val  = %f\n",min_val);
	//printf(" dist  =  %f\n", Dist);

		__syncthreads();

	//first thread
	//naive approach to a reduction algorithm
	//this works if NAtoms is small other wise you need split
	//and do some of log(n) parallel reduction 
		//min_val  = maxD;
		if( atom ==0 )
		{
			for(i  = 0 ; i < NAtoms ; i++ ){
				//sIndex = mol*NAtoms*3 + i*3;
				//if (dist_array[threadIdx.x + i]  < min_val) 
				//	min_val = dist_array[threadIdx.x + i] ;
				min_val =  min(min_val, dist_array[threadIdx.x + i]);
			}
			D_[mol] = min_val;
		}

	//if(tx == 0 && bx == 0 )
	//	printf("end of kernel");
	}
}




//--------------------------------------------------------------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------------------------------------------------------------
//NonOrtho Distance function is complicated hence we will put into a __device__ only function
__device__ double NonOrtho_dist(double a0, double a1, double a2,
				double b0, double b1, double b2,
				double *ucell)
{
	int ixyz[3];
	double minIn  = -1.0;

	 //double closest2
  // The floor() calls serve to bring each point back in the main unit cell.
	double fx = a0 - floor(a0);
	double fy = a1 - floor(a1);
	double fz = a2 - floor(a2); 
	double f2x = b0 - floor(b0);
	double f2y = b1 - floor(b1);
	double f2z = b2 - floor(b2);
  // f2 back in Cartesian space
	double X_factor = (f2x*ucell[0] + f2y*ucell[3] + f2z*ucell[6]);
	double Y_factor = (f2x*ucell[1] + f2y*ucell[4] + f2z*ucell[7]);
	double Z_factor = (f2x*ucell[2] + f2y*ucell[5] + f2z*ucell[8]);
  // Precompute some factors
	double fxm1 = fx - 1.0;
	double fxp1 = fx + 1.0;
	double fym1 = fy - 1.0;
	double fyp1 = fy + 1.0;
	double fzm1 = fz - 1.0;
	double fzp1 = fz + 1.0;

	double fxm1u0 = fxm1 * ucell[0];
	double fxu0   = fx   * ucell[0];
	double fxp1u0 = fxp1 * ucell[0];
	double fxm1u1 = fxm1 * ucell[1];
	double fxu1   = fx   * ucell[1];
	double fxp1u1 = fxp1 * ucell[1];
	double fxm1u2 = fxm1 * ucell[2];
	double fxu2   = fx   * ucell[2];
	double fxp1u2 = fxp1 * ucell[2];

	double fym1u3 = fym1 * ucell[3];
	double fyu3   = fy   * ucell[3];
	double fyp1u3 = fyp1 * ucell[3];
	double fym1u4 = fym1 * ucell[4];
	double fyu4   = fy   * ucell[4];
	double fyp1u4 = fyp1 * ucell[4];
	double fym1u5 = fym1 * ucell[5];
	double fyu5   = fy   * ucell[5];
	double fyp1u5 = fyp1 * ucell[5];

	double fzm1u6 = fzm1 * ucell[6];
	double fzu6   = fz   * ucell[6];
	double fzp1u6 = fzp1 * ucell[6];
	double fzm1u7 = fzm1 * ucell[7];
	double fzu7   = fz   * ucell[7];
	double fzp1u7 = fzp1 * ucell[7];
	double fzm1u8 = fzm1 * ucell[8];
	double fzu8   = fz   * ucell[8];
	double fzp1u8 = fzp1 * ucell[8];

  // Calc ix iy iz = 0 case
	double x = (fxu0 + fyu3 + fzu6) - X_factor;
	double y = (fxu1 + fyu4 + fzu7) - Y_factor;
	double z = (fxu2 + fyu5 + fzu8) - Z_factor;
  // DEBUG
  //mprintf("DEBUG: a2: %g %g %g\n",(fxu0 + fyu3 + fzu6), (fxu1 + fyu4 + fzu7), (fxu2 + fyu5 + fzu8));
  //mprintf("DEBUG: a1: %g %g %g\n", X_factor, Y_factor, Z_factor);
	double min = (x*x) + (y*y) + (z*z);

	if (minIn > 0.0 && minIn < min) min = minIn;

	ixyz[0] = 0;
	ixyz[1] = 0;
	ixyz[2] = 0;

  // -1 -1 -1
	x = (fxm1u0 + fym1u3 + fzm1u6) - X_factor;
	y = (fxm1u1 + fym1u4 + fzm1u7) - Y_factor;
	z = (fxm1u2 + fym1u5 + fzm1u8) - Z_factor;
	double D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] = -1; ixyz[2] = -1; }
  // -1 -1  0
	x = (fxm1u0 + fym1u3 + fzu6  ) - X_factor;
	y = (fxm1u1 + fym1u4 + fzu7  ) - Y_factor;
	z = (fxm1u2 + fym1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] = -1; ixyz[2] =  0; }
  // -1 -1 +1
	x = (fxm1u0 + fym1u3 + fzp1u6) - X_factor;
	y = (fxm1u1 + fym1u4 + fzp1u7) - Y_factor;
	z = (fxm1u2 + fym1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] = -1; ixyz[2] =  1; }
  // -1  0 -1
	x = (fxm1u0 + fyu3   + fzm1u6) - X_factor;
	y = (fxm1u1 + fyu4   + fzm1u7) - Y_factor;
	z = (fxm1u2 + fyu5   + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  0; ixyz[2] = -1; }
  // -1  0  0
	x = (fxm1u0 + fyu3   + fzu6  ) - X_factor;
	y = (fxm1u1 + fyu4   + fzu7  ) - Y_factor;
	z = (fxm1u2 + fyu5   + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  0; ixyz[2] =  0; }
  // -1  0 +1
	x = (fxm1u0 + fyu3   + fzp1u6) - X_factor;
	y = (fxm1u1 + fyu4   + fzp1u7) - Y_factor;
	z = (fxm1u2 + fyu5   + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  0; ixyz[2] =  1; }
  // -1 +1 -1
	x = (fxm1u0 + fyp1u3 + fzm1u6) - X_factor;
	y = (fxm1u1 + fyp1u4 + fzm1u7) - Y_factor;
	z = (fxm1u2 + fyp1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  1; ixyz[2] = -1; }
  // -1 +1  0
	x = (fxm1u0 + fyp1u3 + fzu6  ) - X_factor;
	y = (fxm1u1 + fyp1u4 + fzu7  ) - Y_factor;
	z = (fxm1u2 + fyp1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  1; ixyz[2] =  0; }
  // -1 +1 +1
	x = (fxm1u0 + fyp1u3 + fzp1u6) - X_factor;
	y = (fxm1u1 + fyp1u4 + fzp1u7) - Y_factor;
	z = (fxm1u2 + fyp1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  1; ixyz[2] =  1; }

  //  0 -1 -1
	x = (fxu0   + fym1u3 + fzm1u6) - X_factor;
	y = (fxu1   + fym1u4 + fzm1u7) - Y_factor;
	z = (fxu2   + fym1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] = -1; ixyz[2] = -1; }
  //  0 -1  0
	x = (fxu0   + fym1u3 + fzu6  ) - X_factor;
	y = (fxu1   + fym1u4 + fzu7  ) - Y_factor;
	z = (fxu2   + fym1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] = -1; ixyz[2] =  0; }
  //  0 -1 +1
	x = (fxu0   + fym1u3 + fzp1u6) - X_factor;
	y = (fxu1   + fym1u4 + fzp1u7) - Y_factor;
	z = (fxu2   + fym1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] = -1; ixyz[2] =  1; }
  //  0  0 -1
	x = (fxu0   + fyu3   + fzm1u6) - X_factor;
	y = (fxu1   + fyu4   + fzm1u7) - Y_factor;
	z = (fxu2   + fyu5   + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  0; ixyz[2] = -1; }
  //  0  0  0
  //  0  0 +1
	x = (fxu0   + fyu3   + fzp1u6) - X_factor;
	y = (fxu1   + fyu4   + fzp1u7) - Y_factor;
	z = (fxu2   + fyu5   + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  0; ixyz[2] =  1; }
  //  0 +1 -1
	x = (fxu0   + fyp1u3 + fzm1u6) - X_factor;
	y = (fxu1   + fyp1u4 + fzm1u7) - Y_factor;
	z = (fxu2   + fyp1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  1; ixyz[2] = -1; }
  //  0 +1  0
	x = (fxu0   + fyp1u3 + fzu6  ) - X_factor;
	y = (fxu1   + fyp1u4 + fzu7  ) - Y_factor;
	z = (fxu2   + fyp1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  1; ixyz[2] =  0; }
  //  0 +1 +1
	x = (fxu0   + fyp1u3 + fzp1u6) - X_factor;
	y = (fxu1   + fyp1u4 + fzp1u7) - Y_factor;
	z = (fxu2   + fyp1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  1; ixyz[2] =  1; }

  // +1 -1 -1
	x = (fxp1u0 + fym1u3 + fzm1u6) - X_factor;
	y = (fxp1u1 + fym1u4 + fzm1u7) - Y_factor;
	z = (fxp1u2 + fym1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] = -1; ixyz[2] = -1; }
  // +1 -1  0
	x = (fxp1u0 + fym1u3 + fzu6  ) - X_factor;
	y = (fxp1u1 + fym1u4 + fzu7  ) - Y_factor;
	z = (fxp1u2 + fym1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] = -1; ixyz[2] =  0; }
  // +1 -1 +1
	x = (fxp1u0 + fym1u3 + fzp1u6) - X_factor;
	y = (fxp1u1 + fym1u4 + fzp1u7) - Y_factor;
	z = (fxp1u2 + fym1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] = -1; ixyz[2] =  1; }
  // +1  0 -1
	x = (fxp1u0 + fyu3   + fzm1u6) - X_factor;
	y = (fxp1u1 + fyu4   + fzm1u7) - Y_factor;
	z = (fxp1u2 + fyu5   + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  0; ixyz[2] = -1; }
  // +1  0  0
	x = (fxp1u0 + fyu3   + fzu6  ) - X_factor;
	y = (fxp1u1 + fyu4   + fzu7  ) - Y_factor;
	z = (fxp1u2 + fyu5   + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  0; ixyz[2] =  0; }
  // +1  0 +1
	x = (fxp1u0 + fyu3   + fzp1u6) - X_factor;
	y = (fxp1u1 + fyu4   + fzp1u7) - Y_factor;
	z = (fxp1u2 + fyu5   + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  0; ixyz[2] =  1; }
  // +1 +1 -1
	x = (fxp1u0 + fyp1u3 + fzm1u6) - X_factor;
	y = (fxp1u1 + fyp1u4 + fzm1u7) - Y_factor;
	z = (fxp1u2 + fyp1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  1; ixyz[2] = -1; }
  // +1 +1  0
	x = (fxp1u0 + fyp1u3 + fzu6  ) - X_factor;
	y = (fxp1u1 + fyp1u4 + fzu7  ) - Y_factor;
	z = (fxp1u2 + fyp1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  1; ixyz[2] =  0; }
  // +1 +1 +1
	x = (fxp1u0 + fyp1u3 + fzp1u6) - X_factor;
	y = (fxp1u1 + fyp1u4 + fzp1u7) - Y_factor;
	z = (fxp1u2 + fyp1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  1; ixyz[2] =  1; }

  //if (closest2 != 0.0 && min < closest2) return (min);
//  this->ClosestImage(a1, a2, ixyz);
//  fprintf(stdout,"DEBUG: Predict  = %2i %2i %2i\n",ixyz[0],ixyz[1],ixyz[2]);

//  ix = ixyz[0];
//  iy = ixyz[1];
//  iz = ixyz[2];

//D = sqrt(min);
//  fprintf(stdout,"DEBUG: MinDist  = %2i %2i %2i = %8.3f\n", ixmin, iymin, izmin, D);
//  printf("---------------------------------------------------------------\n");
	return(min);

}

	.file	"tmpxft_002d2772_00000000-6_core_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13NonOrtho_distddddddPd
	.type	_Z13NonOrtho_distddddddPd, @function
_Z13NonOrtho_distddddddPd:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z13NonOrtho_distddddddPd, .-_Z13NonOrtho_distddddddPd
	.globl	_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
	.type	_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii, @function
_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z25Action_noImage_center_GPUPdS_S_diii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L4:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii, .-_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
	.globl	_Z25Action_noImage_center_GPUPdS_S_diii
	.type	_Z25Action_noImage_center_GPUPdS_S_diii, @function
_Z25Action_noImage_center_GPUPdS_S_diii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
	.cfi_endproc
.LFE2053:
	.size	_Z25Action_noImage_center_GPUPdS_S_diii, .-_Z25Action_noImage_center_GPUPdS_S_diii
	.globl	_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
	.type	_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii, @function
_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z28Action_noImage_no_center_GPUPdS_S_diiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L10:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii, .-_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
	.globl	_Z28Action_noImage_no_center_GPUPdS_S_diiii
	.type	_Z28Action_noImage_no_center_GPUPdS_S_diiii, @function
_Z28Action_noImage_no_center_GPUPdS_S_diiii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
	.cfi_endproc
.LFE2055:
	.size	_Z28Action_noImage_no_center_GPUPdS_S_diiii, .-_Z28Action_noImage_no_center_GPUPdS_S_diiii
	.globl	_Z58__device_stub__Z28Action_ImageOrtho_center_GPUPdS_S_dS_iiiPdS_S_dS_iii
	.type	_Z58__device_stub__Z28Action_ImageOrtho_center_GPUPdS_S_dS_iiiPdS_S_dS_iii, @function
_Z58__device_stub__Z28Action_ImageOrtho_center_GPUPdS_S_dS_iiiPdS_S_dS_iii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	%rsp, %rax
	movq	%rax, 168(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L15:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z58__device_stub__Z28Action_ImageOrtho_center_GPUPdS_S_dS_iiiPdS_S_dS_iii, .-_Z58__device_stub__Z28Action_ImageOrtho_center_GPUPdS_S_dS_iiiPdS_S_dS_iii
	.globl	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.type	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii, @function
_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z28Action_ImageOrtho_center_GPUPdS_S_dS_iiiPdS_S_dS_iii
	.cfi_endproc
.LFE2057:
	.size	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii, .-_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.globl	_Z62__device_stub__Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiiiPdS_S_dS_iiii
	.type	_Z62__device_stub__Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiiiPdS_S_dS_iiii, @function
_Z62__device_stub__Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiiiPdS_S_dS_iiii:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L20:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z62__device_stub__Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiiiPdS_S_dS_iiii, .-_Z62__device_stub__Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiiiPdS_S_dS_iiii
	.globl	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.type	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii, @function
_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiiiPdS_S_dS_iiii
	.cfi_endproc
.LFE2059:
	.size	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii, .-_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.globl	_Z63__device_stub__Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iiiPdS_S_dS_S_iii
	.type	_Z63__device_stub__Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iiiPdS_S_dS_S_iii, @function
_Z63__device_stub__Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iiiPdS_S_dS_S_iii:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L25:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z63__device_stub__Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iiiPdS_S_dS_S_iii, .-_Z63__device_stub__Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iiiPdS_S_dS_S_iii
	.globl	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.type	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii, @function
_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z63__device_stub__Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iiiPdS_S_dS_S_iii
	.cfi_endproc
.LFE2061:
	.size	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii, .-_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.globl	_Z67__device_stub__Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiiiPdS_S_dS_S_iiii
	.type	_Z67__device_stub__Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiiiPdS_S_dS_S_iiii, @function
_Z67__device_stub__Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiiiPdS_S_dS_S_iiii:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movsd	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L30:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z67__device_stub__Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiiiPdS_S_dS_S_iiii, .-_Z67__device_stub__Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiiiPdS_S_dS_S_iiii
	.globl	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.type	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii, @function
_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiiiPdS_S_dS_S_iiii
	.cfi_endproc
.LFE2063:
	.size	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii, .-_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii"
.LC1:
	.string	"_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii"
.LC2:
	.string	"_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii"
.LC3:
	.string	"_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii"
.LC4:
	.string	"_Z28Action_noImage_no_center_GPUPdS_S_diiii"
.LC5:
	.string	"_Z25Action_noImage_center_GPUPdS_S_diii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28Action_noImage_no_center_GPUPdS_S_diiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z25Action_noImage_center_GPUPdS_S_diii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2065:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

#define BLOCKDIM 512
#define RSIZE 10
#define JFACTOR 1


__device__ double NonOrtho_dist(double a0, double a1, double a2,
				double b0, double b1, double b2,
				double *ucell);

//------------------------------------------------------------------------------------------------------------------------------------------------
//try thread coarsening 

__global__ void Action_noImage_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, int Nmols , int NAtoms, int active_size)
{

	//__shared__ double dist_array[BLOCKDIM];



	//int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	//int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	int mol = blockIdx.x*BLOCKDIM + threadIdx.x;

	//advantage of register
	double a0 = maskCenter[0];
	double a1 = maskCenter[1];
	double a2 = maskCenter[2];



	if ( mol < Nmols )
	{



		int sIndex =  mol*NAtoms*3;
		double min_val  = maxD;
		for(int offset  = 0 ; offset < NAtoms*3 ; offset+=3 )
		{

			//double x = a0 - SolventMols_[sIndex++];
			//double y = a1 - SolventMols_[sIndex++];
			//double z = a2 - SolventMols_[sIndex++];

			double x = a0 - SolventMols_[sIndex+ offset + 0 ];
			double y = a1 - SolventMols_[sIndex+offset + 1];
			double z = a2 - SolventMols_[sIndex+offset + 2];

			min_val  =  min(min_val, x*x + y*y + z*z);

		}

		D_[mol] = min_val;






	}
}


//------------------------------------------------------------------------------------------------------------------------------------------------

__global__ void Action_noImage_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, int Nmols , int NAtoms,int NSAtoms , int active_size)
{

	__shared__ double dist_array[BLOCKDIM];
	//__shared__ double sAtom_shared[RSIZE];




	int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	

	//handling the chunks for  solute_atoms
	int chunksize,start,end, NChunks,i,j;

	if(NSAtoms*3 > RSIZE)
	{
		chunksize = (RSIZE/3)*3;
		NChunks = ceil(double(NSAtoms*3)/chunksize);
		start = 0;
		end = chunksize;
	}
	else
	{
		chunksize = NSAtoms*3;
		NChunks = 1;
		start = 0;
		end = NSAtoms*3;
	}

	// if(threadIdx.x == 0 && blockIdx.x == 0 )
	// 	printf("chunkszize = %d ; Nchunk =  %d; start = %d; end = %d\n ",
	// 		chunksize,NChunks,start,end);



	if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
	{

		// if(atom == 0 )
		// 	D_[mol] = maxD;
		//__syncthreads(); 
		double min_val  = maxD;
		double dist;
		int sIndex =  mol*NAtoms*3 + atom*3;
		double a0 = SolventMols_[sIndex + 0];
		double a1 = SolventMols_[sIndex + 1];
		double a2 = SolventMols_[sIndex + 2];


		for(i  = 0 ; i  < NChunks ; i++)
		{
			//copying to shared
			//if (threadIdx.x < (end - start))
			//	sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];

			//__syncthreads();

			//TODO - add skew per thread 
			for (j = start ; j < end; j+=3 )
			{
				//int offset = start + (j + threadIdx.x)%(end - start);
				double x = Solute_atoms[j + 0]  - a0;
				double y = Solute_atoms[j + 1]  - a1;
				double z = Solute_atoms[j + 2]  - a2;
				dist =  x*x + y*y + z*z;
				//if (mol ==  11)
				//	printf("min  = %f\n",min_val);
				min_val = min(min_val,dist);


			}

			start = end;
			end = min(end + chunksize, NSAtoms*3);


		}

		dist_array[threadIdx.x] = min_val;
		//if (threadIdx.x == 0)
		//	printf("min_val  = %f\n",min_val);
	//printf(" dist  =  %f\n", Dist);

		__syncthreads();

	//first thread
	//naive approach to a reduction algorithm
	//this works if NAtoms is small other wise you need split
	//and do some of log(n) parallel reduction 
		//min_val  = maxD;
		if( atom ==0 )
		{
			for(i  = 0 ; i < NAtoms ; i++ ){
				//sIndex = mol*NAtoms*3 + i*3;
				//if (dist_array[threadIdx.x + i]  < min_val) 
				//	min_val = dist_array[threadIdx.x + i] ;
				min_val =  min(min_val, dist_array[threadIdx.x + i]);
			}
			D_[mol] = min_val;
		}

	//if(tx == 0 && bx == 0 )
	//	printf("end of kernel");
	}
}





//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageOrtho_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, double *box, int Nmols , int NAtoms, int active_size)
{

	//__shared__ double dist_array[BLOCKDIM];



	//int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	//int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	int mol = blockIdx.x*BLOCKDIM + threadIdx.x;

	//advantage of register
	double a0 = maskCenter[0];
	double a1 = maskCenter[1];
	double a2 = maskCenter[2];



	if ( mol < Nmols )
	{



		int sIndex =  mol*NAtoms*3;
		double min_val  = maxD;
		double dist;
		for(int offset  = 0 ; offset < NAtoms ; offset++ )
		{

			double x = a0 - SolventMols_[sIndex++];
			double y = a1 - SolventMols_[sIndex++];
			double z = a2 - SolventMols_[sIndex++];

					// Get rid of sign info
			if (x<0) x=-x;
			if (y<0) y=-y;
			if (z<0) z=-z;
		  	// Get rid of multiples of box lengths 
			//TODO  WIERD that should be a way to simplify it
			while (x > box[0]) x = x - box[0];
			while (y > box[1]) y = y - box[1];
			while (z > box[2]) z = z - box[2];
		  	// Find shortest distance in periodic reference
			double D = box[0] - x;
			if (D < x) x = D;
			D = box[1] - y;
			if (D < y) y = D;  
			D = box[2] - z;
			if (D < z) z = D;




			//Dist = x*x + y*y + z*z;
			dist = x*x + y*y + z*z;
			if (box[0]==0.0 || box[1]==0.0 || box[2]==0.0)
				dist= -1.0;

			min_val  =  min(min_val, dist);

		}

		D_[mol] = min_val;






	}
}

//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageOrtho_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, double *box, int Nmols , int NAtoms,int NSAtoms , int active_size)
{

	__shared__ double dist_array[BLOCKDIM];
	//__shared__ double sAtom_shared[RSIZE];




	int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	

	//handling the chunks for  solute_atoms
	int chunksize,start,end, NChunks,i,j;

	if(NSAtoms*3 > RSIZE)
	{
		chunksize = (RSIZE/3)*3;
		NChunks = ceil(double(NSAtoms*3)/chunksize);
		start = 0;
		end = chunksize;
	}
	else
	{
		chunksize = NSAtoms*3;
		NChunks = 1;
		start = 0;
		end = NSAtoms*3;
	}

	// if(threadIdx.x == 0 && blockIdx.x == 0 )
	// 	printf("chunkszize = %d ; Nchunk =  %d; start = %d; end = %d\n ",
	// 		chunksize,NChunks,start,end);



	if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
	{

		// if(atom == 0 )
		// 	D_[mol] = maxD;
		//__syncthreads(); 
		double min_val  = maxD;
		double dist;
		int sIndex =  mol*NAtoms*3 + atom*3;
		double a0 = SolventMols_[sIndex + 0];
		double a1 = SolventMols_[sIndex + 1];
		double a2 = SolventMols_[sIndex + 2];


		for(i  = 0 ; i  < NChunks ; i++)
		{
			//copying to shared
			//if (threadIdx.x < (end - start))
			//	sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];

			//__syncthreads();

			//TODO - add skew per thread 
			for (j = start ; j < end; j+=3 )
			{
				//int offset = start + (j + threadIdx.x)%(end - start);
				double x = Solute_atoms[j + 0]  - a0;
				double y = Solute_atoms[j + 1]  - a1;
				double z = Solute_atoms[j + 2]  - a2;


				// Get rid of sign info
				if (x<0) x=-x;
				if (y<0) y=-y;
				if (z<0) z=-z;
		  		// Get rid of multiples of box lengths 
				//TODO  WIERD that should be a way to simplify it
				while (x > box[0]) x = x - box[0];
				while (y > box[1]) y = y - box[1];
				while (z > box[2]) z = z - box[2];

				//below is actually slower! 
				//x = x - box[0]*((int)x/box[0]);
				//y = y - box[0]*((int)y/box[1]);
				//z = z - box[0]*((int)z/box[2]);
		  	// Find shortest distance in periodic reference
				double D = box[0] - x;
				if (D < x) x = D;
				D = box[1] - y;
				if (D < y) y = D;  
				D = box[2] - z;
				if (D < z) z = D;


				//Dist = x*x + y*y + z*z;
				dist =  x*x + y*y + z*z;
				if (box[0]==0.0 || box[1]==0.0 || box[2]==0.0)
					dist = -1.0;





				//if (mol ==  11)
				//	printf("min  = %f\n",min_val);
				min_val = min(min_val,dist);


			}

			start = end;
			end = min(end + chunksize, NSAtoms*3);


		}

		dist_array[threadIdx.x] = min_val;
		//if (threadIdx.x == 0)
		//	printf("min_val  = %f\n",min_val);
	//printf(" dist  =  %f\n", Dist);

		__syncthreads();

	//first thread
	//naive approach to a reduction algorithm
	//this works if NAtoms is small other wise you need split
	//and do some of log(n) parallel reduction 
		//min_val  = maxD;
		if( atom ==0 )
		{
			for(i  = 0 ; i < NAtoms ; i++ ){
				//sIndex = mol*NAtoms*3 + i*3;
				//if (dist_array[threadIdx.x + i]  < min_val) 
				//	min_val = dist_array[threadIdx.x + i] ;
				min_val =  min(min_val, dist_array[threadIdx.x + i]);
			}
			D_[mol] = min_val;
		}

	//if(tx == 0 && bx == 0 )
	//	printf("end of kernel");
	}
}

//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageNonOrtho_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, double *ucell, double *recip, int Nmols , int NAtoms, int active_size)
{

	//__shared__ double dist_array[BLOCKDIM];



	//int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	//int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	int mol = blockIdx.x*BLOCKDIM + threadIdx.x;

	//advantage of register
	double a0 = recip[0]*maskCenter[0] + recip[1]*maskCenter[1] + recip[2]*maskCenter[2];
	double a1 = recip[3]*maskCenter[0] + recip[4]*maskCenter[1] + recip[5]*maskCenter[2];
	double a2 = recip[6]*maskCenter[0] + recip[7]*maskCenter[1] + recip[8]*maskCenter[2];



	if ( mol < Nmols )
	{



		int sIndex =  mol*NAtoms*3;
		double min_val  = maxD;
		for(int offset  = 0 ; offset < NAtoms*3 ; offset+=3 )
		{


			double x =  recip[0]*SolventMols_[sIndex + offset + 0] + recip[1]*SolventMols_[sIndex + offset + 1] + recip[2]*SolventMols_[sIndex + offset + 2];
			double y =  recip[3]*SolventMols_[sIndex + offset + 0] + recip[4]*SolventMols_[sIndex + offset + 1] + recip[5]*SolventMols_[sIndex + offset + 2];
			double z =  recip[6]*SolventMols_[sIndex + offset + 0] + recip[7]*SolventMols_[sIndex + offset + 1] + recip[8]*SolventMols_[sIndex + offset + 2];
			double dist  = NonOrtho_dist(x,y,z,a0,a1,a2,ucell);
			// if (mol ==  0)
			// 	printf("dist  = %f\n",dist);

			min_val  =  min(min_val, dist);

		}

		D_[mol] = min_val;






	}
}

//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_ImageNonOrtho_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, double *ucell, double *recip, int Nmols , int NAtoms,int NSAtoms , int active_size)
{

	__shared__ double dist_array[BLOCKDIM];
	//__shared__ double sAtom_shared[RSIZE];




	int mol  =  (blockIdx.x * active_size + threadIdx.x)/NAtoms; 
	int atom  = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
	//int mol_in_block = threadIdx.x/NAtoms;

	

	//handling the chunks for  solute_atoms
	int chunksize,start,end, NChunks,i,j;

	if(NSAtoms*3 > RSIZE)
	{
		chunksize = (RSIZE/3)*3;
		NChunks = ceil(double(NSAtoms*3)/chunksize);
		start = 0;
		end = chunksize;
	}
	else
	{
		chunksize = NSAtoms*3;
		NChunks = 1;
		start = 0;
		end = NSAtoms*3;
	}

	// if(threadIdx.x == 0 && blockIdx.x == 0 )
	// 	printf("chunkszize = %d ; Nchunk =  %d; start = %d; end = %d\n ",
	// 		chunksize,NChunks,start,end);



	if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
	{

		// if(atom == 0 )
		// 	D_[mol] = maxD;
		//__syncthreads(); 
		double min_val  = maxD;
		double dist;
		int sIndex =  mol*NAtoms*3 + atom*3;

		double a0 = recip[0]*SolventMols_[sIndex + 0] + recip[1]*SolventMols_[sIndex + 1] + recip[2]*SolventMols_[sIndex + 2];
		double a1 = recip[3]*SolventMols_[sIndex + 0] + recip[4]*SolventMols_[sIndex + 1] + recip[5]*SolventMols_[sIndex + 2];
		double a2 = recip[6]*SolventMols_[sIndex + 0] + recip[7]*SolventMols_[sIndex + 1] + recip[8]*SolventMols_[sIndex + 2];


		for(i  = 0 ; i  < NChunks ; i++)
		{
			//copying to shared
			//if (threadIdx.x < (end - start))
			//	sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];

			//__syncthreads();

			//TODO - add skew per thread 
			for (j = start ; j < end; j+=3 )
			{
				//int offset = start + (j + threadIdx.x)%(end - start);

				double x = recip[0]*Solute_atoms[j + 0]  + recip[1]*Solute_atoms[j + 1]  + recip[2]*Solute_atoms[j + 2] ;
				double y = recip[3]*Solute_atoms[j + 0]  + recip[4]*Solute_atoms[j + 1]  + recip[5]*Solute_atoms[j + 2] ;
				double z = recip[6]*Solute_atoms[j + 0]  + recip[7]*Solute_atoms[j + 1]  + recip[8]*Solute_atoms[j + 2] ;

				dist =  NonOrtho_dist(x,y,z,a0,a1,a2,ucell);
				//if (mol ==  11)
				//	printf("min  = %f\n",min_val);
				min_val = min(min_val,dist);


			}

			start = end;
			end = min(end + chunksize, NSAtoms*3);


		}

		dist_array[threadIdx.x] = min_val;
		//if (threadIdx.x == 0)
		//	printf("min_val  = %f\n",min_val);
	//printf(" dist  =  %f\n", Dist);

		__syncthreads();

	//first thread
	//naive approach to a reduction algorithm
	//this works if NAtoms is small other wise you need split
	//and do some of log(n) parallel reduction 
		//min_val  = maxD;
		if( atom ==0 )
		{
			for(i  = 0 ; i < NAtoms ; i++ ){
				//sIndex = mol*NAtoms*3 + i*3;
				//if (dist_array[threadIdx.x + i]  < min_val) 
				//	min_val = dist_array[threadIdx.x + i] ;
				min_val =  min(min_val, dist_array[threadIdx.x + i]);
			}
			D_[mol] = min_val;
		}

	//if(tx == 0 && bx == 0 )
	//	printf("end of kernel");
	}
}




//--------------------------------------------------------------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------------------------------------------------------------
//NonOrtho Distance function is complicated hence we will put into a __device__ only function
__device__ double NonOrtho_dist(double a0, double a1, double a2,
				double b0, double b1, double b2,
				double *ucell)
{
	int ixyz[3];
	double minIn  = -1.0;

	 //double closest2
  // The floor() calls serve to bring each point back in the main unit cell.
	double fx = a0 - floor(a0);
	double fy = a1 - floor(a1);
	double fz = a2 - floor(a2); 
	double f2x = b0 - floor(b0);
	double f2y = b1 - floor(b1);
	double f2z = b2 - floor(b2);
  // f2 back in Cartesian space
	double X_factor = (f2x*ucell[0] + f2y*ucell[3] + f2z*ucell[6]);
	double Y_factor = (f2x*ucell[1] + f2y*ucell[4] + f2z*ucell[7]);
	double Z_factor = (f2x*ucell[2] + f2y*ucell[5] + f2z*ucell[8]);
  // Precompute some factors
	double fxm1 = fx - 1.0;
	double fxp1 = fx + 1.0;
	double fym1 = fy - 1.0;
	double fyp1 = fy + 1.0;
	double fzm1 = fz - 1.0;
	double fzp1 = fz + 1.0;

	double fxm1u0 = fxm1 * ucell[0];
	double fxu0   = fx   * ucell[0];
	double fxp1u0 = fxp1 * ucell[0];
	double fxm1u1 = fxm1 * ucell[1];
	double fxu1   = fx   * ucell[1];
	double fxp1u1 = fxp1 * ucell[1];
	double fxm1u2 = fxm1 * ucell[2];
	double fxu2   = fx   * ucell[2];
	double fxp1u2 = fxp1 * ucell[2];

	double fym1u3 = fym1 * ucell[3];
	double fyu3   = fy   * ucell[3];
	double fyp1u3 = fyp1 * ucell[3];
	double fym1u4 = fym1 * ucell[4];
	double fyu4   = fy   * ucell[4];
	double fyp1u4 = fyp1 * ucell[4];
	double fym1u5 = fym1 * ucell[5];
	double fyu5   = fy   * ucell[5];
	double fyp1u5 = fyp1 * ucell[5];

	double fzm1u6 = fzm1 * ucell[6];
	double fzu6   = fz   * ucell[6];
	double fzp1u6 = fzp1 * ucell[6];
	double fzm1u7 = fzm1 * ucell[7];
	double fzu7   = fz   * ucell[7];
	double fzp1u7 = fzp1 * ucell[7];
	double fzm1u8 = fzm1 * ucell[8];
	double fzu8   = fz   * ucell[8];
	double fzp1u8 = fzp1 * ucell[8];

  // Calc ix iy iz = 0 case
	double x = (fxu0 + fyu3 + fzu6) - X_factor;
	double y = (fxu1 + fyu4 + fzu7) - Y_factor;
	double z = (fxu2 + fyu5 + fzu8) - Z_factor;
  // DEBUG
  //mprintf("DEBUG: a2: %g %g %g\n",(fxu0 + fyu3 + fzu6), (fxu1 + fyu4 + fzu7), (fxu2 + fyu5 + fzu8));
  //mprintf("DEBUG: a1: %g %g %g\n", X_factor, Y_factor, Z_factor);
	double min = (x*x) + (y*y) + (z*z);

	if (minIn > 0.0 && minIn < min) min = minIn;

	ixyz[0] = 0;
	ixyz[1] = 0;
	ixyz[2] = 0;

  // -1 -1 -1
	x = (fxm1u0 + fym1u3 + fzm1u6) - X_factor;
	y = (fxm1u1 + fym1u4 + fzm1u7) - Y_factor;
	z = (fxm1u2 + fym1u5 + fzm1u8) - Z_factor;
	double D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] = -1; ixyz[2] = -1; }
  // -1 -1  0
	x = (fxm1u0 + fym1u3 + fzu6  ) - X_factor;
	y = (fxm1u1 + fym1u4 + fzu7  ) - Y_factor;
	z = (fxm1u2 + fym1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] = -1; ixyz[2] =  0; }
  // -1 -1 +1
	x = (fxm1u0 + fym1u3 + fzp1u6) - X_factor;
	y = (fxm1u1 + fym1u4 + fzp1u7) - Y_factor;
	z = (fxm1u2 + fym1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] = -1; ixyz[2] =  1; }
  // -1  0 -1
	x = (fxm1u0 + fyu3   + fzm1u6) - X_factor;
	y = (fxm1u1 + fyu4   + fzm1u7) - Y_factor;
	z = (fxm1u2 + fyu5   + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  0; ixyz[2] = -1; }
  // -1  0  0
	x = (fxm1u0 + fyu3   + fzu6  ) - X_factor;
	y = (fxm1u1 + fyu4   + fzu7  ) - Y_factor;
	z = (fxm1u2 + fyu5   + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  0; ixyz[2] =  0; }
  // -1  0 +1
	x = (fxm1u0 + fyu3   + fzp1u6) - X_factor;
	y = (fxm1u1 + fyu4   + fzp1u7) - Y_factor;
	z = (fxm1u2 + fyu5   + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  0; ixyz[2] =  1; }
  // -1 +1 -1
	x = (fxm1u0 + fyp1u3 + fzm1u6) - X_factor;
	y = (fxm1u1 + fyp1u4 + fzm1u7) - Y_factor;
	z = (fxm1u2 + fyp1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  1; ixyz[2] = -1; }
  // -1 +1  0
	x = (fxm1u0 + fyp1u3 + fzu6  ) - X_factor;
	y = (fxm1u1 + fyp1u4 + fzu7  ) - Y_factor;
	z = (fxm1u2 + fyp1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  1; ixyz[2] =  0; }
  // -1 +1 +1
	x = (fxm1u0 + fyp1u3 + fzp1u6) - X_factor;
	y = (fxm1u1 + fyp1u4 + fzp1u7) - Y_factor;
	z = (fxm1u2 + fyp1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] = -1; ixyz[1] =  1; ixyz[2] =  1; }

  //  0 -1 -1
	x = (fxu0   + fym1u3 + fzm1u6) - X_factor;
	y = (fxu1   + fym1u4 + fzm1u7) - Y_factor;
	z = (fxu2   + fym1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] = -1; ixyz[2] = -1; }
  //  0 -1  0
	x = (fxu0   + fym1u3 + fzu6  ) - X_factor;
	y = (fxu1   + fym1u4 + fzu7  ) - Y_factor;
	z = (fxu2   + fym1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] = -1; ixyz[2] =  0; }
  //  0 -1 +1
	x = (fxu0   + fym1u3 + fzp1u6) - X_factor;
	y = (fxu1   + fym1u4 + fzp1u7) - Y_factor;
	z = (fxu2   + fym1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] = -1; ixyz[2] =  1; }
  //  0  0 -1
	x = (fxu0   + fyu3   + fzm1u6) - X_factor;
	y = (fxu1   + fyu4   + fzm1u7) - Y_factor;
	z = (fxu2   + fyu5   + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  0; ixyz[2] = -1; }
  //  0  0  0
  //  0  0 +1
	x = (fxu0   + fyu3   + fzp1u6) - X_factor;
	y = (fxu1   + fyu4   + fzp1u7) - Y_factor;
	z = (fxu2   + fyu5   + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  0; ixyz[2] =  1; }
  //  0 +1 -1
	x = (fxu0   + fyp1u3 + fzm1u6) - X_factor;
	y = (fxu1   + fyp1u4 + fzm1u7) - Y_factor;
	z = (fxu2   + fyp1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  1; ixyz[2] = -1; }
  //  0 +1  0
	x = (fxu0   + fyp1u3 + fzu6  ) - X_factor;
	y = (fxu1   + fyp1u4 + fzu7  ) - Y_factor;
	z = (fxu2   + fyp1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  1; ixyz[2] =  0; }
  //  0 +1 +1
	x = (fxu0   + fyp1u3 + fzp1u6) - X_factor;
	y = (fxu1   + fyp1u4 + fzp1u7) - Y_factor;
	z = (fxu2   + fyp1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  0; ixyz[1] =  1; ixyz[2] =  1; }

  // +1 -1 -1
	x = (fxp1u0 + fym1u3 + fzm1u6) - X_factor;
	y = (fxp1u1 + fym1u4 + fzm1u7) - Y_factor;
	z = (fxp1u2 + fym1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] = -1; ixyz[2] = -1; }
  // +1 -1  0
	x = (fxp1u0 + fym1u3 + fzu6  ) - X_factor;
	y = (fxp1u1 + fym1u4 + fzu7  ) - Y_factor;
	z = (fxp1u2 + fym1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] = -1; ixyz[2] =  0; }
  // +1 -1 +1
	x = (fxp1u0 + fym1u3 + fzp1u6) - X_factor;
	y = (fxp1u1 + fym1u4 + fzp1u7) - Y_factor;
	z = (fxp1u2 + fym1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] = -1; ixyz[2] =  1; }
  // +1  0 -1
	x = (fxp1u0 + fyu3   + fzm1u6) - X_factor;
	y = (fxp1u1 + fyu4   + fzm1u7) - Y_factor;
	z = (fxp1u2 + fyu5   + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  0; ixyz[2] = -1; }
  // +1  0  0
	x = (fxp1u0 + fyu3   + fzu6  ) - X_factor;
	y = (fxp1u1 + fyu4   + fzu7  ) - Y_factor;
	z = (fxp1u2 + fyu5   + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  0; ixyz[2] =  0; }
  // +1  0 +1
	x = (fxp1u0 + fyu3   + fzp1u6) - X_factor;
	y = (fxp1u1 + fyu4   + fzp1u7) - Y_factor;
	z = (fxp1u2 + fyu5   + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  0; ixyz[2] =  1; }
  // +1 +1 -1
	x = (fxp1u0 + fyp1u3 + fzm1u6) - X_factor;
	y = (fxp1u1 + fyp1u4 + fzm1u7) - Y_factor;
	z = (fxp1u2 + fyp1u5 + fzm1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  1; ixyz[2] = -1; }
  // +1 +1  0
	x = (fxp1u0 + fyp1u3 + fzu6  ) - X_factor;
	y = (fxp1u1 + fyp1u4 + fzu7  ) - Y_factor;
	z = (fxp1u2 + fyp1u5 + fzu8  ) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  1; ixyz[2] =  0; }
  // +1 +1 +1
	x = (fxp1u0 + fyp1u3 + fzp1u6) - X_factor;
	y = (fxp1u1 + fyp1u4 + fzp1u7) - Y_factor;
	z = (fxp1u2 + fyp1u5 + fzp1u8) - Z_factor;
	D = (x*x) + (y*y) + (z*z);
	if (D < min) { min = D; ixyz[0] =  1; ixyz[1] =  1; ixyz[2] =  1; }

  //if (closest2 != 0.0 && min < closest2) return (min);
//  this->ClosestImage(a1, a2, ixyz);
//  fprintf(stdout,"DEBUG: Predict  = %2i %2i %2i\n",ixyz[0],ixyz[1],ixyz[2]);

//  ix = ixyz[0];
//  iy = ixyz[1];
//  iz = ixyz[2];

//D = sqrt(min);
//  fprintf(stdout,"DEBUG: MinDist  = %2i %2i %2i = %8.3f\n", ixmin, iymin, izmin, D);
//  printf("---------------------------------------------------------------\n");
	return(min);

}

	.text
	.file	"core_kernels.hip"
	.globl	_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii # -- Begin function _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
	.type	_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii,@function
_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii: # @_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	12(%rsp), %r10
	movl	%ecx, (%r10)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25Action_noImage_center_GPUPdS_S_diii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii, .Lfunc_end0-_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii # -- Begin function _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
	.type	_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii,@function
_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii: # @_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	12(%rsp), %r10
	movl	%ecx, (%r10)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28Action_noImage_no_center_GPUPdS_S_diiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii, .Lfunc_end1-_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii # -- Begin function _Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.type	_Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii,@function
_Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii: # @_Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	24(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii, .Lfunc_end2-_Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii # -- Begin function _Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.type	_Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii,@function
_Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii: # @_Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	24(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii, .Lfunc_end3-_Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii # -- Begin function _Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.type	_Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii,@function
_Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii: # @_Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii, .Lfunc_end4-_Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii # -- Begin function _Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.type	_Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii,@function
_Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii: # @_Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii, .Lfunc_end5-_Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25Action_noImage_center_GPUPdS_S_diii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28Action_noImage_no_center_GPUPdS_S_diiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25Action_noImage_center_GPUPdS_S_diii,@object # @_Z25Action_noImage_center_GPUPdS_S_diii
	.section	.rodata,"a",@progbits
	.globl	_Z25Action_noImage_center_GPUPdS_S_diii
	.p2align	3, 0x0
_Z25Action_noImage_center_GPUPdS_S_diii:
	.quad	_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
	.size	_Z25Action_noImage_center_GPUPdS_S_diii, 8

	.type	_Z28Action_noImage_no_center_GPUPdS_S_diiii,@object # @_Z28Action_noImage_no_center_GPUPdS_S_diiii
	.globl	_Z28Action_noImage_no_center_GPUPdS_S_diiii
	.p2align	3, 0x0
_Z28Action_noImage_no_center_GPUPdS_S_diiii:
	.quad	_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
	.size	_Z28Action_noImage_no_center_GPUPdS_S_diiii, 8

	.type	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii,@object # @_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.globl	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.p2align	3, 0x0
_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii:
	.quad	_Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.size	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii, 8

	.type	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii,@object # @_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.globl	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.p2align	3, 0x0
_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii:
	.quad	_Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.size	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii, 8

	.type	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii,@object # @_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.globl	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.p2align	3, 0x0
_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii:
	.quad	_Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.size	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii, 8

	.type	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii,@object # @_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.globl	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.p2align	3, 0x0
_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii:
	.quad	_Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.size	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z25Action_noImage_center_GPUPdS_S_diii"
	.size	.L__unnamed_1, 40

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z28Action_noImage_no_center_GPUPdS_S_diiii"
	.size	.L__unnamed_2, 44

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii"
	.size	.L__unnamed_3, 45

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii"
	.size	.L__unnamed_4, 49

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii"
	.size	.L__unnamed_5, 50

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii"
	.size	.L__unnamed_6, 54

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
	.addrsig_sym _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
	.addrsig_sym _Z43__device_stub__Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.addrsig_sym _Z46__device_stub__Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.addrsig_sym _Z46__device_stub__Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.addrsig_sym _Z49__device_stub__Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25Action_noImage_center_GPUPdS_S_diii
	.addrsig_sym _Z28Action_noImage_no_center_GPUPdS_S_diiii
	.addrsig_sym _Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.addrsig_sym _Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.addrsig_sym _Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.addrsig_sym _Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25Action_noImage_center_GPUPdS_S_diii ; -- Begin function _Z25Action_noImage_center_GPUPdS_S_diii
	.globl	_Z25Action_noImage_center_GPUPdS_S_diii
	.p2align	8
	.type	_Z25Action_noImage_center_GPUPdS_S_diii,@function
_Z25Action_noImage_center_GPUPdS_S_diii: ; @_Z25Action_noImage_center_GPUPdS_S_diii
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x20
	v_lshl_add_u32 v0, s15, 9, v0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v0
	s_cbranch_execz .LBB0_5
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	s_cmp_lt_i32 s9, 1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	s_mul_i32 s12, s9, 3
	s_clause 0x1
	s_load_b128 s[8:11], s[2:3], 0x0
	s_load_b64 s[2:3], s[2:3], 0x10
	v_mul_lo_u32 v1, s12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, s4
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v1, 8
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	global_load_b128 v[6:9], v[4:5], off offset:-8
	global_load_b64 v[10:11], v[4:5], off offset:8
	v_max_f64 v[1:2], v[2:3], v[2:3]
	v_add_co_u32 v4, vcc_lo, v4, 24
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s4, s4, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s4, s12
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_f64 v[8:9], s[10:11], -v[8:9]
	v_add_f64 v[6:7], s[8:9], -v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], s[2:3], -v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], v[8:9]
	v_fma_f64 v[6:7], v[6:7], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], v[10:11], v[6:7]
	v_min_f64 v[2:3], v[1:2], v[6:7]
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %Flow59
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25Action_noImage_center_GPUPdS_S_diii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25Action_noImage_center_GPUPdS_S_diii, .Lfunc_end0-_Z25Action_noImage_center_GPUPdS_S_diii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28Action_noImage_no_center_GPUPdS_S_diiii ; -- Begin function _Z28Action_noImage_no_center_GPUPdS_S_diiii
	.globl	_Z28Action_noImage_no_center_GPUPdS_S_diiii
	.p2align	8
	.type	_Z28Action_noImage_no_center_GPUPdS_S_diiii,@function
_Z28Action_noImage_no_center_GPUPdS_S_diiii: ; @_Z28Action_noImage_no_center_GPUPdS_S_diiii
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x20
	s_mov_b32 s13, 1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s10, 3
	s_cmp_lt_i32 s10, 4
	s_mov_b32 s10, s12
	s_cbranch_scc1 .LBB1_2
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], s12
	s_mov_b32 s10, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[3:4], null, 0x40220000, 0x40220000, v[1:2]
	v_rcp_f64_e32 v[5:6], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_div_scale_f64 v[7:8], vcc_lo, v[1:2], 0x40220000, v[1:2]
	v_mul_f64 v[9:10], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], -v[3:4], v[9:10], v[7:8]
	v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[1:2], v[3:4], 0x40220000, v[1:2]
	v_ceil_f64_e32 v[1:2], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v1, v[1:2]
	v_readfirstlane_b32 s13, v1
.LBB1_2:
	v_mad_u64_u32 v[7:8], null, s15, s11, v[0:1]
	s_mul_i32 s2, s9, s8
	v_cmp_gt_u32_e32 vcc_lo, s11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s2, v7
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_14
; %bb.3:
	s_load_b256 s[0:7], s[0:1], 0x0
	s_cmp_lt_i32 s13, 1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s7
	s_cbranch_scc1 .LBB1_10
; %bb.4:                                ; %.preheader79.preheader
	v_lshl_add_u32 v1, v7, 1, v7
	v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s7
	s_add_u32 s8, s4, 8
	s_addc_u32 s11, s5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s6, s10
	s_mov_b32 s7, 0
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_mov_b32 s2, 0
	s_clause 0x1
	global_load_b64 v[8:9], v[1:2], off offset:16
	global_load_b128 v[1:4], v[1:2], off
.LBB1_5:                                ; %.preheader79
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
	s_cmp_ge_i32 s2, s6
	s_cbranch_scc1 .LBB1_8
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[2:3], 3
	s_add_u32 s4, s8, s4
	s_addc_u32 s5, s11, s5
.LBB1_7:                                ; %.lr.ph
                                        ;   Parent Loop BB1_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_u32 s14, s4, -8
	s_addc_u32 s15, s5, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_max_f64 v[5:6], v[5:6], v[5:6]
	s_clause 0x1
	s_load_b128 s[16:19], s[14:15], 0x0
	s_load_b64 s[14:15], s[4:5], 0x8
	s_add_i32 s2, s2, 3
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lt_i32 s2, s6
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[10:11], s[18:19], -v[3:4]
	v_add_f64 v[12:13], s[16:17], -v[1:2]
	v_add_f64 v[14:15], s[14:15], -v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[10:11], v[10:11]
	v_fma_f64 v[10:11], v[12:13], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[14:15], v[14:15], v[10:11]
	v_min_f64 v[5:6], v[5:6], v[10:11]
	s_cbranch_scc1 .LBB1_7
.LBB1_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_add_i32 s2, s6, s10
	s_add_i32 s7, s7, 1
	s_min_i32 s3, s2, s12
	s_cmp_lg_u32 s7, s13
	s_cbranch_scc0 .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_5 Depth=1
	s_mov_b32 s2, s6
	s_mov_b32 s6, s3
	s_branch .LBB1_5
.LBB1_10:                               ; %._crit_edge86
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v1, s9
	s_sub_i32 s2, 0, s9
	v_lshlrev_b32_e32 v0, 3, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v1, v1
	ds_store_b64 v0, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v7, v1
	v_mul_lo_u32 v2, v1, s9
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v7, v2
	v_subrev_nc_u32_e32 v4, s9, v2
	v_cmp_le_u32_e32 vcc_lo, s9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
	v_cmp_le_u32_e32 vcc_lo, s9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v1, s9
	v_cmp_eq_u32_e32 vcc_lo, v7, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_14
; %bb.11:                               ; %.preheader
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB1_13
.LBB1_12:                               ; %.lr.ph90
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[2:3], v0
	v_max_f64 v[4:5], v[5:6], v[5:6]
	v_add_nc_u32_e32 v0, 8, v0
	s_add_i32 s9, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s9, 0
	s_waitcnt lgkmcnt(0)
	v_max_f64 v[2:3], v[2:3], v[2:3]
	v_min_f64 v[5:6], v[4:5], v[2:3]
	s_cbranch_scc1 .LBB1_12
.LBB1_13:                               ; %._crit_edge91
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[5:6], off
.LBB1_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28Action_noImage_no_center_GPUPdS_S_diiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z28Action_noImage_no_center_GPUPdS_S_diiii, .Lfunc_end1-_Z28Action_noImage_no_center_GPUPdS_S_diiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 820
; NumSgprs: 22
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii ; -- Begin function _Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.globl	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
	.p2align	8
	.type	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii,@function
_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii: ; @_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x28
	v_lshl_add_u32 v4, s15, 9, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v4
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_17
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	s_cmp_lt_i32 s3, 1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	s_cbranch_scc1 .LBB2_16
; %bb.2:                                ; %.lr.ph111
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[20:21], s[0:1], 0x10
	s_clause 0x1
	s_load_b128 s[16:19], s[6:7], 0x0
	s_load_b64 s[6:7], s[6:7], 0x10
	v_mul_lo_u32 v0, v4, s3
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v8, v0, 1, v0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f64_e64 s0, s[12:13], 0
	v_cmp_eq_f64_e64 s1, s[14:15], 0
	v_cmp_eq_f64_e64 s2, s[20:21], 0
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s0, s2
	s_mov_b32 s2, 0
.LBB2_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_5 Depth 2
                                        ;     Child Loop BB2_9 Depth 2
                                        ;     Child Loop BB2_13 Depth 2
	v_ashrrev_i32_e32 v9, 31, v8
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[8:9]
	v_add_co_u32 v9, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v1, vcc_lo
	s_clause 0x1
	global_load_b128 v[0:3], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], s[16:17], -v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[0:1]
	v_xor_b32_e32 v5, 0x80000000, v1
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f64_e32 s[12:13], v[0:1]
	s_cbranch_execz .LBB2_7
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_mov_b32 s10, 0
.LBB2_5:                                ; %.lr.ph
                                        ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_f64 v[0:1], v[0:1], -s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[12:13], v[0:1]
	s_or_b32 s10, vcc_lo, s10
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_5
; %bb.6:                                ; %Flow155
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB2_7:                                ; %Flow156
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[2:3], s[18:19], -v[2:3]
	s_mov_b32 s0, exec_lo
	v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
	v_xor_b32_e32 v5, 0x80000000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v2
	v_cmpx_lt_f64_e32 s[14:15], v[2:3]
	s_cbranch_execz .LBB2_11
; %bb.8:                                ; %.lr.ph100.preheader
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_mov_b32 s10, 0
.LBB2_9:                                ; %.lr.ph100
                                        ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_f64 v[2:3], v[2:3], -s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[14:15], v[2:3]
	s_or_b32 s10, vcc_lo, s10
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_9
; %bb.10:                               ; %Flow153
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB2_11:                               ; %Flow154
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f64 v[9:10], s[6:7], -v[9:10]
	s_mov_b32 s0, exec_lo
	v_cmp_gt_f64_e32 vcc_lo, 0, v[9:10]
	v_xor_b32_e32 v5, 0x80000000, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v5, vcc_lo
	v_cndmask_b32_e32 v9, v9, v9, vcc_lo
	v_cmpx_lt_f64_e32 s[20:21], v[9:10]
	s_cbranch_execz .LBB2_15
; %bb.12:                               ; %.lr.ph104.preheader
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_mov_b32 s10, 0
.LBB2_13:                               ; %.lr.ph104
                                        ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_f64 v[9:10], v[9:10], -s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[20:21], v[9:10]
	s_or_b32 s10, vcc_lo, s10
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_13
; %bb.14:                               ; %Flow
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB2_15:                               ; %Flow152
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[11:12], s[14:15], -v[2:3]
	v_add_f64 v[13:14], s[12:13], -v[0:1]
	v_add_f64 v[15:16], s[20:21], -v[9:10]
	v_add_nc_u32_e32 v8, 3, v8
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	s_cmp_eq_u32 s2, s3
	v_cmp_lt_f64_e32 vcc_lo, v[11:12], v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f64_e64 s0, v[13:14], v[0:1]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_cndmask_b32_e64 v1, v1, v14, s0
	v_cndmask_b32_e64 v0, v0, v13, s0
	v_cmp_lt_f64_e32 vcc_lo, v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[2:3]
	v_fma_f64 v[0:1], v[0:1], v[0:1], v[2:3]
	v_dual_cndmask_b32 v3, v10, v16 :: v_dual_cndmask_b32 v2, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[2:3], v[2:3], v[0:1]
	v_max_f64 v[2:3], v[6:7], v[6:7]
	v_cndmask_b32_e64 v1, v1, 0xbff00000, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, 0, s1
	v_min_f64 v[6:7], v[2:3], v[0:1]
	s_cbranch_scc0 .LBB2_3
.LBB2_16:                               ; %Flow158
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[0:1], v[6:7], off
.LBB2_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 52
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii, .Lfunc_end2-_Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 736
; NumSgprs: 24
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii ; -- Begin function _Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.globl	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
	.p2align	8
	.type	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii,@function
_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii: ; @_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x28
	s_mov_b32 s23, 1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s22, s18, 3
	s_cmp_lt_i32 s18, 4
	s_mov_b32 s24, s22
	s_cbranch_scc1 .LBB3_2
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], s22
	s_mov_b32 s24, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[3:4], null, 0x40220000, 0x40220000, v[1:2]
	v_rcp_f64_e32 v[5:6], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_div_scale_f64 v[7:8], vcc_lo, v[1:2], 0x40220000, v[1:2]
	v_mul_f64 v[9:10], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], -v[3:4], v[9:10], v[7:8]
	v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[1:2], v[3:4], 0x40220000, v[1:2]
	v_ceil_f64_e32 v[1:2], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v1, v[1:2]
	v_readfirstlane_b32 s23, v1
.LBB3_2:
	v_mad_u64_u32 v[5:6], null, s15, s19, v[0:1]
	s_mul_i32 s2, s17, s16
	v_cmp_gt_u32_e32 vcc_lo, s19, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s2, v5
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_26
; %bb.3:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[18:19], s[0:1], 0x20
	s_cmp_lt_i32 s23, 1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	s_cbranch_scc1 .LBB3_22
; %bb.4:                                ; %.preheader142.lr.ph
	v_lshl_add_u32 v1, v5, 1, v5
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
	s_mov_b32 s16, s24
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	s_mov_b32 s6, 0
	s_clause 0x1
	global_load_b64 v[8:9], v[1:2], off offset:16
	global_load_b128 v[1:4], v[1:2], off
.LBB3_5:                                ; %.preheader142
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_7 Depth 2
                                        ;       Child Loop BB3_9 Depth 3
                                        ;       Child Loop BB3_13 Depth 3
                                        ;       Child Loop BB3_17 Depth 3
	s_cmp_ge_i32 s6, s16
	s_cbranch_scc1 .LBB3_20
; %bb.6:                                ; %.lr.ph157
                                        ;   in Loop: Header=BB3_5 Depth=1
	s_clause 0x1
	s_load_b128 s[12:15], s[18:19], 0x0
	s_load_b64 s[10:11], s[18:19], 0x10
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f64_e64 s0, s[12:13], 0
	v_cmp_eq_f64_e64 s1, s[14:15], 0
	v_cmp_eq_f64_e64 s2, s[10:11], 0
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s26, s0, s2
.LBB3_7:                                ;   Parent Loop BB3_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_9 Depth 3
                                        ;       Child Loop BB3_13 Depth 3
                                        ;       Child Loop BB3_17 Depth 3
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[6:7], 3
	s_add_u32 s20, s8, s0
	s_addc_u32 s21, s9, s1
	s_clause 0x1
	s_load_b128 s[0:3], s[20:21], 0x0
	s_load_b64 s[20:21], s[20:21], 0x10
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[10:11], s[0:1], -v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
	v_xor_b32_e32 v12, 0x80000000, v11
	v_dual_cndmask_b32 v11, v11, v12 :: v_dual_cndmask_b32 v10, v10, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f64_e32 s[12:13], v[10:11]
	s_cbranch_execz .LBB3_11
; %bb.8:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_mov_b32 s1, 0
.LBB3_9:                                ; %.lr.ph
                                        ;   Parent Loop BB3_5 Depth=1
                                        ;     Parent Loop BB3_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_f64 v[10:11], v[10:11], -s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[12:13], v[10:11]
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_9
; %bb.10:                               ; %Flow230
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_11:                               ; %Flow231
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[12:13], s[2:3], -v[3:4]
	s_mov_b32 s0, exec_lo
	v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
	v_xor_b32_e32 v14, 0x80000000, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v13, v13, v14 :: v_dual_cndmask_b32 v12, v12, v12
	v_cmpx_lt_f64_e32 s[14:15], v[12:13]
	s_cbranch_execz .LBB3_15
; %bb.12:                               ; %.lr.ph148.preheader
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_mov_b32 s1, 0
.LBB3_13:                               ; %.lr.ph148
                                        ;   Parent Loop BB3_5 Depth=1
                                        ;     Parent Loop BB3_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_f64 v[12:13], v[12:13], -s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[14:15], v[12:13]
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_13
; %bb.14:                               ; %Flow228
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_15:                               ; %Flow229
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[14:15], s[20:21], -v[8:9]
	s_mov_b32 s0, exec_lo
	v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
	v_xor_b32_e32 v16, 0x80000000, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v15, v15, v16 :: v_dual_cndmask_b32 v14, v14, v14
	v_cmpx_lt_f64_e32 s[10:11], v[14:15]
	s_cbranch_execz .LBB3_19
; %bb.16:                               ; %.lr.ph152.preheader
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_mov_b32 s1, 0
.LBB3_17:                               ; %.lr.ph152
                                        ;   Parent Loop BB3_5 Depth=1
                                        ;     Parent Loop BB3_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_f64 v[14:15], v[14:15], -s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nlt_f64_e32 vcc_lo, s[10:11], v[14:15]
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_17
; %bb.18:                               ; %Flow226
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_19:                               ; %Flow227
                                        ;   in Loop: Header=BB3_7 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[16:17], s[14:15], -v[12:13]
	v_add_f64 v[18:19], s[12:13], -v[10:11]
	v_add_f64 v[20:21], s[10:11], -v[14:15]
	v_max_f64 v[6:7], v[6:7], v[6:7]
	s_add_i32 s6, s6, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	s_cmp_lt_i32 s6, s16
	v_cmp_lt_f64_e32 vcc_lo, v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f64_e64 s0, v[18:19], v[10:11]
	v_dual_cndmask_b32 v13, v13, v17 :: v_dual_cndmask_b32 v12, v12, v16
	v_cndmask_b32_e64 v11, v11, v19, s0
	v_cndmask_b32_e64 v10, v10, v18, s0
	v_cmp_lt_f64_e32 vcc_lo, v[20:21], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[12:13], v[12:13]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[12:13]
	v_dual_cndmask_b32 v13, v15, v21 :: v_dual_cndmask_b32 v12, v14, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[12:13], v[12:13], v[10:11]
	v_cndmask_b32_e64 v11, v11, 0xbff00000, s26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v10, 0, s26
	v_min_f64 v[6:7], v[6:7], v[10:11]
	s_cbranch_scc1 .LBB3_7
.LBB3_20:                               ; %._crit_edge158
                                        ;   in Loop: Header=BB3_5 Depth=1
	s_add_i32 s0, s16, s24
	s_add_i32 s25, s25, 1
	s_min_i32 s0, s0, s22
	s_cmp_lg_u32 s25, s23
	s_cbranch_scc0 .LBB3_22
; %bb.21:                               ;   in Loop: Header=BB3_5 Depth=1
	s_mov_b32 s6, s16
	s_mov_b32 s16, s0
	s_branch .LBB3_5
.LBB3_22:                               ; %._crit_edge164
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v1, s17
	s_sub_i32 s0, 0, s17
	v_lshlrev_b32_e32 v0, 3, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v1, v1
	ds_store_b64 v0, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v5, v1
	v_mul_lo_u32 v2, v1, s17
	v_add_nc_u32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v5, v2
	v_subrev_nc_u32_e32 v4, s17, v2
	v_cmp_le_u32_e32 vcc_lo, s17, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
	v_cmp_le_u32_e32 vcc_lo, s17, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v1, s17
	v_cmp_eq_u32_e32 vcc_lo, v5, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_26
; %bb.23:                               ; %.preheader
	s_cmp_lt_i32 s17, 1
	s_cbranch_scc1 .LBB3_25
.LBB3_24:                               ; %.lr.ph168
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[2:3], v0
	v_max_f64 v[4:5], v[6:7], v[6:7]
	v_add_nc_u32_e32 v0, 8, v0
	s_add_i32 s17, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s17, 0
	s_waitcnt lgkmcnt(0)
	v_max_f64 v[2:3], v[2:3], v[2:3]
	v_min_f64 v[6:7], v[4:5], v[2:3]
	s_cbranch_scc1 .LBB3_24
.LBB3_25:                               ; %._crit_edge169
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[0:1], v[6:7], off
.LBB3_26:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii, .Lfunc_end3-_Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1216
; NumSgprs: 29
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function _Z13NonOrtho_distddddddPd
	.type	_Z13NonOrtho_distddddddPd,@function
_Z13NonOrtho_distddddddPd:              ; @_Z13NonOrtho_distddddddPd
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_clause 0x4
	flat_load_b128 v[52:55], v[12:13] offset:32
	flat_load_b128 v[18:21], v[12:13] offset:16
	flat_load_b128 v[22:25], v[12:13]
	flat_load_b128 v[14:17], v[12:13] offset:48
	flat_load_b64 v[12:13], v[12:13] offset:64
	v_floor_f64_e32 v[26:27], v[2:3]
	v_floor_f64_e32 v[28:29], v[0:1]
	v_floor_f64_e32 v[30:31], v[8:9]
	v_floor_f64_e32 v[34:35], v[10:11]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[32:33], v[2:3], -v[26:27]
	v_floor_f64_e32 v[2:3], v[4:5]
	v_floor_f64_e32 v[26:27], v[6:7]
	v_add_f64 v[50:51], v[0:1], -v[28:29]
	v_add_f64 v[8:9], v[8:9], -v[30:31]
	v_add_f64 v[38:39], v[10:11], -v[34:35]
	v_add_f64 v[30:31], v[32:33], -1.0
	v_add_f64 v[0:1], v[4:5], -v[2:3]
	v_add_f64 v[4:5], v[6:7], -v[26:27]
	v_add_f64 v[64:65], v[50:51], -1.0
	v_add_f64 v[128:129], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[2:3], v[0:1], -1.0
	s_waitcnt vmcnt(4) lgkmcnt(4)
	v_mul_f64 v[6:7], v[8:9], v[52:53]
	v_mul_f64 v[28:29], v[32:33], v[52:53]
	v_mul_f64 v[36:37], v[30:31], v[52:53]
	s_waitcnt vmcnt(3) lgkmcnt(3)
	v_mul_f64 v[10:11], v[8:9], v[20:21]
	v_mul_f64 v[26:27], v[32:33], v[20:21]
	v_mul_f64 v[34:35], v[30:31], v[20:21]
	v_mul_f64 v[8:9], v[8:9], v[54:55]
	v_mul_f64 v[48:49], v[30:31], v[54:55]
	v_mul_f64 v[30:31], v[32:33], v[54:55]
	v_mul_f64 v[32:33], v[128:129], v[52:53]
	v_mul_f64 v[20:21], v[128:129], v[20:21]
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_fma_f64 v[6:7], v[4:5], v[24:25], v[6:7]
	v_fma_f64 v[66:67], v[50:51], v[24:25], v[28:29]
	v_fma_f64 v[68:69], v[64:65], v[24:25], v[36:37]
	v_fma_f64 v[10:11], v[4:5], v[22:23], v[10:11]
	v_fma_f64 v[70:71], v[50:51], v[22:23], v[26:27]
	v_fma_f64 v[80:81], v[64:65], v[22:23], v[34:35]
	v_fma_f64 v[8:9], v[4:5], v[18:19], v[8:9]
	v_fma_f64 v[96:97], v[64:65], v[18:19], v[48:49]
	v_fma_f64 v[86:87], v[50:51], v[18:19], v[30:31]
	v_fma_f64 v[116:117], v[64:65], v[24:25], v[28:29]
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_fma_f64 v[6:7], v[38:39], v[16:17], v[6:7]
	v_fma_f64 v[82:83], v[0:1], v[16:17], v[66:67]
	v_fma_f64 v[84:85], v[2:3], v[16:17], v[68:69]
	v_fma_f64 v[4:5], v[38:39], v[14:15], v[10:11]
	v_fma_f64 v[98:99], v[0:1], v[14:15], v[70:71]
	v_fma_f64 v[100:101], v[2:3], v[14:15], v[80:81]
	v_fma_f64 v[102:103], v[0:1], v[16:17], v[68:69]
	v_add_f64 v[10:11], v[0:1], 1.0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[8:9], v[38:39], v[12:13], v[8:9]
	v_fma_f64 v[38:39], v[0:1], v[12:13], v[86:87]
	v_fma_f64 v[112:113], v[2:3], v[12:13], v[96:97]
	v_fma_f64 v[114:115], v[0:1], v[14:15], v[80:81]
	v_fma_f64 v[118:119], v[2:3], v[16:17], v[116:117]
	v_add_f64 v[82:83], v[82:83], -v[6:7]
	v_add_f64 v[84:85], v[84:85], -v[6:7]
	v_add_f64 v[98:99], v[98:99], -v[4:5]
	v_add_f64 v[100:101], v[100:101], -v[4:5]
	v_add_f64 v[102:103], v[102:103], -v[6:7]
	v_fma_f64 v[68:69], v[10:11], v[16:17], v[68:69]
	v_fma_f64 v[80:81], v[10:11], v[14:15], v[80:81]
	v_add_f64 v[38:39], v[38:39], -v[8:9]
	v_add_f64 v[112:113], v[112:113], -v[8:9]
	v_mul_f64 v[82:83], v[82:83], v[82:83]
	v_mul_f64 v[84:85], v[84:85], v[84:85]
	v_mul_f64 v[102:103], v[102:103], v[102:103]
	v_add_f64 v[68:69], v[68:69], -v[6:7]
	v_add_f64 v[80:81], v[80:81], -v[4:5]
	v_fma_f64 v[82:83], v[98:99], v[98:99], v[82:83]
	v_fma_f64 v[84:85], v[100:101], v[100:101], v[84:85]
	v_fma_f64 v[98:99], v[0:1], v[12:13], v[96:97]
	v_add_f64 v[100:101], v[114:115], -v[4:5]
	v_fma_f64 v[114:115], v[64:65], v[22:23], v[26:27]
	v_fma_f64 v[96:97], v[10:11], v[12:13], v[96:97]
	v_mul_f64 v[68:69], v[68:69], v[68:69]
	v_fma_f64 v[38:39], v[38:39], v[38:39], v[82:83]
	v_fma_f64 v[82:83], v[112:113], v[112:113], v[84:85]
	v_add_f64 v[84:85], v[98:99], -v[8:9]
	v_fma_f64 v[98:99], v[100:101], v[100:101], v[102:103]
	v_fma_f64 v[100:101], v[2:3], v[14:15], v[114:115]
	v_fma_f64 v[102:103], v[64:65], v[18:19], v[30:31]
	v_add_f64 v[112:113], v[118:119], -v[6:7]
	v_fma_f64 v[118:119], v[0:1], v[16:17], v[116:117]
	v_fma_f64 v[68:69], v[80:81], v[80:81], v[68:69]
	v_fma_f64 v[116:117], v[10:11], v[16:17], v[116:117]
	v_cmp_lt_f64_e32 vcc_lo, v[82:83], v[38:39]
	v_fma_f64 v[52:53], v[84:85], v[84:85], v[98:99]
	v_add_f64 v[84:85], v[96:97], -v[8:9]
	v_add_f64 v[80:81], v[100:101], -v[4:5]
	v_fma_f64 v[96:97], v[2:3], v[12:13], v[102:103]
	v_mul_f64 v[98:99], v[112:113], v[112:113]
	v_fma_f64 v[100:101], v[0:1], v[14:15], v[114:115]
	v_add_f64 v[112:113], v[118:119], -v[6:7]
	v_fma_f64 v[118:119], v[64:65], v[24:25], v[32:33]
	v_dual_cndmask_b32 v83, v39, v83 :: v_dual_cndmask_b32 v82, v38, v82
	v_mul_f64 v[38:39], v[128:129], v[54:55]
	v_fma_f64 v[68:69], v[84:85], v[84:85], v[68:69]
	v_add_f64 v[84:85], v[96:97], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_lt_f64_e32 vcc_lo, v[52:53], v[82:83]
	v_fma_f64 v[80:81], v[80:81], v[80:81], v[98:99]
	v_add_f64 v[96:97], v[100:101], -v[4:5]
	v_fma_f64 v[98:99], v[0:1], v[12:13], v[102:103]
	v_mul_f64 v[100:101], v[112:113], v[112:113]
	v_fma_f64 v[112:113], v[10:11], v[14:15], v[114:115]
	v_add_f64 v[114:115], v[116:117], -v[6:7]
	v_fma_f64 v[116:117], v[64:65], v[22:23], v[20:21]
	v_fma_f64 v[54:55], v[2:3], v[16:17], v[118:119]
	v_fma_f64 v[64:65], v[64:65], v[18:19], v[38:39]
	v_dual_cndmask_b32 v53, v83, v53 :: v_dual_cndmask_b32 v52, v82, v52
	v_fma_f64 v[80:81], v[84:85], v[84:85], v[80:81]
	v_add_f64 v[82:83], v[98:99], -v[8:9]
	v_fma_f64 v[84:85], v[96:97], v[96:97], v[100:101]
	v_add_f64 v[96:97], v[112:113], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[68:69], v[52:53]
	v_fma_f64 v[98:99], v[10:11], v[12:13], v[102:103]
	v_mul_f64 v[100:101], v[114:115], v[114:115]
	v_fma_f64 v[102:103], v[2:3], v[14:15], v[116:117]
	v_add_f64 v[54:55], v[54:55], -v[6:7]
	v_fma_f64 v[112:113], v[0:1], v[16:17], v[118:119]
	v_fma_f64 v[114:115], v[50:51], v[24:25], v[36:37]
	v_dual_cndmask_b32 v53, v53, v69 :: v_dual_cndmask_b32 v52, v52, v68
	v_fma_f64 v[68:69], v[82:83], v[82:83], v[84:85]
	v_add_f64 v[82:83], v[98:99], -v[8:9]
	v_fma_f64 v[84:85], v[96:97], v[96:97], v[100:101]
	v_add_f64 v[96:97], v[102:103], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[80:81], v[52:53]
	v_fma_f64 v[98:99], v[2:3], v[12:13], v[64:65]
	v_mul_f64 v[54:55], v[54:55], v[54:55]
	v_fma_f64 v[100:101], v[0:1], v[14:15], v[116:117]
	v_add_f64 v[102:103], v[112:113], -v[6:7]
	v_fma_f64 v[112:113], v[10:11], v[16:17], v[118:119]
	v_dual_cndmask_b32 v53, v53, v81 :: v_dual_cndmask_b32 v52, v52, v80
	v_fma_f64 v[80:81], v[82:83], v[82:83], v[84:85]
	v_add_f64 v[82:83], v[98:99], -v[8:9]
	v_fma_f64 v[54:55], v[96:97], v[96:97], v[54:55]
	v_add_f64 v[84:85], v[100:101], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[68:69], v[52:53]
	v_fma_f64 v[96:97], v[0:1], v[12:13], v[64:65]
	v_mul_f64 v[98:99], v[102:103], v[102:103]
	v_fma_f64 v[100:101], v[10:11], v[14:15], v[116:117]
	v_add_f64 v[102:103], v[112:113], -v[6:7]
	v_fma_f64 v[112:113], v[50:51], v[22:23], v[34:35]
	v_fma_f64 v[116:117], v[2:3], v[16:17], v[114:115]
	v_fma_f64 v[64:65], v[10:11], v[12:13], v[64:65]
	v_fma_f64 v[54:55], v[82:83], v[82:83], v[54:55]
	v_dual_cndmask_b32 v53, v53, v69 :: v_dual_cndmask_b32 v52, v52, v68
	v_add_f64 v[68:69], v[96:97], -v[8:9]
	v_fma_f64 v[82:83], v[84:85], v[84:85], v[98:99]
	v_add_f64 v[84:85], v[100:101], -v[4:5]
	v_mul_f64 v[96:97], v[102:103], v[102:103]
	v_cmp_lt_f64_e32 vcc_lo, v[80:81], v[52:53]
	v_fma_f64 v[98:99], v[2:3], v[14:15], v[112:113]
	v_fma_f64 v[100:101], v[50:51], v[18:19], v[48:49]
	v_add_f64 v[102:103], v[116:117], -v[6:7]
	v_fma_f64 v[116:117], v[0:1], v[16:17], v[114:115]
	v_add_f64 v[64:65], v[64:65], -v[8:9]
	v_fma_f64 v[114:115], v[10:11], v[16:17], v[114:115]
	v_fma_f64 v[68:69], v[68:69], v[68:69], v[82:83]
	v_dual_cndmask_b32 v53, v53, v81 :: v_dual_cndmask_b32 v52, v52, v80
	v_fma_f64 v[80:81], v[84:85], v[84:85], v[96:97]
	v_add_f64 v[82:83], v[98:99], -v[4:5]
	v_fma_f64 v[84:85], v[2:3], v[12:13], v[100:101]
	v_mul_f64 v[96:97], v[102:103], v[102:103]
	v_cmp_lt_f64_e32 vcc_lo, v[54:55], v[52:53]
	v_fma_f64 v[98:99], v[0:1], v[14:15], v[112:113]
	v_add_f64 v[102:103], v[116:117], -v[6:7]
	v_dual_cndmask_b32 v53, v53, v55 :: v_dual_cndmask_b32 v52, v52, v54
	v_fma_f64 v[54:55], v[64:65], v[64:65], v[80:81]
	v_add_f64 v[64:65], v[84:85], -v[8:9]
	v_fma_f64 v[80:81], v[82:83], v[82:83], v[96:97]
	v_add_f64 v[82:83], v[98:99], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[68:69], v[52:53]
	v_fma_f64 v[84:85], v[0:1], v[12:13], v[100:101]
	v_mul_f64 v[96:97], v[102:103], v[102:103]
	v_fma_f64 v[98:99], v[10:11], v[14:15], v[112:113]
	v_add_f64 v[102:103], v[114:115], -v[6:7]
	v_fma_f64 v[112:113], v[2:3], v[16:17], v[66:67]
	v_fma_f64 v[66:67], v[10:11], v[16:17], v[66:67]
	v_fma_f64 v[64:65], v[64:65], v[64:65], v[80:81]
	v_dual_cndmask_b32 v53, v53, v69 :: v_dual_cndmask_b32 v52, v52, v68
	v_add_f64 v[68:69], v[84:85], -v[8:9]
	v_fma_f64 v[80:81], v[82:83], v[82:83], v[96:97]
	v_add_f64 v[82:83], v[98:99], -v[4:5]
	v_fma_f64 v[84:85], v[10:11], v[12:13], v[100:101]
	v_cmp_lt_f64_e32 vcc_lo, v[54:55], v[52:53]
	v_mul_f64 v[96:97], v[102:103], v[102:103]
	v_fma_f64 v[98:99], v[2:3], v[14:15], v[70:71]
	v_add_f64 v[100:101], v[112:113], -v[6:7]
	v_fma_f64 v[102:103], v[50:51], v[24:25], v[32:33]
	v_fma_f64 v[70:71], v[10:11], v[14:15], v[70:71]
	v_add_f64 v[66:67], v[66:67], -v[6:7]
	v_dual_cndmask_b32 v53, v53, v55 :: v_dual_cndmask_b32 v52, v52, v54
	v_fma_f64 v[54:55], v[68:69], v[68:69], v[80:81]
	v_add_f64 v[68:69], v[84:85], -v[8:9]
	v_fma_f64 v[80:81], v[82:83], v[82:83], v[96:97]
	v_add_f64 v[82:83], v[98:99], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[64:65], v[52:53]
	v_fma_f64 v[84:85], v[2:3], v[12:13], v[86:87]
	v_mul_f64 v[96:97], v[100:101], v[100:101]
	v_fma_f64 v[98:99], v[50:51], v[22:23], v[20:21]
	v_fma_f64 v[100:101], v[2:3], v[16:17], v[102:103]
	v_add_f64 v[70:71], v[70:71], -v[4:5]
	v_mul_f64 v[66:67], v[66:67], v[66:67]
	v_dual_cndmask_b32 v53, v53, v65 :: v_dual_cndmask_b32 v52, v52, v64
	v_fma_f64 v[64:65], v[68:69], v[68:69], v[80:81]
	v_add_f64 v[68:69], v[84:85], -v[8:9]
	v_fma_f64 v[80:81], v[82:83], v[82:83], v[96:97]
	v_fma_f64 v[82:83], v[10:11], v[12:13], v[86:87]
	v_cmp_lt_f64_e32 vcc_lo, v[54:55], v[52:53]
	v_fma_f64 v[84:85], v[2:3], v[14:15], v[98:99]
	v_fma_f64 v[86:87], v[50:51], v[18:19], v[38:39]
	v_add_f64 v[96:97], v[100:101], -v[6:7]
	v_fma_f64 v[100:101], v[0:1], v[16:17], v[102:103]
	v_add_f64 v[50:51], v[50:51], 1.0
	v_fma_f64 v[66:67], v[70:71], v[70:71], v[66:67]
	v_dual_cndmask_b32 v53, v53, v55 :: v_dual_cndmask_b32 v52, v52, v54
	v_fma_f64 v[54:55], v[68:69], v[68:69], v[80:81]
	v_add_f64 v[68:69], v[82:83], -v[8:9]
	v_add_f64 v[70:71], v[84:85], -v[4:5]
	v_fma_f64 v[80:81], v[2:3], v[12:13], v[86:87]
	v_cmp_lt_f64_e32 vcc_lo, v[64:65], v[52:53]
	v_mul_f64 v[82:83], v[96:97], v[96:97]
	v_fma_f64 v[84:85], v[0:1], v[14:15], v[98:99]
	v_add_f64 v[96:97], v[100:101], -v[6:7]
	v_fma_f64 v[100:101], v[10:11], v[16:17], v[102:103]
	v_fma_f64 v[36:37], v[50:51], v[24:25], v[36:37]
	v_fma_f64 v[34:35], v[50:51], v[22:23], v[34:35]
	v_fma_f64 v[48:49], v[50:51], v[18:19], v[48:49]
	v_fma_f64 v[28:29], v[50:51], v[24:25], v[28:29]
	v_fma_f64 v[26:27], v[50:51], v[22:23], v[26:27]
	v_fma_f64 v[30:31], v[50:51], v[18:19], v[30:31]
	v_fma_f64 v[24:25], v[50:51], v[24:25], v[32:33]
	v_fma_f64 v[20:21], v[50:51], v[22:23], v[20:21]
	v_fma_f64 v[18:19], v[50:51], v[18:19], v[38:39]
	v_dual_cndmask_b32 v53, v53, v65 :: v_dual_cndmask_b32 v52, v52, v64
	v_fma_f64 v[64:65], v[68:69], v[68:69], v[66:67]
	v_add_f64 v[66:67], v[80:81], -v[8:9]
	v_fma_f64 v[68:69], v[70:71], v[70:71], v[82:83]
	v_add_f64 v[70:71], v[84:85], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[54:55], v[52:53]
	v_fma_f64 v[80:81], v[0:1], v[12:13], v[86:87]
	v_mul_f64 v[82:83], v[96:97], v[96:97]
	v_fma_f64 v[84:85], v[10:11], v[14:15], v[98:99]
	v_add_f64 v[96:97], v[100:101], -v[6:7]
	v_fma_f64 v[98:99], v[2:3], v[16:17], v[36:37]
	v_fma_f64 v[22:23], v[2:3], v[16:17], v[24:25]
	v_fma_f64 v[38:39], v[0:1], v[16:17], v[24:25]
	v_dual_cndmask_b32 v53, v53, v55 :: v_dual_cndmask_b32 v52, v52, v54
	v_fma_f64 v[54:55], v[66:67], v[66:67], v[68:69]
	v_add_f64 v[66:67], v[80:81], -v[8:9]
	v_fma_f64 v[68:69], v[70:71], v[70:71], v[82:83]
	v_add_f64 v[70:71], v[84:85], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[64:65], v[52:53]
	v_fma_f64 v[80:81], v[10:11], v[12:13], v[86:87]
	v_mul_f64 v[82:83], v[96:97], v[96:97]
	v_fma_f64 v[84:85], v[2:3], v[14:15], v[34:35]
	v_add_f64 v[86:87], v[98:99], -v[6:7]
	v_fma_f64 v[96:97], v[0:1], v[16:17], v[36:37]
	v_fma_f64 v[36:37], v[10:11], v[16:17], v[36:37]
	v_add_f64 v[22:23], v[22:23], -v[6:7]
	v_add_f64 v[38:39], v[38:39], -v[6:7]
	v_dual_cndmask_b32 v53, v53, v65 :: v_dual_cndmask_b32 v52, v52, v64
	v_fma_f64 v[64:65], v[66:67], v[66:67], v[68:69]
	v_add_f64 v[66:67], v[80:81], -v[8:9]
	v_fma_f64 v[68:69], v[70:71], v[70:71], v[82:83]
	v_add_f64 v[70:71], v[84:85], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[54:55], v[52:53]
	v_fma_f64 v[80:81], v[2:3], v[12:13], v[48:49]
	v_mul_f64 v[82:83], v[86:87], v[86:87]
	v_fma_f64 v[84:85], v[0:1], v[14:15], v[34:35]
	v_add_f64 v[86:87], v[96:97], -v[6:7]
	v_fma_f64 v[34:35], v[10:11], v[14:15], v[34:35]
	v_add_f64 v[36:37], v[36:37], -v[6:7]
	v_mul_f64 v[22:23], v[22:23], v[22:23]
	v_dual_cndmask_b32 v53, v53, v55 :: v_dual_cndmask_b32 v52, v52, v54
	v_fma_f64 v[54:55], v[66:67], v[66:67], v[68:69]
	v_add_f64 v[66:67], v[80:81], -v[8:9]
	v_fma_f64 v[68:69], v[70:71], v[70:71], v[82:83]
	v_add_f64 v[70:71], v[84:85], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[64:65], v[52:53]
	v_fma_f64 v[80:81], v[0:1], v[12:13], v[48:49]
	v_mul_f64 v[82:83], v[86:87], v[86:87]
	v_fma_f64 v[84:85], v[2:3], v[16:17], v[28:29]
	v_add_f64 v[34:35], v[34:35], -v[4:5]
	v_fma_f64 v[48:49], v[10:11], v[12:13], v[48:49]
	v_mul_f64 v[36:37], v[36:37], v[36:37]
	v_dual_cndmask_b32 v53, v53, v65 :: v_dual_cndmask_b32 v52, v52, v64
	v_fma_f64 v[64:65], v[66:67], v[66:67], v[68:69]
	v_add_f64 v[66:67], v[80:81], -v[8:9]
	v_fma_f64 v[68:69], v[70:71], v[70:71], v[82:83]
	v_fma_f64 v[70:71], v[2:3], v[14:15], v[26:27]
	v_cmp_lt_f64_e32 vcc_lo, v[54:55], v[52:53]
	v_add_f64 v[80:81], v[84:85], -v[6:7]
	v_fma_f64 v[82:83], v[0:1], v[16:17], v[28:29]
	v_add_f64 v[48:49], v[48:49], -v[8:9]
	v_fma_f64 v[34:35], v[34:35], v[34:35], v[36:37]
	v_fma_f64 v[28:29], v[10:11], v[16:17], v[28:29]
	v_fma_f64 v[16:17], v[10:11], v[16:17], v[24:25]
	v_add_f64 v[36:37], v[70:71], -v[4:5]
	v_dual_cndmask_b32 v53, v53, v55 :: v_dual_cndmask_b32 v52, v52, v54
	v_fma_f64 v[54:55], v[66:67], v[66:67], v[68:69]
	v_fma_f64 v[66:67], v[2:3], v[12:13], v[30:31]
	v_mul_f64 v[68:69], v[80:81], v[80:81]
	v_fma_f64 v[70:71], v[0:1], v[14:15], v[26:27]
	v_cmp_lt_f64_e32 vcc_lo, v[64:65], v[52:53]
	v_add_f64 v[80:81], v[82:83], -v[6:7]
	v_fma_f64 v[34:35], v[48:49], v[48:49], v[34:35]
	v_fma_f64 v[26:27], v[10:11], v[14:15], v[26:27]
	v_add_f64 v[28:29], v[28:29], -v[6:7]
	v_add_f64 v[6:7], v[16:17], -v[6:7]
	v_add_f64 v[48:49], v[66:67], -v[8:9]
	v_fma_f64 v[36:37], v[36:37], v[36:37], v[68:69]
	v_dual_cndmask_b32 v33, v53, v65 :: v_dual_cndmask_b32 v32, v52, v64
	v_add_f64 v[52:53], v[70:71], -v[4:5]
	v_fma_f64 v[64:65], v[0:1], v[12:13], v[30:31]
	v_mul_f64 v[66:67], v[80:81], v[80:81]
	v_add_f64 v[26:27], v[26:27], -v[4:5]
	v_cmp_lt_f64_e32 vcc_lo, v[54:55], v[32:33]
	v_fma_f64 v[30:31], v[10:11], v[12:13], v[30:31]
	v_mul_f64 v[28:29], v[28:29], v[28:29]
	v_mul_f64 v[6:7], v[6:7], v[6:7]
	v_fma_f64 v[36:37], v[48:49], v[48:49], v[36:37]
	v_add_f64 v[48:49], v[64:65], -v[8:9]
	v_fma_f64 v[52:53], v[52:53], v[52:53], v[66:67]
	v_dual_cndmask_b32 v33, v33, v55 :: v_dual_cndmask_b32 v32, v32, v54
	v_fma_f64 v[54:55], v[2:3], v[14:15], v[20:21]
	v_add_f64 v[30:31], v[30:31], -v[8:9]
	v_fma_f64 v[26:27], v[26:27], v[26:27], v[28:29]
	v_fma_f64 v[2:3], v[2:3], v[12:13], v[18:19]
	v_cmp_lt_f64_e32 vcc_lo, v[34:35], v[32:33]
	v_add_f64 v[28:29], v[54:55], -v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[30:31], v[30:31], v[26:27]
	v_add_f64 v[2:3], v[2:3], -v[8:9]
	v_dual_cndmask_b32 v33, v33, v35 :: v_dual_cndmask_b32 v32, v32, v34
	v_fma_f64 v[34:35], v[48:49], v[48:49], v[52:53]
	v_fma_f64 v[48:49], v[0:1], v[14:15], v[20:21]
	v_fma_f64 v[0:1], v[0:1], v[12:13], v[18:19]
	v_mul_f64 v[30:31], v[38:39], v[38:39]
	v_cmp_lt_f64_e32 vcc_lo, v[36:37], v[32:33]
	v_fma_f64 v[14:15], v[10:11], v[14:15], v[20:21]
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[18:19]
	v_fma_f64 v[22:23], v[28:29], v[28:29], v[22:23]
	v_add_f64 v[28:29], v[48:49], -v[4:5]
	v_add_f64 v[0:1], v[0:1], -v[8:9]
	v_dual_cndmask_b32 v25, v33, v37 :: v_dual_cndmask_b32 v24, v32, v36
	v_add_f64 v[4:5], v[14:15], -v[4:5]
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[34:35], v[24:25]
	v_fma_f64 v[2:3], v[2:3], v[2:3], v[22:23]
	v_fma_f64 v[20:21], v[28:29], v[28:29], v[30:31]
	v_fma_f64 v[4:5], v[4:5], v[4:5], v[6:7]
	v_dual_cndmask_b32 v17, v25, v35 :: v_dual_cndmask_b32 v16, v24, v34
	v_cmp_lt_f64_e32 vcc_lo, v[26:27], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[0:1], v[0:1], v[0:1], v[20:21]
	v_fma_f64 v[4:5], v[8:9], v[8:9], v[4:5]
	v_dual_cndmask_b32 v13, v17, v27 :: v_dual_cndmask_b32 v12, v16, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[2:3], v[12:13]
	v_dual_cndmask_b32 v3, v13, v3 :: v_dual_cndmask_b32 v2, v12, v2
	v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[0:1]
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
	s_setpc_b64 s[30:31]
.Lfunc_end4:
	.size	_Z13NonOrtho_distddddddPd, .Lfunc_end4-_Z13NonOrtho_distddddddPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2840
; NumSgprs: 34
; NumVgprs: 130
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii ; -- Begin function _Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.globl	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
	.p2align	8
	.type	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii,@function
_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii: ; @_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
; %bb.0:
	s_load_b64 s[34:35], s[0:1], 0x30
	v_lshl_add_u32 v46, s15, 9, v0
	s_mov_b32 s32, 0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s34, v46
	s_cbranch_execz .LBB5_5
; %bb.1:
	s_clause 0x1
	s_load_b256 s[16:23], s[0:1], 0x0
	s_load_b128 s[24:27], s[0:1], 0x20
	s_cmp_lt_i32 s35, 1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v57, s23 :: v_dual_mov_b32 v56, s22
	s_cbranch_scc1 .LBB5_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b512 s[0:15], s[26:27], 0x0
	s_clause 0x1
	s_load_b128 s[28:31], s[18:19], 0x0
	s_load_b64 s[36:37], s[18:19], 0x10
	s_load_b64 s[18:19], s[26:27], 0x40
	s_mul_i32 s26, s35, 3
	v_dual_mov_b32 v57, s23 :: v_dual_mov_b32 v56, s22
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[0:1], s[2:3], s[30:31]
	v_mul_f64 v[2:3], s[30:31], s[8:9]
	v_mul_f64 v[4:5], s[30:31], s[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], s[0:1], s[28:29], v[0:1]
	v_fma_f64 v[2:3], s[28:29], s[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], s[28:29], s[12:13], v[4:5]
	v_fma_f64 v[40:41], s[4:5], s[36:37], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], s[36:37], s[10:11], v[2:3]
	v_fma_f64 v[44:45], s[36:37], s[18:19], v[4:5]
	v_mul_lo_u32 v0, s26, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, s20
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v58, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v59, vcc_lo, 0, v1, vcc_lo
.LBB5_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	global_load_b128 v[0:3], v[58:59], off offset:-8
	global_load_b64 v[4:5], v[58:59], off offset:8
	v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, _Z13NonOrtho_distddddddPd@rel32@lo+4
	s_addc_u32 s23, s23, _Z13NonOrtho_distddddddPd@rel32@hi+12
	s_waitcnt vmcnt(1)
	v_mul_f64 v[6:7], s[2:3], v[2:3]
	v_mul_f64 v[8:9], s[8:9], v[2:3]
	v_mul_f64 v[2:3], s[14:15], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[6:7], s[0:1], v[0:1], v[6:7]
	v_fma_f64 v[8:9], s[6:7], v[0:1], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], s[12:13], v[0:1], v[2:3]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], s[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[2:3], s[10:11], v[4:5], v[8:9]
	v_fma_f64 v[4:5], s[18:19], v[4:5], v[10:11]
	v_dual_mov_b32 v6, v40 :: v_dual_mov_b32 v7, v41
	v_dual_mov_b32 v8, v42 :: v_dual_mov_b32 v9, v43
	v_dual_mov_b32 v10, v44 :: v_dual_mov_b32 v11, v45
	s_swappc_b64 s[30:31], s[22:23]
	v_max_f64 v[2:3], v[56:57], v[56:57]
	v_max_f64 v[0:1], v[0:1], v[0:1]
	v_add_co_u32 v58, vcc_lo, v58, 24
	v_add_co_ci_u32_e32 v59, vcc_lo, 0, v59, vcc_lo
	s_add_i32 s20, s20, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_cmp_ge_i32 s20, s26
	v_min_f64 v[56:57], v[2:3], v[0:1]
	s_cbranch_scc0 .LBB5_3
.LBB5_4:                                ; %Flow108
	v_ashrrev_i32_e32 v47, 31, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[46:47]
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	global_store_b64 v[0:1], v[56:57], off
.LBB5_5:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 60
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 130
		.amdhsa_next_free_sgpr 38
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii, .Lfunc_end5-_Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 40
; NumVgprs: 130
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 40
; NumVGPRsForWavesPerEU: 130
; Occupancy: 10
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii ; -- Begin function _Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.globl	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
	.p2align	8
	.type	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii,@function
_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii: ; @_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
; %bb.0:
	s_load_b128 s[24:27], s[0:1], 0x30
	v_mov_b32_e32 v40, v0
	s_mov_b32 s34, 1
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s33, s26, 3
	s_cmp_lt_i32 s26, 4
	s_mov_b32 s26, s33
	s_cbranch_scc1 .LBB6_2
; %bb.1:
	v_cvt_f64_i32_e32 v[0:1], s33
	s_mov_b32 s26, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, 0x40220000, 0x40220000, v[0:1]
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_div_scale_f64 v[6:7], vcc_lo, v[0:1], 0x40220000, v[0:1]
	v_mul_f64 v[8:9], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], 0x40220000, v[0:1]
	v_ceil_f64_e32 v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v0, v[0:1]
	v_readfirstlane_b32 s34, v0
.LBB6_2:
	v_mad_u64_u32 v[56:57], null, s15, s27, v[40:41]
	s_mul_i32 s2, s25, s24
	v_cmp_gt_u32_e32 vcc_lo, s27, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s2, v56
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB6_14
; %bb.3:
	s_clause 0x1
	s_load_b256 s[16:23], s[0:1], 0x0
	s_load_b128 s[28:31], s[0:1], 0x20
	s_cmp_lt_i32 s34, 1
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v58, s23 :: v_dual_mov_b32 v57, s22
	s_cbranch_scc1 .LBB6_10
; %bb.4:                                ; %.preheader121.preheader
	v_lshl_add_u32 v0, v56, 1, v56
	v_dual_mov_b32 v58, s23 :: v_dual_mov_b32 v57, s22
	s_add_u32 s24, s20, 8
	s_addc_u32 s27, s21, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s20, 0
	s_mov_b32 s35, s26
	s_mov_b32 s36, 0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s19, v1, vcc_lo
	s_clause 0x1
	global_load_b128 v[0:3], v[4:5], off
	global_load_b64 v[4:5], v[4:5], off offset:16
	s_clause 0x1
	s_load_b512 s[0:15], s[30:31], 0x0
	s_load_b64 s[18:19], s[30:31], 0x40
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[6:7], s[2:3], v[2:3]
	v_mul_f64 v[8:9], v[2:3], s[8:9]
	v_mul_f64 v[2:3], v[2:3], s[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[6:7], s[0:1], v[0:1], v[6:7]
	v_fma_f64 v[8:9], v[0:1], s[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[12:13], v[2:3]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[41:42], s[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[43:44], v[4:5], s[10:11], v[8:9]
	v_fma_f64 v[45:46], v[4:5], s[18:19], v[0:1]
.LBB6_5:                                ; %.preheader121
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB6_7 Depth 2
	s_cmp_ge_i32 s20, s35
	s_cbranch_scc1 .LBB6_8
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB6_5 Depth=1
	s_ashr_i32 s21, s20, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[22:23], s[20:21], 3
	s_add_u32 s22, s24, s22
	s_addc_u32 s23, s27, s23
.LBB6_7:                                ; %.lr.ph
                                        ;   Parent Loop BB6_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_u32 s30, s22, -8
	s_addc_u32 s31, s23, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v41 :: v_dual_mov_b32 v7, v42
	s_clause 0x1
	s_load_b128 s[40:43], s[30:31], 0x0
	s_load_b64 s[30:31], s[22:23], 0x8
	v_dual_mov_b32 v8, v43 :: v_dual_mov_b32 v9, v44
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v10, v45 :: v_dual_mov_b32 v11, v46
	v_dual_mov_b32 v12, s28 :: v_dual_mov_b32 v13, s29
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[0:1], s[2:3], s[42:43]
	v_mul_f64 v[2:3], s[8:9], s[42:43]
	v_mul_f64 v[4:5], s[14:15], s[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], s[0:1], s[40:41], v[0:1]
	v_fma_f64 v[2:3], s[6:7], s[40:41], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], s[12:13], s[40:41], v[4:5]
	v_fma_f64 v[0:1], s[4:5], s[30:31], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[2:3], s[10:11], s[30:31], v[2:3]
	v_fma_f64 v[4:5], s[18:19], s[30:31], v[4:5]
	s_getpc_b64 s[30:31]
	s_add_u32 s30, s30, _Z13NonOrtho_distddddddPd@rel32@lo+4
	s_addc_u32 s31, s31, _Z13NonOrtho_distddddddPd@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	s_swappc_b64 s[30:31], s[30:31]
	v_max_f64 v[2:3], v[57:58], v[57:58]
	v_max_f64 v[0:1], v[0:1], v[0:1]
	s_add_i32 s20, s20, 3
	s_add_u32 s22, s22, 24
	s_addc_u32 s23, s23, 0
	s_cmp_lt_i32 s20, s35
	s_delay_alu instid0(VALU_DEP_1)
	v_min_f64 v[57:58], v[2:3], v[0:1]
	s_cbranch_scc1 .LBB6_7
.LBB6_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB6_5 Depth=1
	s_add_i32 s20, s35, s26
	s_add_i32 s36, s36, 1
	s_min_i32 s21, s20, s33
	s_cmp_lg_u32 s36, s34
	s_cbranch_scc0 .LBB6_10
; %bb.9:                                ;   in Loop: Header=BB6_5 Depth=1
	s_mov_b32 s20, s35
	s_mov_b32 s35, s21
	s_branch .LBB6_5
.LBB6_10:                               ; %._crit_edge128
	v_cvt_f32_u32_e32 v0, s25
	s_sub_i32 s0, 0, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s0, v0
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_hi_u32 v0, v56, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v0, s25
	v_add_nc_u32_e32 v2, 1, v0
	v_sub_nc_u32_e32 v1, v56, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s25, v1
	v_cmp_le_u32_e32 vcc_lo, s25, v1
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s25, v1
	v_lshlrev_b32_e32 v1, 3, v40
	v_add_nc_u32_e32 v2, 1, v0
	ds_store_b64 v1, v[57:58]
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_mul_lo_u32 v2, v0, s25
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, v56, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB6_14
; %bb.11:                               ; %.preheader
	s_cmp_lt_i32 s25, 1
	s_cbranch_scc1 .LBB6_13
.LBB6_12:                               ; %.lr.ph132
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[2:3], v1
	v_max_f64 v[4:5], v[57:58], v[57:58]
	v_add_nc_u32_e32 v1, 8, v1
	s_add_i32 s25, s25, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s25, 0
	s_waitcnt lgkmcnt(0)
	v_max_f64 v[2:3], v[2:3], v[2:3]
	v_min_f64 v[57:58], v[4:5], v[2:3]
	s_cbranch_scc1 .LBB6_12
.LBB6_13:                               ; %._crit_edge133
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	global_store_b64 v[0:1], v[57:58], off
.LBB6_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 64
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 130
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii, .Lfunc_end6-_Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1056
; NumSgprs: 46
; NumVgprs: 130
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 130
; Occupancy: 10
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25Action_noImage_center_GPUPdS_S_diii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z25Action_noImage_center_GPUPdS_S_diii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28Action_noImage_no_center_GPUPdS_S_diiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z28Action_noImage_no_center_GPUPdS_S_diiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 52
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z28Action_ImageOrtho_center_GPUPdS_S_dS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z31Action_ImageOrtho_no_center_GPUPdS_S_dS_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 60
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     40
    .sgpr_spill_count: 0
    .symbol:         _Z31Action_ImageNonOrtho_center_GPUPdS_S_dS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     130
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 64
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         _Z34Action_ImageNonOrtho_no_center_GPUPdS_S_dS_S_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     130
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
