#include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include <time.h>


#define Mask_size 3  //filter size
#define Width   1024 // image width
#define Height 1024   // image height

#define N (Width*Height)

//---------------kernel-------------------

__global__ void ConvExp (int *I_input, int *Mask1,int *Mask2,int *Mask3,int *Mask4, int *I_output1,int *I_output2,int 												*I_output3,int *I_output4)
{
     	/* Thread Row Index */
	int Row = blockIdx.y * blockDim.y + threadIdx.y;    
    	/* Thread column Index */
	int Col = blockIdx.x * blockDim.x + threadIdx.x; 

    	float value1 = 0;
	float value2 = 0;
	float value3 = 0;
	float value4 = 0;

	int Index = Row*Width+Col; //output Image index
    
/* convolution */

    for(int i=0; i<Mask_size; i++) 
	{
        for(int j=0; j<Mask_size; j++) 
		{
                   int  R_start = i + Row - 1;
                   int  C_start = j + Col - 1;
                         if((C_start>= 0 && C_start < Width) && (R_start>= 0 && R_start < Height))
						 {
                              	value1 += Mask1[i * Mask_size + j] * I_input[R_start* Width + C_start];
				value2 += Mask2[i * Mask_size + j] * I_input[R_start* Width + C_start];
				value1 += Mask2[i * Mask_size + j] * I_input[R_start* Width + C_start];
				value2 += Mask3[i * Mask_size + j] * I_input[R_start* Width + C_start];

						 }
        }
    }
      if((Row < Height) && (Col < Width)) {
            	I_output1[Index] = value1; // convolved image
		I_output2[Index] = value2;
		I_output3[Index] = value3; 
		I_output4[Index] = value4;
    }
}

//----------------------------main-----------------------------------

int main(void)
{
	
//-------------------------------------------------------------------

	int *Image, *Output1,*Output2, *Output3, *Output4;
	int *mask1, *mask2, *mask3, *mask4;
	int SIZE= Width*Height*sizeof(int);
	int Row,Col;

	Image=	(int *)malloc(SIZE);
	Output1= (int *)malloc(SIZE);
	Output2= (int *)malloc(SIZE);
	Output3= (int *)malloc(SIZE);
	Output4= (int *)malloc(SIZE);
	mask1= (int *)malloc(Mask_size*Mask_size*sizeof(int));
	mask2= (int *)malloc(Mask_size*Mask_size*sizeof(int));
	mask3= (int *)malloc(Mask_size*Mask_size*sizeof(int));
	mask4= (int *)malloc(Mask_size*Mask_size*sizeof(int));

	//-------------------------------------------------------------------

	int *d_image, *d_mask1,*d_mask2,*d_mask3,*d_mask4,*d_output1, *d_output2,*d_output3, *d_output4; /* pointer to device memory 		
	
												for input image, mask and output */
	//-----------------------------------------------------------
	
	for(Row=0;Row<Width;Row++)
		for(Col=0;Col<Height;Col++)
		{
			Image[Row*Width+Col]=1;
			Output1[Row*Width+Col]=0;
			Output2[Row*Width+Col]=0;
			Output3[Row*Width+Col]=0;
			Output4[Row*Width+Col]=0;		
		}
	
	//-----------------------------------------------------------

	for(Row=0;Row<Mask_size;Row++) 
	{
		for(Col=0;Col<Mask_size;Col++) 
		mask1[Row*Mask_size+Col]=1;
		mask2[Row*Mask_size+Col]=2;
		mask3[Row*Mask_size+Col]=3;
		mask4[Row*Mask_size+Col]=4;
	}
		
	//------------------------------------------------------

	/* Device Memory Allocation */
	cudaMalloc(&d_image, (Width*Height)* sizeof(int));
	cudaMalloc(&d_output1, (Width*Height)* sizeof(int));
	cudaMalloc(&d_output2, (Width*Height)* sizeof(int));
	cudaMalloc(&d_output3, (Width*Height)* sizeof(int));
	cudaMalloc(&d_output4, (Width*Height)* sizeof(int));
	cudaMalloc(&d_mask1, (Mask_size*Mask_size)* sizeof(int));
	cudaMalloc(&d_mask2, (Mask_size*Mask_size)* sizeof(int));
	cudaMalloc(&d_mask3, (Mask_size*Mask_size)* sizeof(int));
	cudaMalloc(&d_mask4, (Mask_size*Mask_size)* sizeof(int));
	

	//---------------------------------------------------------

	cudaEvent_t start, stop;       // Cuda API to measure time for Cuda Kernel Execution.
	cudaEventCreate(&start);
	cudaEventCreate(&stop);

	cudaEventRecord(start);
	
	//--------------------------------------------------------
	
	/*Copying Input Image to GPU Memory */
	cudaMemcpy(d_image, Image, (Width*Height)* sizeof(int), cudaMemcpyHostToDevice); 

	/*Copying Mask to GPU Memory */
	cudaMemcpy(d_mask1, mask1, (Mask_size*Mask_size)* sizeof(int), cudaMemcpyHostToDevice); 
	cudaMemcpy(d_mask2, mask2, (Mask_size*Mask_size)* sizeof(int), cudaMemcpyHostToDevice); 
	cudaMemcpy(d_mask3, mask3, (Mask_size*Mask_size)* sizeof(int), cudaMemcpyHostToDevice); 
	cudaMemcpy(d_mask4, mask4, (Mask_size*Mask_size)* sizeof(int), cudaMemcpyHostToDevice); 
	
	/* Two Dimesional blocks with two dimensional threads */
	dim3 grid(((Width-1)/Mask_size+1),((Height-1)/Mask_size+1));

	/*Number of threads per block is 3x3=9 */	
	dim3 block(Mask_size,Mask_size); 

	//---------------------------------------------

	printf ("GPU Executing Convolution Kernel...\n") ;
	printf("\n");
		
	//--------------------------------------------

	/*Kernel Launch configuration*/	
	ConvExp <<<grid, block >>>(d_image, d_mask1,d_mask2, d_mask3,d_mask4,d_output1, d_output2,d_output3, d_output4); 
	
	/*copying output Image to Host Memory*/
	cudaMemcpy(Output1, d_output1, (Width*Height)* sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(Output2, d_output2, (Width*Height)* sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(Output3, d_output3, (Width*Height)* sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(Output4, d_output4, (Width*Height)* sizeof(int), cudaMemcpyDeviceToHost);

	//-------------------------------------------
	
	cudaEventRecord(stop);

	cudaEventSynchronize(stop);			// Blocks CPU execution until Device Kernel finishes its job.
	
	float milliseconds = 0;
	cudaEventElapsedTime(&milliseconds, start, stop);   	
	
	printf("GPU Execution Time for Convolution Kernel: %fn\n", milliseconds); //GPU Execution Time.
	printf("Effective Bandwidth (GB/s): %fn\n", N*4*2/milliseconds/1e6); 
	//N*4 is the total number of Bytes transferred and (1+1)=2 is for read Input Image and write Output Image.
	printf("\n");

	//------------------------------------------
	free(Image);
	free(Output1);
	free(Output2);
	free(Output3);
	free(Output4);
	free(mask1);
	free(mask2);
	free(mask3);
	free(mask4);
	
	cudaFree(d_image);
	cudaFree(d_mask1);
	cudaFree(d_mask2);
	cudaFree(d_mask3);
	cudaFree(d_mask4);
	cudaFree(d_output1);
	cudaFree(d_output2);
	cudaFree(d_output3);
	cudaFree(d_output4);
	
return 0;
}


	.file	"tmpxft_0032df86_00000000-6_ConvExp.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0:
.LFB2172:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2172:
	.size	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	.globl	_Z42__device_stub__Z7ConvExpPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	.type	_Z42__device_stub__Z7ConvExpPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_, @function
_Z42__device_stub__Z7ConvExpPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z7ConvExpPiS_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L3:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z42__device_stub__Z7ConvExpPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_, .-_Z42__device_stub__Z7ConvExpPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	.globl	_Z7ConvExpPiS_S_S_S_S_S_S_S_
	.type	_Z7ConvExpPiS_S_S_S_S_S_S_S_, @function
_Z7ConvExpPiS_S_S_S_S_S_S_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z7ConvExpPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2053:
	.size	_Z7ConvExpPiS_S_S_S_S_S_S_S_, .-_Z7ConvExpPiS_S_S_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPU Executing Convolution Kernel...\n"
.LC1:
	.string	"\n"
.LC3:
	.string	"GPU Execution Time for Convolution Kernel: %fn\n"
.LC6:
	.string	"Effective Bandwidth (GB/s): %fn\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$4194304, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, 24(%rsp)
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$36, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%r14, %rdx
	xorl	%ecx, %ecx
	movq	%rax, %rbp
.L11:
	xorl	%eax, %eax
.L10:
	movl	$1, (%rdx,%rax,4)
	incq	%rax
	cmpq	$1024, %rax
	jne	.L10
	addl	$1024, %ecx
	addq	$4096, %rdx
	cmpl	$1048576, %ecx
	jne	.L11
	movq	(%rsp), %rdi
	xorl	%eax, %eax
	movl	$1048576, %ecx
	movl	$4194304, %esi
	movl	$2, 12(%r13)
	leaq	.LC1(%rip), %r15
	rep stosl
	movq	8(%rsp), %rdi
	movl	$1048576, %ecx
	movl	$3, 12(%r12)
	movl	$4, 12(%rbp)
	rep stosl
	movq	16(%rsp), %rdi
	movl	$1048576, %ecx
	movl	$2, 24(%r13)
	movl	$3, 24(%r12)
	rep stosl
	movq	24(%rsp), %rdi
	movl	$1048576, %ecx
	movl	$4, 24(%rbp)
	movl	$1, 32(%rbx)
	rep stosl
	movl	$2, 36(%r13)
	movabsq	$4294967297, %rax
	leaq	40(%rsp), %rdi
	movq	%rax, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rax, 24(%rbx)
	movl	$3, 36(%r12)
	movl	$4, 36(%rbp)
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	80(%rsp), %rdi
	movl	$4194304, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	88(%rsp), %rdi
	movl	$4194304, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	96(%rsp), %rdi
	movl	$4194304, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	104(%rsp), %rdi
	movl	$4194304, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	48(%rsp), %rdi
	movl	$36, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	56(%rsp), %rdi
	movl	$36, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	64(%rsp), %rdi
	movl	$36, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	$36, %esi
	leaq	72(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	112(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	120(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	112(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$36, %edx
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	movabsq	$1468878815574, %rax
	movq	%rax, 128(%rsp)
	movabsq	$12884901891, %rax
	movq	%rax, 140(%rsp)
	xorl	%eax, %eax
	movl	$1, 136(%rsp)
	movl	$1, 148(%rsp)
	call	__printf_chk@PLT
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	148(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	140(%rsp), %rdx
	movq	128(%rsp), %rdi
	movl	136(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	%rax
	.cfi_def_cfa_offset 232
	pushq	112(%rsp)
	.cfi_def_cfa_offset 240
	pushq	112(%rsp)
	.cfi_def_cfa_offset 248
	pushq	112(%rsp)
	.cfi_def_cfa_offset 256
	movq	112(%rsp), %r9
	movq	104(%rsp), %r8
	movq	96(%rsp), %rcx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z42__device_stub__Z7ConvExpPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 224
.L14:
	movq	80(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	96(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	104(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	120(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	120(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	120(%rsp), %rdx
	movq	112(%rsp), %rsi
	leaq	36(%rsp), %rdi
	movl	$0x00000000, 36(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC6(%rip), %rsi
	movss	.LC4(%rip), %xmm0
	divss	36(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	divsd	.LC5(%rip), %xmm0
	call	__printf_chk@PLT
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z7ConvExpPiS_S_S_S_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7ConvExpPiS_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	1258291200
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC5:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include <time.h>


#define Mask_size 3  //filter size
#define Width   1024 // image width
#define Height 1024   // image height

#define N (Width*Height)

//---------------kernel-------------------

__global__ void ConvExp (int *I_input, int *Mask1,int *Mask2,int *Mask3,int *Mask4, int *I_output1,int *I_output2,int 												*I_output3,int *I_output4)
{
     	/* Thread Row Index */
	int Row = blockIdx.y * blockDim.y + threadIdx.y;    
    	/* Thread column Index */
	int Col = blockIdx.x * blockDim.x + threadIdx.x; 

    	float value1 = 0;
	float value2 = 0;
	float value3 = 0;
	float value4 = 0;

	int Index = Row*Width+Col; //output Image index
    
/* convolution */

    for(int i=0; i<Mask_size; i++) 
	{
        for(int j=0; j<Mask_size; j++) 
		{
                   int  R_start = i + Row - 1;
                   int  C_start = j + Col - 1;
                         if((C_start>= 0 && C_start < Width) && (R_start>= 0 && R_start < Height))
						 {
                              	value1 += Mask1[i * Mask_size + j] * I_input[R_start* Width + C_start];
				value2 += Mask2[i * Mask_size + j] * I_input[R_start* Width + C_start];
				value1 += Mask2[i * Mask_size + j] * I_input[R_start* Width + C_start];
				value2 += Mask3[i * Mask_size + j] * I_input[R_start* Width + C_start];

						 }
        }
    }
      if((Row < Height) && (Col < Width)) {
            	I_output1[Index] = value1; // convolved image
		I_output2[Index] = value2;
		I_output3[Index] = value3; 
		I_output4[Index] = value4;
    }
}

//----------------------------main-----------------------------------

int main(void)
{
	
//-------------------------------------------------------------------

	int *Image, *Output1,*Output2, *Output3, *Output4;
	int *mask1, *mask2, *mask3, *mask4;
	int SIZE= Width*Height*sizeof(int);
	int Row,Col;

	Image=	(int *)malloc(SIZE);
	Output1= (int *)malloc(SIZE);
	Output2= (int *)malloc(SIZE);
	Output3= (int *)malloc(SIZE);
	Output4= (int *)malloc(SIZE);
	mask1= (int *)malloc(Mask_size*Mask_size*sizeof(int));
	mask2= (int *)malloc(Mask_size*Mask_size*sizeof(int));
	mask3= (int *)malloc(Mask_size*Mask_size*sizeof(int));
	mask4= (int *)malloc(Mask_size*Mask_size*sizeof(int));

	//-------------------------------------------------------------------

	int *d_image, *d_mask1,*d_mask2,*d_mask3,*d_mask4,*d_output1, *d_output2,*d_output3, *d_output4; /* pointer to device memory 		
	
												for input image, mask and output */
	//-----------------------------------------------------------
	
	for(Row=0;Row<Width;Row++)
		for(Col=0;Col<Height;Col++)
		{
			Image[Row*Width+Col]=1;
			Output1[Row*Width+Col]=0;
			Output2[Row*Width+Col]=0;
			Output3[Row*Width+Col]=0;
			Output4[Row*Width+Col]=0;		
		}
	
	//-----------------------------------------------------------

	for(Row=0;Row<Mask_size;Row++) 
	{
		for(Col=0;Col<Mask_size;Col++) 
		mask1[Row*Mask_size+Col]=1;
		mask2[Row*Mask_size+Col]=2;
		mask3[Row*Mask_size+Col]=3;
		mask4[Row*Mask_size+Col]=4;
	}
		
	//------------------------------------------------------

	/* Device Memory Allocation */
	hipMalloc(&d_image, (Width*Height)* sizeof(int));
	hipMalloc(&d_output1, (Width*Height)* sizeof(int));
	hipMalloc(&d_output2, (Width*Height)* sizeof(int));
	hipMalloc(&d_output3, (Width*Height)* sizeof(int));
	hipMalloc(&d_output4, (Width*Height)* sizeof(int));
	hipMalloc(&d_mask1, (Mask_size*Mask_size)* sizeof(int));
	hipMalloc(&d_mask2, (Mask_size*Mask_size)* sizeof(int));
	hipMalloc(&d_mask3, (Mask_size*Mask_size)* sizeof(int));
	hipMalloc(&d_mask4, (Mask_size*Mask_size)* sizeof(int));
	

	//---------------------------------------------------------

	hipEvent_t start, stop;       // Cuda API to measure time for Cuda Kernel Execution.
	hipEventCreate(&start);
	hipEventCreate(&stop);

	hipEventRecord(start);
	
	//--------------------------------------------------------
	
	/*Copying Input Image to GPU Memory */
	hipMemcpy(d_image, Image, (Width*Height)* sizeof(int), hipMemcpyHostToDevice); 

	/*Copying Mask to GPU Memory */
	hipMemcpy(d_mask1, mask1, (Mask_size*Mask_size)* sizeof(int), hipMemcpyHostToDevice); 
	hipMemcpy(d_mask2, mask2, (Mask_size*Mask_size)* sizeof(int), hipMemcpyHostToDevice); 
	hipMemcpy(d_mask3, mask3, (Mask_size*Mask_size)* sizeof(int), hipMemcpyHostToDevice); 
	hipMemcpy(d_mask4, mask4, (Mask_size*Mask_size)* sizeof(int), hipMemcpyHostToDevice); 
	
	/* Two Dimesional blocks with two dimensional threads */
	dim3 grid(((Width-1)/Mask_size+1),((Height-1)/Mask_size+1));

	/*Number of threads per block is 3x3=9 */	
	dim3 block(Mask_size,Mask_size); 

	//---------------------------------------------

	printf ("GPU Executing Convolution Kernel...\n") ;
	printf("\n");
		
	//--------------------------------------------

	/*Kernel Launch configuration*/	
	ConvExp <<<grid, block >>>(d_image, d_mask1,d_mask2, d_mask3,d_mask4,d_output1, d_output2,d_output3, d_output4); 
	
	/*copying output Image to Host Memory*/
	hipMemcpy(Output1, d_output1, (Width*Height)* sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(Output2, d_output2, (Width*Height)* sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(Output3, d_output3, (Width*Height)* sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(Output4, d_output4, (Width*Height)* sizeof(int), hipMemcpyDeviceToHost);

	//-------------------------------------------
	
	hipEventRecord(stop);

	hipEventSynchronize(stop);			// Blocks CPU execution until Device Kernel finishes its job.
	
	float milliseconds = 0;
	hipEventElapsedTime(&milliseconds, start, stop);   	
	
	printf("GPU Execution Time for Convolution Kernel: %fn\n", milliseconds); //GPU Execution Time.
	printf("Effective Bandwidth (GB/s): %fn\n", N*4*2/milliseconds/1e6); 
	//N*4 is the total number of Bytes transferred and (1+1)=2 is for read Input Image and write Output Image.
	printf("\n");

	//------------------------------------------
	free(Image);
	free(Output1);
	free(Output2);
	free(Output3);
	free(Output4);
	free(mask1);
	free(mask2);
	free(mask3);
	free(mask4);
	
	hipFree(d_image);
	hipFree(d_mask1);
	hipFree(d_mask2);
	hipFree(d_mask3);
	hipFree(d_mask4);
	hipFree(d_output1);
	hipFree(d_output2);
	hipFree(d_output3);
	hipFree(d_output4);
	
return 0;
}


	.text
	.file	"ConvExp.hip"
	.globl	_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_ # -- Begin function _Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_
	.type	_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_,@function
_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_: # @_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7ConvExpPiS_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x4b000000                      # float 8388608
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %rbx
	movl	$1, %edi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	calloc@PLT
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	calloc@PLT
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movl	$1, %edi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	calloc@PLT
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	calloc@PLT
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r13
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$36, %edi
	callq	malloc
	movq	%rax, %r12
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB1_1:                                # %.preheader69
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%edx, %edx
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$1024, %rdx                     # imm = 0x400
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rax
	addq	$4096, %rcx                     # imm = 0x1000
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB1_1
# %bb.4:                                # %.preheader.preheader
	movq	%rbx, 96(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	movq	%r13, 72(%rsp)                  # 8-byte Spill
.LBB1_5:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_6 Depth 2
	leaq	(%rax,%rax,2), %rdx
	xorl	%esi, %esi
.LBB1_6:                                #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1, (%r13,%rsi,4)
	incq	%rsi
	cmpq	$3, %rsi
	jne	.LBB1_6
# %bb.7:                                #   in Loop: Header=BB1_5 Depth=1
	movl	$2, 12(%r14,%rdx,4)
	movl	$3, 12(%r15,%rdx,4)
	movl	$4, 12(%r12,%rdx,4)
	incq	%rax
	addq	$12, %r13
	cmpq	$3, %rax
	jne	.LBB1_5
# %bb.8:
	leaq	64(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	112(%rsp), %rbx
	movl	$36, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	104(%rsp), %r13
	movl	$36, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$36, %esi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$36, %esi
	callq	hipMalloc
	leaq	136(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	64(%rsp), %rax
	movq	(%rax), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movl	$36, %edx
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$36, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rax
	movq	(%rax), %rdi
	movl	$36, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %rax
	movq	(%rax), %rdi
	movl	$36, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$10, %edi
	callq	putchar@PLT
	movabsq	$1468878815574, %rdi            # imm = 0x15600000156
	movabsq	$12884901891, %rdx              # imm = 0x300000003
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.9:
	movq	64(%rsp), %rdi
	movq	112(%rsp), %rsi
	movq	104(%rsp), %rdx
	movq	56(%rsp), %rcx
	movq	48(%rsp), %r8
	movq	40(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_10:
	movq	40(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	88(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	128(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	120(%rsp), %rbp                 # 8-byte Reload
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	148(%rsp), %rbx
	movl	$0, (%rbx)
	movq	136(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	divss	(%rbx), %xmm0
	cvtss2sd	%xmm0, %xmm0
	divsd	.LCPI1_1(%rip), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movl	$10, %edi
	callq	putchar@PLT
	movq	96(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	88(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	80(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	72(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7ConvExpPiS_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7ConvExpPiS_S_S_S_S_S_S_S_,@object # @_Z7ConvExpPiS_S_S_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z7ConvExpPiS_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z7ConvExpPiS_S_S_S_S_S_S_S_:
	.quad	_Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_
	.size	_Z7ConvExpPiS_S_S_S_S_S_S_S_, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"GPU Execution Time for Convolution Kernel: %fn\n"
	.size	.L.str.2, 48

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Effective Bandwidth (GB/s): %fn\n"
	.size	.L.str.3, 33

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7ConvExpPiS_S_S_S_S_S_S_S_"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"GPU Executing Convolution Kernel..."
	.size	.Lstr, 36

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__ConvExpPiS_S_S_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7ConvExpPiS_S_S_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7ConvExpPiS_S_S_S_S_S_S_S_ ; -- Begin function _Z7ConvExpPiS_S_S_S_S_S_S_S_
	.globl	_Z7ConvExpPiS_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z7ConvExpPiS_S_S_S_S_S_S_S_,@function
_Z7ConvExpPiS_S_S_S_S_S_S_S_:           ; @_Z7ConvExpPiS_S_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_and_b32_e32 v3, 0x3ff, v0
	s_add_u32 s12, s4, 0xffffeffc
	s_addc_u32 s13, s5, -1
	v_lshlrev_b32_e32 v4, 10, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v5, v4
	v_mov_b32_e32 v3, 0
	s_mov_b32 s14, 0
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s14, v2
	s_mov_b64 s[4:5], 0
	v_cmp_lt_i32_e32 vcc_lo, 0, v6
	v_cmp_gt_i32_e64 s2, 0x401, v6
	v_mov_b32_e32 v6, v0
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, -1, v6
	v_cmp_gt_u32_e64 s3, 0x400, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s3, vcc_lo
	s_and_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s15, s3
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	v_add_nc_u32_e32 v7, v5, v6
	s_add_u32 s16, s6, s4
	s_addc_u32 s17, s7, s5
	s_add_u32 s18, s8, s4
	s_addc_u32 s19, s9, s5
	v_ashrrev_i32_e32 v8, 31, v7
	s_load_b32 s18, s[18:19], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, s3, s12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s3, s13, v8, s3
	s_load_b32 s3, s[16:17], 0x0
	s_add_u32 s16, s10, s4
	s_addc_u32 s17, s11, s5
	global_load_b32 v7, v[7:8], off
	s_load_b32 s16, s[16:17], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_lo_u32 v8, v7, s3
	v_mul_lo_u32 v9, s18, v7
	v_mul_lo_u32 v7, s16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v8, v8
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v7, v7
	v_add_f32_e32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v9
	v_add_f32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v7
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	v_add_nc_u32_e32 v6, 1, v6
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s4, 12
	s_cbranch_scc0 .LBB0_2
; %bb.5:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s14, s14, 1
	s_add_u32 s6, s6, 12
	s_addc_u32 s7, s7, 0
	s_add_u32 s8, s8, 12
	s_addc_u32 s9, s9, 0
	v_add_nc_u32_e32 v5, 0x400, v5
	s_add_u32 s10, s10, 12
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s14, 3
	s_cbranch_scc0 .LBB0_1
; %bb.6:
	v_max_i32_e32 v2, v2, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x400, v2
	s_cbranch_execz .LBB0_8
; %bb.7:
	s_load_b256 s[0:7], s[0:1], 0x28
	v_add_nc_u32_e32 v4, v4, v0
	v_cvt_i32_f32_e32 v9, v1
	v_cvt_i32_f32_e32 v8, v3
	v_mov_b32_e32 v10, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_store_b32 v[6:7], v9, off
	global_store_b32 v[2:3], v8, off
	global_store_b32 v[0:1], v10, off
	global_store_b32 v[4:5], v10, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7ConvExpPiS_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7ConvExpPiS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z7ConvExpPiS_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7ConvExpPiS_S_S_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z7ConvExpPiS_S_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
