/*
 ============================================================================
 Name        : GScuda.cu
 Author      : caleb
 Version     :
 Copyright   : Your copyright notice
 Description : CUDA compute reciprocals
 ============================================================================
 */

#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdint.h>
#include <limits.h>
#include <curand_kernel.h>
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <cub/cub.cuh>
using namespace cub;
// I ASSUME THROUGHOUT THAT sizeof(int) = 4
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)

static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err);

__global__ void piiKernel(uint8_t n, uint8_t* male_prefs, uint8_t* female_prefs, uint8_t* output) {
    //TODO fix shared bank conflicts

    int idx = threadIdx.x;
    extern __shared__ int s[]; 
    // current_match[i] = j implies female i is matched with male j
    int* current_match = (int*) s;
    //curent_match flipped for fast lookups so match current[j] = i implies female i is matched with male j
    int* match_current = (int*) &current_match[n];
    // nm1[i] = j implies that female i is matched with male (j&0xFF) and female_prefs[i][j] = ((j>>24)&0xFF)
    // no need to reset every time since nm1 pairs always improve things for the woman
    unsigned int* nm1 = (unsigned int*) &match_current[n];
    // an array of three tuples of the form nm2graph[male id(row)] = (row neighbor index, female id (column),column neighbor index), indexes are 255 if null
    // where the row (respectively column) neighbor index is the index into nm2graph of the the nm2 pair it is connected to by the matching pair in the same row as it
    uint8_t* nm2graph= (uint8_t*) &nm1[n];
    uint8_t* shared_fp = (uint8_t*) &nm2graph[3*n];
    uint8_t* unstable = (uint8_t*) &shared_fp[n*n];
    //local cache of male_prefs
    //TODO coalesce
    uint8_t* local_mp = new uint8_t[n];
    for (int i = 0; i < n; i++){
        local_mp[i] = male_prefs[idx*n+i];
    }
    // generated a random permutation on the CPU
    int temp_man = current_match[idx] = output[idx]; 
    match_current[temp_man] = idx;
    //copy female prefs into swap
    //TODO optimize (may be good already)
    for (int i = 0; i < n; i++) {
        shared_fp[i*n + idx] = female_prefs[i*n + idx];
    }
    __syncthreads();
    for (int p = 0; p < n; p++) {
        __syncthreads();
        int partner = match_current[idx]; 
        // the female partner for this male's NM1 pair
        int nm1g = -1;
        //TODO optimize
        unstable[0] = 0;
        __syncthreads();
        //find NM1-generating pairs
        for (int j  = 0; local_mp[j] != partner; j++){
            if (shared_fp[local_mp[j]*n+idx] < shared_fp[local_mp[j]*n+current_match[local_mp[j]]]){
                nm1g = local_mp[j];
#ifdef DEBUG
                printf("found nm1g pair for male %d\n",idx);
#endif
                unstable[0] = 1;
                break;
            }
        }
#ifdef DEBUG
        printf("thread: %d, potential nm1g=%d\n",idx,nm1g);
#endif
        //TODO optimize
        __syncthreads();
        if (unstable[0] == 0){
#ifdef DEBUG
        printf("FOUND STABLE MATCHING\n");
#endif
            break;
        }
        //TODO optimize?
        nm2graph[idx*3 +0] = 255;
        nm2graph[idx*3 +1] = 255;
        nm2graph[idx*3+2] = 255;
        bool is_nm1 = false;
        unsigned int  potential_nm1_construct = ~0;
        // initialize large
        nm1[idx] = INT_MAX;
        __syncthreads();
        if (nm1g != -1) {
            //find NM1 pairs  
            //TODO explain
            potential_nm1_construct = (female_prefs[nm1g*n+idx] << 24)|idx;
            atomicMin(nm1+nm1g, potential_nm1_construct);
        } 
        __syncthreads();
        is_nm1 = (potential_nm1_construct == nm1[nm1g]);
        // find nm2
        if (is_nm1){
                // race condition?
                // horizontal nm2 pair 
                nm2graph[idx*3+0] = current_match[nm1g];
                //vertical nm2 pair
                nm2graph[(current_match[nm1g])*3+1] = partner;
                nm2graph[(current_match[nm1g])*3+2] = idx;

            }
#ifdef DEBUG
                printf("thread: %d ready to sync\n",idx);
#endif

        __syncthreads();
        // if we are nm1
        if (is_nm1) {
#ifdef DEBUG
                printf("thread: %d, final nm1g=%d\n",idx,nm1g);
#endif
            current_match[nm1g] = idx;
            match_current[idx] = nm1g;
            // if we are a column end 
            if (nm2graph[idx*3+2] == 255) {
#ifdef DEBUG
                printf("thread: %d, nm2graph[idx] = (%d,%d,%d)\n",idx,nm2graph[idx*3+0],nm2graph[idx*3+1],nm2graph[idx*3+2]);

#endif
                int nm2column = partner;
                //TODO optimize
                int nm2row= current_match[nm1g];
#ifdef DEBUG
                printf("thread: %d, nm2row=%d, nm2graph[nm2row] = (%d,%d,%d)\n",idx,nm2row,nm2graph[nm2row*3+0],nm2graph[nm2row*3+1],nm2graph[nm2row*3+2]);
#endif
                // if it's a single pair
                if (nm2graph[nm2row*3+0]==nm2graph[nm2row*3+2]){
                    nm2column = nm2graph[nm2row*3+1];
                }
                // if it's a chain
                else {
                    while(nm2graph[nm2row*3+0] != 255) {
#ifdef DEBUG
                        printf("thread: %d, nm2row=%d, nm2graph[nm2row] = (%d,%d,%d)\n",idx,nm2row,nm2graph[nm2row*3+0],nm2graph[nm2row*3+1],nm2graph[nm2row*3+2]);
#endif

                        nm2row = nm2graph[nm2row*3+0];
                    }
                }
#ifdef DEBUG
                printf("final nm2row=%d,nm2column=%d\n",nm2row,nm2column);
#endif
                current_match[nm2column] = nm2row;
                match_current[nm2row] = nm2column;

            }
                    



        }
    }
    // copy output out
    output[idx] = current_match[idx];
    delete[] local_mp;
}

/**
 * Host function that copies the data and launches GS on the CPU
 *
 */
void  pii(uint8_t n, uint8_t* male_prefs, uint8_t* female_prefs, uint8_t* output)
{
	uint8_t *d_male_prefs, *d_female_prefs;
	uint8_t* d_output;

	size_t prefs_size = sizeof(uint8_t)*n*n;
	CUDA_CHECK_RETURN(cudaMalloc((void **)&d_male_prefs, prefs_size));
	CUDA_CHECK_RETURN(cudaMalloc((void **)&d_female_prefs, prefs_size));
	CUDA_CHECK_RETURN(cudaMalloc((void **)&d_output, sizeof(uint8_t)*n));
	CUDA_CHECK_RETURN(cudaMemcpy(d_male_prefs, male_prefs, prefs_size, cudaMemcpyHostToDevice));
	CUDA_CHECK_RETURN(cudaMemcpy(d_female_prefs, female_prefs, prefs_size, cudaMemcpyHostToDevice));

#ifdef TIME_KERNEL
    struct timespec start, end;
    cudaDeviceSynchronize();
    clock_gettime(CLOCK_MONOTONIC, &start);	
#endif
    //knuth shuffle from sgb
    for (uint8_t k = 0;k < n; k++) {
        uint8_t j= rand() % (k+1);
        output[k] = output[j];
        output[j] = k;
    }
#ifdef DEBUG
    printf("male_prefs: \n ");
    for (int i = 0; i < n; i++){ 
        for (int j = 0; j < n; j++)
            printf("%hhd ",male_prefs[i*n+j]);
        printf("\n ");
    }
    printf("female_prefs: \n ");
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++)
            printf("%hhd ",female_prefs[i*n+j]);
        printf("\n ");
    }
    printf("permutation: ");
    for (int i = 0; i < n; i++) 
        printf("%hhd ",output[i]);
    printf("\n ");
#endif
	CUDA_CHECK_RETURN(cudaMemcpy(d_output, output, n*sizeof(uint8_t), cudaMemcpyHostToDevice));
    piiKernel<<<1,n,n*sizeof(int)+n*sizeof(int)+n*sizeof(unsigned int) + 3*n*sizeof(uint8_t) + n*n*sizeof(uint8_t)+1>>> (n, d_male_prefs,d_female_prefs, d_output);
#ifdef TIME_KERNEL
    cudaDeviceSynchronize();
    clock_gettime(CLOCK_MONOTONIC, &end);	
    long long unsigned int diff = (1000000000L) * (end.tv_sec - start.tv_sec) + end.tv_nsec - start.tv_nsec;
    printf("kernel time %llu\n",diff);
#endif
	CUDA_CHECK_RETURN(cudaMemcpy(output, d_output, sizeof(uint8_t)*n, cudaMemcpyDeviceToHost));
#ifdef DEBUG
    printf("result: ");
    for (int i = 0; i < n; i++) 
        printf("%hhd ",output[i]);
    printf("\n ");
#endif
	CUDA_CHECK_RETURN(cudaFree(d_male_prefs));
	CUDA_CHECK_RETURN(cudaFree(d_female_prefs));
	CUDA_CHECK_RETURN(cudaFree(d_output));
}
/**
 * Check the return value of the CUDA runtime API call and exit
 * the application if the call has failed.
 */
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
	if (err == cudaSuccess)
		return;
	std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
	exit (1);
}





	.file	"tmpxft_002657b5_00000000-6_pii.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.weak	nvtxEtiGetModuleFunctionTable_v3
	.hidden	nvtxEtiGetModuleFunctionTable_v3
	.type	nvtxEtiGetModuleFunctionTable_v3, @function
nvtxEtiGetModuleFunctionTable_v3:
.LFB7802:
	.cfi_startproc
	endbr64
	decl	%edi
	xorl	%eax, %eax
	cmpl	$5, %edi
	ja	.L1
	leaq	.L4(%rip), %rcx
	movslq	(%rcx,%rdi,4), %rax
	addq	%rcx, %rax
	notrack jmp	*%rax
	.section	.rodata.nvtxEtiGetModuleFunctionTable_v3,"aG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.align 4
	.align 4
.L4:
	.long	.L9-.L4
	.long	.L14-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
.L9:
	leaq	560+nvtxGlobals_v3(%rip), %rcx
	jmp	.L18
.L7:
	leaq	776+nvtxGlobals_v3(%rip), %rcx
	movl	$128, %eax
	jmp	.L8
.L6:
	leaq	904+nvtxGlobals_v3(%rip), %rcx
	jmp	.L19
.L5:
	leaq	968+nvtxGlobals_v3(%rip), %rcx
.L18:
	movl	$136, %eax
	jmp	.L8
.L3:
	leaq	1104+nvtxGlobals_v3(%rip), %rcx
.L19:
	movl	$64, %eax
	jmp	.L8
.L14:
	leaq	696+nvtxGlobals_v3(%rip), %rcx
	movl	$80, %eax
.L8:
	testq	%rdx, %rdx
	je	.L10
	shrl	$3, %eax
	decl	%eax
	movl	%eax, (%rdx)
.L10:
	testq	%rsi, %rsi
	jne	.L11
.L12:
	movl	$1, %eax
	ret
.L11:
	movq	%rcx, (%rsi)
	jmp	.L12
.L1:
	ret
	.cfi_endproc
.LFE7802:
	.size	nvtxEtiGetModuleFunctionTable_v3, .-nvtxEtiGetModuleFunctionTable_v3
	.section	.text.nvtxGetExportTable_v3,"axG",@progbits,nvtxGetExportTable_v3,comdat
	.weak	nvtxGetExportTable_v3
	.hidden	nvtxGetExportTable_v3
	.type	nvtxGetExportTable_v3, @function
nvtxGetExportTable_v3:
.LFB7803:
	.cfi_startproc
	endbr64
	leaq	8+nvtxGlobals_v3(%rip), %rax
	cmpl	$1, %edi
	je	.L21
	cmpl	$3, %edi
	leaq	16(%rax), %rax
	movl	$0, %edx
	cmovne	%rdx, %rax
.L21:
	ret
	.cfi_endproc
.LFE7803:
	.size	nvtxGetExportTable_v3, .-nvtxGetExportTable_v3
	.section	.text.nvtxEtiSetInjectionNvtxVersion_v3,"axG",@progbits,nvtxEtiSetInjectionNvtxVersion_v3,comdat
	.weak	nvtxEtiSetInjectionNvtxVersion_v3
	.hidden	nvtxEtiSetInjectionNvtxVersion_v3
	.type	nvtxEtiSetInjectionNvtxVersion_v3, @function
nvtxEtiSetInjectionNvtxVersion_v3:
.LFB7804:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE7804:
	.size	nvtxEtiSetInjectionNvtxVersion_v3, .-nvtxEtiSetInjectionNvtxVersion_v3
	.text
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB11962:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE11962:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" returned "
.LC1:
	.string	"("
.LC2:
	.string	") at "
.LC3:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/calebclark/reu/master/small_matching/pii.cu"
.LC4:
	.string	":"
	.text
	.type	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0:
.LFB13133:
	.cfi_startproc
	testl	%edx, %edx
	je	.L30
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %r12
	call	cudaGetErrorString@PLT
	movq	%r12, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L30:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	ret
	.cfi_endproc
.LFE13133:
	.size	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	.section	.text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,"axG",@progbits,_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,comdat
	.weak	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.hidden	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.type	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, @function
_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:
.LFB12377:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L34:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE12377:
	.size	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, .-_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.section	.text.nvtxSetInitFunctionsToNoops_v3,"axG",@progbits,nvtxSetInitFunctionsToNoops_v3,comdat
	.weak	nvtxSetInitFunctionsToNoops_v3
	.hidden	nvtxSetInitFunctionsToNoops_v3
	.type	nvtxSetInitFunctionsToNoops_v3, @function
nvtxSetInitFunctionsToNoops_v3:
.LFB7869:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	leaq	nvtxMarkEx_impl_init_v3(%rip), %rdx
	setne	%al
	cmpq	%rdx, 48+nvtxGlobals_v3(%rip)
	je	.L167
	testb	%al, %al
	je	.L39
.L167:
	xorl	%r10d, %r10d
	movq	%r10, 48+nvtxGlobals_v3(%rip)
.L39:
	leaq	nvtxMarkA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 56+nvtxGlobals_v3(%rip)
	je	.L168
	testb	%al, %al
	je	.L41
.L168:
	xorl	%r9d, %r9d
	movq	%r9, 56+nvtxGlobals_v3(%rip)
.L41:
	leaq	nvtxMarkW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 64+nvtxGlobals_v3(%rip)
	je	.L169
	testb	%al, %al
	je	.L43
.L169:
	xorl	%r8d, %r8d
	movq	%r8, 64+nvtxGlobals_v3(%rip)
.L43:
	leaq	nvtxRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 72+nvtxGlobals_v3(%rip)
	je	.L170
	testb	%al, %al
	je	.L45
.L170:
	xorl	%edi, %edi
	movq	%rdi, 72+nvtxGlobals_v3(%rip)
.L45:
	leaq	nvtxRangeStartA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 80+nvtxGlobals_v3(%rip)
	je	.L171
	testb	%al, %al
	je	.L47
.L171:
	xorl	%esi, %esi
	movq	%rsi, 80+nvtxGlobals_v3(%rip)
.L47:
	leaq	nvtxRangeStartW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 88+nvtxGlobals_v3(%rip)
	je	.L172
	testb	%al, %al
	je	.L49
.L172:
	xorl	%ecx, %ecx
	movq	%rcx, 88+nvtxGlobals_v3(%rip)
.L49:
	leaq	nvtxRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 96+nvtxGlobals_v3(%rip)
	je	.L173
	testb	%al, %al
	je	.L51
.L173:
	xorl	%edx, %edx
	movq	%rdx, 96+nvtxGlobals_v3(%rip)
.L51:
	leaq	nvtxRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 104+nvtxGlobals_v3(%rip)
	je	.L174
	testb	%al, %al
	je	.L53
.L174:
	xorl	%r11d, %r11d
	movq	%r11, 104+nvtxGlobals_v3(%rip)
.L53:
	leaq	nvtxRangePushA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 112+nvtxGlobals_v3(%rip)
	je	.L175
	testb	%al, %al
	je	.L55
.L175:
	xorl	%r10d, %r10d
	movq	%r10, 112+nvtxGlobals_v3(%rip)
.L55:
	leaq	nvtxRangePushW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 120+nvtxGlobals_v3(%rip)
	je	.L176
	testb	%al, %al
	je	.L57
.L176:
	xorl	%r9d, %r9d
	movq	%r9, 120+nvtxGlobals_v3(%rip)
.L57:
	leaq	nvtxRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 128+nvtxGlobals_v3(%rip)
	je	.L177
	testb	%al, %al
	je	.L59
.L177:
	xorl	%r8d, %r8d
	movq	%r8, 128+nvtxGlobals_v3(%rip)
.L59:
	leaq	nvtxNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 136+nvtxGlobals_v3(%rip)
	je	.L178
	testb	%al, %al
	je	.L61
.L178:
	xorl	%edi, %edi
	movq	%rdi, 136+nvtxGlobals_v3(%rip)
.L61:
	leaq	nvtxNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 144+nvtxGlobals_v3(%rip)
	je	.L179
	testb	%al, %al
	je	.L63
.L179:
	xorl	%esi, %esi
	movq	%rsi, 144+nvtxGlobals_v3(%rip)
.L63:
	leaq	nvtxNameOsThreadA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 152+nvtxGlobals_v3(%rip)
	je	.L180
	testb	%al, %al
	je	.L65
.L180:
	xorl	%ecx, %ecx
	movq	%rcx, 152+nvtxGlobals_v3(%rip)
.L65:
	leaq	nvtxNameOsThreadW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 160+nvtxGlobals_v3(%rip)
	je	.L181
	testb	%al, %al
	je	.L67
.L181:
	xorl	%edx, %edx
	movq	%rdx, 160+nvtxGlobals_v3(%rip)
.L67:
	leaq	nvtxNameCuDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 168+nvtxGlobals_v3(%rip)
	je	.L182
	testb	%al, %al
	je	.L69
.L182:
	xorl	%r11d, %r11d
	movq	%r11, 168+nvtxGlobals_v3(%rip)
.L69:
	leaq	nvtxNameCuDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 176+nvtxGlobals_v3(%rip)
	je	.L183
	testb	%al, %al
	je	.L71
.L183:
	xorl	%r10d, %r10d
	movq	%r10, 176+nvtxGlobals_v3(%rip)
.L71:
	leaq	nvtxNameCuContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 184+nvtxGlobals_v3(%rip)
	je	.L184
	testb	%al, %al
	je	.L73
.L184:
	xorl	%r9d, %r9d
	movq	%r9, 184+nvtxGlobals_v3(%rip)
.L73:
	leaq	nvtxNameCuContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 192+nvtxGlobals_v3(%rip)
	je	.L185
	testb	%al, %al
	je	.L75
.L185:
	xorl	%r8d, %r8d
	movq	%r8, 192+nvtxGlobals_v3(%rip)
.L75:
	leaq	nvtxNameCuStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 200+nvtxGlobals_v3(%rip)
	je	.L186
	testb	%al, %al
	je	.L77
.L186:
	xorl	%edi, %edi
	movq	%rdi, 200+nvtxGlobals_v3(%rip)
.L77:
	leaq	nvtxNameCuStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 208+nvtxGlobals_v3(%rip)
	je	.L187
	testb	%al, %al
	je	.L79
.L187:
	xorl	%esi, %esi
	movq	%rsi, 208+nvtxGlobals_v3(%rip)
.L79:
	leaq	nvtxNameCuEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 216+nvtxGlobals_v3(%rip)
	je	.L188
	testb	%al, %al
	je	.L81
.L188:
	xorl	%ecx, %ecx
	movq	%rcx, 216+nvtxGlobals_v3(%rip)
.L81:
	leaq	nvtxNameCuEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 224+nvtxGlobals_v3(%rip)
	je	.L189
	testb	%al, %al
	je	.L83
.L189:
	xorl	%edx, %edx
	movq	%rdx, 224+nvtxGlobals_v3(%rip)
.L83:
	leaq	nvtxNameClDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 232+nvtxGlobals_v3(%rip)
	je	.L190
	testb	%al, %al
	je	.L85
.L190:
	xorl	%r11d, %r11d
	movq	%r11, 232+nvtxGlobals_v3(%rip)
.L85:
	leaq	nvtxNameClDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 240+nvtxGlobals_v3(%rip)
	je	.L191
	testb	%al, %al
	je	.L87
.L191:
	xorl	%r10d, %r10d
	movq	%r10, 240+nvtxGlobals_v3(%rip)
.L87:
	leaq	nvtxNameClContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 248+nvtxGlobals_v3(%rip)
	je	.L192
	testb	%al, %al
	je	.L89
.L192:
	xorl	%r9d, %r9d
	movq	%r9, 248+nvtxGlobals_v3(%rip)
.L89:
	leaq	nvtxNameClContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 256+nvtxGlobals_v3(%rip)
	je	.L193
	testb	%al, %al
	je	.L91
.L193:
	xorl	%r8d, %r8d
	movq	%r8, 256+nvtxGlobals_v3(%rip)
.L91:
	leaq	nvtxNameClCommandQueueA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 264+nvtxGlobals_v3(%rip)
	je	.L194
	testb	%al, %al
	je	.L93
.L194:
	xorl	%edi, %edi
	movq	%rdi, 264+nvtxGlobals_v3(%rip)
.L93:
	leaq	nvtxNameClCommandQueueW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 272+nvtxGlobals_v3(%rip)
	je	.L195
	testb	%al, %al
	je	.L95
.L195:
	xorl	%esi, %esi
	movq	%rsi, 272+nvtxGlobals_v3(%rip)
.L95:
	leaq	nvtxNameClMemObjectA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 280+nvtxGlobals_v3(%rip)
	je	.L196
	testb	%al, %al
	je	.L97
.L196:
	xorl	%ecx, %ecx
	movq	%rcx, 280+nvtxGlobals_v3(%rip)
.L97:
	leaq	nvtxNameClMemObjectW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 288+nvtxGlobals_v3(%rip)
	je	.L197
	testb	%al, %al
	je	.L99
.L197:
	xorl	%edx, %edx
	movq	%rdx, 288+nvtxGlobals_v3(%rip)
.L99:
	leaq	nvtxNameClSamplerA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 296+nvtxGlobals_v3(%rip)
	je	.L198
	testb	%al, %al
	je	.L101
.L198:
	xorl	%r11d, %r11d
	movq	%r11, 296+nvtxGlobals_v3(%rip)
.L101:
	leaq	nvtxNameClSamplerW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 304+nvtxGlobals_v3(%rip)
	je	.L199
	testb	%al, %al
	je	.L103
.L199:
	xorl	%r10d, %r10d
	movq	%r10, 304+nvtxGlobals_v3(%rip)
.L103:
	leaq	nvtxNameClProgramA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 312+nvtxGlobals_v3(%rip)
	je	.L200
	testb	%al, %al
	je	.L105
.L200:
	xorl	%r9d, %r9d
	movq	%r9, 312+nvtxGlobals_v3(%rip)
.L105:
	leaq	nvtxNameClProgramW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 320+nvtxGlobals_v3(%rip)
	je	.L201
	testb	%al, %al
	je	.L107
.L201:
	xorl	%r8d, %r8d
	movq	%r8, 320+nvtxGlobals_v3(%rip)
.L107:
	leaq	nvtxNameClEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 328+nvtxGlobals_v3(%rip)
	je	.L202
	testb	%al, %al
	je	.L109
.L202:
	xorl	%edi, %edi
	movq	%rdi, 328+nvtxGlobals_v3(%rip)
.L109:
	leaq	nvtxNameClEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 336+nvtxGlobals_v3(%rip)
	je	.L203
	testb	%al, %al
	je	.L111
.L203:
	xorl	%esi, %esi
	movq	%rsi, 336+nvtxGlobals_v3(%rip)
.L111:
	leaq	nvtxNameCudaDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 344+nvtxGlobals_v3(%rip)
	je	.L204
	testb	%al, %al
	je	.L113
.L204:
	xorl	%ecx, %ecx
	movq	%rcx, 344+nvtxGlobals_v3(%rip)
.L113:
	leaq	nvtxNameCudaDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 352+nvtxGlobals_v3(%rip)
	je	.L205
	testb	%al, %al
	je	.L115
.L205:
	xorl	%edx, %edx
	movq	%rdx, 352+nvtxGlobals_v3(%rip)
.L115:
	leaq	nvtxNameCudaStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 360+nvtxGlobals_v3(%rip)
	je	.L206
	testb	%al, %al
	je	.L117
.L206:
	xorl	%r11d, %r11d
	movq	%r11, 360+nvtxGlobals_v3(%rip)
.L117:
	leaq	nvtxNameCudaStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 368+nvtxGlobals_v3(%rip)
	je	.L207
	testb	%al, %al
	je	.L119
.L207:
	xorl	%r10d, %r10d
	movq	%r10, 368+nvtxGlobals_v3(%rip)
.L119:
	leaq	nvtxNameCudaEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 376+nvtxGlobals_v3(%rip)
	je	.L208
	testb	%al, %al
	je	.L121
.L208:
	xorl	%r9d, %r9d
	movq	%r9, 376+nvtxGlobals_v3(%rip)
.L121:
	leaq	nvtxNameCudaEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 384+nvtxGlobals_v3(%rip)
	je	.L209
	testb	%al, %al
	je	.L123
.L209:
	xorl	%r8d, %r8d
	movq	%r8, 384+nvtxGlobals_v3(%rip)
.L123:
	leaq	nvtxDomainMarkEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 392+nvtxGlobals_v3(%rip)
	je	.L210
	testb	%al, %al
	je	.L125
.L210:
	xorl	%edi, %edi
	movq	%rdi, 392+nvtxGlobals_v3(%rip)
.L125:
	leaq	nvtxDomainRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 400+nvtxGlobals_v3(%rip)
	je	.L211
	testb	%al, %al
	je	.L127
.L211:
	xorl	%esi, %esi
	movq	%rsi, 400+nvtxGlobals_v3(%rip)
.L127:
	leaq	nvtxDomainRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 408+nvtxGlobals_v3(%rip)
	je	.L212
	testb	%al, %al
	je	.L129
.L212:
	xorl	%ecx, %ecx
	movq	%rcx, 408+nvtxGlobals_v3(%rip)
.L129:
	leaq	nvtxDomainRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 416+nvtxGlobals_v3(%rip)
	je	.L213
	testb	%al, %al
	je	.L131
.L213:
	xorl	%edx, %edx
	movq	%rdx, 416+nvtxGlobals_v3(%rip)
.L131:
	leaq	nvtxDomainRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 424+nvtxGlobals_v3(%rip)
	je	.L214
	testb	%al, %al
	je	.L133
.L214:
	xorl	%r11d, %r11d
	movq	%r11, 424+nvtxGlobals_v3(%rip)
.L133:
	leaq	nvtxDomainResourceCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 432+nvtxGlobals_v3(%rip)
	je	.L215
	testb	%al, %al
	je	.L135
.L215:
	xorl	%r10d, %r10d
	movq	%r10, 432+nvtxGlobals_v3(%rip)
.L135:
	leaq	nvtxDomainResourceDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 440+nvtxGlobals_v3(%rip)
	je	.L216
	testb	%al, %al
	je	.L137
.L216:
	xorl	%r9d, %r9d
	movq	%r9, 440+nvtxGlobals_v3(%rip)
.L137:
	leaq	nvtxDomainNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 448+nvtxGlobals_v3(%rip)
	je	.L217
	testb	%al, %al
	je	.L139
.L217:
	xorl	%r8d, %r8d
	movq	%r8, 448+nvtxGlobals_v3(%rip)
.L139:
	leaq	nvtxDomainNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 456+nvtxGlobals_v3(%rip)
	je	.L218
	testb	%al, %al
	je	.L141
.L218:
	xorl	%edi, %edi
	movq	%rdi, 456+nvtxGlobals_v3(%rip)
.L141:
	leaq	nvtxDomainRegisterStringA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 464+nvtxGlobals_v3(%rip)
	je	.L219
	testb	%al, %al
	je	.L143
.L219:
	xorl	%esi, %esi
	movq	%rsi, 464+nvtxGlobals_v3(%rip)
.L143:
	leaq	nvtxDomainRegisterStringW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 472+nvtxGlobals_v3(%rip)
	je	.L220
	testb	%al, %al
	je	.L145
.L220:
	xorl	%ecx, %ecx
	movq	%rcx, 472+nvtxGlobals_v3(%rip)
.L145:
	leaq	nvtxDomainCreateA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 480+nvtxGlobals_v3(%rip)
	je	.L221
	testb	%al, %al
	je	.L147
.L221:
	xorl	%edx, %edx
	movq	%rdx, 480+nvtxGlobals_v3(%rip)
.L147:
	leaq	nvtxDomainCreateW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 488+nvtxGlobals_v3(%rip)
	je	.L222
	testb	%al, %al
	je	.L149
.L222:
	xorl	%r11d, %r11d
	movq	%r11, 488+nvtxGlobals_v3(%rip)
.L149:
	leaq	nvtxDomainDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 496+nvtxGlobals_v3(%rip)
	je	.L223
	testb	%al, %al
	je	.L151
.L223:
	xorl	%r10d, %r10d
	movq	%r10, 496+nvtxGlobals_v3(%rip)
.L151:
	leaq	nvtxInitialize_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 504+nvtxGlobals_v3(%rip)
	je	.L224
	testb	%al, %al
	je	.L153
.L224:
	xorl	%r9d, %r9d
	movq	%r9, 504+nvtxGlobals_v3(%rip)
.L153:
	leaq	nvtxDomainSyncUserCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 512+nvtxGlobals_v3(%rip)
	je	.L225
	testb	%al, %al
	je	.L155
.L225:
	xorl	%r8d, %r8d
	movq	%r8, 512+nvtxGlobals_v3(%rip)
.L155:
	leaq	nvtxDomainSyncUserDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 520+nvtxGlobals_v3(%rip)
	je	.L226
	testb	%al, %al
	je	.L157
.L226:
	xorl	%edi, %edi
	movq	%rdi, 520+nvtxGlobals_v3(%rip)
.L157:
	leaq	nvtxDomainSyncUserAcquireStart_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 528+nvtxGlobals_v3(%rip)
	je	.L227
	testb	%al, %al
	je	.L159
.L227:
	xorl	%esi, %esi
	movq	%rsi, 528+nvtxGlobals_v3(%rip)
.L159:
	leaq	nvtxDomainSyncUserAcquireFailed_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 536+nvtxGlobals_v3(%rip)
	je	.L228
	testb	%al, %al
	je	.L161
.L228:
	xorl	%ecx, %ecx
	movq	%rcx, 536+nvtxGlobals_v3(%rip)
.L161:
	leaq	nvtxDomainSyncUserAcquireSuccess_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 544+nvtxGlobals_v3(%rip)
	je	.L229
	testb	%al, %al
	je	.L163
.L229:
	xorl	%edx, %edx
	movq	%rdx, 544+nvtxGlobals_v3(%rip)
.L163:
	leaq	nvtxDomainSyncUserReleasing_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 552+nvtxGlobals_v3(%rip)
	je	.L230
	testb	%al, %al
	je	.L38
.L230:
	xorl	%eax, %eax
	movq	%rax, 552+nvtxGlobals_v3(%rip)
.L38:
	ret
	.cfi_endproc
.LFE7869:
	.size	nvtxSetInitFunctionsToNoops_v3, .-nvtxSetInitFunctionsToNoops_v3
	.section	.rodata.nvtxInitializeInjectionLibrary_v3.str1.1,"aMS",@progbits,1
.LC5:
	.string	"NVTX_INJECTION64_PATH"
.LC6:
	.string	"InitializeInjectionNvtx2"
	.section	.text.nvtxInitializeInjectionLibrary_v3,"axG",@progbits,nvtxInitializeInjectionLibrary_v3,comdat
	.weak	nvtxInitializeInjectionLibrary_v3
	.hidden	nvtxInitializeInjectionLibrary_v3
	.type	nvtxInitializeInjectionLibrary_v3, @function
nvtxInitializeInjectionLibrary_v3:
.LFB7870:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	.LC5(%rip), %rdi
	call	getenv@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L424
	movl	$1, %esi
	movq	%rax, %rdi
	call	dlopen@PLT
	movl	$4, %edx
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L423
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	dlsym@PLT
	testq	%rax, %rax
	jne	.L426
	movq	%rbx, %rdi
	call	dlclose@PLT
	movl	$5, %edx
	jmp	.L423
.L424:
	movq	InitializeInjectionNvtx2_fnptr(%rip), %rax
	movl	$7, %edx
	testq	%rax, %rax
	je	.L423
.L426:
	leaq	nvtxGetExportTable_v3(%rip), %rdi
	call	*%rax
	xorl	%edx, %edx
	testl	%eax, %eax
	jne	.L423
	testq	%rbx, %rbx
	je	.L427
	movq	%rbx, %rdi
	call	dlclose@PLT
.L427:
	movl	$6, %edx
.L423:
	movl	%edx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7870:
	.size	nvtxInitializeInjectionLibrary_v3, .-nvtxInitializeInjectionLibrary_v3
	.section	.text.nvtxInitOnce_v3,"axG",@progbits,nvtxInitOnce_v3,comdat
	.weak	nvtxInitOnce_v3
	.hidden	nvtxInitOnce_v3
	.type	nvtxInitOnce_v3, @function
nvtxInitOnce_v3:
.LFB7871:
	.cfi_startproc
	endbr64
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L443
	pushq	%rdx
	.cfi_def_cfa_offset 16
	movl	$1, %eax
	xorl	%edx, %edx
	mfence
	lock cmpxchgl	%edx, nvtxGlobals_v3(%rip)
	testl	%eax, %eax
	jne	.L446
	call	nvtxInitializeInjectionLibrary_v3
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	call	nvtxSetInitFunctionsToNoops_v3
	movl	$2, %eax
	mfence
	xchgl	nvtxGlobals_v3(%rip), %eax
	jmp	.L435
.L446:
	mfence
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L435
	call	sched_yield@PLT
	jmp	.L446
.L435:
	popq	%rax
	.cfi_def_cfa_offset 8
	ret
.L443:
	ret
	.cfi_endproc
.LFE7871:
	.size	nvtxInitOnce_v3, .-nvtxInitOnce_v3
	.section	.text.nvtxDomainSyncUserReleasing_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserReleasing_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserReleasing_impl_init_v3
	.hidden	nvtxDomainSyncUserReleasing_impl_init_v3
	.type	nvtxDomainSyncUserReleasing_impl_init_v3, @function
nvtxDomainSyncUserReleasing_impl_init_v3:
.LFB7868:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	552+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L447
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L447:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7868:
	.size	nvtxDomainSyncUserReleasing_impl_init_v3, .-nvtxDomainSyncUserReleasing_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireSuccess_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireSuccess_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.type	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, @function
nvtxDomainSyncUserAcquireSuccess_impl_init_v3:
.LFB7867:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	544+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L450
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L450:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7867:
	.size	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, .-nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireFailed_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireFailed_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.type	nvtxDomainSyncUserAcquireFailed_impl_init_v3, @function
nvtxDomainSyncUserAcquireFailed_impl_init_v3:
.LFB7866:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	536+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L453
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L453:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7866:
	.size	nvtxDomainSyncUserAcquireFailed_impl_init_v3, .-nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireStart_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireStart_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.type	nvtxDomainSyncUserAcquireStart_impl_init_v3, @function
nvtxDomainSyncUserAcquireStart_impl_init_v3:
.LFB7865:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	528+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L456
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L456:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7865:
	.size	nvtxDomainSyncUserAcquireStart_impl_init_v3, .-nvtxDomainSyncUserAcquireStart_impl_init_v3
	.section	.text.nvtxDomainSyncUserDestroy_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserDestroy_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserDestroy_impl_init_v3
	.hidden	nvtxDomainSyncUserDestroy_impl_init_v3
	.type	nvtxDomainSyncUserDestroy_impl_init_v3, @function
nvtxDomainSyncUserDestroy_impl_init_v3:
.LFB7864:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	520+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L459
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L459:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7864:
	.size	nvtxDomainSyncUserDestroy_impl_init_v3, .-nvtxDomainSyncUserDestroy_impl_init_v3
	.section	.text.nvtxDomainSyncUserCreate_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserCreate_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserCreate_impl_init_v3
	.hidden	nvtxDomainSyncUserCreate_impl_init_v3
	.type	nvtxDomainSyncUserCreate_impl_init_v3, @function
nvtxDomainSyncUserCreate_impl_init_v3:
.LFB7863:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	512+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L463
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L463:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7863:
	.size	nvtxDomainSyncUserCreate_impl_init_v3, .-nvtxDomainSyncUserCreate_impl_init_v3
	.section	.text.nvtxInitialize_impl_init_v3,"axG",@progbits,nvtxInitialize_impl_init_v3,comdat
	.weak	nvtxInitialize_impl_init_v3
	.hidden	nvtxInitialize_impl_init_v3
	.type	nvtxInitialize_impl_init_v3, @function
nvtxInitialize_impl_init_v3:
.LFB7834:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	504+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L465
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L465:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7834:
	.size	nvtxInitialize_impl_init_v3, .-nvtxInitialize_impl_init_v3
	.section	.text.nvtxDomainDestroy_impl_init_v3,"axG",@progbits,nvtxDomainDestroy_impl_init_v3,comdat
	.weak	nvtxDomainDestroy_impl_init_v3
	.hidden	nvtxDomainDestroy_impl_init_v3
	.type	nvtxDomainDestroy_impl_init_v3, @function
nvtxDomainDestroy_impl_init_v3:
.LFB7833:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	496+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L468
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L468:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7833:
	.size	nvtxDomainDestroy_impl_init_v3, .-nvtxDomainDestroy_impl_init_v3
	.section	.text.nvtxDomainCreateW_impl_init_v3,"axG",@progbits,nvtxDomainCreateW_impl_init_v3,comdat
	.weak	nvtxDomainCreateW_impl_init_v3
	.hidden	nvtxDomainCreateW_impl_init_v3
	.type	nvtxDomainCreateW_impl_init_v3, @function
nvtxDomainCreateW_impl_init_v3:
.LFB7832:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	488+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L472
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L472:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7832:
	.size	nvtxDomainCreateW_impl_init_v3, .-nvtxDomainCreateW_impl_init_v3
	.section	.text.nvtxDomainCreateA_impl_init_v3,"axG",@progbits,nvtxDomainCreateA_impl_init_v3,comdat
	.weak	nvtxDomainCreateA_impl_init_v3
	.hidden	nvtxDomainCreateA_impl_init_v3
	.type	nvtxDomainCreateA_impl_init_v3, @function
nvtxDomainCreateA_impl_init_v3:
.LFB7831:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	480+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L475
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L475:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7831:
	.size	nvtxDomainCreateA_impl_init_v3, .-nvtxDomainCreateA_impl_init_v3
	.section	.text.nvtxDomainRegisterStringW_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringW_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringW_impl_init_v3
	.hidden	nvtxDomainRegisterStringW_impl_init_v3
	.type	nvtxDomainRegisterStringW_impl_init_v3, @function
nvtxDomainRegisterStringW_impl_init_v3:
.LFB7830:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	472+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L478
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L478:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7830:
	.size	nvtxDomainRegisterStringW_impl_init_v3, .-nvtxDomainRegisterStringW_impl_init_v3
	.section	.text.nvtxDomainRegisterStringA_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringA_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringA_impl_init_v3
	.hidden	nvtxDomainRegisterStringA_impl_init_v3
	.type	nvtxDomainRegisterStringA_impl_init_v3, @function
nvtxDomainRegisterStringA_impl_init_v3:
.LFB7829:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	464+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L481
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L481:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7829:
	.size	nvtxDomainRegisterStringA_impl_init_v3, .-nvtxDomainRegisterStringA_impl_init_v3
	.section	.text.nvtxDomainNameCategoryW_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryW_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryW_impl_init_v3
	.hidden	nvtxDomainNameCategoryW_impl_init_v3
	.type	nvtxDomainNameCategoryW_impl_init_v3, @function
nvtxDomainNameCategoryW_impl_init_v3:
.LFB7828:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	456+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L483
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L483:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7828:
	.size	nvtxDomainNameCategoryW_impl_init_v3, .-nvtxDomainNameCategoryW_impl_init_v3
	.section	.text.nvtxDomainNameCategoryA_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryA_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryA_impl_init_v3
	.hidden	nvtxDomainNameCategoryA_impl_init_v3
	.type	nvtxDomainNameCategoryA_impl_init_v3, @function
nvtxDomainNameCategoryA_impl_init_v3:
.LFB7827:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	448+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L486
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L486:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7827:
	.size	nvtxDomainNameCategoryA_impl_init_v3, .-nvtxDomainNameCategoryA_impl_init_v3
	.section	.text.nvtxDomainResourceDestroy_impl_init_v3,"axG",@progbits,nvtxDomainResourceDestroy_impl_init_v3,comdat
	.weak	nvtxDomainResourceDestroy_impl_init_v3
	.hidden	nvtxDomainResourceDestroy_impl_init_v3
	.type	nvtxDomainResourceDestroy_impl_init_v3, @function
nvtxDomainResourceDestroy_impl_init_v3:
.LFB7826:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	440+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L489
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L489:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7826:
	.size	nvtxDomainResourceDestroy_impl_init_v3, .-nvtxDomainResourceDestroy_impl_init_v3
	.section	.text.nvtxDomainResourceCreate_impl_init_v3,"axG",@progbits,nvtxDomainResourceCreate_impl_init_v3,comdat
	.weak	nvtxDomainResourceCreate_impl_init_v3
	.hidden	nvtxDomainResourceCreate_impl_init_v3
	.type	nvtxDomainResourceCreate_impl_init_v3, @function
nvtxDomainResourceCreate_impl_init_v3:
.LFB7825:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	432+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L493
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L493:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7825:
	.size	nvtxDomainResourceCreate_impl_init_v3, .-nvtxDomainResourceCreate_impl_init_v3
	.section	.text.nvtxDomainRangePop_impl_init_v3,"axG",@progbits,nvtxDomainRangePop_impl_init_v3,comdat
	.weak	nvtxDomainRangePop_impl_init_v3
	.hidden	nvtxDomainRangePop_impl_init_v3
	.type	nvtxDomainRangePop_impl_init_v3, @function
nvtxDomainRangePop_impl_init_v3:
.LFB7824:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	424+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L496
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L496:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7824:
	.size	nvtxDomainRangePop_impl_init_v3, .-nvtxDomainRangePop_impl_init_v3
	.section	.text.nvtxDomainRangePushEx_impl_init_v3,"axG",@progbits,nvtxDomainRangePushEx_impl_init_v3,comdat
	.weak	nvtxDomainRangePushEx_impl_init_v3
	.hidden	nvtxDomainRangePushEx_impl_init_v3
	.type	nvtxDomainRangePushEx_impl_init_v3, @function
nvtxDomainRangePushEx_impl_init_v3:
.LFB7823:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	416+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L499
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L499:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7823:
	.size	nvtxDomainRangePushEx_impl_init_v3, .-nvtxDomainRangePushEx_impl_init_v3
	.section	.text.nvtxDomainRangeEnd_impl_init_v3,"axG",@progbits,nvtxDomainRangeEnd_impl_init_v3,comdat
	.weak	nvtxDomainRangeEnd_impl_init_v3
	.hidden	nvtxDomainRangeEnd_impl_init_v3
	.type	nvtxDomainRangeEnd_impl_init_v3, @function
nvtxDomainRangeEnd_impl_init_v3:
.LFB7822:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	408+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L501
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L501:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7822:
	.size	nvtxDomainRangeEnd_impl_init_v3, .-nvtxDomainRangeEnd_impl_init_v3
	.section	.text.nvtxDomainRangeStartEx_impl_init_v3,"axG",@progbits,nvtxDomainRangeStartEx_impl_init_v3,comdat
	.weak	nvtxDomainRangeStartEx_impl_init_v3
	.hidden	nvtxDomainRangeStartEx_impl_init_v3
	.type	nvtxDomainRangeStartEx_impl_init_v3, @function
nvtxDomainRangeStartEx_impl_init_v3:
.LFB7821:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	400+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L505
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L505:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7821:
	.size	nvtxDomainRangeStartEx_impl_init_v3, .-nvtxDomainRangeStartEx_impl_init_v3
	.section	.text.nvtxDomainMarkEx_impl_init_v3,"axG",@progbits,nvtxDomainMarkEx_impl_init_v3,comdat
	.weak	nvtxDomainMarkEx_impl_init_v3
	.hidden	nvtxDomainMarkEx_impl_init_v3
	.type	nvtxDomainMarkEx_impl_init_v3, @function
nvtxDomainMarkEx_impl_init_v3:
.LFB7820:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	392+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L507
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L507:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7820:
	.size	nvtxDomainMarkEx_impl_init_v3, .-nvtxDomainMarkEx_impl_init_v3
	.section	.text.nvtxNameCudaEventW_impl_init_v3,"axG",@progbits,nvtxNameCudaEventW_impl_init_v3,comdat
	.weak	nvtxNameCudaEventW_impl_init_v3
	.hidden	nvtxNameCudaEventW_impl_init_v3
	.type	nvtxNameCudaEventW_impl_init_v3, @function
nvtxNameCudaEventW_impl_init_v3:
.LFB7848:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	384+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L510
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L510:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7848:
	.size	nvtxNameCudaEventW_impl_init_v3, .-nvtxNameCudaEventW_impl_init_v3
	.section	.text.nvtxNameCudaEventA_impl_init_v3,"axG",@progbits,nvtxNameCudaEventA_impl_init_v3,comdat
	.weak	nvtxNameCudaEventA_impl_init_v3
	.hidden	nvtxNameCudaEventA_impl_init_v3
	.type	nvtxNameCudaEventA_impl_init_v3, @function
nvtxNameCudaEventA_impl_init_v3:
.LFB7847:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	376+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L513
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L513:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7847:
	.size	nvtxNameCudaEventA_impl_init_v3, .-nvtxNameCudaEventA_impl_init_v3
	.section	.text.nvtxNameCudaStreamW_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamW_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamW_impl_init_v3
	.hidden	nvtxNameCudaStreamW_impl_init_v3
	.type	nvtxNameCudaStreamW_impl_init_v3, @function
nvtxNameCudaStreamW_impl_init_v3:
.LFB7846:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	368+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L516
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L516:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7846:
	.size	nvtxNameCudaStreamW_impl_init_v3, .-nvtxNameCudaStreamW_impl_init_v3
	.section	.text.nvtxNameCudaStreamA_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamA_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamA_impl_init_v3
	.hidden	nvtxNameCudaStreamA_impl_init_v3
	.type	nvtxNameCudaStreamA_impl_init_v3, @function
nvtxNameCudaStreamA_impl_init_v3:
.LFB7845:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	360+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L519
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L519:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7845:
	.size	nvtxNameCudaStreamA_impl_init_v3, .-nvtxNameCudaStreamA_impl_init_v3
	.section	.text.nvtxNameCudaDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceW_impl_init_v3
	.hidden	nvtxNameCudaDeviceW_impl_init_v3
	.type	nvtxNameCudaDeviceW_impl_init_v3, @function
nvtxNameCudaDeviceW_impl_init_v3:
.LFB7844:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	352+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L522
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L522:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7844:
	.size	nvtxNameCudaDeviceW_impl_init_v3, .-nvtxNameCudaDeviceW_impl_init_v3
	.section	.text.nvtxNameCudaDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceA_impl_init_v3
	.hidden	nvtxNameCudaDeviceA_impl_init_v3
	.type	nvtxNameCudaDeviceA_impl_init_v3, @function
nvtxNameCudaDeviceA_impl_init_v3:
.LFB7843:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	344+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L525
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L525:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7843:
	.size	nvtxNameCudaDeviceA_impl_init_v3, .-nvtxNameCudaDeviceA_impl_init_v3
	.section	.text.nvtxNameClEventW_impl_init_v3,"axG",@progbits,nvtxNameClEventW_impl_init_v3,comdat
	.weak	nvtxNameClEventW_impl_init_v3
	.hidden	nvtxNameClEventW_impl_init_v3
	.type	nvtxNameClEventW_impl_init_v3, @function
nvtxNameClEventW_impl_init_v3:
.LFB7862:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	336+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L528
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L528:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7862:
	.size	nvtxNameClEventW_impl_init_v3, .-nvtxNameClEventW_impl_init_v3
	.section	.text.nvtxNameClEventA_impl_init_v3,"axG",@progbits,nvtxNameClEventA_impl_init_v3,comdat
	.weak	nvtxNameClEventA_impl_init_v3
	.hidden	nvtxNameClEventA_impl_init_v3
	.type	nvtxNameClEventA_impl_init_v3, @function
nvtxNameClEventA_impl_init_v3:
.LFB7861:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	328+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L531
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L531:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7861:
	.size	nvtxNameClEventA_impl_init_v3, .-nvtxNameClEventA_impl_init_v3
	.section	.text.nvtxNameClProgramW_impl_init_v3,"axG",@progbits,nvtxNameClProgramW_impl_init_v3,comdat
	.weak	nvtxNameClProgramW_impl_init_v3
	.hidden	nvtxNameClProgramW_impl_init_v3
	.type	nvtxNameClProgramW_impl_init_v3, @function
nvtxNameClProgramW_impl_init_v3:
.LFB7860:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	320+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L534
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L534:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7860:
	.size	nvtxNameClProgramW_impl_init_v3, .-nvtxNameClProgramW_impl_init_v3
	.section	.text.nvtxNameClProgramA_impl_init_v3,"axG",@progbits,nvtxNameClProgramA_impl_init_v3,comdat
	.weak	nvtxNameClProgramA_impl_init_v3
	.hidden	nvtxNameClProgramA_impl_init_v3
	.type	nvtxNameClProgramA_impl_init_v3, @function
nvtxNameClProgramA_impl_init_v3:
.LFB7859:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	312+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L537
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L537:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7859:
	.size	nvtxNameClProgramA_impl_init_v3, .-nvtxNameClProgramA_impl_init_v3
	.section	.text.nvtxNameClSamplerW_impl_init_v3,"axG",@progbits,nvtxNameClSamplerW_impl_init_v3,comdat
	.weak	nvtxNameClSamplerW_impl_init_v3
	.hidden	nvtxNameClSamplerW_impl_init_v3
	.type	nvtxNameClSamplerW_impl_init_v3, @function
nvtxNameClSamplerW_impl_init_v3:
.LFB7858:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	304+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L540
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L540:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7858:
	.size	nvtxNameClSamplerW_impl_init_v3, .-nvtxNameClSamplerW_impl_init_v3
	.section	.text.nvtxNameClSamplerA_impl_init_v3,"axG",@progbits,nvtxNameClSamplerA_impl_init_v3,comdat
	.weak	nvtxNameClSamplerA_impl_init_v3
	.hidden	nvtxNameClSamplerA_impl_init_v3
	.type	nvtxNameClSamplerA_impl_init_v3, @function
nvtxNameClSamplerA_impl_init_v3:
.LFB7857:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	296+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L543
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L543:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7857:
	.size	nvtxNameClSamplerA_impl_init_v3, .-nvtxNameClSamplerA_impl_init_v3
	.section	.text.nvtxNameClMemObjectW_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectW_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectW_impl_init_v3
	.hidden	nvtxNameClMemObjectW_impl_init_v3
	.type	nvtxNameClMemObjectW_impl_init_v3, @function
nvtxNameClMemObjectW_impl_init_v3:
.LFB7856:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	288+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L546
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L546:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7856:
	.size	nvtxNameClMemObjectW_impl_init_v3, .-nvtxNameClMemObjectW_impl_init_v3
	.section	.text.nvtxNameClMemObjectA_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectA_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectA_impl_init_v3
	.hidden	nvtxNameClMemObjectA_impl_init_v3
	.type	nvtxNameClMemObjectA_impl_init_v3, @function
nvtxNameClMemObjectA_impl_init_v3:
.LFB7855:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	280+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L549
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L549:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7855:
	.size	nvtxNameClMemObjectA_impl_init_v3, .-nvtxNameClMemObjectA_impl_init_v3
	.section	.text.nvtxNameClCommandQueueW_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueW_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueW_impl_init_v3
	.hidden	nvtxNameClCommandQueueW_impl_init_v3
	.type	nvtxNameClCommandQueueW_impl_init_v3, @function
nvtxNameClCommandQueueW_impl_init_v3:
.LFB7854:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	272+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L552
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L552:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7854:
	.size	nvtxNameClCommandQueueW_impl_init_v3, .-nvtxNameClCommandQueueW_impl_init_v3
	.section	.text.nvtxNameClCommandQueueA_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueA_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueA_impl_init_v3
	.hidden	nvtxNameClCommandQueueA_impl_init_v3
	.type	nvtxNameClCommandQueueA_impl_init_v3, @function
nvtxNameClCommandQueueA_impl_init_v3:
.LFB7853:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	264+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L555
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L555:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7853:
	.size	nvtxNameClCommandQueueA_impl_init_v3, .-nvtxNameClCommandQueueA_impl_init_v3
	.section	.text.nvtxNameClContextW_impl_init_v3,"axG",@progbits,nvtxNameClContextW_impl_init_v3,comdat
	.weak	nvtxNameClContextW_impl_init_v3
	.hidden	nvtxNameClContextW_impl_init_v3
	.type	nvtxNameClContextW_impl_init_v3, @function
nvtxNameClContextW_impl_init_v3:
.LFB7852:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	256+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L558
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L558:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7852:
	.size	nvtxNameClContextW_impl_init_v3, .-nvtxNameClContextW_impl_init_v3
	.section	.text.nvtxNameClContextA_impl_init_v3,"axG",@progbits,nvtxNameClContextA_impl_init_v3,comdat
	.weak	nvtxNameClContextA_impl_init_v3
	.hidden	nvtxNameClContextA_impl_init_v3
	.type	nvtxNameClContextA_impl_init_v3, @function
nvtxNameClContextA_impl_init_v3:
.LFB7851:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	248+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L561
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L561:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7851:
	.size	nvtxNameClContextA_impl_init_v3, .-nvtxNameClContextA_impl_init_v3
	.section	.text.nvtxNameClDeviceW_impl_init_v3,"axG",@progbits,nvtxNameClDeviceW_impl_init_v3,comdat
	.weak	nvtxNameClDeviceW_impl_init_v3
	.hidden	nvtxNameClDeviceW_impl_init_v3
	.type	nvtxNameClDeviceW_impl_init_v3, @function
nvtxNameClDeviceW_impl_init_v3:
.LFB7850:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	240+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L564
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L564:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7850:
	.size	nvtxNameClDeviceW_impl_init_v3, .-nvtxNameClDeviceW_impl_init_v3
	.section	.text.nvtxNameClDeviceA_impl_init_v3,"axG",@progbits,nvtxNameClDeviceA_impl_init_v3,comdat
	.weak	nvtxNameClDeviceA_impl_init_v3
	.hidden	nvtxNameClDeviceA_impl_init_v3
	.type	nvtxNameClDeviceA_impl_init_v3, @function
nvtxNameClDeviceA_impl_init_v3:
.LFB7849:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	232+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L567
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L567:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7849:
	.size	nvtxNameClDeviceA_impl_init_v3, .-nvtxNameClDeviceA_impl_init_v3
	.section	.text.nvtxNameCuEventW_impl_init_v3,"axG",@progbits,nvtxNameCuEventW_impl_init_v3,comdat
	.weak	nvtxNameCuEventW_impl_init_v3
	.hidden	nvtxNameCuEventW_impl_init_v3
	.type	nvtxNameCuEventW_impl_init_v3, @function
nvtxNameCuEventW_impl_init_v3:
.LFB7842:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	224+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L570
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L570:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7842:
	.size	nvtxNameCuEventW_impl_init_v3, .-nvtxNameCuEventW_impl_init_v3
	.section	.text.nvtxNameCuEventA_impl_init_v3,"axG",@progbits,nvtxNameCuEventA_impl_init_v3,comdat
	.weak	nvtxNameCuEventA_impl_init_v3
	.hidden	nvtxNameCuEventA_impl_init_v3
	.type	nvtxNameCuEventA_impl_init_v3, @function
nvtxNameCuEventA_impl_init_v3:
.LFB7841:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	216+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L573
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L573:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7841:
	.size	nvtxNameCuEventA_impl_init_v3, .-nvtxNameCuEventA_impl_init_v3
	.section	.text.nvtxNameCuStreamW_impl_init_v3,"axG",@progbits,nvtxNameCuStreamW_impl_init_v3,comdat
	.weak	nvtxNameCuStreamW_impl_init_v3
	.hidden	nvtxNameCuStreamW_impl_init_v3
	.type	nvtxNameCuStreamW_impl_init_v3, @function
nvtxNameCuStreamW_impl_init_v3:
.LFB7840:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	208+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L576
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L576:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7840:
	.size	nvtxNameCuStreamW_impl_init_v3, .-nvtxNameCuStreamW_impl_init_v3
	.section	.text.nvtxNameCuStreamA_impl_init_v3,"axG",@progbits,nvtxNameCuStreamA_impl_init_v3,comdat
	.weak	nvtxNameCuStreamA_impl_init_v3
	.hidden	nvtxNameCuStreamA_impl_init_v3
	.type	nvtxNameCuStreamA_impl_init_v3, @function
nvtxNameCuStreamA_impl_init_v3:
.LFB7839:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	200+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L579
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L579:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7839:
	.size	nvtxNameCuStreamA_impl_init_v3, .-nvtxNameCuStreamA_impl_init_v3
	.section	.text.nvtxNameCuContextW_impl_init_v3,"axG",@progbits,nvtxNameCuContextW_impl_init_v3,comdat
	.weak	nvtxNameCuContextW_impl_init_v3
	.hidden	nvtxNameCuContextW_impl_init_v3
	.type	nvtxNameCuContextW_impl_init_v3, @function
nvtxNameCuContextW_impl_init_v3:
.LFB7838:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	192+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L582
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L582:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7838:
	.size	nvtxNameCuContextW_impl_init_v3, .-nvtxNameCuContextW_impl_init_v3
	.section	.text.nvtxNameCuContextA_impl_init_v3,"axG",@progbits,nvtxNameCuContextA_impl_init_v3,comdat
	.weak	nvtxNameCuContextA_impl_init_v3
	.hidden	nvtxNameCuContextA_impl_init_v3
	.type	nvtxNameCuContextA_impl_init_v3, @function
nvtxNameCuContextA_impl_init_v3:
.LFB7837:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	184+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L585
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L585:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7837:
	.size	nvtxNameCuContextA_impl_init_v3, .-nvtxNameCuContextA_impl_init_v3
	.section	.text.nvtxNameCuDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceW_impl_init_v3
	.hidden	nvtxNameCuDeviceW_impl_init_v3
	.type	nvtxNameCuDeviceW_impl_init_v3, @function
nvtxNameCuDeviceW_impl_init_v3:
.LFB7836:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	176+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L588
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L588:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7836:
	.size	nvtxNameCuDeviceW_impl_init_v3, .-nvtxNameCuDeviceW_impl_init_v3
	.section	.text.nvtxNameCuDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceA_impl_init_v3
	.hidden	nvtxNameCuDeviceA_impl_init_v3
	.type	nvtxNameCuDeviceA_impl_init_v3, @function
nvtxNameCuDeviceA_impl_init_v3:
.LFB7835:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	168+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L591
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L591:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7835:
	.size	nvtxNameCuDeviceA_impl_init_v3, .-nvtxNameCuDeviceA_impl_init_v3
	.section	.text.nvtxNameOsThreadW_impl_init_v3,"axG",@progbits,nvtxNameOsThreadW_impl_init_v3,comdat
	.weak	nvtxNameOsThreadW_impl_init_v3
	.hidden	nvtxNameOsThreadW_impl_init_v3
	.type	nvtxNameOsThreadW_impl_init_v3, @function
nvtxNameOsThreadW_impl_init_v3:
.LFB7819:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	160+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L594
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L594:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7819:
	.size	nvtxNameOsThreadW_impl_init_v3, .-nvtxNameOsThreadW_impl_init_v3
	.section	.text.nvtxNameOsThreadA_impl_init_v3,"axG",@progbits,nvtxNameOsThreadA_impl_init_v3,comdat
	.weak	nvtxNameOsThreadA_impl_init_v3
	.hidden	nvtxNameOsThreadA_impl_init_v3
	.type	nvtxNameOsThreadA_impl_init_v3, @function
nvtxNameOsThreadA_impl_init_v3:
.LFB7818:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	152+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L597
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L597:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7818:
	.size	nvtxNameOsThreadA_impl_init_v3, .-nvtxNameOsThreadA_impl_init_v3
	.section	.text.nvtxNameCategoryW_impl_init_v3,"axG",@progbits,nvtxNameCategoryW_impl_init_v3,comdat
	.weak	nvtxNameCategoryW_impl_init_v3
	.hidden	nvtxNameCategoryW_impl_init_v3
	.type	nvtxNameCategoryW_impl_init_v3, @function
nvtxNameCategoryW_impl_init_v3:
.LFB7817:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	144+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L600
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L600:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7817:
	.size	nvtxNameCategoryW_impl_init_v3, .-nvtxNameCategoryW_impl_init_v3
	.section	.text.nvtxNameCategoryA_impl_init_v3,"axG",@progbits,nvtxNameCategoryA_impl_init_v3,comdat
	.weak	nvtxNameCategoryA_impl_init_v3
	.hidden	nvtxNameCategoryA_impl_init_v3
	.type	nvtxNameCategoryA_impl_init_v3, @function
nvtxNameCategoryA_impl_init_v3:
.LFB7816:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	136+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L603
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L603:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7816:
	.size	nvtxNameCategoryA_impl_init_v3, .-nvtxNameCategoryA_impl_init_v3
	.section	.text.nvtxRangePop_impl_init_v3,"axG",@progbits,nvtxRangePop_impl_init_v3,comdat
	.weak	nvtxRangePop_impl_init_v3
	.hidden	nvtxRangePop_impl_init_v3
	.type	nvtxRangePop_impl_init_v3, @function
nvtxRangePop_impl_init_v3:
.LFB7815:
	.cfi_startproc
	endbr64
	pushq	%rsi
	.cfi_def_cfa_offset 16
	call	nvtxInitOnce_v3
	movq	128+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L607
	popq	%rcx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L607:
	.cfi_restore_state
	movl	$-2, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7815:
	.size	nvtxRangePop_impl_init_v3, .-nvtxRangePop_impl_init_v3
	.section	.text.nvtxRangePushW_impl_init_v3,"axG",@progbits,nvtxRangePushW_impl_init_v3,comdat
	.weak	nvtxRangePushW_impl_init_v3
	.hidden	nvtxRangePushW_impl_init_v3
	.type	nvtxRangePushW_impl_init_v3, @function
nvtxRangePushW_impl_init_v3:
.LFB7814:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	120+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L610
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L610:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7814:
	.size	nvtxRangePushW_impl_init_v3, .-nvtxRangePushW_impl_init_v3
	.section	.text.nvtxRangePushA_impl_init_v3,"axG",@progbits,nvtxRangePushA_impl_init_v3,comdat
	.weak	nvtxRangePushA_impl_init_v3
	.hidden	nvtxRangePushA_impl_init_v3
	.type	nvtxRangePushA_impl_init_v3, @function
nvtxRangePushA_impl_init_v3:
.LFB7813:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	112+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L613
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L613:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7813:
	.size	nvtxRangePushA_impl_init_v3, .-nvtxRangePushA_impl_init_v3
	.section	.text.nvtxRangePushEx_impl_init_v3,"axG",@progbits,nvtxRangePushEx_impl_init_v3,comdat
	.weak	nvtxRangePushEx_impl_init_v3
	.hidden	nvtxRangePushEx_impl_init_v3
	.type	nvtxRangePushEx_impl_init_v3, @function
nvtxRangePushEx_impl_init_v3:
.LFB7812:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	104+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L616
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L616:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7812:
	.size	nvtxRangePushEx_impl_init_v3, .-nvtxRangePushEx_impl_init_v3
	.section	.text.nvtxRangeEnd_impl_init_v3,"axG",@progbits,nvtxRangeEnd_impl_init_v3,comdat
	.weak	nvtxRangeEnd_impl_init_v3
	.hidden	nvtxRangeEnd_impl_init_v3
	.type	nvtxRangeEnd_impl_init_v3, @function
nvtxRangeEnd_impl_init_v3:
.LFB7811:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	96+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L618
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L618:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7811:
	.size	nvtxRangeEnd_impl_init_v3, .-nvtxRangeEnd_impl_init_v3
	.section	.text.nvtxRangeStartW_impl_init_v3,"axG",@progbits,nvtxRangeStartW_impl_init_v3,comdat
	.weak	nvtxRangeStartW_impl_init_v3
	.hidden	nvtxRangeStartW_impl_init_v3
	.type	nvtxRangeStartW_impl_init_v3, @function
nvtxRangeStartW_impl_init_v3:
.LFB7810:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	88+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L622
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L622:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7810:
	.size	nvtxRangeStartW_impl_init_v3, .-nvtxRangeStartW_impl_init_v3
	.section	.text.nvtxRangeStartA_impl_init_v3,"axG",@progbits,nvtxRangeStartA_impl_init_v3,comdat
	.weak	nvtxRangeStartA_impl_init_v3
	.hidden	nvtxRangeStartA_impl_init_v3
	.type	nvtxRangeStartA_impl_init_v3, @function
nvtxRangeStartA_impl_init_v3:
.LFB7809:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	80+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L625
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L625:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7809:
	.size	nvtxRangeStartA_impl_init_v3, .-nvtxRangeStartA_impl_init_v3
	.section	.text.nvtxRangeStartEx_impl_init_v3,"axG",@progbits,nvtxRangeStartEx_impl_init_v3,comdat
	.weak	nvtxRangeStartEx_impl_init_v3
	.hidden	nvtxRangeStartEx_impl_init_v3
	.type	nvtxRangeStartEx_impl_init_v3, @function
nvtxRangeStartEx_impl_init_v3:
.LFB7808:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	72+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L628
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L628:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7808:
	.size	nvtxRangeStartEx_impl_init_v3, .-nvtxRangeStartEx_impl_init_v3
	.section	.text.nvtxMarkW_impl_init_v3,"axG",@progbits,nvtxMarkW_impl_init_v3,comdat
	.weak	nvtxMarkW_impl_init_v3
	.hidden	nvtxMarkW_impl_init_v3
	.type	nvtxMarkW_impl_init_v3, @function
nvtxMarkW_impl_init_v3:
.LFB7807:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	64+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L630
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L630:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7807:
	.size	nvtxMarkW_impl_init_v3, .-nvtxMarkW_impl_init_v3
	.section	.text.nvtxMarkA_impl_init_v3,"axG",@progbits,nvtxMarkA_impl_init_v3,comdat
	.weak	nvtxMarkA_impl_init_v3
	.hidden	nvtxMarkA_impl_init_v3
	.type	nvtxMarkA_impl_init_v3, @function
nvtxMarkA_impl_init_v3:
.LFB7806:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	56+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L633
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L633:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7806:
	.size	nvtxMarkA_impl_init_v3, .-nvtxMarkA_impl_init_v3
	.section	.text.nvtxMarkEx_impl_init_v3,"axG",@progbits,nvtxMarkEx_impl_init_v3,comdat
	.weak	nvtxMarkEx_impl_init_v3
	.hidden	nvtxMarkEx_impl_init_v3
	.type	nvtxMarkEx_impl_init_v3, @function
nvtxMarkEx_impl_init_v3:
.LFB7805:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	48+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L636
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L636:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7805:
	.size	nvtxMarkEx_impl_init_v3, .-nvtxMarkEx_impl_init_v3
	.text
	.globl	_Z33__device_stub__Z9piiKernelhPhS_S_hPhS_S_
	.type	_Z33__device_stub__Z9piiKernelhPhS_S_hPhS_S_, @function
_Z33__device_stub__Z9piiKernelhPhS_S_hPhS_S_:
.LFB11984:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movb	%dil, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L639
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9piiKernelhPhS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L639:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L641
	call	__stack_chk_fail@PLT
.L641:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11984:
	.size	_Z33__device_stub__Z9piiKernelhPhS_S_hPhS_S_, .-_Z33__device_stub__Z9piiKernelhPhS_S_hPhS_S_
	.globl	_Z9piiKernelhPhS_S_
	.type	_Z9piiKernelhPhS_S_, @function
_Z9piiKernelhPhS_S_:
.LFB11985:
	.cfi_startproc
	endbr64
	movzbl	%dil, %edi
	jmp	_Z33__device_stub__Z9piiKernelhPhS_S_hPhS_S_
	.cfi_endproc
.LFE11985:
	.size	_Z9piiKernelhPhS_S_, .-_Z9piiKernelhPhS_S_
	.section	.rodata.str1.1
.LC7:
	.string	"cudaMalloc((void **)&d_male_prefs, prefs_size)"
.LC8:
	.string	"cudaMalloc((void **)&d_female_prefs, prefs_size)"
.LC9:
	.string	"cudaMalloc((void **)&d_output, sizeof(uint8_t)*n)"
.LC10:
	.string	"cudaMemcpy(d_male_prefs, male_prefs, prefs_size, cudaMemcpyHostToDevice)"
.LC11:
	.string	"cudaMemcpy(d_female_prefs, female_prefs, prefs_size, cudaMemcpyHostToDevice)"
.LC12:
	.string	"cudaMemcpy(d_output, output, n*sizeof(uint8_t), cudaMemcpyHostToDevice)"
.LC13:
	.string	"cudaMemcpy(output, d_output, sizeof(uint8_t)*n, cudaMemcpyDeviceToHost)"
.LC14:
	.string	"cudaFree(d_male_prefs)"
.LC15:
	.string	"cudaFree(d_female_prefs)"
.LC16:
	.string	"cudaFree(d_output)"
	.text
	.globl	_Z3piihPhS_S_
	.type	_Z3piihPhS_S_, @function
_Z3piihPhS_S_:
.LFB11958:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edi, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movzbl	%dil, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r12, %r13
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	imulq	%r12, %r13
	movl	%edi, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%r13, %rsi
	movq	%rdx, 8(%rsp)
	leaq	24(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	cudaMalloc@PLT
	leaq	.LC7(%rip), %rsi
	movl	$182, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	%r13, %rsi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC8(%rip), %rsi
	movl	$183, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	leaq	40(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	leaq	.LC9(%rip), %rsi
	movl	$184, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	24(%rsp), %rdi
	movq	%r13, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC10(%rip), %rsi
	movl	$185, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r13d, %r13d
	call	cudaMemcpy@PLT
	leaq	.LC11(%rip), %rsi
	movl	$186, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
.L645:
	cmpb	%r15b, %r13b
	jnb	.L650
	call	rand@PLT
	leal	1(%r13), %ecx
	cltd
	idivl	%ecx
	movzbl	%dl, %edx
	addq	%rbp, %rdx
	movb	(%rdx), %al
	movb	%al, 0(%rbp,%r13)
	movb	%r13b, (%rdx)
	incq	%r13
	jmp	.L645
.L650:
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movzbl	%bl, %ebx
	call	cudaMemcpy@PLT
	leaq	.LC12(%rip), %rsi
	movl	$217, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	imulq	$12, %r12, %rdx
	leal	(%rbx,%rbx,2), %eax
	movl	%ebx, 60(%rsp)
	cltq
	xorl	%r9d, %r9d
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%rdi, 64(%rsp)
	movl	68(%rsp), %ecx
	leaq	1(%rdx,%rax), %rdx
	movl	%ebx, %eax
	imull	%ebx, %eax
	cltq
	leaq	(%rdx,%rax), %r8
	movq	60(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L647
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	%ebx, %edi
	movq	24(%rsp), %rsi
	call	_Z33__device_stub__Z9piiKernelhPhS_S_hPhS_S_
.L647:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC13(%rip), %rsi
	movl	$225, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC14(%rip), %rsi
	movl	$232, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC15(%rip), %rsi
	movl	$233, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC16(%rip), %rsi
	movl	$234, %edi
	movl	%eax, %edx
	call	_ZL17CheckCudaErrorAuxPKcjS0_9cudaError.constprop.0
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L648
	call	__stack_chk_fail@PLT
.L648:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11958:
	.size	_Z3piihPhS_S_, .-_Z3piihPhS_S_
	.section	.rodata.str1.1
.LC17:
	.string	"_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv"
.LC18:
	.string	"_Z9piiKernelhPhS_S_"
.LC19:
	.string	"precalc_xorwow_matrix"
.LC20:
	.string	"precalc_xorwow_offset_matrix"
.LC21:
	.string	"mrg32k3aM1"
.LC22:
	.string	"mrg32k3aM2"
.LC23:
	.string	"mrg32k3aM1SubSeq"
.LC24:
	.string	"mrg32k3aM2SubSeq"
.LC25:
	.string	"mrg32k3aM1Seq"
.LC26:
	.string	"mrg32k3aM2Seq"
.LC27:
	.string	"__cr_lgamma_table"
.LC28:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo5beginE"
.LC29:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo3endE"
.LC30:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo6cbeginE"
.LC31:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo4cendE"
.LC32:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo6rbeginE"
.LC33:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo4rendE"
.LC34:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo7crbeginE"
.LC35:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__45__cpo5crendE"
.LC36:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__438_GLOBAL__N__808e2425_6_pii_cu_0b79f9e66ignoreE"
.LC37:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__419piecewise_constructE"
.LC38:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__48in_placeE"
.LC39:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__420unreachable_sentinelE"
.LC40:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std3__47nulloptE"
.LC41:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo4swapE"
.LC42:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo9iter_moveE"
.LC43:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo7advanceE"
.LC44:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo5beginE"
.LC45:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo3endE"
.LC46:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo6cbeginE"
.LC47:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo4cendE"
.LC48:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo9iter_swapE"
.LC49:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo4nextE"
.LC50:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo4prevE"
.LC51:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo4dataE"
.LC52:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo5cdataE"
.LC53:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo4sizeE"
.LC54:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo5ssizeE"
.LC55:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e64cuda3std6ranges3__45__cpo8distanceE"
.LC56:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS6system6detail10sequential3seqE"
.LC57:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_1E"
.LC58:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_2E"
.LC59:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_3E"
.LC60:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_4E"
.LC61:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_5E"
.LC62:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_6E"
.LC63:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_7E"
.LC64:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_8E"
.LC65:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders2_9E"
.LC66:
	.string	"_ZN36_INTERNAL_808e2425_6_pii_cu_0b79f9e66thrust20THRUST_200700_890_NS12placeholders3_10E"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB11989:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9piiKernelhPhS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC25(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC26(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC28(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC29(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC30(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC31(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6rbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC33(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4rendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC34(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo7crbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC35(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5crendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC36(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__438_GLOBAL__N__808e2425_6_pii_cu_0b79f9e66ignoreE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC38(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__48in_placeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC39(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__420unreachable_sentinelE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC40(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__47nulloptE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC41(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC42(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC44(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC45(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC46(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC47(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC48(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC49(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4nextE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC50(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4prevE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC51(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4dataE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC52(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5cdataE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC53(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4sizeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC54(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5ssizeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC55(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo8distanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC56(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC57(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC58(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC60(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC61(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC62(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC63(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC64(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC65(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC66(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE11989:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E:
	.zero	1
	.weak	_ZN4cuda3std3__47nulloptE
	.section	.rodata._ZN4cuda3std3__47nulloptE,"aG",@progbits,_ZN4cuda3std3__47nulloptE,comdat
	.type	_ZN4cuda3std3__47nulloptE, @gnu_unique_object
	.size	_ZN4cuda3std3__47nulloptE, 1
_ZN4cuda3std3__47nulloptE:
	.zero	1
	.hidden	InitializeInjectionNvtx2_fnptr
	.weak	InitializeInjectionNvtx2_fnptr
	.bss
	.align 8
	.type	InitializeInjectionNvtx2_fnptr, @object
	.size	InitializeInjectionNvtx2_fnptr, 8
InitializeInjectionNvtx2_fnptr:
	.zero	8
	.hidden	nvtxGlobals_v3
	.weak	nvtxGlobals_v3
	.section	.data.rel.local,"aw"
	.align 32
	.type	nvtxGlobals_v3, @object
	.size	nvtxGlobals_v3, 1168
nvtxGlobals_v3:
	.long	0
	.zero	4
	.quad	16
	.quad	nvtxEtiGetModuleFunctionTable_v3
	.quad	24
	.long	3
	.long	0
	.quad	nvtxEtiSetInjectionNvtxVersion_v3
	.quad	nvtxMarkEx_impl_init_v3
	.quad	nvtxMarkA_impl_init_v3
	.quad	nvtxMarkW_impl_init_v3
	.quad	nvtxRangeStartEx_impl_init_v3
	.quad	nvtxRangeStartA_impl_init_v3
	.quad	nvtxRangeStartW_impl_init_v3
	.quad	nvtxRangeEnd_impl_init_v3
	.quad	nvtxRangePushEx_impl_init_v3
	.quad	nvtxRangePushA_impl_init_v3
	.quad	nvtxRangePushW_impl_init_v3
	.quad	nvtxRangePop_impl_init_v3
	.quad	nvtxNameCategoryA_impl_init_v3
	.quad	nvtxNameCategoryW_impl_init_v3
	.quad	nvtxNameOsThreadA_impl_init_v3
	.quad	nvtxNameOsThreadW_impl_init_v3
	.quad	nvtxNameCuDeviceA_impl_init_v3
	.quad	nvtxNameCuDeviceW_impl_init_v3
	.quad	nvtxNameCuContextA_impl_init_v3
	.quad	nvtxNameCuContextW_impl_init_v3
	.quad	nvtxNameCuStreamA_impl_init_v3
	.quad	nvtxNameCuStreamW_impl_init_v3
	.quad	nvtxNameCuEventA_impl_init_v3
	.quad	nvtxNameCuEventW_impl_init_v3
	.quad	nvtxNameClDeviceA_impl_init_v3
	.quad	nvtxNameClDeviceW_impl_init_v3
	.quad	nvtxNameClContextA_impl_init_v3
	.quad	nvtxNameClContextW_impl_init_v3
	.quad	nvtxNameClCommandQueueA_impl_init_v3
	.quad	nvtxNameClCommandQueueW_impl_init_v3
	.quad	nvtxNameClMemObjectA_impl_init_v3
	.quad	nvtxNameClMemObjectW_impl_init_v3
	.quad	nvtxNameClSamplerA_impl_init_v3
	.quad	nvtxNameClSamplerW_impl_init_v3
	.quad	nvtxNameClProgramA_impl_init_v3
	.quad	nvtxNameClProgramW_impl_init_v3
	.quad	nvtxNameClEventA_impl_init_v3
	.quad	nvtxNameClEventW_impl_init_v3
	.quad	nvtxNameCudaDeviceA_impl_init_v3
	.quad	nvtxNameCudaDeviceW_impl_init_v3
	.quad	nvtxNameCudaStreamA_impl_init_v3
	.quad	nvtxNameCudaStreamW_impl_init_v3
	.quad	nvtxNameCudaEventA_impl_init_v3
	.quad	nvtxNameCudaEventW_impl_init_v3
	.quad	nvtxDomainMarkEx_impl_init_v3
	.quad	nvtxDomainRangeStartEx_impl_init_v3
	.quad	nvtxDomainRangeEnd_impl_init_v3
	.quad	nvtxDomainRangePushEx_impl_init_v3
	.quad	nvtxDomainRangePop_impl_init_v3
	.quad	nvtxDomainResourceCreate_impl_init_v3
	.quad	nvtxDomainResourceDestroy_impl_init_v3
	.quad	nvtxDomainNameCategoryA_impl_init_v3
	.quad	nvtxDomainNameCategoryW_impl_init_v3
	.quad	nvtxDomainRegisterStringA_impl_init_v3
	.quad	nvtxDomainRegisterStringW_impl_init_v3
	.quad	nvtxDomainCreateA_impl_init_v3
	.quad	nvtxDomainCreateW_impl_init_v3
	.quad	nvtxDomainDestroy_impl_init_v3
	.quad	nvtxInitialize_impl_init_v3
	.quad	nvtxDomainSyncUserCreate_impl_init_v3
	.quad	nvtxDomainSyncUserDestroy_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.quad	nvtxDomainSyncUserReleasing_impl_init_v3
	.quad	0
	.quad	nvtxGlobals_v3+48
	.quad	nvtxGlobals_v3+56
	.quad	nvtxGlobals_v3+64
	.quad	nvtxGlobals_v3+72
	.quad	nvtxGlobals_v3+80
	.quad	nvtxGlobals_v3+88
	.quad	nvtxGlobals_v3+96
	.quad	nvtxGlobals_v3+104
	.quad	nvtxGlobals_v3+112
	.quad	nvtxGlobals_v3+120
	.quad	nvtxGlobals_v3+128
	.quad	nvtxGlobals_v3+136
	.quad	nvtxGlobals_v3+144
	.quad	nvtxGlobals_v3+152
	.quad	nvtxGlobals_v3+160
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+168
	.quad	nvtxGlobals_v3+176
	.quad	nvtxGlobals_v3+184
	.quad	nvtxGlobals_v3+192
	.quad	nvtxGlobals_v3+200
	.quad	nvtxGlobals_v3+208
	.quad	nvtxGlobals_v3+216
	.quad	nvtxGlobals_v3+224
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+232
	.quad	nvtxGlobals_v3+240
	.quad	nvtxGlobals_v3+248
	.quad	nvtxGlobals_v3+256
	.quad	nvtxGlobals_v3+264
	.quad	nvtxGlobals_v3+272
	.quad	nvtxGlobals_v3+280
	.quad	nvtxGlobals_v3+288
	.quad	nvtxGlobals_v3+296
	.quad	nvtxGlobals_v3+304
	.quad	nvtxGlobals_v3+312
	.quad	nvtxGlobals_v3+320
	.quad	nvtxGlobals_v3+328
	.quad	nvtxGlobals_v3+336
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+344
	.quad	nvtxGlobals_v3+352
	.quad	nvtxGlobals_v3+360
	.quad	nvtxGlobals_v3+368
	.quad	nvtxGlobals_v3+376
	.quad	nvtxGlobals_v3+384
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+392
	.quad	nvtxGlobals_v3+400
	.quad	nvtxGlobals_v3+408
	.quad	nvtxGlobals_v3+416
	.quad	nvtxGlobals_v3+424
	.quad	nvtxGlobals_v3+432
	.quad	nvtxGlobals_v3+440
	.quad	nvtxGlobals_v3+448
	.quad	nvtxGlobals_v3+456
	.quad	nvtxGlobals_v3+464
	.quad	nvtxGlobals_v3+472
	.quad	nvtxGlobals_v3+480
	.quad	nvtxGlobals_v3+488
	.quad	nvtxGlobals_v3+496
	.quad	nvtxGlobals_v3+504
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+512
	.quad	nvtxGlobals_v3+520
	.quad	nvtxGlobals_v3+528
	.quad	nvtxGlobals_v3+536
	.quad	nvtxGlobals_v3+544
	.quad	nvtxGlobals_v3+552
	.quad	0
	.weak	_ZN4cuda3std3__420unreachable_sentinelE
	.section	.rodata._ZN4cuda3std3__420unreachable_sentinelE,"aG",@progbits,_ZN4cuda3std3__420unreachable_sentinelE,comdat
	.type	_ZN4cuda3std3__420unreachable_sentinelE, @gnu_unique_object
	.size	_ZN4cuda3std3__420unreachable_sentinelE, 1
_ZN4cuda3std3__420unreachable_sentinelE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo5crendE
	.section	.rodata._ZN4cuda3std3__45__cpo5crendE,"aG",@progbits,_ZN4cuda3std3__45__cpo5crendE,comdat
	.type	_ZN4cuda3std3__45__cpo5crendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo5crendE, 1
_ZN4cuda3std3__45__cpo5crendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo7crbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo7crbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo7crbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo7crbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo7crbeginE, 1
_ZN4cuda3std3__45__cpo7crbeginE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo4rendE
	.section	.rodata._ZN4cuda3std3__45__cpo4rendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4rendE,comdat
	.type	_ZN4cuda3std3__45__cpo4rendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo4rendE, 1
_ZN4cuda3std3__45__cpo4rendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo6rbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo6rbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6rbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo6rbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo6rbeginE, 1
_ZN4cuda3std3__45__cpo6rbeginE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo8distanceE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo8distanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo8distanceE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo8distanceE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo8distanceE, 1
_ZN4cuda3std6ranges3__45__cpo8distanceE:
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	.section	.rodata._ZN4cuda3std6ranges3__45__cpo5ssizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5ssizeE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo5ssizeE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo5ssizeE, 1
_ZN4cuda3std6ranges3__45__cpo5ssizeE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4sizeE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4sizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4sizeE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4sizeE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4sizeE, 1
_ZN4cuda3std6ranges3__45__cpo4sizeE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo5cdataE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo5cdataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5cdataE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo5cdataE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo5cdataE, 1
_ZN4cuda3std6ranges3__45__cpo5cdataE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4dataE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4dataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4dataE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4dataE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4dataE, 1
_ZN4cuda3std6ranges3__45__cpo4dataE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4prevE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4prevE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4prevE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4prevE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4prevE, 1
_ZN4cuda3std6ranges3__45__cpo4prevE:
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_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 ============================================================================
 Name        : GScuda.cu
 Author      : caleb
 Version     :
 Copyright   : Your copyright notice
 Description : CUDA compute reciprocals
 ============================================================================
 */


#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdint.h>
#include <limits.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <hipcub/hipcub.hpp>
using namespace hipcub;
// I ASSUME THROUGHOUT THAT sizeof(int) = 4
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)

static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err);

__global__ void piiKernel(uint8_t n, uint8_t* male_prefs, uint8_t* female_prefs, uint8_t* output) {
    //TODO fix shared bank conflicts

    int idx = threadIdx.x;
    extern __shared__ int s[]; 
    // current_match[i] = j implies female i is matched with male j
    int* current_match = (int*) s;
    //curent_match flipped for fast lookups so match current[j] = i implies female i is matched with male j
    int* match_current = (int*) &current_match[n];
    // nm1[i] = j implies that female i is matched with male (j&0xFF) and female_prefs[i][j] = ((j>>24)&0xFF)
    // no need to reset every time since nm1 pairs always improve things for the woman
    unsigned int* nm1 = (unsigned int*) &match_current[n];
    // an array of three tuples of the form nm2graph[male id(row)] = (row neighbor index, female id (column),column neighbor index), indexes are 255 if null
    // where the row (respectively column) neighbor index is the index into nm2graph of the the nm2 pair it is connected to by the matching pair in the same row as it
    uint8_t* nm2graph= (uint8_t*) &nm1[n];
    uint8_t* shared_fp = (uint8_t*) &nm2graph[3*n];
    uint8_t* unstable = (uint8_t*) &shared_fp[n*n];
    //local cache of male_prefs
    //TODO coalesce
    uint8_t* local_mp = new uint8_t[n];
    for (int i = 0; i < n; i++){
        local_mp[i] = male_prefs[idx*n+i];
    }
    // generated a random permutation on the CPU
    int temp_man = current_match[idx] = output[idx]; 
    match_current[temp_man] = idx;
    //copy female prefs into swap
    //TODO optimize (may be good already)
    for (int i = 0; i < n; i++) {
        shared_fp[i*n + idx] = female_prefs[i*n + idx];
    }
    __syncthreads();
    for (int p = 0; p < n; p++) {
        __syncthreads();
        int partner = match_current[idx]; 
        // the female partner for this male's NM1 pair
        int nm1g = -1;
        //TODO optimize
        unstable[0] = 0;
        __syncthreads();
        //find NM1-generating pairs
        for (int j  = 0; local_mp[j] != partner; j++){
            if (shared_fp[local_mp[j]*n+idx] < shared_fp[local_mp[j]*n+current_match[local_mp[j]]]){
                nm1g = local_mp[j];
#ifdef DEBUG
                printf("found nm1g pair for male %d\n",idx);
#endif
                unstable[0] = 1;
                break;
            }
        }
#ifdef DEBUG
        printf("thread: %d, potential nm1g=%d\n",idx,nm1g);
#endif
        //TODO optimize
        __syncthreads();
        if (unstable[0] == 0){
#ifdef DEBUG
        printf("FOUND STABLE MATCHING\n");
#endif
            break;
        }
        //TODO optimize?
        nm2graph[idx*3 +0] = 255;
        nm2graph[idx*3 +1] = 255;
        nm2graph[idx*3+2] = 255;
        bool is_nm1 = false;
        unsigned int  potential_nm1_construct = ~0;
        // initialize large
        nm1[idx] = INT_MAX;
        __syncthreads();
        if (nm1g != -1) {
            //find NM1 pairs  
            //TODO explain
            potential_nm1_construct = (female_prefs[nm1g*n+idx] << 24)|idx;
            atomicMin(nm1+nm1g, potential_nm1_construct);
        } 
        __syncthreads();
        is_nm1 = (potential_nm1_construct == nm1[nm1g]);
        // find nm2
        if (is_nm1){
                // race condition?
                // horizontal nm2 pair 
                nm2graph[idx*3+0] = current_match[nm1g];
                //vertical nm2 pair
                nm2graph[(current_match[nm1g])*3+1] = partner;
                nm2graph[(current_match[nm1g])*3+2] = idx;

            }
#ifdef DEBUG
                printf("thread: %d ready to sync\n",idx);
#endif

        __syncthreads();
        // if we are nm1
        if (is_nm1) {
#ifdef DEBUG
                printf("thread: %d, final nm1g=%d\n",idx,nm1g);
#endif
            current_match[nm1g] = idx;
            match_current[idx] = nm1g;
            // if we are a column end 
            if (nm2graph[idx*3+2] == 255) {
#ifdef DEBUG
                printf("thread: %d, nm2graph[idx] = (%d,%d,%d)\n",idx,nm2graph[idx*3+0],nm2graph[idx*3+1],nm2graph[idx*3+2]);

#endif
                int nm2column = partner;
                //TODO optimize
                int nm2row= current_match[nm1g];
#ifdef DEBUG
                printf("thread: %d, nm2row=%d, nm2graph[nm2row] = (%d,%d,%d)\n",idx,nm2row,nm2graph[nm2row*3+0],nm2graph[nm2row*3+1],nm2graph[nm2row*3+2]);
#endif
                // if it's a single pair
                if (nm2graph[nm2row*3+0]==nm2graph[nm2row*3+2]){
                    nm2column = nm2graph[nm2row*3+1];
                }
                // if it's a chain
                else {
                    while(nm2graph[nm2row*3+0] != 255) {
#ifdef DEBUG
                        printf("thread: %d, nm2row=%d, nm2graph[nm2row] = (%d,%d,%d)\n",idx,nm2row,nm2graph[nm2row*3+0],nm2graph[nm2row*3+1],nm2graph[nm2row*3+2]);
#endif

                        nm2row = nm2graph[nm2row*3+0];
                    }
                }
#ifdef DEBUG
                printf("final nm2row=%d,nm2column=%d\n",nm2row,nm2column);
#endif
                current_match[nm2column] = nm2row;
                match_current[nm2row] = nm2column;

            }
                    



        }
    }
    // copy output out
    output[idx] = current_match[idx];
    delete[] local_mp;
}

/**
 * Host function that copies the data and launches GS on the CPU
 *
 */
void  pii(uint8_t n, uint8_t* male_prefs, uint8_t* female_prefs, uint8_t* output)
{
	uint8_t *d_male_prefs, *d_female_prefs;
	uint8_t* d_output;

	size_t prefs_size = sizeof(uint8_t)*n*n;
	CUDA_CHECK_RETURN(hipMalloc((void **)&d_male_prefs, prefs_size));
	CUDA_CHECK_RETURN(hipMalloc((void **)&d_female_prefs, prefs_size));
	CUDA_CHECK_RETURN(hipMalloc((void **)&d_output, sizeof(uint8_t)*n));
	CUDA_CHECK_RETURN(hipMemcpy(d_male_prefs, male_prefs, prefs_size, hipMemcpyHostToDevice));
	CUDA_CHECK_RETURN(hipMemcpy(d_female_prefs, female_prefs, prefs_size, hipMemcpyHostToDevice));

#ifdef TIME_KERNEL
    struct timespec start, end;
    hipDeviceSynchronize();
    clock_gettime(CLOCK_MONOTONIC, &start);	
#endif
    //knuth shuffle from sgb
    for (uint8_t k = 0;k < n; k++) {
        uint8_t j= rand() % (k+1);
        output[k] = output[j];
        output[j] = k;
    }
#ifdef DEBUG
    printf("male_prefs: \n ");
    for (int i = 0; i < n; i++){ 
        for (int j = 0; j < n; j++)
            printf("%hhd ",male_prefs[i*n+j]);
        printf("\n ");
    }
    printf("female_prefs: \n ");
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++)
            printf("%hhd ",female_prefs[i*n+j]);
        printf("\n ");
    }
    printf("permutation: ");
    for (int i = 0; i < n; i++) 
        printf("%hhd ",output[i]);
    printf("\n ");
#endif
	CUDA_CHECK_RETURN(hipMemcpy(d_output, output, n*sizeof(uint8_t), hipMemcpyHostToDevice));
    piiKernel<<<1,n,n*sizeof(int)+n*sizeof(int)+n*sizeof(unsigned int) + 3*n*sizeof(uint8_t) + n*n*sizeof(uint8_t)+1>>> (n, d_male_prefs,d_female_prefs, d_output);
#ifdef TIME_KERNEL
    hipDeviceSynchronize();
    clock_gettime(CLOCK_MONOTONIC, &end);	
    long long unsigned int diff = (1000000000L) * (end.tv_sec - start.tv_sec) + end.tv_nsec - start.tv_nsec;
    printf("kernel time %llu\n",diff);
#endif
	CUDA_CHECK_RETURN(hipMemcpy(output, d_output, sizeof(uint8_t)*n, hipMemcpyDeviceToHost));
#ifdef DEBUG
    printf("result: ");
    for (int i = 0; i < n; i++) 
        printf("%hhd ",output[i]);
    printf("\n ");
#endif
	CUDA_CHECK_RETURN(hipFree(d_male_prefs));
	CUDA_CHECK_RETURN(hipFree(d_female_prefs));
	CUDA_CHECK_RETURN(hipFree(d_output));
}
/**
 * Check the return value of the CUDA runtime API call and exit
 * the application if the call has failed.
 */
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
	if (err == hipSuccess)
		return;
	std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
	exit (1);
}





	.text
	.file	"pii.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__piiKernelhPhS_S_ # -- Begin function _Z24__device_stub__piiKernelhPhS_S_
	.type	_Z24__device_stub__piiKernelhPhS_S_,@function
_Z24__device_stub__piiKernelhPhS_S_:    # @_Z24__device_stub__piiKernelhPhS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	7(%rsp), %rax
	movb	%dil, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9piiKernelhPhS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__piiKernelhPhS_S_, .Lfunc_end0-_Z24__device_stub__piiKernelhPhS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z3piihPhS_S_                   # -- Begin function _Z3piihPhS_S_
	.type	_Z3piihPhS_S_,@function
_Z3piihPhS_S_:                          # @_Z3piihPhS_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %rbx
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rsi, %r13
	movl	%edi, %ebp
	movl	%edi, %r14d
	movq	%r14, %r12
	imulq	%r14, %r12
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %esi
	movl	$184, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %esi
	movl	$185, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %esi
	movl	$186, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	(%r15), %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.4, %esi
	movl	$187, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	$188, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	testl	%ebp, %ebp
	je	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%r15d, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	leaq	1(%r15), %rcx
	cltd
	idivl	%ecx
	movzbl	%dl, %eax
	movb	(%rbx,%rax), %dl
	movb	%dl, (%rbx,%r15)
	movb	%r15b, (%rbx,%rax)
	movq	%rcx, %r15
	cmpq	%rcx, %r14
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movzbl	%bpl, %r15d
	movq	8(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.6, %esi
	movl	$219, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	leaq	(%r14,%r14,2), %rax
	leal	(%r15,%r15,2), %ecx
	movl	%r15d, %edx
	imull	%edx, %edx
	leaq	(%rcx,%rax,4), %rax
	leaq	(%rdx,%rax), %r8
	incq	%r8
	movq	%r14, %rdx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$1, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	%r15d, %edi
	callq	_Z24__device_stub__piiKernelhPhS_S_
.LBB1_5:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.7, %esi
	movl	$227, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	24(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.8, %esi
	movl	$234, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.9, %esi
	movl	$235, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.10, %esi
	movl	$236, %edi
	movl	%eax, %edx
	callq	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z3piihPhS_S_, .Lfunc_end1-_Z3piihPhS_S_
	.cfi_endproc
                                        # -- End function
	.type	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jne	.LBB2_2
# %bb.1:
	retq
.LBB2_2:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%edi, %ebx
	movl	$_ZSt4cerr, %edi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.11, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebp, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.12, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.13, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.14, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebx, %esi
	callq	_ZNSolsEj
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end2-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9piiKernelhPhS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9piiKernelhPhS_S_,@object     # @_Z9piiKernelhPhS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z9piiKernelhPhS_S_
	.p2align	3, 0x0
_Z9piiKernelhPhS_S_:
	.quad	_Z24__device_stub__piiKernelhPhS_S_
	.size	_Z9piiKernelhPhS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/calebclark/reu/master/small_matching/pii.hip"
	.size	.L.str, 107

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"hipMalloc((void **)&d_male_prefs, prefs_size)"
	.size	.L.str.1, 46

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"hipMalloc((void **)&d_female_prefs, prefs_size)"
	.size	.L.str.2, 48

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipMalloc((void **)&d_output, sizeof(uint8_t)*n)"
	.size	.L.str.3, 49

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"hipMemcpy(d_male_prefs, male_prefs, prefs_size, hipMemcpyHostToDevice)"
	.size	.L.str.4, 71

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipMemcpy(d_female_prefs, female_prefs, prefs_size, hipMemcpyHostToDevice)"
	.size	.L.str.5, 75

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"hipMemcpy(d_output, output, n*sizeof(uint8_t), hipMemcpyHostToDevice)"
	.size	.L.str.6, 70

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"hipMemcpy(output, d_output, sizeof(uint8_t)*n, hipMemcpyDeviceToHost)"
	.size	.L.str.7, 70

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"hipFree(d_male_prefs)"
	.size	.L.str.8, 22

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"hipFree(d_female_prefs)"
	.size	.L.str.9, 24

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"hipFree(d_output)"
	.size	.L.str.10, 18

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	" returned "
	.size	.L.str.11, 11

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"("
	.size	.L.str.12, 2

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	") at "
	.size	.L.str.13, 6

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	":"
	.size	.L.str.14, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9piiKernelhPhS_S_"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__piiKernelhPhS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9piiKernelhPhS_S_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text.unlikely.,"ax",@progbits
	.p2align	2                               ; -- Begin function __ockl_dm_alloc
	.type	__ockl_dm_alloc,@function
__ockl_dm_alloc:                        ; @__ockl_dm_alloc
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_or_saveexec_b32 s0, -1
	scratch_store_b32 off, v40, s32         ; 4-byte Folded Spill
	s_mov_b32 exec_lo, s0
	v_writelane_b32 v40, s34, 0
	v_writelane_b32 v40, s35, 1
	v_writelane_b32 v40, s36, 2
	v_writelane_b32 v40, s37, 3
	v_writelane_b32 v40, s38, 4
	v_writelane_b32 v40, s39, 5
	v_writelane_b32 v40, s40, 6
	v_writelane_b32 v40, s41, 7
	v_writelane_b32 v40, s42, 8
	v_writelane_b32 v40, s43, 9
	v_writelane_b32 v40, s44, 10
	v_writelane_b32 v40, s30, 11
	v_writelane_b32 v40, s31, 12
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_ne_u64_e32 0, v[4:5]
	s_cbranch_execz .LBB0_702
; %bb.1:
	v_mbcnt_lo_u32_b32 v2, -1, 0
                                        ; implicit-def: $vgpr0_vgpr1
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u64_e32 0xc01, v[4:5]
	s_xor_b32 s23, exec_lo, s0
	s_cbranch_execz .LBB0_668
; %bb.2:
	v_max_u32_e32 v0, 16, v4
	v_mov_b32_e32 v5, 0
	s_load_b64 s[10:11], s[8:9], 0x60
	v_dual_mov_b32 v118, 1 :: v_dual_mov_b32 v17, 0x1800
	s_delay_alu instid0(VALU_DEP_3)
	v_clz_i32_u32_e32 v1, v0
	v_mov_b32_e32 v20, 0x200000
	v_mov_b32_e32 v8, v5
	v_mov_b32_e32 v14, 1
	v_mov_b32_e32 v68, 0x100
	v_not_b32_e32 v3, v1
	v_lshlrev_b32_e32 v1, 1, v1
	v_mov_b32_e32 v13, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 15, v3
	v_lshlrev_b32_e64 v3, v3, 1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s12, s10, 0x1a800
	s_addc_u32 s13, s11, 0
	s_add_u32 s14, s10, 0x1a808
	v_lshrrev_b32_e32 v4, 1, v3
	v_cmp_gt_u32_e32 vcc_lo, v0, v3
	s_addc_u32 s15, s11, 0
	s_add_u32 s4, s10, 0x800
	s_addc_u32 s5, s11, 0
	v_or_b32_e32 v3, v4, v3
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __unnamed_1@rel32@lo+12
	s_addc_u32 s1, s1, __unnamed_1@rel32@hi+20
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+4
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+12
	s_add_u32 s6, s10, 0x1000
	v_cmp_gt_u32_e32 vcc_lo, v0, v3
	v_sub_nc_u32_e32 v1, v6, v1
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 54, v1, vcc_lo
	v_lshlrev_b64 v[0:1], 7, v[7:8]
	v_lshlrev_b64 v[3:4], 5, v[7:8]
	v_lshrrev_b64 v[8:9], v7, 0xbf
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v32, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v33, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v34, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v35, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v36, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v37, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v38, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v39, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v48, vcc_lo, s6, v0
	s_add_u32 s0, s10, 0x2000
	v_add_co_ci_u32_e32 v49, vcc_lo, s7, v1, vcc_lo
	s_addc_u32 s1, s11, 0
	v_add_co_u32 v50, vcc_lo, s0, v0
	s_add_u32 s2, s10, 0x1800
	v_add_co_ci_u32_e32 v51, vcc_lo, s1, v1, vcc_lo
	s_addc_u32 s3, s11, 0
	v_add_co_u32 v52, vcc_lo, s2, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __unnamed_1@rel32@lo+24
	s_addc_u32 s1, s1, __unnamed_1@rel32@hi+32
	v_add_co_ci_u32_e32 v53, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v54, vcc_lo, v3, s0
	v_and_b32_e32 v0, 1, v8
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+20
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+28
	v_add_co_ci_u32_e32 v55, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v64, vcc_lo, v3, s2
	v_mov_b32_e32 v9, v5
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, __unnamed_1@rel32@lo+28
	s_addc_u32 s5, s5, __unnamed_1@rel32@hi+36
	v_add_co_ci_u32_e32 v65, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v66, vcc_lo, v3, s4
	v_cmp_eq_u32_e64 s0, 1, v0
	v_mov_b32_e32 v0, 0
	v_add_co_ci_u32_e32 v67, vcc_lo, s5, v4, vcc_lo
	v_mov_b32_e32 v8, v5
	v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v1, 0
	v_mov_b32_e32 v3, v14
	s_add_u32 s24, s10, 0x100
	s_mov_b32 s4, 0
	s_addc_u32 s25, s11, 0
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_11 Depth 3
                                        ;         Child Loop BB0_14 Depth 4
                                        ;         Child Loop BB0_43 Depth 4
                                        ;           Child Loop BB0_47 Depth 5
                                        ;           Child Loop BB0_75 Depth 5
                                        ;             Child Loop BB0_93 Depth 6
                                        ;             Child Loop BB0_101 Depth 6
                                        ;             Child Loop BB0_107 Depth 6
                                        ;             Child Loop BB0_116 Depth 6
                                        ;             Child Loop BB0_121 Depth 6
                                        ;             Child Loop BB0_123 Depth 6
                                        ;             Child Loop BB0_144 Depth 6
                                        ;             Child Loop BB0_152 Depth 6
                                        ;             Child Loop BB0_158 Depth 6
                                        ;             Child Loop BB0_167 Depth 6
                                        ;             Child Loop BB0_175 Depth 6
                                        ;             Child Loop BB0_178 Depth 6
                                        ;             Child Loop BB0_180 Depth 6
                                        ;             Child Loop BB0_182 Depth 6
                                        ;             Child Loop BB0_184 Depth 6
                                        ;             Child Loop BB0_186 Depth 6
                                        ;             Child Loop BB0_188 Depth 6
                                        ;             Child Loop BB0_210 Depth 6
                                        ;             Child Loop BB0_218 Depth 6
                                        ;             Child Loop BB0_224 Depth 6
                                        ;             Child Loop BB0_233 Depth 6
                                        ;             Child Loop BB0_240 Depth 6
                                        ;             Child Loop BB0_243 Depth 6
                                        ;             Child Loop BB0_248 Depth 6
                                        ;             Child Loop BB0_255 Depth 6
                                        ;             Child Loop BB0_288 Depth 6
                                        ;             Child Loop BB0_296 Depth 6
                                        ;             Child Loop BB0_302 Depth 6
                                        ;             Child Loop BB0_311 Depth 6
                                        ;           Child Loop BB0_320 Depth 5
                                        ;           Child Loop BB0_323 Depth 5
                                        ;           Child Loop BB0_325 Depth 5
                                        ;           Child Loop BB0_327 Depth 5
                                        ;           Child Loop BB0_329 Depth 5
                                        ;           Child Loop BB0_331 Depth 5
                                        ;           Child Loop BB0_333 Depth 5
                                        ;       Child Loop BB0_347 Depth 3
                                        ;         Child Loop BB0_351 Depth 4
                                        ;         Child Loop BB0_378 Depth 4
                                        ;           Child Loop BB0_396 Depth 5
                                        ;           Child Loop BB0_404 Depth 5
                                        ;           Child Loop BB0_410 Depth 5
                                        ;           Child Loop BB0_419 Depth 5
                                        ;           Child Loop BB0_424 Depth 5
                                        ;           Child Loop BB0_426 Depth 5
                                        ;           Child Loop BB0_447 Depth 5
                                        ;           Child Loop BB0_455 Depth 5
                                        ;           Child Loop BB0_461 Depth 5
                                        ;           Child Loop BB0_470 Depth 5
                                        ;           Child Loop BB0_478 Depth 5
                                        ;           Child Loop BB0_481 Depth 5
                                        ;           Child Loop BB0_483 Depth 5
                                        ;           Child Loop BB0_485 Depth 5
                                        ;           Child Loop BB0_487 Depth 5
                                        ;           Child Loop BB0_489 Depth 5
                                        ;           Child Loop BB0_491 Depth 5
                                        ;           Child Loop BB0_513 Depth 5
                                        ;           Child Loop BB0_521 Depth 5
                                        ;           Child Loop BB0_527 Depth 5
                                        ;           Child Loop BB0_536 Depth 5
                                        ;           Child Loop BB0_543 Depth 5
                                        ;           Child Loop BB0_546 Depth 5
                                        ;           Child Loop BB0_551 Depth 5
                                        ;           Child Loop BB0_558 Depth 5
                                        ;           Child Loop BB0_591 Depth 5
                                        ;           Child Loop BB0_599 Depth 5
                                        ;           Child Loop BB0_605 Depth 5
                                        ;           Child Loop BB0_614 Depth 5
                                        ;         Child Loop BB0_623 Depth 4
                                        ;         Child Loop BB0_626 Depth 4
                                        ;         Child Loop BB0_628 Depth 4
                                        ;         Child Loop BB0_630 Depth 4
                                        ;         Child Loop BB0_632 Depth 4
                                        ;         Child Loop BB0_634 Depth 4
                                        ;         Child Loop BB0_636 Depth 4
                                        ;       Child Loop BB0_649 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v119, v3
	v_mov_b32_e32 v3, v5
	s_mov_b32 s26, exec_lo
	;;#ASMSTART
	;;#ASMEND
	v_cmpx_ne_u32_e32 0, v119
	s_cbranch_execz .LBB0_666
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_readfirstlane_b32 s1, v7
	s_mov_b32 s27, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e64 s1, v7
	s_cbranch_execz .LBB0_665
; %bb.5:                                ; %.preheader196.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v3, 1
.LBB0_6:                                ; %.preheader196
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_11 Depth 3
                                        ;         Child Loop BB0_14 Depth 4
                                        ;         Child Loop BB0_43 Depth 4
                                        ;           Child Loop BB0_47 Depth 5
                                        ;           Child Loop BB0_75 Depth 5
                                        ;             Child Loop BB0_93 Depth 6
                                        ;             Child Loop BB0_101 Depth 6
                                        ;             Child Loop BB0_107 Depth 6
                                        ;             Child Loop BB0_116 Depth 6
                                        ;             Child Loop BB0_121 Depth 6
                                        ;             Child Loop BB0_123 Depth 6
                                        ;             Child Loop BB0_144 Depth 6
                                        ;             Child Loop BB0_152 Depth 6
                                        ;             Child Loop BB0_158 Depth 6
                                        ;             Child Loop BB0_167 Depth 6
                                        ;             Child Loop BB0_175 Depth 6
                                        ;             Child Loop BB0_178 Depth 6
                                        ;             Child Loop BB0_180 Depth 6
                                        ;             Child Loop BB0_182 Depth 6
                                        ;             Child Loop BB0_184 Depth 6
                                        ;             Child Loop BB0_186 Depth 6
                                        ;             Child Loop BB0_188 Depth 6
                                        ;             Child Loop BB0_210 Depth 6
                                        ;             Child Loop BB0_218 Depth 6
                                        ;             Child Loop BB0_224 Depth 6
                                        ;             Child Loop BB0_233 Depth 6
                                        ;             Child Loop BB0_240 Depth 6
                                        ;             Child Loop BB0_243 Depth 6
                                        ;             Child Loop BB0_248 Depth 6
                                        ;             Child Loop BB0_255 Depth 6
                                        ;             Child Loop BB0_288 Depth 6
                                        ;             Child Loop BB0_296 Depth 6
                                        ;             Child Loop BB0_302 Depth 6
                                        ;             Child Loop BB0_311 Depth 6
                                        ;           Child Loop BB0_320 Depth 5
                                        ;           Child Loop BB0_323 Depth 5
                                        ;           Child Loop BB0_325 Depth 5
                                        ;           Child Loop BB0_327 Depth 5
                                        ;           Child Loop BB0_329 Depth 5
                                        ;           Child Loop BB0_331 Depth 5
                                        ;           Child Loop BB0_333 Depth 5
                                        ;       Child Loop BB0_347 Depth 3
                                        ;         Child Loop BB0_351 Depth 4
                                        ;         Child Loop BB0_378 Depth 4
                                        ;           Child Loop BB0_396 Depth 5
                                        ;           Child Loop BB0_404 Depth 5
                                        ;           Child Loop BB0_410 Depth 5
                                        ;           Child Loop BB0_419 Depth 5
                                        ;           Child Loop BB0_424 Depth 5
                                        ;           Child Loop BB0_426 Depth 5
                                        ;           Child Loop BB0_447 Depth 5
                                        ;           Child Loop BB0_455 Depth 5
                                        ;           Child Loop BB0_461 Depth 5
                                        ;           Child Loop BB0_470 Depth 5
                                        ;           Child Loop BB0_478 Depth 5
                                        ;           Child Loop BB0_481 Depth 5
                                        ;           Child Loop BB0_483 Depth 5
                                        ;           Child Loop BB0_485 Depth 5
                                        ;           Child Loop BB0_487 Depth 5
                                        ;           Child Loop BB0_489 Depth 5
                                        ;           Child Loop BB0_491 Depth 5
                                        ;           Child Loop BB0_513 Depth 5
                                        ;           Child Loop BB0_521 Depth 5
                                        ;           Child Loop BB0_527 Depth 5
                                        ;           Child Loop BB0_536 Depth 5
                                        ;           Child Loop BB0_543 Depth 5
                                        ;           Child Loop BB0_546 Depth 5
                                        ;           Child Loop BB0_551 Depth 5
                                        ;           Child Loop BB0_558 Depth 5
                                        ;           Child Loop BB0_591 Depth 5
                                        ;           Child Loop BB0_599 Depth 5
                                        ;           Child Loop BB0_605 Depth 5
                                        ;           Child Loop BB0_614 Depth 5
                                        ;         Child Loop BB0_623 Depth 4
                                        ;         Child Loop BB0_626 Depth 4
                                        ;         Child Loop BB0_628 Depth 4
                                        ;         Child Loop BB0_630 Depth 4
                                        ;         Child Loop BB0_632 Depth 4
                                        ;         Child Loop BB0_634 Depth 4
                                        ;         Child Loop BB0_636 Depth 4
                                        ;       Child Loop BB0_649 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v128, v3 :: v_dual_mov_b32 v3, 0
	s_mov_b32 s28, exec_lo
	;;#ASMSTART
	;;#ASMEND
	v_cmpx_ne_u32_e32 0, v128
	s_cbranch_execz .LBB0_664
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=2
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=2
	global_load_b32 v3, v[32:33], off glc
.LBB0_9:                                ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s29, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_gt_u32 s29, 0x100ff
	s_cbranch_scc0 .LBB0_344
; %bb.10:                               ;   in Loop: Header=BB0_6 Depth=2
	v_mbcnt_lo_u32_b32 v129, exec_lo, 0
	v_mov_b32_e32 v4, v7
	s_mov_b32 s30, 0
	s_bcnt1_i32_b32 s31, exec_lo
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_11:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_14 Depth 4
                                        ;         Child Loop BB0_43 Depth 4
                                        ;           Child Loop BB0_47 Depth 5
                                        ;           Child Loop BB0_75 Depth 5
                                        ;             Child Loop BB0_93 Depth 6
                                        ;             Child Loop BB0_101 Depth 6
                                        ;             Child Loop BB0_107 Depth 6
                                        ;             Child Loop BB0_116 Depth 6
                                        ;             Child Loop BB0_121 Depth 6
                                        ;             Child Loop BB0_123 Depth 6
                                        ;             Child Loop BB0_144 Depth 6
                                        ;             Child Loop BB0_152 Depth 6
                                        ;             Child Loop BB0_158 Depth 6
                                        ;             Child Loop BB0_167 Depth 6
                                        ;             Child Loop BB0_175 Depth 6
                                        ;             Child Loop BB0_178 Depth 6
                                        ;             Child Loop BB0_180 Depth 6
                                        ;             Child Loop BB0_182 Depth 6
                                        ;             Child Loop BB0_184 Depth 6
                                        ;             Child Loop BB0_186 Depth 6
                                        ;             Child Loop BB0_188 Depth 6
                                        ;             Child Loop BB0_210 Depth 6
                                        ;             Child Loop BB0_218 Depth 6
                                        ;             Child Loop BB0_224 Depth 6
                                        ;             Child Loop BB0_233 Depth 6
                                        ;             Child Loop BB0_240 Depth 6
                                        ;             Child Loop BB0_243 Depth 6
                                        ;             Child Loop BB0_248 Depth 6
                                        ;             Child Loop BB0_255 Depth 6
                                        ;             Child Loop BB0_288 Depth 6
                                        ;             Child Loop BB0_296 Depth 6
                                        ;             Child Loop BB0_302 Depth 6
                                        ;             Child Loop BB0_311 Depth 6
                                        ;           Child Loop BB0_320 Depth 5
                                        ;           Child Loop BB0_323 Depth 5
                                        ;           Child Loop BB0_325 Depth 5
                                        ;           Child Loop BB0_327 Depth 5
                                        ;           Child Loop BB0_329 Depth 5
                                        ;           Child Loop BB0_331 Depth 5
                                        ;           Child Loop BB0_333 Depth 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], 7, v[4:5]
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e64 s1, 0, v129
	v_mov_b32_e32 v6, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=3
	v_add_co_u32 v18, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v16, vcc_lo
	global_load_b32 v6, v[18:19], off glc
.LBB0_13:                               ;   in Loop: Header=BB0_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[18:19], 5, v[4:5]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+8
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v6
	global_load_b32 v3, v[18:19], off
	v_add_nc_u32_e32 v6, s2, v129
	s_mov_b32 s2, 0x10100
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v18, 0xff00ff01, v6
	v_lshrrev_b32_e32 v18, 16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v18, 0x10100, v18
	v_sub_nc_u32_e32 v6, v6, v18
	v_add_co_u32 v18, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v16, vcc_lo
.LBB0_14:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr15_vgpr16
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_gt_u32_e32 0x100, v6
	s_xor_b32 s3, exec_lo, s3
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=4
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, 0x1800, v4, s[6:7]
	v_mad_u64_u32 v[15:16], null, v6, 24, v[21:22]
; %bb.16:                               ; %Flow1135
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_14 Depth=4
	s_add_u32 s6, s10, 0x2800
	v_add_nc_u32_e32 v21, 0xffffff00, v6
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0x1800, v4, s[6:7]
	v_lshrrev_b32_e32 v23, 8, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, v23, 24, v[15:16]
	v_and_b32_e32 v23, 0xff, v6
	global_load_b64 v[21:22], v[21:22], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[15:16], null, v23, 24, v[21:22]
.LBB0_18:                               ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v15, v[15:16], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v15, v3
	s_cbranch_vccz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_14 Depth=4
	s_ctz_i32_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s3, s3, 2
	v_mov_b32_e32 v15, s3
	ds_bpermute_b32 v15, v15, v6
	s_branch .LBB0_21
.LBB0_20:                               ;   in Loop: Header=BB0_14 Depth=4
	v_mov_b32_e32 v15, -1
.LBB0_21:                               ;   in Loop: Header=BB0_14 Depth=4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v15
	s_cmp_eq_u32 s5, -1
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_24
; %bb.22:                               ;   in Loop: Header=BB0_14 Depth=4
	s_cmpk_lt_u32 s5, 0x100
	s_cbranch_scc0 .LBB0_25
; %bb.23:                               ;   in Loop: Header=BB0_14 Depth=4
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, 0x1800, v4, s[6:7]
	s_mov_b32 s6, 0
	v_mad_u64_u32 v[15:16], null, s5, 24, v[21:22]
	s_branch .LBB0_26
.LBB0_24:                               ;   in Loop: Header=BB0_14 Depth=4
	s_mov_b32 s5, -1
                                        ; implicit-def: $vgpr15_vgpr16
	s_branch .LBB0_29
.LBB0_25:                               ;   in Loop: Header=BB0_14 Depth=4
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr15_vgpr16
.LBB0_26:                               ; %Flow1128
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_14 Depth=4
	s_add_i32 s6, s5, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_lshr_b32 s16, s6, 8
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_and_b32 s5, s5, 0xff
	v_mad_u64_u32 v[15:16], null, 0x1800, v4, s[6:7]
	v_mad_u64_u32 v[21:22], null, s16, 24, v[15:16]
	global_load_b64 v[21:22], v[21:22], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[15:16], null, s5, 24, v[21:22]
.LBB0_28:                               ; %Flow1129
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_mov_b32 s5, 0
.LBB0_29:                               ; %Flow1131
                                        ;   in Loop: Header=BB0_14 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_33
; %bb.30:                               ;   in Loop: Header=BB0_14 Depth=4
	v_add_nc_u32_e32 v6, s31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v15, 0xff00ff01, v6
	v_lshrrev_b32_e32 v15, 16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v15, 0x10100, v15
	v_sub_nc_u32_e32 v6, v6, v15
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_32
; %bb.31:                               ;   in Loop: Header=BB0_14 Depth=4
	global_store_b32 v[18:19], v6, off
.LBB0_32:                               ;   in Loop: Header=BB0_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	v_dual_mov_b32 v16, v12 :: v_dual_mov_b32 v15, v11
	s_sub_i32 s2, s2, s31
.LBB0_33:                               ;   in Loop: Header=BB0_14 Depth=4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_14 Depth=4
	s_mov_b32 s3, 0
	s_mov_b32 s5, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr6
	s_branch .LBB0_36
.LBB0_35:                               ;   in Loop: Header=BB0_14 Depth=4
	s_cmp_lt_i32 s2, 1
	s_mov_b32 s5, 0
	s_cselect_b32 s6, -1, 0
                                        ; implicit-def: $sgpr3
.LBB0_36:                               ; %Flow1137
                                        ;   in Loop: Header=BB0_14 Depth=4
	v_dual_mov_b32 v11, v15 :: v_dual_mov_b32 v12, v16
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_14
; %bb.37:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_11 Depth=3
	v_dual_mov_b32 v11, v15 :: v_dual_mov_b32 v12, v16
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_342
; %bb.38:                               ;   in Loop: Header=BB0_11 Depth=3
	v_and_b32_e32 v3, -2, v4
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e32 vcc_lo, v4, v7
	s_mov_b32 s3, 0
	v_cmp_gt_u32_e64 s2, 14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s34, s2
	s_cbranch_execz .LBB0_341
; %bb.39:                               ;   in Loop: Header=BB0_11 Depth=3
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_41
; %bb.40:                               ;   in Loop: Header=BB0_11 Depth=3
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 7, v[3:4]
	v_add_co_u32 v11, vcc_lo, s24, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s25, v12, vcc_lo
	global_load_b32 v4, v[11:12], off offset:2048 glc
.LBB0_41:                               ;   in Loop: Header=BB0_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s36, v4
	v_add_nc_u32_e32 v22, 2, v3
	s_mov_b32 s6, -1
	s_delay_alu instid0(VALU_DEP_2)
	s_cmp_gt_u32 s36, 0x100ff
	s_cbranch_scc1 .LBB0_340
; %bb.42:                               ;   in Loop: Header=BB0_11 Depth=3
	v_mov_b32_e32 v4, v5
	s_bcnt1_i32_b32 s35, exec_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+76
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+84
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, __unnamed_1@rel32@lo+68
	s_addc_u32 s7, s7, __unnamed_1@rel32@hi+76
	s_add_u32 s1, s24, 0x800
	v_lshlrev_b64 v[11:12], 7, v[3:4]
	v_lshlrev_b64 v[3:4], 5, v[3:4]
	v_lshrrev_b64 v[15:16], v22, 0xbf
	v_mbcnt_lo_u32_b32 v130, exec_lo, 0
	v_mov_b32_e32 v23, v5
	v_mov_b32_e32 v24, v5
	v_add_co_u32 v70, vcc_lo, s24, v11
	v_add_co_ci_u32_e32 v71, vcc_lo, s25, v12, vcc_lo
	v_add_co_u32 v80, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v81, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v82, vcc_lo, v3, s6
	v_add_co_ci_u32_e32 v83, vcc_lo, s7, v4, vcc_lo
	s_addc_u32 s2, s25, 0
	v_add_co_u32 v84, vcc_lo, s1, v11
	s_add_u32 s1, s24, 0x1000
	v_add_co_ci_u32_e32 v85, vcc_lo, s2, v12, vcc_lo
	s_addc_u32 s2, s25, 0
	v_add_co_u32 v86, vcc_lo, s1, v11
	s_add_u32 s1, s24, 0x2000
	v_add_co_ci_u32_e32 v87, vcc_lo, s2, v12, vcc_lo
	s_addc_u32 s2, s25, 0
	v_add_co_u32 v96, vcc_lo, s1, v11
	s_add_u32 s1, s24, 0x1800
	v_add_co_ci_u32_e32 v97, vcc_lo, s2, v12, vcc_lo
	s_addc_u32 s5, s25, 0
	v_add_co_u32 v98, vcc_lo, s1, v11
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+88
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+96
	v_add_co_ci_u32_e32 v99, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v100, vcc_lo, v3, s2
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, __unnamed_1@rel32@lo+84
	s_addc_u32 s7, s7, __unnamed_1@rel32@hi+92
	v_add_co_ci_u32_e32 v101, vcc_lo, s3, v4, vcc_lo
	v_and_b32_e32 v6, 1, v15
	v_add_co_u32 v102, vcc_lo, v3, s6
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+92
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+100
	v_add_co_ci_u32_e32 v103, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v112, vcc_lo, v3, s2
	v_cmp_eq_u32_e64 s1, 1, v6
	v_add_co_ci_u32_e32 v113, vcc_lo, s3, v4, vcc_lo
	v_mov_b32_e32 v25, v5
                                        ; implicit-def: $vgpr114_vgpr115
.LBB0_43:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_47 Depth 5
                                        ;           Child Loop BB0_75 Depth 5
                                        ;             Child Loop BB0_93 Depth 6
                                        ;             Child Loop BB0_101 Depth 6
                                        ;             Child Loop BB0_107 Depth 6
                                        ;             Child Loop BB0_116 Depth 6
                                        ;             Child Loop BB0_121 Depth 6
                                        ;             Child Loop BB0_123 Depth 6
                                        ;             Child Loop BB0_144 Depth 6
                                        ;             Child Loop BB0_152 Depth 6
                                        ;             Child Loop BB0_158 Depth 6
                                        ;             Child Loop BB0_167 Depth 6
                                        ;             Child Loop BB0_175 Depth 6
                                        ;             Child Loop BB0_178 Depth 6
                                        ;             Child Loop BB0_180 Depth 6
                                        ;             Child Loop BB0_182 Depth 6
                                        ;             Child Loop BB0_184 Depth 6
                                        ;             Child Loop BB0_186 Depth 6
                                        ;             Child Loop BB0_188 Depth 6
                                        ;             Child Loop BB0_210 Depth 6
                                        ;             Child Loop BB0_218 Depth 6
                                        ;             Child Loop BB0_224 Depth 6
                                        ;             Child Loop BB0_233 Depth 6
                                        ;             Child Loop BB0_240 Depth 6
                                        ;             Child Loop BB0_243 Depth 6
                                        ;             Child Loop BB0_248 Depth 6
                                        ;             Child Loop BB0_255 Depth 6
                                        ;             Child Loop BB0_288 Depth 6
                                        ;             Child Loop BB0_296 Depth 6
                                        ;             Child Loop BB0_302 Depth 6
                                        ;             Child Loop BB0_311 Depth 6
                                        ;           Child Loop BB0_320 Depth 5
                                        ;           Child Loop BB0_323 Depth 5
                                        ;           Child Loop BB0_325 Depth 5
                                        ;           Child Loop BB0_327 Depth 5
                                        ;           Child Loop BB0_329 Depth 5
                                        ;           Child Loop BB0_331 Depth 5
                                        ;           Child Loop BB0_333 Depth 5
	s_cmp_eq_u32 s36, 0
	s_mov_b32 s5, -1
	;;#ASMSTART
	;;#ASMEND
	s_cbranch_scc1 .LBB0_72
; %bb.44:                               ;   in Loop: Header=BB0_43 Depth=4
	v_cmp_eq_u32_e64 s2, 0, v130
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_46
; %bb.45:                               ;   in Loop: Header=BB0_43 Depth=4
	global_load_b32 v3, v[70:71], off glc
.LBB0_46:                               ;   in Loop: Header=BB0_43 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v6, v[80:81], off
	v_cvt_f32_u32_e32 v4, s36
	s_sub_i32 s3, 0, s36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, s3, v4
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s3, v3
	v_add_nc_u32_e32 v3, s3, v130
	s_mov_b32 s3, s36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v4, v11
	v_add_nc_u32_e32 v11, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v11
	v_mul_lo_u32 v4, v4, s36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v3, v4, vcc_lo
.LBB0_47:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x100, v12
	s_xor_b32 s6, exec_lo, s6
; %bb.48:                               ;   in Loop: Header=BB0_47 Depth=5
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, 0x1800, v22, s[16:17]
	v_mad_u64_u32 v[3:4], null, v12, 24, v[15:16]
; %bb.49:                               ; %Flow952
                                        ;   in Loop: Header=BB0_47 Depth=5
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_51
; %bb.50:                               ;   in Loop: Header=BB0_47 Depth=5
	s_add_u32 s16, s10, 0x2800
	v_add_nc_u32_e32 v15, 0xffffff00, v12
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	v_lshrrev_b32_e32 v18, 8, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v18, 24, v[3:4]
	v_and_b32_e32 v18, 0xff, v12
	global_load_b64 v[15:16], v[15:16], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v18, 24, v[15:16]
.LBB0_51:                               ;   in Loop: Header=BB0_47 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b32 v3, v[3:4], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v3, v6
	s_cbranch_vccz .LBB0_53
; %bb.52:                               ;   in Loop: Header=BB0_47 Depth=5
	s_ctz_i32_b32 s6, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s6, s6, 2
	v_mov_b32_e32 v3, s6
	ds_bpermute_b32 v3, v3, v12
	s_branch .LBB0_54
.LBB0_53:                               ;   in Loop: Header=BB0_47 Depth=5
	v_mov_b32_e32 v3, -1
.LBB0_54:                               ;   in Loop: Header=BB0_47 Depth=5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s7, v3
	s_cmp_eq_u32 s7, -1
	s_cselect_b32 s6, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_57
; %bb.55:                               ;   in Loop: Header=BB0_47 Depth=5
	s_cmpk_lt_u32 s7, 0x100
	s_cbranch_scc0 .LBB0_58
; %bb.56:                               ;   in Loop: Header=BB0_47 Depth=5
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	s_mov_b32 s16, 0
	v_mad_u64_u32 v[15:16], null, s7, 24, v[3:4]
	s_branch .LBB0_59
.LBB0_57:                               ;   in Loop: Header=BB0_47 Depth=5
	s_mov_b32 s7, -1
                                        ; implicit-def: $vgpr15_vgpr16
	s_branch .LBB0_62
.LBB0_58:                               ;   in Loop: Header=BB0_47 Depth=5
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr15_vgpr16
.LBB0_59:                               ; %Flow946
                                        ;   in Loop: Header=BB0_47 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_61
; %bb.60:                               ;   in Loop: Header=BB0_47 Depth=5
	s_add_i32 s16, s7, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_lshr_b32 s18, s16, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_and_b32 s7, s7, 0xff
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	v_mad_u64_u32 v[15:16], null, s18, 24, v[3:4]
	global_load_b64 v[3:4], v[15:16], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[15:16], null, s7, 24, v[3:4]
.LBB0_61:                               ; %Flow947
                                        ;   in Loop: Header=BB0_47 Depth=5
	s_mov_b32 s7, 0
.LBB0_62:                               ; %Flow948
                                        ;   in Loop: Header=BB0_47 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_66
; %bb.63:                               ;   in Loop: Header=BB0_47 Depth=5
	v_add_nc_u32_e32 v3, s35, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v11
	v_mul_lo_u32 v4, v4, s36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v3, v4, vcc_lo
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_65
; %bb.64:                               ;   in Loop: Header=BB0_47 Depth=5
	global_store_b32 v[70:71], v12, off
.LBB0_65:                               ;   in Loop: Header=BB0_47 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
	v_dual_mov_b32 v15, v114 :: v_dual_mov_b32 v16, v115
	s_sub_i32 s3, s3, s35
.LBB0_66:                               ;   in Loop: Header=BB0_47 Depth=5
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_47 Depth=5
	s_mov_b32 s6, 0
	s_mov_b32 s7, -1
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr12
	s_branch .LBB0_69
.LBB0_68:                               ;   in Loop: Header=BB0_47 Depth=5
	s_cmp_lt_i32 s3, 1
	s_mov_b32 s7, 0
	s_cselect_b32 s16, -1, 0
                                        ; implicit-def: $sgpr6
.LBB0_69:                               ; %Flow954
                                        ;   in Loop: Header=BB0_47 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB0_71
; %bb.70:                               ;   in Loop: Header=BB0_47 Depth=5
	v_dual_mov_b32 v115, v16 :: v_dual_mov_b32 v114, v15
	s_branch .LBB0_47
.LBB0_71:                               ; %loop.exit.guard903
                                        ;   in Loop: Header=BB0_43 Depth=4
	v_dual_mov_b32 v115, v16 :: v_dual_mov_b32 v114, v15
	s_xor_b32 s2, s7, -1
	s_branch .LBB0_73
.LBB0_72:                               ;   in Loop: Header=BB0_43 Depth=4
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr6
.LBB0_73:                               ; %Flow1121
                                        ;   in Loop: Header=BB0_43 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_314
; %bb.74:                               ; %.loopexit188
                                        ;   in Loop: Header=BB0_43 Depth=4
	v_mbcnt_lo_u32_b32 v131, exec_lo, 0
                                        ; implicit-def: $vgpr116_vgpr117
.LBB0_75:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB0_93 Depth 6
                                        ;             Child Loop BB0_101 Depth 6
                                        ;             Child Loop BB0_107 Depth 6
                                        ;             Child Loop BB0_116 Depth 6
                                        ;             Child Loop BB0_121 Depth 6
                                        ;             Child Loop BB0_123 Depth 6
                                        ;             Child Loop BB0_144 Depth 6
                                        ;             Child Loop BB0_152 Depth 6
                                        ;             Child Loop BB0_158 Depth 6
                                        ;             Child Loop BB0_167 Depth 6
                                        ;             Child Loop BB0_175 Depth 6
                                        ;             Child Loop BB0_178 Depth 6
                                        ;             Child Loop BB0_180 Depth 6
                                        ;             Child Loop BB0_182 Depth 6
                                        ;             Child Loop BB0_184 Depth 6
                                        ;             Child Loop BB0_186 Depth 6
                                        ;             Child Loop BB0_188 Depth 6
                                        ;             Child Loop BB0_210 Depth 6
                                        ;             Child Loop BB0_218 Depth 6
                                        ;             Child Loop BB0_224 Depth 6
                                        ;             Child Loop BB0_233 Depth 6
                                        ;             Child Loop BB0_240 Depth 6
                                        ;             Child Loop BB0_243 Depth 6
                                        ;             Child Loop BB0_248 Depth 6
                                        ;             Child Loop BB0_255 Depth 6
                                        ;             Child Loop BB0_288 Depth 6
                                        ;             Child Loop BB0_296 Depth 6
                                        ;             Child Loop BB0_302 Depth 6
                                        ;             Child Loop BB0_311 Depth 6
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s2, 0, v131
	v_mov_b32_e32 v3, 0
	s_mov_b32 s18, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v3, v[84:85], off glc
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s37, v3
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_cmp_eq_u32 s37, 0x10100
	s_cbranch_scc1 .LBB0_137
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=5
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_80
; %bb.79:                               ;   in Loop: Header=BB0_75 Depth=5
	v_mov_b32_e32 v69, v5
	global_atomic_cmpswap_b32 v3, v[86:87], v[68:69], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, 0x100, v3, vcc_lo
.LBB0_80:                               ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s38, v3
	s_cmp_lg_u32 s37, s38
	s_cbranch_scc1 .LBB0_138
; %bb.81:                               ;   in Loop: Header=BB0_75 Depth=5
	v_mbcnt_lo_u32_b32 v21, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_83
; %bb.82:                               ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v3, v[86:87], off glc
.LBB0_83:                               ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_mov_b32 s5, 2
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s20, 0x10100
	s_cbranch_scc1 .LBB0_171
; %bb.84:                               ;   in Loop: Header=BB0_75 Depth=5
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_88
; %bb.85:                               ;   in Loop: Header=BB0_75 Depth=5
	global_load_b64 v[28:29], v[96:97], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, s3, s6, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v4, s3, s7, v29, s3
	v_cmp_lt_u64_e64 s3, 0x752f, v[3:4]
	v_mov_b32_e32 v3, 1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s16, s3
	s_cbranch_execz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v26, s6 :: v_dual_mov_b32 v27, s7
	global_atomic_cmpswap_b64 v[3:4], v[96:97], v[26:29], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s3, v[3:4], v[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 1, 2, s3
.LBB0_87:                               ; %Flow1110
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s16
.LBB0_88:                               ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s5
	v_readfirstlane_b32 s39, v3
	s_mov_b32 s5, 1
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s39, 1
	s_cbranch_scc1 .LBB0_171
; %bb.89:                               ;   in Loop: Header=BB0_75 Depth=5
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s21, vcc_lo
	s_cbranch_execz .LBB0_118
; %bb.90:                               ;   in Loop: Header=BB0_75 Depth=5
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s3, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB0_96
; %bb.91:                               ;   in Loop: Header=BB0_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB0_95
; %bb.92:                               ; %.preheader3.i.i.i117.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_93:                               ; %.preheader3.i.i.i117
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v28
	v_and_b32_e32 v6, v16, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_93
; %bb.94:                               ; %Flow1104
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_95:                               ; %Flow1106
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_96:                               ; %.loopexit4.i.i.i112
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[26:29], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s40, s7, 24
	s_mul_hi_u32 s41, s6, 24
	s_mul_i32 s42, s6, 24
	s_and_saveexec_b32 s43, s3
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s41, s40
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v26, s42
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s43
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_mov_b32_e32 v15, v5
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v31, s7
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v29, s5
	v_mov_b32_e32 v30, s6
	v_mov_b32_e32 v28, s4
	s_clause 0x3
	global_store_b128 v[11:12], v[15:18], off
	global_store_b128 v[11:12], v[28:31], off offset:16
	global_store_b128 v[11:12], v[28:31], off offset:32
	global_store_b128 v[11:12], v[28:31], off offset:48
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB0_106
; %bb.99:                               ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x1
	global_load_b64 v[134:135], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v132, s18 :: v_dual_mov_b32 v133, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[134:135], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[132:135], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[134:135]
	s_cbranch_execz .LBB0_102
; %bb.100:                              ; %.preheader1.i.i.i115.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_101:                              ; %.preheader1.i.i.i115
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s18 :: v_dual_mov_b32 v29, s19
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[28:31], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[30:31]
	v_dual_mov_b32 v31, v16 :: v_dual_mov_b32 v30, v15
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_101
.LBB0_102:                              ; %Flow1102
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[15:16], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[15:16], v[4:5], off offset:8
.LBB0_104:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[18:19], v[15:16], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	s_cbranch_vccnz .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v4, v[15:16], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[18:19], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_106:                              ; %Flow1103
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s41, s41, s40
	v_add_co_u32 v3, vcc_lo, v26, s42
	v_add_co_ci_u32_e32 v4, vcc_lo, s41, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_107:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_107 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_109:                              ;   in Loop: Header=BB0_107 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_111
; %bb.110:                              ;   in Loop: Header=BB0_107 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB0_112
.LBB0_111:                              ;   in Loop: Header=BB0_107 Depth=6
	s_mov_b32 s5, -1
.LBB0_112:                              ; %Flow1097
                                        ;   in Loop: Header=BB0_107 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_107
; %bb.113:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB0_117
; %bb.114:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17] offset:24 glc
	global_load_b64 v[18:19], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v12, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v29, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v27, vcc_lo, s19, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[26:27]
	v_dual_cndmask_b32 v27, v27, v28 :: v_dual_cndmask_b32 v26, v26, v6
	v_mov_b32_e32 v28, v15
	v_and_b32_e32 v6, v27, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v26, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v18, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v6, vcc_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_117
; %bb.115:                              ; %.preheader.i.i.i114.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s3, 0
.LBB0_116:                              ; %.preheader.i.i.i114
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[11:12], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[28:29]
	v_dual_mov_b32 v29, v16 :: v_dual_mov_b32 v28, v15
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_116
.LBB0_117:                              ; %Flow1095
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_118:                              ; %Flow1107
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_cmp_eq_u64 s[18:19], 0
	s_cbranch_scc1 .LBB0_170
; %bb.119:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s3, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v11, s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x300, v11
	s_cbranch_execz .LBB0_122
; %bb.120:                              ; %.preheader175.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	v_lshlrev_b32_e32 v3, 3, v11
	s_bcnt1_i32_b32 s6, s3
	s_mov_b32 s16, 0
	s_lshl_b32 s7, s6, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, s18, v3
	v_add_co_ci_u32_e64 v4, null, s19, 0, s3
.LBB0_121:                              ; %.preheader175
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v6, v5 :: v_dual_add_nc_u32 v11, s6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v11
	global_store_b64 v[3:4], v[5:6], off
	v_add_co_u32 v3, s3, v3, s7
	v_add_co_ci_u32_e64 v4, s3, 0, v4, s3
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_121
.LBB0_122:                              ; %Flow1089
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $sgpr5
.LBB0_123:                              ; %.loopexit176
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_mov_b32_e32 v3, s20
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_125
; %bb.124:                              ;   in Loop: Header=BB0_123 Depth=6
	global_load_b32 v3, v[86:87], off glc
.LBB0_125:                              ;   in Loop: Header=BB0_123 Depth=6
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s3, s5
	s_cmp_lg_u32 s20, 0x10100
	s_cbranch_scc0 .LBB0_132
; %bb.126:                              ;   in Loop: Header=BB0_123 Depth=6
	v_mov_b32_e32 v3, s39
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB0_130
; %bb.127:                              ;   in Loop: Header=BB0_123 Depth=6
	s_add_i32 s3, s20, 0xffffff00
	v_mov_b32_e32 v6, v5
	s_lshr_b32 s3, s3, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	v_mad_u64_u32 v[11:12], null, s3, 24, v[3:4]
	v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s3, 0, v[3:4]
	v_mov_b32_e32 v3, s39
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s7, s3
	s_cbranch_execz .LBB0_129
; %bb.128:                              ;   in Loop: Header=BB0_123 Depth=6
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[86:87], v68, off
	v_mov_b32_e32 v3, 0
.LBB0_129:                              ; %Flow1082
                                        ;   in Loop: Header=BB0_123 Depth=6
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_130:                              ;   in Loop: Header=BB0_123 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_readfirstlane_b32 s3, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_133
; %bb.131:                              ;   in Loop: Header=BB0_123 Depth=6
	s_mov_b32 s6, 0
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_sleep 2
                                        ; implicit-def: $sgpr39
	s_branch .LBB0_134
.LBB0_132:                              ;   in Loop: Header=BB0_123 Depth=6
	s_mov_b32 s16, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr7
	s_branch .LBB0_135
.LBB0_133:                              ;   in Loop: Header=BB0_123 Depth=6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr3
.LBB0_134:                              ; %Flow1086
                                        ;   in Loop: Header=BB0_123 Depth=6
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_mov_b32 s7, 0
	s_mov_b32 s16, 0
	s_or_b32 s5, s5, s17
.LBB0_135:                              ; %Flow1085
                                        ;   in Loop: Header=BB0_123 Depth=6
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_139
; %bb.136:                              ;   in Loop: Header=BB0_123 Depth=6
	s_mov_b32 s39, s3
	s_branch .LBB0_123
.LBB0_137:                              ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v117, v4 :: v_dual_mov_b32 v116, v3
	s_branch .LBB0_199
.LBB0_138:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr18
	s_branch .LBB0_191
.LBB0_139:                              ; %loop.exit.guard909
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB0_169
; %bb.140:                              ;   in Loop: Header=BB0_75 Depth=5
	s_and_saveexec_b32 s40, s5
	s_cbranch_execz .LBB0_168
; %bb.141:                              ;   in Loop: Header=BB0_75 Depth=5
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s3, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB0_147
; %bb.142:                              ;   in Loop: Header=BB0_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB0_146
; %bb.143:                              ; %.preheader3.i.i.i124.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_144:                              ; %.preheader3.i.i.i124
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v28
	v_and_b32_e32 v6, v16, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_144
; %bb.145:                              ; %Flow1077
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_146:                              ; %Flow1079
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_147:                              ; %.loopexit4.i.i.i119
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[26:29], v5, s[16:17]
	v_readfirstlane_b32 s20, v11
	v_readfirstlane_b32 s21, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s41, s7, 24
	s_mul_hi_u32 s42, s6, 24
	s_mul_i32 s43, s6, 24
	s_and_saveexec_b32 s44, s3
	s_cbranch_execz .LBB0_149
; %bb.148:                              ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s42, s41
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v26, s43
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB0_149:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s44
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v11, s18 :: v_dual_mov_b32 v12, s19
	v_dual_mov_b32 v31, s7 :: v_dual_mov_b32 v30, s6
	v_dual_mov_b32 v29, s5 :: v_dual_mov_b32 v28, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[28:31], off offset:8
	global_store_b128 v[3:4], v[28:31], off offset:24
	global_store_b128 v[3:4], v[28:31], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB0_157
; %bb.150:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x1
	global_load_b64 v[134:135], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v132, s20 :: v_dual_mov_b32 v133, s21
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s21, v4
	v_and_b32_e32 v3, s20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[134:135], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[132:135], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[134:135]
	s_cbranch_execz .LBB0_153
; %bb.151:                              ; %.preheader1.i.i.i122.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_152:                              ; %.preheader1.i.i.i122
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s20 :: v_dual_mov_b32 v29, s21
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[28:31], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[30:31]
	v_dual_mov_b32 v31, v12 :: v_dual_mov_b32 v30, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_152
.LBB0_153:                              ; %Flow1075
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[11:12], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_155
; %bb.154:                              ;   in Loop: Header=BB0_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB0_155:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB0_157
; %bb.156:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_157:                              ; %Flow1076
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s42, s42, s41
	v_add_co_u32 v3, vcc_lo, v26, s43
	v_add_co_ci_u32_e32 v4, vcc_lo, s42, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_158:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB0_160
; %bb.159:                              ;   in Loop: Header=BB0_158 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_160:                              ;   in Loop: Header=BB0_158 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_158 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB0_163
.LBB0_162:                              ;   in Loop: Header=BB0_158 Depth=6
	s_mov_b32 s5, -1
.LBB0_163:                              ; %Flow1070
                                        ;   in Loop: Header=BB0_158 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_158
; %bb.164:                              ;   in Loop: Header=BB0_75 Depth=5
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_168
; %bb.165:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	global_load_b64 v[11:12], v5, s[16:17] offset:24 glc
	global_load_b64 v[15:16], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v28, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v21, vcc_lo
	v_mov_b32_e32 v29, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v27, v19, v21 :: v_dual_cndmask_b32 v26, v18, v6
	v_and_b32_e32 v4, v27, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v26, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_168
; %bb.166:                              ; %.preheader.i.i.i121.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s3, 0
.LBB0_167:                              ; %.preheader.i.i.i121
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[3:4], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_167
.LBB0_168:                              ; %Flow1080
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s40
	s_mov_b32 s7, s39
.LBB0_169:                              ; %Flow1081
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s39, s7
.LBB0_170:                              ; %Flow1091
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, s39
.LBB0_171:                              ; %__ockl_devmem_request.exit125
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, 0
	s_cselect_b32 s3, -1, 0
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_190
; %bb.172:                              ;   in Loop: Header=BB0_75 Depth=5
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_189
; %bb.173:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b64 v[3:4], v[96:97], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s6, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_189
; %bb.174:                              ;   in Loop: Header=BB0_75 Depth=5
	v_sub_nc_u32_e32 v3, 0x7530, v3
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s7, s6, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s16, s6
	s_addc_u32 s7, s17, s7
.LBB0_175:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x659
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_178
; %bb.176:                              ; %.preheader11.i138
                                        ;   in Loop: Header=BB0_175 Depth=6
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB0_175
.LBB0_177:                              ; %.preheader9.i137
                                        ;   in Loop: Header=BB0_178 Depth=6
	s_sleep 63
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_178:                              ; %Flow1061
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x326
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB0_177
; %bb.179:                              ; %Flow1058
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_add_u32 s20, s16, 0x18c
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_182
.LBB0_180:                              ; %.preheader7.i136
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 31
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x18c
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_180
	s_branch .LBB0_182
.LBB0_181:                              ; %.preheader5.i135
                                        ;   in Loop: Header=BB0_182 Depth=6
	s_sleep 15
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_182:                              ; %.loopexit8.i128
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0xc0
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB0_181
	s_branch .LBB0_184
.LBB0_183:                              ; %.preheader3.i134
                                        ;   in Loop: Header=BB0_184 Depth=6
	s_sleep 7
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_184:                              ; %Flow1052
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x59
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB0_183
	s_branch .LBB0_186
.LBB0_185:                              ; %.preheader1.i133
                                        ;   in Loop: Header=BB0_186 Depth=6
	s_sleep 3
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_186:                              ; %Flow1049
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 38
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB0_185
; %bb.187:                              ; %Flow1046
                                        ;   in Loop: Header=BB0_75 Depth=5
	v_cmp_le_u64_e64 s16, s[6:7], s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_189
.LBB0_188:                              ; %.preheader.i132
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s16, s[6:7], s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_188
.LBB0_189:                              ; %__ockl_rtcwait_u32.exit139
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s18
	s_cmp_lg_u32 s5, 2
	v_mov_b32_e32 v117, s4
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v116, 0, 1, s5
.LBB0_190:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s18, 0
.LBB0_191:                              ; %Flow1113
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_199
; %bb.192:                              ;   in Loop: Header=BB0_75 Depth=5
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_196
; %bb.193:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b64 v[28:29], v[98:99], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s6, v28
	v_sub_co_ci_u32_e32 v4, vcc_lo, s7, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[3:4]
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v26, s6 :: v_dual_mov_b32 v27, s7
	global_atomic_cmpswap_b64 v[3:4], v[98:99], v[26:29], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[28:29]
	v_mov_b32_e32 v4, s4
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
.LBB0_195:                              ; %Flow1040
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_196:                              ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_readfirstlane_b32 s6, v3
	v_readfirstlane_b32 s7, v4
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_200
; %bb.197:                              ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v15, s6
.LBB0_198:                              ; %Flow1039
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v117, v16 :: v_dual_mov_b32 v116, v15
.LBB0_199:                              ; %Flow1116
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_xor_b32 s2, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_75
	s_branch .LBB0_315
.LBB0_200:                              ;   in Loop: Header=BB0_75 Depth=5
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v15 :: v_dual_mov_b32 v4, v16
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_236
; %bb.201:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x1
	global_load_b64 v[3:4], v5, s[12:13] glc
	global_load_b64 v[11:12], v5, s[14:15]
	s_waitcnt vmcnt(0)
	v_cmp_ge_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_cbranch_vccnz .LBB0_205
; %bb.202:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s5, exec_lo
	s_mov_b32 s2, exec_lo
	v_mbcnt_lo_u32_b32 v6, s5, 0
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_204
; %bb.203:                              ;   in Loop: Header=BB0_75 Depth=5
	s_bcnt1_i32_b32 s5, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s5, s5, 21
	v_mov_b32_e32 v4, s5
	global_atomic_add_u64 v[3:4], v5, v[4:5], s[12:13] glc
.LBB0_204:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v4
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x200000, v6, s[6:7]
	v_cmp_ge_u64_e64 s2, v[3:4], v[11:12]
	s_branch .LBB0_206
.LBB0_205:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr3_vgpr4
.LBB0_206:                              ; %Flow1037
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB0_235
; %bb.207:                              ;   in Loop: Header=BB0_75 Depth=5
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_213
; %bb.208:                              ;   in Loop: Header=BB0_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v18, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB0_212
; %bb.209:                              ; %.preheader3.i.i.i145.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_210:                              ; %.preheader3.i.i.i145
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[16:17] offset:40
	global_load_b64 v[26:27], v5, s[16:17]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v18, v28
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v12 :: v_dual_and_b32 v6, v19, v29
	v_mad_u64_u32 v[18:19], null, v6, 24, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v12, v18
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_210
; %bb.211:                              ; %Flow1033
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_212:                              ; %Flow1035
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_213:                              ; %.loopexit4.i.i.i140
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[16:17] offset:40
	global_load_b128 v[26:29], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v18
	v_readfirstlane_b32 s7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s21, s7, 24
	s_mul_hi_u32 s39, s6, 24
	s_mul_i32 s40, s6, 24
	s_and_saveexec_b32 s41, s2
	s_cbranch_execz .LBB0_215
; %bb.214:                              ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s39, s21
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, s40
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[18:19], v[11:14], off offset:8
.LBB0_215:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s41
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v31, s7
	v_dual_mov_b32 v19, v5 :: v_dual_mov_b32 v30, s6
	v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v28, s4
	v_mov_b32_e32 v29, s5
	s_clause 0x3
	global_store_b128 v[11:12], v[18:21], off
	global_store_b128 v[11:12], v[28:31], off offset:16
	global_store_b128 v[11:12], v[28:31], off offset:32
	global_store_b128 v[11:12], v[28:31], off offset:48
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_223
; %bb.216:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x1
	global_load_b64 v[134:135], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v132, s18 :: v_dual_mov_b32 v133, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[134:135], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[132:135], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[134:135]
	s_cbranch_execz .LBB0_219
; %bb.217:                              ; %.preheader1.i.i.i143.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_218:                              ; %.preheader1.i.i.i143
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s18 :: v_dual_mov_b32 v29, s19
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[28:31], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[30:31]
	v_dual_mov_b32 v31, v19 :: v_dual_mov_b32 v30, v18
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_218
.LBB0_219:                              ; %Flow1031
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[18:19], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_221
; %bb.220:                              ;   in Loop: Header=BB0_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[18:19], v[4:5], off offset:8
.LBB0_221:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[28:29], v[18:19], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[28:29]
	s_cbranch_vccnz .LBB0_223
; %bb.222:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v4, v[18:19], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[28:29], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_223:                              ; %Flow1032
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s39, s39, s21
	v_add_co_u32 v3, vcc_lo, v26, s40
	v_add_co_ci_u32_e32 v4, vcc_lo, s39, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_224:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_226
; %bb.225:                              ;   in Loop: Header=BB0_224 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_226:                              ;   in Loop: Header=BB0_224 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_228
; %bb.227:                              ;   in Loop: Header=BB0_224 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB0_229
.LBB0_228:                              ;   in Loop: Header=BB0_224 Depth=6
	s_mov_b32 s5, -1
.LBB0_229:                              ; %Flow1026
                                        ;   in Loop: Header=BB0_224 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_224
; %bb.230:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_234
; %bb.231:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17] offset:24 glc
	global_load_b64 v[28:29], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v26, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v27, vcc_lo, s19, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[26:27]
	v_dual_cndmask_b32 v27, v27, v21 :: v_dual_cndmask_b32 v26, v26, v6
	v_and_b32_e32 v6, v27, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v26, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v28, v11
	v_mov_b32_e32 v28, v18
	v_add_co_ci_u32_e32 v12, vcc_lo, v29, v6, vcc_lo
	v_mov_b32_e32 v29, v19
	global_store_b64 v[11:12], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[18:19]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_234
; %bb.232:                              ; %.preheader.i.i.i142.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s2, 0
.LBB0_233:                              ; %.preheader.i.i.i142
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[11:12], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[28:29]
	v_dual_mov_b32 v29, v19 :: v_dual_mov_b32 v28, v18
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_233
.LBB0_234:                              ; %Flow1024
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_235:                              ; %Flow1038
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_236:                              ; %__ockl_devmem_request.exit146
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v3
	v_readfirstlane_b32 s17, v4
	s_cmp_eq_u64 s[16:17], 0
	s_cbranch_scc1 .LBB0_281
; %bb.237:                              ;   in Loop: Header=BB0_75 Depth=5
	v_mbcnt_lo_u32_b32 v4, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	global_load_b32 v6, v[82:83], off
	s_bcnt1_i32_b32 s3, exec_lo
	s_add_u32 s6, s16, 16
	s_addc_u32 s7, s17, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v3, 5, v3
	s_and_saveexec_b32 s2, s1
	s_xor_b32 s5, exec_lo, s2
	s_cbranch_execz .LBB0_245
; %bb.238:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v15, v[100:101], off
	s_mov_b32 s18, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB0_241
; %bb.239:                              ; %.preheader172.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s19, s3, 2
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB0_240:                              ; %.preheader172
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_add_nc_u32_e32 v16, s3, v16
	global_store_b32 v[11:12], v5, off
	v_add_co_u32 v11, s2, v11, s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s2, 0, v12, s2
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s20, vcc_lo, s20
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_240
.LBB0_241:                              ; %Flow1013
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s18
	global_load_b32 v16, v[102:103], off
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v15, v4, v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v11, v6
	s_cbranch_execz .LBB0_244
; %bb.242:                              ; %.preheader170.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	v_mul_lo_u32 v12, v15, s3
	s_mov_b32 s18, 0
.LBB0_243:                              ; %.preheader170
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_lshlrev_b32_e64 v15, v11, 1
	v_lshrrev_b32_e32 v16, 3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v11, v12
	v_and_b32_e32 v16, 0x1ffffffc, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v11, v6
	global_store_b32 v16, v15, s[6:7]
	s_or_b32 s18, vcc_lo, s18
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_243
.LBB0_244:                              ; %Flow1010
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_245:                              ; %Flow1018
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_250
; %bb.246:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s18, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB0_249
; %bb.247:                              ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v15, v[112:113], off
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s19, s3, 2
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB0_248:                              ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_add_nc_u32_e32 v16, s3, v16
	s_waitcnt vmcnt(0)
	global_store_b32 v[11:12], v15, off
	v_add_co_u32 v11, s2, v11, s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s2, 0, v12, s2
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s20, vcc_lo, s20
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_248
.LBB0_249:                              ; %Flow1016
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s18
.LBB0_250:                              ; %.loopexit
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_254
; %bb.251:                              ;   in Loop: Header=BB0_75 Depth=5
	v_and_b32_e32 v6, 31, v6
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v6
	s_cbranch_execz .LBB0_253
; %bb.252:                              ;   in Loop: Header=BB0_75 Depth=5
	v_add_nc_u32_e32 v4, -1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v11, v[3:4], off
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v6, -1, v6, v11
	global_store_b32 v[3:4], v6, off
.LBB0_253:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	global_store_b128 v5, v[22:25], s[16:17]
.LBB0_254:                              ; %Flow1007
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $sgpr5
.LBB0_255:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e64 s2, 0, v131
	v_mov_b32_e32 v3, s37
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_257
; %bb.256:                              ;   in Loop: Header=BB0_255 Depth=6
	global_load_b32 v3, v[84:85], off glc
.LBB0_257:                              ;   in Loop: Header=BB0_255 Depth=6
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s37, v3
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s5, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s3, s5
	s_cmp_eq_u32 s37, 0x10100
	s_cbranch_scc1 .LBB0_264
; %bb.258:                              ;   in Loop: Header=BB0_255 Depth=6
	v_mov_b32_e32 v3, s38
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_260
; %bb.259:                              ;   in Loop: Header=BB0_255 Depth=6
	global_load_b32 v3, v[86:87], off glc
.LBB0_260:                              ;   in Loop: Header=BB0_255 Depth=6
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s38, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u32 s37, s38
	s_cbranch_scc0 .LBB0_265
; %bb.261:                              ;   in Loop: Header=BB0_255 Depth=6
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_272
; %bb.262:                              ;   in Loop: Header=BB0_255 Depth=6
	s_cmpk_lt_u32 s37, 0x100
	s_cbranch_scc0 .LBB0_266
; %bb.263:                              ;   in Loop: Header=BB0_255 Depth=6
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[6:7]
	s_mov_b32 s6, 0
	v_mad_u64_u32 v[11:12], null, s37, 24, v[3:4]
	s_branch .LBB0_267
.LBB0_264:                              ;   in Loop: Header=BB0_255 Depth=6
	s_mov_b64 s[2:3], 0
	s_mov_b32 s20, -1
	s_mov_b32 s18, 0
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr38
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB0_277
.LBB0_265:                              ;   in Loop: Header=BB0_255 Depth=6
	s_mov_b32 s18, -1
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr38
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB0_276
.LBB0_266:                              ;   in Loop: Header=BB0_255 Depth=6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_267:                              ; %Flow999
                                        ;   in Loop: Header=BB0_255 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_269
; %bb.268:                              ;   in Loop: Header=BB0_255 Depth=6
	s_add_i32 s6, s37, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s18, s6, 8
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[6:7]
	s_and_b32 s6, s37, 0xff
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s18, 24, v[3:4]
	global_load_b64 v[3:4], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, s6, 24, v[3:4]
.LBB0_269:                              ;   in Loop: Header=BB0_255 Depth=6
	v_dual_mov_b32 v15, s37 :: v_dual_mov_b32 v4, s17
	v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v6, v5
	global_store_b32 v5, v15, s[16:17] offset:4
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off offset:8 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB0_271
; %bb.270:                              ;   in Loop: Header=BB0_255 Depth=6
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[84:85], v118, off
	v_dual_mov_b32 v3, v11 :: v_dual_mov_b32 v4, v12
.LBB0_271:                              ; %Flow997
                                        ;   in Loop: Header=BB0_255 Depth=6
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_272:                              ; %Flow1000
                                        ;   in Loop: Header=BB0_255 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s7, v4
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_274
; %bb.273:                              ;   in Loop: Header=BB0_255 Depth=6
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr38
	s_branch .LBB0_275
.LBB0_274:                              ;   in Loop: Header=BB0_255 Depth=6
	s_mov_b32 s19, 0
	s_and_not1_b32 s2, s2, exec_lo
	s_sleep 2
.LBB0_275:                              ; %Flow1005
                                        ;   in Loop: Header=BB0_255 Depth=6
	s_mov_b32 s18, 0
.LBB0_276:                              ; %Flow1004
                                        ;   in Loop: Header=BB0_255 Depth=6
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_mov_b32 s20, 0
	s_or_b32 s5, s3, s2
                                        ; implicit-def: $sgpr2_sgpr3
.LBB0_277:                              ; %Flow1003
                                        ;   in Loop: Header=BB0_255 Depth=6
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB0_255
; %bb.278:                              ; %loop.exit.guard913
                                        ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v16, s3 :: v_dual_mov_b32 v15, s2
	s_and_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_198
; %bb.279:                              ; %loop.exit.guard914
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_xor_b32 s2, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_282
; %bb.280:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s18, 0
	s_branch .LBB0_283
.LBB0_281:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s18, 0
	s_branch .LBB0_198
.LBB0_282:                              ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr6_sgpr7
.LBB0_283:                              ; %Flow994
                                        ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v15, s6
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_198
; %bb.284:                              ;   in Loop: Header=BB0_75 Depth=5
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_313
; %bb.285:                              ;   in Loop: Header=BB0_75 Depth=5
	s_load_b64 s[18:19], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_291
; %bb.286:                              ;   in Loop: Header=BB0_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[18:19] offset:40
	global_load_b64 v[15:16], v5, s[18:19]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB0_290
; %bb.287:                              ; %.preheader3.i.i.i152.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_288:                              ; %.preheader3.i.i.i152
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[18:19] offset:40
	global_load_b64 v[18:19], v5, s[18:19]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v28
	v_and_b32_e32 v6, v16, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_288
; %bb.289:                              ; %Flow990
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_290:                              ; %Flow992
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_291:                              ; %.loopexit4.i.i.i147
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[18:19] offset:40
	global_load_b128 v[26:29], v5, s[18:19]
	v_readfirstlane_b32 s20, v11
	v_readfirstlane_b32 s21, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s37, s7, 24
	s_mul_hi_u32 s38, s6, 24
	s_mul_i32 s39, s6, 24
	s_and_saveexec_b32 s40, s2
	s_cbranch_execz .LBB0_293
; %bb.292:                              ;   in Loop: Header=BB0_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s38, s37
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v26, s39
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB0_293:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s40
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
	v_dual_mov_b32 v31, s7 :: v_dual_mov_b32 v30, s6
	v_dual_mov_b32 v29, s5 :: v_dual_mov_b32 v28, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[28:31], off offset:8
	global_store_b128 v[3:4], v[28:31], off offset:24
	global_store_b128 v[3:4], v[28:31], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_301
; %bb.294:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x1
	global_load_b64 v[133:134], v5, s[18:19] offset:32 glc
	global_load_b64 v[3:4], v5, s[18:19] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v131, s20 :: v_dual_mov_b32 v132, s21
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s21, v4
	v_and_b32_e32 v3, s20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[133:134], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[131:134], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[133:134]
	s_cbranch_execz .LBB0_297
; %bb.295:                              ; %.preheader1.i.i.i150.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s7, 0
.LBB0_296:                              ; %.preheader1.i.i.i150
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s20 :: v_dual_mov_b32 v29, s21
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[28:31], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[30:31]
	v_dual_mov_b32 v31, v12 :: v_dual_mov_b32 v30, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_296
.LBB0_297:                              ; %Flow988
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[11:12], v5, s[18:19] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_299
; %bb.298:                              ;   in Loop: Header=BB0_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB0_299:                              ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB0_301
; %bb.300:                              ;   in Loop: Header=BB0_75 Depth=5
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_301:                              ; %Flow989
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s38, s38, s37
	v_add_co_u32 v3, vcc_lo, v26, s39
	v_add_co_ci_u32_e32 v4, vcc_lo, s38, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_302:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_304
; %bb.303:                              ;   in Loop: Header=BB0_302 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_304:                              ;   in Loop: Header=BB0_302 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_306
; %bb.305:                              ;   in Loop: Header=BB0_302 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB0_307
.LBB0_306:                              ;   in Loop: Header=BB0_302 Depth=6
	s_mov_b32 s5, -1
.LBB0_307:                              ; %Flow983
                                        ;   in Loop: Header=BB0_302 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_302
; %bb.308:                              ;   in Loop: Header=BB0_75 Depth=5
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_312
; %bb.309:                              ;   in Loop: Header=BB0_75 Depth=5
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[18:19] offset:40
	global_load_b64 v[11:12], v5, s[18:19] offset:24 glc
	global_load_b64 v[15:16], v5, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v28, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v21, vcc_lo
	v_mov_b32_e32 v29, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v27, v19, v21 :: v_dual_cndmask_b32 v26, v18, v6
	v_and_b32_e32 v4, v27, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v26, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_312
; %bb.310:                              ; %.preheader.i.i.i149.preheader
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_mov_b32 s2, 0
.LBB0_311:                              ; %.preheader.i.i.i149
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ;           Parent Loop BB0_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[3:4], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_311
.LBB0_312:                              ; %Flow981
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v131, 0
.LBB0_313:                              ; %Flow993
                                        ;   in Loop: Header=BB0_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v15, v116 :: v_dual_mov_b32 v16, v117
	s_mov_b32 s18, -1
	s_branch .LBB0_198
.LBB0_314:                              ;   in Loop: Header=BB0_43 Depth=4
                                        ; implicit-def: $vgpr114_vgpr115
                                        ; implicit-def: $sgpr36
                                        ; implicit-def: $vgpr130
	s_branch .LBB0_338
.LBB0_315:                              ;   in Loop: Header=BB0_43 Depth=4
	v_cmp_ne_u64_e64 s5, 1, v[116:117]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_317
; %bb.316:                              ;   in Loop: Header=BB0_43 Depth=4
	v_dual_mov_b32 v114, v116 :: v_dual_mov_b32 v115, v117
	s_branch .LBB0_337
.LBB0_317:                              ;   in Loop: Header=BB0_43 Depth=4
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s16, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_334
; %bb.318:                              ;   in Loop: Header=BB0_43 Depth=4
	global_load_b64 v[3:4], v[98:99], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_334
; %bb.319:                              ;   in Loop: Header=BB0_43 Depth=4
	v_sub_nc_u32_e32 v3, 0x4e20, v3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
.LBB0_320:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x659
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB0_323
; %bb.321:                              ; %.preheader11.i166
                                        ;   in Loop: Header=BB0_320 Depth=5
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB0_320
.LBB0_322:                              ; %.preheader9.i165
                                        ;   in Loop: Header=BB0_323 Depth=5
	s_sleep 63
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_323:                              ; %Flow975
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x326
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB0_322
; %bb.324:                              ; %Flow972
                                        ;   in Loop: Header=BB0_43 Depth=4
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB0_327
.LBB0_325:                              ; %.preheader7.i164
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 31
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB0_325
	s_branch .LBB0_327
.LBB0_326:                              ; %.preheader5.i163
                                        ;   in Loop: Header=BB0_327 Depth=5
	s_sleep 15
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_327:                              ; %.loopexit8.i156
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0xc0
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB0_326
	s_branch .LBB0_329
.LBB0_328:                              ; %.preheader3.i162
                                        ;   in Loop: Header=BB0_329 Depth=5
	s_sleep 7
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_329:                              ; %Flow966
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x59
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB0_328
	s_branch .LBB0_331
.LBB0_330:                              ; %.preheader1.i161
                                        ;   in Loop: Header=BB0_331 Depth=5
	s_sleep 3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_331:                              ; %Flow963
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 38
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB0_330
; %bb.332:                              ; %Flow960
                                        ;   in Loop: Header=BB0_43 Depth=4
	v_cmp_le_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_334
.LBB0_333:                              ; %.preheader.i160
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_11 Depth=3
                                        ;         Parent Loop BB0_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_333
.LBB0_334:                              ; %__ockl_rtcwait_u32.exit167
                                        ;   in Loop: Header=BB0_43 Depth=4
	s_or_b32 exec_lo, exec_lo, s16
	v_mov_b32_e32 v3, s36
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v130
	s_cbranch_execz .LBB0_336
; %bb.335:                              ;   in Loop: Header=BB0_43 Depth=4
	global_load_b32 v3, v[84:85], off glc
.LBB0_336:                              ;   in Loop: Header=BB0_43 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s36, v3
.LBB0_337:                              ;   in Loop: Header=BB0_43 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v15, v114 :: v_dual_mov_b32 v16, v115
	s_mov_b32 s6, 0
.LBB0_338:                              ; %Flow1122
                                        ;   in Loop: Header=BB0_43 Depth=4
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_43
; %bb.339:                              ; %Flow1123
                                        ;   in Loop: Header=BB0_11 Depth=3
	v_mov_b32_e32 v22, v7
.LBB0_340:                              ; %Flow1124
                                        ;   in Loop: Header=BB0_11 Depth=3
	v_dual_mov_b32 v11, v15 :: v_dual_mov_b32 v12, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v4, v22
	s_and_b32 s3, s6, exec_lo
.LBB0_341:                              ; %Flow1126
                                        ;   in Loop: Header=BB0_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s34
.LBB0_342:                              ; %.loopexit187
                                        ;   in Loop: Header=BB0_11 Depth=3
	s_xor_b32 s1, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s30, s1, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB0_11
; %bb.343:                              ; %Flow1139
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_mov_b32 s1, 0
	s_branch .LBB0_345
.LBB0_344:                              ;   in Loop: Header=BB0_6 Depth=2
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_345:                              ; %Flow1321
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_642
; %bb.346:                              ;   in Loop: Header=BB0_6 Depth=2
	v_mbcnt_lo_u32_b32 v70, exec_lo, 0
	s_bcnt1_i32_b32 s30, exec_lo
                                        ; implicit-def: $vgpr28_vgpr29
.LBB0_347:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_351 Depth 4
                                        ;         Child Loop BB0_378 Depth 4
                                        ;           Child Loop BB0_396 Depth 5
                                        ;           Child Loop BB0_404 Depth 5
                                        ;           Child Loop BB0_410 Depth 5
                                        ;           Child Loop BB0_419 Depth 5
                                        ;           Child Loop BB0_424 Depth 5
                                        ;           Child Loop BB0_426 Depth 5
                                        ;           Child Loop BB0_447 Depth 5
                                        ;           Child Loop BB0_455 Depth 5
                                        ;           Child Loop BB0_461 Depth 5
                                        ;           Child Loop BB0_470 Depth 5
                                        ;           Child Loop BB0_478 Depth 5
                                        ;           Child Loop BB0_481 Depth 5
                                        ;           Child Loop BB0_483 Depth 5
                                        ;           Child Loop BB0_485 Depth 5
                                        ;           Child Loop BB0_487 Depth 5
                                        ;           Child Loop BB0_489 Depth 5
                                        ;           Child Loop BB0_491 Depth 5
                                        ;           Child Loop BB0_513 Depth 5
                                        ;           Child Loop BB0_521 Depth 5
                                        ;           Child Loop BB0_527 Depth 5
                                        ;           Child Loop BB0_536 Depth 5
                                        ;           Child Loop BB0_543 Depth 5
                                        ;           Child Loop BB0_546 Depth 5
                                        ;           Child Loop BB0_551 Depth 5
                                        ;           Child Loop BB0_558 Depth 5
                                        ;           Child Loop BB0_591 Depth 5
                                        ;           Child Loop BB0_599 Depth 5
                                        ;           Child Loop BB0_605 Depth 5
                                        ;           Child Loop BB0_614 Depth 5
                                        ;         Child Loop BB0_623 Depth 4
                                        ;         Child Loop BB0_626 Depth 4
                                        ;         Child Loop BB0_628 Depth 4
                                        ;         Child Loop BB0_630 Depth 4
                                        ;         Child Loop BB0_632 Depth 4
                                        ;         Child Loop BB0_634 Depth 4
                                        ;         Child Loop BB0_636 Depth 4
	s_delay_alu instid0(VALU_DEP_2)
	s_cmp_eq_u32 s29, 0
	s_mov_b32 s5, -1
	;;#ASMSTART
	;;#ASMEND
	s_cbranch_scc1 .LBB0_375
; %bb.348:                              ;   in Loop: Header=BB0_347 Depth=3
	v_cmp_eq_u32_e64 s1, 0, v70
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_350
; %bb.349:                              ;   in Loop: Header=BB0_347 Depth=3
	global_load_b32 v3, v[34:35], off glc
.LBB0_350:                              ;   in Loop: Header=BB0_347 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v6, v[36:37], off
	v_cvt_f32_u32_e32 v4, s29
	s_sub_i32 s2, 0, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, s2, v4
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s2, v3
	v_add_nc_u32_e32 v3, s2, v70
	s_mov_b32 s2, s29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v4, v11
	v_add_nc_u32_e32 v15, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v15
	v_mul_lo_u32 v4, v4, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v3, v4, vcc_lo
.LBB0_351:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x100, v16
	s_xor_b32 s3, exec_lo, s3
; %bb.352:                              ;   in Loop: Header=BB0_351 Depth=4
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0x1800, v7, s[6:7]
	v_mad_u64_u32 v[3:4], null, v16, 24, v[11:12]
; %bb.353:                              ; %Flow1148
                                        ;   in Loop: Header=BB0_351 Depth=4
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_355
; %bb.354:                              ;   in Loop: Header=BB0_351 Depth=4
	s_add_u32 s6, s10, 0x2800
	v_add_nc_u32_e32 v11, 0xffffff00, v16
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[6:7]
	v_lshrrev_b32_e32 v18, 8, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v18, 24, v[3:4]
	v_and_b32_e32 v18, 0xff, v16
	global_load_b64 v[11:12], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v18, 24, v[11:12]
.LBB0_355:                              ;   in Loop: Header=BB0_351 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v3, v[3:4], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v3, v6
	s_cbranch_vccz .LBB0_357
; %bb.356:                              ;   in Loop: Header=BB0_351 Depth=4
	s_ctz_i32_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s3, s3, 2
	v_mov_b32_e32 v3, s3
	ds_bpermute_b32 v3, v3, v16
	s_branch .LBB0_358
.LBB0_357:                              ;   in Loop: Header=BB0_351 Depth=4
	v_mov_b32_e32 v3, -1
.LBB0_358:                              ;   in Loop: Header=BB0_351 Depth=4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v3
	s_cmp_eq_u32 s6, -1
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_361
; %bb.359:                              ;   in Loop: Header=BB0_351 Depth=4
	s_cmpk_lt_u32 s6, 0x100
	s_cbranch_scc0 .LBB0_362
; %bb.360:                              ;   in Loop: Header=BB0_351 Depth=4
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_mov_b32 s7, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s6, 24, v[3:4]
	s_branch .LBB0_363
.LBB0_361:                              ;   in Loop: Header=BB0_351 Depth=4
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr11_vgpr12
	s_branch .LBB0_366
.LBB0_362:                              ;   in Loop: Header=BB0_351 Depth=4
	s_mov_b32 s7, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_363:                              ; %Flow1141
                                        ;   in Loop: Header=BB0_351 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_365
; %bb.364:                              ;   in Loop: Header=BB0_351 Depth=4
	s_add_i32 s7, s6, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_lshr_b32 s7, s7, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_and_b32 s6, s6, 0xff
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	v_mad_u64_u32 v[11:12], null, s7, 24, v[3:4]
	global_load_b64 v[3:4], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, s6, 24, v[3:4]
.LBB0_365:                              ; %Flow1142
                                        ;   in Loop: Header=BB0_351 Depth=4
	s_mov_b32 s6, 0
.LBB0_366:                              ; %Flow1144
                                        ;   in Loop: Header=BB0_351 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_370
; %bb.367:                              ;   in Loop: Header=BB0_351 Depth=4
	v_add_nc_u32_e32 v3, s30, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v15
	v_mul_lo_u32 v4, v4, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v3, v4, vcc_lo
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB0_369
; %bb.368:                              ;   in Loop: Header=BB0_351 Depth=4
	global_store_b32 v[34:35], v16, off
.LBB0_369:                              ;   in Loop: Header=BB0_351 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	v_dual_mov_b32 v11, v28 :: v_dual_mov_b32 v12, v29
	s_sub_i32 s2, s2, s30
.LBB0_370:                              ;   in Loop: Header=BB0_351 Depth=4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_372
; %bb.371:                              ;   in Loop: Header=BB0_351 Depth=4
	s_mov_b32 s3, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr16
	s_branch .LBB0_373
.LBB0_372:                              ;   in Loop: Header=BB0_351 Depth=4
	s_cmp_lt_i32 s2, 1
	s_mov_b32 s3, 0
	s_cselect_b32 s6, -1, 0
.LBB0_373:                              ; %Flow1150
                                        ;   in Loop: Header=BB0_351 Depth=4
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_351
; %bb.374:                              ; %loop.exit.guard922
                                        ;   in Loop: Header=BB0_347 Depth=3
	s_xor_b32 s1, s3, -1
	s_branch .LBB0_376
.LBB0_375:                              ;   in Loop: Header=BB0_347 Depth=3
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_376:                              ; %Flow1317
                                        ;   in Loop: Header=BB0_347 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_617
; %bb.377:                              ; %.loopexit190
                                        ;   in Loop: Header=BB0_347 Depth=3
	v_mbcnt_lo_u32_b32 v71, exec_lo, 0
                                        ; implicit-def: $vgpr30_vgpr31
.LBB0_378:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_396 Depth 5
                                        ;           Child Loop BB0_404 Depth 5
                                        ;           Child Loop BB0_410 Depth 5
                                        ;           Child Loop BB0_419 Depth 5
                                        ;           Child Loop BB0_424 Depth 5
                                        ;           Child Loop BB0_426 Depth 5
                                        ;           Child Loop BB0_447 Depth 5
                                        ;           Child Loop BB0_455 Depth 5
                                        ;           Child Loop BB0_461 Depth 5
                                        ;           Child Loop BB0_470 Depth 5
                                        ;           Child Loop BB0_478 Depth 5
                                        ;           Child Loop BB0_481 Depth 5
                                        ;           Child Loop BB0_483 Depth 5
                                        ;           Child Loop BB0_485 Depth 5
                                        ;           Child Loop BB0_487 Depth 5
                                        ;           Child Loop BB0_489 Depth 5
                                        ;           Child Loop BB0_491 Depth 5
                                        ;           Child Loop BB0_513 Depth 5
                                        ;           Child Loop BB0_521 Depth 5
                                        ;           Child Loop BB0_527 Depth 5
                                        ;           Child Loop BB0_536 Depth 5
                                        ;           Child Loop BB0_543 Depth 5
                                        ;           Child Loop BB0_546 Depth 5
                                        ;           Child Loop BB0_551 Depth 5
                                        ;           Child Loop BB0_558 Depth 5
                                        ;           Child Loop BB0_591 Depth 5
                                        ;           Child Loop BB0_599 Depth 5
                                        ;           Child Loop BB0_605 Depth 5
                                        ;           Child Loop BB0_614 Depth 5
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s1, 0, v71
	v_mov_b32_e32 v3, 0
	s_mov_b32 s18, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_380
; %bb.379:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v3, v[32:33], off glc
.LBB0_380:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s31, v3
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_cmp_eq_u32 s31, 0x10100
	s_cbranch_scc1 .LBB0_440
; %bb.381:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_383
; %bb.382:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mov_b32_e32 v69, v5
	global_atomic_cmpswap_b32 v3, v[48:49], v[68:69], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, 0x100, v3, vcc_lo
.LBB0_383:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s34, v3
	s_cmp_lg_u32 s31, s34
	s_cbranch_scc1 .LBB0_441
; %bb.384:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mbcnt_lo_u32_b32 v27, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v27
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_386
; %bb.385:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v3, v[48:49], off glc
.LBB0_386:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_mov_b32 s16, 2
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s20, 0x10100
	s_cbranch_scc1 .LBB0_474
; %bb.387:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_391
; %bb.388:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b64 v[23:24], v[50:51], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, s2, s6, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v4, s2, s7, v24, s2
	v_cmp_lt_u64_e64 s2, 0x752f, v[3:4]
	v_mov_b32_e32 v3, 1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_390
; %bb.389:                              ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v21, s6 :: v_dual_mov_b32 v22, s7
	global_atomic_cmpswap_b64 v[3:4], v[50:51], v[21:24], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s2, v[3:4], v[23:24]
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 1, 2, s2
.LBB0_390:                              ; %Flow1306
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_391:                              ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s16, 1
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s3, 1
	s_cbranch_scc1 .LBB0_474
; %bb.392:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s21, vcc_lo
	s_cbranch_execz .LBB0_421
; %bb.393:                              ;   in Loop: Header=BB0_378 Depth=4
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_399
; %bb.394:                              ;   in Loop: Header=BB0_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB0_398
; %bb.395:                              ; %.preheader3.i.i.i75.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s7, 0
.LBB0_396:                              ; %.preheader3.i.i.i75
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v23
	v_and_b32_e32 v6, v16, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_396
; %bb.397:                              ; %Flow1300
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_398:                              ; %Flow1302
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_399:                              ; %.loopexit4.i.i.i70
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[21:24], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s35, s7, 24
	s_mul_hi_u32 s36, s6, 24
	s_mul_i32 s37, s6, 24
	s_and_saveexec_b32 s38, s2
	s_cbranch_execz .LBB0_401
; %bb.400:                              ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s36, s35
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v21, s37
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB0_401:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s38
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_dual_mov_b32 v15, v5 :: v_dual_mov_b32 v26, s7
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v23, s4
	v_mov_b32_e32 v24, s5
	s_clause 0x3
	global_store_b128 v[11:12], v[15:18], off
	global_store_b128 v[11:12], v[23:26], off offset:16
	global_store_b128 v[11:12], v[23:26], off offset:32
	global_store_b128 v[11:12], v[23:26], off offset:48
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_409
; %bb.402:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v80, s18 :: v_dual_mov_b32 v81, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v21, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v22, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v5, v[80:83], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[82:83]
	s_cbranch_execz .LBB0_405
; %bb.403:                              ; %.preheader1.i.i.i73.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s7, 0
.LBB0_404:                              ; %.preheader1.i.i.i73
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v23, s18 :: v_dual_mov_b32 v24, s19
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[23:26], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[25:26]
	v_dual_mov_b32 v26, v16 :: v_dual_mov_b32 v25, v15
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_404
.LBB0_405:                              ; %Flow1298
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[15:16], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_407
; %bb.406:                              ;   in Loop: Header=BB0_378 Depth=4
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[15:16], v[4:5], off offset:8
.LBB0_407:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[18:19], v[15:16], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	s_cbranch_vccnz .LBB0_409
; %bb.408:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v4, v[15:16], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[18:19], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_409:                              ; %Flow1299
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s36, s36, s35
	v_add_co_u32 v3, vcc_lo, v21, s37
	v_add_co_ci_u32_e32 v4, vcc_lo, s36, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_410:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_412
; %bb.411:                              ;   in Loop: Header=BB0_410 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_412:                              ;   in Loop: Header=BB0_410 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_414
; %bb.413:                              ;   in Loop: Header=BB0_410 Depth=5
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB0_415
.LBB0_414:                              ;   in Loop: Header=BB0_410 Depth=5
	s_mov_b32 s5, -1
.LBB0_415:                              ; %Flow1293
                                        ;   in Loop: Header=BB0_410 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_410
; %bb.416:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_420
; %bb.417:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17] offset:24 glc
	global_load_b64 v[18:19], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v12, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v24, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v21, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v22, vcc_lo, s19, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[21:22]
	v_dual_cndmask_b32 v22, v22, v23 :: v_dual_cndmask_b32 v21, v21, v6
	v_dual_mov_b32 v23, v15 :: v_dual_and_b32 v6, v22, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v21, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v18, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v6, vcc_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_420
; %bb.418:                              ; %.preheader.i.i.i72.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s2, 0
.LBB0_419:                              ; %.preheader.i.i.i72
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[11:12], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[23:24]
	v_dual_mov_b32 v24, v16 :: v_dual_mov_b32 v23, v15
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_419
.LBB0_420:                              ; %Flow1291
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_421:                              ; %Flow1303
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_cmp_eq_u64 s[18:19], 0
	s_cbranch_scc1 .LBB0_473
; %bb.422:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s2, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v11, s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x300, v11
	s_cbranch_execz .LBB0_425
; %bb.423:                              ; %.preheader185.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	v_lshlrev_b32_e32 v3, 3, v11
	s_bcnt1_i32_b32 s6, s2
	s_mov_b32 s16, 0
	s_lshl_b32 s7, s6, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s2, s18, v3
	v_add_co_ci_u32_e64 v4, null, s19, 0, s2
.LBB0_424:                              ; %.preheader185
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v6, v5 :: v_dual_add_nc_u32 v11, s6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v11
	global_store_b64 v[3:4], v[5:6], off
	v_add_co_u32 v3, s2, v3, s7
	v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_424
.LBB0_425:                              ; %Flow1285
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $sgpr5
.LBB0_426:                              ; %.loopexit186
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e32 vcc_lo, 0, v27
	v_mov_b32_e32 v3, s20
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_428
; %bb.427:                              ;   in Loop: Header=BB0_426 Depth=5
	global_load_b32 v3, v[48:49], off glc
.LBB0_428:                              ;   in Loop: Header=BB0_426 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_and_not1_b32 s2, s5, exec_lo
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s2, s5
	s_cmp_lg_u32 s20, 0x10100
	s_cbranch_scc0 .LBB0_435
; %bb.429:                              ;   in Loop: Header=BB0_426 Depth=5
	v_mov_b32_e32 v3, s3
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB0_433
; %bb.430:                              ;   in Loop: Header=BB0_426 Depth=5
	s_add_i32 s2, s20, 0xffffff00
	v_mov_b32_e32 v6, v5
	s_lshr_b32 s2, s2, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	v_mad_u64_u32 v[11:12], null, s2, 24, v[3:4]
	v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s2, 0, v[3:4]
	v_mov_b32_e32 v3, s3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_432
; %bb.431:                              ;   in Loop: Header=BB0_426 Depth=5
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[48:49], v68, off
	v_mov_b32_e32 v3, 0
.LBB0_432:                              ; %Flow1278
                                        ;   in Loop: Header=BB0_426 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_433:                              ;   in Loop: Header=BB0_426 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB0_436
; %bb.434:                              ;   in Loop: Header=BB0_426 Depth=5
	s_mov_b32 s6, 0
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_sleep 2
                                        ; implicit-def: $sgpr3
	s_branch .LBB0_437
.LBB0_435:                              ;   in Loop: Header=BB0_426 Depth=5
	s_mov_b32 s16, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr7
	s_branch .LBB0_438
.LBB0_436:                              ;   in Loop: Header=BB0_426 Depth=5
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr2
.LBB0_437:                              ; %Flow1282
                                        ;   in Loop: Header=BB0_426 Depth=5
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_mov_b32 s7, 0
	s_mov_b32 s16, 0
	s_or_b32 s5, s5, s17
.LBB0_438:                              ; %Flow1281
                                        ;   in Loop: Header=BB0_426 Depth=5
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_442
; %bb.439:                              ;   in Loop: Header=BB0_426 Depth=5
	s_mov_b32 s3, s2
	s_branch .LBB0_426
.LBB0_440:                              ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v31, v4 :: v_dual_mov_b32 v30, v3
	s_branch .LBB0_502
.LBB0_441:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s5, -1
                                        ; implicit-def: $sgpr18
	s_branch .LBB0_494
.LBB0_442:                              ; %loop.exit.guard925
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB0_472
; %bb.443:                              ;   in Loop: Header=BB0_378 Depth=4
	s_and_saveexec_b32 s35, s5
	s_cbranch_execz .LBB0_471
; %bb.444:                              ;   in Loop: Header=BB0_378 Depth=4
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_450
; %bb.445:                              ;   in Loop: Header=BB0_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB0_449
; %bb.446:                              ; %.preheader3.i.i.i82.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s7, 0
.LBB0_447:                              ; %.preheader3.i.i.i82
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v23
	v_and_b32_e32 v6, v16, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_447
; %bb.448:                              ; %Flow1273
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_449:                              ; %Flow1275
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_450:                              ; %.loopexit4.i.i.i77
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[21:24], v5, s[16:17]
	v_readfirstlane_b32 s20, v11
	v_readfirstlane_b32 s21, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s36, s7, 24
	s_mul_hi_u32 s37, s6, 24
	s_mul_i32 s38, s6, 24
	s_and_saveexec_b32 s39, s2
	s_cbranch_execz .LBB0_452
; %bb.451:                              ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s37, s36
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB0_452:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s39
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v11, s18 :: v_dual_mov_b32 v12, s19
	v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v24, s5 :: v_dual_mov_b32 v23, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[23:26], off offset:8
	global_store_b128 v[3:4], v[23:26], off offset:24
	global_store_b128 v[3:4], v[23:26], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_460
; %bb.453:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v80, s20 :: v_dual_mov_b32 v81, s21
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s21, v4
	v_and_b32_e32 v3, s20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v21, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v22, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v5, v[80:83], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[82:83]
	s_cbranch_execz .LBB0_456
; %bb.454:                              ; %.preheader1.i.i.i80.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s7, 0
.LBB0_455:                              ; %.preheader1.i.i.i80
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v23, s20 :: v_dual_mov_b32 v24, s21
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[23:26], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_455
.LBB0_456:                              ; %Flow1271
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[11:12], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_458
; %bb.457:                              ;   in Loop: Header=BB0_378 Depth=4
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB0_458:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB0_460
; %bb.459:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_460:                              ; %Flow1272
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s37, s37, s36
	v_add_co_u32 v3, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v4, vcc_lo, s37, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_461:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB0_463
; %bb.462:                              ;   in Loop: Header=BB0_461 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_463:                              ;   in Loop: Header=BB0_461 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_465
; %bb.464:                              ;   in Loop: Header=BB0_461 Depth=5
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB0_466
.LBB0_465:                              ;   in Loop: Header=BB0_461 Depth=5
	s_mov_b32 s5, -1
.LBB0_466:                              ; %Flow1266
                                        ;   in Loop: Header=BB0_461 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_461
; %bb.467:                              ;   in Loop: Header=BB0_378 Depth=4
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_471
; %bb.468:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	global_load_b64 v[11:12], v5, s[16:17] offset:24 glc
	global_load_b64 v[15:16], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v23, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v21, vcc_lo
	v_mov_b32_e32 v24, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v22, v19, v21 :: v_dual_cndmask_b32 v21, v18, v6
	v_and_b32_e32 v4, v22, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v21, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_471
; %bb.469:                              ; %.preheader.i.i.i79.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s2, 0
.LBB0_470:                              ; %.preheader.i.i.i79
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[3:4], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_470
.LBB0_471:                              ; %Flow1276
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s35
	s_mov_b32 s7, s3
.LBB0_472:                              ; %Flow1277
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, s7
.LBB0_473:                              ; %Flow1287
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s16, s3
.LBB0_474:                              ; %__ockl_devmem_request.exit83
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 0
	s_cselect_b32 s5, -1, 0
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_493
; %bb.475:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_492
; %bb.476:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b64 v[3:4], v[50:51], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_492
; %bb.477:                              ;   in Loop: Header=BB0_378 Depth=4
	v_sub_nc_u32_e32 v3, 0x7530, v3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
.LBB0_478:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x659
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_481
; %bb.479:                              ; %.preheader11.i
                                        ;   in Loop: Header=BB0_478 Depth=5
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB0_478
.LBB0_480:                              ; %.preheader9.i
                                        ;   in Loop: Header=BB0_481 Depth=5
	s_sleep 63
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_481:                              ; %Flow1257
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x326
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB0_480
; %bb.482:                              ; %Flow1254
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_485
.LBB0_483:                              ; %.preheader7.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 31
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_483
	s_branch .LBB0_485
.LBB0_484:                              ; %.preheader5.i
                                        ;   in Loop: Header=BB0_485 Depth=5
	s_sleep 15
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_485:                              ; %.loopexit8.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0xc0
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB0_484
	s_branch .LBB0_487
.LBB0_486:                              ; %.preheader3.i
                                        ;   in Loop: Header=BB0_487 Depth=5
	s_sleep 7
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_487:                              ; %Flow1248
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x59
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB0_486
	s_branch .LBB0_489
.LBB0_488:                              ; %.preheader1.i
                                        ;   in Loop: Header=BB0_489 Depth=5
	s_sleep 3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_489:                              ; %Flow1245
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 38
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB0_488
; %bb.490:                              ; %Flow1242
                                        ;   in Loop: Header=BB0_378 Depth=4
	v_cmp_le_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_492
.LBB0_491:                              ; %.preheader.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_491
.LBB0_492:                              ; %__ockl_rtcwait_u32.exit
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s17
	s_cmp_lg_u32 s16, 2
	v_mov_b32_e32 v31, s4
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v30, 0, 1, s2
.LBB0_493:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s18, 0
.LBB0_494:                              ; %Flow1309
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_502
; %bb.495:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_499
; %bb.496:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b64 v[23:24], v[52:53], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v23
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[3:4]
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB0_498
; %bb.497:                              ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v21, s2 :: v_dual_mov_b32 v22, s3
	global_atomic_cmpswap_b64 v[3:4], v[52:53], v[21:24], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[23:24]
	v_mov_b32_e32 v4, s4
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
.LBB0_498:                              ; %Flow1236
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_499:                              ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s5
	v_readfirstlane_b32 s2, v3
	v_readfirstlane_b32 s3, v4
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u64 s[2:3], 0
	s_cbranch_scc0 .LBB0_503
; %bb.500:                              ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v16, s3 :: v_dual_mov_b32 v15, s2
.LBB0_501:                              ; %Flow1235
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v31, v16 :: v_dual_mov_b32 v30, v15
.LBB0_502:                              ; %Flow1312
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_xor_b32 s1, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_378
	s_branch .LBB0_618
.LBB0_503:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v15 :: v_dual_mov_b32 v4, v16
	s_and_saveexec_b32 s18, s1
	s_cbranch_execz .LBB0_539
; %bb.504:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x1
	global_load_b64 v[3:4], v5, s[12:13] glc
	global_load_b64 v[11:12], v5, s[14:15]
	s_waitcnt vmcnt(0)
	v_cmp_ge_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_cbranch_vccnz .LBB0_508
; %bb.505:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s2, exec_lo
	s_mov_b32 s1, exec_lo
	v_mbcnt_lo_u32_b32 v6, s2, 0
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_507
; %bb.506:                              ;   in Loop: Header=BB0_378 Depth=4
	s_bcnt1_i32_b32 s2, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s2, s2, 21
	v_mov_b32_e32 v4, s2
	global_atomic_add_u64 v[3:4], v5, v[4:5], s[12:13] glc
.LBB0_507:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s3, v4
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x200000, v6, s[2:3]
	v_cmp_ge_u64_e64 s1, v[3:4], v[11:12]
	s_branch .LBB0_509
.LBB0_508:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr3_vgpr4
.LBB0_509:                              ; %Flow1233
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s19, s1
	s_cbranch_execz .LBB0_538
; %bb.510:                              ;   in Loop: Header=BB0_378 Depth=4
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s1, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s1, s1, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_516
; %bb.511:                              ;   in Loop: Header=BB0_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[2:3] offset:40
	global_load_b64 v[18:19], v5, s[2:3]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v18, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB0_515
; %bb.512:                              ; %.preheader3.i.i.i89.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s7, 0
.LBB0_513:                              ; %.preheader3.i.i.i89
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[2:3] offset:40
	global_load_b64 v[21:22], v5, s[2:3]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v18, v23
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v12 :: v_dual_and_b32 v6, v19, v24
	v_mad_u64_u32 v[18:19], null, v6, 24, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v12, v18
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_513
; %bb.514:                              ; %Flow1229
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_515:                              ; %Flow1231
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_516:                              ; %.loopexit4.i.i.i84
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[2:3] offset:40
	global_load_b128 v[22:25], v5, s[2:3]
	v_readfirstlane_b32 s16, v11
	v_readfirstlane_b32 s17, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v18
	v_readfirstlane_b32 s7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[16:17], s[6:7]
	s_mul_i32 s20, s7, 24
	s_mul_hi_u32 s21, s6, 24
	s_mul_i32 s35, s6, 24
	s_and_saveexec_b32 s36, s1
	s_cbranch_execz .LBB0_518
; %bb.517:                              ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s21, s20
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v22, s35
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v23, vcc_lo
	global_store_b128 v[18:19], v[11:14], off offset:8
.LBB0_518:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s36
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v24, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v25, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v27, s7
	v_dual_mov_b32 v19, v5 :: v_dual_mov_b32 v26, s6
	v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v24, s4
	v_mov_b32_e32 v25, s5
	s_clause 0x3
	global_store_b128 v[11:12], v[18:21], off
	global_store_b128 v[11:12], v[24:27], off offset:16
	global_store_b128 v[11:12], v[24:27], off offset:32
	global_store_b128 v[11:12], v[24:27], off offset:48
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_526
; %bb.519:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v5, s[2:3] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v80, s16 :: v_dual_mov_b32 v81, s17
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s17, v4
	v_and_b32_e32 v3, s16, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v22, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v23, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[26:27], v5, v[80:83], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[26:27], v[82:83]
	s_cbranch_execz .LBB0_522
; %bb.520:                              ; %.preheader1.i.i.i87.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s7, 0
.LBB0_521:                              ; %.preheader1.i.i.i87
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v24, s16 :: v_dual_mov_b32 v25, s17
	s_sleep 1
	global_store_b64 v[3:4], v[26:27], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[24:27], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[26:27]
	v_dual_mov_b32 v27, v19 :: v_dual_mov_b32 v26, v18
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_521
.LBB0_522:                              ; %Flow1227
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[18:19], v5, s[2:3] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_524
; %bb.523:                              ;   in Loop: Header=BB0_378 Depth=4
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[18:19], v[4:5], off offset:8
.LBB0_524:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[24:25], v[18:19], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[24:25]
	s_cbranch_vccnz .LBB0_526
; %bb.525:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v4, v[18:19], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[24:25], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_526:                              ; %Flow1228
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s21, s21, s20
	v_add_co_u32 v3, vcc_lo, v22, s35
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_527:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_529
; %bb.528:                              ;   in Loop: Header=BB0_527 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_529:                              ;   in Loop: Header=BB0_527 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_531
; %bb.530:                              ;   in Loop: Header=BB0_527 Depth=5
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB0_532
.LBB0_531:                              ;   in Loop: Header=BB0_527 Depth=5
	s_mov_b32 s5, -1
.LBB0_532:                              ; %Flow1222
                                        ;   in Loop: Header=BB0_527 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_527
; %bb.533:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_537
; %bb.534:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[2:3] offset:40
	global_load_b64 v[18:19], v5, s[2:3] offset:24 glc
	global_load_b64 v[23:24], v5, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, v6, s16
	v_add_co_ci_u32_e32 v22, vcc_lo, s17, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[21:22]
	v_dual_cndmask_b32 v22, v22, v25 :: v_dual_cndmask_b32 v21, v21, v6
	v_and_b32_e32 v6, v22, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v21, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v23, v11
	v_mov_b32_e32 v23, v18
	v_add_co_ci_u32_e32 v12, vcc_lo, v24, v6, vcc_lo
	v_mov_b32_e32 v24, v19
	global_store_b64 v[11:12], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[18:19]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_537
; %bb.535:                              ; %.preheader.i.i.i86.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s1, 0
.LBB0_536:                              ; %.preheader.i.i.i86
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[11:12], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[23:24]
	v_dual_mov_b32 v24, v19 :: v_dual_mov_b32 v23, v18
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_536
.LBB0_537:                              ; %Flow1220
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_538:                              ; %Flow1234
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s19
.LBB0_539:                              ; %__ockl_devmem_request.exit90
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s18
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v3
	v_readfirstlane_b32 s3, v4
	s_cmp_eq_u64 s[2:3], 0
	s_cbranch_scc1 .LBB0_584
; %bb.540:                              ;   in Loop: Header=BB0_378 Depth=4
	v_mbcnt_lo_u32_b32 v4, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	global_load_b32 v6, v[38:39], off
	s_bcnt1_i32_b32 s5, exec_lo
	s_add_u32 s6, s2, 16
	s_addc_u32 s7, s3, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v3, 5, v3
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s16, exec_lo, s1
	s_cbranch_execz .LBB0_548
; %bb.541:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v15, v[54:55], off
	s_mov_b32 s17, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB0_544
; %bb.542:                              ; %.preheader182.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s18, s5, 2
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB0_543:                              ; %.preheader182
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_add_nc_u32_e32 v16, s5, v16
	global_store_b32 v[11:12], v5, off
	v_add_co_u32 v11, s1, v11, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s1, 0, v12, s1
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB0_543
.LBB0_544:                              ; %Flow1209
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b32 v16, v[64:65], off
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v15, v4, v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v11, v6
	s_cbranch_execz .LBB0_547
; %bb.545:                              ; %.preheader180.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	v_mul_lo_u32 v12, v15, s5
	s_mov_b32 s17, 0
.LBB0_546:                              ; %.preheader180
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_lshlrev_b32_e64 v15, v11, 1
	v_lshrrev_b32_e32 v16, 3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v11, v12
	v_and_b32_e32 v16, 0x1ffffffc, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v11, v6
	global_store_b32 v16, v15, s[6:7]
	s_or_b32 s17, vcc_lo, s17
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_546
.LBB0_547:                              ; %Flow1206
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_548:                              ; %Flow1214
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_and_not1_saveexec_b32 s16, s16
	s_cbranch_execz .LBB0_553
; %bb.549:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s17, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB0_552
; %bb.550:                              ; %.preheader178.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v15, v[66:67], off
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s18, s5, 2
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB0_551:                              ; %.preheader178
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_add_nc_u32_e32 v16, s5, v16
	s_waitcnt vmcnt(0)
	global_store_b32 v[11:12], v15, off
	v_add_co_u32 v11, s1, v11, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s1, 0, v12, s1
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB0_551
.LBB0_552:                              ; %Flow1212
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s17
.LBB0_553:                              ; %.loopexit179
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_557
; %bb.554:                              ;   in Loop: Header=BB0_378 Depth=4
	v_and_b32_e32 v6, 31, v6
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v6
	s_cbranch_execz .LBB0_556
; %bb.555:                              ;   in Loop: Header=BB0_378 Depth=4
	v_add_nc_u32_e32 v4, -1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v11, v[3:4], off
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v6, -1, v6, v11
	global_store_b32 v[3:4], v6, off
.LBB0_556:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_store_b128 v5, v[7:10], s[2:3]
.LBB0_557:                              ; %Flow1203
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $sgpr5
.LBB0_558:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e64 s1, 0, v71
	v_mov_b32_e32 v3, s31
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB0_560
; %bb.559:                              ;   in Loop: Header=BB0_558 Depth=5
	global_load_b32 v3, v[32:33], off glc
.LBB0_560:                              ;   in Loop: Header=BB0_558 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s31, v3
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s6, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s5, s6
	s_cmp_eq_u32 s31, 0x10100
	s_cbranch_scc1 .LBB0_567
; %bb.561:                              ;   in Loop: Header=BB0_558 Depth=5
	v_mov_b32_e32 v3, s34
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB0_563
; %bb.562:                              ;   in Loop: Header=BB0_558 Depth=5
	global_load_b32 v3, v[48:49], off glc
.LBB0_563:                              ;   in Loop: Header=BB0_558 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s34, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u32 s31, s34
	s_cbranch_scc0 .LBB0_568
; %bb.564:                              ;   in Loop: Header=BB0_558 Depth=5
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB0_575
; %bb.565:                              ;   in Loop: Header=BB0_558 Depth=5
	s_cmpk_lt_u32 s31, 0x100
	s_cbranch_scc0 .LBB0_569
; %bb.566:                              ;   in Loop: Header=BB0_558 Depth=5
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_mov_b32 s7, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s31, 24, v[3:4]
	s_branch .LBB0_570
.LBB0_567:                              ;   in Loop: Header=BB0_558 Depth=5
	s_mov_b64 s[16:17], 0
	s_mov_b32 s1, -1
	s_mov_b32 s18, 0
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr31
                                        ; implicit-def: $sgpr34
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB0_580
.LBB0_568:                              ;   in Loop: Header=BB0_558 Depth=5
	s_mov_b32 s18, -1
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr31
                                        ; implicit-def: $sgpr34
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB0_579
.LBB0_569:                              ;   in Loop: Header=BB0_558 Depth=5
	s_mov_b32 s7, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_570:                              ; %Flow1195
                                        ;   in Loop: Header=BB0_558 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_572
; %bb.571:                              ;   in Loop: Header=BB0_558 Depth=5
	s_add_i32 s7, s31, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s7, s7, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s7, 24, v[3:4]
	s_and_b32 s7, s31, 0xff
	global_load_b64 v[3:4], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, s7, 24, v[3:4]
.LBB0_572:                              ;   in Loop: Header=BB0_558 Depth=5
	v_dual_mov_b32 v15, s31 :: v_dual_mov_b32 v4, s3
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v6, v5
	global_store_b32 v5, v15, s[2:3] offset:4
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off offset:8 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB0_574
; %bb.573:                              ;   in Loop: Header=BB0_558 Depth=5
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[32:33], v118, off
	v_dual_mov_b32 v3, v11 :: v_dual_mov_b32 v4, v12
.LBB0_574:                              ; %Flow1193
                                        ;   in Loop: Header=BB0_558 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_575:                              ; %Flow1196
                                        ;   in Loop: Header=BB0_558 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s7, v4
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_577
; %bb.576:                              ;   in Loop: Header=BB0_558 Depth=5
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr31
                                        ; implicit-def: $sgpr34
	s_branch .LBB0_578
.LBB0_577:                              ;   in Loop: Header=BB0_558 Depth=5
	s_mov_b32 s19, 0
	s_and_not1_b32 s1, s1, exec_lo
	s_sleep 2
.LBB0_578:                              ; %Flow1201
                                        ;   in Loop: Header=BB0_558 Depth=5
	s_mov_b32 s18, 0
.LBB0_579:                              ; %Flow1200
                                        ;   in Loop: Header=BB0_558 Depth=5
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s16, s1, exec_lo
	s_mov_b32 s1, 0
	s_or_b32 s5, s5, s16
                                        ; implicit-def: $sgpr16_sgpr17
.LBB0_580:                              ; %Flow1199
                                        ;   in Loop: Header=BB0_558 Depth=5
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB0_558
; %bb.581:                              ; %loop.exit.guard930
                                        ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v16, s17
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_501
; %bb.582:                              ; %loop.exit.guard931
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_xor_b32 s1, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_585
; %bb.583:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s18, 0
	s_branch .LBB0_586
.LBB0_584:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s18, 0
	s_branch .LBB0_501
.LBB0_585:                              ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr6_sgpr7
.LBB0_586:                              ; %Flow1190
                                        ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v15, s6
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_501
; %bb.587:                              ;   in Loop: Header=BB0_378 Depth=4
	s_and_saveexec_b32 s20, s5
	s_cbranch_execz .LBB0_616
; %bb.588:                              ;   in Loop: Header=BB0_378 Depth=4
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s1, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s1, s1, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_594
; %bb.589:                              ;   in Loop: Header=BB0_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB0_593
; %bb.590:                              ; %.preheader3.i.i.i96.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s7, 0
.LBB0_591:                              ; %.preheader3.i.i.i96
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v23
	v_and_b32_e32 v6, v16, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_591
; %bb.592:                              ; %Flow1186
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_593:                              ; %Flow1188
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_594:                              ; %.loopexit4.i.i.i91
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[21:24], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s21, s7, 24
	s_mul_hi_u32 s31, s6, 24
	s_mul_i32 s34, s6, 24
	s_and_saveexec_b32 s35, s1
	s_cbranch_execz .LBB0_596
; %bb.595:                              ;   in Loop: Header=BB0_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s31, s21
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v21, s34
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB0_596:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s35
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v12, s3 :: v_dual_mov_b32 v11, s2
	v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v24, s5 :: v_dual_mov_b32 v23, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[23:26], off offset:8
	global_store_b128 v[3:4], v[23:26], off offset:24
	global_store_b128 v[3:4], v[23:26], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_604
; %bb.597:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s3, exec_lo
	v_dual_mov_b32 v80, s18 :: v_dual_mov_b32 v81, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v21, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v22, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v5, v[80:83], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[82:83]
	s_cbranch_execz .LBB0_600
; %bb.598:                              ; %.preheader1.i.i.i94.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s5, 0
.LBB0_599:                              ; %.preheader1.i.i.i94
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v23, s18 :: v_dual_mov_b32 v24, s19
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[23:26], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_599
.LBB0_600:                              ; %Flow1184
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b64 v[11:12], v5, s[16:17] offset:16
	s_mov_b32 s5, exec_lo
	s_mov_b32 s3, exec_lo
	v_mbcnt_lo_u32_b32 v3, s5, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_602
; %bb.601:                              ;   in Loop: Header=BB0_378 Depth=4
	s_bcnt1_i32_b32 s5, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s5
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB0_602:                              ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB0_604
; %bb.603:                              ;   in Loop: Header=BB0_378 Depth=4
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s3, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s3, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_604:                              ; %Flow1185
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s31, s31, s21
	v_add_co_u32 v3, vcc_lo, v21, s34
	v_add_co_ci_u32_e32 v4, vcc_lo, s31, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_605:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_607
; %bb.606:                              ;   in Loop: Header=BB0_605 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_607:                              ;   in Loop: Header=BB0_605 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v6
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB0_609
; %bb.608:                              ;   in Loop: Header=BB0_605 Depth=5
	s_mov_b32 s2, 0
	s_sleep 1
	s_branch .LBB0_610
.LBB0_609:                              ;   in Loop: Header=BB0_605 Depth=5
	s_mov_b32 s2, -1
.LBB0_610:                              ; %Flow1179
                                        ;   in Loop: Header=BB0_605 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_605
; %bb.611:                              ;   in Loop: Header=BB0_378 Depth=4
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_615
; %bb.612:                              ;   in Loop: Header=BB0_378 Depth=4
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	global_load_b64 v[11:12], v5, s[16:17] offset:24 glc
	global_load_b64 v[15:16], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v23, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v19, vcc_lo, s19, v21, vcc_lo
	v_mov_b32_e32 v24, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v22, v19, v21 :: v_dual_cndmask_b32 v21, v18, v6
	v_and_b32_e32 v4, v22, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v21, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_615
; %bb.613:                              ; %.preheader.i.i.i93.preheader
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_mov_b32 s1, 0
.LBB0_614:                              ; %.preheader.i.i.i93
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ;         Parent Loop BB0_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[3:4], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_614
.LBB0_615:                              ; %Flow1177
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v71, 0
.LBB0_616:                              ; %Flow1189
                                        ;   in Loop: Header=BB0_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s20
	v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v31
	s_mov_b32 s18, -1
	s_branch .LBB0_501
.LBB0_617:                              ;   in Loop: Header=BB0_347 Depth=3
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $sgpr29
                                        ; implicit-def: $vgpr70
	s_branch .LBB0_641
.LBB0_618:                              ;   in Loop: Header=BB0_347 Depth=3
	v_cmp_ne_u64_e64 s5, 1, v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_620
; %bb.619:                              ;   in Loop: Header=BB0_347 Depth=3
	v_dual_mov_b32 v28, v30 :: v_dual_mov_b32 v29, v31
	s_branch .LBB0_640
.LBB0_620:                              ;   in Loop: Header=BB0_347 Depth=3
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_637
; %bb.621:                              ;   in Loop: Header=BB0_347 Depth=3
	global_load_b64 v[3:4], v[52:53], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_637
; %bb.622:                              ;   in Loop: Header=BB0_347 Depth=3
	v_sub_nc_u32_e32 v3, 0x4e20, v3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
.LBB0_623:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x659
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_626
; %bb.624:                              ; %.preheader11.i110
                                        ;   in Loop: Header=BB0_623 Depth=4
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB0_623
.LBB0_625:                              ; %.preheader9.i109
                                        ;   in Loop: Header=BB0_626 Depth=4
	s_sleep 63
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_626:                              ; %Flow1171
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x326
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB0_625
; %bb.627:                              ; %Flow1168
                                        ;   in Loop: Header=BB0_347 Depth=3
	s_add_u32 s16, s6, 0x18c
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_630
.LBB0_628:                              ; %.preheader7.i108
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 31
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x18c
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_628
	s_branch .LBB0_630
.LBB0_629:                              ; %.preheader5.i107
                                        ;   in Loop: Header=BB0_630 Depth=4
	s_sleep 15
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_630:                              ; %.loopexit8.i100
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0xc0
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB0_629
	s_branch .LBB0_632
.LBB0_631:                              ; %.preheader3.i106
                                        ;   in Loop: Header=BB0_632 Depth=4
	s_sleep 7
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_632:                              ; %Flow1162
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x59
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB0_631
	s_branch .LBB0_634
.LBB0_633:                              ; %.preheader1.i105
                                        ;   in Loop: Header=BB0_634 Depth=4
	s_sleep 3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB0_634:                              ; %Flow1159
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 38
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB0_633
; %bb.635:                              ; %Flow1156
                                        ;   in Loop: Header=BB0_347 Depth=3
	v_cmp_le_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_637
.LBB0_636:                              ; %.preheader.i104
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ;       Parent Loop BB0_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_636
.LBB0_637:                              ; %__ockl_rtcwait_u32.exit111
                                        ;   in Loop: Header=BB0_347 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, s29
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v70
	s_cbranch_execz .LBB0_639
; %bb.638:                              ;   in Loop: Header=BB0_347 Depth=3
	global_load_b32 v3, v[32:33], off glc
.LBB0_639:                              ;   in Loop: Header=BB0_347 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s29, v3
.LBB0_640:                              ; %Flow1173
                                        ;   in Loop: Header=BB0_347 Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v11, v28 :: v_dual_mov_b32 v12, v29
.LBB0_641:                              ; %Flow1318
                                        ;   in Loop: Header=BB0_347 Depth=3
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_347
.LBB0_642:                              ; %.loopexit189
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_cmp_eq_u64 s[6:7], 0
	s_cbranch_scc1 .LBB0_663
; %bb.643:                              ;   in Loop: Header=BB0_6 Depth=2
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mbcnt_lo_u32_b32 v3, s5, 0
	;;#ASMSTART
	;;#ASMEND
	global_load_b64 v[0:1], v5, s[6:7] offset:8 glc
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_waitcnt vmcnt(0)
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_647
; %bb.644:                              ;   in Loop: Header=BB0_6 Depth=2
	s_mov_b32 s17, exec_lo
	s_bcnt1_i32_b32 s5, s5
	v_mbcnt_lo_u32_b32 v4, s17, 0
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_646
; %bb.645:                              ;   in Loop: Header=BB0_6 Depth=2
	s_bcnt1_i32_b32 s1, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s5, s1
	v_mov_b32_e32 v6, s1
	global_atomic_add_u32 v6, v[0:1], v6, off offset:8 glc
.LBB0_646:                              ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v4, s5, v4, s1
.LBB0_647:                              ; %Flow944
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, s4
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, __unnamed_1@rel32@lo+4
	s_addc_u32 s19, s19, __unnamed_1@rel32@hi+12
	s_lshl_b64 s[16:17], s[2:3], 5
	v_mov_b32_e32 v11, 0
	s_add_u32 s18, s16, s18
	s_addc_u32 s19, s17, s19
	v_readfirstlane_b32 s1, v4
	s_load_b32 s5, s[18:19], 0x0
	v_mov_b32_e32 v12, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s3, 32
	s_cbranch_scc1 .LBB0_657
; %bb.648:                              ;   in Loop: Header=BB0_6 Depth=2
	v_cvt_f32_u32_e32 v4, s5
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, __unnamed_1@rel32@lo+32
	s_addc_u32 s19, s19, __unnamed_1@rel32@hi+40
	s_lshr_b32 s3, s3, 5
	s_add_u32 s18, s16, s18
	s_addc_u32 s19, s17, s19
	v_rcp_iflag_f32_e32 v4, v4
	s_load_b32 s18, s[18:19], 0x0
	s_sub_i32 s19, 0, s5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v4, 0x4f7ffffe, v4 :: v_dual_add_nc_u32 v3, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v6, s19, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v3, s18, v3
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, __unnamed_1@rel32@lo+16
	s_addc_u32 s19, s19, __unnamed_1@rel32@hi+24
	s_add_u32 s16, s16, s18
	s_addc_u32 s17, s17, s19
	s_lshr_b32 s18, s2, 1
	s_add_i32 s19, s3, -1
	s_add_i32 s18, s18, 4
	v_mul_hi_u32 v6, v4, v6
	s_lshl_b32 s18, 1, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v6
	v_cvt_f32_u32_e32 v6, s3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v6, v6
	v_mul_lo_u32 v4, v4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v3, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v6
	v_subrev_nc_u32_e32 v6, s5, v3
	v_cmp_le_u32_e64 s1, s5, v3
	v_cvt_u32_f32_e32 v15, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v3, v6, s1
	s_sub_i32 s1, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v11, s1, v15
	v_add_co_u32 v3, s1, v0, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, 0, v1, s1
	v_subrev_nc_u32_e32 v12, s5, v4
	v_cmp_le_u32_e64 s1, s5, v4
	s_mov_b32 s5, 0
	v_mul_hi_u32 v16, v15, v11
	v_cndmask_b32_e64 v4, v4, v12, s1
	v_mov_b32_e32 v11, 0
	s_bfe_i32 s1, s2, 0x10000
	s_lshr_b32 s2, s18, 1
	v_mov_b32_e32 v12, 0
	v_lshrrev_b32_e32 v4, 5, v4
	v_add_nc_u32_e32 v18, v15, v16
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s18, s1, s18
.LBB0_649:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 2, v[4:5]
	s_mov_b32 s2, -1
	s_mov_b32 s20, exec_lo
                                        ; implicit-def: $vgpr19
	v_add_co_u32 v15, s1, v3, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s1, v6, v16, s1
	global_load_b32 v21, v[15:16], off glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v21
	s_cbranch_execz .LBB0_653
; %bb.650:                              ;   in Loop: Header=BB0_649 Depth=3
	v_not_b32_e32 v19, v21
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ctz_i32_b32_e32 v19, v19
	v_min_u32_e32 v21, 32, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e64 v19, v21, 1
	global_atomic_or_b32 v15, v[15:16], v19, off glc
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, v15, v19
	v_mov_b32_e32 v19, 0
	v_cmp_ne_u32_e64 s1, 0, v15
	v_cmpx_eq_u32_e32 0, v15
	s_cbranch_execz .LBB0_652
; %bb.651:                              ;   in Loop: Header=BB0_649 Depth=3
	s_load_b32 s2, s[16:17], 0x0
	v_lshl_add_u32 v11, v4, 5, v21
	v_mov_b32_e32 v19, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v11, s18
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v12, s2, v0, s2
	v_add_co_ci_u32_e64 v15, s2, 0, v1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s2, v12, v11
	v_add_co_ci_u32_e64 v12, s2, 0, v15, s2
.LBB0_652:                              ;   in Loop: Header=BB0_649 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_not1_b32 s2, s1, exec_lo
.LBB0_653:                              ; %Flow941
                                        ;   in Loop: Header=BB0_649 Depth=3
	s_or_b32 exec_lo, exec_lo, s20
	s_and_saveexec_b32 s20, s2
; %bb.654:                              ;   in Loop: Header=BB0_649 Depth=3
	v_dual_mov_b32 v19, 0 :: v_dual_add_nc_u32 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v15, v4, v18
	v_mul_lo_u32 v15, v15, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v15
	v_subrev_nc_u32_e32 v15, s3, v4
	v_cmp_le_u32_e64 s1, s3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v15, s1
	v_subrev_nc_u32_e32 v15, s3, v4
	v_cmp_le_u32_e64 s1, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v15, s1
; %bb.655:                              ;   in Loop: Header=BB0_649 Depth=3
	s_or_b32 exec_lo, exec_lo, s20
	v_cmp_ne_u32_e64 s1, 0, v19
	s_cmp_eq_u32 s19, 0
	s_cselect_b32 s2, -1, 0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_and_b32 s1, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s5, s1, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_649
; %bb.656:                              ; %Flow942
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_657:                              ; %.loopexit193
                                        ;   in Loop: Header=BB0_6 Depth=2
	v_cmp_ne_u64_e64 s1, 0, v[11:12]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_660
; %bb.658:                              ;   in Loop: Header=BB0_6 Depth=2
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s3, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s5, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s5
	s_cbranch_execz .LBB0_660
; %bb.659:                              ;   in Loop: Header=BB0_6 Depth=2
	s_bcnt1_i32_b32 s1, s1
	s_bcnt1_i32_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s3
	v_mov_b32_e32 v0, s1
	global_atomic_add_u32 v5, v0, s[6:7] offset:16
.LBB0_660:                              ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u64_e32 0, v[11:12]
; %bb.661:                              ;   in Loop: Header=BB0_6 Depth=2
	v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v119, 0
	v_dual_mov_b32 v128, 0 :: v_dual_mov_b32 v1, v12
; %bb.662:                              ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v128 :: v_dual_mov_b32 v4, v119
.LBB0_663:                              ; %Flow945
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v119, v4
.LBB0_664:                              ; %Flow1324
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v3
	;;#ASMSTART
	;;#ASMEND
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB0_6
.LBB0_665:                              ; %Flow1326
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	v_mov_b32_e32 v3, v119
.LBB0_666:                              ; %.loopexit197
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v3
	;;#ASMSTART
	;;#ASMEND
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB0_3
; %bb.667:                              ; %Flow1328
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_668:                              ; %Flow1347
	s_and_not1_saveexec_b32 s1, s23
	s_cbranch_execz .LBB0_701
; %bb.669:
	s_load_b64 s[2:3], s[8:9], 0x50
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v2
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_675
; %bb.670:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v8
	v_and_b32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[8:9]
	s_cbranch_execz .LBB0_674
; %bb.671:                              ; %.preheader3.i.i.i.preheader
	s_mov_b32 s6, 0
.LBB0_672:                              ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[10:11]
	v_and_b32_e32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v10, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_672
; %bb.673:                              ; %Flow1343
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_674:                              ; %Flow1345
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_675:                              ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s13, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[6:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s10, s7, 24
	s_mul_hi_u32 s11, s6, 24
	s_mul_i32 s12, s6, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_677
; %bb.676:
	v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, v3
	s_add_i32 s13, s11, s10
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v7, vcc_lo
	v_dual_mov_b32 v12, 3 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB0_677:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v8, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v1, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
	v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s18
	s_clause 0x3
	global_store_b128 v[8:9], v[2:5], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_685
; %bb.678:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v4, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v1, vcc_lo
	global_store_b64 v[4:5], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_681
; %bb.679:                              ; %.preheader1.i.i.i.preheader
	s_mov_b32 s13, 0
.LBB0_680:                              ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_680
.LBB0_681:                              ; %Flow1341
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s13, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_683
; %bb.682:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_683:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_685
; %bb.684:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_685:                              ; %Flow1342
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s11, s11, s10
	v_add_co_u32 v0, vcc_lo, v6, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_686:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_688
; %bb.687:                              ;   in Loop: Header=BB0_686 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_688:                              ;   in Loop: Header=BB0_686 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB0_690
; %bb.689:                              ;   in Loop: Header=BB0_686 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB0_691
.LBB0_690:                              ;   in Loop: Header=BB0_686 Depth=1
	s_mov_b32 s6, -1
.LBB0_691:                              ; %Flow1336
                                        ;   in Loop: Header=BB0_686 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_686
; %bb.692:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_696
; %bb.693:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_696
; %bb.694:                              ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_695:                              ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_695
.LBB0_696:                              ; %__ockl_devmem_request.exit
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e32 0, v[0:1]
	s_cbranch_execz .LBB0_700
; %bb.697:
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v2, s2, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s3, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s3
	s_cbranch_execz .LBB0_700
; %bb.698:
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v2, s3, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s4, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s4
	s_cbranch_execz .LBB0_700
; %bb.699:
	s_load_b64 s[4:5], s[8:9], 0x60
	s_bcnt1_i32_b32 s2, s2
	s_bcnt1_i32_b32 s3, s3
	v_mov_b32_e32 v4, 0x1a000
	s_mul_i32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s2
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u64 v4, v[2:3], s[4:5] offset:2184
.LBB0_700:
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_701:                              ; %Flow1348
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_702:                              ; %.loopexit198
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	v_readlane_b32 s30, v40, 11
	v_readlane_b32 s31, v40, 12
	v_readlane_b32 s44, v40, 10
	v_readlane_b32 s43, v40, 9
	v_readlane_b32 s42, v40, 8
	v_readlane_b32 s41, v40, 7
	v_readlane_b32 s40, v40, 6
	v_readlane_b32 s39, v40, 5
	v_readlane_b32 s38, v40, 4
	v_readlane_b32 s37, v40, 3
	v_readlane_b32 s36, v40, 2
	v_readlane_b32 s35, v40, 1
	v_readlane_b32 s34, v40, 0
	s_or_saveexec_b32 s0, -1
	scratch_load_b32 v40, off, s32          ; 4-byte Folded Reload
	s_mov_b32 exec_lo, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_dm_alloc, .Lfunc_end0-__ockl_dm_alloc
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 24288
; NumSgprs: 47
; NumVgprs: 136
; ScratchSize: 8
; MemoryBound: 1
	.section	.text.unlikely.,"ax",@progbits
	.p2align	2                               ; -- Begin function __ockl_dm_dealloc
	.type	__ockl_dm_dealloc,@function
__ockl_dm_dealloc:                      ; @__ockl_dm_dealloc
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0xfff, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u64_e32 0, v[2:3]
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB1_12
; %bb.1:
	v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v4, 0xffe00000, v0
	s_load_b64 s[0:1], s[8:9], 0x60
	v_and_b32_e32 v15, 0x1fffff, v0
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, 0x2800
	s_addc_u32 s1, s1, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+16
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+24
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v1, 1, v6
	v_bfe_i32 v2, v6, 0, 1
	v_and_b32_e32 v16, 0xff, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, 4, v1
	v_lshlrev_b32_e64 v1, v1, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v8, 1, v1
	v_and_b32_e32 v2, v2, v8
	v_add_nc_u32_e32 v8, 0xffffff00, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v14, v2, v1
	v_mov_b32_e32 v2, v6
	v_lshrrev_b32_e32 v18, 8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_u32_e32 v1, v14
	v_sub_nc_u32_e32 v0, 0, v14
	v_lshlrev_b64 v[12:13], 5, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_add_co_u32 v12, vcc_lo, v12, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, v0, v17
	v_mad_u64_u32 v[0:1], null, 0x1800, v6, s[0:1]
	v_cmp_gt_u32_e64 s0, 0x100, v7
	v_mul_hi_u32 v2, v17, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v7, 24, v[0:1]
	v_mad_u64_u32 v[10:11], null, v18, 24, v[0:1]
	v_dual_mov_b32 v17, 1 :: v_dual_add_nc_u32 v2, v17, v2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v0, v17
	v_cmp_ne_u32_e32 vcc_lo, 0, v17
	v_mov_b32_e32 v17, 0
	;;#ASMSTART
	;;#ASMEND
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_11
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_readfirstlane_b32 s1, v6
	v_readfirstlane_b32 s2, v7
	v_mov_b32_e32 v17, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, s1, v6
	v_cmp_eq_u32_e64 s1, s2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB1_10
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s7, 0
	v_cmp_ne_u32_e64 s1, 0, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v1, v9, 0, s1
	v_cndmask_b32_e64 v0, v8, 0, s1
	s_or_b32 s1, s1, s0
	s_xor_b32 s2, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	global_load_b64 v[17:18], v[10:11], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v16, 24, v[17:18]
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b32 v17, v[12:13], off
	v_readfirstlane_b32 s2, v0
	v_readfirstlane_b32 s3, v1
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v17, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v18, v17, v2
	v_mul_lo_u32 v19, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, v17, v19
	v_add_nc_u32_e32 v19, 1, v18
	v_sub_nc_u32_e32 v20, v17, v14
	v_cmp_ge_u32_e64 s1, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v19, s1
	v_cndmask_b32_e64 v17, v17, v20, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, 1, v18
	v_cmp_ge_u32_e64 s1, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, v18, v19, s1
	v_lshrrev_b32_e32 v18, 3, v17
	v_lshlrev_b32_e64 v17, v17, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, 0x1ffffffc, v18
	v_not_b32_e32 v19, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s1, v4, v18
	v_add_co_ci_u32_e64 v18, s1, 0, v5, s1
	global_atomic_and_b32 v[17:18], v19, off offset:16
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB1_9
; %bb.7:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s10, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s11, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s11
	s_cbranch_execz .LBB1_9
; %bb.8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s10
	v_mov_b32_e32 v0, s7
	global_atomic_sub_u32 v3, v0, s[2:3] offset:16
.LBB1_9:                                ; %Flow16
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v17, 0
.LBB1_10:                               ; %Flow18
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_11:                               ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v0, v17
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0_vgpr1
	s_cbranch_vccnz .LBB1_2
.LBB1_12:                               ; %Flow40
	s_and_not1_saveexec_b32 s1, s4
	s_cbranch_execz .LBB1_45
; %bb.13:
	s_mov_b32 s10, exec_lo
	v_cmpx_ne_u64_e32 0, v[0:1]
	s_cbranch_execz .LBB1_44
; %bb.14:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_20
; %bb.15:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB1_19
; %bb.16:                               ; %.preheader3.i.i.i.preheader
	s_mov_b32 s6, 0
.LBB1_17:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_17
; %bb.18:                               ; %Flow34
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_19:                               ; %Flow36
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_20:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s14, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s11, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s13, s6, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB1_22
; %bb.21:
	v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, v3
	s_add_i32 s14, s12, s11
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v13, vcc_lo, s14, v5, vcc_lo
	v_dual_mov_b32 v10, 3 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB1_22:
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v2, v8
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v9, s19
	v_dual_mov_b32 v7, s17 :: v_dual_mov_b32 v8, s18
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_30
; %bb.23:
	v_mov_b32_e32 v8, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	v_dual_mov_b32 v9, s4 :: v_dual_mov_b32 v10, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v6, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB1_26
; %bb.24:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s14, 0
.LBB1_25:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB1_25
.LBB1_26:                               ; %Flow32
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s14, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s14, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_28
; %bb.27:
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_28:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_30
; %bb.29:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_30:                               ; %Flow33
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s12, s12, s11
	v_add_co_u32 v0, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_31:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_33
; %bb.32:                               ;   in Loop: Header=BB1_31 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_33:                               ;   in Loop: Header=BB1_31 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB1_35
; %bb.34:                               ;   in Loop: Header=BB1_31 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB1_36
.LBB1_35:                               ;   in Loop: Header=BB1_31 Depth=1
	s_mov_b32 s6, -1
.LBB1_36:                               ; %Flow27
                                        ;   in Loop: Header=BB1_31 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB1_31
; %bb.37:
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB1_41
; %bb.38:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_41
; %bb.39:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB1_40:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_40
.LBB1_41:                               ; %__ockl_devmem_request.exit
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_mbcnt_lo_u32_b32 v0, s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s2, exec_lo, vcc_lo
	s_mov_b32 exec_lo, s2
	s_cbranch_execz .LBB1_44
; %bb.42:
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s2, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s3, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s3
	s_cbranch_execz .LBB1_44
; %bb.43:
	s_load_b64 s[4:5], s[8:9], 0x60
	s_bcnt1_i32_b32 s0, s0
	s_bcnt1_i32_b32 s2, s2
	v_mov_b32_e32 v2, 0x1a000
	s_mul_i32 s0, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
	s_waitcnt lgkmcnt(0)
	global_atomic_sub_u64 v2, v[0:1], s[4:5] offset:2184
.LBB1_44:                               ; %Flow38
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_45:                               ; %.loopexit
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end1:
	.size	__ockl_dm_dealloc, .Lfunc_end1-__ockl_dm_dealloc
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2296
; NumSgprs: 34
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z9piiKernelhPhS_S_     ; -- Begin function _Z9piiKernelhPhS_S_
	.globl	_Z9piiKernelhPhS_S_
	.p2align	8
	.type	_Z9piiKernelhPhS_S_,@function
_Z9piiKernelhPhS_S_:                    ; @_Z9piiKernelhPhS_S_
; %bb.0:
	s_mov_b64 s[46:47], s[0:1]
	s_clause 0x2
	s_load_b32 s0, s[0:1], 0x0
	s_load_b128 s[48:51], s[46:47], 0x8
	s_load_b64 s[52:53], s[46:47], 0x18
	v_mov_b32_e32 v41, v0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	v_and_b32_e64 v42, 0xff, s0
	s_and_b32 s33, s0, 0xff
	s_add_u32 s8, s46, 32
	s_addc_u32 s9, s47, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_dm_alloc@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_dm_alloc@rel32@hi+12
	v_max_u16 v0, v42, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v0, 0xffff, v0
	s_swappc_b64 s[30:31], s[0:1]
	v_cmp_eq_u16_e32 vcc_lo, 0, v42
	v_cmp_ne_u16_e64 s0, 0, v42
	s_cbranch_vccnz .LBB2_3
; %bb.1:                                ; %.lr.ph
	v_mul_u32_u24_e32 v2, s33, v41
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s48, v2
	v_add_co_ci_u32_e64 v3, null, s49, 0, s1
	s_mov_b32 s1, s33
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_u8 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 0
	s_waitcnt vmcnt(0)
	global_store_b8 v[4:5], v6, off
	v_add_co_u32 v4, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_cbranch_scc0 .LBB2_2
.LBB2_3:                                ; %._crit_edge
	global_load_u8 v4, v41, s[52:53]
	s_lshl_b32 s2, s33, 2
	v_add_co_u32 v2, s3, s52, v41
	s_add_i32 s1, s2, 0
	v_cndmask_b32_e64 v6, 0, 1, s0
	v_lshl_add_u32 v8, v41, 2, 0
	v_add_co_ci_u32_e64 v3, null, s53, 0, s3
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v5, v4, 2, s1
	ds_store_b32 v8, v4
	ds_store_b32 v5, v41
	s_cbranch_vccnz .LBB2_6
; %bb.4:                                ; %.lr.ph154.preheader
	s_mul_i32 s0, s33, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v7, 0, s0, v41
	v_add_co_u32 v4, s0, s50, v41
	v_add_co_ci_u32_e64 v5, null, s51, 0, s0
	s_mov_b32 s0, s33
.LBB2_5:                                ; %.lr.ph154
                                        ; =>This Inner Loop Header: Depth=1
	global_load_u8 v9, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, s33
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	ds_store_b8 v7, v9
	v_add_nc_u32_e32 v7, s33, v7
	s_cbranch_scc0 .LBB2_5
.LBB2_6:                                ; %._crit_edge155
	v_cmp_ne_u32_e32 vcc_lo, 1, v6
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB2_33
; %bb.7:                                ; %.lr.ph166
	s_add_i32 s3, s1, s2
	v_dual_mov_b32 v13, 0 :: v_dual_lshlrev_b32 v4, 2, v41
	s_mul_i32 s0, s33, 3
	s_add_i32 s2, s3, s2
	v_mul_u32_u24_e32 v6, 3, v41
	s_add_i32 s4, s2, s0
	s_mul_i32 s0, s33, s33
	v_dual_mov_b32 v16, 1 :: v_dual_add_nc_u32 v11, s3, v4
	s_add_i32 s0, s4, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s0 :: v_dual_add_nc_u32 v9, s1, v4
	v_add_co_u32 v4, vcc_lo, v0, 1
	v_dual_mov_b32 v17, 0xff :: v_dual_add_nc_u32 v10, s4, v41
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	v_add_nc_u32_e32 v14, s2, v6
	v_bfrev_b32_e32 v15, -2
	s_mov_b32 s5, 0
.LBB2_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_10 Depth 2
                                        ;     Child Loop BB2_25 Depth 2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v18, v9
	ds_store_b8 v12, v13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_u8 v21, v[0:1], off
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v19, -1 :: v_dual_and_b32 v20, 0xff, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e64 v18, v20
	s_cbranch_execz .LBB2_16
; %bb.9:                                ; %.lr.ph159.preheader
                                        ;   in Loop: Header=BB2_8 Depth=1
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_mov_b32 s7, 0
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $sgpr10
                                        ; implicit-def: $sgpr9
.LBB2_10:                               ; %.lr.ph159
                                        ;   Parent Loop BB2_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v22, v20 :: v_dual_and_b32 v19, 0xff, v21
	s_or_b32 s9, s9, exec_lo
	s_or_b32 s10, s10, exec_lo
                                        ; implicit-def: $sgpr0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v19, v19, 2, 0
	v_mul_u32_u24_e32 v20, s33, v22
	v_mad_u32_u24 v21, v22, s33, v10
	ds_load_b32 v19, v19
	s_waitcnt lgkmcnt(0)
	v_add3_u32 v19, s4, v20, v19
	ds_load_u8 v20, v21
	ds_load_u8 v19, v19
                                        ; implicit-def: $vgpr21
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_u16_e32 vcc_lo, v20, v19
                                        ; implicit-def: $vgpr20
	s_and_saveexec_b32 s11, vcc_lo
	s_cbranch_execz .LBB2_12
; %bb.11:                               ;   in Loop: Header=BB2_10 Depth=2
	global_load_u8 v21, v[6:7], off
	v_add_co_u32 v6, s0, v6, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_and_not1_b32 s10, s10, exec_lo
	s_mov_b32 s0, -1
	s_and_not1_b32 s9, s9, exec_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xff, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, v18, v20
	s_and_b32 s12, vcc_lo, exec_lo
	s_or_b32 s10, s10, s12
.LBB2_12:                               ; %Flow230
                                        ;   in Loop: Header=BB2_10 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, exec_lo, s10
	v_mov_b32_e32 v19, s0
	s_or_b32 s7, s11, s7
	s_and_not1_b32 s0, s8, exec_lo
	s_and_b32 s8, s9, exec_lo
	s_or_b32 s8, s0, s8
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB2_10
; %bb.13:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_and_saveexec_b32 s0, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB2_15
; %bb.14:                               ;   in Loop: Header=BB2_8 Depth=1
	v_mov_b32_e32 v19, v22
	ds_store_b8 v12, v16
.LBB2_15:                               ; %Flow229
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB2_16:                               ; %Flow231
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v6, v12
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v6
	s_cbranch_vccnz .LBB2_31
; %bb.17:                               ;   in Loop: Header=BB2_8 Depth=1
	v_mov_b32_e32 v7, -1
	v_lshl_add_u32 v6, v19, 2, s3
	s_mov_b32 s0, exec_lo
	ds_store_b8 v14, v17
	ds_store_b8 v14, v17 offset:1
	ds_store_b8 v14, v17 offset:2
	ds_store_b32 v11, v15
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_ne_u32_e32 -1, v19
	s_cbranch_execz .LBB2_19
; %bb.18:                               ;   in Loop: Header=BB2_8 Depth=1
	v_mad_i32_i24 v7, v19, s33, v41
	global_load_u8 v7, v7, s[50:51]
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v7, v7, 24, v41
	ds_min_u32 v6, v7
.LBB2_19:                               ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v6, v6
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v7, v6
	v_lshl_add_u32 v6, v19, 2, 0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB2_21
; %bb.20:                               ;   in Loop: Header=BB2_8 Depth=1
	ds_load_b32 v7, v6
	s_waitcnt lgkmcnt(0)
	ds_store_b8 v14, v7
	ds_load_b32 v7, v6
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[20:21], null, v7, 3, s[2:3]
	ds_store_b8 v20, v18 offset:1
	ds_load_b32 v7, v6
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[20:21], null, v7, 3, s[2:3]
	ds_store_b8 v20, v41 offset:2
.LBB2_21:                               ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB2_30
; %bb.22:                               ;   in Loop: Header=BB2_8 Depth=1
	ds_store_b32 v6, v41
	ds_store_b32 v9, v19
	ds_load_u8 v7, v14 offset:2
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0xff, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_30
; %bb.23:                               ;   in Loop: Header=BB2_8 Depth=1
	ds_load_b32 v6, v6
	s_waitcnt lgkmcnt(0)
	v_lshl_add_u32 v7, v6, 1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v19, s2, v7
	ds_load_u8 v7, v19
	ds_load_u8 v20, v19 offset:2
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v7, v20
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s6, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB2_27
; %bb.24:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_mov_b32 s7, 0
.LBB2_25:                               ; %.preheader
                                        ;   Parent Loop BB2_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[19:20], null, v7, 3, s[2:3]
	ds_load_u8 v6, v19
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0xff, v6
	s_or_b32 s7, vcc_lo, s7
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB2_25
; %bb.26:                               ; %Flow
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr6
.LBB2_27:                               ; %Flow227
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB2_29
; %bb.28:                               ;   in Loop: Header=BB2_8 Depth=1
	ds_load_u8 v18, v19 offset:1
	v_mov_b32_e32 v7, v6
.LBB2_29:                               ; %.loopexit
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	v_lshl_add_u32 v6, v18, 2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v19, v7, 2, s1
	ds_store_b32 v6, v7
	ds_store_b32 v19, v18
.LBB2_30:                               ;   in Loop: Header=BB2_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, s33
	s_cselect_b32 s0, -1, 0
	s_branch .LBB2_32
.LBB2_31:                               ;   in Loop: Header=BB2_8 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr5
.LBB2_32:                               ; %Flow232
                                        ;   in Loop: Header=BB2_8 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_8
.LBB2_33:                               ; %.critedge
	ds_load_b32 v4, v8
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	global_store_b8 v[2:3], v4, off
	v_cmpx_ne_u64_e32 0, v[0:1]
	s_cbranch_execnz .LBB2_35
; %bb.34:                               ; %_ZdaPv.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
.LBB2_35:
	s_add_u32 s8, s46, 32
	s_addc_u32 s9, s47, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_dm_dealloc@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_dm_dealloc@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9piiKernelhPhS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 8
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 136
		.amdhsa_next_free_sgpr 54
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9piiKernelhPhS_S_, .Lfunc_end2-_Z9piiKernelhPhS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1532
; NumSgprs: 56
; NumVgprs: 136
; ScratchSize: 8
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 56
; NumVGPRsForWavesPerEU: 136
; Occupancy: 10
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.type	__unnamed_1,@object             ; @0
	.section	.rodata,"a",@progbits
	.p2align	2, 0x0
__unnamed_1:
	.long	130054                          ; 0x1fc06
	.long	129546                          ; 0x1fa0a
	.long	110114                          ; 0x1ae22
	.long	16288                           ; 0x3fa0
	.long	6                               ; 0x6
	.long	256                             ; 0x100
	.long	0                               ; 0x0
	.long	4195                            ; 0x1063
	.long	86927                           ; 0x1538f
	.long	86758                           ; 0x152e6
	.long	73744                           ; 0x12010
	.long	10904                           ; 0x2a98
	.long	399                             ; 0x18f
	.long	512                             ; 0x200
	.long	0                               ; 0x0
	.long	2804                            ; 0xaf4
	.long	65280                           ; 0xff00
	.long	64770                           ; 0xfd02
	.long	55054                           ; 0xd70e
	.long	8192                            ; 0x2000
	.long	0                               ; 0x0
	.long	128                             ; 0x80
	.long	0                               ; 0x0
	.long	2107                            ; 0x83b
	.long	43576                           ; 0xaa38
	.long	43406                           ; 0xa98e
	.long	36895                           ; 0x901f
	.long	5504                            ; 0x1580
	.long	56                              ; 0x38
	.long	256                             ; 0x100
	.long	0                               ; 0x0
	.long	1405                            ; 0x57d
	.long	32703                           ; 0x7fbf
	.long	32193                           ; 0x7dc1
	.long	27364                           ; 0x6ae4
	.long	4160                            ; 0x1040
	.long	63                              ; 0x3f
	.long	64                              ; 0x40
	.long	0                               ; 0x0
	.long	1054                            ; 0x41e
	.long	21816                           ; 0x5538
	.long	21646                           ; 0x548e
	.long	18399                           ; 0x47df
	.long	2816                            ; 0xb00
	.long	56                              ; 0x38
	.long	128                             ; 0x80
	.long	0                               ; 0x0
	.long	703                             ; 0x2bf
	.long	16367                           ; 0x3fef
	.long	15856                           ; 0x3df0
	.long	13477                           ; 0x34a5
	.long	2176                            ; 0x880
	.long	15                              ; 0xf
	.long	32                              ; 0x20
	.long	32768                           ; 0x8000
	.long	527                             ; 0x20f
	.long	10915                           ; 0x2aa3
	.long	10745                           ; 0x29f9
	.long	9133                            ; 0x23ad
	.long	1472                            ; 0x5c0
	.long	35                              ; 0x23
	.long	64                              ; 0x40
	.long	0                               ; 0x0
	.long	352                             ; 0x160
	.long	8187                            ; 0x1ffb
	.long	7676                            ; 0x1dfc
	.long	6524                            ; 0x197c
	.long	1280                            ; 0x500
	.long	11                              ; 0xb
	.long	16                              ; 0x10
	.long	134219776                       ; 0x8000800
	.long	265                             ; 0x109
	.long	5459                            ; 0x1553
	.long	5289                            ; 0x14a9
	.long	4495                            ; 0x118f
	.long	896                             ; 0x380
	.long	19                              ; 0x13
	.long	32                              ; 0x20
	.long	524288                          ; 0x80000
	.long	176                             ; 0xb0
	.long	4094                            ; 0xffe
	.long	3583                            ; 0xdff
	.long	3045                            ; 0xbe5
	.long	1024                            ; 0x400
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	1077952576                      ; 0x40404040
	.long	133                             ; 0x85
	.long	2730                            ; 0xaaa
	.long	2560                            ; 0xa00
	.long	2176                            ; 0x880
	.long	512                             ; 0x200
	.long	10                              ; 0xa
	.long	16                              ; 0x10
	.long	67109888                        ; 0x4000400
	.long	89                              ; 0x59
	.long	2047                            ; 0x7ff
	.long	1536                            ; 0x600
	.long	1305                            ; 0x519
	.long	1024                            ; 0x400
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	2290649224                      ; 0x88888888
	.long	66                              ; 0x42
	.long	1365                            ; 0x555
	.long	1195                            ; 0x4ab
	.long	1015                            ; 0x3f7
	.long	512                             ; 0x200
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	538976288                       ; 0x20202020
	.long	44                              ; 0x2c
	.long	1023                            ; 0x3ff
	.long	512                             ; 0x200
	.long	435                             ; 0x1b3
	.long	2048                            ; 0x800
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	2863311530                      ; 0xaaaaaaaa
	.long	34                              ; 0x22
	.long	682                             ; 0x2aa
	.long	512                             ; 0x200
	.long	435                             ; 0x1b3
	.long	2048                            ; 0x800
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	1145324612                      ; 0x44444444
	.long	35                              ; 0x23
	.size	__unnamed_1, 512

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym s
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           1
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
      - .offset:         128
        .size:           8
        .value_kind:     hidden_heap_v1
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9piiKernelhPhS_S_
    .private_segment_fixed_size: 8
    .sgpr_count:     56
    .sgpr_spill_count: 0
    .symbol:         _Z9piiKernelhPhS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     136
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
