__global__ void evaluateSymbolRegression(float* resultScore, float* result, float* programArray, float* evaluateBuffer, int* stackCountArray, int* programLength, int *maxProgramLengthFromMain, int *targetFunction, float* targetValueArray){
  // allocate buffer for processing
  const unsigned int maxProgramLength = maxProgramLengthFromMain[0];
  // extern __shared__ float copyBuffer[];

  const int index = threadIdx.x;

  int posCounter = programLength[index] - 1;

  // Copy a program array(individual) into buffer for processing
  while(posCounter >= 0){
    evaluateBuffer[index*maxProgramLength + posCounter] = 
      programArray[index*maxProgramLength + posCounter];
    posCounter--;
  }
  
  unsigned int currentProgramLength = programLength[index];
  while(currentProgramLength > 1){
    
    unsigned int currentProgramNode = 0;
    for(int i=currentProgramLength-1; i>=0; i--){
      // Remainder with 1.0 equals 0.0 (means integer),
      // stack count is less than zero,
      // detected as function node
      if(fmod((double)evaluateBuffer[index*maxProgramLength + i], 1.0) == 0.0 && 
	 (int)evaluateBuffer[index*maxProgramLength + i] > 65535 &&
	 stackCountArray[(int)evaluateBuffer[index*maxProgramLength + i] - 65535] <= 0){
	// Search Last Function Node
	currentProgramNode = i;
	break;
      }
    }

    int currentStackCount = 
      stackCountArray[(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] -65535];
    unsigned int subTreeRange = 1;

    while(currentStackCount < 1){
      currentStackCount += 1;
      subTreeRange++;
    }

    float resultFromFunctionNode = 0.0;
    unsigned int functionLabel = 
      (int)evaluateBuffer[index*maxProgramLength + currentProgramNode] - 65535;

    switch(functionLabel){
    case 0: //add
      resultFromFunctionNode = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	+ 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      break;
    case 1: //sub
      resultFromFunctionNode = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	- 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      break;
    case 2: //mul
      resultFromFunctionNode = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	*
	evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      break;
    case 3: //div
      if(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1] != 0.0 &&
	 evaluateBuffer[index*maxProgramLength + currentProgramNode + 2] != 0.0){
	resultFromFunctionNode = 
	  evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	  /
	  evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      }
      else
	resultFromFunctionNode = 1.0;
      break;
    case 4: //IfLessThenElse
      if(evaluateBuffer[index*maxProgramLength + currentProgramNode +1] > 
	 evaluateBuffer[index*maxProgramLength + currentProgramNode +2])
	resultFromFunctionNode = 
	  evaluateBuffer[index*maxProgramLength + currentProgramNode + 3];
      else
	resultFromFunctionNode =
	  evaluateBuffer[index*maxProgramLength + currentProgramNode + 4];
      break;
    case 5: //cos
      resultFromFunctionNode = 
	cos(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
      break;
    case 6: //sin
      resultFromFunctionNode = 
	sin(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
      break;
    default:
      resultFromFunctionNode = 0.0;
      break;
    }
    
    // Replace current function node with result of calc subtree
    evaluateBuffer[index*maxProgramLength + currentProgramNode] = 
      resultFromFunctionNode;
    // Copy node array after current subtree.
    for(int i=0; i<subTreeRange; i++)
      evaluateBuffer[index*maxProgramLength + currentProgramNode + 1 + i] = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode + subTreeRange + i];
    // new currentProgramLength
    currentProgramLength = currentProgramLength - subTreeRange + 1;
    // Fill zero after currentProgramLength
    for(int i=index*maxProgramLength + currentProgramLength; 
	i<(index+1)*maxProgramLength;
	i++)
      evaluateBuffer[i] = 0.0;
  }
  result[index] = (float)evaluateBuffer[index*maxProgramLength] - targetValueArray[index] * evaluateBuffer[index*maxProgramLength] - targetValueArray[index];
  
  __syncthreads(); // Waiting Finish All Threads
  
 resultScore[0] = 0.0;

  if(index == 0){ // If thread ID == 0 then calc score from RSS array
      float sum = 0;
      for(unsigned int j=0; j<blockDim.x; j++){
          sum += result[j];
      }
      if(targetFunction[0] == 0){ //MSE: Mean Square Error
	resultScore[0] = (sum / blockDim.x);
      }
      else if(targetFunction[0] == 1){ //MDL: Minimum Description Length
	resultScore[0] = (sum / blockDim.x) + (programLength[0] * logf(blockDim.x));
      }
      else{
	resultScore[0] = 0.0;
      }
  }
}

	.file	"tmpxft_0038cd48_00000000-6_evaluateSymbolRegression.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
	.type	_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_, @function
_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_, .-_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
	.globl	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.type	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, @function
_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
	.cfi_endproc
.LFE2033:
	.size	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, .-_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void evaluateSymbolRegression(float* resultScore, float* result, float* programArray, float* evaluateBuffer, int* stackCountArray, int* programLength, int *maxProgramLengthFromMain, int *targetFunction, float* targetValueArray){
  // allocate buffer for processing
  const unsigned int maxProgramLength = maxProgramLengthFromMain[0];
  // extern __shared__ float copyBuffer[];

  const int index = threadIdx.x;

  int posCounter = programLength[index] - 1;

  // Copy a program array(individual) into buffer for processing
  while(posCounter >= 0){
    evaluateBuffer[index*maxProgramLength + posCounter] = 
      programArray[index*maxProgramLength + posCounter];
    posCounter--;
  }
  
  unsigned int currentProgramLength = programLength[index];
  while(currentProgramLength > 1){
    
    unsigned int currentProgramNode = 0;
    for(int i=currentProgramLength-1; i>=0; i--){
      // Remainder with 1.0 equals 0.0 (means integer),
      // stack count is less than zero,
      // detected as function node
      if(fmod((double)evaluateBuffer[index*maxProgramLength + i], 1.0) == 0.0 && 
	 (int)evaluateBuffer[index*maxProgramLength + i] > 65535 &&
	 stackCountArray[(int)evaluateBuffer[index*maxProgramLength + i] - 65535] <= 0){
	// Search Last Function Node
	currentProgramNode = i;
	break;
      }
    }

    int currentStackCount = 
      stackCountArray[(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] -65535];
    unsigned int subTreeRange = 1;

    while(currentStackCount < 1){
      currentStackCount += 1;
      subTreeRange++;
    }

    float resultFromFunctionNode = 0.0;
    unsigned int functionLabel = 
      (int)evaluateBuffer[index*maxProgramLength + currentProgramNode] - 65535;

    switch(functionLabel){
    case 0: //add
      resultFromFunctionNode = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	+ 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      break;
    case 1: //sub
      resultFromFunctionNode = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	- 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      break;
    case 2: //mul
      resultFromFunctionNode = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	*
	evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      break;
    case 3: //div
      if(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1] != 0.0 &&
	 evaluateBuffer[index*maxProgramLength + currentProgramNode + 2] != 0.0){
	resultFromFunctionNode = 
	  evaluateBuffer[index*maxProgramLength + currentProgramNode +1] 
	  /
	  evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
      }
      else
	resultFromFunctionNode = 1.0;
      break;
    case 4: //IfLessThenElse
      if(evaluateBuffer[index*maxProgramLength + currentProgramNode +1] > 
	 evaluateBuffer[index*maxProgramLength + currentProgramNode +2])
	resultFromFunctionNode = 
	  evaluateBuffer[index*maxProgramLength + currentProgramNode + 3];
      else
	resultFromFunctionNode =
	  evaluateBuffer[index*maxProgramLength + currentProgramNode + 4];
      break;
    case 5: //cos
      resultFromFunctionNode = 
	cos(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
      break;
    case 6: //sin
      resultFromFunctionNode = 
	sin(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
      break;
    default:
      resultFromFunctionNode = 0.0;
      break;
    }
    
    // Replace current function node with result of calc subtree
    evaluateBuffer[index*maxProgramLength + currentProgramNode] = 
      resultFromFunctionNode;
    // Copy node array after current subtree.
    for(int i=0; i<subTreeRange; i++)
      evaluateBuffer[index*maxProgramLength + currentProgramNode + 1 + i] = 
	evaluateBuffer[index*maxProgramLength + currentProgramNode + subTreeRange + i];
    // new currentProgramLength
    currentProgramLength = currentProgramLength - subTreeRange + 1;
    // Fill zero after currentProgramLength
    for(int i=index*maxProgramLength + currentProgramLength; 
	i<(index+1)*maxProgramLength;
	i++)
      evaluateBuffer[i] = 0.0;
  }
  result[index] = (float)evaluateBuffer[index*maxProgramLength] - targetValueArray[index] * evaluateBuffer[index*maxProgramLength] - targetValueArray[index];
  
  __syncthreads(); // Waiting Finish All Threads
  
 resultScore[0] = 0.0;

  if(index == 0){ // If thread ID == 0 then calc score from RSS array
      float sum = 0;
      for(unsigned int j=0; j<blockDim.x; j++){
          sum += result[j];
      }
      if(targetFunction[0] == 0){ //MSE: Mean Square Error
	resultScore[0] = (sum / blockDim.x);
      }
      else if(targetFunction[0] == 1){ //MDL: Minimum Description Length
	resultScore[0] = (sum / blockDim.x) + (programLength[0] * logf(blockDim.x));
      }
      else{
	resultScore[0] = 0.0;
      }
  }
}

	.text
	.file	"evaluateSymbolRegression.hip"
	.globl	_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_ # -- Begin function _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.type	_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_,@function
_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_: # @_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, .Lfunc_end0-_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_,@object # @_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.section	.rodata,"a",@progbits
	.globl	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.p2align	3, 0x0
_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_:
	.quad	_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.size	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_"
	.size	.L__unnamed_1, 50

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_ ; -- Begin function _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.globl	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
	.p2align	8
	.type	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_,@function
_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_: ; @_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
; %bb.0:
	s_load_b512 s[4:19], s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v8, 2, v0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v9, v8, s[14:15]
	s_load_b32 s3, s[16:17], 0x0
	s_mov_b32 s17, 0
	s_mov_b32 s16, exec_lo
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, s3, v0
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 0, v9
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v4, 1, v9
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v2, v1, v4, -2
	v_add_nc_u32_e32 v4, -1, v4
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_u32_e32 vcc_lo, 2, v4
	v_add_co_u32 v5, s2, s10, v5
	global_load_b32 v2, v[10:11], off
	v_add_co_ci_u32_e64 v6, s2, s11, v6, s2
	s_or_b32 s17, vcc_lo, s17
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v2, off
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow337
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s8, exec_lo
	v_cmpx_lt_u32_e32 1, v9
	s_cbranch_execz .LBB0_73
; %bb.4:                                ; %.preheader195.lr.ph
	v_add_nc_u32_e32 v10, s3, v1
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v11, 1, v1
	v_mov_b32_e32 v12, 0x3ff00000
	s_add_u32 s9, s12, 0xfffc0004
	s_addc_u32 s12, s13, -1
	s_mov_b32 s13, 0
	s_mov_b32 s16, 0x7fffff
	s_mov_b32 s17, 0xb94c1982
	s_mov_b32 s20, 0x37d75334
.LBB0_5:                                ; %.preheader195
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_12 Depth 3
                                        ;     Child Loop BB0_68 Depth 2
                                        ;     Child Loop BB0_71 Depth 2
	v_dual_mov_b32 v13, v2 :: v_dual_add_nc_u32 v14, -1, v9
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v14
	s_cbranch_execz .LBB0_23
; %bb.6:                                ; %.lr.ph202.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s3, 0
.LBB0_7:                                ; %.lr.ph202
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_12 Depth 3
	v_add_nc_u32_e32 v3, v14, v1
	v_mov_b32_e32 v4, v2
                                        ; implicit-def: $vgpr6_vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v15, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[4:5], v15
	v_and_b32_e32 v13, 0x80000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s21, |v[4:5]|, 1.0
	s_and_saveexec_b32 s22, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s22
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	v_cmp_eq_f64_e64 vcc_lo, |v[4:5]|, 1.0
	v_cndmask_b32_e32 v7, v5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v4, 0, vcc_lo
                                        ; implicit-def: $vgpr13
; %bb.9:                                ; %Flow325
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_and_not1_saveexec_b32 s21, s21
	s_cbranch_execz .LBB0_15
; %bb.10:                               ;   in Loop: Header=BB0_7 Depth=2
	v_frexp_mant_f64_e64 v[6:7], |v[4:5]|
	v_frexp_exp_i32_f64_e32 v16, v[4:5]
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[6:7], v[6:7], 26
	v_add_nc_u32_e32 v3, -1, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 26, v3
	s_cbranch_execz .LBB0_14
; %bb.11:                               ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB0_7 Depth=2
	v_add_nc_u32_e32 v16, 25, v16
	s_mov_b32 s23, 0
.LBB0_12:                               ; %.preheader.i.i
                                        ;   Parent Loop BB0_5 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[17:18], v[6:7]
	v_add_f64 v[6:7], v[6:7], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
	v_cndmask_b32_e32 v3, 0x80000000, v12, vcc_lo
	v_add_f64 v[6:7], v[6:7], v[2:3]
	v_mov_b32_e32 v3, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v16, 26, v3
	v_cmp_gt_u32_e32 vcc_lo, 53, v16
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(VALU_DEP_4)
	v_ldexp_f64 v[6:7], v[6:7], 26
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_12
; %bb.13:                               ; %Flow323
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	v_subrev_nc_u32_e32 v3, 52, v3
.LBB0_14:                               ; %Flow324
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v3, 25, v3
	v_ldexp_f64 v[6:7], v[6:7], v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[16:17], v[6:7]
	v_add_f64 v[6:7], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
	v_cndmask_b32_e32 v3, 0x80000000, v12, vcc_lo
	v_add_f64 v[6:7], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v7, v13, v7
.LBB0_15:                               ; %Flow326
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x1f8
	s_mov_b32 s21, -1
	s_mov_b32 s23, -1
	s_mov_b32 s22, exec_lo
                                        ; implicit-def: $vgpr13
	v_cndmask_b32_e32 v4, 0x7ff80000, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0, v6, vcc_lo
	v_cmpx_eq_f64_e32 0, v[3:4]
	s_cbranch_execz .LBB0_19
; %bb.16:                               ;   in Loop: Header=BB0_7 Depth=2
	v_cvt_i32_f32_e32 v3, v15
	s_mov_b32 s24, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e64 s23, 0x10000, v3
	v_cmpx_lt_i32_e32 0xffff, v3
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_7 Depth=2
	v_mov_b32_e32 v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_not1_b32 s23, s23, exec_lo
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s9, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s12, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, 0, v3
	s_and_b32 s25, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, s25
.LBB0_18:                               ; %Flow330
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	v_mov_b32_e32 v13, v14
	s_or_not1_b32 s23, s23, exec_lo
.LBB0_19:                               ; %Flow329
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_and_saveexec_b32 s22, s23
; %bb.20:                               ;   in Loop: Header=BB0_7 Depth=2
	v_add_nc_u32_e32 v3, -1, v14
	v_cmp_gt_i32_e32 vcc_lo, 1, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, v3
	s_or_not1_b32 s21, vcc_lo, exec_lo
; %bb.21:                               ; %Flow331
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s21, exec_lo, s21
	s_or_b32 s3, s21, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_7
; %bb.22:                               ; %Flow332
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_23:                               ; %Flow333
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, v13, v1
	s_mov_b32 s2, exec_lo
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v6, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cvt_i32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[14:15], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s9, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s12, v15, vcc_lo
	global_load_b32 v7, v[14:15], off
                                        ; implicit-def: $vgpr14
	v_cmpx_lt_i32_e32 0x10001, v6
	s_xor_b32 s21, exec_lo, s2
	s_cbranch_execz .LBB0_55
; %bb.24:                               ; %NodeBlock285
                                        ;   in Loop: Header=BB0_5 Depth=1
                                        ; implicit-def: $vgpr14
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0x10003, v6
	s_xor_b32 s22, exec_lo, s2
	s_cbranch_execz .LBB0_40
; %bb.25:                               ; %NodeBlock283
                                        ;   in Loop: Header=BB0_5 Depth=1
                                        ; implicit-def: $vgpr14
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0x10004, v6
	s_xor_b32 s23, exec_lo, s2
	s_cbranch_execz .LBB0_33
; %bb.26:                               ; %LeafBlock281
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v14, 0
	s_mov_b32 s24, exec_lo
	v_cmpx_eq_u32_e32 0x10005, v6
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 1, v5
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr14
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0x7fffffff, v5
	v_cmpx_ngt_f32_e64 0x48000000, |v5|
	s_xor_b32 s25, exec_lo, s3
	s_cbranch_execz .LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_and_or_b32 v24, v6, s16, 0x800000
	v_mov_b32_e32 v16, v2
	v_lshrrev_b32_e32 v21, 23, v6
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v24, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v22, 0xffffff88, v21
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v24, v[15:16]
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v15, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v23, v23, v22
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v24, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s2, 31, v23
	v_cndmask_b32_e64 v25, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v15, v19 :: v_dual_cndmask_b32 v14, v18, v14
	v_add_nc_u32_e32 v25, v25, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v24, v[15:16]
	v_cmp_lt_u32_e64 s3, 31, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v15, v20
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v24, v[15:16]
	v_cndmask_b32_e64 v14, v17, v14, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v21
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v24, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v24, v[15:16]
	v_cndmask_b32_e64 v15, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v21, v19 :: v_dual_add_nc_u32 v15, v15, v25
	v_dual_cndmask_b32 v22, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_cndmask_b32_e64 v19, v22, v16, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v22, s2
	v_cndmask_b32_e64 v16, v16, v20, s2
	v_sub_nc_u32_e32 v22, 32, v15
	v_cndmask_b32_e64 v20, v20, v17, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v19, s3
	v_cndmask_b32_e64 v19, v19, v16, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v16, v20, s3
	v_cndmask_b32_e64 v14, v20, v14, s3
	v_alignbit_b32 v23, v21, v19, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v19, v16, v22
	v_cndmask_b32_e32 v15, v23, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v16, v14, v22
	v_cndmask_b32_e32 v17, v18, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v18, v15, 29, 1
	v_cndmask_b32_e32 v16, v21, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v15, v17, 30
	v_sub_nc_u32_e32 v20, 0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v17, v16, 30
	v_alignbit_b32 v14, v16, v14, 30
	v_xor_b32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v16, v17, v20
	v_xor_b32_e32 v14, v14, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v19, v19, v16, v17
	v_alignbit_b32 v14, v16, v14, v17
	v_lshrrev_b32_e32 v17, 29, v15
	v_lshrrev_b32_e32 v15, 30, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v19, v14, 9
	v_lshlrev_b32_e32 v17, 31, v17
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v15, v18, v15
	v_clz_i32_u32_e32 v20, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v22, 0.5, v17
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v22, v22, v23
	v_sub_nc_u32_e32 v24, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v16, v14, v24
	v_or_b32_e32 v16, v19, v22
	v_add_lshl_u32 v19, v20, v21, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v19
	v_fma_f32 v19, 0x3fc90fda, v16, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmac_f32_e32 v19, 0x33a22168, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v17
	v_fmac_f32_e32 v19, 0x3fc90fda, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v14, v20, v19
.LBB0_29:                               ; %Flow304
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s2, s25
; %bb.30:                               ;   in Loop: Header=BB0_5 Depth=1
	v_mul_f32_e64 v14, 0x3f22f983, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v15, v14
	v_fma_f32 v14, 0xbfc90fda, v15, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 0xb3a22168, v15
	v_fmac_f32_e32 v14, 0xa7c234c4, v15
	v_cvt_i32_f32_e32 v15, v15
; %bb.31:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v16, v14, v14 :: v_dual_and_b32 v19, 1, v15
	v_xor_b32_e32 v6, v6, v5
	v_lshlrev_b32_e32 v15, 30, v15
	v_fmaak_f32 v17, s17, v16, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	v_and_b32_e32 v15, 0x80000000, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v17, v16, v17, 0xbe2aaa9d
	v_dual_fmaak_f32 v18, s20, v16, 0xbab64f3b :: v_dual_mul_f32 v17, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v18, v16, v18, 0x3d2aabf7
	v_fmac_f32_e32 v14, v14, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v18, v16, v18, 0xbf000004
	v_fma_f32 v16, v16, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v16, v14, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	v_xor3_b32 v6, v6, v15, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v14, 0x7fc00000, v6, vcc_lo
.LBB0_32:                               ; %Flow305
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
                                        ; implicit-def: $vgpr5
.LBB0_33:                               ; %Flow307
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s23, s23
	s_cbranch_execz .LBB0_39
; %bb.34:                               ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 1, v5
                                        ; implicit-def: $vgpr14
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
                                        ; implicit-def: $vgpr6
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e64 0x48000000, |v5|
	s_xor_b32 s24, exec_lo, s3
	s_cbranch_execz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_5 Depth=1
	v_and_b32_e32 v6, 0x7fffffff, v5
	v_mov_b32_e32 v16, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v24, v6, s16, 0x800000
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v24, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v24, v[15:16]
	v_mov_b32_e32 v15, v18
	v_lshrrev_b32_e32 v6, 23, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v24, v[15:16]
	v_add_nc_u32_e32 v6, 0xffffff88, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v6
	v_mov_b32_e32 v15, v19
	v_cndmask_b32_e64 v22, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v24, v[15:16]
	v_cndmask_b32_e32 v14, v18, v14, vcc_lo
	v_dual_mov_b32 v15, v20 :: v_dual_add_nc_u32 v6, v22, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v6
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v24, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, 0, 0xffffffe0, s2
	v_dual_mov_b32 v15, v21 :: v_dual_add_nc_u32 v6, v23, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v6
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v24, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v24, v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v21, v19, vcc_lo
	v_cndmask_b32_e64 v15, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v21, v23, v21 :: v_dual_cndmask_b32 v22, v22, v20
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v6, v15, v6
	v_cndmask_b32_e32 v15, v19, v17, vcc_lo
	v_cndmask_b32_e64 v17, v22, v16, s2
	v_cndmask_b32_e64 v19, v21, v22, s2
	v_cndmask_b32_e64 v16, v16, v20, s2
	v_sub_nc_u32_e32 v21, 32, v6
	v_cndmask_b32_e64 v20, v20, v15, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	v_cndmask_b32_e64 v19, v19, v17, s3
	v_cndmask_b32_e64 v17, v17, v16, s3
	v_cndmask_b32_e64 v14, v15, v14, s2
	v_cndmask_b32_e64 v16, v16, v20, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v19, v17, v21
	v_cndmask_b32_e64 v14, v20, v14, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v17, v16, v21
	v_cndmask_b32_e32 v6, v22, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v16, v14, v21
	v_cndmask_b32_e32 v15, v18, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v17, v6, 29, 1
	v_cndmask_b32_e32 v16, v20, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v6, v15, 30
	v_sub_nc_u32_e32 v19, 0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v15, v16, 30
	v_alignbit_b32 v14, v16, v14, 30
	v_xor_b32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v15, v19
	v_xor_b32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v20, v18
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v15, v18, v14, 9
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v19, v15
	v_or_b32_e32 v21, 0.5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v19, 32, v19
	v_sub_nc_u32_e32 v21, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v23, 31, v19
	v_alignbit_b32 v14, v15, v14, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	v_lshrrev_b32_e32 v14, 9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	v_sub_nc_u32_e32 v14, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	v_add_nc_u32_e32 v14, 0x33000000, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, 0x33a22168, v15
	v_or_b32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, 0x3fc90fda, v14
	v_lshrrev_b32_e32 v14, 30, v6
	v_add_f32_e32 v6, v19, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v17, v14
.LBB0_36:                               ; %Flow306
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s2, s24
; %bb.37:                               ;   in Loop: Header=BB0_5 Depth=1
	v_mul_f32_e64 v6, 0x3f22f983, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v14, v6
	v_fma_f32 v6, 0xbfc90fda, v14, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0xb3a22168, v14
	v_fmac_f32_e32 v6, 0xa7c234c4, v14
	v_cvt_i32_f32_e32 v14, v14
; %bb.38:                               ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v6, v6
	v_and_b32_e32 v18, 1, v14
	v_lshlrev_b32_e32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v16, s17, v15, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v14, 0x80000000, v14
	v_fmaak_f32 v16, v15, v16, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v17, s20, v15, 0xbab64f3b :: v_dual_mul_f32 v16, v15, v16
	v_dual_fmaak_f32 v17, v15, v17, 0x3d2aabf7 :: v_dual_fmac_f32 v6, v6, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v17, v15, v17, 0xbf000004
	v_fma_f32 v15, v15, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, -v6, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	v_xor_b32_e32 v6, v14, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v14, 0x7fc00000, v6, vcc_lo
.LBB0_39:                               ; %Flow308
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
.LBB0_40:                               ; %Flow315
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s2, s22
	s_cbranch_execz .LBB0_54
; %bb.41:                               ; %NodeBlock279
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr14
	v_cmpx_lt_i32_e32 0x10002, v6
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_47
; %bb.42:                               ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v15, v2 :: v_dual_add_nc_u32 v14, 1, v5
	v_dual_mov_b32 v17, v2 :: v_dual_add_nc_u32 v16, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
	s_clause 0x1
	global_load_b32 v6, v[14:15], off
	global_load_b32 v14, v[16:17], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e32 vcc_lo, v6, v14
                                        ; implicit-def: $vgpr14
	s_and_saveexec_b32 s22, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v14, v[5:6], off
                                        ; implicit-def: $vgpr5
.LBB0_44:                               ; %Flow309
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB0_46
; %bb.45:                               ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_load_b32 v14, v[5:6], off
.LBB0_46:                               ; %Flow310
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
                                        ; implicit-def: $vgpr5
.LBB0_47:                               ; %Flow313
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_53
; %bb.48:                               ;   in Loop: Header=BB0_5 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v15, v2 :: v_dual_add_nc_u32 v14, 1, v5
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s10, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	global_load_b32 v6, v[14:15], off
	v_mov_b32_e32 v14, 1.0
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v6
	s_cbranch_execz .LBB0_52
; %bb.49:                               ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v15, v2 :: v_dual_add_nc_u32 v14, 2, v5
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s10, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	global_load_b32 v5, v[14:15], off
	v_mov_b32_e32 v14, 1.0
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v5
; %bb.50:                               ;   in Loop: Header=BB0_5 Depth=1
	v_div_scale_f32 v14, null, v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	v_fmac_f32_e32 v15, v16, v15
	v_div_scale_f32 v16, vcc_lo, v6, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v16, v15
	v_fma_f32 v18, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v15
	v_fma_f32 v14, -v14, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v14, v14, v15, v17
	v_div_fixup_f32 v14, v14, v5, v6
; %bb.51:                               ; %Flow311
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_52:                               ; %Flow312
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_53:                               ; %Flow314
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_54:                               ; %Flow316
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
.LBB0_55:                               ; %Flow322
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s2, s21
	s_cbranch_execz .LBB0_67
; %bb.56:                               ; %NodeBlock277
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr14
	v_cmpx_lt_i32_e32 0xffff, v6
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_62
; %bb.57:                               ; %NodeBlock
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s21, exec_lo
                                        ; implicit-def: $vgpr14
	v_cmpx_lt_i32_e32 0x10000, v6
	s_xor_b32 s21, exec_lo, s21
	s_cbranch_execz .LBB0_59
; %bb.58:                               ;   in Loop: Header=BB0_5 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v15, v2 :: v_dual_add_nc_u32 v14, 1, v5
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v14, v[14:15], off
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v14, v14, v5
                                        ; implicit-def: $vgpr5
.LBB0_59:                               ; %Flow317
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s21, s21
	s_cbranch_execz .LBB0_61
; %bb.60:                               ;   in Loop: Header=BB0_5 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v15, v2 :: v_dual_add_nc_u32 v14, 1, v5
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v14, v[14:15], off
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v14, v14, v5
.LBB0_61:                               ; %Flow318
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
.LBB0_62:                               ; %Flow320
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_66
; %bb.63:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v14, 0
	s_mov_b32 s21, exec_lo
	v_cmpx_eq_u32_e32 0xffff, v6
	s_cbranch_execz .LBB0_65
; %bb.64:                               ;   in Loop: Header=BB0_5 Depth=1
	v_dual_mov_b32 v15, v2 :: v_dual_add_nc_u32 v14, 1, v5
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v14, v[14:15], off
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v14, v5
.LBB0_65:                               ; %Flow319
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_66:                               ; %Flow321
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_67:                               ; %.lr.ph213
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_max_i32_e32 v6, 1, v7
	v_sub_nc_u32_e32 v15, 2, v7
	v_cmp_gt_i32_e32 vcc_lo, 1, v7
	v_add_nc_u32_e32 v5, v11, v13
	s_mov_b32 s3, 0
	v_sub_nc_u32_e32 v13, v6, v7
	s_mov_b32 s21, 0
	v_cndmask_b32_e32 v6, 1, v15, vcc_lo
	global_store_b32 v[3:4], v14, off
	v_add_nc_u32_e32 v7, v13, v5
.LBB0_68:                               ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v3, s21, v7
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v13, v[3:4], off
	v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v3, s21, v5
	s_add_i32 s21, s21, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, s21, v6
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s2, s10, v3
	v_add_co_ci_u32_e64 v4, s2, s11, v4, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v13, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_68
; %bb.69:                               ; %._crit_edge214
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_sub_nc_u32_e32 v3, v9, v6
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, 1, v3
	v_add_nc_u32_e32 v3, v9, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v3, v10
	s_cbranch_execz .LBB0_72
; %bb.70:                               ; %.lr.ph217.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_mov_b32 s21, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
.LBB0_71:                               ; %.lr.ph217
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v3, 1, v3
	global_store_b32 v[4:5], v2, off
	v_add_co_u32 v4, s2, v4, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v5, s2, 0, v5, s2
	v_cmp_ge_u32_e32 vcc_lo, v3, v10
	s_or_b32 s21, vcc_lo, s21
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_71
.LBB0_72:                               ; %Flow303
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_gt_u32_e32 vcc_lo, 2, v9
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_5
.LBB0_73:                               ; %Flow335
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b64 s[2:3], s[0:1], 0x40
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_load_b32 v1, v[3:4], off
	s_waitcnt lgkmcnt(0)
	global_load_b32 v3, v8, s[2:3]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	v_fma_f32 v1, -v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v3
	global_store_b32 v8, v1, s[6:7]
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_store_b32 v2, v2, s[4:5]
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_88
; %bb.74:                               ; %.preheader
	s_load_b32 s0, s[0:1], 0x54
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_77
; %bb.75:                               ; %.lr.ph224.preheader
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s0, s1
.LBB0_76:                               ; %.lr.ph224
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v1, v0, s[6:7]
	s_add_i32 s0, s0, -1
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v1
	s_cbranch_scc0 .LBB0_76
.LBB0_77:                               ; %NodeBlock293
	s_load_b32 s2, s[18:19], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_80
; %bb.78:                               ; %LeafBlock291
	s_cmp_eq_u32 s2, 1
	s_mov_b32 s3, 0
	s_cbranch_scc0 .LBB0_81
; %bb.79:
	v_cvt_f32_u32_e32 v0, s1
	s_load_b32 s6, s[14:15], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v1, null, v0, v0, v2
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_div_scale_f32 v6, s0, v2, v0, v2
	v_rcp_f32_e32 v3, v1
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v1, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v0, v4 :: v_dual_fmac_f32 v3, v5, v3
	v_log_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x3f317217, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v9, 0x3f317217, v4, -v7
	v_mul_f32_e32 v5, v6, v3
	v_fma_f32 v8, -v1, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v5, v8, v3
	v_fmamk_f32 v8, v4, 0x3377d1cf, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v1, -v1, v5, v6
	v_cndmask_b32_e64 v6, 0, 0x41b17218, vcc_lo
	s_mov_b32 vcc_lo, s0
	v_add_f32_e32 v7, v7, v8
	s_mov_b32 s0, -1
	v_div_fmas_f32 v1, v1, v3, v5
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v0, v1, v0, v2
	v_cndmask_b32_e32 v3, v4, v7, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v4, s6
	v_sub_f32_e32 v1, v3, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, v1, v4
	s_branch .LBB0_82
.LBB0_80:
	s_mov_b32 s3, -1
.LBB0_81:                               ; %Flow
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr0
.LBB0_82:                               ; %Flow
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_86
; %bb.83:                               ; %LeafBlock289
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB0_85
; %bb.84:
                                        ; implicit-def: $vgpr0
	s_branch .LBB0_86
.LBB0_85:
	v_cvt_f32_u32_e32 v0, s1
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v1, null, v0, v0, v2
	v_rcp_f32_e32 v3, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v1, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v3
	v_div_scale_f32 v4, vcc_lo, v2, v0, v2
	v_mul_f32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v1, v5, v4
	v_fmac_f32_e32 v5, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v5, v4
	v_div_fmas_f32 v1, v1, v3, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, v0, v2
.LBB0_86:                               ; %Flow296
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_88
; %bb.87:                               ; %.sink.split
	v_mov_b32_e32 v1, 0
	global_store_b32 v1, v0, s[4:5]
.LBB0_88:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, .Lfunc_end0-_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4800
; NumSgprs: 28
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
