#include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
/****************************************************************************
  This program gives an example of a poor way to implement a password cracker
  in CUDA C. It is poor because it acheives this with just one thread, which
  is obviously not good given the scale of parallelism available to CUDA
  programs.
 
  The intentions of this program are:
    1) Demonstrate the use of __device__ and __global__ functions
    2) Enable a simulation of password cracking in the absence of library
       with equivalent functionality to libcrypt. The password to be found
       is hardcoded into a function called is_a_match.   

  Compile and run with:
  nvcc -o crackpwd_2alph2digt crackpwd_2alpha_2digit.cu


     To Run:
     ./crackpwd_2alph2digt > resultscuda_2alp2dig.txt

  Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/

/****************************************************************************
  This function returns 1 if the attempt at cracking the password is
  identical to the plain text password string stored in the program.
  Otherwise,it returns 0.
*****************************************************************************/
__device__ int is_a_match(char *attempt) {
  char password1[] = "DV72";
  char password2[] = "ET21";
  char password3[] = "IR24";
  char password4[] = "SD49";

  char *a = attempt;
  char *y = attempt;
  char *u = attempt;
  char *s = attempt;
  char *pass1 = password1;
  char *pass2 = password2;
  char *pass3 = password3;
  char *pass4 = password4;

  while(*a == *pass1) {
   if(*a == '\0')
    {
    printf("Found password: %s\n",password1);
      break;
    }

    a++;
    pass1++;
  }
    
  while(*y == *pass2) {
   if(*y == '\0')
    {
    printf("Found password: %s\n",password2);
      break;
}

    y++;
    pass2++;
  }

  while(*u == *pass3) {
   if(*u == '\0')
    {
    printf("Found password: %s\n",password3);
      break;
    }

    u++;
    pass3++;
  }

  while(*s == *pass4) {
   if(*s == '\0')
    {
    printf("Found password: %s\n",password4);
      return 1;
    }

    s++;
    pass4++;
  }
  return 0;

}
/****************************************************************************
  The kernel function assume that there will be only one thread and uses
  nested loops to generate all possible passwords and test whether they match
  the hidden password.
*****************************************************************************/

__global__ void  kernel() {
char h,t;
 
  char password[5];
  password[4] = '\0';

int i = blockIdx.x+65;
int j = threadIdx.x+65;
char firstValue = i;
char secondValue = j;
    
password[0] = firstValue;
password[1] = secondValue;
    for(h='0'; h<='9'; h++){
      for(t='0'; t<='9'; t++){
            password[2] = h;
            password[3] = t;
          if(is_a_match(password)) {
        //printf("Success");
          }
             else {
         //printf("tried: %s\n", password);          
            }
          }
        } 
      
}
int time_difference(struct timespec *start,
                    struct timespec *finish,
                    long long int *difference) {
  long long int ds =  finish->tv_sec - start->tv_sec;
  long long int dn =  finish->tv_nsec - start->tv_nsec;

  if(dn < 0 ) {
    ds--;
    dn += 1000000000;
  }
  *difference = ds * 1000000000 + dn;
  return !(*difference > 0);
}


int main() {

  struct  timespec start, finish;
  long long int time_elapsed;
  clock_gettime(CLOCK_MONOTONIC, &start);

kernel <<<26,26>>>();
  cudaThreadSynchronize();

  clock_gettime(CLOCK_MONOTONIC, &finish);
  time_difference(&start, &finish, &time_elapsed);
  printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed, (time_elapsed/1.0e9));
  return 0;
}





	.file	"tmpxft_002650d9_00000000-6_cudapass.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10is_a_matchPc
	.type	_Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10is_a_matchPc, .-_Z10is_a_matchPc
	.globl	_Z15time_differenceP8timespecS0_Px
	.type	_Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	(%rsi), %rax
	movq	8(%rsi), %rcx
	subq	(%rdi), %rax
	subq	8(%rdi), %rcx
	jns	.L5
	decq	%rax
	addq	$1000000000, %rcx
.L5:
	imulq	$1000000000, %rax, %rax
	addq	%rcx, %rax
	testq	%rax, %rax
	movq	%rax, (%rdx)
	setle	%al
	movzbl	%al, %eax
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
	.globl	_Z24__device_stub__Z6kernelvv
	.type	_Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z6kernelv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L7:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
	.globl	_Z6kernelv
	.type	_Z6kernelv, @function
_Z6kernelv:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z6kernelvv
	.cfi_endproc
.LFE2055:
	.size	_Z6kernelv, .-_Z6kernelv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Time elapsed was %lldns or %0.9lfs\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$72, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rbx
	movq	%rbx, %rsi
	call	clock_gettime@PLT
	movl	$2147483661, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addq	%rdi, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 48(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 40(%rsp)
	movq	%rdi, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	call	_Z24__device_stub__Z6kernelvv
.L13:
	call	cudaThreadSynchronize@PLT
	leaq	40(%rsp), %rbp
	movl	$1, %edi
	movq	%rbp, %rsi
	call	clock_gettime@PLT
	leaq	8(%rsp), %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	call	_Z15time_differenceP8timespecS0_Px
	movq	8(%rsp), %rdx
	leaq	.LC1(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtsi2sdq	%rdx, %xmm0
	divsd	.LC0(%rip), %xmm0
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$72, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z6kernelv"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1104006501
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
/****************************************************************************
  This program gives an example of a poor way to implement a password cracker
  in CUDA C. It is poor because it acheives this with just one thread, which
  is obviously not good given the scale of parallelism available to CUDA
  programs.
 
  The intentions of this program are:
    1) Demonstrate the use of __device__ and __global__ functions
    2) Enable a simulation of password cracking in the absence of library
       with equivalent functionality to libcrypt. The password to be found
       is hardcoded into a function called is_a_match.   

  Compile and run with:
  nvcc -o crackpwd_2alph2digt crackpwd_2alpha_2digit.cu


     To Run:
     ./crackpwd_2alph2digt > resultscuda_2alp2dig.txt

  Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/

/****************************************************************************
  This function returns 1 if the attempt at cracking the password is
  identical to the plain text password string stored in the program.
  Otherwise,it returns 0.
*****************************************************************************/
__device__ int is_a_match(char *attempt) {
  char password1[] = "DV72";
  char password2[] = "ET21";
  char password3[] = "IR24";
  char password4[] = "SD49";

  char *a = attempt;
  char *y = attempt;
  char *u = attempt;
  char *s = attempt;
  char *pass1 = password1;
  char *pass2 = password2;
  char *pass3 = password3;
  char *pass4 = password4;

  while(*a == *pass1) {
   if(*a == '\0')
    {
    printf("Found password: %s\n",password1);
      break;
    }

    a++;
    pass1++;
  }
    
  while(*y == *pass2) {
   if(*y == '\0')
    {
    printf("Found password: %s\n",password2);
      break;
}

    y++;
    pass2++;
  }

  while(*u == *pass3) {
   if(*u == '\0')
    {
    printf("Found password: %s\n",password3);
      break;
    }

    u++;
    pass3++;
  }

  while(*s == *pass4) {
   if(*s == '\0')
    {
    printf("Found password: %s\n",password4);
      return 1;
    }

    s++;
    pass4++;
  }
  return 0;

}
/****************************************************************************
  The kernel function assume that there will be only one thread and uses
  nested loops to generate all possible passwords and test whether they match
  the hidden password.
*****************************************************************************/

__global__ void  kernel() {
char h,t;
 
  char password[5];
  password[4] = '\0';

int i = blockIdx.x+65;
int j = threadIdx.x+65;
char firstValue = i;
char secondValue = j;
    
password[0] = firstValue;
password[1] = secondValue;
    for(h='0'; h<='9'; h++){
      for(t='0'; t<='9'; t++){
            password[2] = h;
            password[3] = t;
          if(is_a_match(password)) {
        //printf("Success");
          }
             else {
         //printf("tried: %s\n", password);          
            }
          }
        } 
      
}
int time_difference(struct timespec *start,
                    struct timespec *finish,
                    long long int *difference) {
  long long int ds =  finish->tv_sec - start->tv_sec;
  long long int dn =  finish->tv_nsec - start->tv_nsec;

  if(dn < 0 ) {
    ds--;
    dn += 1000000000;
  }
  *difference = ds * 1000000000 + dn;
  return !(*difference > 0);
}


int main() {

  struct  timespec start, finish;
  long long int time_elapsed;
  clock_gettime(CLOCK_MONOTONIC, &start);

kernel <<<26,26>>>();
  hipDeviceSynchronize();

  clock_gettime(CLOCK_MONOTONIC, &finish);
  time_difference(&start, &finish, &time_elapsed);
  printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed, (time_elapsed/1.0e9));
  return 0;
}





	.text
	.file	"cudapass.hip"
	.globl	_Z21__device_stub__kernelv      # -- Begin function _Z21__device_stub__kernelv
	.type	_Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv:             # @_Z21__device_stub__kernelv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z6kernelv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
	.cfi_endproc
                                        # -- End function
	.globl	_Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
	.type	_Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px:     # @_Z15time_differenceP8timespecS0_Px
	.cfi_startproc
# %bb.0:
	movq	(%rsi), %rax
	subq	(%rdi), %rax
	movq	8(%rsi), %rcx
	subq	8(%rdi), %rcx
	leaq	1000000000(%rcx), %rsi
	movq	%rcx, %rdi
	sarq	$63, %rdi
	addq	%rax, %rdi
	testq	%rcx, %rcx
	cmovnsq	%rcx, %rsi
	imulq	$1000000000, %rdi, %rcx         # imm = 0x3B9ACA00
	xorl	%eax, %eax
	addq	%rsi, %rcx
	movq	%rcx, (%rdx)
	setle	%al
	retq
.Lfunc_end1:
	.size	_Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	%rsp, %rsi
	movl	$1, %edi
	callq	clock_gettime
	movabsq	$4294967322, %rdi               # imm = 0x10000001A
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	callq	_Z21__device_stub__kernelv
.LBB2_2:
	callq	hipDeviceSynchronize
	leaq	16(%rsp), %rbx
	movl	$1, %edi
	movq	%rbx, %rsi
	callq	clock_gettime
	movq	(%rbx), %rax
	subq	(%rsp), %rax
	movq	8(%rbx), %rcx
	subq	8(%rsp), %rcx
	leaq	1000000000(%rcx), %rdx
	movq	%rcx, %rsi
	sarq	$63, %rsi
	addq	%rax, %rsi
	testq	%rcx, %rcx
	cmovnsq	%rcx, %rdx
	imulq	$1000000000, %rsi, %rsi         # imm = 0x3B9ACA00
	addq	%rdx, %rsi
	cvtsi2sd	%rsi, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelv, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelv,@object              # @_Z6kernelv
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelv
	.p2align	3, 0x0
_Z6kernelv:
	.quad	_Z21__device_stub__kernelv
	.size	_Z6kernelv, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Time elapsed was %lldns or %0.9lfs\n"
	.size	.L.str, 36

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelv"
	.size	.L__unnamed_1, 11

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelv
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelv
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	v_or_b32_e32 v2, 2, v0
	v_cmp_eq_u32_e64 s0, 0, v6
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v2, v0, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u64_e32 0, v[7:8]
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v11, 2 :: v_dual_and_b32 v6, 2, v10
	v_mov_b32_e32 v30, 0
	v_and_b32_e32 v0, -3, v10
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_mov_b32_e32 v12, 1
	s_mov_b32 s12, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v32, 0, v5 :: v_dual_cndmask_b32 v31, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v31
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v31
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[9:10], 3, v[31:32]
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v14, v8
	v_mov_b32_e32 v13, v7
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader31
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v10, v[13:14]
	v_mov_b32_e32 v16, s11
	v_add_co_u32 v13, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v15, 0xffff, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], s4, v[15:16]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v9
	v_or_b32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v15, v2
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow232
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow234
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow236
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v7
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	s_clause 0x5
	flat_load_u8 v2, v[7:8]
	flat_load_u8 v3, v[7:8] offset:1
	flat_load_u8 v9, v[7:8] offset:2
	flat_load_u8 v10, v[7:8] offset:3
	flat_load_u8 v13, v[7:8] offset:5
	flat_load_u8 v14, v[7:8] offset:4
	v_mov_b32_e32 v16, v30
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v3, 8, v3
	s_clause 0x1
	flat_load_u8 v15, v[7:8] offset:7
	flat_load_d16_hi_u8 v16, v[7:8] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_or_b32_e32 v2, v3, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v3, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v3, 0, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v2, v2, 0, 0
	v_or3_b32 v2, v2, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v15
	v_add_nc_u32_e32 v15, -8, v31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_or3_b32 v3, v3, v16, v9
	v_add_co_u32 v9, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
.LBB0_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v15
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v15
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_13:                               ; %.preheader29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v16, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v15
	flat_load_u8 v16, v[16:17]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v17, s11 :: v_dual_and_b32 v16, 0xffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], s0, v[16:17]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v16, v13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow227
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_15:                               ; %Flow229
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr15
.LBB0_16:                               ; %Flow231
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v13, v[9:10]
	flat_load_u8 v14, v[9:10] offset:1
	flat_load_u8 v16, v[9:10] offset:2
	flat_load_u8 v17, v[9:10] offset:3
	flat_load_u8 v18, v[9:10] offset:5
	flat_load_u8 v19, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v20, v30 :: v_dual_and_b32 v13, 0xffff, v13
	s_clause 0x1
	flat_load_u8 v21, v[9:10] offset:7
	flat_load_d16_hi_u8 v20, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v14, 8, v14
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v16, 16, v16
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v17, 24, v17
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v13, v14, v13
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v14, 8, v18
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v13, v13, v16, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v14, 0, v19, v14
	v_add_nc_u32_e32 v17, -8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v13, v13, 0, 0
	v_or3_b32 v13, v13, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v16, 24, v21
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v14, v14, v20, v16
.LBB0_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_21:                               ; %.preheader27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v17
	flat_load_u8 v18, v[18:19]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v19, s11 :: v_dual_and_b32 v18, 0xffff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_21
; %bb.22:                               ; %Flow222
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_23:                               ; %Flow224
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB0_24:                               ; %Flow226
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v15, v[9:10]
	flat_load_u8 v16, v[9:10] offset:1
	flat_load_u8 v18, v[9:10] offset:2
	flat_load_u8 v19, v[9:10] offset:3
	flat_load_u8 v20, v[9:10] offset:5
	flat_load_u8 v21, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v22, v30 :: v_dual_and_b32 v15, 0xffff, v15
	s_clause 0x1
	flat_load_u8 v23, v[9:10] offset:7
	flat_load_d16_hi_u8 v22, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v16, 8, v16
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v18
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v15, v16, v15
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v16, 8, v20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v15, v15, v18, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v16, 0, v21, v16
	v_add_nc_u32_e32 v19, -8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v15, v15, 0, 0
	v_or3_b32 v15, v15, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v23
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v16, v16, v22, v18
.LBB0_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_29:                               ; %.preheader25
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v20, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v19
	flat_load_u8 v20, v[20:21]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v21, s11 :: v_dual_and_b32 v20, 0xffff, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v18, v21, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v20, v17
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_29
; %bb.30:                               ; %Flow217
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_31:                               ; %Flow219
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr19
.LBB0_32:                               ; %Flow221
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v17, v[9:10]
	flat_load_u8 v18, v[9:10] offset:1
	flat_load_u8 v20, v[9:10] offset:2
	flat_load_u8 v21, v[9:10] offset:3
	flat_load_u8 v22, v[9:10] offset:5
	flat_load_u8 v23, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v24, v30 :: v_dual_and_b32 v17, 0xffff, v17
	s_clause 0x1
	flat_load_u8 v25, v[9:10] offset:7
	flat_load_d16_hi_u8 v24, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v18, 8, v18
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v20, 16, v20
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v21, 24, v21
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v17, v18, v17
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v22
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v17, v17, v20, v21
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v23, v18
	v_add_nc_u32_e32 v21, -8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v17, v17, 0, 0
	v_or3_b32 v17, v17, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v20, 24, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v18, v18, v24, v20
.LBB0_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_37:                               ; %.preheader23
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v21
	flat_load_u8 v22, v[22:23]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v23, s11 :: v_dual_and_b32 v22, 0xffff, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow212
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_39:                               ; %Flow214
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr21
.LBB0_40:                               ; %Flow216
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v23, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v19, v[9:10]
	flat_load_u8 v20, v[9:10] offset:1
	flat_load_u8 v22, v[9:10] offset:2
	flat_load_u8 v23, v[9:10] offset:3
	flat_load_u8 v24, v[9:10] offset:5
	flat_load_u8 v25, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v26, v30 :: v_dual_and_b32 v19, 0xffff, v19
	s_clause 0x1
	flat_load_u8 v27, v[9:10] offset:7
	flat_load_d16_hi_u8 v26, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v20, 8, v20
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v22, 16, v22
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v23, 24, v23
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v19, v20, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v20, 8, v24
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v19, v19, v22, v23
	s_waitcnt vmcnt(2)
	v_or3_b32 v20, 0, v25, v20
	v_add_nc_u32_e32 v23, -8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v19, v19, 0, 0
	v_or3_b32 v19, v19, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v22, 24, v27
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v20, v20, v26, v22
.LBB0_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v23
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_48
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v23
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_45:                               ; %.preheader21
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v24, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v23
	flat_load_u8 v24, v[24:25]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v25, s11 :: v_dual_and_b32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], s0, v[24:25]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v24, v21
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_45
; %bb.46:                               ; %Flow207
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_47:                               ; %Flow209
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr23
.LBB0_48:                               ; %Flow211
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v25, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v21, v[9:10]
	flat_load_u8 v22, v[9:10] offset:1
	flat_load_u8 v24, v[9:10] offset:2
	flat_load_u8 v25, v[9:10] offset:3
	flat_load_u8 v26, v[9:10] offset:5
	flat_load_u8 v27, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v28, v30 :: v_dual_and_b32 v21, 0xffff, v21
	s_clause 0x1
	flat_load_u8 v29, v[9:10] offset:7
	flat_load_d16_hi_u8 v28, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v22, 8, v22
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v24, 16, v24
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v25, 24, v25
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v21, v22, v21
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v22, 8, v26
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v21, v21, v24, v25
	s_waitcnt vmcnt(2)
	v_or3_b32 v22, 0, v27, v22
	v_add_nc_u32_e32 v25, -8, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v21, 0, 0
	v_or3_b32 v21, v21, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v24, 24, v29
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v22, v22, v28, v24
.LBB0_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v25
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.51:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB0_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB0_53:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v26, v[9:10]
	v_mov_b32_e32 v27, s11
	v_add_nc_u32_e32 v25, -1, v25
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v26, 0xffff, v26
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, v27, v24
	v_or_b32_e32 v23, v26, v23
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_53
; %bb.54:                               ; %Flow202
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_55:                               ; %Flow204
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_56:                               ; %Flow206
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v23, v[9:10]
	flat_load_u8 v24, v[9:10] offset:1
	flat_load_u8 v25, v[9:10] offset:2
	flat_load_u8 v26, v[9:10] offset:3
	flat_load_u8 v27, v[9:10] offset:5
	flat_load_u8 v28, v[9:10] offset:4
	v_mov_b32_e32 v29, v30
	s_clause 0x1
	flat_load_u8 v34, v[9:10] offset:7
	flat_load_d16_hi_u8 v29, v[9:10] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v9, 0xffff, v23
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v10, 8, v24
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v25
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v24, 8, v27
	v_or_b32_e32 v9, v10, v9
	v_lshlrev_b32_e32 v10, 24, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v23, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v10, 0, v28, v24
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v34
	v_or3_b32 v9, v9, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v24, v10, v29, v23
	v_or3_b32 v23, v9, 0, 0
.LBB0_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v29, v33
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v29
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_64
; %bb.59:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[2:3] offset:40
	global_load_b64 v[25:26], v30, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v10, v10, v28
	v_and_b32_e32 v9, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, 24
	v_mul_hi_u32 v34, v9, 24
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v34, v10
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v26, v10, vcc_lo
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[27:28]
	s_cbranch_execz .LBB0_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s5, 0
.LBB0_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v30, s[2:3] offset:40
	global_load_b64 v[34:35], v30, s[2:3]
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v27, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v25, 24, v[34:35]
	v_and_b32_e32 v34, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v34, 24, v[10:11]
	v_mov_b32_e32 v10, v25
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[27:28]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_61
; %bb.62:                               ; %Flow199
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_63:                               ; %Flow201
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[34:35], v30, s[2:3] offset:40
	global_load_b128 v[25:28], v30, s[2:3]
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s15, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v34
	v_readfirstlane_b32 s7, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s13, s6, 24
	s_mul_i32 s14, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s17, s13, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v26, vcc_lo
	v_dual_mov_b32 v9, s15 :: v_dual_mov_b32 v10, v30
	global_store_b128 v[34:35], v[9:12], off offset:8
.LBB0_66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v9, 0, v1
	v_or_b32_e32 v10, v0, v6
	v_lshl_add_u32 v34, v31, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v10, v0
	v_lshlrev_b64 v[9:10], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v27, vcc_lo, v27, s6
	v_and_b32_e32 v34, 0x1e0, v34
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v27, v9
	v_and_or_b32 v0, 0xffffff1f, v0, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, v28, v10, vcc_lo
	s_clause 0x3
	global_store_b128 v[9:10], v[0:3], off
	global_store_b128 v[9:10], v[13:16], off offset:16
	global_store_b128 v[9:10], v[17:20], off offset:32
	global_store_b128 v[9:10], v[21:24], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_74
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v30, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v30, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v0
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[4:5]
	s_mul_i32 s7, s17, 24
	s_mul_hi_u32 s15, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v13, vcc_lo, v25, s16
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v26, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[17:18]
	s_cbranch_execz .LBB0_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s15, 0
.LBB0_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[13:14], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v30, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_69
.LBB0_70:                               ; %Flow197
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[0:1], v30, s[2:3] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[29:30], off offset:8
.LBB0_72:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v29, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[29:30], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_74:                               ; %Flow198
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s13, s13, s1
	v_add_co_u32 v0, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_75:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, -1
.LBB0_80:                               ; %Flow192
                                        ;   in Loop: Header=BB0_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_75
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[0:3], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_85
; %bb.82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v30, s[2:3] offset:40
	global_load_b64 v[9:10], v30, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v17, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v17, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v18 :: v_dual_cndmask_b32 v13, v13, v17
	v_and_b32_e32 v3, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v13, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v17, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v15, v2
	v_mov_b32_e32 v15, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, v16, v3, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[2:3], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[2:3], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_84
.LBB0_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v4, vcc_lo, v4, v31
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v32, vcc_lo
	v_add_co_u32 v7, s0, v7, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, v8, v32, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_2
; %bb.86:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr10
.LBB0_87:                               ; %Flow253
	s_and_not1_saveexec_b32 s1, s10
	s_cbranch_execz .LBB0_116
; %bb.88:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_waitcnt vmcnt(0)
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_94
; %bb.89:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[7:8], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v9, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[5:6]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s6, 0
.LBB0_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, 24, v[11:12]
	v_mov_b32_e32 v3, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[5:6]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_93:                               ; %Flow251
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s8, s7, 24
	s_mul_hi_u32 s9, s6, 24
	s_mul_i32 s10, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_96
; %bb.95:
	s_add_i32 s13, s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v12, v3
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[8:9], v[11:14], off offset:8
.LBB0_96:
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_104
; %bb.97:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s11, 0
.LBB0_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow247
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_102
; %bb.101:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow248
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s9, s9, s8
	v_add_co_u32 v0, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, -1
.LBB0_110:                              ; %Flow242
                                        ;   in Loop: Header=BB0_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_105
; %bb.111:
	global_load_b128 v[0:3], v[6:7], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_115
; %bb.112:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_116:                              ; %Flow254
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_printf_append_string_n, .Lfunc_end0-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5708
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z6kernelv              ; -- Begin function _Z6kernelv
	.globl	_Z6kernelv
	.p2align	8
	.type	_Z6kernelv,@function
_Z6kernelv:                             ; @_Z6kernelv
; %bb.0:
	v_add_nc_u16 v1, s15, 0x41
	v_mov_b32_e32 v38, 0
	v_lshlrev_b16 v0, 8, v0
	s_mov_b64 s[18:19], s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_and_b32_e32 v1, 0xff, v1
	v_cmp_ne_u32_e64 s28, 4, -1
	v_cmp_ne_u32_e64 s29, 12, -1
	v_cmp_ne_u32_e64 s33, 20, -1
	v_cmp_ne_u32_e64 s34, 28, -1
	v_or_b32_e32 v0, v0, v1
	v_add_nc_u32_e64 v43, 4, -1
	v_add_nc_u32_e64 v44, 12, -1
	v_add_nc_u32_e64 v45, 20, -1
	v_add_nc_u32_e64 v46, 28, -1
	v_dual_mov_b32 v50, 48 :: v_dual_mov_b32 v47, 0x32375644
	v_dual_mov_b32 v48, 0x31325445 :: v_dual_mov_b32 v41, 2
	v_dual_mov_b32 v49, 0x34325249 :: v_dual_mov_b32 v42, 1
	v_dual_mov_b32 v51, 0x39344453 :: v_dual_mov_b32 v36, 33
	v_mbcnt_lo_u32_b32 v52, -1, 0
	s_cmp_lg_u64 s[0:1], 0
	v_add_nc_u16 v0, v0, 0x4100
	s_mov_b64 s[24:25], src_private_base
	s_mov_b32 s20, 0
	s_cselect_b32 s24, 20, 0
	s_mov_b32 s32, 48
	s_clause 0x1
	scratch_store_b8 off, v38, off offset:40
	scratch_store_b16 off, v0, off offset:36
.LBB1_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_2 Depth 2
                                        ;       Child Loop BB1_4 Depth 3
                                        ;       Child Loop BB1_11 Depth 3
                                        ;       Child Loop BB1_19 Depth 3
                                        ;       Child Loop BB1_25 Depth 3
                                        ;       Child Loop BB1_34 Depth 3
                                        ;       Child Loop BB1_36 Depth 3
                                        ;       Child Loop BB1_39 Depth 3
                                        ;         Child Loop BB1_42 Depth 4
                                        ;         Child Loop BB1_50 Depth 4
                                        ;         Child Loop BB1_58 Depth 4
                                        ;         Child Loop BB1_66 Depth 4
                                        ;         Child Loop BB1_74 Depth 4
                                        ;         Child Loop BB1_82 Depth 4
                                        ;         Child Loop BB1_90 Depth 4
                                        ;         Child Loop BB1_98 Depth 4
                                        ;         Child Loop BB1_106 Depth 4
                                        ;         Child Loop BB1_112 Depth 4
                                        ;         Child Loop BB1_121 Depth 4
                                        ;       Child Loop BB1_129 Depth 3
                                        ;       Child Loop BB1_137 Depth 3
                                        ;       Child Loop BB1_143 Depth 3
                                        ;       Child Loop BB1_152 Depth 3
                                        ;       Child Loop BB1_156 Depth 3
                                        ;       Child Loop BB1_163 Depth 3
                                        ;       Child Loop BB1_171 Depth 3
                                        ;       Child Loop BB1_177 Depth 3
                                        ;       Child Loop BB1_186 Depth 3
                                        ;       Child Loop BB1_188 Depth 3
                                        ;       Child Loop BB1_191 Depth 3
                                        ;         Child Loop BB1_194 Depth 4
                                        ;         Child Loop BB1_202 Depth 4
                                        ;         Child Loop BB1_210 Depth 4
                                        ;         Child Loop BB1_218 Depth 4
                                        ;         Child Loop BB1_226 Depth 4
                                        ;         Child Loop BB1_234 Depth 4
                                        ;         Child Loop BB1_242 Depth 4
                                        ;         Child Loop BB1_250 Depth 4
                                        ;         Child Loop BB1_258 Depth 4
                                        ;         Child Loop BB1_264 Depth 4
                                        ;         Child Loop BB1_273 Depth 4
                                        ;       Child Loop BB1_281 Depth 3
                                        ;       Child Loop BB1_289 Depth 3
                                        ;       Child Loop BB1_295 Depth 3
                                        ;       Child Loop BB1_304 Depth 3
                                        ;       Child Loop BB1_308 Depth 3
                                        ;       Child Loop BB1_315 Depth 3
                                        ;       Child Loop BB1_323 Depth 3
                                        ;       Child Loop BB1_329 Depth 3
                                        ;       Child Loop BB1_338 Depth 3
                                        ;       Child Loop BB1_340 Depth 3
                                        ;       Child Loop BB1_343 Depth 3
                                        ;         Child Loop BB1_346 Depth 4
                                        ;         Child Loop BB1_354 Depth 4
                                        ;         Child Loop BB1_362 Depth 4
                                        ;         Child Loop BB1_370 Depth 4
                                        ;         Child Loop BB1_378 Depth 4
                                        ;         Child Loop BB1_386 Depth 4
                                        ;         Child Loop BB1_394 Depth 4
                                        ;         Child Loop BB1_402 Depth 4
                                        ;         Child Loop BB1_410 Depth 4
                                        ;         Child Loop BB1_416 Depth 4
                                        ;         Child Loop BB1_425 Depth 4
                                        ;       Child Loop BB1_433 Depth 3
                                        ;       Child Loop BB1_441 Depth 3
                                        ;       Child Loop BB1_447 Depth 3
                                        ;       Child Loop BB1_456 Depth 3
                                        ;       Child Loop BB1_460 Depth 3
                                        ;       Child Loop BB1_467 Depth 3
                                        ;       Child Loop BB1_475 Depth 3
                                        ;       Child Loop BB1_481 Depth 3
                                        ;       Child Loop BB1_490 Depth 3
                                        ;       Child Loop BB1_492 Depth 3
                                        ;       Child Loop BB1_495 Depth 3
                                        ;         Child Loop BB1_498 Depth 4
                                        ;         Child Loop BB1_506 Depth 4
                                        ;         Child Loop BB1_514 Depth 4
                                        ;         Child Loop BB1_522 Depth 4
                                        ;         Child Loop BB1_530 Depth 4
                                        ;         Child Loop BB1_538 Depth 4
                                        ;         Child Loop BB1_546 Depth 4
                                        ;         Child Loop BB1_554 Depth 4
                                        ;         Child Loop BB1_562 Depth 4
                                        ;         Child Loop BB1_568 Depth 4
                                        ;         Child Loop BB1_577 Depth 4
                                        ;       Child Loop BB1_585 Depth 3
                                        ;       Child Loop BB1_593 Depth 3
                                        ;       Child Loop BB1_599 Depth 3
                                        ;       Child Loop BB1_608 Depth 3
	v_mov_b32_e32 v53, 48
.LBB1_2:                                ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_4 Depth 3
                                        ;       Child Loop BB1_11 Depth 3
                                        ;       Child Loop BB1_19 Depth 3
                                        ;       Child Loop BB1_25 Depth 3
                                        ;       Child Loop BB1_34 Depth 3
                                        ;       Child Loop BB1_36 Depth 3
                                        ;       Child Loop BB1_39 Depth 3
                                        ;         Child Loop BB1_42 Depth 4
                                        ;         Child Loop BB1_50 Depth 4
                                        ;         Child Loop BB1_58 Depth 4
                                        ;         Child Loop BB1_66 Depth 4
                                        ;         Child Loop BB1_74 Depth 4
                                        ;         Child Loop BB1_82 Depth 4
                                        ;         Child Loop BB1_90 Depth 4
                                        ;         Child Loop BB1_98 Depth 4
                                        ;         Child Loop BB1_106 Depth 4
                                        ;         Child Loop BB1_112 Depth 4
                                        ;         Child Loop BB1_121 Depth 4
                                        ;       Child Loop BB1_129 Depth 3
                                        ;       Child Loop BB1_137 Depth 3
                                        ;       Child Loop BB1_143 Depth 3
                                        ;       Child Loop BB1_152 Depth 3
                                        ;       Child Loop BB1_156 Depth 3
                                        ;       Child Loop BB1_163 Depth 3
                                        ;       Child Loop BB1_171 Depth 3
                                        ;       Child Loop BB1_177 Depth 3
                                        ;       Child Loop BB1_186 Depth 3
                                        ;       Child Loop BB1_188 Depth 3
                                        ;       Child Loop BB1_191 Depth 3
                                        ;         Child Loop BB1_194 Depth 4
                                        ;         Child Loop BB1_202 Depth 4
                                        ;         Child Loop BB1_210 Depth 4
                                        ;         Child Loop BB1_218 Depth 4
                                        ;         Child Loop BB1_226 Depth 4
                                        ;         Child Loop BB1_234 Depth 4
                                        ;         Child Loop BB1_242 Depth 4
                                        ;         Child Loop BB1_250 Depth 4
                                        ;         Child Loop BB1_258 Depth 4
                                        ;         Child Loop BB1_264 Depth 4
                                        ;         Child Loop BB1_273 Depth 4
                                        ;       Child Loop BB1_281 Depth 3
                                        ;       Child Loop BB1_289 Depth 3
                                        ;       Child Loop BB1_295 Depth 3
                                        ;       Child Loop BB1_304 Depth 3
                                        ;       Child Loop BB1_308 Depth 3
                                        ;       Child Loop BB1_315 Depth 3
                                        ;       Child Loop BB1_323 Depth 3
                                        ;       Child Loop BB1_329 Depth 3
                                        ;       Child Loop BB1_338 Depth 3
                                        ;       Child Loop BB1_340 Depth 3
                                        ;       Child Loop BB1_343 Depth 3
                                        ;         Child Loop BB1_346 Depth 4
                                        ;         Child Loop BB1_354 Depth 4
                                        ;         Child Loop BB1_362 Depth 4
                                        ;         Child Loop BB1_370 Depth 4
                                        ;         Child Loop BB1_378 Depth 4
                                        ;         Child Loop BB1_386 Depth 4
                                        ;         Child Loop BB1_394 Depth 4
                                        ;         Child Loop BB1_402 Depth 4
                                        ;         Child Loop BB1_410 Depth 4
                                        ;         Child Loop BB1_416 Depth 4
                                        ;         Child Loop BB1_425 Depth 4
                                        ;       Child Loop BB1_433 Depth 3
                                        ;       Child Loop BB1_441 Depth 3
                                        ;       Child Loop BB1_447 Depth 3
                                        ;       Child Loop BB1_456 Depth 3
                                        ;       Child Loop BB1_460 Depth 3
                                        ;       Child Loop BB1_467 Depth 3
                                        ;       Child Loop BB1_475 Depth 3
                                        ;       Child Loop BB1_481 Depth 3
                                        ;       Child Loop BB1_490 Depth 3
                                        ;       Child Loop BB1_492 Depth 3
                                        ;       Child Loop BB1_495 Depth 3
                                        ;         Child Loop BB1_498 Depth 4
                                        ;         Child Loop BB1_506 Depth 4
                                        ;         Child Loop BB1_514 Depth 4
                                        ;         Child Loop BB1_522 Depth 4
                                        ;         Child Loop BB1_530 Depth 4
                                        ;         Child Loop BB1_538 Depth 4
                                        ;         Child Loop BB1_546 Depth 4
                                        ;         Child Loop BB1_554 Depth 4
                                        ;         Child Loop BB1_562 Depth 4
                                        ;         Child Loop BB1_568 Depth 4
                                        ;         Child Loop BB1_577 Depth 4
                                        ;       Child Loop BB1_585 Depth 3
                                        ;       Child Loop BB1_593 Depth 3
                                        ;       Child Loop BB1_599 Depth 3
                                        ;       Child Loop BB1_608 Depth 3
	scratch_load_u8 v0, off, off offset:36
	s_mov_b32 s35, exec_lo
	s_clause 0x9
	scratch_store_b8 off, v50, off offset:38
	scratch_store_b8 off, v53, off offset:39
	scratch_store_b8 off, v38, off offset:8
	scratch_store_b32 off, v47, off offset:4
	scratch_store_b8 off, v38, off offset:16
	scratch_store_b32 off, v48, off offset:12
	scratch_store_b8 off, v38, off offset:24
	scratch_store_b32 off, v49, off offset:20
	scratch_store_b8 off, v38, off offset:32
	scratch_store_b32 off, v51, off offset:28
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0x44, v0
	s_cbranch_execz .LBB1_154
; %bb.3:                                ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	v_mov_b32_e32 v0, 0x44
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_4:                                ; %.lr.ph.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=3
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 4
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_6:                                ; %Flow1117
                                        ;   in Loop: Header=BB1_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_4
; %bb.7:                                ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_154
; %bb.8:                                ;   in Loop: Header=BB1_2 Depth=2
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_14
; %bb.9:                                ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_13
; %bb.10:                               ; %.preheader3.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_11:                               ; %.preheader3.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_11
; %bb.12:                               ; %Flow1111
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_13:                               ; %Flow1113
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_14:                               ; %.loopexit4.i.i.i.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_16
; %bb.15:                               ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_16:                               ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_24
; %bb.17:                               ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_20
; %bb.18:                               ; %.preheader1.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_19:                               ; %.preheader1.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_19
.LBB1_20:                               ; %Flow1109
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_22
; %bb.21:                               ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_22:                               ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_24
; %bb.23:                               ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_24:                               ; %Flow1110
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_25:                               ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_27
; %bb.26:                               ;   in Loop: Header=BB1_25 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_27:                               ;   in Loop: Header=BB1_25 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_29
; %bb.28:                               ;   in Loop: Header=BB1_25 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_30
.LBB1_29:                               ;   in Loop: Header=BB1_25 Depth=3
	s_mov_b32 s1, -1
.LBB1_30:                               ; %Flow1104
                                        ;   in Loop: Header=BB1_25 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_25
; %bb.31:                               ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_35
; %bb.32:                               ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_35
; %bb.33:                               ; %.preheader.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_34:                               ; %.preheader.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_34
.LBB1_35:                               ; %__ockl_printf_begin.exit.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v43
	s_mov_b32 s0, 0
.LBB1_36:                               ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_36
; %bb.37:                               ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccz .LBB1_124
; %bb.38:                               ;   in Loop: Header=BB1_2 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 4
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 4
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_39:                               ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_42 Depth 4
                                        ;         Child Loop BB1_50 Depth 4
                                        ;         Child Loop BB1_58 Depth 4
                                        ;         Child Loop BB1_66 Depth 4
                                        ;         Child Loop BB1_74 Depth 4
                                        ;         Child Loop BB1_82 Depth 4
                                        ;         Child Loop BB1_90 Depth 4
                                        ;         Child Loop BB1_98 Depth 4
                                        ;         Child Loop BB1_106 Depth 4
                                        ;         Child Loop BB1_112 Depth 4
                                        ;         Child Loop BB1_121 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_45
; %bb.40:                               ;   in Loop: Header=BB1_39 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_44
; %bb.41:                               ; %.preheader31.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_42:                               ; %.preheader31.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_42
; %bb.43:                               ; %Flow1076
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_44:                               ; %Flow1078
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_45:                               ; %Flow1080
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_47
; %bb.46:                               ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_47:                               ; %.loopexit32.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_53
; %bb.48:                               ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_52
; %bb.49:                               ; %.preheader29.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_50:                               ; %.preheader29.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_50
; %bb.51:                               ; %Flow1071
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_52:                               ; %Flow1073
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_53:                               ; %Flow1075
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_55
; %bb.54:                               ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_55:                               ; %.loopexit30.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_61
; %bb.56:                               ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_60
; %bb.57:                               ; %.preheader27.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_58:                               ; %.preheader27.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_58
; %bb.59:                               ; %Flow1066
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_60:                               ; %Flow1068
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_61:                               ; %Flow1070
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_63
; %bb.62:                               ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_63:                               ; %.loopexit28.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_69
; %bb.64:                               ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_68
; %bb.65:                               ; %.preheader25.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_66:                               ; %.preheader25.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_66
; %bb.67:                               ; %Flow1061
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_68:                               ; %Flow1063
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_69:                               ; %Flow1065
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_71
; %bb.70:                               ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_71:                               ; %.loopexit26.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_77
; %bb.72:                               ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_76
; %bb.73:                               ; %.preheader23.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_74:                               ; %.preheader23.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_74
; %bb.75:                               ; %Flow1056
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_76:                               ; %Flow1058
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_77:                               ; %Flow1060
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_79
; %bb.78:                               ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_79:                               ; %.loopexit24.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_85
; %bb.80:                               ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_84
; %bb.81:                               ; %.preheader21.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_82:                               ; %.preheader21.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_82
; %bb.83:                               ; %Flow1051
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_84:                               ; %Flow1053
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_85:                               ; %Flow1055
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_87
; %bb.86:                               ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_87:                               ; %.loopexit22.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_93
; %bb.88:                               ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_92
; %bb.89:                               ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_90:                               ; %.preheader.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_90
; %bb.91:                               ; %Flow1046
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_92:                               ; %Flow1048
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_93:                               ; %Flow1050
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_95
; %bb.94:                               ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_95:                               ; %.loopexit.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_101
; %bb.96:                               ;   in Loop: Header=BB1_39 Depth=3
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_100
; %bb.97:                               ; %.preheader3.i.i19.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_mov_b32 s3, 0
.LBB1_98:                               ; %.preheader3.i.i19.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_98
; %bb.99:                               ; %Flow1043
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_100:                              ; %Flow1045
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_101:                              ; %.loopexit4.i.i14.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_103
; %bb.102:                              ;   in Loop: Header=BB1_39 Depth=3
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_103:                              ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_111
; %bb.104:                              ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_107
; %bb.105:                              ; %.preheader1.i.i17.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_mov_b32 s9, 0
.LBB1_106:                              ; %.preheader1.i.i17.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_106
.LBB1_107:                              ; %Flow1041
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_109
; %bb.108:                              ;   in Loop: Header=BB1_39 Depth=3
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_109:                              ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_111
; %bb.110:                              ;   in Loop: Header=BB1_39 Depth=3
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_111:                              ; %Flow1042
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_112:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_114
; %bb.113:                              ;   in Loop: Header=BB1_112 Depth=4
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_114:                              ;   in Loop: Header=BB1_112 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_116
; %bb.115:                              ;   in Loop: Header=BB1_112 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_117
.LBB1_116:                              ;   in Loop: Header=BB1_112 Depth=4
	s_mov_b32 s1, -1
.LBB1_117:                              ; %Flow1036
                                        ;   in Loop: Header=BB1_112 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_112
; %bb.118:                              ;   in Loop: Header=BB1_39 Depth=3
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_122
; %bb.119:                              ;   in Loop: Header=BB1_39 Depth=3
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_122
; %bb.120:                              ; %.preheader.i.i16.i.i.preheader
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_mov_b32 s0, 0
.LBB1_121:                              ; %.preheader.i.i16.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_39 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_121
.LBB1_122:                              ; %__ockl_hostcall_preview.exit20.i.i
                                        ;   in Loop: Header=BB1_39 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_39
; %bb.123:                              ; %Flow1081
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_125
.LBB1_124:                              ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, -1
.LBB1_125:                              ; %Flow1098
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_154
; %bb.126:                              ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_132
; %bb.127:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_131
; %bb.128:                              ; %.preheader3.i.i.i41.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_129:                              ; %.preheader3.i.i.i41.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_129
; %bb.130:                              ; %Flow1094
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_131:                              ; %Flow1096
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_132:                              ; %.loopexit4.i.i.i36.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_134
; %bb.133:                              ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_134:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_142
; %bb.135:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_138
; %bb.136:                              ; %.preheader1.i.i.i39.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_137:                              ; %.preheader1.i.i.i39.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_137
.LBB1_138:                              ; %Flow1092
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_140
; %bb.139:                              ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_140:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_142
; %bb.141:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_142:                              ; %Flow1093
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_143:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_145
; %bb.144:                              ;   in Loop: Header=BB1_143 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_145:                              ;   in Loop: Header=BB1_143 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_147
; %bb.146:                              ;   in Loop: Header=BB1_143 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_148
.LBB1_147:                              ;   in Loop: Header=BB1_143 Depth=3
	s_mov_b32 s1, -1
.LBB1_148:                              ; %Flow1087
                                        ;   in Loop: Header=BB1_143 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_143
; %bb.149:                              ;   in Loop: Header=BB1_2 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_153
; %bb.150:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_153
; %bb.151:                              ; %.preheader.i.i.i38.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_152:                              ; %.preheader.i.i.i38.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_152
.LBB1_153:                              ; %Flow1085
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_154:                              ; %Flow1118
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s35
	s_clause 0x1
	scratch_load_u8 v0, off, off offset:36
	scratch_load_u8 v1, off, off offset:12
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v0, v1
	s_cbranch_execz .LBB1_306
; %bb.155:                              ; %.lr.ph218.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_156:                              ; %.lr.ph218.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_158
; %bb.157:                              ;   in Loop: Header=BB1_156 Depth=3
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 12
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_158:                              ; %Flow1030
                                        ;   in Loop: Header=BB1_156 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_156
; %bb.159:                              ; %loop.exit.guard767
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_306
; %bb.160:                              ;   in Loop: Header=BB1_2 Depth=2
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_166
; %bb.161:                              ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_165
; %bb.162:                              ; %.preheader3.i.i.i48.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_163:                              ; %.preheader3.i.i.i48.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_163
; %bb.164:                              ; %Flow1024
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_165:                              ; %Flow1026
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_166:                              ; %.loopexit4.i.i.i42.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_168
; %bb.167:                              ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_168:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_176
; %bb.169:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_172
; %bb.170:                              ; %.preheader1.i.i.i46.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_171:                              ; %.preheader1.i.i.i46.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_171
.LBB1_172:                              ; %Flow1022
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_174
; %bb.173:                              ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_174:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_176
; %bb.175:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_176:                              ; %Flow1023
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_177:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_179
; %bb.178:                              ;   in Loop: Header=BB1_177 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_179:                              ;   in Loop: Header=BB1_177 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_181
; %bb.180:                              ;   in Loop: Header=BB1_177 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_182
.LBB1_181:                              ;   in Loop: Header=BB1_177 Depth=3
	s_mov_b32 s1, -1
.LBB1_182:                              ; %Flow1017
                                        ;   in Loop: Header=BB1_177 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_177
; %bb.183:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_187
; %bb.184:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_187
; %bb.185:                              ; %.preheader.i.i.i45.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_186:                              ; %.preheader.i.i.i45.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_186
.LBB1_187:                              ; %__ockl_printf_begin.exit49.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v44
	s_mov_b32 s0, 0
.LBB1_188:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_188
; %bb.189:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccz .LBB1_276
; %bb.190:                              ;   in Loop: Header=BB1_2 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 12
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 12
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_191:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_194 Depth 4
                                        ;         Child Loop BB1_202 Depth 4
                                        ;         Child Loop BB1_210 Depth 4
                                        ;         Child Loop BB1_218 Depth 4
                                        ;         Child Loop BB1_226 Depth 4
                                        ;         Child Loop BB1_234 Depth 4
                                        ;         Child Loop BB1_242 Depth 4
                                        ;         Child Loop BB1_250 Depth 4
                                        ;         Child Loop BB1_258 Depth 4
                                        ;         Child Loop BB1_264 Depth 4
                                        ;         Child Loop BB1_273 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_197
; %bb.192:                              ;   in Loop: Header=BB1_191 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_196
; %bb.193:                              ; %.preheader31.i50.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_194:                              ; %.preheader31.i50.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_194
; %bb.195:                              ; %Flow989
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_196:                              ; %Flow991
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_197:                              ; %Flow993
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_199
; %bb.198:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_199:                              ; %.loopexit32.i51.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_205
; %bb.200:                              ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_204
; %bb.201:                              ; %.preheader29.i52.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_202:                              ; %.preheader29.i52.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_202
; %bb.203:                              ; %Flow984
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_204:                              ; %Flow986
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_205:                              ; %Flow988
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_207
; %bb.206:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_207:                              ; %.loopexit30.i53.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_213
; %bb.208:                              ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_212
; %bb.209:                              ; %.preheader27.i54.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_210:                              ; %.preheader27.i54.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_210
; %bb.211:                              ; %Flow979
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_212:                              ; %Flow981
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_213:                              ; %Flow983
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_215
; %bb.214:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_215:                              ; %.loopexit28.i55.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_221
; %bb.216:                              ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_220
; %bb.217:                              ; %.preheader25.i56.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_218:                              ; %.preheader25.i56.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_218
; %bb.219:                              ; %Flow974
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_220:                              ; %Flow976
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_221:                              ; %Flow978
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_223
; %bb.222:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_223:                              ; %.loopexit26.i57.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_229
; %bb.224:                              ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_228
; %bb.225:                              ; %.preheader23.i58.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_226:                              ; %.preheader23.i58.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_226
; %bb.227:                              ; %Flow969
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_228:                              ; %Flow971
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_229:                              ; %Flow973
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_231
; %bb.230:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_231:                              ; %.loopexit24.i59.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_237
; %bb.232:                              ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_236
; %bb.233:                              ; %.preheader21.i60.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_234:                              ; %.preheader21.i60.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_234
; %bb.235:                              ; %Flow964
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_236:                              ; %Flow966
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_237:                              ; %Flow968
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_239
; %bb.238:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_239:                              ; %.loopexit22.i61.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_245
; %bb.240:                              ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_244
; %bb.241:                              ; %.preheader.i62.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_242:                              ; %.preheader.i62.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_242
; %bb.243:                              ; %Flow959
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_244:                              ; %Flow961
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_245:                              ; %Flow963
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_247
; %bb.246:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_247:                              ; %.loopexit.i63.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_253
; %bb.248:                              ;   in Loop: Header=BB1_191 Depth=3
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_252
; %bb.249:                              ; %.preheader3.i.i19.i70.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_mov_b32 s3, 0
.LBB1_250:                              ; %.preheader3.i.i19.i70.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_250
; %bb.251:                              ; %Flow956
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_252:                              ; %Flow958
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_253:                              ; %.loopexit4.i.i14.i64.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_255
; %bb.254:                              ;   in Loop: Header=BB1_191 Depth=3
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_255:                              ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_263
; %bb.256:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_259
; %bb.257:                              ; %.preheader1.i.i17.i68.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_mov_b32 s9, 0
.LBB1_258:                              ; %.preheader1.i.i17.i68.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_258
.LBB1_259:                              ; %Flow954
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_261
; %bb.260:                              ;   in Loop: Header=BB1_191 Depth=3
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_261:                              ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_263
; %bb.262:                              ;   in Loop: Header=BB1_191 Depth=3
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_263:                              ; %Flow955
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_264:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_266
; %bb.265:                              ;   in Loop: Header=BB1_264 Depth=4
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_266:                              ;   in Loop: Header=BB1_264 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_268
; %bb.267:                              ;   in Loop: Header=BB1_264 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_269
.LBB1_268:                              ;   in Loop: Header=BB1_264 Depth=4
	s_mov_b32 s1, -1
.LBB1_269:                              ; %Flow949
                                        ;   in Loop: Header=BB1_264 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_264
; %bb.270:                              ;   in Loop: Header=BB1_191 Depth=3
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_274
; %bb.271:                              ;   in Loop: Header=BB1_191 Depth=3
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_274
; %bb.272:                              ; %.preheader.i.i16.i67.i.preheader
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_mov_b32 s0, 0
.LBB1_273:                              ; %.preheader.i.i16.i67.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_191 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_273
.LBB1_274:                              ; %__ockl_hostcall_preview.exit20.i66.i
                                        ;   in Loop: Header=BB1_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_191
; %bb.275:                              ; %Flow994
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_277
.LBB1_276:                              ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, -1
.LBB1_277:                              ; %Flow1011
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_306
; %bb.278:                              ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_284
; %bb.279:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_283
; %bb.280:                              ; %.preheader3.i.i.i77.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_281:                              ; %.preheader3.i.i.i77.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_281
; %bb.282:                              ; %Flow1007
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_283:                              ; %Flow1009
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_284:                              ; %.loopexit4.i.i.i71.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_286
; %bb.285:                              ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_286:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_294
; %bb.287:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_290
; %bb.288:                              ; %.preheader1.i.i.i75.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_289:                              ; %.preheader1.i.i.i75.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_289
.LBB1_290:                              ; %Flow1005
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_292
; %bb.291:                              ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_292:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_294
; %bb.293:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_294:                              ; %Flow1006
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_295:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_297
; %bb.296:                              ;   in Loop: Header=BB1_295 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_297:                              ;   in Loop: Header=BB1_295 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_299
; %bb.298:                              ;   in Loop: Header=BB1_295 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_300
.LBB1_299:                              ;   in Loop: Header=BB1_295 Depth=3
	s_mov_b32 s1, -1
.LBB1_300:                              ; %Flow1000
                                        ;   in Loop: Header=BB1_295 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_295
; %bb.301:                              ;   in Loop: Header=BB1_2 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_305
; %bb.302:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_305
; %bb.303:                              ; %.preheader.i.i.i74.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_304:                              ; %.preheader.i.i.i74.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_304
.LBB1_305:                              ; %Flow998
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_306:                              ; %Flow1031
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s35
	s_clause 0x1
	scratch_load_u8 v0, off, off offset:36
	scratch_load_u8 v1, off, off offset:20
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v0, v1
	s_cbranch_execz .LBB1_458
; %bb.307:                              ; %.lr.ph221.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_308:                              ; %.lr.ph221.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_310
; %bb.309:                              ;   in Loop: Header=BB1_308 Depth=3
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 20
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_310:                              ; %Flow943
                                        ;   in Loop: Header=BB1_308 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_308
; %bb.311:                              ; %loop.exit.guard769
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_458
; %bb.312:                              ;   in Loop: Header=BB1_2 Depth=2
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_318
; %bb.313:                              ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_317
; %bb.314:                              ; %.preheader3.i.i.i85.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_315:                              ; %.preheader3.i.i.i85.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_315
; %bb.316:                              ; %Flow937
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_317:                              ; %Flow939
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_318:                              ; %.loopexit4.i.i.i79.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_320
; %bb.319:                              ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_320:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_328
; %bb.321:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_324
; %bb.322:                              ; %.preheader1.i.i.i83.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_323:                              ; %.preheader1.i.i.i83.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_323
.LBB1_324:                              ; %Flow935
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_326
; %bb.325:                              ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_326:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_328
; %bb.327:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_328:                              ; %Flow936
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_329:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_331
; %bb.330:                              ;   in Loop: Header=BB1_329 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_331:                              ;   in Loop: Header=BB1_329 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_333
; %bb.332:                              ;   in Loop: Header=BB1_329 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_334
.LBB1_333:                              ;   in Loop: Header=BB1_329 Depth=3
	s_mov_b32 s1, -1
.LBB1_334:                              ; %Flow930
                                        ;   in Loop: Header=BB1_329 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_329
; %bb.335:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_339
; %bb.336:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_339
; %bb.337:                              ; %.preheader.i.i.i82.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_338:                              ; %.preheader.i.i.i82.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_338
.LBB1_339:                              ; %__ockl_printf_begin.exit86.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v45
	s_mov_b32 s0, 0
.LBB1_340:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_340
; %bb.341:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccz .LBB1_428
; %bb.342:                              ;   in Loop: Header=BB1_2 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 20
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 20
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_343:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_346 Depth 4
                                        ;         Child Loop BB1_354 Depth 4
                                        ;         Child Loop BB1_362 Depth 4
                                        ;         Child Loop BB1_370 Depth 4
                                        ;         Child Loop BB1_378 Depth 4
                                        ;         Child Loop BB1_386 Depth 4
                                        ;         Child Loop BB1_394 Depth 4
                                        ;         Child Loop BB1_402 Depth 4
                                        ;         Child Loop BB1_410 Depth 4
                                        ;         Child Loop BB1_416 Depth 4
                                        ;         Child Loop BB1_425 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_349
; %bb.344:                              ;   in Loop: Header=BB1_343 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_348
; %bb.345:                              ; %.preheader31.i87.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_346:                              ; %.preheader31.i87.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_346
; %bb.347:                              ; %Flow902
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_348:                              ; %Flow904
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_349:                              ; %Flow906
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_351
; %bb.350:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_351:                              ; %.loopexit32.i88.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_357
; %bb.352:                              ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_356
; %bb.353:                              ; %.preheader29.i89.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_354:                              ; %.preheader29.i89.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_354
; %bb.355:                              ; %Flow897
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_356:                              ; %Flow899
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_357:                              ; %Flow901
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_359
; %bb.358:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_359:                              ; %.loopexit30.i90.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_365
; %bb.360:                              ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_364
; %bb.361:                              ; %.preheader27.i91.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_362:                              ; %.preheader27.i91.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_362
; %bb.363:                              ; %Flow892
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_364:                              ; %Flow894
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_365:                              ; %Flow896
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_367
; %bb.366:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_367:                              ; %.loopexit28.i92.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_373
; %bb.368:                              ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_372
; %bb.369:                              ; %.preheader25.i93.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_370:                              ; %.preheader25.i93.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_370
; %bb.371:                              ; %Flow887
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_372:                              ; %Flow889
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_373:                              ; %Flow891
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_375
; %bb.374:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_375:                              ; %.loopexit26.i94.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_381
; %bb.376:                              ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_380
; %bb.377:                              ; %.preheader23.i95.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_378:                              ; %.preheader23.i95.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_378
; %bb.379:                              ; %Flow882
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_380:                              ; %Flow884
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_381:                              ; %Flow886
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_383
; %bb.382:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_383:                              ; %.loopexit24.i96.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_389
; %bb.384:                              ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_388
; %bb.385:                              ; %.preheader21.i97.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_386:                              ; %.preheader21.i97.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_386
; %bb.387:                              ; %Flow877
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_388:                              ; %Flow879
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_389:                              ; %Flow881
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_391
; %bb.390:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_391:                              ; %.loopexit22.i98.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_397
; %bb.392:                              ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_396
; %bb.393:                              ; %.preheader.i99.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_394:                              ; %.preheader.i99.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_394
; %bb.395:                              ; %Flow872
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_396:                              ; %Flow874
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_397:                              ; %Flow876
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_399
; %bb.398:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_399:                              ; %.loopexit.i100.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_405
; %bb.400:                              ;   in Loop: Header=BB1_343 Depth=3
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_404
; %bb.401:                              ; %.preheader3.i.i19.i107.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_mov_b32 s3, 0
.LBB1_402:                              ; %.preheader3.i.i19.i107.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_402
; %bb.403:                              ; %Flow869
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_404:                              ; %Flow871
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_405:                              ; %.loopexit4.i.i14.i101.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_407
; %bb.406:                              ;   in Loop: Header=BB1_343 Depth=3
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_407:                              ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_415
; %bb.408:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_411
; %bb.409:                              ; %.preheader1.i.i17.i105.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_mov_b32 s9, 0
.LBB1_410:                              ; %.preheader1.i.i17.i105.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_410
.LBB1_411:                              ; %Flow867
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_413
; %bb.412:                              ;   in Loop: Header=BB1_343 Depth=3
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_413:                              ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_415
; %bb.414:                              ;   in Loop: Header=BB1_343 Depth=3
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_415:                              ; %Flow868
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_416:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_418
; %bb.417:                              ;   in Loop: Header=BB1_416 Depth=4
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_418:                              ;   in Loop: Header=BB1_416 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_420
; %bb.419:                              ;   in Loop: Header=BB1_416 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_421
.LBB1_420:                              ;   in Loop: Header=BB1_416 Depth=4
	s_mov_b32 s1, -1
.LBB1_421:                              ; %Flow862
                                        ;   in Loop: Header=BB1_416 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_416
; %bb.422:                              ;   in Loop: Header=BB1_343 Depth=3
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_426
; %bb.423:                              ;   in Loop: Header=BB1_343 Depth=3
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_426
; %bb.424:                              ; %.preheader.i.i16.i104.i.preheader
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_mov_b32 s0, 0
.LBB1_425:                              ; %.preheader.i.i16.i104.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_343 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_425
.LBB1_426:                              ; %__ockl_hostcall_preview.exit20.i103.i
                                        ;   in Loop: Header=BB1_343 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_343
; %bb.427:                              ; %Flow907
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_429
.LBB1_428:                              ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, -1
.LBB1_429:                              ; %Flow924
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_458
; %bb.430:                              ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_436
; %bb.431:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_435
; %bb.432:                              ; %.preheader3.i.i.i114.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_433:                              ; %.preheader3.i.i.i114.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_433
; %bb.434:                              ; %Flow920
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_435:                              ; %Flow922
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_436:                              ; %.loopexit4.i.i.i108.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_438
; %bb.437:                              ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_438:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_446
; %bb.439:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_442
; %bb.440:                              ; %.preheader1.i.i.i112.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_441:                              ; %.preheader1.i.i.i112.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_441
.LBB1_442:                              ; %Flow918
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_444
; %bb.443:                              ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_444:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_446
; %bb.445:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_446:                              ; %Flow919
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_447:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_449
; %bb.448:                              ;   in Loop: Header=BB1_447 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_449:                              ;   in Loop: Header=BB1_447 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_451
; %bb.450:                              ;   in Loop: Header=BB1_447 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_452
.LBB1_451:                              ;   in Loop: Header=BB1_447 Depth=3
	s_mov_b32 s1, -1
.LBB1_452:                              ; %Flow913
                                        ;   in Loop: Header=BB1_447 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_447
; %bb.453:                              ;   in Loop: Header=BB1_2 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_457
; %bb.454:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_457
; %bb.455:                              ; %.preheader.i.i.i111.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_456:                              ; %.preheader.i.i.i111.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_456
.LBB1_457:                              ; %Flow911
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_458:                              ; %Flow944
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s35
	s_clause 0x1
	scratch_load_u8 v0, off, off offset:36
	scratch_load_u8 v1, off, off offset:28
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v0, v1
	s_cbranch_execz .LBB1_610
; %bb.459:                              ; %.lr.ph224.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_460:                              ; %.lr.ph224.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_462
; %bb.461:                              ;   in Loop: Header=BB1_460 Depth=3
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 28
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_462:                              ; %Flow856
                                        ;   in Loop: Header=BB1_460 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_460
; %bb.463:                              ; %loop.exit.guard771
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_610
; %bb.464:                              ;   in Loop: Header=BB1_2 Depth=2
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_470
; %bb.465:                              ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_469
; %bb.466:                              ; %.preheader3.i.i.i122.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_467:                              ; %.preheader3.i.i.i122.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_467
; %bb.468:                              ; %Flow850
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_469:                              ; %Flow852
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_470:                              ; %.loopexit4.i.i.i116.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_472
; %bb.471:                              ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_472:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_480
; %bb.473:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_476
; %bb.474:                              ; %.preheader1.i.i.i120.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_475:                              ; %.preheader1.i.i.i120.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_475
.LBB1_476:                              ; %Flow848
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_478
; %bb.477:                              ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_478:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_480
; %bb.479:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_480:                              ; %Flow849
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_481:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_483
; %bb.482:                              ;   in Loop: Header=BB1_481 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_483:                              ;   in Loop: Header=BB1_481 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_485
; %bb.484:                              ;   in Loop: Header=BB1_481 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_486
.LBB1_485:                              ;   in Loop: Header=BB1_481 Depth=3
	s_mov_b32 s1, -1
.LBB1_486:                              ; %Flow843
                                        ;   in Loop: Header=BB1_481 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_481
; %bb.487:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_491
; %bb.488:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_491
; %bb.489:                              ; %.preheader.i.i.i119.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_490:                              ; %.preheader.i.i.i119.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_490
.LBB1_491:                              ; %__ockl_printf_begin.exit123.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v46
	s_mov_b32 s0, 0
.LBB1_492:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_492
; %bb.493:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s34
	s_cbranch_vccz .LBB1_580
; %bb.494:                              ;   in Loop: Header=BB1_2 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 28
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 28
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_495:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_498 Depth 4
                                        ;         Child Loop BB1_506 Depth 4
                                        ;         Child Loop BB1_514 Depth 4
                                        ;         Child Loop BB1_522 Depth 4
                                        ;         Child Loop BB1_530 Depth 4
                                        ;         Child Loop BB1_538 Depth 4
                                        ;         Child Loop BB1_546 Depth 4
                                        ;         Child Loop BB1_554 Depth 4
                                        ;         Child Loop BB1_562 Depth 4
                                        ;         Child Loop BB1_568 Depth 4
                                        ;         Child Loop BB1_577 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_501
; %bb.496:                              ;   in Loop: Header=BB1_495 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_500
; %bb.497:                              ; %.preheader31.i124.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_498:                              ; %.preheader31.i124.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_498
; %bb.499:                              ; %Flow815
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_500:                              ; %Flow817
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_501:                              ; %Flow819
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_503
; %bb.502:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_503:                              ; %.loopexit32.i125.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_509
; %bb.504:                              ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_508
; %bb.505:                              ; %.preheader29.i126.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_506:                              ; %.preheader29.i126.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_506
; %bb.507:                              ; %Flow810
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_508:                              ; %Flow812
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_509:                              ; %Flow814
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_511
; %bb.510:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_511:                              ; %.loopexit30.i127.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_517
; %bb.512:                              ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_516
; %bb.513:                              ; %.preheader27.i128.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_514:                              ; %.preheader27.i128.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_514
; %bb.515:                              ; %Flow805
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_516:                              ; %Flow807
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_517:                              ; %Flow809
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_519
; %bb.518:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_519:                              ; %.loopexit28.i129.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_525
; %bb.520:                              ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_524
; %bb.521:                              ; %.preheader25.i130.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_522:                              ; %.preheader25.i130.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_522
; %bb.523:                              ; %Flow800
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_524:                              ; %Flow802
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_525:                              ; %Flow804
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_527
; %bb.526:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_527:                              ; %.loopexit26.i131.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_533
; %bb.528:                              ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_532
; %bb.529:                              ; %.preheader23.i132.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_530:                              ; %.preheader23.i132.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_530
; %bb.531:                              ; %Flow795
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_532:                              ; %Flow797
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_533:                              ; %Flow799
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_535
; %bb.534:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_535:                              ; %.loopexit24.i133.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_541
; %bb.536:                              ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_540
; %bb.537:                              ; %.preheader21.i134.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_538:                              ; %.preheader21.i134.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_538
; %bb.539:                              ; %Flow790
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_540:                              ; %Flow792
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_541:                              ; %Flow794
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_543
; %bb.542:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_543:                              ; %.loopexit22.i135.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_549
; %bb.544:                              ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_548
; %bb.545:                              ; %.preheader.i136.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_546:                              ; %.preheader.i136.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_546
; %bb.547:                              ; %Flow785
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_548:                              ; %Flow787
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_549:                              ; %Flow789
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_551
; %bb.550:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_551:                              ; %.loopexit.i137.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_557
; %bb.552:                              ;   in Loop: Header=BB1_495 Depth=3
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_556
; %bb.553:                              ; %.preheader3.i.i19.i144.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_mov_b32 s3, 0
.LBB1_554:                              ; %.preheader3.i.i19.i144.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_554
; %bb.555:                              ; %Flow782
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_556:                              ; %Flow784
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_557:                              ; %.loopexit4.i.i14.i138.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_559
; %bb.558:                              ;   in Loop: Header=BB1_495 Depth=3
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_559:                              ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_567
; %bb.560:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_563
; %bb.561:                              ; %.preheader1.i.i17.i142.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_mov_b32 s9, 0
.LBB1_562:                              ; %.preheader1.i.i17.i142.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_562
.LBB1_563:                              ; %Flow780
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_565
; %bb.564:                              ;   in Loop: Header=BB1_495 Depth=3
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_565:                              ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_567
; %bb.566:                              ;   in Loop: Header=BB1_495 Depth=3
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_567:                              ; %Flow781
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_568:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_570
; %bb.569:                              ;   in Loop: Header=BB1_568 Depth=4
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_570:                              ;   in Loop: Header=BB1_568 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_572
; %bb.571:                              ;   in Loop: Header=BB1_568 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_573
.LBB1_572:                              ;   in Loop: Header=BB1_568 Depth=4
	s_mov_b32 s1, -1
.LBB1_573:                              ; %Flow775
                                        ;   in Loop: Header=BB1_568 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_568
; %bb.574:                              ;   in Loop: Header=BB1_495 Depth=3
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_578
; %bb.575:                              ;   in Loop: Header=BB1_495 Depth=3
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_578
; %bb.576:                              ; %.preheader.i.i16.i141.i.preheader
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_mov_b32 s0, 0
.LBB1_577:                              ; %.preheader.i.i16.i141.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_495 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_577
.LBB1_578:                              ; %__ockl_hostcall_preview.exit20.i140.i
                                        ;   in Loop: Header=BB1_495 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_495
; %bb.579:                              ; %Flow820
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_581
.LBB1_580:                              ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, -1
.LBB1_581:                              ; %Flow837
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_610
; %bb.582:                              ;   in Loop: Header=BB1_2 Depth=2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v52 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_588
; %bb.583:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_587
; %bb.584:                              ; %.preheader3.i.i.i151.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s3, 0
.LBB1_585:                              ; %.preheader3.i.i.i151.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_585
; %bb.586:                              ; %Flow833
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_587:                              ; %Flow835
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_588:                              ; %.loopexit4.i.i.i145.i
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_590
; %bb.589:                              ;   in Loop: Header=BB1_2 Depth=2
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_590:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_598
; %bb.591:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_594
; %bb.592:                              ; %.preheader1.i.i.i149.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s8, 0
.LBB1_593:                              ; %.preheader1.i.i.i149.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_593
.LBB1_594:                              ; %Flow831
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_596
; %bb.595:                              ;   in Loop: Header=BB1_2 Depth=2
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_596:                              ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_598
; %bb.597:                              ;   in Loop: Header=BB1_2 Depth=2
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_598:                              ; %Flow832
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_599:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_601
; %bb.600:                              ;   in Loop: Header=BB1_599 Depth=3
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_601:                              ;   in Loop: Header=BB1_599 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_603
; %bb.602:                              ;   in Loop: Header=BB1_599 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_604
.LBB1_603:                              ;   in Loop: Header=BB1_599 Depth=3
	s_mov_b32 s1, -1
.LBB1_604:                              ; %Flow826
                                        ;   in Loop: Header=BB1_599 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_599
; %bb.605:                              ;   in Loop: Header=BB1_2 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_609
; %bb.606:                              ;   in Loop: Header=BB1_2 Depth=2
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_609
; %bb.607:                              ; %.preheader.i.i.i148.i.preheader
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_mov_b32 s0, 0
.LBB1_608:                              ; %.preheader.i.i.i148.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_608
.LBB1_609:                              ; %Flow824
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_610:                              ; %Flow857
                                        ;   in Loop: Header=BB1_2 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s35
	v_and_b32_e32 v0, 0xff, v53
	v_cmp_gt_u16_e32 vcc_lo, 57, v0
	v_add_nc_u16 v53, v0, 1
	s_cbranch_vccnz .LBB1_2
; %bb.611:                              ;   in Loop: Header=BB1_1 Depth=1
	v_and_b32_e32 v0, 0xff, v50
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u16_e32 vcc_lo, 57, v0
	v_add_nc_u16 v50, v0, 1
	s_cbranch_vccnz .LBB1_1
; %bb.612:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 48
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 54
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6kernelv, .Lfunc_end1-_Z6kernelv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 28852
; NumSgprs: 38
; NumVgprs: 54
; ScratchSize: 48
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 54
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"Found password: %s\n"
	.size	.str, 20

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         80
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelv
    .private_segment_fixed_size: 48
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     54
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
