/* 
 * James Jun 2019/12/22 
 * Fast approximation of knn using binned minimum parallel search
*/

#include <cuda_runtime.h>
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? -(my_val) : (my_val)
#define NC (45) //3pca x 16 channels max
#define SINGLE_INF (3.402E+38) // equipvalent to NAN. consider -1 value
#define SWAP(x, y, T) do { T SWAP = x; x = y; y = SWAP; } while (0)
#define CHUNK (8) // 16

/** Main entry point.
 * Works out where the current thread should read/write to global memory
 * and calls doIterations to do the actual work.
 * D: Mininum distances (nT x nA, float)
 * I: Index (nT x nA, int32)
 * F: Feature matrix (nC x nF, single)
 * IBB: vector of B offset (nBB x 1, int)
 * NBB: vector of B counts (nBB x 1, int)
 * const: [nC, nF, nBB, iA0, nA]
 */
__global__ void search_min_drift(float *D, int *I, float const *F, const int *IBB, const int *NBB, const int *vnConst){
    
    int nC = vnConst[0]; // number of feature dimension
    int nF = vnConst[1]; // number of channels
    int nBB = vnConst[2]; // number of blocks to read
    int iA0 = vnConst[3]; // A offset
    int nA = vnConst[4]; // number of A to read

    int tx = threadIdx.x;
    int nT = blockDim.x; // must be less than NTHREADS

    // shared memory
    __shared__ float sA[NC][CHUNK];
    __shared__ int sI[CHUNK];
    // thread memory
    float tD[CHUNK]; // t: thread, s: shraed
    int tI[CHUNK];
    
    // initialize
    if (tx < CHUNK){    
        int iA_ = tx; // loop over CHUNK
        int iA = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK + tx;
        iA = (iA % nA) + iA0;
        for (int iC=0; iC<nC; ++iC){
            sA[iC][iA_] = F[iC + iA*nC]; // copy A->sA 
        }
        sI[iA_] = iA;         
    }    
    __syncthreads();
    
    //#pragma unroll
    for (int iA_=0; iA_<CHUNK; ++iA_){            
        tD[iA_] = SINGLE_INF; // sD = inf
        tI[iA_] = sI[iA_];                
    }     
    
    // find minimum for each bin, stride of 2xnThread to save shared memory
    int iB0 = IBB[tx % nBB];
    int nB0 = NBB[tx % nBB];
    int iT0 = tx / nBB;
    int nT0 = nT / nBB;
    for (int iB=iT0+iB0; iB<nB0+iB0; iB+=nT0){    
        // Initialize distance vector
        float dist_[CHUNK];  // #programa unroll?   
        for (int iA_=0; iA_<CHUNK; ++iA_) dist_[iA_] = 0.0f;

        for (int iC=0; iC<nC; ++iC){
            float b_ = F[iC + iB*nC];
            for (int iA_=0; iA_<CHUNK; ++iA_){
                float d_ = b_ - sA[iC][iA_];
                dist_[iA_] += (d_ * d_);
            }            
        }         
        for (int iA_=0; iA_<CHUNK; ++iA_){
            float d_ = dist_[iA_];
            if (dist_[iA_] < tD[iA_] && d_ > 0.0f){
                tD[iA_] = d_;
                tI[iA_] = iB;
            }
        }
    } // while
    
    // write the output
    for (int iA_=0; iA_<CHUNK; ++iA_){ 
        int iA1 = sI[iA_] - iA0; // guaranteed to be bound due to modulus algebra     
        if (iA1 >= 0 && iA1 < nA){
            D[tx + nT*iA1] = sqrt(ABS(tD[iA_]));
            I[tx + nT*iA1] = tI[iA_] + 1; // matlab 1 base
        }
    } // for
} // func

	.file	"tmpxft_003450b0_00000000-6_search_min_drift.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z16search_min_driftPfPiPKfPKiS4_S4_PfPiPKfPKiS4_S4_
	.type	_Z50__device_stub__Z16search_min_driftPfPiPKfPKiS4_S4_PfPiPKfPKiS4_S4_, @function
_Z50__device_stub__Z16search_min_driftPfPiPKfPKiS4_S4_PfPiPKfPKiS4_S4_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z16search_min_driftPfPiPKfPKiS4_S4_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z50__device_stub__Z16search_min_driftPfPiPKfPKiS4_S4_PfPiPKfPKiS4_S4_, .-_Z50__device_stub__Z16search_min_driftPfPiPKfPKiS4_S4_PfPiPKfPKiS4_S4_
	.globl	_Z16search_min_driftPfPiPKfPKiS4_S4_
	.type	_Z16search_min_driftPfPiPKfPKiS4_S4_, @function
_Z16search_min_driftPfPiPKfPKiS4_S4_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z16search_min_driftPfPiPKfPKiS4_S4_PfPiPKfPKiS4_S4_
	.cfi_endproc
.LFE2033:
	.size	_Z16search_min_driftPfPiPKfPKiS4_S4_, .-_Z16search_min_driftPfPiPKfPKiS4_S4_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16search_min_driftPfPiPKfPKiS4_S4_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16search_min_driftPfPiPKfPKiS4_S4_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* 
 * James Jun 2019/12/22 
 * Fast approximation of knn using binned minimum parallel search
*/

#include <hip/hip_runtime.h>
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? -(my_val) : (my_val)
#define NC (45) //3pca x 16 channels max
#define SINGLE_INF (3.402E+38) // equipvalent to NAN. consider -1 value
#define SWAP(x, y, T) do { T SWAP = x; x = y; y = SWAP; } while (0)
#define CHUNK (8) // 16

/** Main entry point.
 * Works out where the current thread should read/write to global memory
 * and calls doIterations to do the actual work.
 * D: Mininum distances (nT x nA, float)
 * I: Index (nT x nA, int32)
 * F: Feature matrix (nC x nF, single)
 * IBB: vector of B offset (nBB x 1, int)
 * NBB: vector of B counts (nBB x 1, int)
 * const: [nC, nF, nBB, iA0, nA]
 */
__global__ void search_min_drift(float *D, int *I, float const *F, const int *IBB, const int *NBB, const int *vnConst){
    
    int nC = vnConst[0]; // number of feature dimension
    int nF = vnConst[1]; // number of channels
    int nBB = vnConst[2]; // number of blocks to read
    int iA0 = vnConst[3]; // A offset
    int nA = vnConst[4]; // number of A to read

    int tx = threadIdx.x;
    int nT = blockDim.x; // must be less than NTHREADS

    // shared memory
    __shared__ float sA[NC][CHUNK];
    __shared__ int sI[CHUNK];
    // thread memory
    float tD[CHUNK]; // t: thread, s: shraed
    int tI[CHUNK];
    
    // initialize
    if (tx < CHUNK){    
        int iA_ = tx; // loop over CHUNK
        int iA = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK + tx;
        iA = (iA % nA) + iA0;
        for (int iC=0; iC<nC; ++iC){
            sA[iC][iA_] = F[iC + iA*nC]; // copy A->sA 
        }
        sI[iA_] = iA;         
    }    
    __syncthreads();
    
    //#pragma unroll
    for (int iA_=0; iA_<CHUNK; ++iA_){            
        tD[iA_] = SINGLE_INF; // sD = inf
        tI[iA_] = sI[iA_];                
    }     
    
    // find minimum for each bin, stride of 2xnThread to save shared memory
    int iB0 = IBB[tx % nBB];
    int nB0 = NBB[tx % nBB];
    int iT0 = tx / nBB;
    int nT0 = nT / nBB;
    for (int iB=iT0+iB0; iB<nB0+iB0; iB+=nT0){    
        // Initialize distance vector
        float dist_[CHUNK];  // #programa unroll?   
        for (int iA_=0; iA_<CHUNK; ++iA_) dist_[iA_] = 0.0f;

        for (int iC=0; iC<nC; ++iC){
            float b_ = F[iC + iB*nC];
            for (int iA_=0; iA_<CHUNK; ++iA_){
                float d_ = b_ - sA[iC][iA_];
                dist_[iA_] += (d_ * d_);
            }            
        }         
        for (int iA_=0; iA_<CHUNK; ++iA_){
            float d_ = dist_[iA_];
            if (dist_[iA_] < tD[iA_] && d_ > 0.0f){
                tD[iA_] = d_;
                tI[iA_] = iB;
            }
        }
    } // while
    
    // write the output
    for (int iA_=0; iA_<CHUNK; ++iA_){ 
        int iA1 = sI[iA_] - iA0; // guaranteed to be bound due to modulus algebra     
        if (iA1 >= 0 && iA1 < nA){
            D[tx + nT*iA1] = sqrt(ABS(tD[iA_]));
            I[tx + nT*iA1] = tI[iA_] + 1; // matlab 1 base
        }
    } // for
} // func

	.text
	.file	"search_min_drift.hip"
	.globl	_Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_ # -- Begin function _Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_
	.type	_Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_,@function
_Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_: # @_Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16search_min_driftPfPiPKfPKiS4_S4_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_, .Lfunc_end0-_Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16search_min_driftPfPiPKfPKiS4_S4_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16search_min_driftPfPiPKfPKiS4_S4_,@object # @_Z16search_min_driftPfPiPKfPKiS4_S4_
	.section	.rodata,"a",@progbits
	.globl	_Z16search_min_driftPfPiPKfPKiS4_S4_
	.p2align	3, 0x0
_Z16search_min_driftPfPiPKfPKiS4_S4_:
	.quad	_Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_
	.size	_Z16search_min_driftPfPiPKfPKiS4_S4_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16search_min_driftPfPiPKfPKiS4_S4_"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__search_min_driftPfPiPKfPKiS4_S4_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16search_min_driftPfPiPKfPKiS4_S4_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16search_min_driftPfPiPKfPKiS4_S4_ ; -- Begin function _Z16search_min_driftPfPiPKfPKiS4_S4_
	.globl	_Z16search_min_driftPfPiPKfPKiS4_S4_
	.p2align	8
	.type	_Z16search_min_driftPfPiPKfPKiS4_S4_,@function
_Z16search_min_driftPfPiPKfPKiS4_S4_:   ; @_Z16search_min_driftPfPiPKfPKiS4_S4_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s12, s0, 48
	s_addc_u32 s13, s1, 0
	s_waitcnt lgkmcnt(0)
	s_clause 0x2
	s_load_b32 s20, s[18:19], 0x0
	s_load_b64 s[2:3], s[18:19], 0x8
	s_load_b32 s18, s[18:19], 0x10
	s_mov_b32 s19, exec_lo
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB0_5
; %bb.1:
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s21, s18, 31
	s_load_b32 s12, s[12:13], 0x0
	s_add_i32 s22, s18, s21
	v_lshlrev_b32_e32 v4, 2, v0
	s_xor_b32 s21, s22, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s21
	s_sub_i32 s13, 0, s21
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s12, s12, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s12, s12, s14
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s13, v1
	s_lshl_b32 s13, s12, 3
	s_bfe_i32 s12, s12, 0x1001c
	v_or_b32_e32 v3, s13, v0
	s_cmp_lt_i32 s20, 1
	v_add_nc_u32_e32 v3, s12, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, v1, v2
	v_xor_b32_e32 v3, s12, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	v_mul_hi_u32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s21
	v_sub_nc_u32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s21, v1
	v_cmp_le_u32_e32 vcc_lo, s21, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s21, v1
	v_cmp_le_u32_e32 vcc_lo, s21, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, s12, v1
	v_subrev_nc_u32_e32 v1, s12, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s3, v1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v3, s20
	v_mov_b32_e32 v5, v4
	s_mov_b32 s12, s20
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[1:2], off
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v6
	v_add_nc_u32_e32 v5, 32, v5
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %._crit_edge
	ds_store_b32 v4, v3 offset:1440
.LBB0_5:                                ; %Flow239
	s_or_b32 exec_lo, exec_lo, s19
	s_load_b32 s12, s[0:1], 0x3c
	s_mov_b64 s[0:1], 0
	s_movk_i32 s13, 0x5a0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr9
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v17, s13
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_add_i32 s13, s13, 4
	ds_load_b32 v17, v17
	s_cmp_eq_u32 s0, 8
	v_movreld_b32_e32 v1, 0x7f7ff023
	s_waitcnt lgkmcnt(0)
	v_movreld_b32_e32 v9, v17
	s_cbranch_scc0 .LBB0_6
; %bb.7:
	s_ashr_i32 s0, s2, 31
	s_mov_b32 s13, 0
	s_add_i32 s1, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s1, s1, s0
	v_cvt_f32_u32_e32 v17, s1
	s_sub_i32 s14, 0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v17, v17
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v17, 0x4f7ffffe, v17
	v_cvt_u32_f32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, s14, v20
	v_mul_hi_u32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v17, v20, v17
	v_mul_hi_u32 v17, v0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v18, v17, s1
	v_add_nc_u32_e32 v19, 1, v17
	v_sub_nc_u32_e32 v18, v0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v21, s1, v18
	v_cmp_le_u32_e32 vcc_lo, s1, v18
	v_dual_cndmask_b32 v17, v17, v19 :: v_dual_cndmask_b32 v18, v18, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, 1, v17
	v_cmp_le_u32_e32 vcc_lo, s1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v18, 0 :: v_dual_cndmask_b32 v17, v17, v19
	v_xor_b32_e32 v17, s0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v19, s0, v17
	v_mul_lo_u32 v17, v19, s2
	s_and_b32 s2, 0xffff, s12
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, v0, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, s16, v17
	v_add_co_ci_u32_e32 v22, vcc_lo, s17, v18, vcc_lo
	global_load_b32 v21, v[21:22], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v19, v21
	s_cbranch_execz .LBB0_20
; %bb.8:                                ; %.preheader128.lr.ph
	v_add_co_u32 v17, vcc_lo, s10, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s11, v18, vcc_lo
	v_readfirstlane_b32 s10, v20
	global_load_b32 v17, v[17:18], off
	s_mul_i32 s14, s14, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s11, s10, s14
	s_add_i32 s10, s10, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s10, s2, s10
	s_mul_i32 s11, s10, s1
	s_add_i32 s14, s10, 1
	s_sub_i32 s11, s2, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s15, s11, s1
	s_cmp_ge_u32 s11, s1
	s_cselect_b32 s10, s14, s10
	s_cselect_b32 s11, s15, s11
	s_add_i32 s14, s10, 1
	s_cmp_ge_u32 s11, s1
	s_cselect_b32 s1, s14, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s1, s1, s0
	s_sub_i32 s14, s1, s0
	s_cmp_gt_i32 s20, 0
	s_cselect_b32 s15, -1, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v25, v21, v17
	v_add_nc_u32_e32 v26, v19, v17
                                        ; implicit-def: $vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24
.LBB0_9:                                ; %.preheader128
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_10 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;     Child Loop BB0_17 Depth 2
	s_mov_b64 s[0:1], 0
.LBB0_10:                               ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 8
	v_movreld_b32_e32 v17, 0
	s_cbranch_scc0 .LBB0_10
; %bb.11:                               ; %.preheader127
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccnz .LBB0_16
; %bb.12:                               ; %.lr.ph139
                                        ;   in Loop: Header=BB0_9 Depth=1
	v_mul_lo_u32 v27, v26, s20
	s_mov_b32 s10, 0
	s_mov_b32 s11, 0
.LBB0_13:                               ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_14 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v28, s11, v27
	s_mov_b64 s[0:1], 0
	s_mov_b32 s16, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v29, 31, v28
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, s8, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v28, v[28:29], off
.LBB0_14:                               ;   Parent Loop BB0_9 Depth=1
                                        ;     Parent Loop BB0_13 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v29, s16
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	v_movrels_b32_e32 v30, v17
	s_addc_u32 s1, s1, 0
	ds_load_b32 v29, v29
	s_add_i32 s16, s16, 4
	s_cmp_eq_u32 s0, 8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v29, v28, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, v29, v29
	v_movreld_b32_e32 v17, v30
	s_cbranch_scc0 .LBB0_14
; %bb.15:                               ;   in Loop: Header=BB0_13 Depth=2
	s_add_i32 s11, s11, 1
	s_add_i32 s10, s10, 32
	s_cmp_eq_u32 s11, s20
	s_cbranch_scc0 .LBB0_13
.LBB0_16:                               ; %Flow234
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_mov_b64 s[10:11], 0
.LBB0_17:                               ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 m0, s10
	v_dual_mov_b32 v34, v8 :: v_dual_mov_b32 v33, v7
	v_movrels_b32_e32 v43, v17
	v_movrels_b32_e32 v44, v1
	v_dual_mov_b32 v42, v16 :: v_dual_mov_b32 v41, v15
	v_dual_mov_b32 v28, v2 :: v_dual_mov_b32 v27, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, v43, v44
	v_cmp_lt_f32_e64 s0, 0, v43
	v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v9
	v_dual_mov_b32 v32, v6 :: v_dual_mov_b32 v31, v5
	s_and_b32 vcc_lo, vcc_lo, s0
	v_dual_mov_b32 v30, v4 :: v_dual_mov_b32 v29, v3
	v_dual_mov_b32 v40, v14 :: v_dual_mov_b32 v39, v13
	v_dual_mov_b32 v38, v12 :: v_dual_mov_b32 v37, v11
	v_movreld_b32_e32 v27, v43
	v_movreld_b32_e32 v35, v26
	v_dual_cndmask_b32 v16, v16, v42 :: v_dual_cndmask_b32 v15, v15, v41
	v_dual_cndmask_b32 v14, v14, v40 :: v_dual_cndmask_b32 v13, v13, v39
	v_dual_cndmask_b32 v12, v12, v38 :: v_dual_cndmask_b32 v11, v11, v37
	v_dual_cndmask_b32 v10, v10, v36 :: v_dual_cndmask_b32 v9, v9, v35
	v_dual_cndmask_b32 v8, v8, v34 :: v_dual_cndmask_b32 v7, v7, v33
	v_dual_cndmask_b32 v6, v6, v32 :: v_dual_cndmask_b32 v5, v5, v31
	v_dual_cndmask_b32 v4, v4, v30 :: v_dual_cndmask_b32 v3, v3, v29
	v_dual_cndmask_b32 v2, v2, v28 :: v_dual_cndmask_b32 v1, v1, v27
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s10, 8
	s_cbranch_scc0 .LBB0_17
; %bb.18:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v26, s14, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v26, v25
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_9
; %bb.19:                               ; %Flow235
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_20:                               ; %Flow236
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[8:9], 0
	s_movk_i32 s1, 0x5a0
.LBB0_21:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, s1
	ds_load_b32 v18, v18
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s0, v18
	s_sub_i32 s10, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_gt_i32 s10, -1
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s10, s18
	s_cselect_b32 s11, -1, 0
	s_and_b32 s0, s0, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=1
	s_mov_b32 m0, s8
	v_movrels_b32_e32 v18, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v18, v18, -v18, vcc_lo
	v_mul_f32_e32 v19, 0x4f800000, v18
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v22, v18, v19, vcc_lo
	v_sqrt_f32_e32 v18, v22
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v19, -1, v18
	v_add_nc_u32_e32 v20, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v19, v18, v22
	v_fma_f32 v23, -v20, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v21
	v_cndmask_b32_e64 v21, v18, v19, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e64 s0, 0, v23
	v_mad_u64_u32 v[18:19], null, s10, s2, v[0:1]
	v_mov_b32_e32 v19, v17
	v_cndmask_b32_e64 v20, v21, v20, s0
	v_movrels_b32_e32 v21, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_dual_mul_f32 v23, 0x37800000, v20 :: v_dual_add_nc_u32 v24, 1, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v23, v20, v23, vcc_lo
	v_add_co_u32 v20, vcc_lo, s4, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v19, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v22, 0x260
	v_cndmask_b32_e32 v22, v23, v22, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	global_store_b32 v[20:21], v22, off
	global_store_b32 v[18:19], v24, off
.LBB0_23:                               ;   in Loop: Header=BB0_21 Depth=1
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s8, 8
	s_cbranch_scc0 .LBB0_21
; %bb.24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16search_min_driftPfPiPKfPKiS4_S4_
		.amdhsa_group_segment_fixed_size 1472
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16search_min_driftPfPiPKfPKiS4_S4_, .Lfunc_end0-_Z16search_min_driftPfPiPKfPKiS4_S4_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1608
; NumSgprs: 25
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1472 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1472
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16search_min_driftPfPiPKfPKiS4_S4_
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z16search_min_driftPfPiPKfPKiS4_S4_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
