//Based on the work of Andrew Krepps
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#define N 256
#define BLOCK_SIZE 16
#define NUM_BLOCKS N/BLOCK_SIZE

#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(int) * (ARRAY_SIZE))

///generate data//
__host__ void generateData(int * host_data_ptr, int arrayNum)
{
        for(unsigned int i=0; i < N; i++)
        {
        	if(arrayNum ==1)
        	{
        		host_data_ptr[i] = i;
        	}
        	else if(arrayNum ==2)
        	{
        		host_data_ptr[i] = 1;
        	}
        	else
        	{
        		host_data_ptr[i] = rand()%3;
        	}
                
        }
}

//REGISTER MEMORY
__global__  void operations_reg(int* array1,int* array2,int* array3, int opNum)
{
	int marker = threadIdx.x+blockDim.x*blockIdx.x;

	int tmp_data1 = array1[marker];
	int tmp_data2 = array2[marker];
	int tmp_data3 = array3[marker];

	if (opNum ==1){ tmp_data3=tmp_data1+tmp_data2;}
	else if (opNum ==2){tmp_data3=tmp_data1-tmp_data2;}
	else if (opNum ==3){tmp_data3=tmp_data1*tmp_data2;}
	else { tmp_data3=tmp_data1%tmp_data2;}

	array3[marker]=tmp_data3;
}
//SHARED MEMORY
__global__  void operations_shared(int * array1, int * array2, int *array3, int opNum)
{
	int i = threadIdx.x;

	__shared__ int tmpArray1_s[ARRAY_SIZE];
	__shared__ int tmpArray2_s[ARRAY_SIZE];
	__shared__ int tmpArray3_s[ARRAY_SIZE];

	tmpArray1_s[i] = array1[i];
	tmpArray2_s[i] = array2[i];
	tmpArray3_s[i] = array3[i];

	if (opNum ==1)
	{ tmpArray3_s[i]=tmpArray1_s[i]+tmpArray2_s[i];}
	else if (opNum ==2)
	{ tmpArray3_s[i]=tmpArray1_s[i]-tmpArray2_s[i];}
	else if (opNum ==3)
	{ tmpArray3_s[i]=tmpArray1_s[i]*tmpArray2_s[i];}
	else //if (opNum ==4)
	{ tmpArray3_s[i]=tmpArray1_s[i]%tmpArray2_s[i];}

	__syncthreads();

	array1[i] = tmpArray1_s[i];
	array2[i] = tmpArray2_s[i];
	array3[i] = tmpArray3_s[i];

}

//****************************************************************************

void main_register(int opNum)
{  

	cudaEvent_t start, stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	
///////////Declare Arrays/////////

	
	int* host_array1;
	int* host_array2;
	int* host_array3;

	host_array1=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array2=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array3=(int*)malloc(ARRAY_SIZE_IN_BYTES);

	/* Declare pointers for GPU based params */
	int *gpu_array1;
	int *gpu_array2;
	int *gpu_array3;

	cudaMalloc((void**)&gpu_array1, ARRAY_SIZE_IN_BYTES);
	cudaMalloc((void**)&gpu_array2, ARRAY_SIZE_IN_BYTES);
	cudaMalloc((void**)&gpu_array3, ARRAY_SIZE_IN_BYTES);

///////////Fill host arrays with values/////////

	generateData(host_array1, 1);
	generateData(host_array2, 2);
	generateData(host_array3, 3);

	cudaEventRecord(start);
	
///////////copy over memory /////////
	cudaMemcpy( gpu_array1,host_array1, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
	cudaMemcpy( gpu_array2,host_array2, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
	cudaMemcpy( gpu_array3,host_array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );

///////////execute operation/////////
	operations_reg<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array1,gpu_array2,gpu_array3,opNum);

	cudaEventRecord(stop);
	cudaEventSynchronize(stop);
	float milliseconds = 0;
	cudaEventElapsedTime(&milliseconds, start, stop);
	printf("Time elapsed: %f\n", milliseconds);

///////////copy memory back /////////
	cudaMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost); //only need array 3


	cudaFree(gpu_array1);
	cudaFree(gpu_array2);
	cudaFree(gpu_array3);
	

	printf("\n/////////////////REGISTER MEMORY RESULTS//////////////////\n");
	for( int k=0; k<ARRAY_SIZE; k++)
	{
		printf("\nINDEX: %i\tVALUE:%i\n",k, host_array3[k]);

	}
	
	
}

//****************************************************************************
/////////////////////////USE SHARED MEMORY/////////////////////////
void main_shared( int opNum)
{

	cudaEvent_t start, stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	
///////////Declare Arrays/////////

	
	int* host_array1;
	int* host_array2;
	int* host_array3;

	host_array1=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array2=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array3=(int*)malloc(ARRAY_SIZE_IN_BYTES);

	/* Declare pointers for GPU based params */
	int *gpu_array1;
	int *gpu_array2;
	int *gpu_array3;

	cudaMalloc((void**)&gpu_array1, ARRAY_SIZE_IN_BYTES);
	cudaMalloc((void**)&gpu_array2, ARRAY_SIZE_IN_BYTES);
	cudaMalloc((void**)&gpu_array3, ARRAY_SIZE_IN_BYTES);

///////////Fill host arrays with values/////////

	generateData(host_array1, 1);
	generateData(host_array2, 2);
	generateData(host_array3, 3);

	cudaEventRecord(start);
	
///////////copy over memory /////////
	cudaMemcpy( gpu_array1,host_array1, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
	cudaMemcpy( gpu_array2,host_array2, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );
	cudaMemcpy( gpu_array3,host_array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyHostToDevice );

///////////execute operation/////////
	operations_shared<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array1,gpu_array2,gpu_array3,opNum);

	cudaEventRecord(stop);
	cudaEventSynchronize(stop);
	float milliseconds = 0;
	cudaEventElapsedTime(&milliseconds, start, stop);
	printf("Time elapsed: %f\n", milliseconds);

///////////copy memory back /////////
	cudaMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost); //only need array 3


	cudaFree(gpu_array1);
	cudaFree(gpu_array2);
	cudaFree(gpu_array3);
	

	printf("\n/////////////////SHARED MEMORY RESULTS//////////////////\n");
	for( int k=0; k<ARRAY_SIZE; k++)
	{
		printf("\nINDEX: %i\tVALUE:%i\n",k, host_array3[k]);

	}
	
	
}

int main(int argc, char** argv){

	int opNum=1; 
	

	if (argc >= 2) {
		opNum = atoi(argv[1]);
	}

	main_shared(opNum);
	main_register(opNum);

	return 0;
}


	.file	"tmpxft_00290e5a_00000000-6_assignment_256.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12generateDataPii
	.type	_Z12generateDataPii, @function
_Z12generateDataPii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
.L5:
	movl	%ebx, %edx
	cmpl	$1, %ebp
	je	.L4
	movl	$1, %edx
	cmpl	$2, %ebp
	je	.L4
	call	rand@PLT
	movl	$3, %ecx
	cltd
	idivl	%ecx
.L4:
	movl	%edx, (%r12,%rbx,4)
	incq	%rbx
	cmpq	$256, %rbx
	jne	.L5
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z12generateDataPii, .-_Z12generateDataPii
	.globl	_Z39__device_stub__Z14operations_regPiS_S_iPiS_S_i
	.type	_Z39__device_stub__Z14operations_regPiS_S_iPiS_S_i, @function
_Z39__device_stub__Z14operations_regPiS_S_iPiS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14operations_regPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L11:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z39__device_stub__Z14operations_regPiS_S_iPiS_S_i, .-_Z39__device_stub__Z14operations_regPiS_S_iPiS_S_i
	.globl	_Z14operations_regPiS_S_i
	.type	_Z14operations_regPiS_S_i, @function
_Z14operations_regPiS_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z14operations_regPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2056:
	.size	_Z14operations_regPiS_S_i, .-_Z14operations_regPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Time elapsed: %f\n"
.LC2:
	.string	"\n/////////////////REGISTER MEMORY RESULTS//////////////////\n"
.LC3:
	.string	"\nINDEX: %i\tVALUE:%i\n"
	.text
	.globl	_Z13main_registeri
	.type	_Z13main_registeri, @function
_Z13main_registeri:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$1024, %edi
	call	malloc@PLT
	movl	$1024, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$1024, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1024, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	movl	$1, %esi
	movq	%r12, %rdi
	call	_Z12generateDataPii
	movl	$2, %esi
	movq	%rbp, %rdi
	call	_Z12generateDataPii
	movl	$3, %esi
	movq	%rbx, %rdi
	call	_Z12generateDataPii
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movl	$268435457, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 68(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%r13d, %ecx
	movq	24(%rsp), %rdi
	call	_Z39__device_stub__Z14operations_regPiS_S_iPiS_S_i
.L17:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebp, %ebp
	leaq	.LC3(%rip), %r12
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	60(%rsp), %rdi
	movl	$0x00000000, 60(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	60(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$1024, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L18:
	movl	(%rbx,%rbp,4), %ecx
	movl	%ebp, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$256, %rbp
	jne	.L18
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z13main_registeri, .-_Z13main_registeri
	.globl	_Z42__device_stub__Z17operations_sharedPiS_S_iPiS_S_i
	.type	_Z42__device_stub__Z17operations_sharedPiS_S_iPiS_S_i, @function
_Z42__device_stub__Z17operations_sharedPiS_S_iPiS_S_i:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17operations_sharedPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L22:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z42__device_stub__Z17operations_sharedPiS_S_iPiS_S_i, .-_Z42__device_stub__Z17operations_sharedPiS_S_iPiS_S_i
	.globl	_Z17operations_sharedPiS_S_i
	.type	_Z17operations_sharedPiS_S_i, @function
_Z17operations_sharedPiS_S_i:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z17operations_sharedPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2058:
	.size	_Z17operations_sharedPiS_S_i, .-_Z17operations_sharedPiS_S_i
	.section	.rodata.str1.1
.LC4:
	.string	"\n/////////////////SHARED MEMORY RESULTS//////////////////\n"
	.text
	.globl	_Z11main_sharedi
	.type	_Z11main_sharedi, @function
_Z11main_sharedi:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	$1024, %edi
	call	malloc@PLT
	movl	$1024, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$1024, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1024, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	movl	$1, %esi
	movq	%r12, %rdi
	call	_Z12generateDataPii
	movl	$2, %esi
	movq	%rbp, %rdi
	call	_Z12generateDataPii
	movl	$3, %esi
	movq	%rbx, %rdi
	call	_Z12generateDataPii
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movl	$268435457, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 68(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%r13d, %ecx
	movq	24(%rsp), %rdi
	call	_Z42__device_stub__Z17operations_sharedPiS_S_iPiS_S_i
.L28:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebp, %ebp
	leaq	.LC3(%rip), %r12
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	leaq	60(%rsp), %rdi
	movl	$0x00000000, 60(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	60(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$1024, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L29:
	movl	(%rbx,%rbp,4), %ecx
	movl	%ebp, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$256, %rbp
	jne	.L29
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z11main_sharedi, .-_Z11main_sharedi
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	decl	%edi
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$1, %ebx
	jle	.L34
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
.L34:
	movl	%ebx, %edi
	call	_Z11main_sharedi
	movl	%ebx, %edi
	call	_Z13main_registeri
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z17operations_sharedPiS_S_i"
.LC6:
	.string	"_Z14operations_regPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17operations_sharedPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14operations_regPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//Based on the work of Andrew Krepps

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

#define N 256
#define BLOCK_SIZE 16
#define NUM_BLOCKS N/BLOCK_SIZE

#define ARRAY_SIZE N
#define ARRAY_SIZE_IN_BYTES (sizeof(int) * (ARRAY_SIZE))

///generate data//
__host__ void generateData(int * host_data_ptr, int arrayNum)
{
        for(unsigned int i=0; i < N; i++)
        {
        	if(arrayNum ==1)
        	{
        		host_data_ptr[i] = i;
        	}
        	else if(arrayNum ==2)
        	{
        		host_data_ptr[i] = 1;
        	}
        	else
        	{
        		host_data_ptr[i] = rand()%3;
        	}
                
        }
}

//REGISTER MEMORY
__global__  void operations_reg(int* array1,int* array2,int* array3, int opNum)
{
	int marker = threadIdx.x+blockDim.x*blockIdx.x;

	int tmp_data1 = array1[marker];
	int tmp_data2 = array2[marker];
	int tmp_data3 = array3[marker];

	if (opNum ==1){ tmp_data3=tmp_data1+tmp_data2;}
	else if (opNum ==2){tmp_data3=tmp_data1-tmp_data2;}
	else if (opNum ==3){tmp_data3=tmp_data1*tmp_data2;}
	else { tmp_data3=tmp_data1%tmp_data2;}

	array3[marker]=tmp_data3;
}
//SHARED MEMORY
__global__  void operations_shared(int * array1, int * array2, int *array3, int opNum)
{
	int i = threadIdx.x;

	__shared__ int tmpArray1_s[ARRAY_SIZE];
	__shared__ int tmpArray2_s[ARRAY_SIZE];
	__shared__ int tmpArray3_s[ARRAY_SIZE];

	tmpArray1_s[i] = array1[i];
	tmpArray2_s[i] = array2[i];
	tmpArray3_s[i] = array3[i];

	if (opNum ==1)
	{ tmpArray3_s[i]=tmpArray1_s[i]+tmpArray2_s[i];}
	else if (opNum ==2)
	{ tmpArray3_s[i]=tmpArray1_s[i]-tmpArray2_s[i];}
	else if (opNum ==3)
	{ tmpArray3_s[i]=tmpArray1_s[i]*tmpArray2_s[i];}
	else //if (opNum ==4)
	{ tmpArray3_s[i]=tmpArray1_s[i]%tmpArray2_s[i];}

	__syncthreads();

	array1[i] = tmpArray1_s[i];
	array2[i] = tmpArray2_s[i];
	array3[i] = tmpArray3_s[i];

}

//****************************************************************************

void main_register(int opNum)
{  

	hipEvent_t start, stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);
	
///////////Declare Arrays/////////

	
	int* host_array1;
	int* host_array2;
	int* host_array3;

	host_array1=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array2=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array3=(int*)malloc(ARRAY_SIZE_IN_BYTES);

	/* Declare pointers for GPU based params */
	int *gpu_array1;
	int *gpu_array2;
	int *gpu_array3;

	hipMalloc((void**)&gpu_array1, ARRAY_SIZE_IN_BYTES);
	hipMalloc((void**)&gpu_array2, ARRAY_SIZE_IN_BYTES);
	hipMalloc((void**)&gpu_array3, ARRAY_SIZE_IN_BYTES);

///////////Fill host arrays with values/////////

	generateData(host_array1, 1);
	generateData(host_array2, 2);
	generateData(host_array3, 3);

	hipEventRecord(start);
	
///////////copy over memory /////////
	hipMemcpy( gpu_array1,host_array1, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
	hipMemcpy( gpu_array2,host_array2, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
	hipMemcpy( gpu_array3,host_array3, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );

///////////execute operation/////////
	operations_reg<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array1,gpu_array2,gpu_array3,opNum);

	hipEventRecord(stop);
	hipEventSynchronize(stop);
	float milliseconds = 0;
	hipEventElapsedTime(&milliseconds, start, stop);
	printf("Time elapsed: %f\n", milliseconds);

///////////copy memory back /////////
	hipMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost); //only need array 3


	hipFree(gpu_array1);
	hipFree(gpu_array2);
	hipFree(gpu_array3);
	

	printf("\n/////////////////REGISTER MEMORY RESULTS//////////////////\n");
	for( int k=0; k<ARRAY_SIZE; k++)
	{
		printf("\nINDEX: %i\tVALUE:%i\n",k, host_array3[k]);

	}
	
	
}

//****************************************************************************
/////////////////////////USE SHARED MEMORY/////////////////////////
void main_shared( int opNum)
{

	hipEvent_t start, stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);
	
///////////Declare Arrays/////////

	
	int* host_array1;
	int* host_array2;
	int* host_array3;

	host_array1=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array2=(int*)malloc(ARRAY_SIZE_IN_BYTES);
	host_array3=(int*)malloc(ARRAY_SIZE_IN_BYTES);

	/* Declare pointers for GPU based params */
	int *gpu_array1;
	int *gpu_array2;
	int *gpu_array3;

	hipMalloc((void**)&gpu_array1, ARRAY_SIZE_IN_BYTES);
	hipMalloc((void**)&gpu_array2, ARRAY_SIZE_IN_BYTES);
	hipMalloc((void**)&gpu_array3, ARRAY_SIZE_IN_BYTES);

///////////Fill host arrays with values/////////

	generateData(host_array1, 1);
	generateData(host_array2, 2);
	generateData(host_array3, 3);

	hipEventRecord(start);
	
///////////copy over memory /////////
	hipMemcpy( gpu_array1,host_array1, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
	hipMemcpy( gpu_array2,host_array2, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );
	hipMemcpy( gpu_array3,host_array3, ARRAY_SIZE_IN_BYTES, hipMemcpyHostToDevice );

///////////execute operation/////////
	operations_shared<<<NUM_BLOCKS,BLOCK_SIZE>>>(gpu_array1,gpu_array2,gpu_array3,opNum);

	hipEventRecord(stop);
	hipEventSynchronize(stop);
	float milliseconds = 0;
	hipEventElapsedTime(&milliseconds, start, stop);
	printf("Time elapsed: %f\n", milliseconds);

///////////copy memory back /////////
	hipMemcpy(host_array3, gpu_array3, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost); //only need array 3


	hipFree(gpu_array1);
	hipFree(gpu_array2);
	hipFree(gpu_array3);
	

	printf("\n/////////////////SHARED MEMORY RESULTS//////////////////\n");
	for( int k=0; k<ARRAY_SIZE; k++)
	{
		printf("\nINDEX: %i\tVALUE:%i\n",k, host_array3[k]);

	}
	
	
}

int main(int argc, char** argv){

	int opNum=1; 
	

	if (argc >= 2) {
		opNum = atoi(argv[1]);
	}

	main_shared(opNum);
	main_register(opNum);

	return 0;
}


	.text
	.file	"assignment_256.hip"
	.globl	_Z12generateDataPii             # -- Begin function _Z12generateDataPii
	.type	_Z12generateDataPii,@function
_Z12generateDataPii:                    # @_Z12generateDataPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	xorl	%r15d, %r15d
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	cmpl	$2, %ebx
	je	.LBB0_4
# %bb.2:                                #   in Loop: Header=BB0_1 Depth=1
	cmpl	$1, %ebx
	jne	.LBB0_5
# %bb.3:                                #   in Loop: Header=BB0_1 Depth=1
	movl	%r15d, (%r14,%r15,4)
	jmp	.LBB0_6
.LBB0_4:                                #   in Loop: Header=BB0_1 Depth=1
	movl	$1, (%r14,%r15,4)
	jmp	.LBB0_6
.LBB0_5:                                #   in Loop: Header=BB0_1 Depth=1
	callq	rand
	cltq
	imulq	$1431655766, %rax, %rcx         # imm = 0x55555556
	movq	%rcx, %rdx
	shrq	$63, %rdx
	shrq	$32, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,2), %ecx
	subl	%ecx, %eax
	movl	%eax, (%r14,%r15,4)
.LBB0_6:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%r15
	cmpq	$256, %r15                      # imm = 0x100
	jne	.LBB0_1
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z12generateDataPii, .Lfunc_end0-_Z12generateDataPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__operations_regPiS_S_i # -- Begin function _Z29__device_stub__operations_regPiS_S_i
	.type	_Z29__device_stub__operations_regPiS_S_i,@function
_Z29__device_stub__operations_regPiS_S_i: # @_Z29__device_stub__operations_regPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14operations_regPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__operations_regPiS_S_i, .Lfunc_end1-_Z29__device_stub__operations_regPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__operations_sharedPiS_S_i # -- Begin function _Z32__device_stub__operations_sharedPiS_S_i
	.type	_Z32__device_stub__operations_sharedPiS_S_i,@function
_Z32__device_stub__operations_sharedPiS_S_i: # @_Z32__device_stub__operations_sharedPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17operations_sharedPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__operations_sharedPiS_S_i, .Lfunc_end2-_Z32__device_stub__operations_sharedPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z13main_registeri              # -- Begin function _Z13main_registeri
	.type	_Z13main_registeri,@function
_Z13main_registeri:                     # @_Z13main_registeri
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebp
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %r15
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %r14
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %rbx
	leaq	16(%rsp), %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	xorl	%eax, %eax
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%r15,%rax,4)
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB3_1
# %bb.2:                                # %_Z12generateDataPii.exit.preheader
	xorl	%eax, %eax
.LBB3_3:                                # %_Z12generateDataPii.exit
                                        # =>This Inner Loop Header: Depth=1
	movl	$1, (%r14,%rax,4)
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB3_3
# %bb.4:                                # %_Z12generateDataPii.exit17.preheader
	xorl	%r12d, %r12d
.LBB3_5:                                # %_Z12generateDataPii.exit17
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1431655766, %rax, %rcx         # imm = 0x55555556
	movq	%rcx, %rdx
	shrq	$63, %rdx
	shrq	$32, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,2), %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r12,4)
	incq	%r12
	cmpq	$256, %r12                      # imm = 0x100
	jne	.LBB3_5
# %bb.6:                                # %_Z12generateDataPii.exit21
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967312, %rdi               # imm = 0x100000010
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%ebp, %ecx
	callq	_Z29__device_stub__operations_regPiS_S_i
.LBB3_8:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	44(%rsp), %r14
	movl	$0, (%r14)
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
.LBB3_9:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %edx
	movl	$.L.str.2, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$256, %r14                      # imm = 0x100
	jne	.LBB3_9
# %bb.10:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z13main_registeri, .Lfunc_end3-_Z13main_registeri
	.cfi_endproc
                                        # -- End function
	.globl	_Z11main_sharedi                # -- Begin function _Z11main_sharedi
	.type	_Z11main_sharedi,@function
_Z11main_sharedi:                       # @_Z11main_sharedi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebp
	leaq	32(%rsp), %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %r15
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %r14
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %rbx
	leaq	16(%rsp), %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	xorl	%eax, %eax
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%r15,%rax,4)
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB4_1
# %bb.2:                                # %_Z12generateDataPii.exit.preheader
	xorl	%eax, %eax
.LBB4_3:                                # %_Z12generateDataPii.exit
                                        # =>This Inner Loop Header: Depth=1
	movl	$1, (%r14,%rax,4)
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB4_3
# %bb.4:                                # %_Z12generateDataPii.exit17.preheader
	xorl	%r12d, %r12d
.LBB4_5:                                # %_Z12generateDataPii.exit17
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1431655766, %rax, %rcx         # imm = 0x55555556
	movq	%rcx, %rdx
	shrq	$63, %rdx
	shrq	$32, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,2), %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r12,4)
	incq	%r12
	cmpq	$256, %r12                      # imm = 0x100
	jne	.LBB4_5
# %bb.6:                                # %_Z12generateDataPii.exit21
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967312, %rdi               # imm = 0x100000010
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%ebp, %ecx
	callq	_Z32__device_stub__operations_sharedPiS_S_i
.LBB4_8:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	44(%rsp), %r14
	movl	$0, (%r14)
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	(%rsp), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
.LBB4_9:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %edx
	movl	$.L.str.2, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$256, %r14                      # imm = 0x100
	jne	.LBB4_9
# %bb.10:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z11main_sharedi, .Lfunc_end4-_Z11main_sharedi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	$1, %ebx
	cmpl	$2, %edi
	jl	.LBB5_2
# %bb.1:
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
.LBB5_2:
	movl	%ebx, %edi
	callq	_Z11main_sharedi
	movl	%ebx, %edi
	callq	_Z13main_registeri
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14operations_regPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17operations_sharedPiS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14operations_regPiS_S_i,@object # @_Z14operations_regPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z14operations_regPiS_S_i
	.p2align	3, 0x0
_Z14operations_regPiS_S_i:
	.quad	_Z29__device_stub__operations_regPiS_S_i
	.size	_Z14operations_regPiS_S_i, 8

	.type	_Z17operations_sharedPiS_S_i,@object # @_Z17operations_sharedPiS_S_i
	.globl	_Z17operations_sharedPiS_S_i
	.p2align	3, 0x0
_Z17operations_sharedPiS_S_i:
	.quad	_Z32__device_stub__operations_sharedPiS_S_i
	.size	_Z17operations_sharedPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Time elapsed: %f\n"
	.size	.L.str, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\nINDEX: %i\tVALUE:%i\n"
	.size	.L.str.2, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14operations_regPiS_S_i"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17operations_sharedPiS_S_i"
	.size	.L__unnamed_2, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n/////////////////REGISTER MEMORY RESULTS//////////////////"
	.size	.Lstr, 60

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\n/////////////////SHARED MEMORY RESULTS//////////////////"
	.size	.Lstr.1, 58

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__operations_regPiS_S_i
	.addrsig_sym _Z32__device_stub__operations_sharedPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14operations_regPiS_S_i
	.addrsig_sym _Z17operations_sharedPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14operations_regPiS_S_i ; -- Begin function _Z14operations_regPiS_S_i
	.globl	_Z14operations_regPiS_S_i
	.p2align	8
	.type	_Z14operations_regPiS_S_i,@function
_Z14operations_regPiS_S_i:              ; @_Z14operations_regPiS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_lt_i32 s3, 2
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	s_cbranch_scc1 .LBB0_4
; %bb.1:                                ; %NodeBlock
	s_cmp_gt_i32 s3, 2
	s_cbranch_scc0 .LBB0_5
; %bb.2:                                ; %LeafBlock33
	s_cmp_eq_u32 s3, 3
	s_cbranch_scc0 .LBB0_6
; %bb.3:
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v4, v3, v2
	s_mov_b32 s4, 0
	s_branch .LBB0_7
.LBB0_4:
	s_mov_b32 s5, -1
	s_mov_b32 s4, 0
                                        ; implicit-def: $vgpr4
	s_branch .LBB0_11
.LBB0_5:
	s_mov_b32 s5, -1
	s_mov_b32 s4, 0
                                        ; implicit-def: $vgpr4
	s_branch .LBB0_8
.LBB0_6:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr4
.LBB0_7:                                ; %Flow38
	s_mov_b32 s5, 0
.LBB0_8:                                ; %Flow37
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_10
; %bb.9:
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v4, v2, v3
.LBB0_10:                               ; %Flow39
	s_mov_b32 s5, 0
.LBB0_11:                               ; %Flow
	s_load_b64 s[0:1], s[0:1], 0x10
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB0_13
; %bb.12:                               ; %LeafBlock
	s_cmp_lg_u32 s3, 1
	s_mov_b32 s2, -1
	s_cselect_b32 s4, -1, 0
                                        ; implicit-def: $vgpr4
.LBB0_13:                               ; %Flow40
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_15
; %bb.14:
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v7, 31, v2
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v3, v4
	v_add_nc_u32_e32 v8, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v5, v4
	v_xor_b32_e32 v8, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, v4
	v_sub_nc_u32_e32 v6, 0, v4
	v_rcp_iflag_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v5, v5
	v_mul_lo_u32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v6
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v8, v5
	v_mul_lo_u32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v5
	v_sub_nc_u32_e32 v6, v5, v4
	v_cmp_ge_u32_e32 vcc_lo, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_sub_nc_u32_e32 v6, v5, v4
	v_cmp_ge_u32_e32 vcc_lo, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v5, v6, vcc_lo
	v_xor_b32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v7
.LBB0_15:                               ; %Flow41
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_17
; %bb.16:
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v3, v2
.LBB0_17:
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14operations_regPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14operations_regPiS_S_i, .Lfunc_end0-_Z14operations_regPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17operations_sharedPiS_S_i ; -- Begin function _Z17operations_sharedPiS_S_i
	.globl	_Z17operations_sharedPiS_S_i
	.p2align	8
	.type	_Z17operations_sharedPiS_S_i,@function
_Z17operations_sharedPiS_S_i:           ; @_Z17operations_sharedPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_lshlrev_b32_e32 v5, 2, v0
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v7, v5, s[4:5]
	global_load_b32 v8, v5, s[6:7]
	v_add_co_u32 v1, s4, s4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, null, s5, 0, s4
	v_add_co_u32 v3, s4, s6, v5
	v_add_co_ci_u32_e64 v4, null, s7, 0, s4
	v_add_nc_u32_e32 v6, 0x400, v5
	s_mov_b32 s4, 0
	s_cmp_lt_i32 s0, 2
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v5, v7, v8 offset1:4
	s_cbranch_scc1 .LBB1_4
; %bb.1:                                ; %NodeBlock
	s_cmp_gt_i32 s0, 2
	s_cbranch_scc0 .LBB1_5
; %bb.2:                                ; %LeafBlock45
	s_cmp_eq_u32 s0, 3
	s_cbranch_scc0 .LBB1_6
; %bb.3:
	v_mul_lo_u32 v9, v8, v7
	s_branch .LBB1_7
.LBB1_4:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr9
	s_branch .LBB1_11
.LBB1_5:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr9
	s_branch .LBB1_8
.LBB1_6:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr9
.LBB1_7:                                ; %Flow50
	s_mov_b32 s1, 0
.LBB1_8:                                ; %Flow49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB1_10
; %bb.9:
	v_sub_nc_u32_e32 v9, v7, v8
.LBB1_10:                               ; %Flow51
	s_mov_b32 s1, 0
.LBB1_11:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_mov_b32 s1, 0
	s_cbranch_vccz .LBB1_13
; %bb.12:                               ; %LeafBlock
	s_cmp_lg_u32 s0, 1
	s_mov_b32 s1, -1
	s_cselect_b32 s4, -1, 0
                                        ; implicit-def: $vgpr9
.LBB1_13:                               ; %Flow52
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_15
; %bb.14:
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v12, 31, v7
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v8, v9
	v_add_nc_u32_e32 v13, v7, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v10, v9
	v_xor_b32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v10, v9
	v_sub_nc_u32_e32 v11, 0, v9
	v_rcp_iflag_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v10, v10
	v_mul_lo_u32 v11, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v10, v11
	v_add_nc_u32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v10, v13, v10
	v_mul_lo_u32 v10, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v13, v10
	v_sub_nc_u32_e32 v11, v10, v9
	v_cmp_ge_u32_e32 vcc_lo, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_sub_nc_u32_e32 v11, v10, v9
	v_cmp_ge_u32_e32 vcc_lo, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, v10, v11, vcc_lo
	v_xor_b32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v9, v12
.LBB1_15:                               ; %Flow53
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_17
; %bb.16:
	v_add_nc_u32_e32 v9, v8, v7
.LBB1_17:
	v_lshlrev_b32_e32 v0, 2, v0
	ds_store_b32 v0, v9 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v5, v5
	ds_load_b32 v6, v6
	ds_load_b32 v7, v0 offset:2048
	s_waitcnt lgkmcnt(2)
	global_store_b32 v[1:2], v5, off
	s_waitcnt lgkmcnt(1)
	global_store_b32 v[3:4], v6, off
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v7, s[2:3]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17operations_sharedPiS_S_i
		.amdhsa_group_segment_fixed_size 3072
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17operations_sharedPiS_S_i, .Lfunc_end1-_Z17operations_sharedPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 516
; NumSgprs: 10
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3072 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14operations_regPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14operations_regPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 3072
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17operations_sharedPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z17operations_sharedPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
