#include "includes.h"
extern "C" {
}



#define TB 256
#define EPS 1e-4

__global__ void bilateral_smooth_kernel( float *affine_model, float *filtered_affine_model, float *guide, int h, int w, int kernel_radius, float sigma1, float sigma2 )
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (id < size) {
int x = id % w;
int y = id / w;

double sum_affine[12] = {};
double sum_weight = 0;
for (int dx = -kernel_radius; dx <= kernel_radius; dx++) {
for (int dy = -kernel_radius; dy <= kernel_radius; dy++) {
int yy = y + dy, xx = x + dx;
int id2 = yy * w + xx;
if (0 <= xx && xx < w && 0 <= yy && yy < h) {
float color_diff1 = guide[yy*w + xx] - guide[y*w + x];
float color_diff2 = guide[yy*w + xx + size] - guide[y*w + x + size];
float color_diff3 = guide[yy*w + xx + 2*size] - guide[y*w + x + 2*size];
float color_diff_sqr =
(color_diff1*color_diff1 + color_diff2*color_diff2 + color_diff3*color_diff3) / 3;

float v1 = exp(-(dx * dx + dy * dy) / (2 * sigma1 * sigma1));
float v2 = exp(-(color_diff_sqr) / (2 * sigma2 * sigma2));
float weight = v1 * v2;

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
int affine_id = i * 4 + j;
sum_affine[affine_id] += weight * affine_model[id2*12 + affine_id];
}
}
sum_weight += weight;
}
}
}

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
int affine_id = i * 4 + j;
filtered_affine_model[id*12 + affine_id] = sum_affine[affine_id] / sum_weight;
}
}
}
return ;
}
	.file	"tmpxft_0029294d_00000000-6_bilateral_smooth_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z23bilateral_smooth_kernelPfS_S_iiiffPfS_S_iiiff
	.type	_Z52__device_stub__Z23bilateral_smooth_kernelPfS_S_iiiffPfS_S_iiiff, @function
_Z52__device_stub__Z23bilateral_smooth_kernelPfS_S_iiiffPfS_S_iiiff:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z23bilateral_smooth_kernelPfS_S_iiiff(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z52__device_stub__Z23bilateral_smooth_kernelPfS_S_iiiffPfS_S_iiiff, .-_Z52__device_stub__Z23bilateral_smooth_kernelPfS_S_iiiffPfS_S_iiiff
	.globl	_Z23bilateral_smooth_kernelPfS_S_iiiff
	.type	_Z23bilateral_smooth_kernelPfS_S_iiiff, @function
_Z23bilateral_smooth_kernelPfS_S_iiiff:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z23bilateral_smooth_kernelPfS_S_iiiffPfS_S_iiiff
	.cfi_endproc
.LFE2033:
	.size	_Z23bilateral_smooth_kernelPfS_S_iiiff, .-_Z23bilateral_smooth_kernelPfS_S_iiiff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z23bilateral_smooth_kernelPfS_S_iiiff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z23bilateral_smooth_kernelPfS_S_iiiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}



#define TB 256
#define EPS 1e-4

__global__ void bilateral_smooth_kernel( float *affine_model, float *filtered_affine_model, float *guide, int h, int w, int kernel_radius, float sigma1, float sigma2 )
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (id < size) {
int x = id % w;
int y = id / w;

double sum_affine[12] = {};
double sum_weight = 0;
for (int dx = -kernel_radius; dx <= kernel_radius; dx++) {
for (int dy = -kernel_radius; dy <= kernel_radius; dy++) {
int yy = y + dy, xx = x + dx;
int id2 = yy * w + xx;
if (0 <= xx && xx < w && 0 <= yy && yy < h) {
float color_diff1 = guide[yy*w + xx] - guide[y*w + x];
float color_diff2 = guide[yy*w + xx + size] - guide[y*w + x + size];
float color_diff3 = guide[yy*w + xx + 2*size] - guide[y*w + x + 2*size];
float color_diff_sqr =
(color_diff1*color_diff1 + color_diff2*color_diff2 + color_diff3*color_diff3) / 3;

float v1 = exp(-(dx * dx + dy * dy) / (2 * sigma1 * sigma1));
float v2 = exp(-(color_diff_sqr) / (2 * sigma2 * sigma2));
float weight = v1 * v2;

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
int affine_id = i * 4 + j;
sum_affine[affine_id] += weight * affine_model[id2*12 + affine_id];
}
}
sum_weight += weight;
}
}
}

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
int affine_id = i * 4 + j;
filtered_affine_model[id*12 + affine_id] = sum_affine[affine_id] / sum_weight;
}
}
}
return ;
}
	.text
	.file	"bilateral_smooth_kernel.hip"
	.globl	_Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff # -- Begin function _Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff
	.type	_Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff,@function
_Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff: # @_Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	4(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23bilateral_smooth_kernelPfS_S_iiiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff, .Lfunc_end0-_Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23bilateral_smooth_kernelPfS_S_iiiff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23bilateral_smooth_kernelPfS_S_iiiff,@object # @_Z23bilateral_smooth_kernelPfS_S_iiiff
	.section	.rodata,"a",@progbits
	.globl	_Z23bilateral_smooth_kernelPfS_S_iiiff
	.p2align	3, 0x0
_Z23bilateral_smooth_kernelPfS_S_iiiff:
	.quad	_Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff
	.size	_Z23bilateral_smooth_kernelPfS_S_iiiff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z23bilateral_smooth_kernelPfS_S_iiiff"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__bilateral_smooth_kernelPfS_S_iiiff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23bilateral_smooth_kernelPfS_S_iiiff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23bilateral_smooth_kernelPfS_S_iiiff ; -- Begin function _Z23bilateral_smooth_kernelPfS_S_iiiff
	.globl	_Z23bilateral_smooth_kernelPfS_S_iiiff
	.p2align	8
	.type	_Z23bilateral_smooth_kernelPfS_S_iiiff,@function
_Z23bilateral_smooth_kernelPfS_S_iiiff: ; @_Z23bilateral_smooth_kernelPfS_S_iiiff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s12, s5, s4
	v_mad_u64_u32 v[43:44], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v43
	s_cbranch_execz .LBB0_20
; %bb.1:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[14:15], s[0:1], 0x10
	s_mov_b32 s36, 0
	v_mul_lo_u32 v32, v43, 12
	s_mov_b32 s37, s36
	s_mov_b32 s38, s36
	s_mov_b32 s39, s36
	s_mov_b32 s40, s36
	s_mov_b32 s41, s36
	s_mov_b32 s42, s36
	s_mov_b32 s43, s36
	s_mov_b32 s44, s36
	s_mov_b32 s45, s36
	s_mov_b32 s46, s36
	s_mov_b32 s47, s36
	s_mov_b32 s48, s36
	s_mov_b32 s49, s36
	s_mov_b32 s50, s36
	s_mov_b32 s51, s36
	s_mov_b32 s52, s36
	s_mov_b32 s53, s36
	s_mov_b32 s54, s36
	s_mov_b32 s55, s36
	s_mov_b32 s56, s36
	s_mov_b32 s57, s36
	s_mov_b32 s58, s36
	s_mov_b32 s59, s36
	v_mov_b32_e32 v34, 0
	v_dual_mov_b32 v35, 0 :: v_dual_mov_b32 v0, s36
	v_dual_mov_b32 v1, s37 :: v_dual_mov_b32 v2, s38
	v_dual_mov_b32 v3, s39 :: v_dual_mov_b32 v4, s40
	v_dual_mov_b32 v5, s41 :: v_dual_mov_b32 v6, s42
	v_dual_mov_b32 v7, s43 :: v_dual_mov_b32 v8, s44
	v_dual_mov_b32 v9, s45 :: v_dual_mov_b32 v10, s46
	v_dual_mov_b32 v11, s47 :: v_dual_mov_b32 v12, s48
	v_dual_mov_b32 v13, s49 :: v_dual_mov_b32 v14, s50
	v_dual_mov_b32 v15, s51 :: v_dual_mov_b32 v16, s52
	v_dual_mov_b32 v17, s53 :: v_dual_mov_b32 v18, s54
	v_dual_mov_b32 v19, s55 :: v_dual_mov_b32 v20, s56
	v_dual_mov_b32 v21, s57 :: v_dual_mov_b32 v22, s58
	v_dual_mov_b32 v23, s59 :: v_dual_mov_b32 v24, s60
	v_dual_mov_b32 v25, s61 :: v_dual_mov_b32 v26, s62
	v_dual_mov_b32 v27, s63 :: v_dual_mov_b32 v28, s64
	v_dual_mov_b32 v29, s65 :: v_dual_mov_b32 v30, s66
	v_mov_b32_e32 v31, s67
	s_cmp_lt_i32 s6, 0
	s_cbranch_scc1 .LBB0_16
; %bb.2:                                ; %.preheader121.lr.ph
	s_ashr_i32 s0, s5, 31
	v_ashrrev_i32_e32 v44, 31, v43
	s_add_i32 s1, s5, s0
	s_mov_b32 s37, s36
	s_xor_b32 s1, s1, s0
	s_mov_b32 s38, s36
	v_cvt_f32_u32_e32 v0, s1
	s_sub_i32 s3, 0, s1
	v_add_nc_u32_e32 v2, v43, v44
	s_mov_b32 s39, s36
	s_mov_b32 s40, s36
	v_rcp_iflag_f32_e32 v0, v0
	s_mov_b32 s41, s36
	s_mov_b32 s42, s36
	s_mov_b32 s43, s36
	s_mov_b32 s44, s36
	s_mov_b32 s45, s36
	s_mov_b32 s46, s36
	s_mov_b32 s47, s36
	s_mov_b32 s48, s36
	s_mov_b32 s49, s36
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_mov_b32 s50, s36
	s_mov_b32 s51, s36
	s_mov_b32 s52, s36
	s_mov_b32 s53, s36
	v_cvt_u32_f32_e32 v0, v0
	s_mov_b32 s54, s36
	s_mov_b32 s55, s36
	s_mov_b32 s56, s36
	s_mov_b32 s57, s36
	v_mul_lo_u32 v1, s3, v0
	s_mov_b32 s58, s36
	s_mov_b32 s59, s36
	v_mov_b32_e32 v34, 0
	v_mov_b32_e32 v35, 0
	v_xor_b32_e32 v2, v2, v44
	v_xor_b32_e32 v42, s0, v44
	v_add3_u32 v38, s12, s12, v43
	v_mul_hi_u32 v1, v0, v1
	v_add_f32_e64 v33, s7, s7
	v_lshlrev_b64 v[40:41], 2, v[43:44]
	s_not_b32 s3, s5
	v_ashrrev_i32_e32 v39, 31, v38
	s_mul_i32 s0, s6, s3
	s_ashr_i32 s13, s12, 31
	v_mul_f32_e32 v48, s7, v33
	v_add_nc_u32_e32 v0, v0, v1
	v_lshlrev_b64 v[44:45], 2, v[38:39]
	s_lshl_b64 s[16:17], s[12:13], 2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v46, s2, s2
	s_sub_i32 s7, 0, s6
	v_mul_hi_u32 v0, v2, v0
	s_mul_i32 s13, s5, 12
	s_mov_b32 s20, s7
	v_mul_f32_e32 v51, s2, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v0, s1
	v_sub_nc_u32_e32 v1, v2, v1
	v_add_nc_u32_e32 v2, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s1, v1
	v_cmp_le_u32_e32 vcc_lo, s1, v1
	v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v36, v0, v2, vcc_lo
	v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v13, s49
	v_mov_b32_e32 v11, s47
	v_mov_b32_e32 v1, s37
	v_xor_b32_e32 v47, v36, v42
	v_mad_u64_u32 v[36:37], null, s0, 12, v[32:33]
	v_add_co_u32 v37, vcc_lo, s14, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v49, v47, v42
	v_add_co_ci_u32_e32 v38, vcc_lo, s15, v41, vcc_lo
	v_add_co_u32 v39, vcc_lo, v37, s16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v33, v49, s5
	v_add_co_ci_u32_e32 v40, vcc_lo, s17, v38, vcc_lo
	v_add_co_u32 v41, vcc_lo, s14, v44
	v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v15, s51
	v_dual_mov_b32 v3, s39 :: v_dual_mov_b32 v4, s40
	v_mov_b32_e32 v17, s53
	v_dual_mov_b32 v5, s41 :: v_dual_mov_b32 v6, s42
	v_mov_b32_e32 v19, s55
	v_dual_mov_b32 v7, s43 :: v_dual_mov_b32 v8, s44
	v_mov_b32_e32 v21, s57
	v_dual_mov_b32 v9, s45 :: v_dual_mov_b32 v10, s46
	v_dual_mov_b32 v23, s59 :: v_dual_mov_b32 v12, s48
	v_dual_mov_b32 v25, s61 :: v_dual_mov_b32 v14, s50
	v_dual_mov_b32 v27, s63 :: v_dual_mov_b32 v16, s52
	v_dual_mov_b32 v29, s65 :: v_dual_mov_b32 v18, s54
	v_dual_mov_b32 v31, s67 :: v_dual_mov_b32 v20, s56
	v_mov_b32_e32 v22, s58
	v_mov_b32_e32 v24, s60
	v_mov_b32_e32 v26, s62
	v_mov_b32_e32 v28, s64
	v_mov_b32_e32 v30, s66
	v_add_co_ci_u32_e32 v42, vcc_lo, s15, v45, vcc_lo
	v_sub_nc_u32_e32 v50, v43, v33
.LBB0_3:                                ; %.preheader121
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v33, s20, v50
	v_mov_b32_e32 v43, v36
	s_mul_i32 s21, s20, s20
	s_mov_b32 s22, s7
	v_cmp_lt_i32_e64 s0, -1, v33
	v_cmp_gt_i32_e64 s1, s5, v33
.LBB0_4:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s23, s0
	s_cbranch_execz .LBB0_12
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v44, s22, v49
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v44
	v_cmp_gt_i32_e64 s2, s4, v44
	s_and_b32 s3, s1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s24, s2
	s_cbranch_execz .LBB0_11
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	v_mad_u64_u32 v[45:46], null, v44, s5, v[33:34]
	s_mul_i32 s2, s22, s22
	s_mov_b32 s25, 0
	s_add_i32 s2, s21, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s2, 0, s2
	v_ashrrev_i32_e32 v46, 31, v45
	v_add3_u32 v44, s12, s12, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[46:47], 2, v[45:46]
	v_ashrrev_i32_e32 v45, 31, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[44:45], 2, v[44:45]
	v_add_co_u32 v46, vcc_lo, s14, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v47, vcc_lo, s15, v47, vcc_lo
	v_add_co_u32 v52, vcc_lo, v46, s16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v53, vcc_lo, s17, v47, vcc_lo
	s_clause 0x2
	global_load_b32 v54, v[37:38], off
	global_load_b32 v55, v[39:40], off
	global_load_b32 v52, v[52:53], off
	v_add_co_u32 v44, vcc_lo, s14, v44
	v_add_co_ci_u32_e32 v45, vcc_lo, s15, v45, vcc_lo
	s_clause 0x2
	global_load_b32 v46, v[46:47], off
	global_load_b32 v44, v[44:45], off
	global_load_b32 v45, v[41:42], off
	s_waitcnt vmcnt(2)
	v_dual_sub_f32 v47, v52, v55 :: v_dual_sub_f32 v46, v46, v54
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v47, v47, v47 :: v_dual_sub_f32 v44, v44, v45
	v_cvt_f32_i32_e32 v45, s2
	v_fmac_f32_e32 v47, v46, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v56, vcc_lo, v45, v48, v45
	v_fmac_f32_e32 v47, v44, v44
	v_div_scale_f32 v44, null, v48, v48, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v46, null, 0xc0400000, 0xc0400000, v47
	v_rcp_f32_e32 v52, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v53, v46
	s_waitcnt_depctr 0xfff
	v_fma_f32 v54, -v44, v52, 1.0
	v_fma_f32 v55, -v46, v53, 1.0
	v_fmac_f32_e32 v52, v54, v52
	v_div_scale_f32 v54, s2, v47, 0xc0400000, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v53, v55, v53
	v_mul_f32_e32 v55, v56, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v57, v54, v53
	v_fma_f32 v58, -v44, v55, v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v59, -v46, v57, v54
	v_fmac_f32_e32 v55, v58, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v57, v59, v53
	v_fma_f32 v44, -v44, v55, v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v46, -v46, v57, v54
	v_div_fmas_f32 v44, v44, v52, v55
	s_mov_b32 vcc_lo, s2
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v46, v46, v53, v57
	v_div_fixup_f32 v46, v46, 0xc0400000, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v47, null, v51, v51, v46
	v_div_scale_f32 v54, vcc_lo, v46, v51, v46
	v_rcp_f32_e32 v52, v47
	s_waitcnt_depctr 0xfff
	v_fma_f32 v53, -v47, v52, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v52, v53, v52
	v_mul_f32_e32 v53, v54, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v55, -v47, v53, v54
	v_fmac_f32_e32 v53, v55, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v47, -v47, v53, v54
	v_div_fmas_f32 v47, v47, v52, v53
	v_div_fixup_f32 v52, v44, v48, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v46, v47, v51, v46
	v_mul_f32_e32 v44, 0x3fb8aa3b, v52
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v45, 0x3fb8aa3b, v46
	v_fma_f32 v47, 0x3fb8aa3b, v52, -v44
	v_rndne_f32_e32 v53, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v54, 0x3fb8aa3b, v46, -v45
	v_rndne_f32_e32 v55, v45
	v_dual_fmac_f32 v47, 0x32a5705f, v52 :: v_dual_sub_f32 v44, v44, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v54, 0x32a5705f, v46 :: v_dual_sub_f32 v45, v45, v55
	v_add_f32_e32 v44, v44, v47
	v_cvt_i32_f32_e32 v47, v53
	v_cvt_i32_f32_e32 v53, v55
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v45, v45, v54
	v_exp_f32_e32 v44, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_exp_f32_e32 v45, v45
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v47, v44, v47
	v_ashrrev_i32_e32 v44, 31, v43
	v_ldexp_f32 v45, v45, v53
	v_cndmask_b32_e32 v47, 0, v47, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v46
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v53, 0, v45, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v52
	v_lshlrev_b64 v[44:45], 2, v[43:44]
	v_cndmask_b32_e32 v47, 0x7f800000, v47, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v46
	v_cndmask_b32_e32 v46, 0x7f800000, v53, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v44, vcc_lo, s8, v44
	v_add_co_ci_u32_e32 v45, vcc_lo, s9, v45, vcc_lo
	v_mul_f32_e32 v52, v47, v46
.LBB0_7:                                ; %.preheader120
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_8 Depth 4
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v47, v45 :: v_dual_mov_b32 v46, v44
	s_mov_b64 s[18:19], 0
.LBB0_8:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v53, v[46:47], off
	s_add_i32 s26, s2, s18
	v_add_co_u32 v46, vcc_lo, v46, 4
	s_lshl_b32 s26, s26, 1
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v47, vcc_lo
	s_mov_b32 m0, s26
	s_add_u32 s18, s18, 1
	v_movrels_b32_e32 v56, v1
	v_movrels_b32_e32 v55, v0
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s18, 4
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v53, v52, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[53:54], v53
	v_add_f64 v[53:54], v[55:56], v[53:54]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_movreld_b32_e32 v0, v53
	v_movreld_b32_e32 v1, v54
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=3
	v_add_co_u32 v44, vcc_lo, v44, 16
	s_add_i32 s25, s25, 1
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v45, vcc_lo
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s25, 3
	s_cbranch_scc0 .LBB0_7
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=2
	v_cvt_f64_f32_e32 v[44:45], v52
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[34:35], v[34:35], v[44:45]
.LBB0_11:                               ; %Flow187
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
.LBB0_12:                               ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s23
	v_add_nc_u32_e32 v43, s13, v43
	s_add_i32 s2, s22, 1
	s_cmp_eq_u32 s22, s6
	s_cbranch_scc1 .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s22, s2
	s_branch .LBB0_4
.LBB0_14:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v36, 12, v36
	s_add_i32 s0, s20, 1
	s_cmp_eq_u32 s20, s6
	s_cbranch_scc1 .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s20, s0
	s_branch .LBB0_3
.LBB0_16:                               ; %.preheader119
	v_ashrrev_i32_e32 v33, 31, v32
	s_mov_b32 s4, 0
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[32:33], 2, v[32:33]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v32, vcc_lo, s10, v32
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v33, vcc_lo, s11, v33, vcc_lo
.LBB0_17:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_18 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v37, v33 :: v_dual_mov_b32 v36, v32
	s_mov_b64 s[2:3], 0
.LBB0_18:                               ;   Parent Loop BB0_17 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s0, s2
	s_lshl_b32 s5, s5, 1
	s_add_u32 s2, s2, 1
	s_mov_b32 m0, s5
	s_addc_u32 s3, s3, 0
	v_movrels_b32_e32 v39, v1
	v_movrels_b32_e32 v38, v0
	s_cmp_eq_u32 s2, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[40:41], null, v[34:35], v[34:35], v[38:39]
	v_div_scale_f64 v[46:47], vcc_lo, v[38:39], v[34:35], v[38:39]
	v_rcp_f64_e32 v[42:43], v[40:41]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[44:45], -v[40:41], v[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[42:43], v[42:43], v[44:45], v[42:43]
	v_fma_f64 v[44:45], -v[40:41], v[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[42:43], v[42:43], v[44:45], v[42:43]
	v_mul_f64 v[44:45], v[46:47], v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], -v[40:41], v[44:45], v[46:47]
	v_div_fmas_f64 v[40:41], v[40:41], v[42:43], v[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[38:39], v[40:41], v[34:35], v[38:39]
	v_cvt_f32_f64_e32 v38, v[38:39]
	global_store_b32 v[36:37], v38, off
	v_add_co_u32 v36, vcc_lo, v36, 4
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	s_cbranch_scc0 .LBB0_18
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=1
	v_add_co_u32 v32, vcc_lo, v32, 16
	s_add_i32 s4, s4, 1
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v33, vcc_lo
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s4, 3
	s_cbranch_scc0 .LBB0_17
.LBB0_20:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23bilateral_smooth_kernelPfS_S_iiiff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 60
		.amdhsa_next_free_sgpr 68
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23bilateral_smooth_kernelPfS_S_iiiff, .Lfunc_end0-_Z23bilateral_smooth_kernelPfS_S_iiiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2188
; NumSgprs: 70
; NumVgprs: 60
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 60
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23bilateral_smooth_kernelPfS_S_iiiff
    .private_segment_fixed_size: 0
    .sgpr_count:     70
    .sgpr_spill_count: 0
    .symbol:         _Z23bilateral_smooth_kernelPfS_S_iiiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     60
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
