/*
 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <iostream>
#include <cuda_runtime_api.h>
#include <cuda_fp16.h>

namespace nvinfer1
{
namespace plugin
{
const int PILLARS_PER_BLOCK = 64;
const int PILLAR_FEATURE_SIZE = 64;

template <typename Element>
__global__ void scatterBEV_kernel(const Element *pillar_features_data,
          const unsigned int *coords_data, const unsigned int *params_data,
          unsigned int featureX, unsigned int featureY,
          Element *spatial_feature_data)
{
    int pillar_idx = blockIdx.x * PILLARS_PER_BLOCK + threadIdx.x;
    int valid_pillars_inBlock = PILLARS_PER_BLOCK;
    const int num_pillars = params_data[0];
    int valid_blocks = (num_pillars+PILLARS_PER_BLOCK-1)/PILLARS_PER_BLOCK;
    if(blockIdx.x >= valid_blocks) return;
    if(blockIdx.x == (valid_blocks-1)) {
      valid_pillars_inBlock = num_pillars % PILLARS_PER_BLOCK;
    }
    valid_pillars_inBlock = (valid_pillars_inBlock==0) ? PILLARS_PER_BLOCK : valid_pillars_inBlock;
    __shared__ Element pillarSM[PILLARS_PER_BLOCK][PILLAR_FEATURE_SIZE]; //pillar*64
    for (int i = 0; i < valid_pillars_inBlock; i++)
    {
      pillarSM[i][threadIdx.x] = pillar_features_data[ (blockIdx.x * PILLARS_PER_BLOCK +i)*PILLAR_FEATURE_SIZE + threadIdx.x];
    }
    __syncthreads();
    if(pillar_idx >= num_pillars) return;
    int4 coord = ((const int4 *)coords_data)[pillar_idx];
    int x = coord.w;
    int y = coord.z;
    for (int i = 0; i < PILLAR_FEATURE_SIZE; i++)
    {
      spatial_feature_data[i*featureY*featureX + y*featureX + x] = pillarSM[threadIdx.x][i];
    }
}

template <typename Element>
int pillarScatterKernelLaunch(
  int batch_size,
  int max_pillar_num,
  int num_features,
  const Element *pillar_features_data,
  const unsigned int *coords_data,
  const unsigned int *params_data,
  unsigned int featureX, unsigned int featureY,
  Element *spatial_feature_data,
  cudaStream_t stream)
{
    dim3 blocks( (featureX*featureY+PILLARS_PER_BLOCK-1)/PILLARS_PER_BLOCK);
    dim3 threads(PILLARS_PER_BLOCK);
    for (int b = 0; b < batch_size; b++) {
      scatterBEV_kernel<Element><<<blocks, threads, 0, stream>>>
        (pillar_features_data + b*max_pillar_num*num_features,
         coords_data + b*max_pillar_num*4,
         params_data + b,
         featureX,
         featureY,
         spatial_feature_data + b*num_features*featureX*featureY
        );
      auto err = cudaGetLastError();
      if (cudaSuccess != err) {
          fprintf(stderr, "CUDA kernel failed : %s\n", cudaGetErrorString(err));
          return -1;
      }
    }
    return 0;
}

template int pillarScatterKernelLaunch<half>(
  int batch_size,
  int max_pillar_num,
  int num_features,
  const half *pillar_features_data,
  const unsigned int *coords_data,
  const unsigned int *params_data,
  unsigned int featureX, unsigned int featureY,
  half *spatial_feature_data,
  cudaStream_t stream);

template int pillarScatterKernelLaunch<float>(
  int batch_size,
  int max_pillar_num,
  int num_features,
  const float *pillar_features_data,
  const unsigned int *coords_data,
  const unsigned int *params_data,
  unsigned int featureX, unsigned int featureY,
  float *spatial_feature_data,
  cudaStream_t stream);
} // namespace plugin
} // namespace nvinfer1

	.file	"tmpxft_0033809e_00000000-6_pillarScatterKernels.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4014:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4014:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL79__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_PK6__halfPKjS3_jjPS_, @function
_ZL79__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_PK6__halfPKjS3_jjPS_:
.LFB4036:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4036:
	.size	_ZL79__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_PK6__halfPKjS3_jjPS_, .-_ZL79__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_PK6__halfPKjS3_jjPS_
	.type	_ZL73__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_PKfPKjS2_jjPf, @function
_ZL73__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_PKfPKjS2_jjPf:
.LFB4038:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L7:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4038:
	.size	_ZL73__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_PKfPKjS2_jjPf, .-_ZL73__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_PKfPKjS2_jjPf
	.section	.text._ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,"axG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,comdat
	.weak	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.type	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_, @function
_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_:
.LFB4343:
	.cfi_startproc
	endbr64
	jmp	_ZL79__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_PK6__halfPKjS3_jjPS_
	.cfi_endproc
.LFE4343:
	.size	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_, .-_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.section	.text._ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,"axG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,comdat
	.weak	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.type	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_, @function
_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_:
.LFB4345:
	.cfi_startproc
	endbr64
	jmp	_ZL73__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_PKfPKjS2_jjPf
	.cfi_endproc
.LFE4345:
	.size	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_, .-_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.section	.rodata._ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA kernel failed : %s\n"
	.section	.text._ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st,"axG",@progbits,_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st,comdat
	.weak	_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st
	.type	_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st, @function
_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st:
.LFB4341:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %eax
	movq	%r8, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movabsq	$4294967297, %rbx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	128(%rsp), %ecx
	imull	136(%rsp), %ecx
	movq	%rbx, 44(%rsp)
	addq	$63, %rbx
	movq	%rbx, 52(%rsp)
	leal	0(,%rsi,4), %ebx
	imull	%eax, %esi
	movl	%edi, 28(%rsp)
	leal	63(%rcx), %edx
	movl	$1, 60(%rsp)
	imull	%eax, %ecx
	shrl	$6, %edx
	movq	%r9, 8(%rsp)
	movl	%edx, 40(%rsp)
	movl	%esi, 16(%rsp)
	movl	%ecx, 24(%rsp)
	movl	%ebx, 20(%rsp)
	xorl	%ebx, %ebx
.L14:
	movl	28(%rsp), %eax
	cmpl	%eax, %ebx
	jge	.L20
	movl	60(%rsp), %ecx
	movq	152(%rsp), %r9
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdx
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movslq	%r13d, %rdx
	movl	%r12d, %eax
	movslq	%ebp, %rdi
	movl	128(%rsp), %ecx
	leaq	(%r15,%rdx,4), %rsi
	addq	%rax, %rax
	movq	144(%rsp), %rdx
	addq	%rdi, %rdi
	movl	136(%rsp), %r8d
	addq	%r14, %rdi
	leaq	(%rdx,%rax), %r9
	movq	8(%rsp), %rdx
	call	_ZL79__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_PK6__halfPKjS3_jjPS_
.L15:
	call	cudaGetLastError@PLT
	addq	$4, 8(%rsp)
	movl	%eax, %edi
	movl	24(%rsp), %eax
	addl	%eax, %r12d
	movl	20(%rsp), %eax
	addl	%eax, %r13d
	movl	16(%rsp), %eax
	addl	%eax, %ebp
	testl	%edi, %edi
	je	.L16
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %eax
	jmp	.L13
.L16:
	incl	%ebx
	jmp	.L14
.L20:
	xorl	%eax, %eax
.L13:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4341:
	.size	_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st, .-_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P11CUstream_st
	.section	.text._ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P11CUstream_st,"axG",@progbits,_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P11CUstream_st,comdat
	.weak	_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P11CUstream_st
	.type	_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P11CUstream_st, @function
_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P11CUstream_st:
.LFB4342:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%edx, %eax
	movq	%r8, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movabsq	$4294967297, %rbx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	128(%rsp), %ecx
	imull	136(%rsp), %ecx
	movq	%rbx, 44(%rsp)
	addq	$63, %rbx
	movq	%rbx, 52(%rsp)
	leal	0(,%rsi,4), %ebx
	imull	%eax, %esi
	movl	%edi, 28(%rsp)
	leal	63(%rcx), %edx
	movl	$1, 60(%rsp)
	imull	%eax, %ecx
	shrl	$6, %edx
	movq	%r9, 8(%rsp)
	movl	%edx, 40(%rsp)
	movl	%esi, 16(%rsp)
	movl	%ecx, 24(%rsp)
	movl	%ebx, 20(%rsp)
	xorl	%ebx, %ebx
.L22:
	movl	28(%rsp), %eax
	cmpl	%eax, %ebx
	jge	.L28
	movl	60(%rsp), %ecx
	movq	152(%rsp), %r9
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdx
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movslq	%r13d, %rdx
	movl	%r12d, %eax
	movl	136(%rsp), %r8d
	movl	128(%rsp), %ecx
	leaq	(%r15,%rdx,4), %rsi
	movslq	%ebp, %rdx
	leaq	(%r14,%rdx,4), %rdi
	movq	144(%rsp), %rdx
	leaq	(%rdx,%rax,4), %r9
	movq	8(%rsp), %rdx
	call	_ZL73__device_stub__ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_PKfPKjS2_jjPf
.L23:
	call	cudaGetLastError@PLT
	addq	$4, 8(%rsp)
	movl	%eax, %edi
	movl	24(%rsp), %eax
	addl	%eax, %r12d
	movl	20(%rsp), %eax
	addl	%eax, %r13d
	movl	16(%rsp), %eax
	addl	%eax, %ebp
	testl	%edi, %edi
	je	.L24
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %eax
	jmp	.L21
.L24:
	incl	%ebx
	jmp	.L22
.L28:
	xorl	%eax, %eax
.L21:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4342:
	.size	_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P11CUstream_st, .-_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P11CUstream_st
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_"
.LC2:
	.string	"_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4041:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4041:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */


#include <hip/hip_runtime.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
#include <hip/hip_fp16.h>

namespace nvinfer1
{
namespace plugin
{
const int PILLARS_PER_BLOCK = 64;
const int PILLAR_FEATURE_SIZE = 64;

template <typename Element>
__global__ void scatterBEV_kernel(const Element *pillar_features_data,
          const unsigned int *coords_data, const unsigned int *params_data,
          unsigned int featureX, unsigned int featureY,
          Element *spatial_feature_data)
{
    int pillar_idx = blockIdx.x * PILLARS_PER_BLOCK + threadIdx.x;
    int valid_pillars_inBlock = PILLARS_PER_BLOCK;
    const int num_pillars = params_data[0];
    int valid_blocks = (num_pillars+PILLARS_PER_BLOCK-1)/PILLARS_PER_BLOCK;
    if(blockIdx.x >= valid_blocks) return;
    if(blockIdx.x == (valid_blocks-1)) {
      valid_pillars_inBlock = num_pillars % PILLARS_PER_BLOCK;
    }
    valid_pillars_inBlock = (valid_pillars_inBlock==0) ? PILLARS_PER_BLOCK : valid_pillars_inBlock;
    __shared__ Element pillarSM[PILLARS_PER_BLOCK][PILLAR_FEATURE_SIZE]; //pillar*64
    for (int i = 0; i < valid_pillars_inBlock; i++)
    {
      pillarSM[i][threadIdx.x] = pillar_features_data[ (blockIdx.x * PILLARS_PER_BLOCK +i)*PILLAR_FEATURE_SIZE + threadIdx.x];
    }
    __syncthreads();
    if(pillar_idx >= num_pillars) return;
    int4 coord = ((const int4 *)coords_data)[pillar_idx];
    int x = coord.w;
    int y = coord.z;
    for (int i = 0; i < PILLAR_FEATURE_SIZE; i++)
    {
      spatial_feature_data[i*featureY*featureX + y*featureX + x] = pillarSM[threadIdx.x][i];
    }
}

template <typename Element>
int pillarScatterKernelLaunch(
  int batch_size,
  int max_pillar_num,
  int num_features,
  const Element *pillar_features_data,
  const unsigned int *coords_data,
  const unsigned int *params_data,
  unsigned int featureX, unsigned int featureY,
  Element *spatial_feature_data,
  hipStream_t stream)
{
    dim3 blocks( (featureX*featureY+PILLARS_PER_BLOCK-1)/PILLARS_PER_BLOCK);
    dim3 threads(PILLARS_PER_BLOCK);
    for (int b = 0; b < batch_size; b++) {
      scatterBEV_kernel<Element><<<blocks, threads, 0, stream>>>
        (pillar_features_data + b*max_pillar_num*num_features,
         coords_data + b*max_pillar_num*4,
         params_data + b,
         featureX,
         featureY,
         spatial_feature_data + b*num_features*featureX*featureY
        );
      auto err = hipGetLastError();
      if (hipSuccess != err) {
          fprintf(stderr, "CUDA kernel failed : %s\n", hipGetErrorString(err));
          return -1;
      }
    }
    return 0;
}

template int pillarScatterKernelLaunch<half>(
  int batch_size,
  int max_pillar_num,
  int num_features,
  const half *pillar_features_data,
  const unsigned int *coords_data,
  const unsigned int *params_data,
  unsigned int featureX, unsigned int featureY,
  half *spatial_feature_data,
  hipStream_t stream);

template int pillarScatterKernelLaunch<float>(
  int batch_size,
  int max_pillar_num,
  int num_features,
  const float *pillar_features_data,
  const unsigned int *coords_data,
  const unsigned int *params_data,
  unsigned int featureX, unsigned int featureY,
  float *spatial_feature_data,
  hipStream_t stream);
} // namespace plugin
} // namespace nvinfer1

	.text
	.file	"pillarScatterKernels.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.text._ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t,"axG",@progbits,_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t,comdat
	.weak	_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t # -- Begin function _ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t
	.type	_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t,@function
_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t: # @_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, 16(%rsp)                   # 8-byte Spill
	xorl	%r14d, %r14d
	testl	%edi, %edi
	jle	.LBB0_1
# %bb.2:                                # %.lr.ph
	movq	%r9, %rbx
	movq	%rcx, %r15
	movl	136(%rsp), %eax
	movabsq	$4294967296, %rcx               # imm = 0x100000000
                                        # kill: def $eax killed $eax def $rax
	imull	128(%rsp), %eax
	leal	63(%rax), %r8d
	shrl	$6, %r8d
	btsq	$32, %r8
	movq	%r8, 56(%rsp)                   # 8-byte Spill
	movl	%edi, %edi
	movslq	%esi, %rsi
	movslq	%edx, %rdx
	leal	(,%rsi,4), %r8d
	movl	%r8d, 12(%rsp)                  # 4-byte Spill
	imulq	%rdx, %rsi
	addq	%rsi, %rsi
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	imull	%eax, %edx
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	negq	%rdi
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movb	$1, %r12b
	movl	$1, %ebp
	addq	$64, %rcx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	xorl	%r13d, %r13d
.LBB0_4:                                # =>This Inner Loop Header: Depth=1
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	152(%rsp), %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_6
# %bb.5:                                #   in Loop: Header=BB0_4 Depth=1
	movslq	%r13d, %rax
	movq	16(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rsi
	movl	%r14d, %eax
	movq	144(%rsp), %rcx
	leaq	(%rcx,%rax,2), %r9
	movq	%r15, %rdi
	movq	%rbx, %rdx
	movl	128(%rsp), %ecx
	movl	136(%rsp), %r8d
	callq	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
.LBB0_6:                                # %.critedge
                                        #   in Loop: Header=BB0_4 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_7
# %bb.3:                                #   in Loop: Header=BB0_4 Depth=1
	cmpq	48(%rsp), %rbp                  # 8-byte Folded Reload
	setb	%r12b
	addl	12(%rsp), %r13d                 # 4-byte Folded Reload
	addq	40(%rsp), %r15                  # 8-byte Folded Reload
	addq	$4, %rbx
	addl	32(%rsp), %r14d                 # 4-byte Folded Reload
	movq	24(%rsp), %rax                  # 8-byte Reload
	addq	%rbp, %rax
	incq	%rax
	incq	%rbp
	cmpq	$1, %rax
	jne	.LBB0_4
	jmp	.LBB0_8
.LBB0_1:
	xorl	%r12d, %r12d
.LBB0_8:                                # %.loopexit
	movzbl	%r12b, %eax
	andl	$1, %eax
	negl	%eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_7:
	.cfi_def_cfa_offset 128
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB0_8
.Lfunc_end0:
	.size	_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t, .Lfunc_end0-_ZN8nvinfer16plugin25pillarScatterKernelLaunchI6__halfEEiiiiPKT_PKjS7_jjPS3_P12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,"axG",@progbits,_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,comdat
	.weak	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_ # -- Begin function _ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.type	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,@function
_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_: # @_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_, .Lfunc_end1-_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t,"axG",@progbits,_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t,comdat
	.weak	_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t # -- Begin function _ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t
	.type	_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t,@function
_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t: # @_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, 16(%rsp)                   # 8-byte Spill
	xorl	%r14d, %r14d
	testl	%edi, %edi
	jle	.LBB2_1
# %bb.2:                                # %.lr.ph
	movq	%r9, %rbx
	movq	%rcx, %r15
	movl	136(%rsp), %eax
	movabsq	$4294967296, %rcx               # imm = 0x100000000
                                        # kill: def $eax killed $eax def $rax
	imull	128(%rsp), %eax
	leal	63(%rax), %r8d
	shrl	$6, %r8d
	btsq	$32, %r8
	movq	%r8, 56(%rsp)                   # 8-byte Spill
	movl	%edi, %edi
	movslq	%esi, %rsi
	movslq	%edx, %rdx
	leal	(,%rsi,4), %r8d
	movl	%r8d, 12(%rsp)                  # 4-byte Spill
	imulq	%rdx, %rsi
	shlq	$2, %rsi
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	imull	%eax, %edx
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	negq	%rdi
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movb	$1, %r12b
	movl	$1, %ebp
	addq	$64, %rcx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	xorl	%r13d, %r13d
.LBB2_4:                                # =>This Inner Loop Header: Depth=1
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	152(%rsp), %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:                                #   in Loop: Header=BB2_4 Depth=1
	movslq	%r13d, %rax
	movq	16(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rsi
	movl	%r14d, %eax
	movq	144(%rsp), %rcx
	leaq	(%rcx,%rax,4), %r9
	movq	%r15, %rdi
	movq	%rbx, %rdx
	movl	128(%rsp), %ecx
	movl	136(%rsp), %r8d
	callq	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
.LBB2_6:                                # %.critedge
                                        #   in Loop: Header=BB2_4 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.3:                                #   in Loop: Header=BB2_4 Depth=1
	cmpq	48(%rsp), %rbp                  # 8-byte Folded Reload
	setb	%r12b
	addl	12(%rsp), %r13d                 # 4-byte Folded Reload
	addq	40(%rsp), %r15                  # 8-byte Folded Reload
	addq	$4, %rbx
	addl	32(%rsp), %r14d                 # 4-byte Folded Reload
	movq	24(%rsp), %rax                  # 8-byte Reload
	addq	%rbp, %rax
	incq	%rax
	incq	%rbp
	cmpq	$1, %rax
	jne	.LBB2_4
	jmp	.LBB2_8
.LBB2_1:
	xorl	%r12d, %r12d
.LBB2_8:                                # %.loopexit
	movzbl	%r12b, %eax
	andl	$1, %eax
	negl	%eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_7:
	.cfi_def_cfa_offset 128
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB2_8
.Lfunc_end2:
	.size	_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t, .Lfunc_end2-_ZN8nvinfer16plugin25pillarScatterKernelLaunchIfEEiiiiPKT_PKjS6_jjPS2_P12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,"axG",@progbits,_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,comdat
	.weak	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_ # -- Begin function _ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.type	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,@function
_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_: # @_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_, .Lfunc_end3-_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,@object # @_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.section	.rodata._ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,"aG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,comdat
	.weak	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.p2align	3, 0x0
_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_:
	.quad	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.size	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA kernel failed : %s\n"
	.size	.L.str, 25

	.type	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,@object # @_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.section	.rodata._ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,"aG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,comdat
	.weak	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.p2align	3, 0x0
_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_:
	.quad	_ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.size	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_"
	.size	.L__unnamed_1, 66

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_"
	.size	.L__unnamed_2, 60

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.addrsig_sym _ZN8nvinfer16plugin32__device_stub__scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.addrsig_sym _ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,"axG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,comdat
	.protected	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_ ; -- Begin function _ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.globl	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
	.p2align	8
	.type	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,@function
_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_: ; @_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s2, 63
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s4, s3, 31
	s_lshr_b32 s4, s4, 26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s4
	s_ashr_i32 s3, s3, 6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s15, s3
	s_cbranch_scc1 .LBB0_7
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_ashr_i32 s8, s2, 31
	s_add_i32 s3, s3, -1
	s_lshr_b32 s8, s8, 26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s2, s8
	s_and_not1_b32 s8, s8, 63
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s8, s2, s8
	s_cmp_eq_u32 s15, s3
	s_cselect_b32 s3, s8, 64
	s_cmp_lg_u32 s3, 0
	s_cselect_b32 s3, s3, 64
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_lshl_or_b32 v1, s15, 12, v0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 1, v0
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[4:5], 1, v[1:2]
	v_add_nc_u32_e32 v1, 64, v1
	s_add_i32 s3, s3, -1
	s_cmp_eq_u32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_u16 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b16 v3, v4
	v_add_nc_u32_e32 v3, 0x80, v3
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %._crit_edge
	v_lshl_add_u32 v1, s15, 6, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.5:
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b128 s[0:3], s[0:1], 0x18
	v_lshlrev_b32_e32 v0, 7, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 4, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b64 v[3:4], v[1:2], off offset:8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, v3, s0, v[4:5]
	v_mov_b32_e32 v2, 0
	s_mul_i32 s0, s1, s0
	s_mov_b32 s1, 0
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_add_i32 s1, s1, 2
	s_cmpk_lg_i32 s1, 0x80
	ds_load_u16 v5, v3
	v_lshlrev_b64 v[3:4], 1, v[1:2]
	v_add_nc_u32_e32 v1, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b16 v[3:4], v5, off
	s_cbranch_scc1 .LBB0_6
.LBB0_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,"axG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_,comdat
.Lfunc_end0:
	.size	_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_, .Lfunc_end0-_ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 416
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,"axG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,comdat
	.protected	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_ ; -- Begin function _ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.globl	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
	.p2align	8
	.type	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,@function
_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_: ; @_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s2, 63
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s4, s3, 31
	s_lshr_b32 s4, s4, 26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s4
	s_ashr_i32 s3, s3, 6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s15, s3
	s_cbranch_scc1 .LBB1_7
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_ashr_i32 s8, s2, 31
	s_add_i32 s3, s3, -1
	s_lshr_b32 s8, s8, 26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s2, s8
	s_and_not1_b32 s8, s8, 63
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s8, s2, s8
	s_cmp_eq_u32 s15, s3
	s_cselect_b32 s3, s8, 64
	s_cmp_lg_u32 s3, 0
	s_cselect_b32 s3, s3, 64
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph
	v_lshl_or_b32 v1, s15, 12, v0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_nc_u32_e32 v1, 64, v1
	s_add_i32 s3, s3, -1
	s_cmp_eq_u32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	v_add_nc_u32_e32 v3, 0x100, v3
	s_cbranch_scc0 .LBB1_3
.LBB1_4:                                ; %._crit_edge
	v_lshl_add_u32 v1, s15, 6, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_7
; %bb.5:
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b128 s[0:3], s[0:1], 0x18
	v_lshlrev_b32_e32 v0, 8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 4, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b64 v[3:4], v[1:2], off offset:8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, v3, s0, v[4:5]
	v_mov_b32_e32 v2, 0
	s_mul_i32 s0, s1, s0
	s_mov_b32 s1, 0
.LBB1_6:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_add_i32 s1, s1, 4
	s_cmpk_lg_i32 s1, 0x100
	ds_load_b32 v5, v3
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v1, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[3:4], v5, off
	s_cbranch_scc1 .LBB1_6
.LBB1_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,"axG",@progbits,_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_,comdat
.Lfunc_end1:
	.size	_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_, .Lfunc_end1-_ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 416
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN8nvinfer16plugin17scatterBEV_kernelI6__halfEEvPKT_PKjS7_jjPS3_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN8nvinfer16plugin17scatterBEV_kernelIfEEvPKT_PKjS6_jjPS2_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
