#include "includes.h"
__global__ void MHDComputedUz_CUDA3_kernel(float *FluxD, float *FluxS1, float *FluxS2, float *FluxS3, float *FluxTau, float *FluxBx, float *FluxBy, float *FluxBz, float *FluxPhi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dtdx, int size, int dim0, int dim1, int dim2)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;

int igridz = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;


if (igridz < 2 || igridz > size - 3)
return;

int j = igridz / (dim0*dim2);
int i = (igridz - j*dim0*dim2) / dim2;
int k = igridz - j*dim0*dim2 - i*dim2;
int igrid = i + (j + k*dim1) * dim0;

int igridzp1 = igridz + 1;
j = igridzp1 / (dim0*dim2);
i = (igridzp1 - j*dim0*dim2) / dim2;
k = igridzp1 - j*dim0*dim2 - i*dim2;
int igridp1 = i + (j + k*dim1) * dim0;

dUD  [igrid] += (FluxD  [igrid] - FluxD  [igridp1])*dtdx;
dUS1 [igrid] += (FluxS1 [igrid] - FluxS1 [igridp1])*dtdx;
dUS2 [igrid] += (FluxS2 [igrid] - FluxS2 [igridp1])*dtdx;
dUS3 [igrid] += (FluxS3 [igrid] - FluxS3 [igridp1])*dtdx;
dUTau[igrid] += (FluxTau[igrid] - FluxTau[igridp1])*dtdx;
dUBx [igrid] += (FluxBx [igrid] - FluxBx [igridp1])*dtdx;
dUBy [igrid] += (FluxBy [igrid] - FluxBy [igridp1])*dtdx;
dUBz [igrid] += (FluxBz [igrid] - FluxBz [igridp1])*dtdx;
dUPhi[igrid] += (FluxPhi[igrid] - FluxPhi[igridp1])*dtdx;

}
	.file	"tmpxft_0030bfe8_00000000-6_MHDComputedUz_CUDA3_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z85__device_stub__Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.type	_Z85__device_stub__Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, @function
_Z85__device_stub__Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$424, %rsp
	.cfi_def_cfa_offset 432
	movq	432(%rsp), %rax
	movq	%rdi, 152(%rsp)
	leaq	176(%rsp), %rdi
	movq	%rsi, 144(%rsp)
	leaq	188(%rsp), %rsi
	movq	%rax, 104(%rsp)
	movq	440(%rsp), %rax
	movq	%rdx, 136(%rsp)
	leaq	160(%rsp), %rdx
	movq	%rax, 96(%rsp)
	movq	448(%rsp), %rax
	movq	%rcx, 128(%rsp)
	leaq	168(%rsp), %rcx
	movq	%rax, 88(%rsp)
	movq	456(%rsp), %rax
	movq	%r8, 120(%rsp)
	movq	%rax, 80(%rsp)
	movq	464(%rsp), %rax
	movq	%r9, 112(%rsp)
	movq	%rax, 72(%rsp)
	movq	472(%rsp), %rax
	movss	%xmm0, 12(%rsp)
	movq	%rax, 64(%rsp)
	movq	480(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	488(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	496(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	504(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	512(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	520(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 408(%rsp)
	xorl	%eax, %eax
	leaq	152(%rsp), %rax
	movl	$1, 184(%rsp)
	movq	%rax, 224(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	528(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	536(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	544(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	552(%rsp), %rax
	movq	%rax, 400(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 176(%rsp)
	movq	%rax, 188(%rsp)
	movl	$1, 196(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	168(%rsp)
	.cfi_def_cfa_offset 440
	leaq	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii(%rip), %rdi
	pushq	168(%rsp)
	.cfi_def_cfa_offset 448
	movq	204(%rsp), %rcx
	movl	212(%rsp), %r8d
	movq	192(%rsp), %rsi
	movl	200(%rsp), %edx
	leaq	240(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 440
	popq	%rdx
	.cfi_def_cfa_offset 432
.L2:
	movq	408(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$424, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z85__device_stub__Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, .-_Z85__device_stub__Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.globl	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.type	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, @function
_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z85__device_stub__Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.cfi_endproc
.LFE2033:
	.size	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, .-_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MHDComputedUz_CUDA3_kernel(float *FluxD, float *FluxS1, float *FluxS2, float *FluxS3, float *FluxTau, float *FluxBx, float *FluxBy, float *FluxBz, float *FluxPhi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dtdx, int size, int dim0, int dim1, int dim2)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;

int igridz = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;


if (igridz < 2 || igridz > size - 3)
return;

int j = igridz / (dim0*dim2);
int i = (igridz - j*dim0*dim2) / dim2;
int k = igridz - j*dim0*dim2 - i*dim2;
int igrid = i + (j + k*dim1) * dim0;

int igridzp1 = igridz + 1;
j = igridzp1 / (dim0*dim2);
i = (igridzp1 - j*dim0*dim2) / dim2;
k = igridzp1 - j*dim0*dim2 - i*dim2;
int igridp1 = i + (j + k*dim1) * dim0;

dUD  [igrid] += (FluxD  [igrid] - FluxD  [igridp1])*dtdx;
dUS1 [igrid] += (FluxS1 [igrid] - FluxS1 [igridp1])*dtdx;
dUS2 [igrid] += (FluxS2 [igrid] - FluxS2 [igridp1])*dtdx;
dUS3 [igrid] += (FluxS3 [igrid] - FluxS3 [igridp1])*dtdx;
dUTau[igrid] += (FluxTau[igrid] - FluxTau[igridp1])*dtdx;
dUBx [igrid] += (FluxBx [igrid] - FluxBx [igridp1])*dtdx;
dUBy [igrid] += (FluxBy [igrid] - FluxBy [igridp1])*dtdx;
dUBz [igrid] += (FluxBz [igrid] - FluxBz [igridp1])*dtdx;
dUPhi[igrid] += (FluxPhi[igrid] - FluxPhi[igridp1])*dtdx;

}
	.text
	.file	"MHDComputedUz_CUDA3_kernel.hip"
	.globl	_Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii # -- Begin function _Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.type	_Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii,@function
_Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii: # @_Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$304, %rsp                      # imm = 0x130
	.cfi_def_cfa_offset 352
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	112(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	352(%rsp), %rcx
	movq	%rcx, 48(%rbx)
	leaq	360(%rsp), %rcx
	movq	%rcx, 56(%rbx)
	leaq	368(%rsp), %rcx
	movq	%rcx, 64(%rbx)
	leaq	376(%rsp), %rcx
	movq	%rcx, 72(%rbx)
	leaq	384(%rsp), %rcx
	movq	%rcx, 80(%rbx)
	leaq	392(%rsp), %rcx
	movq	%rcx, 88(%rbx)
	leaq	400(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	408(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	leaq	416(%rsp), %rcx
	movq	%rcx, 112(%rbx)
	leaq	424(%rsp), %rcx
	movq	%rcx, 120(%rbx)
	leaq	432(%rsp), %rcx
	movq	%rcx, 128(%rbx)
	leaq	440(%rsp), %rcx
	movq	%rcx, 136(%rbx)
	movq	%rax, 144(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$320, %rsp                      # imm = 0x140
	.cfi_adjust_cfa_offset -320
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, .Lfunc_end0-_Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii,@object # @_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.section	.rodata,"a",@progbits
	.globl	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.p2align	3, 0x0
_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii:
	.quad	_Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.size	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii"
	.size	.L__unnamed_1, 72

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii ; -- Begin function _Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.globl	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
	.p2align	8
	.type	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii,@function
_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii: ; @_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
; %bb.0:
	s_load_b128 s[36:39], s[0:1], 0x90
	s_lshl_b32 s2, s14, 6
	s_mul_i32 s15, s15, 0xa000
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s15, s2, v0
	v_cmp_lt_i32_e32 vcc_lo, 1, v0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s37, -3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s2, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0xa0
	s_load_b128 s[40:43], s[0:1], 0x80
	v_ashrrev_i32_e32 v4, 31, v0
	v_add_nc_u32_e32 v3, 1, v0
	s_load_b512 s[16:31], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v0, v4
	v_ashrrev_i32_e32 v5, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v6, v4
	v_add_nc_u32_e32 v7, v3, v5
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s3, s38
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s2, s4, 31
	s_add_i32 s5, s4, s2
	v_xor_b32_e32 v4, s2, v4
	s_xor_b32 s5, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s5
	s_sub_i32 s6, 0, s5
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s6, v1
	s_ashr_i32 s6, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s7, s3, s6
	s_xor_b32 s7, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	v_xor_b32_e32 v2, v7, v5
	v_xor_b32_e32 v5, s2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, v6, v1
	v_mul_hi_u32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v7, s5
	v_mul_lo_u32 v9, v1, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v8
	v_sub_nc_u32_e32 v2, v2, v9
	v_add_nc_u32_e32 v8, 1, v7
	v_add_nc_u32_e32 v9, 1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v10, s5, v6
	v_cmp_le_u32_e32 vcc_lo, s5, v6
	v_cmp_le_u32_e64 s2, s5, v2
	v_cndmask_b32_e32 v6, v6, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v9, s2
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_subrev_nc_u32_e32 v8, s5, v2
	v_cvt_f32_u32_e32 v10, s7
	v_cmp_le_u32_e32 vcc_lo, s5, v6
	v_cndmask_b32_e64 v2, v2, v8, s2
	v_add_nc_u32_e32 v8, 1, v1
	v_add_nc_u32_e32 v9, 1, v7
	s_sub_i32 s2, 0, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v7, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	v_rcp_iflag_f32_e32 v7, v10
	v_xor_b32_e32 v2, v6, v4
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v1, v5
	v_sub_nc_u32_e32 v1, v2, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v7
	v_sub_nc_u32_e32 v2, v6, v5
	v_mul_lo_u32 v5, s4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v6, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v7, s2, v4
	v_sub_nc_u32_e32 v5, v0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v3, v6
	v_ashrrev_i32_e32 v0, 31, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, v4, v7
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v5, v0
	v_add_nc_u32_e32 v9, v6, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v4, v3
	v_xor_b32_e32 v4, v8, v0
	v_xor_b32_e32 v0, s6, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v9, v7
	v_xor_b32_e32 v7, s6, v7
	v_mul_hi_u32 v9, v4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v8, v3
	v_mul_lo_u32 v10, v9, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v3, s7
	v_sub_nc_u32_e32 v4, v4, v10
	v_add_nc_u32_e32 v10, 1, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v8, v8, v11
	v_add_nc_u32_e32 v11, 1, v3
	v_subrev_nc_u32_e32 v12, s7, v4
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e64 s2, s7, v8
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	v_subrev_nc_u32_e32 v10, s7, v8
	v_cndmask_b32_e32 v4, v4, v12, vcc_lo
	v_cndmask_b32_e64 v3, v3, v11, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v11, 1, v9
	v_cndmask_b32_e64 v8, v8, v10, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	v_add_nc_u32_e32 v10, 1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, v9, v11, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v4, v0
	v_cndmask_b32_e32 v3, v3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v4, v0
	v_xor_b32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v0, s3
	v_sub_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v7, v3, s3
	s_load_b512 s[0:15], s[0:1], 0x40
	v_sub_nc_u32_e32 v8, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v8, s39, v[1:2]
	v_sub_nc_u32_e32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, v7, s39, v[2:3]
	v_mad_u64_u32 v[1:2], null, v4, s38, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, v5, s38, v[3:4]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[6:7]
	v_add_co_u32 v4, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v10, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v12, v[8:9], off
	v_add_co_u32 v4, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s19, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v10, v10, v6
	v_add_co_u32 v6, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, s36, v10
	v_add_co_u32 v10, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[8:9], v12, off
	s_clause 0x1
	global_load_b32 v8, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v12, v[10:11], off
	v_add_co_u32 v4, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v8, v8, v6
	v_add_co_u32 v6, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, s36, v8
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[10:11], v12, off
	s_clause 0x1
	global_load_b32 v10, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v12, v[8:9], off
	v_add_co_u32 v4, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v10, v10, v6
	v_add_co_u32 v6, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s23, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, s36, v10
	v_add_co_u32 v10, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[8:9], v12, off
	s_clause 0x1
	global_load_b32 v8, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v12, v[10:11], off
	v_add_co_u32 v4, vcc_lo, s24, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v8, v8, v6
	v_add_co_u32 v6, vcc_lo, s24, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, s36, v8
	v_add_co_u32 v8, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[10:11], v12, off
	s_clause 0x1
	global_load_b32 v10, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v12, v[8:9], off
	v_add_co_u32 v4, vcc_lo, s26, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v10, v10, v6
	v_add_co_u32 v6, vcc_lo, s26, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s27, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, s36, v10
	v_add_co_u32 v10, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v1, vcc_lo
	global_store_b32 v[8:9], v12, off
	s_clause 0x1
	global_load_b32 v8, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v12, v[10:11], off
	v_add_co_u32 v4, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s29, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v8, v8, v6
	v_add_co_u32 v6, vcc_lo, s28, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, s36, v8
	v_add_co_u32 v8, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v1, vcc_lo
	global_store_b32 v[10:11], v12, off
	s_clause 0x1
	global_load_b32 v10, v[4:5], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v12, v[8:9], off
	v_add_co_u32 v4, vcc_lo, s30, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s31, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v10, v10, v6
	v_add_co_u32 v6, vcc_lo, s30, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s31, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v12, s36, v10
	v_add_co_u32 v10, vcc_lo, s40, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s41, v1, vcc_lo
	global_store_b32 v[8:9], v12, off
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[6:7], off
	global_load_b32 v6, v[10:11], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v7, v4, v5
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v6, s36, v7
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s42, v0
	global_store_b32 v[10:11], v6, off
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v2, v[2:3], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s43, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v2, v4, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, s36, v2
	global_store_b32 v[0:1], v3, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 164
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii, .Lfunc_end0-_Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1672
; NumSgprs: 46
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         128
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         136
        .size:           8
        .value_kind:     global_buffer
      - .offset:         144
        .size:           4
        .value_kind:     by_value
      - .offset:         148
        .size:           4
        .value_kind:     by_value
      - .offset:         152
        .size:           4
        .value_kind:     by_value
      - .offset:         156
        .size:           4
        .value_kind:     by_value
      - .offset:         160
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 164
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     46
    .sgpr_spill_count: 0
    .symbol:         _Z26MHDComputedUz_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
