//function kernel
__device__ float length(float3 r) {
    return r.x*r.x + r.y*r.y + r.z*r.z;
}
__device__ float3 mul_float3(float3 r1, float3 r2) {
    return make_float3(r1.x * r2.x,  r1.y * r2.y,  r1.z * r2.z);
}
__device__ float3 add_float3(float3 r1, float3 r2) {
    return make_float3(r1.x + r2.x,  r1.y + r2.y,  r1.z + r2.z);
}
__device__ float3 dif_float3(float3 r1, float3 r2) {
    return make_float3(r1.x - r2.x,  r1.y - r2.y,  r1.z - r2.z);
}
__device__ float3 scale_float3(float s, float3 r) {
    r.x *= s;
    r.y *= s;
    r.z *= s;
    return r;
}
__device__ float Kernel_Poly6(float3 r, float h) {
    float PI = 3.14159;
    return 315.0f / (64 * PI * pow(h, 9)) * pow(pow(h, 2) - length(r), 3);
}
__device__ float3 Gradient_Kernel_Poly6(float3 r, float h) {
    float PI = 3.14159;
    return make_float3(
            r.x * -945.0f / ( 32.0f * PI * pow(h,9) ) * pow(pow(h, 2) - length(r), 2),
            r.y * -945.0f / ( 32.0f * PI * pow(h,9) ) * pow(pow(h, 2) - length(r), 2),
            r.z * -945.0f / ( 32.0f * PI * pow(h,9) ) * pow(pow(h, 2) - length(r), 2));
}
__device__ float Lap_Kernel_Poly6(float3 r, float h) {
    float PI = 3.14159;
    return 945.0f / (8 * PI * pow(h, 9)) * (pow(h, 2) - length(r)) * (length(r) - 3 / 4 * (pow(h, 2) - length(r)));
}




//SPH particle struct
struct pSPH {
    float3 pos;
    float3 vel;
    float m;
    float rho;
    float _;
    float col;
};

extern "C" __global__ void
MC(pSPH *p, float4 *MCBuf, const int len, const float scale, const float h, const int N, const int M)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x; 
    if (idx > M) return;

    int px = idx%len;
    int py = (idx/len)%len;
    int pz = (idx/len/len);
    float3 pos = make_float3(px*scale,py*scale,pz*scale);

    float rho = 0;
    float3 grad_rho = make_float3(0,0,0);

    int i;
    for (i = 0; i < N; ++i)
    {
        pSPH _p = p[i];
        float3 r = dif_float3(pos, _p.pos);
        if (i == idx) continue;
        if (length(r) > h*h) continue;
        if (_p._ <= 0.5f) continue;
        rho += _p.m * Kernel_Poly6(r, h);
        grad_rho = add_float3(grad_rho, scale_float3(_p.m * -1.0f, Gradient_Kernel_Poly6(r, h)));
    }
    float4 _MCBuf = make_float4(grad_rho.x, grad_rho.y, grad_rho.z, rho);
    MCBuf[idx] = _MCBuf;
    return;
}

	.file	"tmpxft_002089b1_00000000-6_MC.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2018:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2018:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z6length6float3
	.type	_Z6length6float3, @function
_Z6length6float3:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$1, 28(%rsp)
	movl	28(%rsp), %edi
	movq	%xmm0, (%rsp)
	movss	%xmm1, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z6length6float3, .-_Z6length6float3
	.globl	_Z10mul_float36float3S_
	.type	_Z10mul_float36float3S_, @function
_Z10mul_float36float3S_:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movl	$1, 44(%rsp)
	movl	44(%rsp), %edi
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 24(%rsp)
	movq	%xmm2, (%rsp)
	movss	%xmm3, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z10mul_float36float3S_, .-_Z10mul_float36float3S_
	.globl	_Z10add_float36float3S_
	.type	_Z10add_float36float3S_, @function
_Z10add_float36float3S_:
.LFB2160:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	call	_Z10mul_float36float3S_
	.cfi_endproc
.LFE2160:
	.size	_Z10add_float36float3S_, .-_Z10add_float36float3S_
	.globl	_Z10dif_float36float3S_
	.type	_Z10dif_float36float3S_, @function
_Z10dif_float36float3S_:
.LFB2162:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	call	_Z10mul_float36float3S_
	.cfi_endproc
.LFE2162:
	.size	_Z10dif_float36float3S_, .-_Z10dif_float36float3S_
	.globl	_Z12scale_float3f6float3
	.type	_Z12scale_float3f6float3, @function
_Z12scale_float3f6float3:
.LFB2012:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$1, 28(%rsp)
	movl	28(%rsp), %edi
	movq	%xmm1, (%rsp)
	movss	%xmm2, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE2012:
	.size	_Z12scale_float3f6float3, .-_Z12scale_float3f6float3
	.globl	_Z12Kernel_Poly66float3f
	.type	_Z12Kernel_Poly66float3f, @function
_Z12Kernel_Poly66float3f:
.LFB2013:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$1, 28(%rsp)
	movl	28(%rsp), %edi
	movq	%xmm0, (%rsp)
	movss	%xmm1, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE2013:
	.size	_Z12Kernel_Poly66float3f, .-_Z12Kernel_Poly66float3f
	.globl	_Z21Gradient_Kernel_Poly66float3f
	.type	_Z21Gradient_Kernel_Poly66float3f, @function
_Z21Gradient_Kernel_Poly66float3f:
.LFB2014:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$1, 28(%rsp)
	movl	28(%rsp), %edi
	movq	%xmm0, (%rsp)
	movss	%xmm1, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE2014:
	.size	_Z21Gradient_Kernel_Poly66float3f, .-_Z21Gradient_Kernel_Poly66float3f
	.globl	_Z16Lap_Kernel_Poly66float3f
	.type	_Z16Lap_Kernel_Poly66float3f, @function
_Z16Lap_Kernel_Poly66float3f:
.LFB2164:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	call	_Z12Kernel_Poly66float3f
	.cfi_endproc
.LFE2164:
	.size	_Z16Lap_Kernel_Poly66float3f, .-_Z16Lap_Kernel_Poly66float3f
	.globl	_Z38__device_stub__Z2MCP4pSPHP6float4iffiiP4pSPHP6float4iffii
	.type	_Z38__device_stub__Z2MCP4pSPHP6float4iffiiP4pSPHP6float4iffii, @function
_Z38__device_stub__Z2MCP4pSPHP6float4iffiiP4pSPHP6float4iffii:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 24(%rsp)
	movss	%xmm1, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	MC(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L18:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z38__device_stub__Z2MCP4pSPHP6float4iffiiP4pSPHP6float4iffii, .-_Z38__device_stub__Z2MCP4pSPHP6float4iffiiP4pSPHP6float4iffii
	.globl	MC
	.type	MC, @function
MC:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z2MCP4pSPHP6float4iffiiP4pSPHP6float4iffii
	.cfi_endproc
.LFE2041:
	.size	MC, .-MC
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"MC"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	MC(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//function kernel
__device__ float length(float3 r) {
    return r.x*r.x + r.y*r.y + r.z*r.z;
}
__device__ float3 mul_float3(float3 r1, float3 r2) {
    return make_float3(r1.x * r2.x,  r1.y * r2.y,  r1.z * r2.z);
}
__device__ float3 add_float3(float3 r1, float3 r2) {
    return make_float3(r1.x + r2.x,  r1.y + r2.y,  r1.z + r2.z);
}
__device__ float3 dif_float3(float3 r1, float3 r2) {
    return make_float3(r1.x - r2.x,  r1.y - r2.y,  r1.z - r2.z);
}
__device__ float3 scale_float3(float s, float3 r) {
    r.x *= s;
    r.y *= s;
    r.z *= s;
    return r;
}
__device__ float Kernel_Poly6(float3 r, float h) {
    float PI = 3.14159;
    return 315.0f / (64 * PI * pow(h, 9)) * pow(pow(h, 2) - length(r), 3);
}
__device__ float3 Gradient_Kernel_Poly6(float3 r, float h) {
    float PI = 3.14159;
    return make_float3(
            r.x * -945.0f / ( 32.0f * PI * pow(h,9) ) * pow(pow(h, 2) - length(r), 2),
            r.y * -945.0f / ( 32.0f * PI * pow(h,9) ) * pow(pow(h, 2) - length(r), 2),
            r.z * -945.0f / ( 32.0f * PI * pow(h,9) ) * pow(pow(h, 2) - length(r), 2));
}
__device__ float Lap_Kernel_Poly6(float3 r, float h) {
    float PI = 3.14159;
    return 945.0f / (8 * PI * pow(h, 9)) * (pow(h, 2) - length(r)) * (length(r) - 3 / 4 * (pow(h, 2) - length(r)));
}




//SPH particle struct
struct pSPH {
    float3 pos;
    float3 vel;
    float m;
    float rho;
    float _;
    float col;
};

extern "C" __global__ void
MC(pSPH *p, float4 *MCBuf, const int len, const float scale, const float h, const int N, const int M)
{
    int idx = blockDim.x * blockIdx.x + threadIdx.x; 
    if (idx > M) return;

    int px = idx%len;
    int py = (idx/len)%len;
    int pz = (idx/len/len);
    float3 pos = make_float3(px*scale,py*scale,pz*scale);

    float rho = 0;
    float3 grad_rho = make_float3(0,0,0);

    int i;
    for (i = 0; i < N; ++i)
    {
        pSPH _p = p[i];
        float3 r = dif_float3(pos, _p.pos);
        if (i == idx) continue;
        if (length(r) > h*h) continue;
        if (_p._ <= 0.5f) continue;
        rho += _p.m * Kernel_Poly6(r, h);
        grad_rho = add_float3(grad_rho, scale_float3(_p.m * -1.0f, Gradient_Kernel_Poly6(r, h)));
    }
    float4 _MCBuf = make_float4(grad_rho.x, grad_rho.y, grad_rho.z, rho);
    MCBuf[idx] = _MCBuf;
    return;
}

	.text
	.file	"MC.hip"
	.globl	__device_stub__MC               # -- Begin function __device_stub__MC
	.type	__device_stub__MC,@function
__device_stub__MC:                      # @__device_stub__MC
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	28(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	20(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	16(%rsp), %r10
	movl	%ecx, (%r10)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%rcx, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$MC, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__MC, .Lfunc_end0-__device_stub__MC
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$MC, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	MC,@object                      # @MC
	.section	.rodata,"a",@progbits
	.globl	MC
	.p2align	3, 0x0
MC:
	.quad	__device_stub__MC
	.size	MC, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"MC"
	.size	.L__unnamed_1, 3

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__MC
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym MC
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	MC                      ; -- Begin function MC
	.globl	MC
	.p2align	8
	.type	MC,@function
MC:                                     ; @MC
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s3, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_ge_i32_e64 s3, v4
	s_cbranch_execz .LBB0_9
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
	v_ashrrev_i32_e32 v5, 31, v4
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s11, 1
	s_cbranch_scc1 .LBB0_8
; %bb.2:                                ; %.lr.ph
	v_frexp_mant_f32_e64 v0, |s10|
	s_mov_b32 s12, 0x3e76c4e1
	s_ashr_i32 s1, s8, 31
	v_cmp_class_f32_e64 s3, s10, 0x204
	s_add_i32 s0, s8, s1
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	s_xor_b32 s2, s0, s1
	v_xor_b32_e32 v15, s1, v5
	s_sub_i32 s0, 0, s2
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, v1
	v_add_f32_e32 v3, -1.0, v0
	v_add_f32_e32 v1, 1.0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, v3, v2
	v_dual_mul_f32 v8, v1, v6 :: v_dual_add_f32 v7, -1.0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v1, v6, v1, -v8
	v_sub_f32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v6, v0
	v_add_f32_e32 v0, v8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v3, v0
	v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v8, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v0, v3, v0 :: v_dual_sub_f32 v1, v8, v1
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v7, v0
	v_mul_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v6, v0
	v_sub_f32_e32 v2, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v3, v1, v1 :: v_dual_sub_f32 v0, v0, v2
	v_fma_f32 v2, v1, v1, -v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v0, v0
	v_fmac_f32_e32 v2, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v3, v2
	v_sub_f32_e32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v7, s12, v6, 0x3e91f4c4 :: v_dual_sub_f32 v2, v2, v3
	v_fmaak_f32 v7, v6, v7, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v6, v7
	v_fma_f32 v3, v6, v7, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v2, v7
	v_add_f32_e32 v7, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v7, v8 :: v_dual_add_f32 v9, 0x3f2aaaaa, v7
	v_dual_sub_f32 v3, v3, v8 :: v_dual_mul_f32 v10, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, 0x31739010, v3
	v_fma_f32 v11, v6, v1, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, 0xbf2aaaaa, v9 :: v_dual_fmac_f32 v11, v6, v0
	v_sub_f32_e32 v7, v7, v8
	v_ldexp_f32 v0, v0, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v2, v1
	v_ldexp_f32 v1, v1, 1
	v_add_f32_e32 v6, v10, v11
	v_add_f32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v9, v3
	v_sub_f32_e32 v7, v9, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v6, v10
	v_dual_sub_f32 v9, v11, v9 :: v_dual_mul_f32 v8, v6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v3, v3, v7
	v_cvt_f32_u32_e32 v11, s2
	v_fma_f32 v7, v6, v2, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v6, v3
	v_frexp_exp_i32_f32_e32 v3, s10
	v_fmac_f32_e32 v7, v9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_add_f32_e32 v3, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v2, v2
	v_add_f32_e32 v6, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v3, v8 :: v_dual_sub_f32 v1, v6, v1
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, 0x3f317218, v2
	v_dual_sub_f32 v1, v3, v1 :: v_dual_add_f32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3f317218, v2, -v9
	v_add_f32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, 0xb102e308, v2
	v_add_f32_e32 v2, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v1, v9, v8 :: v_dual_sub_f32 v6, v2, v6
	v_add_f32_e32 v3, v1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v6
	v_rcp_iflag_f32_e32 v6, v11
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v7, v3, v1 :: v_dual_mul_f32 v6, 0x4f7ffffe, v6
	v_sub_f32_e32 v10, v3, v7
	v_dual_sub_f32 v2, v2, v7 :: v_dual_sub_f32 v9, v1, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v6, v6
	v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v1, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v8, v0
	v_dual_add_f32 v1, v2, v1 :: v_dual_sub_f32 v2, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v1, v7, v1 :: v_dual_sub_f32 v0, v0, v2
	v_add_f32_e32 v9, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v9, v3
	v_sub_f32_e32 v1, v1, v3
	v_sub_f32_e32 v7, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v8, v7
	v_mul_lo_u32 v7, s0, v6
	v_add_f32_e32 v0, v0, v2
	v_add_nc_u32_e32 v2, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v0, v0, v1
	v_mul_hi_u32 v1, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v2, v2, v5
	v_add_f32_e32 v3, v9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v6, 0x41100000, v3 :: v_dual_add_nc_u32 v1, v6, v1
	v_mul_f32_e32 v8, 0, v3
	v_cmp_class_f32_e64 vcc_lo, v6, 0x204
	v_sub_f32_e32 v7, v3, v9
	v_fma_f32 v9, 0x41100000, v3, -v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v0, v0, v7
	v_mul_hi_u32 v7, v2, v1
	v_fmamk_f32 v10, v0, 0x41100000, v8
	v_fmac_f32_e32 v8, 2.0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v7, s2
	v_sub_nc_u32_e32 v2, v2, v11
	v_add_nc_u32_e32 v11, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v13, s2, v2
	v_add_f32_e32 v9, v9, v10
	v_add_f32_e32 v10, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v12, v10, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_sub_f32_e32 v6, v10, v6
	v_add_f32_e32 v10, v3, v3
	v_cmp_eq_f32_e64 s0, 0x42b17218, v12
	v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v2, v2, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v3, v3, 2.0, -v10
	v_sub_f32_e32 v6, v9, v6
	v_cndmask_b32_e64 v11, 0, 0x37000000, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v13, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_cmp_eq_f32_e64 s0, s10, 0
	v_sub_f32_e32 v14, v12, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v7, v13, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
	v_mul_f32_e32 v7, 0x3fb8aa3b, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v15
	v_fma_f32 v13, 0x3fb8aa3b, v14, -v7
	v_rndne_f32_e32 v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v2, v15
	v_dual_fmac_f32 v13, 0x32a5705f, v14 :: v_dual_sub_f32 v2, v7, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v15
	v_cvt_i32_f32_e32 v16, v16
	v_dual_add_f32 v2, v2, v13 :: v_dual_add_nc_u32 v13, v15, v7
	v_xor_b32_e32 v19, s1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v2, v2
	v_xor_b32_e32 v13, v13, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_hi_u32 v1, v13, v1
	v_add_f32_e32 v8, v3, v8
	v_cndmask_b32_e32 v0, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v2, v16
	v_mul_f32_e64 v6, s10, s10
	v_add_f32_e32 v9, v10, v8
	v_add_f32_e32 v0, v11, v0
	v_mul_lo_u32 v3, v1, s2
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_cndmask_b32_e64 v11, 0x7f800000, 0, s0
	s_or_b32 s0, s0, s3
	s_add_u32 s4, s4, 32
	s_addc_u32 s5, s5, 0
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_bfi_b32 v14, 0x7fffffff, v11, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v0, v2, v0, v2
	v_cndmask_b32_e32 v12, v9, v10, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v2
	v_sub_f32_e32 v9, v9, v10
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	v_sub_nc_u32_e32 v2, v13, v3
	v_add_nc_u32_e32 v3, 1, v1
	v_mul_lo_u32 v13, v15, s8
	v_cndmask_b32_e64 v16, 0, 0x37000000, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_subrev_nc_u32_e32 v18, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v12, v16
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v18
	v_sub_f32_e32 v8, v8, v9
	v_sub_nc_u32_e32 v13, v4, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, 1, v1
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_bfi_b32 v0, 0x7fffffff, v0, s10
	v_mov_b32_e32 v3, 0
	v_xor_b32_e32 v1, v1, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v0, v14, s0
	v_mul_f32_e32 v14, 0x3fb8aa3b, v17
	v_mul_f32_e32 v18, 0x43490fd0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v7, 0x3fb8aa3b, v17, -v14
	v_rndne_f32_e32 v20, v14
	v_div_scale_f32 v21, null, v18, v18, 0x439d8000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v7, 0x32a5705f, v17 :: v_dual_sub_f32 v14, v14, v20
	v_cvt_i32_f32_e32 v9, v20
	v_rcp_f32_e32 v22, v21
	v_cmp_neq_f32_e64 s1, 0x7f800000, |v12|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v14, v7 :: v_dual_mov_b32 v7, v4
	v_cndmask_b32_e64 v8, 0, v8, s1
	v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_exp_f32_e32 v10, v14
	v_sub_nc_u32_e32 v14, v1, v19
	v_fma_f32 v1, -v21, v22, 1.0
	v_div_scale_f32 v19, vcc_lo, 0x439d8000, v18, 0x439d8000
	v_add_f32_e32 v12, v16, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v20, v14, s8
	v_fmac_f32_e32 v22, v1, v22
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v1, v10, v9
	v_cvt_f32_i32_e32 v10, v13
	v_mul_f32_e32 v9, v19, v22
	v_sub_nc_u32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v1, 0, v1, s1
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v17
	v_fma_f32 v8, -v21, v9, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, 0x7f800000, v1, s1
	v_fmac_f32_e32 v9, v8, v22
	v_dual_mul_f32 v8, s9, v10 :: v_dual_mov_b32 v1, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v10, v13, v12, v13
	v_cvt_f32_i32_e32 v12, v14
	v_cvt_f32_i32_e32 v14, v15
	v_fma_f32 v15, -v21, v9, v19
	v_cmp_eq_f32_e64 s1, 0x7f800000, v13
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v15, v15, v22, v9
	v_mul_f32_e32 v9, s9, v12
	v_cndmask_b32_e64 v13, v10, v13, s1
	v_mul_f32_e32 v10, s9, v14
	v_mul_f32_e32 v12, 0x42c90fd0, v0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, |v13|, v11, s0
	v_div_fixup_f32 v13, v15, v18, 0x439d8000
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s8, exec_lo
	v_cmpx_ne_u32_e32 0, v7
	s_cbranch_execz .LBB0_7
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s0, s4, 0xffffffe0
	s_addc_u32 s1, s5, -1
	s_add_u32 s2, s4, 0xffffffe8
	s_load_b64 s[0:1], s[0:1], 0x0
	s_addc_u32 s3, s5, -1
	s_clause 0x1
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s3, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_subrev_f32 v16, s0, v8 :: v_dual_subrev_f32 v15, s1, v10
	v_subrev_f32_e32 v14, s2, v9
	v_cmp_nle_f32_e64 s0, s3, 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v16, v16
	v_fmac_f32_e32 v17, v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v14, v14
	v_cmp_ngt_f32_e32 vcc_lo, v17, v6
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	v_sub_f32_e32 v17, v11, v17
	s_add_u32 s0, s4, -8
	s_addc_u32 s1, s5, -1
	v_mul_f32_e32 v16, 0x446c4000, v16
	s_load_b32 s10, s[0:1], 0x0
	v_frexp_mant_f32_e64 v18, |v17|
	v_mul_f32_e32 v14, 0x446c4000, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v18
	v_cndmask_b32_e64 v19, 0, 1, vcc_lo
	v_ldexp_f32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, 1.0, v18
	v_add_f32_e32 v21, -1.0, v18
	v_add_f32_e32 v23, -1.0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v18, v23
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v22, v21, v20
	v_cmp_eq_f32_e64 s0, 0, v17
	v_mul_f32_e32 v24, v19, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v22, v19, -v24
	v_fmac_f32_e32 v19, v22, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v24, v19
	v_dual_sub_f32 v23, v21, v18 :: v_dual_sub_f32 v24, v18, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v24, v19
	v_sub_f32_e32 v21, v21, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v18, v21, v18
	v_add_f32_e32 v18, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v23, v18
	v_mul_f32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v22, v18
	v_mul_f32_e32 v21, v19, v19
	v_sub_f32_e32 v20, v19, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v18, v20
	v_fma_f32 v20, v19, v19, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v18, v18
	v_fmac_f32_e32 v20, v19, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v21, v20
	v_fmaak_f32 v23, s12, v22, 0x3e91f4c4
	v_sub_f32_e32 v21, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v23, v22, v23, 0x3ecccdef :: v_dual_sub_f32 v20, v20, v21
	v_mul_f32_e32 v24, v22, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, v22, v23, -v24
	v_fmac_f32_e32 v21, v20, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, v24, v21
	v_dual_sub_f32 v24, v23, v24 :: v_dual_add_f32 v25, 0x3f2aaaaa, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v26, v19, v22 :: v_dual_sub_f32 v21, v21, v24
	v_fma_f32 v27, v22, v19, -v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v24, 0xbf2aaaaa, v25
	v_add_f32_e32 v21, 0x31739010, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v27, v22, v18
	v_sub_f32_e32 v23, v23, v24
	v_ldexp_f32 v18, v18, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v27, v20, v19
	v_ldexp_f32 v19, v19, 1
	v_add_f32_e32 v22, v26, v27
	v_add_f32_e32 v21, v21, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v25, v21
	v_sub_f32_e32 v23, v25, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, v22, v20
	v_sub_f32_e32 v25, v22, v26
	v_add_f32_e32 v21, v21, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v23, v22, v20, -v24
	v_sub_f32_e32 v25, v27, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, v22, v21
	v_frexp_exp_i32_f32_e32 v21, v17
	v_fmac_f32_e32 v23, v25, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v20, vcc_lo, 0, v21, vcc_lo
	v_add_f32_e32 v21, v24, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v20, v20
	v_sub_f32_e32 v24, v21, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v25, 0x3f317218, v20 :: v_dual_add_f32 v22, v19, v21
	v_sub_f32_e32 v23, v23, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, 0x3f317218, v20, -v25
	v_add_f32_e32 v18, v18, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v24, 0xb102e308, v20 :: v_dual_sub_f32 v19, v22, v19
	v_sub_f32_e32 v19, v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v18, v19
	v_dual_add_f32 v20, v22, v18 :: v_dual_add_f32 v19, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v22, v20, v22 :: v_dual_add_f32 v21, v19, v20
	v_dual_sub_f32 v18, v18, v22 :: v_dual_sub_f32 v23, v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v26, v21, v23
	v_dual_sub_f32 v20, v20, v23 :: v_dual_sub_f32 v25, v19, v25
	v_dual_sub_f32 v19, v19, v26 :: v_dual_sub_f32 v24, v24, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v20, v19
	v_add_f32_e32 v22, v24, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v22, v24
	v_add_f32_e32 v19, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v22, v22, v20
	v_sub_f32_e32 v18, v18, v20
	v_dual_sub_f32 v20, v24, v22 :: v_dual_add_f32 v23, v21, v19
	v_div_scale_f32 v22, vcc_lo, v16, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v18, v18, v20 :: v_dual_sub_f32 v21, v23, v21
	v_sub_f32_e32 v19, v19, v21
	v_div_scale_f32 v21, null, v12, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v18, v18, v19
	v_mul_f32_e32 v15, 0x446c4000, v15
	v_cndmask_b32_e64 v19, 0x7f800000, 0, s0
	v_add_f32_e32 v20, v23, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v24, null, v12, v12, v15
	v_div_scale_f32 v27, s1, v15, v12, v15
	v_dual_mul_f32 v26, 0, v20 :: v_dual_sub_f32 v23, v20, v23
	v_mul_f32_e32 v25, 0x40400000, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v31, v24
	v_bfi_b32 v19, 0x7fffffff, v19, v17
	v_dual_sub_f32 v18, v18, v23 :: v_dual_add_f32 v23, v20, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v28, 0x40400000, v20, -v25
	v_cmp_class_f32_e64 s3, v25, 0x204
	v_fma_f32 v20, v20, 2.0, -v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
	v_fmamk_f32 v29, v18, 0x40400000, v26
	v_fmac_f32_e32 v26, 2.0, v18
	v_div_scale_f32 v18, null, v12, v12, v14
	v_fma_f32 v38, -v24, v31, 1.0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v20, v20, v26
	v_add_f32_e32 v28, v28, v29
	v_rcp_f32_e32 v26, v21
	v_rcp_f32_e32 v32, v18
	v_fmac_f32_e32 v31, v38, v31
	v_add_f32_e32 v33, v23, v20
	v_add_f32_e32 v30, v25, v28
	v_div_scale_f32 v29, s2, v14, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_cndmask_b32_e64 v34, v30, v25, s3
	v_cmp_class_f32_e64 s3, v23, 0x204
	v_fma_f32 v36, -v21, v26, 1.0
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v40, -v18, v32, 1.0
	v_cndmask_b32_e64 v35, v33, v23, s3
	v_cmp_eq_f32_e64 s3, 0x42b17218, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v26, v36, v26
	v_cndmask_b32_e64 v37, 0, 0x37000000, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e64 s3, 0x42b17218, v35
	v_sub_f32_e32 v41, v34, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v39, 0, 0x37000000, s3
	v_dual_mul_f32 v42, v27, v31 :: v_dual_sub_f32 v25, v30, v25
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v34|
	v_sub_f32_e32 v36, v35, v39
	v_dual_mul_f32 v38, 0x3fb8aa3b, v41 :: v_dual_sub_f32 v23, v33, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v25, v28, v25
	v_fma_f32 v50, -v24, v42, v27
	v_mul_f32_e32 v43, 0x3fb8aa3b, v36
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v45, 0x3fb8aa3b, v41, -v38
	v_rndne_f32_e32 v46, v38
	v_fmac_f32_e32 v32, v40, v32
	v_sub_f32_e32 v20, v20, v23
	v_fma_f32 v48, 0x3fb8aa3b, v36, -v43
	v_fmac_f32_e32 v45, 0x32a5705f, v41
	v_rndne_f32_e32 v49, v43
	v_mul_f32_e32 v40, v22, v26
	v_mul_f32_e32 v44, v29, v32
	v_fmac_f32_e32 v48, 0x32a5705f, v36
	v_cvt_i32_f32_e32 v28, v46
	v_dual_sub_f32 v43, v43, v49 :: v_dual_sub_f32 v38, v38, v46
	v_cndmask_b32_e64 v25, 0, v25, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v35|
	v_cvt_i32_f32_e32 v23, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v43, v43, v48 :: v_dual_add_f32 v38, v38, v45
	v_fma_f32 v47, -v21, v40, v22
	v_cndmask_b32_e64 v20, 0, v20, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v41
	s_delay_alu instid0(VALU_DEP_4)
	v_exp_f32_e32 v33, v43
	v_exp_f32_e32 v30, v38
	v_dual_fmac_f32 v40, v47, v26 :: v_dual_add_f32 v25, v37, v25
	v_fmac_f32_e32 v42, v50, v31
	v_fma_f32 v51, -v18, v44, v29
	v_add_f32_e32 v20, v39, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v21, -v21, v40, v22
	v_fma_f32 v22, -v24, v42, v27
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_ldexp_f32 v23, v33, v23
	v_ldexp_f32 v28, v30, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v21, v21, v26, v40
	v_fmac_f32_e32 v44, v51, v32
	v_cndmask_b32_e64 v28, 0, v28, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -v18, v44, v29
	v_div_fixup_f32 v16, v21, v12, v16
	v_cndmask_b32_e64 v23, 0, v23, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v28, 0x7f800000, v28, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v36
	v_fma_f32 v24, v28, v25, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, 0x7f800000, v23, s3
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v28
	v_fma_f32 v20, v23, v20, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v24, v24, v28, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v23
	v_cndmask_b32_e32 v20, v20, v23, vcc_lo
	s_mov_b32 vcc_lo, s1
	v_cmp_class_f32_e64 s1, v17, 0x204
	v_div_fmas_f32 v22, v22, v31, v42
	s_mov_b32 vcc_lo, s2
	v_bfi_b32 v23, 0x7fffffff, v24, v17
	v_div_fmas_f32 v18, v18, v32, v44
	v_cndmask_b32_e64 v17, |v20|, 0x7f800000, s1
	s_or_b32 vcc_lo, s0, s1
	v_div_fixup_f32 v15, v22, v12, v15
	v_cndmask_b32_e32 v19, v23, v19, vcc_lo
	v_div_fixup_f32 v14, v18, v12, v14
	v_cndmask_b32_e64 v17, v17, 0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v13, v19
	v_mul_f32_e32 v16, v16, v17
	v_mul_f32_e32 v15, v15, v17
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v14, v14, v17 :: v_dual_fmac_f32 v3, s10, v18
	v_dual_fmac_f32 v0, s10, v16 :: v_dual_fmac_f32 v1, s10, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v2, s10, v14
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_7:                                ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s11, s11, -1
	v_add_nc_u32_e32 v7, -1, v7
	s_add_u32 s4, s4, 40
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s11, 0
	s_cbranch_scc1 .LBB0_3
.LBB0_8:                                ; %._crit_edge
	v_lshlrev_b64 v[4:5], 4, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel MC
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 52
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	MC, .Lfunc_end0-MC
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3564
; NumSgprs: 18
; NumVgprs: 52
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 52
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           MC
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         MC.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     52
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
