#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <device_launch_parameters.h>

constexpr auto PI = 3.14f;

//umplerea a doua matrici cu date 
__global__ void fill_array2D(float *a, float *b, int N, int M) 
{
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    int col = blockIdx.y * blockDim.y + threadIdx.y;
    if (row < N && col < M)
    {
        a[row*N + col] = powf(sinf(2 * PI * row / N), 2) + powf(cosf(2 * PI * col / M), 2);  //dupa egal se poate pune orice conditie avem nevoie
        b[row*N + col] = powf(cosf(2 * PI * row / N), 2) + powf(sinf(2 * PI * col / M), 2);  //dupa egal se poate pune orice conditie avem nevoie
    }
}

//umplerea a doi vectori cu date
__global__ void fill_array1D(float *a,float*b, int N, int M)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int row = idx / N;
    int col = idx % N;
    if (row < N && col < M)
    {
        a[row*N + col] = powf(sinf(2 * PI*row/N), 2) + powf(cosf(2 * PI*col/N), 2);
        b[row*N + col] = powf(cosf(2 * PI*row/M), 2) + powf(sinf(2 * PI*col/M), 2);
    }
}

//suma a doi vectori, intr-un vector c
__global__ void sum_vectors1D(float *a, float *b, float *c, int N, int M)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int row = idx/N;
    int col = idx%N;
    if (row < N && col < M)
    {
        c[row*N + col] = a[row*N + col] + b[row*N + col];
    }
}

//suma a doua matrici, intr-o matrice c
__global__ void sum_vectors2D(float *a, float *b, float *c, int N,int M) 
{
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    int col = blockIdx.y * blockDim.y + threadIdx.y;
    if (row < N && col < M)
    {
        c[row*N + col] = a[row*N + col]+ b[row*N + col];
    }
}

int main()
{

    float *a_h, *a_d, *b_h, *b_d, *c_h, *c_d;
    const int N = 512;
    const int M = 512;
    size_t size = N * M * sizeof(float);
    
    //alocare host
    a_h = (float*)malloc(size);
    b_h = (float*)malloc(size);
    c_h = (float*)malloc(size);
    
    //alocare device
    cudaMalloc((void**)&a_d, size);
    cudaMalloc((void**)&b_d, size);
    cudaMalloc((void**)&c_d, size);

    //dimensiuni grid si threads
    dim3 grid2D(16,16,1);
    dim3 threads2D(32,32,1);
    dim3 grid1D(512, 1, 1);
    dim3 threads1D(512, 1, 1);

    //fill arrays
    fill_array2D <<< grid2D, threads2D >>> (a_d, b_d,N, M);
    sum_vectors2D <<< grid2D, threads2D >>> (a_d, b_d, c_d, N, M);
    fill_array1D <<< grid1D, threads1D >>> (a_d, b_d, N, M);
    sum_vectors1D <<< grid1D, threads1D >>> (a_d, b_d, c_d, N, M);
    
    //copy device data to host
    cudaMemcpy(a_h, a_d, size, cudaMemcpyDeviceToHost);
    cudaMemcpy(b_h, b_d, size, cudaMemcpyDeviceToHost);
    cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
    
    for (int i = 0; i < N; ++i) 
    {
        for (int j = 0; j < M; ++j) 
        {
            std::cout << c_h[i*N + j]<<" ";
        }
        std::cout << std::endl;
    }

    //cuda cleanup
    free(a_h);
    free(b_h);
    free(c_h);
    cudaFree(a_d);
    cudaFree(b_d);
    cudaFree(c_d);

    return 0;
}

	.file	"tmpxft_003b7147_00000000-6_CUDA_Suma_Populare.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z12fill_array2DPfS_iiPfS_ii
	.type	_Z36__device_stub__Z12fill_array2DPfS_iiPfS_ii, @function
_Z36__device_stub__Z12fill_array2DPfS_iiPfS_ii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12fill_array2DPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z36__device_stub__Z12fill_array2DPfS_iiPfS_ii, .-_Z36__device_stub__Z12fill_array2DPfS_iiPfS_ii
	.globl	_Z12fill_array2DPfS_ii
	.type	_Z12fill_array2DPfS_ii, @function
_Z12fill_array2DPfS_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12fill_array2DPfS_iiPfS_ii
	.cfi_endproc
.LFE3661:
	.size	_Z12fill_array2DPfS_ii, .-_Z12fill_array2DPfS_ii
	.globl	_Z36__device_stub__Z12fill_array1DPfS_iiPfS_ii
	.type	_Z36__device_stub__Z12fill_array1DPfS_iiPfS_ii, @function
_Z36__device_stub__Z12fill_array1DPfS_iiPfS_ii:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12fill_array1DPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z36__device_stub__Z12fill_array1DPfS_iiPfS_ii, .-_Z36__device_stub__Z12fill_array1DPfS_iiPfS_ii
	.globl	_Z12fill_array1DPfS_ii
	.type	_Z12fill_array1DPfS_ii, @function
_Z12fill_array1DPfS_ii:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12fill_array1DPfS_iiPfS_ii
	.cfi_endproc
.LFE3663:
	.size	_Z12fill_array1DPfS_ii, .-_Z12fill_array1DPfS_ii
	.globl	_Z39__device_stub__Z13sum_vectors1DPfS_S_iiPfS_S_ii
	.type	_Z39__device_stub__Z13sum_vectors1DPfS_S_iiPfS_S_ii, @function
_Z39__device_stub__Z13sum_vectors1DPfS_S_iiPfS_S_ii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13sum_vectors1DPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z39__device_stub__Z13sum_vectors1DPfS_S_iiPfS_S_ii, .-_Z39__device_stub__Z13sum_vectors1DPfS_S_iiPfS_S_ii
	.globl	_Z13sum_vectors1DPfS_S_ii
	.type	_Z13sum_vectors1DPfS_S_ii, @function
_Z13sum_vectors1DPfS_S_ii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z13sum_vectors1DPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE3665:
	.size	_Z13sum_vectors1DPfS_S_ii, .-_Z13sum_vectors1DPfS_S_ii
	.globl	_Z39__device_stub__Z13sum_vectors2DPfS_S_iiPfS_S_ii
	.type	_Z39__device_stub__Z13sum_vectors2DPfS_S_iiPfS_S_ii, @function
_Z39__device_stub__Z13sum_vectors2DPfS_S_iiPfS_S_ii:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13sum_vectors2DPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z39__device_stub__Z13sum_vectors2DPfS_S_iiPfS_S_ii, .-_Z39__device_stub__Z13sum_vectors2DPfS_S_iiPfS_S_ii
	.globl	_Z13sum_vectors2DPfS_S_ii
	.type	_Z13sum_vectors2DPfS_S_ii, @function
_Z13sum_vectors2DPfS_S_ii:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z13sum_vectors2DPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE3667:
	.size	_Z13sum_vectors2DPfS_S_ii, .-_Z13sum_vectors2DPfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1048576, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$1048576, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$1048576, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1048576, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	movl	$8388609, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rax
	movl	$1, %ecx
	movabsq	$68719476752, %rdi
	movabsq	$137438953504, %rdx
	movl	$1, %esi
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$512, %ecx
	movl	$512, %edx
	call	_Z36__device_stub__Z12fill_array2DPfS_iiPfS_ii
.L24:
	movl	60(%rsp), %ecx
	movq	52(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$512, %ecx
	movl	$512, %r8d
	movq	16(%rsp), %rdi
	call	_Z39__device_stub__Z13sum_vectors2DPfS_S_iiPfS_S_ii
.L25:
	movl	84(%rsp), %ecx
	movq	76(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$512, %ecx
	movl	$512, %edx
	call	_Z36__device_stub__Z12fill_array1DPfS_iiPfS_ii
.L26:
	movl	84(%rsp), %ecx
	movq	76(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$512, %ecx
	movl	$512, %r8d
	movq	16(%rsp), %rdi
	call	_Z39__device_stub__Z13sum_vectors1DPfS_S_iiPfS_S_ii
.L27:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%r13d, %r13d
	movl	$1048576, %edx
	leaq	_ZSt4cout(%rip), %r15
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
.L28:
	movq	%r13, %r14
	xorl	%ebp, %ebp
	salq	$11, %r14
	addq	%rbx, %r14
.L29:
	movq	%r15, %rdi
	cvtss2sd	(%r14,%rbp,4), %xmm0
	incq	%rbp
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$1, %edx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$512, %rbp
	jne	.L29
	movq	%r15, %rdi
	incq	%r13
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$512, %r13
	jne	.L28
	movq	%r12, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z13sum_vectors2DPfS_S_ii"
.LC2:
	.string	"_Z13sum_vectors1DPfS_S_ii"
.LC3:
	.string	"_Z12fill_array1DPfS_ii"
.LC4:
	.string	"_Z12fill_array2DPfS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13sum_vectors2DPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13sum_vectors1DPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12fill_array1DPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12fill_array2DPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>

#include <iostream>


constexpr auto PI = 3.14f;

//umplerea a doua matrici cu date 
__global__ void fill_array2D(float *a, float *b, int N, int M) 
{
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    int col = blockIdx.y * blockDim.y + threadIdx.y;
    if (row < N && col < M)
    {
        a[row*N + col] = powf(sinf(2 * PI * row / N), 2) + powf(cosf(2 * PI * col / M), 2);  //dupa egal se poate pune orice conditie avem nevoie
        b[row*N + col] = powf(cosf(2 * PI * row / N), 2) + powf(sinf(2 * PI * col / M), 2);  //dupa egal se poate pune orice conditie avem nevoie
    }
}

//umplerea a doi vectori cu date
__global__ void fill_array1D(float *a,float*b, int N, int M)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int row = idx / N;
    int col = idx % N;
    if (row < N && col < M)
    {
        a[row*N + col] = powf(sinf(2 * PI*row/N), 2) + powf(cosf(2 * PI*col/N), 2);
        b[row*N + col] = powf(cosf(2 * PI*row/M), 2) + powf(sinf(2 * PI*col/M), 2);
    }
}

//suma a doi vectori, intr-un vector c
__global__ void sum_vectors1D(float *a, float *b, float *c, int N, int M)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int row = idx/N;
    int col = idx%N;
    if (row < N && col < M)
    {
        c[row*N + col] = a[row*N + col] + b[row*N + col];
    }
}

//suma a doua matrici, intr-o matrice c
__global__ void sum_vectors2D(float *a, float *b, float *c, int N,int M) 
{
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    int col = blockIdx.y * blockDim.y + threadIdx.y;
    if (row < N && col < M)
    {
        c[row*N + col] = a[row*N + col]+ b[row*N + col];
    }
}

int main()
{

    float *a_h, *a_d, *b_h, *b_d, *c_h, *c_d;
    const int N = 512;
    const int M = 512;
    size_t size = N * M * sizeof(float);
    
    //alocare host
    a_h = (float*)malloc(size);
    b_h = (float*)malloc(size);
    c_h = (float*)malloc(size);
    
    //alocare device
    hipMalloc((void**)&a_d, size);
    hipMalloc((void**)&b_d, size);
    hipMalloc((void**)&c_d, size);

    //dimensiuni grid si threads
    dim3 grid2D(16,16,1);
    dim3 threads2D(32,32,1);
    dim3 grid1D(512, 1, 1);
    dim3 threads1D(512, 1, 1);

    //fill arrays
    fill_array2D <<< grid2D, threads2D >>> (a_d, b_d,N, M);
    sum_vectors2D <<< grid2D, threads2D >>> (a_d, b_d, c_d, N, M);
    fill_array1D <<< grid1D, threads1D >>> (a_d, b_d, N, M);
    sum_vectors1D <<< grid1D, threads1D >>> (a_d, b_d, c_d, N, M);
    
    //copy device data to host
    hipMemcpy(a_h, a_d, size, hipMemcpyDeviceToHost);
    hipMemcpy(b_h, b_d, size, hipMemcpyDeviceToHost);
    hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
    
    for (int i = 0; i < N; ++i) 
    {
        for (int j = 0; j < M; ++j) 
        {
            std::cout << c_h[i*N + j]<<" ";
        }
        std::cout << std::endl;
    }

    //cuda cleanup
    free(a_h);
    free(b_h);
    free(c_h);
    hipFree(a_d);
    hipFree(b_d);
    hipFree(c_d);

    return 0;
}

	.text
	.file	"CUDA_Suma_Populare.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__fill_array2DPfS_ii # -- Begin function _Z27__device_stub__fill_array2DPfS_ii
	.type	_Z27__device_stub__fill_array2DPfS_ii,@function
_Z27__device_stub__fill_array2DPfS_ii:  # @_Z27__device_stub__fill_array2DPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12fill_array2DPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__fill_array2DPfS_ii, .Lfunc_end0-_Z27__device_stub__fill_array2DPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__fill_array1DPfS_ii # -- Begin function _Z27__device_stub__fill_array1DPfS_ii
	.type	_Z27__device_stub__fill_array1DPfS_ii,@function
_Z27__device_stub__fill_array1DPfS_ii:  # @_Z27__device_stub__fill_array1DPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12fill_array1DPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__fill_array1DPfS_ii, .Lfunc_end1-_Z27__device_stub__fill_array1DPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__sum_vectors1DPfS_S_ii # -- Begin function _Z28__device_stub__sum_vectors1DPfS_S_ii
	.type	_Z28__device_stub__sum_vectors1DPfS_S_ii,@function
_Z28__device_stub__sum_vectors1DPfS_S_ii: # @_Z28__device_stub__sum_vectors1DPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13sum_vectors1DPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__sum_vectors1DPfS_S_ii, .Lfunc_end2-_Z28__device_stub__sum_vectors1DPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__sum_vectors2DPfS_S_ii # -- Begin function _Z28__device_stub__sum_vectors2DPfS_S_ii
	.type	_Z28__device_stub__sum_vectors2DPfS_S_ii,@function
_Z28__device_stub__sum_vectors2DPfS_S_ii: # @_Z28__device_stub__sum_vectors2DPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13sum_vectors2DPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__sum_vectors2DPfS_S_ii, .Lfunc_end3-_Z28__device_stub__sum_vectors2DPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$137438953504, %r12             # imm = 0x2000000020
	movabsq	$68719476752, %r13              # imm = 0x1000000010
	movl	$1048576, %edi                  # imm = 0x100000
	callq	malloc
	movq	%rax, %rbx
	movl	$1048576, %edi                  # imm = 0x100000
	callq	malloc
	movq	%rax, %rbp
	movl	$1048576, %edi                  # imm = 0x100000
	callq	malloc
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leaq	16(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$512, %edx                      # imm = 0x200
	movl	$512, %ecx                      # imm = 0x200
	callq	_Z27__device_stub__fill_array2DPfS_ii
.LBB4_2:
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	$512, %ecx                      # imm = 0x200
	movl	$512, %r8d                      # imm = 0x200
	callq	_Z28__device_stub__sum_vectors2DPfS_S_ii
.LBB4_4:
	movabsq	$4294967808, %r12               # imm = 0x100000200
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$512, %edx                      # imm = 0x200
	movl	$512, %ecx                      # imm = 0x200
	callq	_Z27__device_stub__fill_array1DPfS_ii
.LBB4_6:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	$512, %ecx                      # imm = 0x200
	movl	$512, %r8d                      # imm = 0x200
	callq	_Z28__device_stub__sum_vectors1DPfS_S_ii
.LBB4_8:
	movq	16(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%rbx, %r14
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%rbp, %r15
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	32(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
	movl	$_ZSt4cout, %r13d
.LBB4_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_10 Depth 2
	xorl	%ebx, %ebx
.LBB4_10:                               #   Parent Loop BB4_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbp,%rbx,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbx
	cmpq	$512, %rbx                      # imm = 0x200
	jne	.LBB4_10
# %bb.11:                               #   in Loop: Header=BB4_9 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r12
	addq	$2048, %rbp                     # imm = 0x800
	cmpq	$512, %r12                      # imm = 0x200
	jne	.LBB4_9
# %bb.12:
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12fill_array2DPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12fill_array1DPfS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13sum_vectors1DPfS_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13sum_vectors2DPfS_S_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12fill_array2DPfS_ii,@object  # @_Z12fill_array2DPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z12fill_array2DPfS_ii
	.p2align	3, 0x0
_Z12fill_array2DPfS_ii:
	.quad	_Z27__device_stub__fill_array2DPfS_ii
	.size	_Z12fill_array2DPfS_ii, 8

	.type	_Z12fill_array1DPfS_ii,@object  # @_Z12fill_array1DPfS_ii
	.globl	_Z12fill_array1DPfS_ii
	.p2align	3, 0x0
_Z12fill_array1DPfS_ii:
	.quad	_Z27__device_stub__fill_array1DPfS_ii
	.size	_Z12fill_array1DPfS_ii, 8

	.type	_Z13sum_vectors1DPfS_S_ii,@object # @_Z13sum_vectors1DPfS_S_ii
	.globl	_Z13sum_vectors1DPfS_S_ii
	.p2align	3, 0x0
_Z13sum_vectors1DPfS_S_ii:
	.quad	_Z28__device_stub__sum_vectors1DPfS_S_ii
	.size	_Z13sum_vectors1DPfS_S_ii, 8

	.type	_Z13sum_vectors2DPfS_S_ii,@object # @_Z13sum_vectors2DPfS_S_ii
	.globl	_Z13sum_vectors2DPfS_S_ii
	.p2align	3, 0x0
_Z13sum_vectors2DPfS_S_ii:
	.quad	_Z28__device_stub__sum_vectors2DPfS_S_ii
	.size	_Z13sum_vectors2DPfS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" "
	.size	.L.str, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12fill_array2DPfS_ii"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12fill_array1DPfS_ii"
	.size	.L__unnamed_2, 23

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13sum_vectors1DPfS_S_ii"
	.size	.L__unnamed_3, 26

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z13sum_vectors2DPfS_S_ii"
	.size	.L__unnamed_4, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__fill_array2DPfS_ii
	.addrsig_sym _Z27__device_stub__fill_array1DPfS_ii
	.addrsig_sym _Z28__device_stub__sum_vectors1DPfS_S_ii
	.addrsig_sym _Z28__device_stub__sum_vectors2DPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12fill_array2DPfS_ii
	.addrsig_sym _Z12fill_array1DPfS_ii
	.addrsig_sym _Z13sum_vectors1DPfS_S_ii
	.addrsig_sym _Z13sum_vectors2DPfS_S_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12fill_array2DPfS_ii  ; -- Begin function _Z12fill_array2DPfS_ii
	.globl	_Z12fill_array2DPfS_ii
	.p2align	8
	.type	_Z12fill_array2DPfS_ii,@function
_Z12fill_array2DPfS_ii:                 ; @_Z12fill_array2DPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[6:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	v_cmp_gt_i32_e64 s2, s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_18
; %bb.1:
	v_cvt_f32_i32_e32 v2, v0
	v_cvt_f32_i32_e32 v3, s6
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x40c8f5c3, v2
	v_div_scale_f32 v4, null, v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v4, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v7
	v_div_fixup_f32 v5, v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, 0x7fffffff, v5
	v_cmp_ngt_f32_e64 s12, 0x48000000, |v5|
	v_lshrrev_b32_e32 v4, 23, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s12
	s_xor_b32 s4, exec_lo, s2
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v16, v6, s2, 0x800000
	v_mad_u64_u32 v[2:3], null, 0xfe5163ab, v16, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, v3
	v_add_nc_u32_e32 v3, 0xffffff88, v4
	v_mad_u64_u32 v[9:10], null, 0x3c439041, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v3
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v14, v3
	v_mad_u64_u32 v[10:11], null, 0xdb629599, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v3
	v_mov_b32_e32 v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
	v_cndmask_b32_e32 v2, v10, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[11:12], null, 0xf534ddc0, v16, v[7:8]
	v_add_nc_u32_e32 v3, v15, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v3
	v_mov_b32_e32 v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0xfc2757d1, v16, v[7:8]
	v_mov_b32_e32 v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0x4e441529, v16, v[7:8]
	v_mov_b32_e32 v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[14:15], null, 0xa2f9836e, v16, v[7:8]
	v_cndmask_b32_e64 v7, 0, 0xffffffe0, s3
	v_cndmask_b32_e32 v8, v13, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_add_nc_u32 v3, v7, v3
	v_dual_cndmask_b32 v13, v15, v13 :: v_dual_cndmask_b32 v12, v12, v10
	v_cndmask_b32_e32 v7, v11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v9, v14, v8, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v13, v14, s2
	v_cndmask_b32_e64 v8, v8, v12, s2
	v_sub_nc_u32_e32 v13, 32, v3
	v_cndmask_b32_e64 v12, v12, v7, s2
	v_cndmask_b32_e64 v2, v7, v2, s2
	v_cndmask_b32_e64 v11, v11, v9, s3
	v_cndmask_b32_e64 v9, v9, v8, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, v12, s3
	v_cndmask_b32_e64 v2, v12, v2, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v11, v9, v13
	v_alignbit_b32 v10, v9, v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v8, v2, v13
	v_cndmask_b32_e32 v3, v14, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, v10, v9 :: v_dual_cndmask_b32 v8, v12, v8
	v_bfe_u32 v9, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v3, v7, 30
	v_alignbit_b32 v7, v7, v8, 30
	v_alignbit_b32 v2, v8, v2, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, 0, v9
	v_xor_b32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v7, v11
	v_xor_b32_e32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v12, v10
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, 31, v12
	v_lshlrev_b32_e32 v14, 23, v12
	v_alignbit_b32 v10, v10, v7, v8
	v_alignbit_b32 v2, v7, v2, v8
	v_lshrrev_b32_e32 v8, 29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v7, v10, v2, 9
	v_lshlrev_b32_e32 v8, 31, v8
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v11, v7
	v_or_b32_e32 v13, 0.5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, 31, v11
	v_alignbit_b32 v2, v7, v2, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v7, v10, v13
	v_add_lshl_u32 v10, v11, v12, 23
	v_lshrrev_b32_e32 v2, 9, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fc90fda, v7
	v_sub_nc_u32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0x3fc90fda, v7, -v11
	v_add_nc_u32_e32 v2, 0x33000000, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v7, v7, 0x33a22168, v10
	v_or_b32_e32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, 0x3fc90fda, v2
	v_lshrrev_b32_e32 v2, 30, v3
	v_dual_add_f32 v10, v11, v7 :: v_dual_add_nc_u32 v11, v9, v2
.LBB0_3:                                ; %Flow71
	s_or_saveexec_b32 s2, s4
	v_mul_f32_e64 v8, 0x3f22f983, |v5|
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v8
	v_fma_f32 v3, 0xbfc90fda, v2, |v5|
	v_cvt_i32_f32_e32 v11, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v2, 0xb3a22168, v3
	v_fmamk_f32 v10, v2, 0xa7c234c4, v3
; %bb.5:                                ; %_ZL4sinff.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_cvt_f32_i32_e32 v2, v1
	v_cvt_f32_i32_e32 v3, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x40c8f5c3, v2
	v_div_scale_f32 v7, null, v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v7, v9, 1.0
	v_fmac_f32_e32 v9, v12, v9
	v_div_scale_f32 v12, vcc_lo, v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v12, v9
	v_fma_f32 v14, -v7, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v14, v9
	v_fma_f32 v7, -v7, v13, v12
                                        ; implicit-def: $vgpr12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v9, v13
                                        ; implicit-def: $vgpr13
	v_div_fixup_f32 v2, v7, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, 0x7fffffff, v2
	v_cmp_ngt_f32_e64 s7, 0x48000000, |v2|
	v_lshrrev_b32_e32 v7, 23, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s7
	s_xor_b32 s4, exec_lo, s2
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v14, 0
	v_and_or_b32 v9, v3, s2, 0x800000
	v_add_nc_u32_e32 v20, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0xfe5163ab, v9, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v20
	v_cndmask_b32_e64 v21, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0x3c439041, v9, v[13:14]
	v_add_nc_u32_e32 v21, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v13, v16
	v_cmp_lt_u32_e64 s2, 31, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0xdb629599, v9, v[13:14]
	v_cndmask_b32_e64 v22, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v13, v17 :: v_dual_add_nc_u32 v22, v22, v21
	v_cndmask_b32_e32 v12, v16, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v22
	v_mad_u64_u32 v[17:18], null, 0xf534ddc0, v9, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v13, v18
	v_cndmask_b32_e32 v15, v17, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xfc2757d1, v9, v[13:14]
	v_cndmask_b32_e64 v12, v15, v12, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v19
	v_mad_u64_u32 v[19:20], null, 0x4e441529, v9, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v20
	v_mad_u64_u32 v[20:21], null, 0xa2f9836e, v9, v[13:14]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, v19, v17, vcc_lo
	v_add_nc_u32_e32 v9, v9, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v14, v20, v18 :: v_dual_cndmask_b32 v19, v21, v19
	v_cndmask_b32_e32 v18, v18, v16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v14, v13, s2
	v_cndmask_b32_e64 v14, v19, v14, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, v13, v18, s2
	v_sub_nc_u32_e32 v19, 32, v9
	v_cndmask_b32_e64 v18, v18, v15, s2
	v_cndmask_b32_e64 v14, v14, v17, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v13, s3
	v_cndmask_b32_e64 v13, v13, v18, s3
	v_cndmask_b32_e64 v12, v18, v12, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v14, v17, v19
	v_alignbit_b32 v16, v17, v13, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v13, v12, v19
	v_cndmask_b32_e32 v9, v20, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, v16, v17, vcc_lo
	v_cndmask_b32_e32 v13, v18, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v15, v9, 29, 1
	v_alignbit_b32 v16, v9, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v14, v14, v13, 30
	v_alignbit_b32 v12, v13, v12, 30
	v_sub_nc_u32_e32 v17, 0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v17
	v_xor_b32_e32 v13, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v17
	v_clz_i32_u32_e32 v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v18, 32, v18
	v_sub_nc_u32_e32 v14, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v16, v13, v14
	v_alignbit_b32 v12, v13, v12, v14
	v_lshrrev_b32_e32 v14, 29, v9
	v_alignbit_b32 v13, v16, v12, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v14, 31, v14
	v_lshrrev_b32_e32 v16, 9, v16
	v_clz_i32_u32_e32 v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v19, 0.5, v14
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v20
	v_sub_nc_u32_e32 v21, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v13, v12, v21
	v_or_b32_e32 v13, v16, v19
	v_add_lshl_u32 v16, v17, v18, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v12, 9, v12
	v_mul_f32_e32 v17, 0x3fc90fda, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v12, v16
	v_fma_f32 v16, 0x3fc90fda, v13, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, 0x33000000, v12
	v_fmamk_f32 v13, v13, 0x33a22168, v16
	v_lshrrev_b32_e32 v9, 30, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v12, v12, v14
	v_fmac_f32_e32 v13, 0x3fc90fda, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v12, v17, v13
	v_add_nc_u32_e32 v13, v15, v9
.LBB0_7:                                ; %Flow70
	s_or_saveexec_b32 s2, s4
	v_mul_f32_e64 v9, 0x3f22f983, |v2|
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.8:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v13, v9
	v_fma_f32 v12, 0xbfc90fda, v13, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v12, v13, 0xb3a22168, v12
	v_fmamk_f32 v12, v13, 0xa7c234c4, v12
	v_cvt_i32_f32_e32 v13, v13
; %bb.9:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, v10, v10 :: v_dual_mul_f32 v15, v12, v12
	s_mov_b32 s2, 0xb94c1982
	s_mov_b32 s3, 0x37d75334
	s_mov_b32 s5, 0x3e76c4e1
	v_dual_fmaak_f32 v16, s2, v14, 0x3c0881c4 :: v_dual_fmaak_f32 v19, s2, v15, 0x3c0881c4
	v_dual_fmaak_f32 v17, s3, v14, 0xbab64f3b :: v_dual_and_b32 v18, 1, v11
	v_dual_fmaak_f32 v20, s3, v15, 0xbab64f3b :: v_dual_and_b32 v21, 1, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v16, v14, v16, 0xbe2aaa9d :: v_dual_lshlrev_b32 v11, 30, v11
	v_dual_fmaak_f32 v17, v14, v17, 0x3d2aabf7 :: v_dual_fmaak_f32 v20, v15, v20, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v19, v15, v19, 0xbe2aaa9d :: v_dual_mul_f32 v16, v14, v16
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_dual_fmaak_f32 v17, v14, v17, 0xbf000004 :: v_dual_fmaak_f32 v20, v15, v20, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v19, v15, v19 :: v_dual_fmac_f32 v10, v10, v16
	v_lshlrev_b32_e32 v13, 30, v13
	v_fma_f32 v14, v14, v17, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v15, v15, v20, 1.0
	v_fmac_f32_e32 v12, v12, v19
	v_and_b32_e32 v11, 0x80000000, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0x80000000, v13
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_xor_b32_e32 v14, v6, v5
	v_cmp_class_f32_e64 s2, v2, 0x1f8
	s_load_b128 s[8:11], s[0:1], 0x0
	v_cndmask_b32_e64 v12, -v12, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor3_b32 v10, v14, v11, v10
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	v_xor_b32_e32 v11, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v11, 0x7fc00000, v11, s2
	v_frexp_mant_f32_e64 v13, |v11|
	v_frexp_exp_i32_f32_e32 v27, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s4, 0x3f2aaaab, v13
	v_cndmask_b32_e64 v15, 0, 1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v13, v13, v15
	v_dual_cndmask_b32 v10, 0x7fc00000, v10 :: v_dual_add_f32 v15, 1.0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e64 v12, |v10|
	v_cmp_class_f32_e64 s13, v10, 0x204
	v_add_f32_e32 v19, -1.0, v13
	v_rcp_f32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s3, 0x3f2aaaab, v12
	v_cndmask_b32_e64 v14, 0, 1, s3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v21, v19, v17
	v_ldexp_f32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v24, -1.0, v15 :: v_dual_mul_f32 v25, v15, v21
	v_add_f32_e32 v14, 1.0, v12
	v_add_f32_e32 v18, -1.0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v13, v13, v24
	v_fma_f32 v15, v21, v15, -v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v14
	v_fmac_f32_e32 v15, v21, v13
	s_waitcnt_depctr 0xfff
	v_dual_add_f32 v13, v25, v15 :: v_dual_mul_f32 v20, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v22, -1.0, v14 :: v_dual_sub_f32 v25, v13, v25
	v_dual_mul_f32 v23, v14, v20 :: v_dual_sub_f32 v12, v12, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v24, v19, v13 :: v_dual_sub_f32 v15, v25, v15
	v_fma_f32 v14, v20, v14, -v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v20, v12
	v_add_f32_e32 v12, v23, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v22, v18, v12 :: v_dual_sub_f32 v23, v12, v23
	v_sub_f32_e32 v18, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v23, v14
	v_sub_f32_e32 v12, v18, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v14, v12
	v_add_f32_e32 v12, v22, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v16, v12
	v_add_f32_e32 v14, v20, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v19, v19, v24 :: v_dual_mul_f32 v18, v14, v14
	v_sub_f32_e32 v13, v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v15, v13
	v_add_f32_e32 v13, v24, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v17, v13
	v_add_f32_e32 v15, v21, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v15, v21 :: v_dual_sub_f32 v16, v14, v20
	v_dual_sub_f32 v13, v13, v17 :: v_dual_sub_f32 v12, v12, v16
	v_fma_f32 v17, v14, v14, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v21, v13, v13 :: v_dual_mul_f32 v16, v15, v15
	v_add_f32_e32 v19, v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, v15, v15, -v16
	v_dual_fmac_f32 v17, v14, v19 :: v_dual_fmac_f32 v20, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v16, v20
	v_dual_add_f32 v19, v18, v17 :: v_dual_sub_f32 v16, v21, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v22, s5, v19, 0x3e91f4c4 :: v_dual_fmaak_f32 v23, s5, v21, 0x3e91f4c4
	v_sub_f32_e32 v18, v19, v18
	v_sub_f32_e32 v16, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v22, v19, v22, 0x3ecccdef :: v_dual_fmaak_f32 v23, v21, v23, 0x3ecccdef
	v_sub_f32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v24, v19, v22 :: v_dual_mul_f32 v25, v21, v23
	v_fma_f32 v18, v19, v22, -v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, v21, v23, -v25
	v_fmac_f32_e32 v18, v17, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v20, v16, v23
	v_mul_f32_e32 v23, v14, v19
	v_frexp_exp_i32_f32_e32 v22, v10
	v_add_f32_e32 v26, v24, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v30, v19, v14, -v23
	v_add_f32_e32 v31, 0x3f2aaaaa, v26
	v_add_f32_e32 v29, v25, v20
	v_sub_f32_e32 v24, v26, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v30, v19, v12
	v_ldexp_f32 v12, v12, 1
	v_sub_f32_e32 v25, v29, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v33, 0x3f2aaaaa, v29 :: v_dual_sub_f32 v18, v18, v24
	v_add_f32_e32 v24, 0xbf2aaaaa, v31
	v_dual_fmac_f32 v30, v17, v14 :: v_dual_sub_f32 v19, v20, v25
	v_mul_f32_e32 v28, v15, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v20, 0xbf2aaaaa, v33
	v_add_f32_e32 v18, 0x31739010, v18
	v_dual_sub_f32 v24, v26, v24 :: v_dual_add_f32 v17, 0x31739010, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v32, v21, v15, -v28
	v_sub_f32_e32 v19, v29, v20
	v_subrev_co_ci_u32_e64 v20, s3, 0, v22, s3
	v_ldexp_f32 v14, v14, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v32, v21, v13
	v_subrev_co_ci_u32_e64 v21, s3, 0, v27, s4
	v_cvt_f32_i32_e32 v20, v20
	v_ldexp_f32 v13, v13, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v32, v16, v15
	v_dual_add_f32 v16, v17, v19 :: v_dual_add_f32 v17, v23, v30
	v_ldexp_f32 v15, v15, 1
	v_cmp_eq_f32_e64 s3, 1.0, v10
	v_sub_f32_e32 v23, v17, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v33, v16
	v_dual_add_f32 v18, v18, v24 :: v_dual_sub_f32 v27, v33, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v31, v18
	v_sub_f32_e32 v25, v31, v19
	v_mul_f32_e32 v26, v17, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, v18, v25
	v_fma_f32 v25, v17, v19, -v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v25, v17, v18 :: v_dual_add_f32 v24, v28, v32
	v_sub_f32_e32 v28, v24, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v32, v28
	v_sub_f32_e32 v23, v30, v23
	v_fmac_f32_e32 v25, v23, v19
	v_mul_f32_e32 v29, v24, v22
	v_add_f32_e32 v16, v16, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v27, v24, v22, -v29
	v_fmac_f32_e32 v27, v24, v16
	v_add_f32_e32 v19, v26, v25
	v_cvt_f32_i32_e32 v16, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v27, v17, v22 :: v_dual_mul_f32 v18, 0x3f317218, v20
	v_dual_add_f32 v23, v14, v19 :: v_dual_sub_f32 v24, v19, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v17, 0x3f317218, v16
	v_add_f32_e32 v21, v29, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0x3f317218, v20, -v18
	v_add_f32_e32 v26, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v28, v21, v29 :: v_dual_sub_f32 v15, v26, v15
	v_sub_f32_e32 v15, v21, v15
	v_sub_f32_e32 v24, v25, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v25, v27, v28
	v_sub_f32_e32 v14, v23, v14
	v_fma_f32 v27, 0x3f317218, v16, -v17
	v_dual_add_f32 v13, v13, v25 :: v_dual_fmac_f32 v22, 0xb102e308, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v19, v14 :: v_dual_fmac_f32 v27, 0xb102e308, v16
	v_add_f32_e32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v17, v27
	v_dual_add_f32 v19, v26, v13 :: v_dual_add_f32 v12, v12, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v15, v17
	v_dual_add_f32 v21, v15, v19 :: v_dual_add_f32 v12, v12, v14
	v_add_f32_e32 v14, v18, v22
	v_sub_f32_e32 v25, v19, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v17, v27, v17 :: v_dual_sub_f32 v24, v21, v15
	v_add_f32_e32 v16, v23, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v18, v14, v18 :: v_dual_sub_f32 v13, v13, v25
	v_sub_f32_e32 v26, v21, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, v14, v16
	v_sub_f32_e32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v22, v16, v23 :: v_dual_sub_f32 v15, v15, v26
	v_sub_f32_e32 v23, v20, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v19, v19, v24 :: v_dual_sub_f32 v12, v12, v22
	v_sub_f32_e32 v22, v20, v23
	v_dual_sub_f32 v16, v16, v23 :: v_dual_add_f32 v23, v17, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v15, v19, v15 :: v_dual_sub_f32 v14, v14, v22
	v_dual_add_f32 v22, v18, v12 :: v_dual_sub_f32 v19, v23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v15, v23, v15 :: v_dual_add_f32 v14, v16, v14
	v_dual_sub_f32 v16, v22, v18 :: v_dual_sub_f32 v13, v13, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v24, v21, v15
	v_add_f32_e32 v14, v22, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v22, v22, v16
	v_sub_f32_e32 v12, v12, v16
	v_dual_sub_f32 v16, v23, v19 :: v_dual_sub_f32 v19, v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v23, v20, v14 :: v_dual_sub_f32 v16, v17, v16
	v_dual_sub_f32 v15, v15, v19 :: v_dual_sub_f32 v18, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v23, v20
	v_dual_add_f32 v13, v13, v16 :: v_dual_sub_f32 v14, v14, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v13, v15 :: v_dual_add_f32 v12, v12, v18
	v_add_f32_e32 v12, v12, v14
	v_cndmask_b32_e64 v14, 2.0, 1.0, s3
	v_cmp_eq_f32_e64 s3, 1.0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v23, v12
	v_trunc_f32_e32 v27, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, 2.0, 1.0, s3
	v_mul_f32_e32 v28, 0.5, v14
	v_sub_f32_e32 v18, v15, v23
	v_mul_f32_e32 v19, v14, v15
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v33, 0.5, v17
	v_cmp_eq_f32_e64 s1, v27, v14
	v_trunc_f32_e32 v30, v17
	v_sub_f32_e32 v12, v12, v18
	v_fma_f32 v15, v14, v15, -v19
	v_add_f32_e32 v16, v24, v13
	v_cmp_class_f32_e64 s3, v19, 0x204
	v_trunc_f32_e32 v27, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v15, v14, v12
	v_sub_f32_e32 v20, v16, v24
	v_mul_f32_e32 v21, v17, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s4, v27, v28
	v_dual_add_f32 v18, v19, v15 :: v_dual_sub_f32 v13, v13, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, v17, v16, -v21
	s_and_b32 s4, s1, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v22, v18, v19, s3
	v_sub_f32_e32 v18, v18, v19
	v_fmac_f32_e32 v16, v17, v13
	v_cmp_class_f32_e64 s3, v21, 0x204
	v_mad_u64_u32 v[12:13], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v18
	v_cmp_eq_f32_e64 s0, 0x42b17218, v22
	v_cmp_neq_f32_e64 s5, 0x7f800000, |v22|
	v_cndmask_b32_e64 v24, 0, 0x37000000, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, 0, v15, s5
	v_add_f32_e32 v20, v21, v16
	v_dual_sub_f32 v0, v22, v24 :: v_dual_add_f32 v15, v24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v20, v21, s3
	v_sub_f32_e32 v20, v20, v21
	v_cmp_eq_f32_e64 s3, v30, v17
	v_mul_f32_e32 v26, 0x3fb8aa3b, v0
	v_trunc_f32_e32 v17, v33
	v_cmp_eq_f32_e64 s0, 0x42b17218, v23
	v_sub_f32_e32 v16, v16, v20
	v_cmp_neq_f32_e64 s5, 0x7f800000, |v23|
	v_fma_f32 v31, 0x3fb8aa3b, v0, -v26
	v_rndne_f32_e32 v32, v26
	v_cndmask_b32_e64 v25, 0, 0x37000000, s0
	v_cmp_eq_f32_e64 s0, 0, v10
	v_cndmask_b32_e64 v16, 0, v16, s5
	v_fmac_f32_e32 v31, 0x32a5705f, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v26, v26, v32 :: v_dual_sub_f32 v1, v23, v25
	v_cvt_i32_f32_e32 v18, v32
	v_cmp_ngt_f32_e64 s5, 0xc2ce8ed0, v0
	v_add_f32_e32 v16, v25, v16
	v_dual_add_f32 v26, v26, v31 :: v_dual_mul_f32 v29, 0x3fb8aa3b, v1
	v_cndmask_b32_e64 v13, 0x7f800000, 0, s0
	s_or_b32 s0, s0, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v19, v26
	v_fma_f32 v34, 0x3fb8aa3b, v1, -v29
	v_rndne_f32_e32 v35, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v34, 0x32a5705f, v1
	v_sub_f32_e32 v14, v29, v35
	v_cvt_i32_f32_e32 v20, v35
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v18, v19, v18
	v_add_f32_e32 v14, v14, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, 0, v18, s5
	v_cmp_ngt_f32_e64 s5, 0xc2ce8ed0, v1
	v_exp_f32_e32 v14, v14
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v14, v14, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, 0, v14, s5
	v_cmp_nlt_f32_e64 s5, 0x42b17218, v0
	v_cndmask_b32_e64 v0, 0x7f800000, v18, s5
	v_cmp_nlt_f32_e64 s5, 0x42b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, v0, v15, v0
	v_cndmask_b32_e64 v1, 0x7f800000, v14, s5
	v_cmp_eq_f32_e64 s6, 0x7f800000, v0
	v_cmp_neq_f32_e64 s5, v17, v33
	v_cndmask_b32_e64 v14, 1.0, v10, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v16, v1, v16, v1
	v_cndmask_b32_e64 v0, v15, v0, s6
	v_cmp_eq_f32_e64 s6, 0x7f800000, v1
	s_and_b32 s5, s3, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, 1.0, v11, s5
	v_bfi_b32 v0, 0x7fffffff, v0, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v16, v1, s6
	v_cmp_eq_f32_e64 s6, 0, v11
	v_cndmask_b32_e64 v14, 0, v10, s4
	v_cndmask_b32_e64 v16, 0, v11, s5
	v_cmp_class_f32_e64 s4, v11, 0x204
	v_bfi_b32 v1, 0x7fffffff, v1, v17
	v_cndmask_b32_e64 v17, 0x7fc00000, v0, s1
	v_cmp_gt_f32_e64 s1, 0, v10
	v_cndmask_b32_e64 v15, 0x7f800000, 0, s6
	v_bfi_b32 v13, 0x7fffffff, v13, v14
	v_cndmask_b32_e64 v14, 0x7fc00000, v1, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v0, v0, v17, s1
	v_cmp_gt_f32_e64 s1, 0, v11
	v_bfi_b32 v15, 0x7fffffff, v15, v16
	v_cndmask_b32_e64 v0, v0, v13, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v1, v14, s1
	s_or_b32 s0, s6, s4
	v_ashrrev_i32_e32 v13, 31, v12
	v_cndmask_b32_e64 v1, v1, v15, s0
	v_cmp_o_f32_e64 s0, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, 0x7fc00000, v0, s0
	v_cmp_o_f32_e64 s0, v11, v11
	v_cndmask_b32_e64 v11, 0x7fc00000, v1, s0
	v_lshlrev_b64 v[0:1], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v10, v11
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, s0, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v11, s0, s9, v1, s0
	global_store_b32 v[10:11], v12, off
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
	s_and_saveexec_b32 s0, s12
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_mov_b32 s0, 0x7fffff
	v_add_nc_u32_e32 v4, 0xffffff88, v4
	v_and_or_b32 v8, v6, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 63, v4
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, v6
	v_cndmask_b32_e64 v6, 0, 0xffffffc0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0x3c439041, v8, v[10:11]
	v_add_nc_u32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v4
	v_mov_b32_e32 v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
	v_mad_u64_u32 v[13:14], null, 0xdb629599, v8, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_mov_b32_e32 v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e64 s3, 31, v4
	v_cndmask_b32_e64 v5, v13, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[14:15], null, 0xf534ddc0, v8, v[10:11]
	v_cndmask_b32_e64 v6, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, v6, v4
	v_mov_b32_e32 v10, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v14, v12, s0
	v_mad_u64_u32 v[15:16], null, 0xfc2757d1, v8, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, v6, v5, s1
	v_mov_b32_e32 v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v8, v[10:11]
	v_mov_b32_e32 v10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[17:18], null, 0xa2f9836e, v8, v[10:11]
	v_cndmask_b32_e64 v8, v16, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v17, v15, s0
	v_cndmask_b32_e64 v11, v18, v16, s0
	v_cndmask_b32_e64 v15, v15, v13, s0
	v_cmp_eq_u32_e64 s0, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v10, v8, s1
	v_cndmask_b32_e64 v10, v11, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, v15, s1
	v_sub_nc_u32_e32 v11, 32, v4
	v_cndmask_b32_e64 v14, v15, v6, s1
	v_cndmask_b32_e64 v10, v10, v12, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v12, v8, s3
	v_cndmask_b32_e64 v8, v8, v14, s3
	v_cndmask_b32_e64 v5, v14, v5, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v10, v12, v11
	v_alignbit_b32 v13, v12, v8, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v8, v5, v11
	v_cndmask_b32_e64 v4, v15, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v13, v12, s0
	v_cndmask_b32_e64 v8, v11, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v12, v4, 29, 1
	v_alignbit_b32 v10, v4, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v6, v6, v8, 30
	v_alignbit_b32 v5, v8, v5, 30
	v_sub_nc_u32_e32 v13, 0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v10, v13
	v_xor_b32_e32 v6, v6, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v13
	v_clz_i32_u32_e32 v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v8, 31, v11
	v_lshlrev_b32_e32 v15, 23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v10, v6, v8
	v_alignbit_b32 v5, v6, v5, v8
	v_lshrrev_b32_e32 v8, 29, v4
	v_lshrrev_b32_e32 v4, 30, v4
	v_alignbit_b32 v6, v10, v5, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v8, 31, v8
	v_lshrrev_b32_e32 v10, 9, v10
	v_clz_i32_u32_e32 v13, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v8
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v15
	v_sub_nc_u32_e32 v16, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v5, v16
	v_or_b32_e32 v6, v10, v14
	v_add_lshl_u32 v10, v13, v11, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v5, 9, v5
	v_mul_f32_e32 v11, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v10
	v_fma_f32 v10, 0x3fc90fda, v6, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, 0x33000000, v5
	v_fmamk_f32 v6, v6, 0x33a22168, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v5, v8
                                        ; implicit-def: $vgpr8
	v_fmac_f32_e32 v6, 0x3fc90fda, v5
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v10, v11, v6 :: v_dual_add_nc_u32 v11, v12, v4
.LBB0_11:                               ; %Flow69
	s_and_not1_saveexec_b32 s0, s4
; %bb.12:
	v_rndne_f32_e32 v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v5, 0xbfc90fda, v4, |v5|
	v_cvt_i32_f32_e32 v11, v4
	v_fmamk_f32 v5, v4, 0xb3a22168, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v10, v4, 0xa7c234c4, v5
; %bb.13:                               ; %_ZL4cosff.exit35
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_15
; %bb.14:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v6, 0
	v_and_or_b32 v18, v3, s0, 0x800000
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, 0xfe5163ab, v18, 0
	v_cmp_lt_u32_e64 s0, 63, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0x3c439041, v18, v[5:6]
	v_mov_b32_e32 v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0, 0xffffffc0, s0
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v9, v7
	v_cmp_lt_u32_e64 s1, 31, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v5, v13
	v_cndmask_b32_e64 v4, v12, v4, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v9, v7
	v_mov_b32_e32 v5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v7
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v15
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v16
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[5:6]
	v_cndmask_b32_e64 v5, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v15, v13, s0
	v_add_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v16, v14, s0
	v_cndmask_b32_e64 v15, v17, v15, s0
	v_cndmask_b32_e64 v14, v14, v12, s0
	v_cndmask_b32_e64 v7, v13, v8, s0
	v_sub_nc_u32_e32 v13, 32, v5
	v_cndmask_b32_e64 v8, v9, v6, s1
	v_cndmask_b32_e64 v9, v15, v9, s1
	v_cndmask_b32_e64 v6, v6, v14, s1
	v_cndmask_b32_e64 v14, v14, v7, s1
	v_cmp_eq_u32_e64 s0, 0, v5
	v_cndmask_b32_e64 v4, v7, v4, s1
	v_cndmask_b32_e64 v9, v9, v8, s3
	v_cndmask_b32_e64 v8, v8, v6, s3
	v_cndmask_b32_e64 v6, v6, v14, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v14, v4, s3
	v_alignbit_b32 v15, v9, v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v8, v6, v13
	v_alignbit_b32 v13, v6, v4, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v15, v9, s0
	v_cndmask_b32_e64 v7, v12, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v13, v6, s0
	v_bfe_u32 v8, v5, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v5, v7, 30
	v_alignbit_b32 v7, v7, v6, 30
	v_alignbit_b32 v4, v6, v4, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, 0, v8
	v_xor_b32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v7, v12
	v_xor_b32_e32 v4, v4, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v13, v9
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	v_alignbit_b32 v9, v9, v6, v7
	v_alignbit_b32 v4, v6, v4, v7
	v_lshrrev_b32_e32 v7, 29, v5
	v_lshrrev_b32_e32 v5, 30, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v9, v4, 9
	v_lshlrev_b32_e32 v7, 31, v7
	v_lshrrev_b32_e32 v9, 9, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v8, v5
	v_clz_i32_u32_e32 v12, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v7
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v15
	v_sub_nc_u32_e32 v16, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v6, v4, v16
	v_or_b32_e32 v6, v9, v14
	v_add_lshl_u32 v9, v12, v13, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v4, 9, v4
	v_mul_f32_e32 v12, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v9
	v_fma_f32 v9, 0x3fc90fda, v6, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 0x33000000, v4
	v_fmamk_f32 v6, v6, 0x33a22168, v9
                                        ; implicit-def: $vgpr9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v4, v4, v7
	v_fmac_f32_e32 v6, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v12, v6
.LBB0_15:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s4
; %bb.16:
	v_rndne_f32_e32 v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, 0xbfc90fda, v5, |v2|
	v_fmamk_f32 v4, v5, 0xb3a22168, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v4, v5, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v5, v5
; %bb.17:                               ; %_ZL4sinff.exit43
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v6, v10, v10 :: v_dual_mul_f32 v7, v4, v4
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_xor_b32_e32 v2, v3, v2
	v_dual_fmaak_f32 v8, s0, v6, 0x3c0881c4 :: v_dual_fmaak_f32 v13, s0, v7, 0x3c0881c4
	v_dual_fmaak_f32 v9, s1, v6, 0xbab64f3b :: v_dual_and_b32 v12, 1, v11
	v_dual_fmaak_f32 v14, s1, v7, 0xbab64f3b :: v_dual_and_b32 v15, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v8, v6, v8, 0xbe2aaa9d :: v_dual_lshlrev_b32 v11, 30, v11
	v_dual_fmaak_f32 v9, v6, v9, 0x3d2aabf7 :: v_dual_fmaak_f32 v14, v7, v14, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v13, v7, v13, 0xbe2aaa9d :: v_dual_mul_f32 v8, v6, v8
	v_cmp_eq_u32_e64 s0, 0, v12
	v_dual_fmaak_f32 v9, v6, v9, 0xbf000004 :: v_dual_fmaak_f32 v14, v7, v14, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v13, v7, v13 :: v_dual_fmac_f32 v10, v10, v8
	v_and_b32_e32 v8, 0x80000000, v11
	v_fma_f32 v6, v6, v9, 1.0
	v_lshlrev_b32_e32 v5, 30, v5
	v_fma_f32 v7, v7, v14, 1.0
	s_mov_b32 s1, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, -v10, v6, s0
	v_cmp_eq_u32_e64 s0, 0, v15
	v_and_b32_e32 v5, 0x80000000, v5
	v_xor_b32_e32 v3, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v4, v4, v13 :: v_dual_cndmask_b32 v3, 0x7fc00000, v3
	v_cndmask_b32_e64 v4, v7, v4, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_class_f32_e64 s5, v3, 0x204
	v_xor3_b32 v2, v2, v5, v4
	v_frexp_mant_f32_e64 v4, |v3|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, 0x7fc00000, v2, s2
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v5, |v2|
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_frexp_exp_i32_f32_e32 v19, v2
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v4, v4, v6
	v_cndmask_b32_e64 v7, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, 1.0, v4
	v_add_f32_e32 v10, -1.0, v4
	v_ldexp_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	v_dual_add_f32 v14, -1.0, v6 :: v_dual_add_f32 v7, 1.0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v11, -1.0, v5 :: v_dual_sub_f32 v4, v4, v14
	v_rcp_f32_e32 v9, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v12, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v16, -1.0, v7 :: v_dual_mul_f32 v15, v6, v12
	v_mul_f32_e32 v13, v11, v9
	v_fma_f32 v6, v12, v6, -v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v7, v13
	v_fma_f32 v7, v13, v7, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v12, v4
	v_dual_sub_f32 v5, v5, v16 :: v_dual_add_f32 v4, v15, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v7, v13, v5 :: v_dual_sub_f32 v14, v10, v4
	v_add_f32_e32 v5, v17, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v15, v4, v15 :: v_dual_sub_f32 v10, v10, v14
	v_sub_f32_e32 v17, v5, v17
	v_sub_f32_e32 v16, v11, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v15, v6
	v_dual_sub_f32 v4, v10, v4 :: v_dual_sub_f32 v7, v17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v6, v4
	v_add_f32_e32 v4, v14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v8, v4
	v_add_f32_e32 v6, v12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v11, v16 :: v_dual_mul_f32 v10, v6, v6
	v_sub_f32_e32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v7, v5
	v_add_f32_e32 v5, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v9, v5
	v_dual_add_f32 v7, v13, v5 :: v_dual_sub_f32 v8, v6, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v7, v13 :: v_dual_sub_f32 v4, v4, v8
	v_dual_sub_f32 v5, v5, v9 :: v_dual_mul_f32 v8, v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, v4, v4
	v_fma_f32 v9, v6, v6, -v10
	v_fma_f32 v12, v7, v7, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v6, v11
	v_add_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v5, v5 :: v_dual_fmaak_f32 v14, s1, v11, 0x3e91f4c4
	v_fmac_f32_e32 v12, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v8, v12
	v_sub_f32_e32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v14, v11, v14, 0x3ecccdef
	v_dual_fmaak_f32 v15, s1, v13, 0x3e91f4c4 :: v_dual_sub_f32 v10, v11, v10
	v_sub_f32_e32 v8, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, v11, v14 :: v_dual_fmaak_f32 v15, v13, v15, 0x3ecccdef
	v_mul_f32_e32 v17, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v12, v13, v15, -v17
	v_sub_f32_e32 v9, v9, v10
	v_fma_f32 v10, v11, v14, -v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v8, v15
	v_dual_mul_f32 v15, v6, v11 :: v_dual_fmac_f32 v10, v9, v14
	v_frexp_exp_i32_f32_e32 v14, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v21, v17, v12
	v_fma_f32 v22, v11, v6, -v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v18, v16, v10
	v_mul_f32_e32 v20, v7, v13
	v_dual_sub_f32 v17, v21, v17 :: v_dual_fmac_f32 v22, v11, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v23, 0x3f2aaaaa, v18
	v_fma_f32 v24, v13, v7, -v20
	v_dual_sub_f32 v16, v18, v16 :: v_dual_add_f32 v25, 0x3f2aaaaa, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v12, v17
	v_ldexp_f32 v4, v4, 1
	v_fmac_f32_e32 v24, v13, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v10, v16
	v_add_f32_e32 v16, 0xbf2aaaaa, v23
	v_ldexp_f32 v5, v5, 1
	v_fmac_f32_e32 v24, v8, v7
	v_fmac_f32_e32 v22, v9, v6
	v_add_f32_e32 v12, 0xbf2aaaaa, v25
	v_add_f32_e32 v10, 0x31739010, v10
	v_dual_sub_f32 v16, v18, v16 :: v_dual_add_f32 v9, 0x31739010, v11
	v_ldexp_f32 v6, v6, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v21, v12
	v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v14, vcc_lo
	v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v19, s0
	v_dual_add_f32 v8, v9, v11 :: v_dual_add_f32 v9, v15, v22
	v_add_f32_e32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v12, v12
	v_ldexp_f32 v7, v7, 1
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
	v_sub_f32_e32 v15, v9, v15
	v_dual_add_f32 v11, v23, v10 :: v_dual_add_f32 v14, v25, v8
	v_sub_f32_e32 v17, v23, v11
	v_mul_f32_e32 v18, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v19, v25, v14 :: v_dual_add_f32 v10, v10, v17
	v_fma_f32 v17, v9, v11, -v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v16, v20, v24 :: v_dual_fmac_f32 v17, v9, v10
	v_sub_f32_e32 v20, v16, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v24, v20
	v_sub_f32_e32 v15, v22, v15
	v_mul_f32_e32 v21, v16, v14
	v_fmac_f32_e32 v17, v15, v11
	v_add_f32_e32 v8, v8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v16, v14, -v21
	v_fmac_f32_e32 v19, v16, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, v18, v17
	v_cvt_f32_i32_e32 v8, v13
	v_dual_fmac_f32 v19, v9, v14 :: v_dual_mul_f32 v10, 0x3f317218, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v9, 0x3f317218, v8 :: v_dual_sub_f32 v16, v11, v18
	v_add_f32_e32 v13, v21, v19
	v_add_f32_e32 v15, v6, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, 0x3f317218, v12, -v10
	v_add_f32_e32 v18, v7, v13
	v_sub_f32_e32 v20, v13, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v17, v16 :: v_dual_sub_f32 v7, v18, v7
	v_dual_sub_f32 v6, v15, v6 :: v_dual_sub_f32 v7, v13, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v6, v11, v6
	v_sub_f32_e32 v17, v19, v20
	v_fma_f32 v19, 0x3f317218, v8, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v5, v17 :: v_dual_fmac_f32 v14, 0xb102e308, v12
	v_add_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, 0xb102e308, v8
	v_dual_add_f32 v11, v18, v5 :: v_dual_add_f32 v4, v4, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v9, v19
	v_sub_f32_e32 v17, v11, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v4, v6
	v_dual_add_f32 v6, v10, v14 :: v_dual_add_f32 v13, v7, v11
	v_sub_f32_e32 v9, v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v5, v5, v17 :: v_dual_add_f32 v8, v15, v4
	v_sub_f32_e32 v10, v6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v16, v13, v7 :: v_dual_sub_f32 v9, v19, v9
	v_add_f32_e32 v12, v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v14, v10
	v_sub_f32_e32 v14, v8, v15
	v_dual_sub_f32 v18, v13, v16 :: v_dual_sub_f32 v15, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v14
	v_sub_f32_e32 v7, v7, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v11, v16 :: v_dual_sub_f32 v14, v12, v15
	v_dual_sub_f32 v8, v8, v15 :: v_dual_add_f32 v15, v9, v5
	v_dual_add_f32 v7, v11, v7 :: v_dual_sub_f32 v6, v6, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v10, v4 :: v_dual_sub_f32 v11, v15, v9
	v_dual_add_f32 v7, v15, v7 :: v_dual_add_f32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v8, v14, v10 :: v_dual_sub_f32 v5, v5, v11
	v_add_f32_e32 v16, v13, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v14, v6
	v_sub_f32_e32 v14, v14, v8
	v_sub_f32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v15, v11 :: v_dual_sub_f32 v11, v16, v13
	v_dual_add_f32 v15, v12, v6 :: v_dual_sub_f32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v10, v10, v14 :: v_dual_sub_f32 v9, v15, v12
	v_sub_f32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v5, v8 :: v_dual_add_f32 v4, v4, v10
	v_dual_sub_f32 v6, v6, v9 :: v_dual_add_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v4, v6
	v_cndmask_b32_e64 v6, 2.0, 1.0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	v_add_f32_e32 v7, v15, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v21, 0.5, v6
	v_cndmask_b32_e64 v9, 2.0, 1.0, vcc_lo
	v_trunc_f32_e32 v20, v6
	v_mul_f32_e32 v11, v6, v7
	v_sub_f32_e32 v10, v7, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v23, v9
	v_cmp_eq_f32_e64 s0, v20, v6
	v_mul_f32_e32 v26, 0.5, v9
	v_fma_f32 v7, v6, v7, -v11
	v_add_f32_e32 v8, v16, v5
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	v_trunc_f32_e32 v20, v21
	v_cmp_eq_f32_e64 s1, v23, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v12, v8, v16
	v_mul_f32_e32 v13, v9, v8
	v_cmp_neq_f32_e64 s2, v20, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v5, v12
	v_fma_f32 v8, v9, v8, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s2, s0, s2
	v_fmac_f32_e32 v8, v9, v5
	v_trunc_f32_e32 v9, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v13, v8 :: v_dual_sub_f32 v4, v4, v10
	v_fmac_f32_e32 v7, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v11, v7
	v_cndmask_b32_e32 v10, v4, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x204
	v_cndmask_b32_e32 v12, v5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_sub_f32_e32 v5, v5, v13
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	v_sub_f32_e32 v16, v10, v14
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v19, 0x3fb8aa3b, v16
	v_sub_f32_e32 v17, v12, v15
	v_sub_f32_e32 v5, v8, v5
	v_cndmask_b32_e64 v18, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s5
	v_fma_f32 v24, 0x3fb8aa3b, v16, -v19
	v_mul_f32_e32 v22, 0x3fb8aa3b, v17
	v_rndne_f32_e32 v25, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v24, 0x32a5705f, v16
	v_fma_f32 v27, 0x3fb8aa3b, v17, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v19, v25
	v_rndne_f32_e32 v28, v22
	v_dual_fmac_f32 v27, 0x32a5705f, v17 :: v_dual_sub_f32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v19, v19, v24
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v10|
	v_cvt_i32_f32_e32 v8, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v7, v4
	v_exp_f32_e32 v11, v19
	v_cvt_i32_f32_e32 v7, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, 0, v4, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v12|
	v_add_f32_e32 v4, v14, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_cndmask_b32_e64 v5, 0, v5, s3
	v_sub_f32_e32 v6, v22, v28
	v_ldexp_f32 v7, v11, v7
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v5, v15, v5 :: v_dual_add_f32 v6, v6, v27
	v_cndmask_b32_e64 v7, 0, v7, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v6, v8
	v_cndmask_b32_e64 v8, 1.0, v3, s2
	v_cndmask_b32_e64 v6, 0, v6, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x7f800000, v7, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v17
	v_fma_f32 v4, v7, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, 0x7f800000, v6, s3
	v_cmp_eq_f32_e64 s4, 0x7f800000, v7
	v_cmp_neq_f32_e64 s3, v9, v26
	v_fma_f32 v5, v6, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v7, s4
	v_cmp_eq_f32_e64 s4, 0x7f800000, v6
	s_and_b32 s3, s1, s3
	v_cndmask_b32_e64 v7, 0, v3, s2
	v_cndmask_b32_e64 v9, 1.0, v2, s3
	v_bfi_b32 v4, 0x7fffffff, v4, v8
	v_cndmask_b32_e64 v5, v5, v6, s4
	v_cmp_eq_f32_e64 s4, 0, v2
	v_cndmask_b32_e64 v8, 0, v2, s3
	v_cmp_class_f32_e64 s2, v2, 0x204
	v_bfi_b32 v7, 0x7fffffff, v18, v7
	v_bfi_b32 v5, 0x7fffffff, v5, v9
	v_cndmask_b32_e64 v9, 0x7fc00000, v4, s0
	v_cmp_gt_f32_e64 s0, 0, v3
	v_cndmask_b32_e64 v6, 0x7f800000, 0, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0x7fc00000, v5, s1
	v_cndmask_b32_e64 v4, v4, v9, s0
	v_cmp_gt_f32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v6, 0x7fffffff, v6, v8
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v10, s0
	s_or_b32 vcc_lo, s4, s2
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v3, v3
	v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0x7fc00000, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_add_f32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12fill_array2DPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12fill_array2DPfS_ii, .Lfunc_end0-_Z12fill_array2DPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8364
; NumSgprs: 18
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12fill_array1DPfS_ii  ; -- Begin function _Z12fill_array1DPfS_ii
	.globl	_Z12fill_array1DPfS_ii
	.p2align	8
	.type	_Z12fill_array1DPfS_ii,@function
_Z12fill_array1DPfS_ii:                 ; @_Z12fill_array1DPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s4, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s6, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s3
	v_cvt_f32_u32_e32 v1, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_sub_i32 s2, 0, s6
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s6
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s6, v3
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	v_mul_lo_u32 v3, v0, s4
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v1, v3
	v_cmp_gt_i32_e64 s2, s5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_18
; %bb.1:
	v_cvt_f32_i32_e32 v0, v0
	v_cvt_f32_i32_e32 v8, s4
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x40c8f5c3, v0
	v_div_scale_f32 v0, null, v8, v8, v3
	v_div_scale_f32 v7, vcc_lo, v3, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v0, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v5
	v_fma_f32 v9, -v0, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v9, v5
	v_fma_f32 v0, -v0, v6, v7
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v0, v0, v5, v6
                                        ; implicit-def: $vgpr6
	v_div_fixup_f32 v0, v0, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v5, 0x7fffffff, v0
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s4, exec_lo, s3
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v18, v5, s2, 0x800000
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, v7
	v_lshrrev_b32_e32 v7, 23, v5
	v_mad_u64_u32 v[11:12], null, 0x3c439041, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v12
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v16, v7
	v_mov_b32_e32 v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e64 s2, 31, v7
	v_cndmask_b32_e32 v6, v12, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[9:10]
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v17, v7
	v_mov_b32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v7
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v15
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v16
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[9:10]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v7, v9, v7
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v9, v13, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v11, v16, v10, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, v15, v16, s2
	v_cndmask_b32_e64 v10, v10, v14, s2
	v_sub_nc_u32_e32 v15, 32, v7
	v_cndmask_b32_e64 v14, v14, v9, s2
	v_cndmask_b32_e64 v6, v9, v6, s2
	v_cndmask_b32_e64 v13, v13, v11, s3
	v_cndmask_b32_e64 v11, v11, v10, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s3
	v_cndmask_b32_e64 v6, v14, v6, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v13, v11, v15
	v_alignbit_b32 v12, v11, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v10, v6, v15
	v_cndmask_b32_e32 v7, v16, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v12, v11 :: v_dual_cndmask_b32 v10, v14, v10
	v_bfe_u32 v11, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v7, v9, 30
	v_alignbit_b32 v9, v9, v10, 30
	v_alignbit_b32 v6, v10, v6, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, 0, v11
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v13
	v_xor_b32_e32 v6, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v12
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	v_alignbit_b32 v12, v12, v9, v10
	v_alignbit_b32 v6, v9, v6, v10
	v_lshrrev_b32_e32 v10, 29, v7
	v_lshrrev_b32_e32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v12, v6, 9
	v_lshlrev_b32_e32 v10, 31, v10
	v_lshrrev_b32_e32 v12, 9, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v11, v7
	v_clz_i32_u32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v15, 0.5, v10
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v15, v16
	v_sub_nc_u32_e32 v17, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v9, v6, v17
	v_or_b32_e32 v9, v12, v15
	v_add_lshl_u32 v12, v13, v14, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v6, 9, v6
	v_mul_f32_e32 v13, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v12
	v_fma_f32 v12, 0x3fc90fda, v9, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0x33000000, v6
	v_fmamk_f32 v9, v9, 0x33a22168, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, v6, v10
	v_fmac_f32_e32 v9, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v13, v9
.LBB1_3:                                ; %Flow71
	s_and_not1_saveexec_b32 s2, s4
; %bb.4:
	v_mul_f32_e64 v6, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v6
	v_fma_f32 v6, 0xbfc90fda, v7, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
; %bb.5:                                ; %_ZL4sinff.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_cvt_f32_i32_e32 v4, v4
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x40c8f5c3, v4
	v_div_scale_f32 v9, null, v8, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	v_div_scale_f32 v11, vcc_lo, v4, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v11, v10
	v_fma_f32 v13, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v10
	v_fma_f32 v9, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v10, v12
                                        ; implicit-def: $vgpr10
	v_div_fixup_f32 v8, v9, v8, v4
                                        ; implicit-def: $vgpr9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e64 0x48000000, |v8|
	s_xor_b32 s4, exec_lo, s3
	s_cbranch_execz .LBB1_7
; %bb.6:
	v_dual_mov_b32 v11, 0 :: v_dual_and_b32 v16, 0x7fffffff, v8
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v19, v16, s2, 0x800000
	v_lshrrev_b32_e32 v16, 23, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xfe5163ab, v19, 0
	v_add_nc_u32_e32 v17, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v17
	v_mad_u64_u32 v[12:13], null, 0x3c439041, v19, v[10:11]
	v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v10, v13
	v_add_nc_u32_e32 v18, v18, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0xdb629599, v19, v[10:11]
	v_cmp_lt_u32_e64 s2, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s2
	v_dual_mov_b32 v10, v14 :: v_dual_cndmask_b32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v20, v20, v18
	v_mad_u64_u32 v[14:15], null, 0xf534ddc0, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v20
	v_mov_b32_e32 v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v14, v12, vcc_lo
	v_mad_u64_u32 v[15:16], null, 0xfc2757d1, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v12, v9, s2
	v_mov_b32_e32 v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v19, v[10:11]
	v_mov_b32_e32 v10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0xa2f9836e, v19, v[10:11]
	v_cndmask_b32_e64 v10, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v11, v16, v14 :: v_dual_add_nc_u32 v10, v10, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v17, v15 :: v_dual_cndmask_b32 v16, v18, v16
	v_cndmask_b32_e32 v15, v15, v13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v17, v11, s2
	v_cndmask_b32_e64 v16, v16, v17, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v15, s2
	v_sub_nc_u32_e32 v17, 32, v10
	v_cndmask_b32_e64 v15, v15, v12, s2
	v_cndmask_b32_e64 v16, v16, v14, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, v14, v11, s3
	v_cndmask_b32_e64 v11, v11, v15, s3
	v_cndmask_b32_e64 v9, v15, v9, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v16, v14, v17
	v_alignbit_b32 v13, v14, v11, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v10, v18, v16, vcc_lo
	v_alignbit_b32 v16, v11, v9, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v13, v14, vcc_lo
	v_bfe_u32 v13, v10, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v16, v11, vcc_lo
	v_alignbit_b32 v14, v10, v12, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v15, 0, v13
	v_alignbit_b32 v12, v12, v11, 30
	v_alignbit_b32 v9, v11, v9, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v15
	v_xor_b32_e32 v11, v12, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v15
	v_clz_i32_u32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v16, 32, v16
	v_sub_nc_u32_e32 v12, 31, v16
	v_lshlrev_b32_e32 v18, 23, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v14, v14, v11, v12
	v_alignbit_b32 v9, v11, v9, v12
	v_lshrrev_b32_e32 v12, 29, v10
	v_alignbit_b32 v11, v14, v9, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v12, 31, v12
	v_lshrrev_b32_e32 v14, 9, v14
	v_clz_i32_u32_e32 v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, 0.5, v12
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, v17, v18
	v_sub_nc_u32_e32 v19, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v11, v9, v19
	v_or_b32_e32 v11, v14, v17
	v_add_lshl_u32 v14, v15, v16, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v9, 9, v9
	v_mul_f32_e32 v15, 0x3fc90fda, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v14
	v_fma_f32 v14, 0x3fc90fda, v11, -v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 0x33000000, v9
	v_fmamk_f32 v11, v11, 0x33a22168, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v9, v9, v12
	v_fmac_f32_e32 v11, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v15, v11
	v_lshrrev_b32_e32 v10, 30, v10
	v_add_nc_u32_e32 v10, v13, v10
.LBB1_7:                                ; %Flow70
	s_and_not1_saveexec_b32 s2, s4
; %bb.8:
	v_mul_f32_e64 v9, 0x3f22f983, |v8|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v10, v9
	v_fma_f32 v9, 0xbfc90fda, v10, |v8|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v10, 0xb3a22168, v9
	v_fmamk_f32 v9, v10, 0xa7c234c4, v9
	v_cvt_i32_f32_e32 v10, v10
; %bb.9:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v11, v6, v6 :: v_dual_mul_f32 v12, v9, v9
	s_mov_b32 s2, 0xb94c1982
	s_mov_b32 s3, 0x37d75334
	v_xor_b32_e32 v5, v5, v0
	v_dual_fmaak_f32 v13, s2, v11, 0x3c0881c4 :: v_dual_fmaak_f32 v16, s2, v12, 0x3c0881c4
	v_dual_fmaak_f32 v14, s3, v11, 0xbab64f3b :: v_dual_fmaak_f32 v17, s3, v12, 0xbab64f3b
	v_and_b32_e32 v15, 1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v13, v11, v13, 0xbe2aaa9d :: v_dual_fmaak_f32 v16, v12, v16, 0xbe2aaa9d
	v_dual_fmaak_f32 v14, v11, v14, 0x3d2aabf7 :: v_dual_lshlrev_b32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v17, v12, v17, 0x3d2aabf7 :: v_dual_and_b32 v18, 1, v10
	v_dual_mul_f32 v13, v11, v13 :: v_dual_mul_f32 v16, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v14, v11, v14, 0xbf000004 :: v_dual_fmaak_f32 v17, v12, v17, 0xbf000004
	v_lshlrev_b32_e32 v10, 30, v10
	v_dual_fmac_f32 v6, v6, v13 :: v_dual_fmac_f32 v9, v9, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v11, v11, v14, 1.0
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_fma_f32 v12, v12, v17, 1.0
	v_and_b32_e32 v7, 0x80000000, v7
	v_and_b32_e32 v10, 0x80000000, v10
	s_mov_b32 s3, 0x3e76c4e1
	v_cndmask_b32_e32 v6, v11, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor3_b32 v5, v5, v7, v6
	v_cndmask_b32_e64 v9, -v9, v12, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	v_xor_b32_e32 v6, v10, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x1f8
	v_cndmask_b32_e32 v5, 0x7fc00000, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v7, |v5|
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v9, 0, 1, s2
	v_ldexp_f32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, -1.0, v7
	v_frexp_mant_f32_e64 v6, |v0|
	v_add_f32_e32 v9, 1.0, v7
	v_cmp_class_f32_e64 s6, v0, 0x204
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v9
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f32 v6, v6, v8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v15, v13, v11 :: v_dual_add_f32 v8, 1.0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v12, -1.0, v6 :: v_dual_mul_f32 v19, v9, v15
	v_add_f32_e32 v18, -1.0, v9
	v_rcp_f32_e32 v10, v8
	v_add_f32_e32 v16, -1.0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, v15, v9, -v19
	v_sub_f32_e32 v7, v7, v18
	v_frexp_exp_i32_f32_e32 v21, v5
	v_cmp_class_f32_e64 s7, v5, 0x204
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_sub_f32 v6, v6, v16 :: v_dual_fmac_f32 v9, v15, v7
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, v12, v10 :: v_dual_add_f32 v7, v19, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v8, v14
	v_sub_f32_e32 v19, v7, v19
	v_sub_f32_e32 v18, v13, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v8, v14, v8, -v17
	v_sub_f32_e32 v9, v19, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v18
	v_dual_fmac_f32 v8, v14, v6 :: v_dual_sub_f32 v7, v13, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v17, v8
	v_dual_sub_f32 v16, v12, v6 :: v_dual_sub_f32 v17, v6, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v9, v7 :: v_dual_sub_f32 v12, v12, v16
	v_dual_sub_f32 v8, v17, v8 :: v_dual_add_f32 v7, v18, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v12, v6 :: v_dual_mul_f32 v7, v11, v7
	v_dual_add_f32 v6, v8, v6 :: v_dual_add_f32 v9, v15, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v16, v6 :: v_dual_sub_f32 v11, v9, v15
	v_dual_mul_f32 v6, v10, v6 :: v_dual_sub_f32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v14, v6 :: v_dual_add_f32 v15, v7, v7
	v_sub_f32_e32 v10, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v10
	v_dual_mul_f32 v12, v8, v8 :: v_dual_add_f32 v13, v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v8, v8, -v12
	v_fmac_f32_e32 v11, v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, v9, v9 :: v_dual_add_f32 v13, v12, v11
	v_fma_f32 v14, v9, v9, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v16, s3, v13, 0x3e91f4c4
	v_fmac_f32_e32 v14, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v13, v12 :: v_dual_add_f32 v15, v10, v14
	v_fmaak_f32 v17, s3, v15, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v16, v13, v16, 0x3ecccdef
	v_sub_f32_e32 v10, v15, v10
	v_sub_f32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v17, v15, v17, 0x3ecccdef :: v_dual_mul_f32 v18, v13, v16
	v_dual_sub_f32 v10, v14, v10 :: v_dual_mul_f32 v19, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v13, v16, -v18
	v_fma_f32 v14, v15, v17, -v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v10, v17
	v_dual_mul_f32 v17, v8, v13 :: v_dual_mul_f32 v22, v9, v15
	v_add_f32_e32 v23, v19, v14
	v_fmac_f32_e32 v12, v11, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v24, v13, v8, -v17
	v_fma_f32 v26, v15, v9, -v22
	v_frexp_exp_i32_f32_e32 v16, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v27, 0x3f2aaaaa, v23 :: v_dual_add_f32 v20, v18, v12
	v_dual_sub_f32 v19, v23, v19 :: v_dual_fmac_f32 v24, v13, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v26, v15, v7
	v_ldexp_f32 v7, v7, 1
	v_dual_add_f32 v25, 0x3f2aaaaa, v20 :: v_dual_sub_f32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v13, v14, v19
	v_fmac_f32_e32 v26, v10, v9
	v_fmac_f32_e32 v24, v11, v8
	v_add_f32_e32 v14, 0xbf2aaaaa, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v12, v18 :: v_dual_add_f32 v11, 0x31739010, v13
	v_add_f32_e32 v18, 0xbf2aaaaa, v25
	v_ldexp_f32 v8, v8, 1
	v_dual_sub_f32 v13, v23, v14 :: v_dual_add_f32 v12, 0x31739010, v12
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v20, v18
	v_dual_add_f32 v10, v11, v13 :: v_dual_add_f32 v11, v17, v24
	v_subrev_co_ci_u32_e64 v15, vcc_lo, 0, v21, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v14, v14
	v_ldexp_f32 v9, v9, 1
	v_sub_f32_e32 v17, v11, v17
	v_add_f32_e32 v16, v27, v10
	v_add_f32_e32 v12, v12, v18
	v_ldexp_f32 v6, v6, 1
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v21, v27, v16
	v_add_f32_e32 v13, v25, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v25, v13
	v_mul_f32_e32 v20, v11, v13
	v_add_f32_e32 v12, v12, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v11, v13, -v20
	v_dual_fmac_f32 v19, v11, v12 :: v_dual_add_f32 v18, v22, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v18, v22
	v_sub_f32_e32 v11, v26, v22
	v_sub_f32_e32 v17, v24, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v17, v13
	v_mul_f32_e32 v23, v18, v16
	v_dual_add_f32 v13, v20, v19 :: v_dual_add_f32 v10, v10, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, v18, v16, -v23
	v_add_f32_e32 v17, v8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v21, v18, v10 :: v_dual_sub_f32 v18, v13, v20
	v_cvt_f32_i32_e32 v10, v15
	v_dual_fmac_f32 v21, v11, v16 :: v_dual_mul_f32 v12, 0x3f317218, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3f317218, v10
	v_add_f32_e32 v15, v23, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, 0x3f317218, v14, -v12
	v_add_f32_e32 v20, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v22, v15, v23 :: v_dual_sub_f32 v9, v20, v9
	v_sub_f32_e32 v9, v15, v9
	v_sub_f32_e32 v18, v19, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v21, v22
	v_sub_f32_e32 v8, v17, v8
	v_fma_f32 v21, 0x3f317218, v10, -v11
	v_dual_add_f32 v7, v7, v19 :: v_dual_sub_f32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, 0xb102e308, v10
	v_dual_fmac_f32 v16, 0xb102e308, v14 :: v_dual_add_f32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v11, v21
	v_dual_add_f32 v13, v20, v7 :: v_dual_add_f32 v6, v6, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v9, v11
	v_dual_add_f32 v15, v9, v13 :: v_dual_add_f32 v6, v6, v8
	v_add_f32_e32 v8, v12, v16
	v_sub_f32_e32 v19, v13, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v11, v21, v11 :: v_dual_sub_f32 v18, v15, v9
	v_add_f32_e32 v10, v17, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v12, v8, v12 :: v_dual_sub_f32 v7, v7, v19
	v_sub_f32_e32 v20, v15, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v8, v10
	v_sub_f32_e32 v12, v16, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v9, v9, v20 :: v_dual_sub_f32 v16, v10, v17
	v_sub_f32_e32 v13, v13, v18
	v_sub_f32_e32 v17, v14, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v6, v6, v16 :: v_dual_add_f32 v9, v13, v9
	v_sub_f32_e32 v16, v14, v17
	v_dual_sub_f32 v10, v10, v17 :: v_dual_add_f32 v17, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v13, v17, v11 :: v_dual_sub_f32 v8, v8, v16
	v_dual_add_f32 v9, v17, v9 :: v_dual_add_f32 v16, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v7, v7, v13 :: v_dual_add_f32 v8, v10, v8
	v_add_f32_e32 v18, v15, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v16, v12
	v_add_f32_e32 v8, v16, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v16, v10
	v_sub_f32_e32 v6, v6, v10
	v_dual_sub_f32 v10, v17, v13 :: v_dual_sub_f32 v13, v18, v15
	v_dual_sub_f32 v10, v11, v10 :: v_dual_sub_f32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v10
	v_add_f32_e32 v17, v14, v8
	v_sub_f32_e32 v12, v12, v16
	v_cndmask_b32_e64 v10, 2.0, 1.0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v5
	v_add_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v11, v17, v14 :: v_dual_add_f32 v12, v6, v12
	v_mul_f32_e32 v29, 0.5, v10
	v_cndmask_b32_e64 v13, 2.0, 1.0, vcc_lo
	v_cvt_f32_i32_e32 v6, s5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v8, v11
	v_trunc_f32_e32 v28, v10
	v_trunc_f32_e32 v31, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v9, null, v6, v6, v3
	v_add_f32_e32 v8, v12, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e64 s1, v28, v10
	v_mul_f32_e32 v34, 0.5, v13
	v_rcp_f32_e32 v14, v9
	v_trunc_f32_e32 v28, v29
	v_dual_add_f32 v11, v17, v8 :: v_dual_add_f32 v12, v18, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_neq_f32_e64 s3, v28, v29
	v_dual_sub_f32 v15, v11, v17 :: v_dual_mul_f32 v16, v10, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v12, v18
	s_and_b32 s3, s1, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v8, v15
	v_fma_f32 v11, v10, v11, -v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v7, v7, v17
	v_cmp_class_f32_e64 s2, v16, 0x204
	v_fmac_f32_e32 v11, v10, v8
	v_fma_f32 v8, -v9, v14, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v16, v11
	v_cndmask_b32_e64 v17, v15, v16, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e64 s0, 0x42b17218, v17
	v_cmp_neq_f32_e64 s4, 0x7f800000, |v17|
	v_cndmask_b32_e64 v21, 0, 0x37000000, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v24, v17, v21
	v_mul_f32_e32 v27, 0x3fb8aa3b, v24
	v_mul_f32_e32 v18, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f32_e32 v33, v27
	v_fma_f32 v12, v13, v12, -v18
	v_fma_f32 v32, 0x3fb8aa3b, v24, -v27
	v_cmp_class_f32_e64 s2, v18, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v27, v27, v33 :: v_dual_fmac_f32 v12, v13, v7
	v_div_scale_f32 v7, vcc_lo, v3, v6, v3
	v_dual_fmac_f32 v14, v8, v14 :: v_dual_sub_f32 v15, v15, v16
	v_dual_add_f32 v8, v18, v12 :: v_dual_mul_f32 v19, v7, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v11, v15
	v_cndmask_b32_e64 v20, v8, v18, s2
	v_cvt_i32_f32_e32 v15, v33
	v_cmp_eq_f32_e64 s2, v31, v13
	v_fma_f32 v22, -v9, v19, v7
	v_cndmask_b32_e64 v11, 0, v11, s4
	v_cmp_eq_f32_e64 s0, 0x42b17218, v20
	v_cmp_neq_f32_e64 s4, 0x7f800000, |v20|
	v_trunc_f32_e32 v13, v34
	v_dual_fmac_f32 v19, v22, v14 :: v_dual_fmac_f32 v32, 0x32a5705f, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, 0, 0x37000000, s0
	v_add_f32_e32 v11, v21, v11
	v_cmp_eq_f32_e64 s0, 0, v0
	v_fma_f32 v7, -v9, v19, v7
	v_add_f32_e32 v27, v27, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, 0x7f800000, 0, s0
	v_div_fmas_f32 v7, v7, v14, v19
	v_cmp_o_f32_e32 vcc_lo, v0, v0
	v_sub_f32_e32 v26, v20, v23
	v_exp_f32_e32 v16, v27
	s_or_b32 s0, s0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v30, 0x3fb8aa3b, v26
	v_fma_f32 v35, 0x3fb8aa3b, v26, -v30
	v_rndne_f32_e32 v36, v30
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v15, v16, v15
	v_dual_fmac_f32 v35, 0x32a5705f, v26 :: v_dual_sub_f32 v10, v30, v36
	v_sub_f32_e32 v8, v8, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v35
	v_sub_f32_e32 v8, v12, v8
	v_cvt_i32_f32_e32 v12, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v10, v10
	v_cndmask_b32_e64 v8, 0, v8, s4
	v_cmp_ngt_f32_e64 s4, 0xc2ce8ed0, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v23, v8
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v10, v12
	v_cndmask_b32_e64 v12, 0, v15, s4
	v_cmp_ngt_f32_e64 s4, 0xc2ce8ed0, v26
	v_cndmask_b32_e64 v10, 0, v10, s4
	v_cmp_nlt_f32_e64 s4, 0x42b17218, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, 0x7f800000, v12, s4
	v_cmp_nlt_f32_e64 s4, 0x42b17218, v26
	v_fma_f32 v11, v12, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, 0x7f800000, v10, s4
	v_cmp_eq_f32_e64 s5, 0x7f800000, v12
	v_cmp_neq_f32_e64 s4, v13, v34
	v_cndmask_b32_e64 v13, 1.0, v0, s3
	v_fma_f32 v8, v10, v8, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v12, s5
	v_cmp_eq_f32_e64 s5, 0x7f800000, v10
	s_and_b32 s4, s2, s4
	v_cndmask_b32_e64 v12, 0, v0, s3
	v_cndmask_b32_e64 v15, 1.0, v5, s4
	v_bfi_b32 v11, 0x7fffffff, v11, v13
	v_cndmask_b32_e64 v8, v8, v10, s5
	v_cmp_eq_f32_e64 s5, 0, v5
	v_cndmask_b32_e64 v13, 0, v5, s4
	v_bfi_b32 v12, 0x7fffffff, v25, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_bfi_b32 v8, 0x7fffffff, v8, v15
	v_cndmask_b32_e64 v15, 0x7fc00000, v11, s1
	v_cmp_gt_f32_e64 s1, 0, v0
	v_cndmask_b32_e64 v10, 0x7f800000, 0, s5
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cndmask_b32_e64 v16, 0x7fc00000, v8, s2
	v_div_fixup_f32 v2, v7, v6, v3
	v_cndmask_b32_e64 v11, v11, v15, s1
	v_cmp_gt_f32_e64 s1, 0, v5
	v_bfi_b32 v10, 0x7fffffff, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v11, v12, s0
	v_cndmask_b32_e64 v8, v8, v16, s1
	s_or_b32 s0, s5, s7
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
	v_cndmask_b32_e64 v8, v8, v10, s0
	v_cmp_o_f32_e32 vcc_lo, v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, 0x7fc00000, v8, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v1, vcc_lo
	v_add_f32_e32 v3, v9, v5
                                        ; implicit-def: $vgpr5
	global_store_b32 v[7:8], v3, off
                                        ; implicit-def: $vgpr3
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB1_11
; %bb.10:
	v_and_b32_e32 v3, 0x7fffffff, v2
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v5, v3, s0, 0x800000
	v_mad_u64_u32 v[7:8], null, 0xfe5163ab, v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x3c439041, v5, v[8:9]
	v_mov_b32_e32 v8, v11
	v_lshrrev_b32_e32 v3, 23, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, 0xdb629599, v5, v[8:9]
	v_add_nc_u32_e32 v3, 0xffffff88, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v3
	v_mov_b32_e32 v8, v12
	v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0xf534ddc0, v5, v[8:9]
	v_cndmask_b32_e32 v7, v11, v7, vcc_lo
	v_dual_mov_b32 v8, v13 :: v_dual_add_nc_u32 v3, v15, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v3
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v5, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
	v_dual_mov_b32 v8, v14 :: v_dual_add_nc_u32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v3
	v_mad_u64_u32 v[14:15], null, 0x4e441529, v5, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v8, v15
	v_mad_u64_u32 v[15:16], null, 0xa2f9836e, v5, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v14, v12, vcc_lo
	v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v9, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
	v_cndmask_b32_e32 v13, v13, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, v5, v3
	v_cndmask_b32_e32 v5, v12, v10, vcc_lo
	v_cndmask_b32_e64 v10, v9, v8, s0
	v_cndmask_b32_e64 v9, v14, v9, s0
	v_cndmask_b32_e64 v8, v8, v13, s0
	v_sub_nc_u32_e32 v12, 32, v3
	v_cndmask_b32_e64 v13, v13, v5, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v9, v9, v10, s1
	v_cndmask_b32_e64 v10, v10, v8, s1
	v_cndmask_b32_e64 v5, v5, v7, s0
	v_cndmask_b32_e64 v8, v8, v13, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v9, v10, v12
	v_cndmask_b32_e64 v5, v13, v5, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v10, v8, v12
	v_cndmask_b32_e32 v3, v14, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v8, v5, v12
	v_cndmask_b32_e32 v7, v11, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v9, v3, 29, 1
	v_cndmask_b32_e32 v8, v12, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v3, v7, 30
	v_sub_nc_u32_e32 v11, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v7, v8, 30
	v_alignbit_b32 v5, v8, v5, 30
	v_xor_b32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v11
	v_xor_b32_e32 v5, v5, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v12, v10
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, 31, v12
	v_lshlrev_b32_e32 v14, 23, v12
	v_alignbit_b32 v10, v10, v7, v8
	v_alignbit_b32 v5, v7, v5, v8
	v_lshrrev_b32_e32 v8, 29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v7, v10, v5, 9
	v_lshlrev_b32_e32 v8, 31, v8
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v11, v7
	v_or_b32_e32 v13, 0.5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, 31, v11
	v_alignbit_b32 v5, v7, v5, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v7, v10, v13
	v_add_lshl_u32 v10, v11, v12, 23
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fc90fda, v7
	v_sub_nc_u32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0x3fc90fda, v7, -v11
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v7, v7, 0x33a22168, v10
	v_or_b32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, 0x3fc90fda, v5
	v_lshrrev_b32_e32 v5, 30, v3
	v_add_f32_e32 v3, v11, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v9, v5
.LBB1_11:                               ; %Flow69
	s_and_not1_saveexec_b32 s0, s2
; %bb.12:
	v_mul_f32_e64 v3, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v5, v3
	v_fma_f32 v3, 0xbfc90fda, v5, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v5, 0xb3a22168, v3
	v_fmamk_f32 v3, v5, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v5, v5
; %bb.13:                               ; %_ZL4cosff.exit38
	s_or_b32 exec_lo, exec_lo, s0
	v_div_scale_f32 v7, null, v6, v6, v4
	v_div_scale_f32 v10, vcc_lo, v4, v6, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v8
	v_fma_f32 v7, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v8, v9
                                        ; implicit-def: $vgpr8
	v_div_fixup_f32 v4, v7, v6, v4
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v6, 0x7fffffff, v4
	v_cmpx_ngt_f32_e64 0x48000000, |v4|
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB1_15
; %bb.14:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v9, 0
	v_and_or_b32 v17, v6, s0, 0x800000
	v_lshrrev_b32_e32 v14, 23, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0xfe5163ab, v17, 0
	v_add_nc_u32_e32 v15, 0xffffff88, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v15
	v_mad_u64_u32 v[10:11], null, 0x3c439041, v17, v[8:9]
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v8, v11
	v_add_nc_u32_e32 v16, v16, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, 0xdb629599, v17, v[8:9]
	v_cmp_lt_u32_e64 s0, 31, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s0
	v_dual_mov_b32 v8, v12 :: v_dual_cndmask_b32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v18, v18, v16
	v_mad_u64_u32 v[12:13], null, 0xf534ddc0, v17, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v18
	v_mov_b32_e32 v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v12, v10, vcc_lo
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v17, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v10, v7, s0
	v_mov_b32_e32 v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0x4e441529, v17, v[8:9]
	v_mov_b32_e32 v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, 0xa2f9836e, v17, v[8:9]
	v_cndmask_b32_e64 v8, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v9, v14, v12 :: v_dual_add_nc_u32 v8, v8, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
	v_cndmask_b32_e32 v13, v13, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v15, v9, s0
	v_cndmask_b32_e64 v14, v14, v15, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v9, v13, s0
	v_sub_nc_u32_e32 v15, 32, v8
	v_cndmask_b32_e64 v13, v13, v10, s0
	v_cndmask_b32_e64 v14, v14, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v12, v9, s1
	v_cndmask_b32_e64 v9, v9, v13, s1
	v_cndmask_b32_e64 v7, v13, v7, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v14, v12, v15
	v_alignbit_b32 v11, v12, v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, v16, v14, vcc_lo
	v_alignbit_b32 v14, v9, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v11, v12, vcc_lo
	v_bfe_u32 v11, v8, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v14, v9, vcc_lo
	v_alignbit_b32 v12, v8, v10, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v13, 0, v11
	v_alignbit_b32 v10, v10, v9, 30
	v_alignbit_b32 v7, v9, v7, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v13
	v_xor_b32_e32 v9, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v13
	v_clz_i32_u32_e32 v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v10, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v12, v9, v10
	v_alignbit_b32 v7, v9, v7, v10
	v_lshrrev_b32_e32 v10, 29, v8
	v_alignbit_b32 v9, v12, v7, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v10, 31, v10
	v_lshrrev_b32_e32 v12, 9, v12
	v_clz_i32_u32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v15, 0.5, v10
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v15, v16
	v_sub_nc_u32_e32 v17, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v9, v7, v17
	v_or_b32_e32 v9, v12, v15
	v_add_lshl_u32 v12, v13, v14, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v7, 9, v7
	v_mul_f32_e32 v13, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v12
	v_fma_f32 v12, 0x3fc90fda, v9, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 0x33000000, v7
	v_fmamk_f32 v9, v9, 0x33a22168, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v7, v7, v10
	v_fmac_f32_e32 v9, 0x3fc90fda, v7
	v_lshrrev_b32_e32 v8, 30, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v7, v13, v9 :: v_dual_add_nc_u32 v8, v11, v8
.LBB1_15:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s2
; %bb.16:
	v_mul_f32_e64 v7, 0x3f22f983, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v8, v7
	v_fma_f32 v7, 0xbfc90fda, v8, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v7, v8, 0xb3a22168, v7
	v_fmamk_f32 v7, v8, 0xa7c234c4, v7
	v_cvt_i32_f32_e32 v8, v8
; %bb.17:                               ; %_ZL4sinff.exit46
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0xb94c1982
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v10, v7, v7
	v_mul_f32_e32 v9, v3, v3
	s_mov_b32 s1, 0x37d75334
	v_xor_b32_e32 v6, v6, v4
	v_and_b32_e32 v16, 1, v8
	v_dual_fmaak_f32 v14, s0, v10, 0x3c0881c4 :: v_dual_fmaak_f32 v11, s0, v9, 0x3c0881c4
	v_dual_fmaak_f32 v12, s1, v9, 0xbab64f3b :: v_dual_fmaak_f32 v15, s1, v10, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v14, v10, v14, 0xbe2aaa9d :: v_dual_and_b32 v13, 1, v5
	v_fmaak_f32 v11, v9, v11, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v12, v9, v12, 0x3d2aabf7 :: v_dual_lshlrev_b32 v5, 30, v5
	v_fmaak_f32 v15, v10, v15, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v14, v10, v14 :: v_dual_mul_f32 v11, v9, v11
	v_fmaak_f32 v12, v9, v12, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v15, v10, v15, 0xbf000004 :: v_dual_lshlrev_b32 v8, 30, v8
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	v_fmac_f32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v9, v9, v12, 1.0
	v_and_b32_e32 v8, 0x80000000, v8
	v_and_b32_e32 v5, 0x80000000, v5
	v_fma_f32 v10, v10, v15, 1.0
	s_mov_b32 s1, 0x3e76c4e1
	v_cndmask_b32_e64 v3, -v3, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v5, v3
	v_fmac_f32_e32 v7, v7, v14
	v_cndmask_b32_e32 v7, v10, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor3_b32 v5, v6, v8, v7
	v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
	v_frexp_mant_f32_e64 v4, |v2|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0x7fc00000, v5, vcc_lo
	v_cmp_class_f32_e64 s5, v2, 0x204
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v4, v4, v6
	v_add_f32_e32 v6, 1.0, v4
	v_add_f32_e32 v10, -1.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	v_add_f32_e32 v14, -1.0, v6
	v_sub_f32_e32 v4, v4, v14
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v12, v10, v8
	v_frexp_mant_f32_e64 v5, |v3|
	v_frexp_exp_i32_f32_e32 v19, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v5
	v_cndmask_b32_e64 v7, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v5, v5, v7
	v_add_f32_e32 v7, 1.0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, -1.0, v5 :: v_dual_add_f32 v16, -1.0, v7
	v_rcp_f32_e32 v9, v7
	v_sub_f32_e32 v5, v5, v16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v13, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v7, v13
	v_fma_f32 v7, v13, v7, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v13, v5
	v_add_f32_e32 v5, v17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v15, v6, v12 :: v_dual_sub_f32 v16, v11, v5
	v_fma_f32 v6, v12, v6, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v12, v4
	v_add_f32_e32 v4, v15, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v10, v4
	v_dual_sub_f32 v10, v10, v14 :: v_dual_sub_f32 v15, v4, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v10, v4 :: v_dual_sub_f32 v17, v5, v17
	v_dual_sub_f32 v6, v15, v6 :: v_dual_sub_f32 v7, v17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v6, v4
	v_add_f32_e32 v4, v14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v8, v4
	v_add_f32_e32 v6, v12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v11, v16 :: v_dual_mul_f32 v10, v6, v6
	v_dual_sub_f32 v5, v11, v5 :: v_dual_sub_f32 v8, v6, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v7, v5 :: v_dual_sub_f32 v4, v4, v8
	v_add_f32_e32 v5, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v9, v5
	v_add_f32_e32 v7, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v7, v13
	v_dual_mul_f32 v8, v7, v7 :: v_dual_sub_f32 v5, v5, v9
	v_fma_f32 v9, v6, v6, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v12, v7, v7, -v8
	v_add_f32_e32 v13, v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v4, v4 :: v_dual_fmac_f32 v12, v7, v13
	v_fmac_f32_e32 v9, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v8, v12
	v_dual_add_f32 v11, v10, v9 :: v_dual_sub_f32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v14, s1, v11, 0x3e91f4c4
	v_sub_f32_e32 v10, v11, v10
	v_sub_f32_e32 v8, v12, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v14, v11, v14, 0x3ecccdef
	v_sub_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v16, v11, v14 :: v_dual_fmaak_f32 v15, s1, v13, 0x3e91f4c4
	v_mul_f32_e32 v20, v7, v13
	v_fma_f32 v10, v11, v14, -v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, v13, v7, -v20
	v_fmac_f32_e32 v10, v9, v14
	v_fmaak_f32 v15, v13, v15, 0x3ecccdef
	v_frexp_exp_i32_f32_e32 v14, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v18, v16, v10 :: v_dual_mul_f32 v17, v13, v15
	v_dual_sub_f32 v16, v18, v16 :: v_dual_add_f32 v23, 0x3f2aaaaa, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v13, v15, -v17
	v_fmac_f32_e32 v12, v8, v15
	v_mul_f32_e32 v15, v6, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v10, v16
	v_dual_add_f32 v16, 0xbf2aaaaa, v23 :: v_dual_add_f32 v21, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, v11, v6, -v15
	v_dual_sub_f32 v16, v18, v16 :: v_dual_sub_f32 v17, v21, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v22, v11, v4 :: v_dual_add_f32 v25, 0x3f2aaaaa, v21
	v_ldexp_f32 v4, v4, 1
	v_dual_sub_f32 v11, v12, v17 :: v_dual_add_f32 v10, 0x31739010, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v22, v9, v6
	v_add_f32_e32 v12, 0xbf2aaaaa, v25
	v_ldexp_f32 v6, v6, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v9, 0x31739010, v11 :: v_dual_add_f32 v10, v10, v16
	v_fmac_f32_e32 v24, v13, v5
	v_sub_f32_e32 v11, v21, v12
	v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v14, vcc_lo
	v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v19, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v24, v8, v7
	v_cvt_f32_i32_e32 v12, v12
	v_ldexp_f32 v7, v7, 1
	v_ldexp_f32 v5, v5, 1
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	v_add_f32_e32 v16, v20, v24
	v_dual_add_f32 v8, v9, v11 :: v_dual_add_f32 v11, v23, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v23, v11
	v_add_f32_e32 v9, v15, v22
	v_sub_f32_e32 v15, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v25, v8 :: v_dual_sub_f32 v15, v22, v15
	v_sub_f32_e32 v19, v25, v14
	v_mul_f32_e32 v21, v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v8, v19
	v_fma_f32 v19, v16, v14, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v10, v17 :: v_dual_fmac_f32 v19, v16, v8
	v_sub_f32_e32 v20, v16, v20
	v_mul_f32_e32 v18, v9, v11
	v_cvt_f32_i32_e32 v8, v13
	v_fma_f32 v17, v9, v11, -v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v9, v10
	v_sub_f32_e32 v9, v24, v20
	v_dual_mul_f32 v10, 0x3f317218, v12 :: v_dual_fmac_f32 v17, v15, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v9, v14
	v_fma_f32 v14, 0x3f317218, v12, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v18, v17 :: v_dual_fmac_f32 v14, 0xb102e308, v12
	v_add_f32_e32 v15, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v6, v15, v6 :: v_dual_add_f32 v13, v21, v19
	v_dual_mul_f32 v9, 0x3f317218, v8 :: v_dual_sub_f32 v16, v11, v18
	v_sub_f32_e32 v6, v11, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, v7, v13
	v_sub_f32_e32 v20, v13, v21
	v_dual_sub_f32 v16, v17, v16 :: v_dual_sub_f32 v7, v18, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v19, v20
	v_fma_f32 v19, 0x3f317218, v8, -v9
	v_sub_f32_e32 v7, v13, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v5, v17
	v_fmac_f32_e32 v19, 0xb102e308, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v7
	v_add_f32_e32 v7, v9, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v18, v5 :: v_dual_add_f32 v4, v4, v16
	v_dual_add_f32 v13, v7, v11 :: v_dual_add_f32 v4, v4, v6
	v_add_f32_e32 v6, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v17, v11, v18 :: v_dual_sub_f32 v16, v13, v7
	v_add_f32_e32 v8, v15, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v10, v6, v10 :: v_dual_sub_f32 v9, v7, v9
	v_sub_f32_e32 v5, v5, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v16
	v_add_f32_e32 v12, v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v14, v10
	v_sub_f32_e32 v14, v8, v15
	v_dual_sub_f32 v18, v13, v16 :: v_dual_sub_f32 v9, v19, v9
	v_sub_f32_e32 v15, v12, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v14
	v_dual_sub_f32 v7, v7, v18 :: v_dual_sub_f32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v12, v15 :: v_dual_add_f32 v15, v9, v5
	v_sub_f32_e32 v6, v6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v10, v4 :: v_dual_add_f32 v7, v11, v7
	v_dual_sub_f32 v11, v15, v9 :: v_dual_add_f32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v8, v14, v10 :: v_dual_add_f32 v7, v15, v7
	v_dual_sub_f32 v5, v5, v11 :: v_dual_add_f32 v6, v14, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v14, v8
	v_sub_f32_e32 v4, v4, v8
	v_add_f32_e32 v16, v13, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v15, v11 :: v_dual_add_f32 v15, v12, v6
	v_dual_sub_f32 v11, v16, v13 :: v_dual_sub_f32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v10, v10, v14 :: v_dual_sub_f32 v9, v15, v12
	v_sub_f32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v5, v8 :: v_dual_add_f32 v4, v4, v10
	v_dual_sub_f32 v6, v6, v9 :: v_dual_add_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v16, v5
	v_sub_f32_e32 v12, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v5, v5, v12 :: v_dual_add_f32 v4, v4, v6
	v_cndmask_b32_e64 v6, 2.0, 1.0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
	v_trunc_f32_e32 v20, v6
	v_cndmask_b32_e64 v9, 2.0, 1.0, vcc_lo
	v_mul_f32_e32 v21, 0.5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e64 s0, v20, v6
	v_mul_f32_e32 v13, v9, v8
	v_add_f32_e32 v7, v15, v4
	v_trunc_f32_e32 v23, v9
	v_mul_f32_e32 v26, 0.5, v9
	v_trunc_f32_e32 v20, v21
	v_fma_f32 v8, v9, v8, -v13
	v_sub_f32_e32 v10, v7, v15
	v_mul_f32_e32 v11, v6, v7
	v_cmp_eq_f32_e64 s1, v23, v9
	v_cmp_neq_f32_e64 s2, v20, v21
	v_fmac_f32_e32 v8, v9, v5
	v_sub_f32_e32 v4, v4, v10
	v_fma_f32 v7, v6, v7, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	v_trunc_f32_e32 v9, v26
	v_add_f32_e32 v5, v13, v8
	s_and_b32 s2, s0, s2
	v_fmac_f32_e32 v7, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v11, v7
	v_cndmask_b32_e32 v10, v4, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x204
	v_cndmask_b32_e32 v12, v5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_sub_f32_e32 v5, v5, v13
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v10, v14
	v_dual_mul_f32 v19, 0x3fb8aa3b, v16 :: v_dual_sub_f32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v24, 0x3fb8aa3b, v16, -v19
	v_rndne_f32_e32 v25, v19
	v_sub_f32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v24, 0x32a5705f, v16 :: v_dual_sub_f32 v19, v19, v25
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v10|
	v_cvt_i32_f32_e32 v7, v25
	v_add_f32_e32 v19, v19, v24
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, 0, v4, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v12|
	v_exp_f32_e32 v11, v19
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v14, v4
	v_cmp_eq_f32_e32 vcc_lo, 0, v2
	v_sub_f32_e32 v17, v12, v15
	v_sub_f32_e32 v5, v8, v5
	v_cndmask_b32_e64 v18, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s5
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ldexp_f32 v7, v11, v7
	v_mul_f32_e32 v22, 0x3fb8aa3b, v17
	v_cndmask_b32_e64 v5, 0, v5, s3
	v_fma_f32 v27, 0x3fb8aa3b, v17, -v22
	v_rndne_f32_e32 v28, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v15, v5
	v_dual_fmac_f32 v27, 0x32a5705f, v17 :: v_dual_sub_f32 v6, v22, v28
	v_cvt_i32_f32_e32 v8, v28
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v6, v27
	v_cndmask_b32_e64 v7, 0, v7, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v6, v8
	v_cndmask_b32_e64 v8, 1.0, v2, s2
	v_cndmask_b32_e64 v6, 0, v6, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x7f800000, v7, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v17
	v_fma_f32 v4, v7, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, 0x7f800000, v6, s3
	v_cmp_eq_f32_e64 s4, 0x7f800000, v7
	v_cmp_neq_f32_e64 s3, v9, v26
	v_fma_f32 v5, v6, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v7, s4
	v_cmp_eq_f32_e64 s4, 0x7f800000, v6
	s_and_b32 s3, s1, s3
	v_cndmask_b32_e64 v7, 0, v2, s2
	v_cndmask_b32_e64 v9, 1.0, v3, s3
	v_bfi_b32 v4, 0x7fffffff, v4, v8
	v_cndmask_b32_e64 v5, v5, v6, s4
	v_cmp_eq_f32_e64 s4, 0, v3
	v_cndmask_b32_e64 v8, 0, v3, s3
	v_cmp_class_f32_e64 s2, v3, 0x204
	v_bfi_b32 v7, 0x7fffffff, v18, v7
	v_bfi_b32 v5, 0x7fffffff, v5, v9
	v_cndmask_b32_e64 v9, 0x7fc00000, v4, s0
	v_cmp_gt_f32_e64 s0, 0, v2
	v_cndmask_b32_e64 v6, 0x7f800000, 0, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0x7fc00000, v5, s1
	v_cndmask_b32_e64 v4, v4, v9, s0
	v_cmp_gt_f32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v6, 0x7fffffff, v6, v8
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v10, s0
	s_or_b32 vcc_lo, s4, s2
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	v_cndmask_b32_e32 v2, 0x7fc00000, v4, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v3, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0x7fc00000, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB1_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12fill_array1DPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12fill_array1DPfS_ii, .Lfunc_end1-_Z12fill_array1DPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8596
; NumSgprs: 18
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13sum_vectors1DPfS_S_ii ; -- Begin function _Z13sum_vectors1DPfS_S_ii
	.globl	_Z13sum_vectors1DPfS_S_ii
	.p2align	8
	.type	_Z13sum_vectors1DPfS_S_ii,@function
_Z13sum_vectors1DPfS_S_ii:              ; @_Z13sum_vectors1DPfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x18
	s_load_b32 s4, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s2, 31
	s_and_b32 s4, s4, 0xffff
	s_add_i32 s6, s2, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s5
	v_cvt_f32_u32_e32 v1, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v3, v1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_sub_i32 s4, 0, s6
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_hi_u32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v3, v0
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s6
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s6, v3
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	v_mul_lo_u32 v3, v0, s2
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v1, v3
	v_cmp_gt_i32_e64 s2, s3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13sum_vectors1DPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13sum_vectors1DPfS_S_ii, .Lfunc_end2-_Z13sum_vectors1DPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 376
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13sum_vectors2DPfS_S_ii ; -- Begin function _Z13sum_vectors2DPfS_S_ii
	.globl	_Z13sum_vectors2DPfS_S_ii
	.p2align	8
	.type	_Z13sum_vectors2DPfS_S_ii,@function
_Z13sum_vectors2DPfS_S_ii:              ; @_Z13sum_vectors2DPfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x10
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13sum_vectors2DPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z13sum_vectors2DPfS_S_ii, .Lfunc_end3-_Z13sum_vectors2DPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12fill_array2DPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12fill_array2DPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12fill_array1DPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12fill_array1DPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13sum_vectors1DPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13sum_vectors1DPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13sum_vectors2DPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13sum_vectors2DPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
