#include "includes.h"
__global__ void rgbUtoLab3F_kernel(int width, int height, float gamma, unsigned int* rgbU, float* devL, float* devA, float* devB) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < width) && (y0 < height)) {
int index = y0 * width + x0;
unsigned int rgb = rgbU[index];
float r = (float)(rgb & 0xff)/255.0;
float g = (float)((rgb & 0xff00) >> 8)/255.0;
float b = (float)((rgb & 0xff0000) >> 16)/255.0;
r = powf(r, gamma);
g = powf(g, gamma);
b = powf(b, gamma);
float x = (0.412453 * r) +  (0.357580 * g) + (0.180423 * b);
float y = (0.212671 * r) +  (0.715160 * g) + (0.072169 * b);
float z = (0.019334 * r) +  (0.119193 * g) + (0.950227 * b);
/*D65 white point reference */
const float x_ref = 0.950456;
const float y_ref = 1.000000;
const float z_ref = 1.088754;
/* threshold value  */
const float threshold = 0.008856;
x = x / x_ref;
y = y / y_ref;
z = z / z_ref;

float fx =
(x > threshold) ? powf(x,(1.0/3.0)) : (7.787*x + (16.0/116.0));
float fy =
(y > threshold) ? powf(y,(1.0/3.0)) : (7.787*y + (16.0/116.0));
float fz =
(z > threshold) ? powf(z,(1.0/3.0)) : (7.787*z + (16.0/116.0));
/* compute Lab color value */
devL[index] =
(y > threshold) ? (116*powf(y,(1.0/3.0)) - 16) : (903.3*y);
devA[index] = 500.0f * (fx - fy);
devB[index] = 200.0f * (fy - fz);
}
}
	.file	"tmpxft_00200039_00000000-6_rgbUtoLab3F_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z18rgbUtoLab3F_kerneliifPjPfS0_S0_iifPjPfS0_S0_
	.type	_Z49__device_stub__Z18rgbUtoLab3F_kerneliifPjPfS0_S0_iifPjPfS0_S0_, @function
_Z49__device_stub__Z18rgbUtoLab3F_kerneliifPjPfS0_S0_iifPjPfS0_S0_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movss	%xmm0, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z49__device_stub__Z18rgbUtoLab3F_kerneliifPjPfS0_S0_iifPjPfS0_S0_, .-_Z49__device_stub__Z18rgbUtoLab3F_kerneliifPjPfS0_S0_iifPjPfS0_S0_
	.globl	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
	.type	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_, @function
_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z18rgbUtoLab3F_kerneliifPjPfS0_S0_iifPjPfS0_S0_
	.cfi_endproc
.LFE2033:
	.size	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_, .-_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rgbUtoLab3F_kernel(int width, int height, float gamma, unsigned int* rgbU, float* devL, float* devA, float* devB) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < width) && (y0 < height)) {
int index = y0 * width + x0;
unsigned int rgb = rgbU[index];
float r = (float)(rgb & 0xff)/255.0;
float g = (float)((rgb & 0xff00) >> 8)/255.0;
float b = (float)((rgb & 0xff0000) >> 16)/255.0;
r = powf(r, gamma);
g = powf(g, gamma);
b = powf(b, gamma);
float x = (0.412453 * r) +  (0.357580 * g) + (0.180423 * b);
float y = (0.212671 * r) +  (0.715160 * g) + (0.072169 * b);
float z = (0.019334 * r) +  (0.119193 * g) + (0.950227 * b);
/*D65 white point reference */
const float x_ref = 0.950456;
const float y_ref = 1.000000;
const float z_ref = 1.088754;
/* threshold value  */
const float threshold = 0.008856;
x = x / x_ref;
y = y / y_ref;
z = z / z_ref;

float fx =
(x > threshold) ? powf(x,(1.0/3.0)) : (7.787*x + (16.0/116.0));
float fy =
(y > threshold) ? powf(y,(1.0/3.0)) : (7.787*y + (16.0/116.0));
float fz =
(z > threshold) ? powf(z,(1.0/3.0)) : (7.787*z + (16.0/116.0));
/* compute Lab color value */
devL[index] =
(y > threshold) ? (116*powf(y,(1.0/3.0)) - 16) : (903.3*y);
devA[index] = 500.0f * (fx - fy);
devB[index] = 200.0f * (fy - fz);
}
}
	.text
	.file	"rgbUtoLab3F_kernel.hip"
	.globl	_Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_ # -- Begin function _Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_
	.type	_Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_,@function
_Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_: # @_Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	56(%rsp), %r10
	movq	%rdx, (%r10)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_, .Lfunc_end0-_Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_,@object # @_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
	.p2align	3, 0x0
_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_:
	.quad	_Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_
	.size	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__rgbUtoLab3F_kerneliifPjPfS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_ ; -- Begin function _Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
	.globl	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
	.p2align	8
	.type	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_,@function
_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_:    ; @_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_18
; %bb.1:
	s_load_b256 s[8:15], s[0:1], 0x10
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_mov_b32 s5, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xff, v6
	v_bfe_u32 v4, v6, 8, 8
	v_bfe_u32 v6, v6, 16, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_u32_e32 v[2:3], v2
	v_cvt_f64_u32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_u32_e32 v[6:7], v6
	v_div_scale_f64 v[8:9], null, 0x406fe000, 0x406fe000, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[10:11], null, 0x406fe000, 0x406fe000, v[4:5]
	v_div_scale_f64 v[12:13], null, 0x406fe000, 0x406fe000, v[6:7]
	v_div_scale_f64 v[26:27], vcc_lo, v[2:3], 0x406fe000, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[14:15], v[8:9]
	v_rcp_f64_e32 v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[18:19], v[12:13]
	v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[10:11], v[16:17], 1.0
	v_fma_f64 v[24:25], -v[12:13], v[18:19], 1.0
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
	v_fma_f64 v[22:23], -v[10:11], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], -v[12:13], v[18:19], 1.0
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_div_scale_f64 v[20:21], s0, v[4:5], 0x406fe000, v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	v_div_scale_f64 v[22:23], s1, v[6:7], 0x406fe000, v[6:7]
	v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
	v_mul_f64 v[24:25], v[26:27], v[14:15]
	v_mul_f64 v[28:29], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[30:31], v[22:23], v[18:19]
	v_fma_f64 v[8:9], -v[8:9], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], -v[10:11], v[28:29], v[20:21]
	v_fma_f64 v[12:13], -v[12:13], v[30:31], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[24:25]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[10:11], v[10:11], v[16:17], v[28:29]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[12:13], v[12:13], v[18:19], v[30:31]
	v_div_fixup_f64 v[2:3], v[8:9], 0x406fe000, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[4:5], v[10:11], 0x406fe000, v[4:5]
	v_div_fixup_f64 v[6:7], v[12:13], 0x406fe000, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_f64_e32 v4, v[4:5]
	v_cvt_f32_f64_e32 v5, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v7, v[6:7]
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v4
	v_cndmask_b32_e64 v2, 1.0, s6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	v_cmp_neq_f32_e64 s8, v2, |v2|
	v_cmp_gt_f32_e64 s1, 0, v2
	v_cndmask_b32_e32 v3, 1.0, v4, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v5
	v_frexp_mant_f32_e32 v8, v3
	v_cndmask_b32_e64 v4, 1.0, s6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v7
	v_frexp_exp_i32_f32_e32 v11, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v8
	v_cmp_neq_f32_e64 s7, v4, |v4|
	v_cndmask_b32_e64 v6, 1.0, s6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, 0, 1, s2
	v_subrev_co_ci_u32_e64 v11, s2, 0, v11, s2
	v_cmp_neq_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f32 v8, v8, v9
	v_cndmask_b32_e32 v5, 1.0, v5, vcc_lo
	v_cvt_f32_i32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, 1.0, v7, s0
	v_cmp_gt_f32_e32 vcc_lo, 0, v4
	v_frexp_mant_f32_e32 v10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e32 v12, v7
	v_frexp_exp_i32_f32_e32 v15, v7
	v_cmp_gt_f32_e64 s3, 0x3f2aaaab, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e64 s4, 0x3f2aaaab, v12
	v_cndmask_b32_e64 v14, 0, 1, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, 0, 1, s4
	v_subrev_co_ci_u32_e64 v15, s2, 0, v15, s4
	v_ldexp_f32 v10, v10, v14
	v_add_f32_e32 v14, -1.0, v8
	v_add_f32_e32 v13, 1.0, v8
	v_ldexp_f32 v12, v12, v16
	v_frexp_exp_i32_f32_e32 v9, v5
	v_cvt_f32_i32_e32 v15, v15
	v_cmp_eq_f32_e64 s4, 0x7f800000, v3
	v_rcp_f32_e32 v17, v13
	v_cmp_gt_f32_e64 s0, 1.0, v5
	v_subrev_co_ci_u32_e64 v9, s3, 0, v9, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s0, s7, s0
	v_cvt_f32_i32_e32 v9, v9
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v16, v14, v17 :: v_dual_add_f32 v19, 1.0, v10
	v_add_f32_e32 v20, -1.0, v13
	v_add_f32_e32 v18, -1.0, v10
	v_add_f32_e32 v22, 1.0, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v21, v13, v16
	v_add_f32_e32 v25, -1.0, v19
	v_rcp_f32_e32 v23, v19
	v_sub_f32_e32 v8, v8, v20
	v_rcp_f32_e32 v24, v22
	v_fma_f32 v13, v16, v13, -v21
	v_sub_f32_e32 v10, v10, v25
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v27, v18, v23
	v_dual_fmac_f32 v13, v16, v8 :: v_dual_mul_f32 v8, 0x3f317218, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v20, -1.0, v12 :: v_dual_add_f32 v29, v21, v13
	v_add_f32_e32 v28, -1.0, v22
	v_dual_mul_f32 v26, 0x3f317218, v11 :: v_dual_mul_f32 v31, v20, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v30, 0x3f317218, v15 :: v_dual_sub_f32 v21, v29, v21
	v_sub_f32_e32 v25, v14, v29
	v_fma_f32 v33, 0x3f317218, v9, -v8
	v_sub_f32_e32 v12, v12, v28
	v_sub_f32_e32 v14, v14, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v32, v19, v27 :: v_dual_fmac_f32 v33, 0xb102e308, v9
	v_fma_f32 v19, v27, v19, -v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v34, v22, v31 :: v_dual_fmac_f32 v19, v27, v10
	v_fma_f32 v22, v31, v22, -v34
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v22, v31, v12
	v_sub_f32_e32 v10, v21, v13
	v_sub_f32_e32 v13, v14, v29
	v_fma_f32 v21, 0x3f317218, v15, -v30
	v_fma_f32 v14, 0x3f317218, v11, -v26
	v_add_f32_e32 v9, v34, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v10, v10, v13 :: v_dual_fmac_f32 v21, 0xb102e308, v15
	v_fmac_f32_e32 v14, 0xb102e308, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v28, v9, v34
	v_dual_add_f32 v10, v25, v10 :: v_dual_sub_f32 v25, v20, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v10, v17, v10 :: v_dual_sub_f32 v17, v20, v25
	v_add_f32_e32 v12, v32, v19
	v_add_f32_e32 v15, v16, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v17, v9
	v_sub_f32_e32 v13, v18, v12
	v_sub_f32_e32 v11, v12, v32
	v_add_f32_e32 v17, v26, v14
	v_ldexp_f32 v32, v15, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v18, v18, v13 :: v_dual_sub_f32 v11, v11, v19
	v_sub_f32_e32 v12, v18, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v11, v12 :: v_dual_sub_f32 v18, v28, v22
	v_dual_add_f32 v12, v8, v33 :: v_dual_add_f32 v11, v13, v11
	v_mul_f32_e32 v13, v15, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v9, v18, v9 :: v_dual_sub_f32 v16, v15, v16
	v_dual_sub_f32 v8, v12, v8 :: v_dual_mul_f32 v11, v23, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, v15, v15, -v13
	v_dual_add_f32 v9, v25, v9 :: v_dual_sub_f32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v33, v8
	v_add_f32_e32 v20, v27, v11
	v_add_f32_e32 v16, v30, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v9, v24, v9
	v_add_f32_e32 v19, v10, v10
	v_dual_sub_f32 v22, v17, v26 :: v_dual_mul_f32 v25, v20, v20
	v_ldexp_f32 v29, v20, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v23, v31, v9
	v_dual_fmac_f32 v18, v15, v19 :: v_dual_sub_f32 v19, v16, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v14, v22
	v_fma_f32 v28, v20, v20, -v25
	v_sub_f32_e32 v26, v23, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v22, v13, v18
	v_ldexp_f32 v34, v10, 1
	v_sub_f32_e32 v19, v21, v19
	v_sub_f32_e32 v9, v9, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v22, v13
	v_add_f32_e32 v31, v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v13, v18, v13 :: v_dual_sub_f32 v24, v20, v27
	v_fmaak_f32 v27, s5, v22, 0x3e91f4c4
	v_mul_f32_e32 v37, v15, v22
	v_sub_f32_e32 v11, v11, v24
	v_mul_f32_e32 v24, v23, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v42, v22, v15, -v37
	v_add_f32_e32 v26, v11, v11
	v_fmaak_f32 v27, v22, v27, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, v23, v23, -v24
	v_fmac_f32_e32 v28, v20, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v30, v23, v31
	v_dual_mul_f32 v26, v22, v27 :: v_dual_add_f32 v31, v25, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v35, v24, v30
	v_fma_f32 v18, v22, v27, -v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v36, s5, v31, 0x3e91f4c4 :: v_dual_sub_f32 v25, v31, v25
	v_sub_f32_e32 v24, v35, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v18, v13, v27
	v_mul_f32_e32 v27, v20, v31
	v_dual_mul_f32 v40, v23, v35 :: v_dual_sub_f32 v25, v28, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v38, s5, v35, 0x3e91f4c4 :: v_dual_add_f32 v39, v26, v18
	v_fma_f32 v28, v31, v20, -v27
	v_cmp_eq_f32_e64 s5, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v26, v39, v26 :: v_dual_add_f32 v41, 0x3f2aaaaa, v39
	v_fmac_f32_e32 v28, v31, v11
	v_ldexp_f32 v11, v11, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_xor_b32 s1, s1, s5
	v_sub_f32_e32 v18, v18, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v28, v25, v20
	v_fmac_f32_e32 v42, v22, v10
	v_add_f32_e32 v18, 0x31739010, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v13, v15
	v_add_f32_e32 v20, v37, v42
	v_fmaak_f32 v38, v35, v38, 0x3ecccdef
	v_add_f32_e32 v26, 0xbf2aaaaa, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v26, v39, v26
	v_add_f32_e32 v18, v18, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v36, v31, v36, 0x3ecccdef :: v_dual_add_f32 v15, v41, v18
	v_dual_mul_f32 v43, v31, v36 :: v_dual_mul_f32 v26, v20, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v31, v36, -v43
	v_dual_sub_f32 v31, v20, v37 :: v_dual_mul_f32 v22, v35, v38
	v_fmac_f32_e32 v10, v25, v36
	v_sub_f32_e32 v24, v30, v24
	v_fma_f32 v30, v35, v23, -v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v13, v35, v38, -v22
	v_add_f32_e32 v25, v43, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, v24, v38 :: v_dual_fmac_f32 v30, v35, v9
	v_dual_add_f32 v35, 0x3f2aaaaa, v25 :: v_dual_sub_f32 v36, v25, v43
	v_ldexp_f32 v9, v9, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v37, v22, v13 :: v_dual_fmac_f32 v30, v24, v23
	v_sub_f32_e32 v24, v41, v15
	v_sub_f32_e32 v10, v10, v36
	v_add_f32_e32 v36, 0xbf2aaaaa, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v18, v18, v24
	v_fma_f32 v24, v20, v15, -v26
	v_add_f32_e32 v10, 0x31739010, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v24, v20, v18
	v_add_f32_e32 v18, 0x3f2aaaaa, v37
	v_sub_f32_e32 v20, v37, v22
	v_sub_f32_e32 v22, v25, v36
	v_dual_sub_f32 v13, v13, v20 :: v_dual_add_f32 v20, 0xbf2aaaaa, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v10, v22 :: v_dual_add_f32 v13, 0x31739010, v13
	v_sub_f32_e32 v20, v37, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v13, v20
	v_add_f32_e32 v25, v40, v30
	v_sub_f32_e32 v31, v42, v31
	v_fmac_f32_e32 v24, v31, v15
	v_add_f32_e32 v31, v35, v10
	v_add_f32_e32 v15, v27, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v20, v35, v31 :: v_dual_add_f32 v35, v18, v13
	v_dual_sub_f32 v27, v15, v27 :: v_dual_add_f32 v10, v10, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v18, v35
	v_sub_f32_e32 v27, v28, v27
	v_mul_f32_e32 v28, v25, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v13, v18 :: v_dual_add_f32 v22, v26, v24
	v_add_f32_e32 v36, v32, v22
	v_sub_f32_e32 v26, v22, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v32, v36, v32
	v_sub_f32_e32 v24, v24, v26
	v_mul_f32_e32 v26, v15, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v22, v32
	v_add_f32_e32 v22, v34, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, v15, v31, -v26
	v_add_f32_e32 v20, v22, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v24, v15, v10
	v_sub_f32_e32 v10, v25, v40
	v_fma_f32 v15, v25, v35, -v28
	v_ldexp_f32 v22, v23, 1
	v_add_f32_e32 v18, v36, v20
	v_fmac_f32_e32 v24, v27, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v10, v30, v10 :: v_dual_fmac_f32 v15, v25, v13
	v_add_f32_e32 v13, v17, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v23, v26, v24
	v_dual_fmac_f32 v15, v10, v35 :: v_dual_sub_f32 v10, v13, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v25, v29, v23 :: v_dual_sub_f32 v26, v23, v26
	v_dual_add_f32 v30, v28, v15 :: v_dual_sub_f32 v31, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v10, v18, v10 :: v_dual_sub_f32 v29, v25, v29
	v_dual_sub_f32 v24, v24, v26 :: v_dual_sub_f32 v17, v17, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v11, v11, v24 :: v_dual_add_f32 v10, v10, v17
	v_sub_f32_e32 v17, v30, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v27, v18, v36 :: v_dual_sub_f32 v18, v23, v29
	v_add_f32_e32 v23, v22, v30
	v_dual_sub_f32 v15, v15, v17 :: v_dual_sub_f32 v20, v20, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v11, v18
	v_dual_sub_f32 v18, v23, v22 :: v_dual_add_f32 v9, v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v24, v14, v20 :: v_dual_add_f32 v17, v25, v11
	v_sub_f32_e32 v18, v30, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v22, v24, v14
	v_add_f32_e32 v10, v24, v10
	v_add_f32_e32 v15, v12, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v9, v9, v18
	v_sub_f32_e32 v24, v24, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v26, v13, v10
	v_sub_f32_e32 v20, v20, v22
	v_sub_f32_e32 v18, v15, v12
	v_sub_f32_e32 v14, v14, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v13, v26, v13
	v_sub_f32_e32 v21, v15, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v20, v14
	v_sub_f32_e32 v10, v10, v13
	v_add_f32_e32 v13, v23, v9
	v_sub_f32_e32 v20, v17, v25
	v_dual_sub_f32 v17, v17, v18 :: v_dual_sub_f32 v12, v12, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v14, v10
	v_dual_sub_f32 v14, v13, v23 :: v_dual_sub_f32 v11, v11, v20
	v_add_f32_e32 v20, v16, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v12, v17, v12
	v_add_f32_e32 v18, v26, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v9, v14 :: v_dual_add_f32 v14, v8, v11
	v_dual_sub_f32 v22, v20, v16 :: v_dual_sub_f32 v17, v18, v26
	v_mul_f32_e32 v21, v2, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v23, v14, v8
	v_dual_add_f32 v12, v14, v12 :: v_dual_sub_f32 v13, v13, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v10, v17
	v_fma_f32 v17, v2, v18, -v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v14, v23
	v_add_f32_e32 v24, v15, v12
	v_cmp_class_f32_e64 s2, v21, 0x204
	v_sub_f32_e32 v18, v20, v22
	v_dual_fmac_f32 v17, v2, v10 :: v_dual_sub_f32 v10, v11, v23
	v_sub_f32_e32 v8, v8, v14
	v_dual_sub_f32 v11, v24, v15 :: v_dual_add_f32 v14, v19, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v15, v21, v17 :: v_dual_sub_f32 v16, v16, v18
	v_add_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v12, v11
	v_sub_f32_e32 v12, v14, v19
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v15, v21, s2
	v_sub_f32_e32 v15, v15, v21
	v_cmp_eq_f32_e64 s2, 0x7f800000, v5
	v_add_f32_e32 v8, v8, v10
	v_add_f32_e32 v10, v13, v16
	v_cmp_eq_f32_e64 s3, 0x42b17218, v11
	v_sub_f32_e32 v18, v14, v12
	v_sub_f32_e32 v9, v9, v12
	v_add_f32_e32 v16, v24, v8
	v_add_f32_e32 v10, v14, v10
	v_cndmask_b32_e64 v13, 0, 0x37000000, s3
	v_sub_f32_e32 v18, v19, v18
	v_cmp_gt_f32_e64 s3, 1.0, v3
	v_sub_f32_e32 v12, v16, v24
	v_mul_f32_e32 v22, v4, v16
	v_dual_sub_f32 v14, v11, v13 :: v_dual_add_f32 v23, v20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v9, v9, v18 :: v_dual_sub_f32 v8, v8, v12
	v_fma_f32 v12, v4, v16, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v24, 0x3fb8aa3b, v14
	v_sub_f32_e32 v16, v23, v20
	v_cmp_class_f32_e64 s6, v22, 0x204
	s_xor_b32 s3, s8, s3
	v_fmac_f32_e32 v12, v4, v8
	v_fma_f32 v19, 0x3fb8aa3b, v14, -v24
	v_rndne_f32_e32 v20, v24
	v_sub_f32_e32 v8, v10, v16
	v_cndmask_b32_e64 v18, |v2|, 0, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v16, v22, v12 :: v_dual_fmac_f32 v19, 0x32a5705f, v14
	v_sub_f32_e32 v10, v24, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v8, v9, v8
	v_cvt_i32_f32_e32 v20, v20
	v_sub_f32_e32 v15, v17, v15
	v_add_f32_e32 v9, v10, v19
	v_cndmask_b32_e64 v10, v16, v22, s6
	v_add_f32_e32 v19, v23, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v9, v9
	v_cmp_eq_f32_e64 s3, 0x42b17218, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v23, v19, v23
	v_mul_f32_e32 v24, v6, v19
	v_cndmask_b32_e64 v21, 0, 0x37000000, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v11|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v8, v23
	v_fma_f32 v19, v6, v19, -v24
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_ldexp_f32 v9, v9, v20
	v_sub_f32_e32 v17, v10, v21
	v_cndmask_b32_e64 v11, 0, v15, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v14
	v_fmac_f32_e32 v19, v6, v8
	v_mul_f32_e32 v15, 0x3fb8aa3b, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v11, v13, v11
	v_cndmask_b32_e64 v9, 0, v9, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v14
	v_cndmask_b32_e64 v14, 0x7f800000, 0, s1
	v_cmp_eq_f32_e64 s1, 1.0, v3
	v_fma_f32 v13, 0x3fb8aa3b, v17, -v15
	v_rndne_f32_e32 v20, v15
	v_cndmask_b32_e64 v9, 0x7f800000, v9, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v17
	v_cndmask_b32_e64 v3, v18, v3, s1
	v_fmac_f32_e32 v13, 0x32a5705f, v17
	v_sub_f32_e32 v15, v15, v20
	v_fma_f32 v8, v9, v11, v9
	v_cmp_eq_f32_e64 s1, 0x7f800000, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, v15, v13
	v_sub_f32_e32 v13, v16, v22
	v_cndmask_b32_e64 v8, v8, v9, s1
	v_cmp_class_f32_e64 s1, v2, 0x204
	v_add_f32_e32 v9, v24, v19
	v_exp_f32_e32 v11, v11
	v_sub_f32_e32 v12, v12, v13
	v_cvt_i32_f32_e32 v13, v20
	v_cndmask_b32_e64 v3, |v8|, v3, s1
	v_cmp_class_f32_e64 s1, v24, 0x204
	v_cndmask_b32_e64 v15, |v4|, 0, s0
	v_cmp_eq_f32_e64 s0, 1.0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_cndmask_b32_e64 v8, v9, v24, s1
	s_or_b32 s1, s5, s4
	v_ldexp_f32 v11, v11, v13
	v_cndmask_b32_e64 v3, v3, v14, s1
	v_sub_f32_e32 v9, v9, v24
	v_cmp_eq_f32_e64 s1, 0x42b17218, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v19, v9
	v_cndmask_b32_e64 v14, 0, 0x37000000, s1
	v_cmp_o_f32_e64 s1, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, 0x7fc00000, v3, s1
	v_cmp_neq_f32_e64 s1, 0x7f800000, |v10|
	v_cvt_f64_f32_e32 v[2:3], v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0, v12, s1
	v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v17
	v_sub_f32_e32 v12, v8, v14
	v_add_f32_e32 v10, v21, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 0, v11, s1
	v_mul_f32_e32 v13, 0x3fb8aa3b, v12
	v_cmp_eq_f32_e64 s1, 0, v5
	v_cndmask_b32_e64 v5, v15, v5, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, 0x7f800000, v11, s3
	v_fma_f32 v16, 0x3fb8aa3b, v12, -v13
	v_rndne_f32_e32 v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v10, v11, v10, v11
	v_cmp_eq_f32_e64 s0, 0x7f800000, v11
	v_dual_fmac_f32 v16, 0x32a5705f, v12 :: v_dual_sub_f32 v13, v13, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v10, v11, s0
	s_xor_b32 s0, vcc_lo, s1
	v_add_f32_e32 v13, v13, v16
	v_cndmask_b32_e64 v11, 0x7f800000, 0, s0
	v_cmp_class_f32_e64 s0, v4, 0x204
	s_or_b32 vcc_lo, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, |v10|, v5, s0
	v_exp_f32_e32 v10, v13
	s_mov_b32 s0, 0x396d0918
	s_mov_b32 s1, 0x3fd6e297
	v_cndmask_b32_e32 v5, v5, v11, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v4, v4
	v_cvt_i32_f32_e32 v11, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v8|
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v10, v11
	v_cvt_f64_f32_e32 v[4:5], v4
	v_cndmask_b32_e32 v11, 0, v9, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
	v_mul_f64 v[8:9], v[2:3], s[0:1]
	v_cmp_neq_f32_e64 s1, v6, |v6|
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v12
	v_dual_add_f32 v11, v14, v11 :: v_dual_cndmask_b32 v10, 0, v10
	v_cmp_gt_f32_e32 vcc_lo, 1.0, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 0x7f800000, v10, s0
	s_xor_b32 s0, s1, vcc_lo
	v_cmp_eq_f32_e64 s1, 1.0, v7
	v_cndmask_b32_e64 v12, |v6|, 0, s0
	v_cmp_gt_f32_e32 vcc_lo, 0, v6
	v_cmp_eq_f32_e64 s0, 0, v7
	v_fma_f32 v11, v10, v11, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v7, s1
	v_cmp_eq_f32_e64 s1, 0x7f800000, v10
	s_xor_b32 s2, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v11, v10, s1
	v_cmp_eq_f32_e64 s1, 0x7f800000, v7
	v_cndmask_b32_e64 v7, 0x7f800000, 0, s2
	v_cmp_class_f32_e64 s2, v6, 0x204
	s_or_b32 vcc_lo, s0, s1
	s_mov_b32 s0, 0x4488c60d
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, |v10|, v12, s2
	s_mov_b32 s1, 0x3fda65a1
	v_cndmask_b32_e32 v7, v10, v7, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v6, v6
	v_fma_f64 v[8:9], v[4:5], s[0:1], v[8:9]
	s_mov_b32 s0, 0xd2391d58
	s_mov_b32 s1, 0x3fc71819
	v_cndmask_b32_e32 v6, 0x7fc00000, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[6:7], v6
	v_fma_f64 v[8:9], v[6:7], s[0:1], v[8:9]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v8, v[8:9]
	v_div_scale_f32 v9, null, 0x3f735116, 0x3f735116, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	v_div_scale_f32 v11, vcc_lo, v8, 0x3f735116, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v11, v10
	v_fma_f32 v13, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v10
	v_fma_f32 v9, -v9, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v10, v12
                                        ; implicit-def: $vgpr10
	v_div_fixup_f32 v8, v9, 0x3f735116, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f32_e32 0x3c1118c2, v8
	s_xor_b32 s0, exec_lo, s0
; %bb.2:
	v_cvt_f64_f32_e32 v[8:9], v8
	s_mov_b32 s2, 0x611a7b96
	s_mov_b32 s4, 0x53f7ced9
	s_mov_b32 s3, 0x3fc1a7b9
	s_mov_b32 s5, 0x401f25e3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[8:9], s[4:5], s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v10, v[8:9]
                                        ; implicit-def: $vgpr8
; %bb.3:                                ; %Flow88
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_frexp_mant_f32_e64 v9, |v8|
	s_mov_b32 s0, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v9
	v_cndmask_b32_e64 v10, 0, 1, vcc_lo
	v_ldexp_f32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, -1.0, v9
	v_add_f32_e32 v10, 1.0, v9
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v13, v12, v11 :: v_dual_add_f32 v14, -1.0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v10, v13
	v_sub_f32_e32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v13, v10, -v15
	v_fmac_f32_e32 v10, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v15, v10
	v_dual_sub_f32 v14, v12, v9 :: v_dual_sub_f32 v15, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v15, v10
	v_sub_f32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v12, v9
	v_add_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v14, v9
	v_mul_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v13, v9
	v_mul_f32_e32 v12, v10, v10
	v_sub_f32_e32 v11, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v9, v11
	v_fma_f32 v11, v10, v10, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v9, v9
	v_fmac_f32_e32 v11, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v12, v11
	v_fmaak_f32 v14, s0, v13, 0x3e91f4c4
	v_sub_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v14, v13, v14, 0x3ecccdef :: v_dual_sub_f32 v11, v11, v12
	v_mul_f32_e32 v15, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v13, v14, -v15
	v_dual_fmac_f32 v12, v11, v14 :: v_dual_mul_f32 v17, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v15, v12
	v_fma_f32 v18, v13, v10, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v15, v14, v15 :: v_dual_fmac_f32 v18, v13, v9
	v_add_f32_e32 v16, 0x3f2aaaaa, v14
	v_ldexp_f32 v9, v9, 1
	v_sub_f32_e32 v12, v12, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v11, v10
	v_ldexp_f32 v10, v10, 1
	v_add_f32_e32 v12, 0x31739010, v12
	v_add_f32_e32 v15, 0xbf2aaaaa, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v15
	v_add_f32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v16, v12
	v_dual_add_f32 v13, v17, v18 :: v_dual_sub_f32 v14, v16, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v13, v11
	v_sub_f32_e32 v16, v13, v17
	v_add_f32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v13, v11, -v15
	v_sub_f32_e32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v13, v12
	v_frexp_exp_i32_f32_e32 v12, v8
	v_fmac_f32_e32 v14, v16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v8
	v_add_f32_e32 v12, v15, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v11, v11
	v_sub_f32_e32 v15, v12, v15
	v_add_f32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v15
	v_dual_mul_f32 v16, 0x3f317218, v11 :: v_dual_add_f32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, 0x3f317218, v11, -v16
	v_dual_fmamk_f32 v11, v11, 0xb102e308, v15 :: v_dual_sub_f32 v10, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v12, v10
	v_dual_add_f32 v9, v9, v10 :: v_dual_add_f32 v10, v16, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v13, v9
	v_sub_f32_e32 v16, v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v11, v16
	v_add_f32_e32 v14, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v14, v10
	v_sub_f32_e32 v13, v12, v13
	v_sub_f32_e32 v17, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v9, v13 :: v_dual_sub_f32 v12, v12, v15
	v_sub_f32_e32 v10, v10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v11, v9 :: v_dual_add_f32 v10, v12, v10
	v_sub_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v13, v10
	v_sub_f32_e32 v13, v13, v12
	v_sub_f32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v13
	v_add_f32_e32 v15, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v9, v9, v11 :: v_dual_sub_f32 v12, v15, v14
	v_cndmask_b32_e64 v11, 0x3eaaaaab, 1.0, vcc_lo
	v_sub_f32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v10
	v_add_f32_e32 v10, v15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v10, v15 :: v_dual_mul_f32 v13, v11, v10
	v_sub_f32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v11, v10, -v13
	v_cmp_class_f32_e64 vcc_lo, v13, 0x204
	v_fmac_f32_e32 v10, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v13, v10
	v_cndmask_b32_e32 v12, v9, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
	v_sub_f32_e32 v15, v12, v14
	v_trunc_f32_e32 v12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, 0x3fb8aa3b, v15 :: v_dual_sub_f32 v9, v9, v13
	v_fma_f32 v17, 0x3fb8aa3b, v15, -v16
	v_rndne_f32_e32 v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v10, v9
	v_dual_fmamk_f32 v17, v15, 0x32a5705f, v17 :: v_dual_sub_f32 v16, v16, v18
	v_cvt_i32_f32_e32 v13, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v16, v17
	v_exp_f32_e32 v16, v16
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v16, v13
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v13, 0.5, v11 :: v_dual_cndmask_b32 v10, 0, v10
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	v_trunc_f32_e32 v16, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v9, v14, v9 :: v_dual_cndmask_b32 v10, 0x7f800000, v10
	v_cmp_eq_f32_e32 vcc_lo, v12, v11
	v_cmp_neq_f32_e64 s0, v16, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v9, v10, v9, v10
	v_cmp_eq_f32_e64 s1, 0x7f800000, v10
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 1.0, v8, s0
	v_cndmask_b32_e64 v12, 0, v8, s0
	v_cndmask_b32_e64 v9, v9, v10, s1
	v_cmp_eq_f32_e64 s1, 0, v8
	v_cmp_class_f32_e64 s0, v8, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v9, 0x7fffffff, v9, v11
	v_cndmask_b32_e64 v10, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, 0x7fc00000, v9, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v8
	v_bfi_b32 v10, 0x7fffffff, v10, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, v9, v11, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v8, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v10, 0x7fc00000, v9, vcc_lo
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s0, 0x396d0918
	s_mov_b32 s1, 0x3fe6e297
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_f64 v[8:9], v[2:3], s[0:1]
	s_mov_b32 s0, 0xa6e75ff6
	s_mov_b32 s1, 0x3fcb38cd
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[4:5], s[0:1], v[8:9]
	s_mov_b32 s0, 0xe6c8f755
	s_mov_b32 s1, 0x3fb279aa
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], s[0:1], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v11, v[8:9]
	v_cvt_f64_f32_e32 v[8:9], v11
	v_cmp_nlt_f32_e64 s0, 0x3c1118c2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
; %bb.6:
	s_mov_b32 s2, 0x611a7b96
	s_mov_b32 s4, 0x53f7ced9
	s_mov_b32 s3, 0x3fc1a7b9
	s_mov_b32 s5, 0x401f25e3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[8:9], s[4:5], s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v13, v[12:13]
; %bb.7:                                ; %Flow87
	s_or_saveexec_b32 s4, s1
	v_frexp_mant_f32_e64 v14, |v11|
	v_frexp_exp_i32_f32_e32 v12, v11
	v_cmp_class_f32_e64 s3, v11, 0x204
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v14
	s_mov_b32 s1, 0x3e76c4e1
	v_cndmask_b32_e64 v13, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v13, v14, v13
	v_add_f32_e32 v17, -1.0, v13
	v_add_f32_e32 v15, 1.0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v15
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v18, v17, v16
	v_dual_mul_f32 v20, v15, v18 :: v_dual_add_f32 v19, -1.0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, v18, v15, -v20
	v_sub_f32_e32 v13, v13, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v18, v13
	v_add_f32_e32 v13, v20, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v17, v13
	v_sub_f32_e32 v20, v13, v20
	v_sub_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v20, v15
	v_sub_f32_e32 v13, v17, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v15, v13
	v_add_f32_e32 v13, v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v16, v13
	v_add_f32_e32 v15, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v15, v18
	v_mul_f32_e32 v17, v15, v15
	v_sub_f32_e32 v13, v13, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, v15, v15, -v17
	v_add_f32_e32 v18, v13, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v15, v18
	v_add_f32_e32 v18, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v19, s1, v18, 0x3e91f4c4
	v_dual_sub_f32 v17, v18, v17 :: v_dual_mul_f32 v22, v15, v18
	v_dual_fmaak_f32 v19, v18, v19, 0x3ecccdef :: v_dual_sub_f32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, v18, v15, -v22
	v_mul_f32_e32 v20, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v23, v18, v13
	v_ldexp_f32 v13, v13, 1
	v_fma_f32 v17, v18, v19, -v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, v16, v15
	v_fmac_f32_e32 v17, v16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v18, v22, v23 :: v_dual_add_f32 v19, v20, v17
	v_dual_sub_f32 v20, v19, v20 :: v_dual_add_f32 v21, 0x3f2aaaaa, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v17, v20 :: v_dual_add_f32 v20, 0xbf2aaaaa, v21
	v_add_f32_e32 v17, 0x31739010, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v19, v19, v20
	v_add_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v21, v17
	v_sub_f32_e32 v19, v21, v16
	v_mul_f32_e32 v20, v18, v16
	v_sub_f32_e32 v21, v18, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v17, v17, v19
	v_fma_f32 v19, v18, v16, -v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v23, v21
	v_fmac_f32_e32 v19, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v19, v21, v16
	v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v12, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v11
	v_add_f32_e32 v17, v20, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v16, v16
	v_sub_f32_e32 v20, v17, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, 0x3f317218, v16
	v_sub_f32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, 0x3f317218, v16, -v21
	v_dual_add_f32 v13, v13, v19 :: v_dual_fmamk_f32 v16, v16, 0xb102e308, v20
	v_ldexp_f32 v15, v15, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v15, v17
	v_sub_f32_e32 v15, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v17, v15
	v_add_f32_e32 v13, v13, v15
	v_add_f32_e32 v15, v21, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v18, v13
	v_sub_f32_e32 v21, v15, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v19, v15, v17 :: v_dual_sub_f32 v18, v17, v18
	v_sub_f32_e32 v16, v16, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v20, v19, v15 :: v_dual_sub_f32 v13, v13, v18
	v_sub_f32_e32 v22, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v17, v20 :: v_dual_add_f32 v18, v16, v13
	v_sub_f32_e32 v15, v15, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v17, v15
	v_sub_f32_e32 v17, v18, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v18, v15
	v_sub_f32_e32 v18, v18, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v13, v13, v17 :: v_dual_add_f32 v20, v19, v15
	v_sub_f32_e32 v16, v16, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v20, v19
	v_add_f32_e32 v13, v13, v16
	v_cndmask_b32_e64 v16, 0x3eaaaaab, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v17
	v_add_f32_e32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v20, v13
	v_dual_sub_f32 v17, v15, v20 :: v_dual_mul_f32 v18, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v17
	v_fma_f32 v15, v16, v15, -v18
	v_cmp_class_f32_e64 vcc_lo, v18, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v16, v13
	v_add_f32_e32 v13, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v13, v18, vcc_lo
	v_sub_f32_e32 v13, v13, v18
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v15, v13
	v_cndmask_b32_e64 v19, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v17|
	v_dual_sub_f32 v20, v17, v19 :: v_dual_cndmask_b32 v13, 0, v13
	v_trunc_f32_e32 v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v21, 0x3fb8aa3b, v20
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
	v_add_f32_e32 v13, v19, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v22, 0x3fb8aa3b, v20, -v21
	v_rndne_f32_e32 v23, v21
	v_dual_fmamk_f32 v22, v20, 0x32a5705f, v22 :: v_dual_sub_f32 v21, v21, v23
	v_cvt_i32_f32_e32 v18, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v21, v22
	v_exp_f32_e32 v21, v21
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v15, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v18, 0.5, v16 :: v_dual_cndmask_b32 v15, 0, v15
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
	v_trunc_f32_e32 v21, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, 0x7f800000, v15, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v17, v16
	v_cmp_neq_f32_e64 s1, v21, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v13, v15, v13, v15
	v_cmp_eq_f32_e64 s2, 0x7f800000, v15
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, 1.0, v11, s1
	v_cndmask_b32_e64 v17, 0, v11, s1
	v_cndmask_b32_e64 v13, v13, v15, s2
	v_cmp_eq_f32_e64 s2, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v13, 0x7fffffff, v13, v16
	v_cndmask_b32_e64 v15, 0x7f800000, 0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, 0x7fc00000, v13, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v11
	v_bfi_b32 v15, 0x7fffffff, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v13, v16, vcc_lo
	s_or_b32 vcc_lo, s2, s3
	v_cndmask_b32_e32 v13, v13, v15, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v11, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v13, 0x7fc00000, v13, vcc_lo
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s4
	s_mov_b32 s4, 0xb4e98138
	s_mov_b32 s5, 0x3fbe836e
	s_mov_b32 s1, exec_lo
	v_mul_f64 v[2:3], v[2:3], s[4:5]
	s_mov_b32 s4, 0xc6cdaf4b
	s_mov_b32 s5, 0x3f93cc4a
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
	s_mov_b32 s4, 0x7418d691
	s_mov_b32 s5, 0x3fee6842
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], v[6:7], s[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v2, v[2:3]
	v_div_scale_f32 v3, null, 0x3f8b5c4b, 0x3f8b5c4b, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v2, 0x3f8b5c4b, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v4
	v_fma_f32 v7, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v4
	v_fma_f32 v3, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v6
	v_div_fixup_f32 v3, v3, 0x3f8b5c4b, v2
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f32_e32 0x3c1118c2, v3
	s_xor_b32 s1, exec_lo, s1
; %bb.10:
	v_cvt_f64_f32_e32 v[2:3], v3
	s_mov_b32 s4, 0x611a7b96
	s_mov_b32 s6, 0x53f7ced9
	s_mov_b32 s5, 0x3fc1a7b9
	s_mov_b32 s7, 0x401f25e3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], v[2:3], s[6:7], s[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v2, v[2:3]
                                        ; implicit-def: $vgpr3
; %bb.11:                               ; %Flow86
	s_and_not1_saveexec_b32 s4, s1
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_frexp_mant_f32_e64 v2, |v3|
	s_mov_b32 s1, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	v_ldexp_f32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, -1.0, v2
	v_add_f32_e32 v4, 1.0, v2
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v15, -1.0, v4 :: v_dual_mul_f32 v16, v4, v7
	v_sub_f32_e32 v2, v2, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v7, v4, -v16
	v_fmac_f32_e32 v4, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v16, v4
	v_sub_f32_e32 v15, v6, v2
	v_sub_f32_e32 v16, v2, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v15
	v_sub_f32_e32 v4, v16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v6, v2
	v_add_f32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v15, v2
	v_mul_f32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v7, v2
	v_sub_f32_e32 v5, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v5
	v_dual_mul_f32 v6, v4, v4 :: v_dual_add_f32 v7, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v4, v4, -v6
	v_fmac_f32_e32 v5, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v6, v5
	v_mul_f32_e32 v18, v4, v7
	v_fmaak_f32 v15, s1, v7, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, v7, v4, -v18
	v_fmaak_f32 v15, v7, v15, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, v7, v2
	v_sub_f32_e32 v6, v7, v6
	v_dual_mul_f32 v16, v7, v15 :: v_dual_sub_f32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v7, v15, -v16
	v_fmac_f32_e32 v19, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v7, v18, v19
	v_fmac_f32_e32 v6, v5, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v16, v6
	v_ldexp_f32 v2, v2, 1
	v_dual_sub_f32 v16, v15, v16 :: v_dual_add_f32 v17, 0x3f2aaaaa, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v16
	v_add_f32_e32 v16, 0xbf2aaaaa, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, 0x31739010, v6 :: v_dual_sub_f32 v15, v15, v16
	v_add_f32_e32 v6, v6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v17, v6
	v_sub_f32_e32 v15, v17, v5
	v_ldexp_f32 v4, v4, 1
	v_mul_f32_e32 v16, v7, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v7, v18 :: v_dual_add_f32 v6, v6, v15
	v_fma_f32 v15, v7, v5, -v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v19, v17
	v_fmac_f32_e32 v15, v7, v6
	v_frexp_exp_i32_f32_e32 v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v17, v5
	v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v16, v15
	v_cvt_f32_i32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v4, v6 :: v_dual_sub_f32 v16, v6, v16
	v_dual_mul_f32 v17, 0x3f317218, v5 :: v_dual_sub_f32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v16
	v_fma_f32 v16, 0x3f317218, v5, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v6, v4
	v_dual_add_f32 v2, v2, v15 :: v_dual_fmamk_f32 v5, v5, 0xb102e308, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v2, v4
	v_add_f32_e32 v4, v17, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v7, v2 :: v_dual_sub_f32 v17, v4, v17
	v_add_f32_e32 v15, v4, v6
	v_sub_f32_e32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v5, v5, v17 :: v_dual_sub_f32 v16, v15, v4
	v_sub_f32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v15, v16
	v_dual_sub_f32 v6, v6, v16 :: v_dual_add_f32 v7, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v18
	v_add_f32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v7, v5
	v_add_f32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v6
	v_sub_f32_e32 v2, v2, v6
	v_dual_add_f32 v16, v15, v4 :: v_dual_sub_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v16, v15
	v_add_f32_e32 v2, v2, v5
	v_cndmask_b32_e64 v5, 0x3eaaaaab, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v6
	v_add_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v16, v2
	v_sub_f32_e32 v6, v4, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v5, v4 :: v_dual_sub_f32 v2, v2, v6
	v_fma_f32 v4, v5, v4, -v7
	v_cmp_class_f32_e64 vcc_lo, v7, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v2
	v_add_f32_e32 v2, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v2, v7, vcc_lo
	v_sub_f32_e32 v2, v2, v7
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v4, v2
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	v_sub_f32_e32 v16, v6, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_trunc_f32_e32 v6, v5
	v_mul_f32_e32 v17, 0x3fb8aa3b, v16
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v15, v2
	v_fma_f32 v18, 0x3fb8aa3b, v16, -v17
	v_rndne_f32_e32 v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmamk_f32 v18, v16, 0x32a5705f, v18 :: v_dual_sub_f32 v17, v17, v19
	v_cvt_i32_f32_e32 v7, v19
	v_add_f32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v17, v17
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v17, v7
	v_dual_mul_f32 v7, 0.5, v5 :: v_dual_cndmask_b32 v4, 0, v4
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v17, v7
	v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v6, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s1, v17, v7
	v_fma_f32 v2, v4, v2, v4
	v_cmp_eq_f32_e64 s2, 0x7f800000, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	v_cndmask_b32_e64 v5, 1.0, v3, s1
	v_cndmask_b32_e64 v6, 0, v3, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v2, v4, s2
	v_cmp_eq_f32_e64 s2, 0, v3
	v_cmp_class_f32_e64 s1, v3, 0x204
	v_bfi_b32 v2, 0x7fffffff, v2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, 0x7f800000, 0, s2
	v_cndmask_b32_e32 v5, 0x7fc00000, v2, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v4, 0x7fffffff, v4, v6
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_or_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v3, v3
	v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
.LBB0_13:
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s1
; %bb.14:
	s_mov_b32 s4, 0x66666666
	s_mov_b32 s5, 0x408c3a66
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[8:9], s[4:5]
	v_cvt_f32_f64_e32 v3, v[3:4]
; %bb.15:                               ; %Flow
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v14
	s_mov_b32 s0, 0x3e76c4e1
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v3, v14, v3
	v_add_f32_e32 v6, -1.0, v3
	v_add_f32_e32 v4, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v7, v6, v5 :: v_dual_add_f32 v8, -1.0, v4
	v_mul_f32_e32 v9, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v3, v8
	v_fma_f32 v4, v7, v4, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v7, v3
	v_add_f32_e32 v3, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
	v_sub_f32_e32 v4, v9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v8
	v_sub_f32_e32 v3, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v4, v3
	v_add_f32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v5, v3
	v_add_f32_e32 v4, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v4, v4
	v_sub_f32_e32 v5, v4, v7
	v_sub_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v4, v4, -v6
	v_add_f32_e32 v7, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v4, v7
	v_add_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, s0, v7, 0x3e91f4c4
	v_sub_f32_e32 v6, v7, v6
	v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v7, v8
	v_fma_f32 v6, v7, v8, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v6, v5, v8 :: v_dual_mul_f32 v15, v4, v7
	v_add_f32_e32 v8, v9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, v7, v4, -v15
	v_dual_sub_f32 v9, v8, v9 :: v_dual_fmac_f32 v16, v7, v3
	v_add_f32_e32 v14, 0x3f2aaaaa, v8
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v6, v6, v9
	v_fmac_f32_e32 v16, v5, v4
	v_ldexp_f32 v4, v4, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, 0x31739010, v6
	v_add_f32_e32 v9, 0xbf2aaaaa, v14
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v8
	v_add_f32_e32 v5, v14, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v15, v16 :: v_dual_sub_f32 v8, v14, v5
	v_mul_f32_e32 v9, v7, v5
	v_sub_f32_e32 v14, v7, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v6, v8
	v_fma_f32 v8, v7, v5, -v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v16, v14
	v_fmac_f32_e32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v8, v14, v5
	v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v12, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v11
	v_add_f32_e32 v6, v9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v5, v5
	v_add_f32_e32 v7, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v6, v9 :: v_dual_sub_f32 v4, v7, v4
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, 0x3f317218, v5
	v_sub_f32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v3, v3, v8
	v_fma_f32 v9, 0x3f317218, v5, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v4
	v_dual_fmamk_f32 v5, v5, 0xb102e308, v9 :: v_dual_add_f32 v6, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v6, v7
	v_dual_sub_f32 v3, v3, v7 :: v_dual_add_f32 v4, v12, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v4, v12
	v_dual_sub_f32 v5, v5, v12 :: v_dual_add_f32 v8, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v5, v3
	v_sub_f32_e32 v9, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v8, v9
	v_sub_f32_e32 v6, v6, v9
	v_sub_f32_e32 v4, v4, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v6, v4
	v_sub_f32_e32 v6, v7, v5
	v_add_f32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v6
	v_sub_f32_e32 v3, v3, v6
	v_sub_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v8, v4
	v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v6, v9, v8
	v_cndmask_b32_e64 v5, 0x3eaaaaab, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v6
	v_add_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v9, v3
	v_dual_mul_f32 v7, v5, v4 :: v_dual_sub_f32 v6, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v5, v4, -v7
	v_sub_f32_e32 v3, v3, v6
	v_cmp_class_f32_e64 vcc_lo, v7, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v3
	v_add_f32_e32 v3, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v3, v7, vcc_lo
	v_sub_f32_e32 v3, v3, v7
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v3, v4, v3
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	v_sub_f32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_trunc_f32_e32 v6, v5
	v_dual_mul_f32 v12, 0x3fb8aa3b, v9 :: v_dual_add_f32 v3, v8, v3
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v14, 0x3fb8aa3b, v9, -v12
	v_rndne_f32_e32 v15, v12
	v_fmamk_f32 v14, v9, 0x32a5705f, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v12, v15
	v_cvt_i32_f32_e32 v7, v15
	v_add_f32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v12, v12
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v12, v7
	v_dual_mul_f32 v7, 0.5, v5 :: v_dual_cndmask_b32 v4, 0, v4
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v12, v7
	v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v6, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v12, v7
	v_fma_f32 v3, v4, v3, v4
	v_cmp_eq_f32_e64 s1, 0x7f800000, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v5, 1.0, v11, s0
	v_cndmask_b32_e64 v6, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v4, s1
	v_cmp_eq_f32_e64 s1, 0, v11
	s_mov_b32 s0, 0x42e80000
	v_bfi_b32 v3, 0x7fffffff, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, 0x7f800000, 0, s1
	v_cndmask_b32_e32 v5, 0x7fc00000, v3, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v4, 0x7fffffff, v4, v6
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_or_b32 vcc_lo, s1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v11, v11
	v_fmaak_f32 v3, s0, v3, 0xc1800000
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
.LBB0_17:
	s_or_b32 exec_lo, exec_lo, s2
	v_sub_f32_e32 v6, v10, v13
	v_add_co_u32 v4, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v8, 0x43fa0000, v6
	v_sub_f32_e32 v2, v13, v2
	v_add_co_u32 v6, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_mul_f32_e32 v2, 0x43480000, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_store_b32 v[4:5], v3, off
	global_store_b32 v[6:7], v8, off
	global_store_b32 v[0:1], v2, off
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 44
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_, .Lfunc_end0-_Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8744
; NumSgprs: 18
; NumVgprs: 44
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 44
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18rgbUtoLab3F_kerneliifPjPfS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18rgbUtoLab3F_kerneliifPjPfS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     44
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
