#define _CRT_SECURE_NO_WARNINGS
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <cstdint>
#include <cstdio>
#include <chrono>
#include <algorithm>
#include <cassert>
#include <iostream>

//const bool DEBUG = true;
//   
#define R1 64

//   
#define R2 2

#define INF INT32_MAX / 2

//   
int ceil(const int a, const int b);

//#define Q2 ceil(R1, R2)
#define Q2 (R1 / R2)

//       
#define S1 ((R2 * R2 > R1) ? R1 : R2 * R2)
#define T1 (R1 / S1)
#define T2 ((S1 < R1) ? R1 : Q2 * Q2)
#define S2 (R1 / T2)

#define INPUT_PATH "CUDA_FW/graph.txt"
#define OUTPUT_PATH "output.txt"
#define OUTPUT_TRUE_PATH "output_true.txt"
//n - vertices, m - edges
int n, m;

__global__ void kernelI(int * deviceGraph, int pitch, int n, int k);
__global__ void kernelSD(int* deviceGraph, int pitch, int n, int k);
__global__ void kernelDD(int* deviceGraph, int pitch, int n, int k);

cudaError_t cudaStatus = cudaSetDevice(0);

int* readGraph() {
	FILE* inputFile = fopen(INPUT_PATH, "r");
	fscanf(inputFile, "%d %d", &n, &m);
	int* graph;
	cudaStatus = cudaMallocHost(&graph, sizeof(int) * n * n);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "CudaMallocHost failed!");
	}

	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
			graph[i * n + j] = (i != j) ? INF : 0;
		}
	}

	for (int i = 0; i < m; ++i) {
		int u, v, d;
		fscanf(inputFile, "%d %d %d", &u, &v, &d);
		graph[u * n + v] = d;
	}

	fclose(inputFile);
	return graph;
}

void writeResult(int32_t * hostGraph) {
	FILE* outputFile = fopen("output.txt", "w");
	fprintf(outputFile, "%d\n", n);
	int k = 0;
	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
			fprintf(outputFile, "%d ", hostGraph[k]);
			++k;
		}
		fprintf(outputFile, "\n");
	}
	fclose(outputFile);
}

int ceil(const int a, const int b) {
	return (a + b - 1) / b;
}

bool check(int* graph) {
	FILE* file = fopen(OUTPUT_TRUE_PATH, "r");
	int n1;
	fscanf(file, "%d", &n1);
	for (int i = 0; i < n1; ++i) {
		for (int j = 0; j < n1; ++j) {
			int e;
			fscanf(file, "%d", &e);
			if (e != graph[i * n + j]) {
				fclose(file);
				return false;
			}
		}
	}
	fclose(file);
	return true;
}

__global__ void wakeGPU() {
	int i = threadIdx.x;
}

int main() {

	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?");
	}

	//host located graph
	int* hostGraph = readGraph();
	printf("Graph is loaded\n");

	const int Q1 = ceil(n, R1);
	if (Q1 * R1 != n) {
		printf("n should divide by R1\n");
		return 1;
	}

	int* deviceGraph = 0;
	size_t pitch;
	int pitchInt;
	cudaStatus = cudaMallocPitch((void**)& deviceGraph, &pitch, (size_t)(n * sizeof(int32_t)), (size_t)n);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "CudaMallocPitch failed!");
	}
	cudaStatus = cudaMemcpy2D(deviceGraph, pitch, hostGraph, n * sizeof(int32_t), n * sizeof(int32_t), n, cudaMemcpyHostToDevice);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy2D failed!");
	}
	assert(!(pitch % sizeof(int)));
	pitchInt = pitch / sizeof(int);

	dim3 gridI(1);
	dim3 blockI(Q2, Q2);

	dim3 gridSD(Q1 - 1, 2);
	dim3 blockSD(Q2, Q2);

	dim3 gridDD(Q1 - 1, Q1 - 1);
	dim3 blockDD(Q2, Q2);

	cudaEvent_t stepFinishedEvent;
	cudaEventCreate(&stepFinishedEvent);

	wakeGPU<<<1, 1>>>();

	auto start = std::chrono::high_resolution_clock::now();
	for (int k = 0; k < Q1; ++k) {
		kernelI<<<gridI, blockI>>>(deviceGraph, pitchInt, n, k);
		cudaEventRecord(stepFinishedEvent);
		cudaEventSynchronize(stepFinishedEvent);
		kernelSD<<<gridSD, blockSD>>>(deviceGraph, pitchInt, n, k);
		cudaEventRecord(stepFinishedEvent);
		cudaEventSynchronize(stepFinishedEvent);
		kernelDD<<<gridDD, blockDD>>>(deviceGraph, pitchInt, n, k);
		cudaEventRecord(stepFinishedEvent);
		cudaEventSynchronize(stepFinishedEvent);
	}
	auto end = std::chrono::high_resolution_clock::now();
	std::chrono::duration<double> diff = end - start;
	std::cout << diff.count() * 1000 << "(ms)\n";
	
	cudaStatus = cudaMemcpy2D(hostGraph, n * sizeof(int32_t), deviceGraph, pitch, n * sizeof(int32_t), n, cudaMemcpyHostToDevice);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy2D failed!");
	}
	printf(check(hostGraph) ? "Result is correct\n" : "Result is not correct\n");
	writeResult(hostGraph);
	cudaFree(deviceGraph);
	return 0;
}

//  
__global__ void kernelI(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int base = kBlock * R1;
	//const int globalI = base + localI;
	//const int globalJ = base + localJ;
	__shared__ int localBlock[R1][R1];

	const int threadID = threadIdx.y * Q2 + threadIdx.x;
	const int offsetI = threadID / R1;
	const int offsetJ = threadID % R1;

	int i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			localBlock[i][j] = deviceGraph[(base + i) * pitch + (base + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();
//#pragma unroll
	for (int k = 0; k < R1; ++k) {
//#pragma unroll
		for (int i = 0; i < R2; ++i) {
//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
					localBlock[localI + i][k] + localBlock[k][localJ + j]);
			}
		}
		__syncthreads();
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			deviceGraph[(base + i) * pitch + (base + j)] = localBlock[i][j];
			j += T2;
		}
		i += T1;
	}
}

__global__ void kernelSD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	int baseI, baseJ;
	if (blockIdx.y == 0) {
		baseI = baseLead;
		baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	else {
		baseJ = baseLead;
		baseI = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	//const int globalI = baseI + localI;
	//const int globalJ = baseJ + localJ;
	__shared__ int localBlock[R1][R1];
	__shared__ int leadBlock[R1][R1];

	const int threadID = threadIdx.y * Q2 + threadIdx.x;
	const int offsetI = threadID / R1;
	const int offsetJ = threadID % R1;

	int i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			localBlock[i][j] = deviceGraph[(baseI + i) * pitch + (baseJ + j)];
			j += T2;
		}
		i += T1;
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadBlock[i][j] = deviceGraph[(baseLead + i) * pitch + (baseLead + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();

	if (blockIdx.y == 0) {
//#pragma unroll
		for (int k = 0; k < R1; ++k) {
//#pragma unroll
			for (int i = 0; i < R2; ++i) {
//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						leadBlock[localI + i][k] + localBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}
	else {
//#pragma unroll
		for (int k = 0; k < R1; ++k) {
//#pragma unroll
			for (int i = 0; i < R2; ++i) {
//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						localBlock[localI + i][k] + leadBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			deviceGraph[(baseI + i) * pitch + (baseJ + j)] = localBlock[i][j];
			j += T2;
		}
		i += T1;
	}
}

__global__ void kernelDD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	const int baseI = (blockIdx.y + (blockIdx.y >= kBlock)) * R1;
	const int baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	//const int globalI = baseI + localI;
	//const int globalJ = baseJ + localJ;
	__shared__ int leadRowBlock[R1][R1];
	__shared__ int leadColumnBlock[R1][R1];
	int c[R2][R2];

	const int threadID = threadIdx.y * Q2 + threadIdx.x;
	const int offsetI = threadID / R1;
	const int offsetJ = threadID % R1;

	int i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadRowBlock[i][j] = deviceGraph[(baseI + i) * pitch + (baseJ + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();

//#pragma unroll
	for (int i = 0; i < R2; ++i) {
//#pragma unroll
		for (int j = 0; j < R2; ++j) {
			c[i][j] = leadRowBlock[localI + i][localJ + j];
		}
	}
	__syncthreads();
			
	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadRowBlock[i][j] = deviceGraph[(baseLead + i) * pitch + (baseJ + j)];
			j += T2;
		}
		i += T1;
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadColumnBlock[i][j] = deviceGraph[(baseI + i) * pitch + (baseLead + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();


//#pragma unroll
	for (int k = 0; k < R1; ++k) {
//#pragma unroll
		for (int i = 0; i < R2; ++i) {
//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				c[i][j] = min(c[i][j], leadColumnBlock[localI + i][k] + leadRowBlock[k][localJ + j]);
			}
		}
	}
	__syncthreads();

/*
#pragma unroll
	for (int i2 = 0, i1 = localI; i2 < R2; ++i1, ++i2) {
#pragma unroll
		for (int j2 = 0, j1 = localJ; j2 < R2; ++j1, ++j2) {
			int ind = (globalI + i2) * pitch + (globalJ + j2);
			int c0 = deviceGraph[ind];
#pragma unroll
			for (int k = 0; k < R1; ++k) {
				c0 = min(c0, leadColumnBlock[i1][k] + leadRowBlock[k][j1]);
			}
			deviceGraph[ind] = c0;
		}
	}*/


#pragma unroll
	for (int i = 0; i < R2; ++i) {
#pragma unroll
		for (int j = 0; j < R2; ++j) {
			leadRowBlock[localI + i][localJ + j] = c[i][j];
		}
	}
	__syncthreads();

	i = offsetI;
#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ; 
#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			deviceGraph[(baseI + i) * pitch + (baseJ + j)] = leadRowBlock[i][j];
			j += T2;
		}
		i += T1;
	}
}

//  
/*__global__ void kernelI(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y;
	const int localJ = threadIdx.x;
	const int base = kBlock * R1;
	const int globalI = base + localI;
	const int globalJ = base + localJ;
	__shared__ int localBlock[R1][R1];

	localBlock[localI][localJ] = deviceGraph[globalI * pitch + globalJ];
	__syncthreads();

#pragma unroll
	for (int k = 0; k < R1; ++k) {
		localBlock[localI][localJ] = min(localBlock[localI][localJ],
					localBlock[localI][k] + localBlock[k][localJ]);
		__syncthreads();
	}

	deviceGraph[globalI * pitch + globalJ] = localBlock[localI][localJ];
}

__global__ void kernelSD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y;
	const int localJ = threadIdx.x;
	const int baseLead = kBlock * R1;
	int baseI, baseJ;
	if (blockIdx.y == 0) {
		baseI = baseLead;
		baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	else {
		baseJ = baseLead;
		baseI = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	__shared__ int localBlock[R1][R1];
	__shared__ int leadBlock[R1][R1];

	localBlock[localI][localJ] = deviceGraph[globalI * pitch + globalJ];
	leadBlock[localI][localJ] = deviceGraph[(baseLead + localI) * pitch + (baseLead + localJ)];
	__syncthreads();

	if (blockIdx.y == 0) {
#pragma unroll
		for (int k = 0; k < R1; ++k) {
			localBlock[localI][localJ] = min(localBlock[localI][localJ],
				leadBlock[localI][k] + localBlock[k][localJ]);
			__syncthreads();
		}
	}
	else {
#pragma unroll
		for (int k = 0; k < R1; ++k) {
			localBlock[localI][localJ] = min(localBlock[localI][localJ],
				localBlock[localI][k] + leadBlock[k][localJ]);
			__syncthreads();
		}
	}

	deviceGraph[globalI * pitch + globalJ] = localBlock[localI][localJ];
}

__global__ void kernelDD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y;
	const int localJ = threadIdx.x;
	const int baseLead = kBlock * R1;
	const int baseI = (blockIdx.y + (blockIdx.y >= kBlock)) * R1;
	const int baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	__shared__ int leadRowBlock[R1][R1];
	__shared__ int leadColumnBlock[R1][R1];

	int c = deviceGraph[globalI * pitch + globalJ];
	leadColumnBlock[localI][localJ] = deviceGraph[(baseI + localI) * pitch + (baseLead + localJ)];
	leadRowBlock[localI][localJ] = deviceGraph[(baseLead + localI) * pitch + (baseJ + localJ)];

	__syncthreads();

#pragma unroll
	for (int k = 0; k < R1; ++k) {
		c = min(c, leadColumnBlock[localI][k] + leadRowBlock[k][localJ]);
	}
	__syncthreads();

	deviceGraph[globalI * pitch + globalJ] = c;
}*/

//        
/*__global__ void kernelI(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int base = kBlock * R1;
	const int globalI = base + localI;
	const int globalJ = base + localJ;
	__shared__ int localBlock[R1][R1];

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			localBlock[localI + i][localJ + j] = deviceGraph[(globalI + i) * pitch + (globalJ + j)];
		}
	}

	__syncthreads();
	//#pragma unroll
	for (int k = 0; k < R1; ++k) {
		//#pragma unroll
		for (int i = 0; i < R2; ++i) {
			//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
					localBlock[localI + i][k] + localBlock[k][localJ + j]);
			}
		}
		__syncthreads();
	}

	//#pragma unroll
	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			deviceGraph[(globalI + i) * pitch + (globalJ + j)] = localBlock[localI + i][localJ + j];
		}
	}
}

__global__ void kernelSD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	int baseI, baseJ;
	if (blockIdx.y == 0) {
		baseI = baseLead;
		baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	else {
		baseJ = baseLead;
		baseI = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	const int leadGlobalI = baseLead + localI;
	const int leadGlobalJ = baseLead + localJ;
	__shared__ int localBlock[R1][R1];
	__shared__ int leadBlock[R1][R1];

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			localBlock[localI + i][localJ + j] = deviceGraph[(globalI + i) * pitch + (globalJ + j)];
		}
	}

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			leadBlock[localI + i][localJ + j] = deviceGraph[(leadGlobalI + i) * pitch + (leadGlobalJ + j)];
		}
	}

	__syncthreads();

	if (blockIdx.y == 0) {
		//#pragma unroll
		for (int k = 0; k < R1; ++k) {
			//#pragma unroll
			for (int i = 0; i < R2; ++i) {
				//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						leadBlock[localI + i][k] + localBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}
	else {
		//#pragma unroll
		for (int k = 0; k < R1; ++k) {
			//#pragma unroll
			for (int i = 0; i < R2; ++i) {
				//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						localBlock[localI + i][k] + leadBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			deviceGraph[(globalI + i) * pitch + (globalJ + j)] = localBlock[localI + i][localJ + j];
		}
	}
}

__global__ void kernelDD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	const int baseI = (blockIdx.y + (blockIdx.y >= kBlock)) * R1;
	const int baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	const int leadGlobalI = baseLead + localI;
	const int leadGlobalJ = baseLead + localJ;
	__shared__ int leadRowBlock[R1][R1];
	__shared__ int leadColumnBlock[R1][R1];
	int c[R2][R2];

	//#pragma unroll
	for (int i = 0; i < R2; ++i) {
		//#pragma unroll
		for (int j = 0; j < R2; ++j) {
			c[i][j] = deviceGraph[(globalI + i) * pitch + (globalJ + j)];
		}
	}

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			leadRowBlock[localI + i][localJ + j] = deviceGraph[(leadGlobalI + i) * pitch + (globalJ + j)];
		}
	}
	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			leadColumnBlock[localI + i][localJ + j] = deviceGraph[(globalI + i) * pitch + (leadGlobalJ + j)];
		}
	}

	__syncthreads();

	//#pragma unroll
	for (int k = 0; k < R1; ++k) {
		//#pragma unroll
		for (int i = 0; i < R2; ++i) {
			//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				c[i][j] = min(c[i][j], leadColumnBlock[localI + i][k] + leadRowBlock[k][localJ + j]);
			}
		}
	}
	__syncthreads();

	//#pragma unroll
	for (int i = 0; i < R2; ++i) {
		//#pragma unroll
		for (int j = 0; j < R2; ++j) {
			deviceGraph[(globalI + i) * pitch + (globalJ + j)] = c[i][j];
		}
	}
}*/	

	.file	"tmpxft_0021f794_00000000-6_FW.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3999:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3999:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"CUDA_FW/graph.txt"
.LC2:
	.string	"%d %d"
.LC3:
	.string	"CudaMallocHost failed!"
.LC4:
	.string	"%d %d %d"
	.text
	.globl	_Z9readGraphv
	.type	_Z9readGraphv, @function
_Z9readGraphv:
.LFB3988:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rsi
	leaq	.LC1(%rip), %rdi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	leaq	m(%rip), %rcx
	leaq	n(%rip), %rdx
	movq	%rax, %rdi
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movslq	n(%rip), %rsi
	leaq	16(%rsp), %rdi
	xorl	%edx, %edx
	imulq	%rsi, %rsi
	salq	$2, %rsi
	call	cudaHostAlloc@PLT
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	je	.L3
	movq	stderr(%rip), %rdi
	leaq	.LC3(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L3:
	movq	16(%rsp), %rsi
	xorl	%edx, %edx
	xorl	%edi, %edi
	movl	$1073741823, %r8d
.L4:
	cmpl	%edx, n(%rip)
	jle	.L18
	xorl	%ecx, %ecx
.L7:
	movl	n(%rip), %eax
	cmpl	%ecx, %eax
	jle	.L19
	cmpl	%ecx, %edx
	movl	%r8d, %r9d
	cmove	%edi, %r9d
	imull	%edx, %eax
	addl	%ecx, %eax
	incl	%ecx
	cltq
	movl	%r9d, (%rsi,%rax,4)
	jmp	.L7
.L19:
	incl	%edx
	jmp	.L4
.L18:
	xorl	%r12d, %r12d
	leaq	.LC4(%rip), %rbp
.L8:
	cmpl	%r12d, m(%rip)
	jle	.L20
	leaq	8(%rsp), %rcx
	leaq	4(%rsp), %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	leaq	12(%rsp), %r8
	xorl	%eax, %eax
	incl	%r12d
	call	__isoc23_fscanf@PLT
	movl	4(%rsp), %eax
	movl	12(%rsp), %ecx
	imull	n(%rip), %eax
	movq	16(%rsp), %rdx
	addl	8(%rsp), %eax
	cltq
	movl	%ecx, (%rdx,%rax,4)
	jmp	.L8
.L20:
	movq	%rbx, %rdi
	call	fclose@PLT
	movq	16(%rsp), %rax
	movq	24(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3988:
	.size	_Z9readGraphv, .-_Z9readGraphv
	.section	.rodata.str1.1
.LC5:
	.string	"w"
.LC6:
	.string	"output.txt"
.LC7:
	.string	"%d\n"
.LC8:
	.string	"%d "
.LC9:
	.string	"\n"
	.text
	.globl	_Z11writeResultPi
	.type	_Z11writeResultPi, @function
_Z11writeResultPi:
.LFB3989:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC5(%rip), %rsi
	leaq	.LC8(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	leaq	.LC6(%rip), %rdi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	pushq	%rdx
	.cfi_def_cfa_offset 64
	call	fopen@PLT
	movl	n(%rip), %ecx
	movl	$2, %esi
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L22:
	cmpl	%r13d, n(%rip)
	jle	.L24
	movslq	%r12d, %rbp
.L25:
	movl	%ebp, %eax
	subl	%r12d, %eax
	cmpl	%eax, n(%rip)
	jle	.L27
	movl	(%r14,%rbp,4), %ecx
	movq	%r15, %rdx
	movl	$2, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	incq	%rbp
	call	__fprintf_chk@PLT
	jmp	.L25
.L27:
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%eax, %eax
	movl	%ebp, %r12d
	movl	$2, %esi
	incl	%r13d
	call	__fprintf_chk@PLT
	jmp	.L22
.L24:
	popq	%rax
	.cfi_def_cfa_offset 56
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE3989:
	.size	_Z11writeResultPi, .-_Z11writeResultPi
	.globl	_Z4ceilii
	.type	_Z4ceilii, @function
_Z4ceilii:
.LFB3990:
	.cfi_startproc
	endbr64
	leal	-1(%rsi,%rdi), %eax
	cltd
	idivl	%esi
	ret
	.cfi_endproc
.LFE3990:
	.size	_Z4ceilii, .-_Z4ceilii
	.section	.rodata.str1.1
.LC10:
	.string	"output_true.txt"
.LC11:
	.string	"%d"
	.text
	.globl	_Z5checkPi
	.type	_Z5checkPi, @function
_Z5checkPi:
.LFB3991:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leaq	.LC11(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	leaq	.LC10(%rip), %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %r13
	call	fopen@PLT
	movq	%rsp, %rdx
	movq	%r12, %rsi
	movq	%rax, %rdi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
.L30:
	cmpl	%r14d, (%rsp)
	jle	.L38
	xorl	%r15d, %r15d
.L34:
	cmpl	%r15d, (%rsp)
	jle	.L39
	movq	%r13, %rdx
	movq	%r12, %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	n(%rip), %eax
	movl	4(%rsp), %ecx
	imull	%r14d, %eax
	addl	%r15d, %eax
	cltq
	cmpl	%ecx, 0(%rbp,%rax,4)
	je	.L31
	movq	%rbx, %rdi
	call	fclose@PLT
	xorl	%eax, %eax
	jmp	.L29
.L31:
	incl	%r15d
	jmp	.L34
.L39:
	incl	%r14d
	jmp	.L30
.L38:
	movq	%rbx, %rdi
	call	fclose@PLT
	movb	$1, %al
.L29:
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3991:
	.size	_Z5checkPi, .-_Z5checkPi
	.globl	_Z25__device_stub__Z7wakeGPUvv
	.type	_Z25__device_stub__Z7wakeGPUvv, @function
_Z25__device_stub__Z7wakeGPUvv:
.LFB4021:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z7wakeGPUv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L40:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4021:
	.size	_Z25__device_stub__Z7wakeGPUvv, .-_Z25__device_stub__Z7wakeGPUvv
	.globl	_Z7wakeGPUv
	.type	_Z7wakeGPUv, @function
_Z7wakeGPUv:
.LFB4022:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z7wakeGPUvv
	.cfi_endproc
.LFE4022:
	.size	_Z7wakeGPUv, .-_Z7wakeGPUv
	.globl	_Z29__device_stub__Z7kernelIPiiiiPiiii
	.type	_Z29__device_stub__Z7kernelIPiiiiPiiii, @function
_Z29__device_stub__Z7kernelIPiiiiPiiii:
.LFB4023:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%esi, 12(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	32(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7kernelIPiiii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L45:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4023:
	.size	_Z29__device_stub__Z7kernelIPiiiiPiiii, .-_Z29__device_stub__Z7kernelIPiiiiPiiii
	.globl	_Z7kernelIPiiii
	.type	_Z7kernelIPiiii, @function
_Z7kernelIPiiii:
.LFB4024:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7kernelIPiiiiPiiii
	.cfi_endproc
.LFE4024:
	.size	_Z7kernelIPiiii, .-_Z7kernelIPiiii
	.globl	_Z30__device_stub__Z8kernelSDPiiiiPiiii
	.type	_Z30__device_stub__Z8kernelSDPiiiiPiiii, @function
_Z30__device_stub__Z8kernelSDPiiiiPiiii:
.LFB4025:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%esi, 12(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	32(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8kernelSDPiiii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L50:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4025:
	.size	_Z30__device_stub__Z8kernelSDPiiiiPiiii, .-_Z30__device_stub__Z8kernelSDPiiiiPiiii
	.globl	_Z8kernelSDPiiii
	.type	_Z8kernelSDPiiii, @function
_Z8kernelSDPiiii:
.LFB4026:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z8kernelSDPiiiiPiiii
	.cfi_endproc
.LFE4026:
	.size	_Z8kernelSDPiiii, .-_Z8kernelSDPiiii
	.globl	_Z30__device_stub__Z8kernelDDPiiiiPiiii
	.type	_Z30__device_stub__Z8kernelDDPiiiiPiiii, @function
_Z30__device_stub__Z8kernelDDPiiiiPiiii:
.LFB4027:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%esi, 12(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	32(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8kernelDDPiiii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L55:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4027:
	.size	_Z30__device_stub__Z8kernelDDPiiiiPiiii, .-_Z30__device_stub__Z8kernelDDPiiiiPiiii
	.globl	_Z8kernelDDPiiii
	.type	_Z8kernelDDPiiii, @function
_Z8kernelDDPiiii:
.LFB4028:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z8kernelDDPiiiiPiiii
	.cfi_endproc
.LFE4028:
	.size	_Z8kernelDDPiiii, .-_Z8kernelDDPiiii
	.section	.rodata.str1.1
.LC12:
	.string	"Result is correct\n"
.LC13:
	.string	"Result is not correct\n"
.LC14:
	.string	"cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?"
.LC15:
	.string	"Graph is loaded\n"
.LC16:
	.string	"n should divide by R1\n"
.LC17:
	.string	"CudaMallocPitch failed!"
.LC18:
	.string	"cudaMemcpy2D failed!"
.LC21:
	.string	"(ms)\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3992:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	addq	$-128, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	cmpl	$0, cudaStatus(%rip)
	je	.L61
	movq	stderr(%rip), %rdi
	leaq	.LC14(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
.L61:
	call	_Z9readGraphv
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rbp
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	n(%rip), %rcx
	movl	$64, %esi
	leal	63(%rcx), %eax
	cltd
	idivl	%esi
	movl	%eax, %r12d
	sall	$6, %eax
	cmpl	%eax, %ecx
	je	.L62
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L60
.L62:
	xorl	%r9d, %r9d
	leaq	0(,%rcx,4), %rdx
	leaq	8(%rsp), %rsi
	movq	%rsp, %rdi
	movq	%r9, (%rsp)
	call	cudaMallocPitch@PLT
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	je	.L64
	movq	stderr(%rip), %rdi
	leaq	.LC17(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L64:
	movslq	n(%rip), %r9
	pushq	%rsi
	.cfi_def_cfa_offset 184
	movq	%rbp, %rdx
	pushq	$1
	.cfi_def_cfa_offset 192
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	leaq	0(,%r9,4), %rcx
	movq	%rcx, %r8
	call	cudaMemcpy2D@PLT
	popq	%rdi
	.cfi_def_cfa_offset 184
	popq	%r8
	.cfi_def_cfa_offset 176
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	je	.L65
	movq	stderr(%rip), %rdi
	leaq	.LC18(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L65:
	movl	$2147483649, %ecx
	leal	-1(%r12), %edx
	movabsq	$137438953504, %rax
	movabsq	$4294967297, %r13
	addq	%rcx, %rcx
	movq	8(%rsp), %rbx
	leaq	16(%rsp), %rdi
	movl	%edx, 48(%rsp)
	movq	%rcx, 52(%rsp)
	movl	%edx, 72(%rsp)
	shrq	$2, %rbx
	movl	%edx, 76(%rsp)
	movq	%r13, 24(%rsp)
	movl	$1, 32(%rsp)
	movq	%rax, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	cudaEventCreate@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	call	_Z25__device_stub__Z7wakeGPUvv
.L66:
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	xorl	%r13d, %r13d
	movq	%rax, %r14
.L67:
	cmpl	%r12d, %r13d
	jge	.L86
	movl	44(%rsp), %ecx
	movq	36(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	movl	n(%rip), %edx
	movq	(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%ebx, %esi
	call	_Z29__device_stub__Z7kernelIPiiiiPiiii
.L68:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	68(%rsp), %ecx
	movl	56(%rsp), %esi
	xorl	%r9d, %r9d
	movq	60(%rsp), %rdx
	movq	48(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	movl	n(%rip), %edx
	movq	(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%ebx, %esi
	call	_Z30__device_stub__Z8kernelSDPiiiiPiiii
.L69:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	92(%rsp), %ecx
	movl	80(%rsp), %esi
	xorl	%r9d, %r9d
	movq	84(%rsp), %rdx
	movq	72(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movl	n(%rip), %edx
	movq	(%rsp), %rdi
	movl	%r13d, %ecx
	movl	%ebx, %esi
	call	_Z30__device_stub__Z8kernelDDPiiiiPiiii
.L70:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	incl	%r13d
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	jmp	.L67
.L86:
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	leaq	_ZSt4cout(%rip), %rdi
	subq	%r14, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC19(%rip), %xmm0
	mulsd	.LC20(%rip), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$5, %edx
	leaq	.LC21(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	movslq	n(%rip), %r9
	movq	%rbp, %rdi
	pushq	%rax
	.cfi_def_cfa_offset 184
	pushq	$1
	.cfi_def_cfa_offset 192
	leaq	0(,%r9,4), %rsi
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	%rsi, %r8
	call	cudaMemcpy2D@PLT
	popq	%rdx
	.cfi_def_cfa_offset 184
	popq	%rcx
	.cfi_def_cfa_offset 176
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	je	.L72
	movq	stderr(%rip), %rdi
	leaq	.LC18(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L72:
	movq	%rbp, %rdi
	call	_Z5checkPi
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	testb	%al, %al
	leaq	.LC12(%rip), %rax
	cmovne	%rax, %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	_Z11writeResultPi
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L60:
	movq	120(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L74
	call	__stack_chk_fail@PLT
.L74:
	subq	$-128, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3992:
	.size	main, .-main
	.section	.rodata.str1.1
.LC22:
	.string	"_Z8kernelDDPiiii"
.LC23:
	.string	"_Z8kernelSDPiiii"
.LC24:
	.string	"_Z7kernelIPiiii"
.LC25:
	.string	"_Z7wakeGPUv"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4030:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8kernelDDPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8kernelSDPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7kernelIPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7wakeGPUv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4030:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text.startup
	.type	_GLOBAL__sub_I_n, @function
_GLOBAL__sub_I_n:
.LFB4708:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	movl	%eax, cudaStatus(%rip)
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4708:
	.size	_GLOBAL__sub_I_n, .-_GLOBAL__sub_I_n
	.section	.init_array
	.align 8
	.quad	_GLOBAL__sub_I_n
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	cudaStatus
	.bss
	.align 4
	.type	cudaStatus, @object
	.size	cudaStatus, 4
cudaStatus:
	.zero	4
	.globl	m
	.align 4
	.type	m, @object
	.size	m, 4
m:
	.zero	4
	.globl	n
	.align 4
	.type	n, @object
	.size	n, 4
n:
	.zero	4
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC19:
	.long	0
	.long	1104006501
	.align 8
.LC20:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#define _CRT_SECURE_NO_WARNINGS
#include "hip/hip_runtime.h"


#include <cstdint>
#include <cstdio>
#include <chrono>
#include <algorithm>
#include <cassert>
#include <iostream>

//const bool DEBUG = true;
//   
#define R1 64

//   
#define R2 2

#define INF INT32_MAX / 2

//   
int ceil(const int a, const int b);

//#define Q2 ceil(R1, R2)
#define Q2 (R1 / R2)

//       
#define S1 ((R2 * R2 > R1) ? R1 : R2 * R2)
#define T1 (R1 / S1)
#define T2 ((S1 < R1) ? R1 : Q2 * Q2)
#define S2 (R1 / T2)

#define INPUT_PATH "CUDA_FW/graph.txt"
#define OUTPUT_PATH "output.txt"
#define OUTPUT_TRUE_PATH "output_true.txt"
//n - vertices, m - edges
int n, m;

__global__ void kernelI(int * deviceGraph, int pitch, int n, int k);
__global__ void kernelSD(int* deviceGraph, int pitch, int n, int k);
__global__ void kernelDD(int* deviceGraph, int pitch, int n, int k);

hipError_t cudaStatus = hipSetDevice(0);

int* readGraph() {
	FILE* inputFile = fopen(INPUT_PATH, "r");
	fscanf(inputFile, "%d %d", &n, &m);
	int* graph;
	cudaStatus = hipHostMalloc(&graph, sizeof(int) * n * n, hipHostMallocDefault);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "CudaMallocHost failed!");
	}

	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
			graph[i * n + j] = (i != j) ? INF : 0;
		}
	}

	for (int i = 0; i < m; ++i) {
		int u, v, d;
		fscanf(inputFile, "%d %d %d", &u, &v, &d);
		graph[u * n + v] = d;
	}

	fclose(inputFile);
	return graph;
}

void writeResult(int32_t * hostGraph) {
	FILE* outputFile = fopen("output.txt", "w");
	fprintf(outputFile, "%d\n", n);
	int k = 0;
	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
			fprintf(outputFile, "%d ", hostGraph[k]);
			++k;
		}
		fprintf(outputFile, "\n");
	}
	fclose(outputFile);
}

int ceil(const int a, const int b) {
	return (a + b - 1) / b;
}

bool check(int* graph) {
	FILE* file = fopen(OUTPUT_TRUE_PATH, "r");
	int n1;
	fscanf(file, "%d", &n1);
	for (int i = 0; i < n1; ++i) {
		for (int j = 0; j < n1; ++j) {
			int e;
			fscanf(file, "%d", &e);
			if (e != graph[i * n + j]) {
				fclose(file);
				return false;
			}
		}
	}
	fclose(file);
	return true;
}

__global__ void wakeGPU() {
	int i = threadIdx.x;
}

int main() {

	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipSetDevice failed!  Do you have a CUDA-capable GPU installed?");
	}

	//host located graph
	int* hostGraph = readGraph();
	printf("Graph is loaded\n");

	const int Q1 = ceil(n, R1);
	if (Q1 * R1 != n) {
		printf("n should divide by R1\n");
		return 1;
	}

	int* deviceGraph = 0;
	size_t pitch;
	int pitchInt;
	cudaStatus = hipMallocPitch((void**)& deviceGraph, &pitch, (size_t)(n * sizeof(int32_t)), (size_t)n);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "CudaMallocPitch failed!");
	}
	cudaStatus = hipMemcpy2D(deviceGraph, pitch, hostGraph, n * sizeof(int32_t), n * sizeof(int32_t), n, hipMemcpyHostToDevice);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy2D failed!");
	}
	assert(!(pitch % sizeof(int)));
	pitchInt = pitch / sizeof(int);

	dim3 gridI(1);
	dim3 blockI(Q2, Q2);

	dim3 gridSD(Q1 - 1, 2);
	dim3 blockSD(Q2, Q2);

	dim3 gridDD(Q1 - 1, Q1 - 1);
	dim3 blockDD(Q2, Q2);

	hipEvent_t stepFinishedEvent;
	hipEventCreate(&stepFinishedEvent);

	wakeGPU<<<1, 1>>>();

	auto start = std::chrono::high_resolution_clock::now();
	for (int k = 0; k < Q1; ++k) {
		kernelI<<<gridI, blockI>>>(deviceGraph, pitchInt, n, k);
		hipEventRecord(stepFinishedEvent);
		hipEventSynchronize(stepFinishedEvent);
		kernelSD<<<gridSD, blockSD>>>(deviceGraph, pitchInt, n, k);
		hipEventRecord(stepFinishedEvent);
		hipEventSynchronize(stepFinishedEvent);
		kernelDD<<<gridDD, blockDD>>>(deviceGraph, pitchInt, n, k);
		hipEventRecord(stepFinishedEvent);
		hipEventSynchronize(stepFinishedEvent);
	}
	auto end = std::chrono::high_resolution_clock::now();
	std::chrono::duration<double> diff = end - start;
	std::cout << diff.count() * 1000 << "(ms)\n";
	
	cudaStatus = hipMemcpy2D(hostGraph, n * sizeof(int32_t), deviceGraph, pitch, n * sizeof(int32_t), n, hipMemcpyHostToDevice);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy2D failed!");
	}
	printf(check(hostGraph) ? "Result is correct\n" : "Result is not correct\n");
	writeResult(hostGraph);
	hipFree(deviceGraph);
	return 0;
}

//  
__global__ void kernelI(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int base = kBlock * R1;
	//const int globalI = base + localI;
	//const int globalJ = base + localJ;
	__shared__ int localBlock[R1][R1];

	const int threadID = threadIdx.y * Q2 + threadIdx.x;
	const int offsetI = threadID / R1;
	const int offsetJ = threadID % R1;

	int i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			localBlock[i][j] = deviceGraph[(base + i) * pitch + (base + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();
//#pragma unroll
	for (int k = 0; k < R1; ++k) {
//#pragma unroll
		for (int i = 0; i < R2; ++i) {
//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
					localBlock[localI + i][k] + localBlock[k][localJ + j]);
			}
		}
		__syncthreads();
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			deviceGraph[(base + i) * pitch + (base + j)] = localBlock[i][j];
			j += T2;
		}
		i += T1;
	}
}

__global__ void kernelSD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	int baseI, baseJ;
	if (blockIdx.y == 0) {
		baseI = baseLead;
		baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	else {
		baseJ = baseLead;
		baseI = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	//const int globalI = baseI + localI;
	//const int globalJ = baseJ + localJ;
	__shared__ int localBlock[R1][R1];
	__shared__ int leadBlock[R1][R1];

	const int threadID = threadIdx.y * Q2 + threadIdx.x;
	const int offsetI = threadID / R1;
	const int offsetJ = threadID % R1;

	int i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			localBlock[i][j] = deviceGraph[(baseI + i) * pitch + (baseJ + j)];
			j += T2;
		}
		i += T1;
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadBlock[i][j] = deviceGraph[(baseLead + i) * pitch + (baseLead + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();

	if (blockIdx.y == 0) {
//#pragma unroll
		for (int k = 0; k < R1; ++k) {
//#pragma unroll
			for (int i = 0; i < R2; ++i) {
//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						leadBlock[localI + i][k] + localBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}
	else {
//#pragma unroll
		for (int k = 0; k < R1; ++k) {
//#pragma unroll
			for (int i = 0; i < R2; ++i) {
//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						localBlock[localI + i][k] + leadBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			deviceGraph[(baseI + i) * pitch + (baseJ + j)] = localBlock[i][j];
			j += T2;
		}
		i += T1;
	}
}

__global__ void kernelDD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	const int baseI = (blockIdx.y + (blockIdx.y >= kBlock)) * R1;
	const int baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	//const int globalI = baseI + localI;
	//const int globalJ = baseJ + localJ;
	__shared__ int leadRowBlock[R1][R1];
	__shared__ int leadColumnBlock[R1][R1];
	int c[R2][R2];

	const int threadID = threadIdx.y * Q2 + threadIdx.x;
	const int offsetI = threadID / R1;
	const int offsetJ = threadID % R1;

	int i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadRowBlock[i][j] = deviceGraph[(baseI + i) * pitch + (baseJ + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();

//#pragma unroll
	for (int i = 0; i < R2; ++i) {
//#pragma unroll
		for (int j = 0; j < R2; ++j) {
			c[i][j] = leadRowBlock[localI + i][localJ + j];
		}
	}
	__syncthreads();
			
	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadRowBlock[i][j] = deviceGraph[(baseLead + i) * pitch + (baseJ + j)];
			j += T2;
		}
		i += T1;
	}

	i = offsetI;
//#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ;
//#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			leadColumnBlock[i][j] = deviceGraph[(baseI + i) * pitch + (baseLead + j)];
			j += T2;
		}
		i += T1;
	}
	__syncthreads();


//#pragma unroll
	for (int k = 0; k < R1; ++k) {
//#pragma unroll
		for (int i = 0; i < R2; ++i) {
//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				c[i][j] = min(c[i][j], leadColumnBlock[localI + i][k] + leadRowBlock[k][localJ + j]);
			}
		}
	}
	__syncthreads();

/*
#pragma unroll
	for (int i2 = 0, i1 = localI; i2 < R2; ++i1, ++i2) {
#pragma unroll
		for (int j2 = 0, j1 = localJ; j2 < R2; ++j1, ++j2) {
			int ind = (globalI + i2) * pitch + (globalJ + j2);
			int c0 = deviceGraph[ind];
#pragma unroll
			for (int k = 0; k < R1; ++k) {
				c0 = min(c0, leadColumnBlock[i1][k] + leadRowBlock[k][j1]);
			}
			deviceGraph[ind] = c0;
		}
	}*/


#pragma unroll
	for (int i = 0; i < R2; ++i) {
#pragma unroll
		for (int j = 0; j < R2; ++j) {
			leadRowBlock[localI + i][localJ + j] = c[i][j];
		}
	}
	__syncthreads();

	i = offsetI;
#pragma unroll
	for (int i1 = 0; i1 < S1; ++i1) {
		int j = offsetJ; 
#pragma unroll
		for (int i2 = 0; i2 < S2; ++i2) {
			deviceGraph[(baseI + i) * pitch + (baseJ + j)] = leadRowBlock[i][j];
			j += T2;
		}
		i += T1;
	}
}

//  
/*__global__ void kernelI(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y;
	const int localJ = threadIdx.x;
	const int base = kBlock * R1;
	const int globalI = base + localI;
	const int globalJ = base + localJ;
	__shared__ int localBlock[R1][R1];

	localBlock[localI][localJ] = deviceGraph[globalI * pitch + globalJ];
	__syncthreads();

#pragma unroll
	for (int k = 0; k < R1; ++k) {
		localBlock[localI][localJ] = min(localBlock[localI][localJ],
					localBlock[localI][k] + localBlock[k][localJ]);
		__syncthreads();
	}

	deviceGraph[globalI * pitch + globalJ] = localBlock[localI][localJ];
}

__global__ void kernelSD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y;
	const int localJ = threadIdx.x;
	const int baseLead = kBlock * R1;
	int baseI, baseJ;
	if (blockIdx.y == 0) {
		baseI = baseLead;
		baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	else {
		baseJ = baseLead;
		baseI = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	__shared__ int localBlock[R1][R1];
	__shared__ int leadBlock[R1][R1];

	localBlock[localI][localJ] = deviceGraph[globalI * pitch + globalJ];
	leadBlock[localI][localJ] = deviceGraph[(baseLead + localI) * pitch + (baseLead + localJ)];
	__syncthreads();

	if (blockIdx.y == 0) {
#pragma unroll
		for (int k = 0; k < R1; ++k) {
			localBlock[localI][localJ] = min(localBlock[localI][localJ],
				leadBlock[localI][k] + localBlock[k][localJ]);
			__syncthreads();
		}
	}
	else {
#pragma unroll
		for (int k = 0; k < R1; ++k) {
			localBlock[localI][localJ] = min(localBlock[localI][localJ],
				localBlock[localI][k] + leadBlock[k][localJ]);
			__syncthreads();
		}
	}

	deviceGraph[globalI * pitch + globalJ] = localBlock[localI][localJ];
}

__global__ void kernelDD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y;
	const int localJ = threadIdx.x;
	const int baseLead = kBlock * R1;
	const int baseI = (blockIdx.y + (blockIdx.y >= kBlock)) * R1;
	const int baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	__shared__ int leadRowBlock[R1][R1];
	__shared__ int leadColumnBlock[R1][R1];

	int c = deviceGraph[globalI * pitch + globalJ];
	leadColumnBlock[localI][localJ] = deviceGraph[(baseI + localI) * pitch + (baseLead + localJ)];
	leadRowBlock[localI][localJ] = deviceGraph[(baseLead + localI) * pitch + (baseJ + localJ)];

	__syncthreads();

#pragma unroll
	for (int k = 0; k < R1; ++k) {
		c = min(c, leadColumnBlock[localI][k] + leadRowBlock[k][localJ]);
	}
	__syncthreads();

	deviceGraph[globalI * pitch + globalJ] = c;
}*/

//        
/*__global__ void kernelI(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int base = kBlock * R1;
	const int globalI = base + localI;
	const int globalJ = base + localJ;
	__shared__ int localBlock[R1][R1];

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			localBlock[localI + i][localJ + j] = deviceGraph[(globalI + i) * pitch + (globalJ + j)];
		}
	}

	__syncthreads();
	//#pragma unroll
	for (int k = 0; k < R1; ++k) {
		//#pragma unroll
		for (int i = 0; i < R2; ++i) {
			//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
					localBlock[localI + i][k] + localBlock[k][localJ + j]);
			}
		}
		__syncthreads();
	}

	//#pragma unroll
	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			deviceGraph[(globalI + i) * pitch + (globalJ + j)] = localBlock[localI + i][localJ + j];
		}
	}
}

__global__ void kernelSD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	int baseI, baseJ;
	if (blockIdx.y == 0) {
		baseI = baseLead;
		baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	else {
		baseJ = baseLead;
		baseI = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	}
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	const int leadGlobalI = baseLead + localI;
	const int leadGlobalJ = baseLead + localJ;
	__shared__ int localBlock[R1][R1];
	__shared__ int leadBlock[R1][R1];

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			localBlock[localI + i][localJ + j] = deviceGraph[(globalI + i) * pitch + (globalJ + j)];
		}
	}

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			leadBlock[localI + i][localJ + j] = deviceGraph[(leadGlobalI + i) * pitch + (leadGlobalJ + j)];
		}
	}

	__syncthreads();

	if (blockIdx.y == 0) {
		//#pragma unroll
		for (int k = 0; k < R1; ++k) {
			//#pragma unroll
			for (int i = 0; i < R2; ++i) {
				//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						leadBlock[localI + i][k] + localBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}
	else {
		//#pragma unroll
		for (int k = 0; k < R1; ++k) {
			//#pragma unroll
			for (int i = 0; i < R2; ++i) {
				//#pragma unroll
				for (int j = 0; j < R2; ++j) {
					localBlock[localI + i][localJ + j] = min(localBlock[localI + i][localJ + j],
						localBlock[localI + i][k] + leadBlock[k][localJ + j]);
				}
			}
			__syncthreads();
		}
	}

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			deviceGraph[(globalI + i) * pitch + (globalJ + j)] = localBlock[localI + i][localJ + j];
		}
	}
}

__global__ void kernelDD(int* __restrict__ deviceGraph, const int pitch, const int n, const int kBlock) {
	const int localI = threadIdx.y * R2;
	const int localJ = threadIdx.x * R2;
	const int baseLead = kBlock * R1;
	const int baseI = (blockIdx.y + (blockIdx.y >= kBlock)) * R1;
	const int baseJ = (blockIdx.x + (blockIdx.x >= kBlock)) * R1;
	const int globalI = baseI + localI;
	const int globalJ = baseJ + localJ;
	const int leadGlobalI = baseLead + localI;
	const int leadGlobalJ = baseLead + localJ;
	__shared__ int leadRowBlock[R1][R1];
	__shared__ int leadColumnBlock[R1][R1];
	int c[R2][R2];

	//#pragma unroll
	for (int i = 0; i < R2; ++i) {
		//#pragma unroll
		for (int j = 0; j < R2; ++j) {
			c[i][j] = deviceGraph[(globalI + i) * pitch + (globalJ + j)];
		}
	}

	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			leadRowBlock[localI + i][localJ + j] = deviceGraph[(leadGlobalI + i) * pitch + (globalJ + j)];
		}
	}
	for (int i = 0; i < R2; ++i) {
		for (int j = 0; j < R2; ++j) {
			leadColumnBlock[localI + i][localJ + j] = deviceGraph[(globalI + i) * pitch + (leadGlobalJ + j)];
		}
	}

	__syncthreads();

	//#pragma unroll
	for (int k = 0; k < R1; ++k) {
		//#pragma unroll
		for (int i = 0; i < R2; ++i) {
			//#pragma unroll
			for (int j = 0; j < R2; ++j) {
				c[i][j] = min(c[i][j], leadColumnBlock[localI + i][k] + leadRowBlock[k][localJ + j]);
			}
		}
	}
	__syncthreads();

	//#pragma unroll
	for (int i = 0; i < R2; ++i) {
		//#pragma unroll
		for (int j = 0; j < R2; ++j) {
			deviceGraph[(globalI + i) * pitch + (globalJ + j)] = c[i][j];
		}
	}
}*/	

	.text
	.file	"FW.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z9readGraphv                   # -- Begin function _Z9readGraphv
	.type	_Z9readGraphv,@function
_Z9readGraphv:                          # @_Z9readGraphv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.2, %esi
	movl	$n, %edx
	movl	$m, %ecx
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	n(%rip), %rsi
	imulq	%rsi, %rsi
	shlq	$2, %rsi
	leaq	8(%rsp), %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	jne	.LBB0_1
.LBB0_2:
	movl	n(%rip), %eax
	testl	%eax, %eax
	jle	.LBB0_8
# %bb.3:                                # %.preheader16.lr.ph
	movq	8(%rsp), %rcx
	xorl	%edx, %edx
	xorl	%esi, %esi
.LBB0_4:                                # %.preheader16
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_6 Depth 2
	testl	%eax, %eax
	jle	.LBB0_7
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB0_4 Depth=1
	xorl	%edi, %edi
.LBB0_6:                                # %.lr.ph
                                        #   Parent Loop BB0_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%edi, %esi
	movl	$1073741823, %r8d               # imm = 0x3FFFFFFF
	cmovel	%edx, %r8d
	imull	%esi, %eax
	cltq
	addq	%rdi, %rax
	movl	%r8d, (%rcx,%rax,4)
	movl	n(%rip), %eax
	incq	%rdi
	cmpl	%eax, %edi
	jl	.LBB0_6
.LBB0_7:                                # %._crit_edge
                                        #   in Loop: Header=BB0_4 Depth=1
	incq	%rsi
	cmpl	%eax, %esi
	jl	.LBB0_4
.LBB0_8:                                # %.preheader
	cmpl	$0, m(%rip)
	jle	.LBB0_11
# %bb.9:                                # %.lr.ph20.preheader
	leaq	28(%rsp), %r14
	leaq	24(%rsp), %r15
	leaq	20(%rsp), %r12
	xorl	%ebp, %ebp
.LBB0_10:                               # %.lr.ph20
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	movq	%r12, %r8
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	20(%rsp), %eax
	movq	8(%rsp), %rcx
	movslq	28(%rsp), %rdx
	movslq	n(%rip), %rsi
	imulq	%rdx, %rsi
	movslq	24(%rsp), %rdx
	addq	%rsi, %rdx
	movl	%eax, (%rcx,%rdx,4)
	incl	%ebp
	cmpl	m(%rip), %ebp
	jl	.LBB0_10
.LBB0_11:                               # %._crit_edge21
	movq	%rbx, %rdi
	callq	fclose
	movq	8(%rsp), %rax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_1:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rcx
	movl	$.L.str.3, %edi
	movl	$22, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB0_2
.Lfunc_end0:
	.size	_Z9readGraphv, .Lfunc_end0-_Z9readGraphv
	.cfi_endproc
                                        # -- End function
	.globl	_Z11writeResultPi               # -- Begin function _Z11writeResultPi
	.type	_Z11writeResultPi,@function
_Z11writeResultPi:                      # @_Z11writeResultPi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rbx
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %esi
	callq	fopen
	movq	%rax, %r14
	movl	n(%rip), %edx
	movl	$.L.str.7, %esi
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	fprintf
	movl	n(%rip), %eax
	testl	%eax, %eax
	jle	.LBB1_7
# %bb.1:                                # %.preheader.preheader
	xorl	%ebp, %ebp
	xorl	%r15d, %r15d
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%eax, %eax
	jle	.LBB1_6
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_2 Depth=1
	movslq	%r15d, %rax
	leaq	(%rbx,%rax,4), %r13
	xorl	%r12d, %r12d
.LBB1_4:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r13,%r12,4), %edx
	movl	$.L.str.8, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	fprintf
	incq	%r12
	cmpl	n(%rip), %r12d
	jl	.LBB1_4
# %bb.5:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB1_2 Depth=1
	addl	%r12d, %r15d
.LBB1_6:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	$10, %edi
	movq	%r14, %rsi
	callq	fputc@PLT
	incl	%ebp
	movl	n(%rip), %eax
	cmpl	%eax, %ebp
	jl	.LBB1_2
.LBB1_7:                                # %._crit_edge16
	movq	%r14, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end1:
	.size	_Z11writeResultPi, .Lfunc_end1-_Z11writeResultPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z4ceilii                       # -- Begin function _Z4ceilii
	.type	_Z4ceilii,@function
_Z4ceilii:                              # @_Z4ceilii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	leal	(%rdi,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
	retq
.Lfunc_end2:
	.size	_Z4ceilii, .Lfunc_end2-_Z4ceilii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5checkPi                      # -- Begin function _Z5checkPi
	.type	_Z5checkPi,@function
_Z5checkPi:                             # @_Z5checkPi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rbx
	movl	$.L.str.10, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	4(%rsp), %r15
	movl	$.L.str.11, %esi
	movq	%rax, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	(%r15), %eax
	testl	%eax, %eax
	jle	.LBB3_7
# %bb.1:                                # %.preheader.preheader
	movq	%rsp, %r15
	xorl	%ebp, %ebp
.LBB3_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
	testl	%eax, %eax
	jle	.LBB3_6
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB3_2 Depth=1
	movslq	%ebp, %r12
	xorl	%r13d, %r13d
.LBB3_4:                                # %.lr.ph
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$.L.str.11, %esi
	movq	%r14, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	(%rsp), %eax
	movslq	n(%rip), %rcx
	imulq	%r12, %rcx
	addq	%r13, %rcx
	cmpl	(%rbx,%rcx,4), %eax
	jne	.LBB3_9
# %bb.5:                                # %.critedge
                                        #   in Loop: Header=BB3_4 Depth=2
	movl	4(%rsp), %eax
	incq	%r13
	cmpl	%eax, %r13d
	jl	.LBB3_4
.LBB3_6:                                # %.critedge24
                                        #   in Loop: Header=BB3_2 Depth=1
	incl	%ebp
	cmpl	%eax, %ebp
	jl	.LBB3_2
.LBB3_7:                                # %.critedge26
	movq	%r14, %rdi
	callq	fclose
	movb	$1, %al
	jmp	.LBB3_8
.LBB3_9:
	movq	%r14, %rdi
	callq	fclose
	xorl	%eax, %eax
.LBB3_8:
                                        # kill: def $al killed $al killed $eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z5checkPi, .Lfunc_end3-_Z5checkPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__wakeGPUv     # -- Begin function _Z22__device_stub__wakeGPUv
	.type	_Z22__device_stub__wakeGPUv,@function
_Z22__device_stub__wakeGPUv:            # @_Z22__device_stub__wakeGPUv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z7wakeGPUv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z22__device_stub__wakeGPUv, .Lfunc_end4-_Z22__device_stub__wakeGPUv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
.LCPI5_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$0, cudaStatus(%rip)
	jne	.LBB5_1
.LBB5_2:
	callq	_Z9readGraphv
	movq	%rax, %r15
	movl	$.Lstr, %edi
	callq	puts@PLT
	movslq	n(%rip), %rcx
	leal	63(%rcx), %ebx
	leal	126(%rcx), %r14d
	testl	%ebx, %ebx
	cmovnsl	%ebx, %r14d
	movl	%r14d, %eax
	andl	$-64, %eax
	cmpl	%ecx, %eax
	jne	.LBB5_3
# %bb.4:
	leaq	24(%rsp), %rdi
	movq	$0, (%rdi)
	leaq	(,%rcx,4), %rdx
	leaq	32(%rsp), %rsi
	callq	hipMallocPitch
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	jne	.LBB5_5
.LBB5_6:
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movslq	n(%rip), %r9
	leaq	(,%r9,4), %rcx
	movl	$1, (%rsp)
	movq	%r15, 48(%rsp)                  # 8-byte Spill
	movq	%r15, %rdx
	movq	%rcx, %r8
	callq	hipMemcpy2D
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	jne	.LBB5_7
.LBB5_8:
	movabsq	$4294967297, %r12               # imm = 0x100000001
	movq	32(%rsp), %r15
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.9:
	callq	_Z22__device_stub__wakeGPUv
.LBB5_10:
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	cmpl	$64, %ebx
	jl	.LBB5_19
# %bb.11:                               # %.lr.ph.preheader
	sarl	$6, %r14d
	leal	-1(%r14), %ebp
	shrq	$2, %r15
	movq	%rbp, %r13
	shlq	$32, %r13
	orq	%rbp, %r13
	btsq	$33, %rbp
	xorl	%r12d, %r12d
	movabsq	$137438953504, %rbx             # imm = 0x2000000020
.LBB5_12:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_14
# %bb.13:                               #   in Loop: Header=BB5_12 Depth=1
	movq	24(%rsp), %rdi
	movl	n(%rip), %edx
	movl	%r15d, %esi
	movl	%r12d, %ecx
	callq	_Z22__device_stub__kernelIPiiii
.LBB5_14:                               #   in Loop: Header=BB5_12 Depth=1
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.15:                               #   in Loop: Header=BB5_12 Depth=1
	movq	24(%rsp), %rdi
	movl	n(%rip), %edx
	movl	%r15d, %esi
	movl	%r12d, %ecx
	callq	_Z23__device_stub__kernelSDPiiii
.LBB5_16:                               #   in Loop: Header=BB5_12 Depth=1
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_18
# %bb.17:                               #   in Loop: Header=BB5_12 Depth=1
	movq	24(%rsp), %rdi
	movl	n(%rip), %edx
	movl	%r15d, %esi
	movl	%r12d, %ecx
	callq	_Z23__device_stub__kernelDDPiiii
.LBB5_18:                               #   in Loop: Header=BB5_12 Depth=1
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	incl	%r12d
	cmpl	%r12d, %r14d
	jne	.LBB5_12
.LBB5_19:                               # %._crit_edge
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	subq	40(%rsp), %rax                  # 8-byte Folded Reload
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	mulsd	.LCPI5_1(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.17, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movslq	n(%rip), %r9
	leaq	(,%r9,4), %rsi
	movq	24(%rsp), %rdx
	movq	32(%rsp), %rcx
	movl	$1, (%rsp)
	movq	48(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rdi
	movq	%rsi, %r8
	callq	hipMemcpy2D
	movl	%eax, cudaStatus(%rip)
	testl	%eax, %eax
	jne	.LBB5_20
.LBB5_21:
	movq	%r14, %rdi
	callq	_Z5checkPi
	movl	$.L.str.18, %ecx
	movl	$.L.str.19, %edi
	testb	%al, %al
	cmovneq	%rcx, %rdi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	printf
	movq	%r14, %rdi
	callq	_Z11writeResultPi
	movq	24(%rsp), %rdi
	callq	hipFree
	jmp	.LBB5_22
.LBB5_3:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$1, %ebx
.LBB5_22:
	movl	%ebx, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_1:
	.cfi_def_cfa_offset 112
	movq	stderr(%rip), %rcx
	movl	$.L.str.12, %edi
	movl	$63, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB5_2
.LBB5_5:
	movq	stderr(%rip), %rcx
	movl	$.L.str.15, %edi
	movl	$23, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB5_6
.LBB5_7:
	movq	stderr(%rip), %rcx
	movl	$.L.str.16, %edi
	movl	$19, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB5_8
.LBB5_20:
	movq	stderr(%rip), %rcx
	movl	$.L.str.16, %edi
	movl	$19, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB5_21
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__kernelIPiiii # -- Begin function _Z22__device_stub__kernelIPiiii
	.type	_Z22__device_stub__kernelIPiiii,@function
_Z22__device_stub__kernelIPiiii:        # @_Z22__device_stub__kernelIPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7kernelIPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z22__device_stub__kernelIPiiii, .Lfunc_end6-_Z22__device_stub__kernelIPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernelSDPiiii # -- Begin function _Z23__device_stub__kernelSDPiiii
	.type	_Z23__device_stub__kernelSDPiiii,@function
_Z23__device_stub__kernelSDPiiii:       # @_Z23__device_stub__kernelSDPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8kernelSDPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z23__device_stub__kernelSDPiiii, .Lfunc_end7-_Z23__device_stub__kernelSDPiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernelDDPiiii # -- Begin function _Z23__device_stub__kernelDDPiiii
	.type	_Z23__device_stub__kernelDDPiiii,@function
_Z23__device_stub__kernelDDPiiii:       # @_Z23__device_stub__kernelDDPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8kernelDDPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z23__device_stub__kernelDDPiiii, .Lfunc_end8-_Z23__device_stub__kernelDDPiiii
	.cfi_endproc
                                        # -- End function
	.section	.text.startup,"ax",@progbits
	.type	_GLOBAL__sub_I_FW.hip,@function # -- Begin function _GLOBAL__sub_I_FW.hip
_GLOBAL__sub_I_FW.hip:                  # @_GLOBAL__sub_I_FW.hip
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	%eax, cudaStatus(%rip)
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_GLOBAL__sub_I_FW.hip, .Lfunc_end9-_GLOBAL__sub_I_FW.hip
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB10_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB10_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7wakeGPUv, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7kernelIPiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernelSDPiiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernelDDPiiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end10:
	.size	__hip_module_ctor, .Lfunc_end10-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB11_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB11_2:
	retq
.Lfunc_end11:
	.size	__hip_module_dtor, .Lfunc_end11-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	n,@object                       # @n
	.bss
	.globl	n
	.p2align	2, 0x0
n:
	.long	0                               # 0x0
	.size	n, 4

	.type	m,@object                       # @m
	.globl	m
	.p2align	2, 0x0
m:
	.long	0                               # 0x0
	.size	m, 4

	.type	cudaStatus,@object              # @cudaStatus
	.globl	cudaStatus
	.p2align	2, 0x0
cudaStatus:
	.long	0                               # 0x0
	.size	cudaStatus, 4

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA_FW/graph.txt"
	.size	.L.str, 18

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d %d"
	.size	.L.str.2, 6

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"CudaMallocHost failed!"
	.size	.L.str.3, 23

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d %d %d"
	.size	.L.str.4, 9

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"output.txt"
	.size	.L.str.5, 11

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"w"
	.size	.L.str.6, 2

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%d\n"
	.size	.L.str.7, 4

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"%d "
	.size	.L.str.8, 4

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"output_true.txt"
	.size	.L.str.10, 16

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"%d"
	.size	.L.str.11, 3

	.type	_Z7wakeGPUv,@object             # @_Z7wakeGPUv
	.section	.rodata,"a",@progbits
	.globl	_Z7wakeGPUv
	.p2align	3, 0x0
_Z7wakeGPUv:
	.quad	_Z22__device_stub__wakeGPUv
	.size	_Z7wakeGPUv, 8

	.type	.L.str.12,@object               # @.str.12
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.12:
	.asciz	"hipSetDevice failed!  Do you have a CUDA-capable GPU installed?"
	.size	.L.str.12, 64

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"CudaMallocPitch failed!"
	.size	.L.str.15, 24

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"hipMemcpy2D failed!"
	.size	.L.str.16, 20

	.type	_Z7kernelIPiiii,@object         # @_Z7kernelIPiiii
	.section	.rodata,"a",@progbits
	.globl	_Z7kernelIPiiii
	.p2align	3, 0x0
_Z7kernelIPiiii:
	.quad	_Z22__device_stub__kernelIPiiii
	.size	_Z7kernelIPiiii, 8

	.type	_Z8kernelSDPiiii,@object        # @_Z8kernelSDPiiii
	.globl	_Z8kernelSDPiiii
	.p2align	3, 0x0
_Z8kernelSDPiiii:
	.quad	_Z23__device_stub__kernelSDPiiii
	.size	_Z8kernelSDPiiii, 8

	.type	_Z8kernelDDPiiii,@object        # @_Z8kernelDDPiiii
	.globl	_Z8kernelDDPiiii
	.p2align	3, 0x0
_Z8kernelDDPiiii:
	.quad	_Z23__device_stub__kernelDDPiiii
	.size	_Z8kernelDDPiiii, 8

	.type	.L.str.17,@object               # @.str.17
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.17:
	.asciz	"(ms)\n"
	.size	.L.str.17, 6

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"Result is correct\n"
	.size	.L.str.18, 19

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"Result is not correct\n"
	.size	.L.str.19, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7wakeGPUv"
	.size	.L__unnamed_1, 12

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7kernelIPiiii"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8kernelSDPiiii"
	.size	.L__unnamed_3, 17

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z8kernelDDPiiii"
	.size	.L__unnamed_4, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	_GLOBAL__sub_I_FW.hip
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Graph is loaded"
	.size	.Lstr, 16

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"n should divide by R1"
	.size	.Lstr.1, 22

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__wakeGPUv
	.addrsig_sym _Z22__device_stub__kernelIPiiii
	.addrsig_sym _Z23__device_stub__kernelSDPiiii
	.addrsig_sym _Z23__device_stub__kernelDDPiiii
	.addrsig_sym _GLOBAL__sub_I_FW.hip
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym n
	.addrsig_sym m
	.addrsig_sym _Z7wakeGPUv
	.addrsig_sym _Z7kernelIPiiii
	.addrsig_sym _Z8kernelSDPiiii
	.addrsig_sym _Z8kernelDDPiiii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7wakeGPUv             ; -- Begin function _Z7wakeGPUv
	.globl	_Z7wakeGPUv
	.p2align	8
	.type	_Z7wakeGPUv,@function
_Z7wakeGPUv:                            ; @_Z7wakeGPUv
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7wakeGPUv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7wakeGPUv, .Lfunc_end0-_Z7wakeGPUv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7kernelIPiiii         ; -- Begin function _Z7kernelIPiiii
	.globl	_Z7kernelIPiiii
	.p2align	8
	.type	_Z7kernelIPiiii,@function
_Z7kernelIPiiii:                        ; @_Z7kernelIPiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x10
	s_load_b32 s3, s[0:1], 0x8
	v_bfe_u32 v4, v0, 10, 10
	v_and_b32_e32 v5, 0x3ff, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, v4, 5, v5
	v_lshrrev_b32_e32 v1, 6, v0
	v_and_b32_e32 v0, 63, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b32_e32 v3, 2, v0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s2, 6
	v_add_nc_u32_e32 v2, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_or_b32 v3, v1, 8, v3
	v_mul_lo_u32 v2, s3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v2, s2, v0
	s_lshl_b32 s2, s3, 4
	s_mov_b32 s3, 0
	v_mov_b32_e32 v1, v0
.LBB1_1:                                ; %.preheader67
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b32 v2, v[6:7], off
	v_add_nc_u32_e32 v6, s3, v3
	s_addk_i32 s3, 0x1000
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s3, 0x4000
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v2
	s_cbranch_scc1 .LBB1_1
; %bb.2:
	v_lshlrev_b32_e32 v1, 1, v5
	v_lshlrev_b32_e32 v2, 1, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_lshlrev_b32_e32 v4, 2, v1
	buffer_gl0_inv
.LBB1_3:                                ; %.preheader66
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	v_lshl_add_u32 v5, s3, 8, v4
	s_mov_b32 s4, -1
	s_mov_b32 s5, 0
.LBB1_4:                                ; %.preheader65
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, s5, v2
	s_mov_b32 s5, 1
	s_and_b32 vcc_lo, exec_lo, s4
	s_mov_b32 s4, 0
	v_lshlrev_b32_e32 v6, 8, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v10, s3, 2, v6
	v_lshl_add_u32 v11, v1, 2, v6
	ds_load_b32 v12, v10
	ds_load_b64 v[6:7], v5
	ds_load_b64 v[8:9], v11
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v6, v6, v12
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_min_i32_e32 v6, v8, v6
	ds_store_b32 v11, v6
	ds_load_b32 v6, v10
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v7, v6
	v_min_i32_e32 v6, v9, v6
	ds_store_b32 v11, v6 offset:4
	s_cbranch_vccnz .LBB1_4
; %bb.5:                                ;   in Loop: Header=BB1_3 Depth=1
	s_add_i32 s3, s3, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s3, 64
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_3
; %bb.6:                                ; %.preheader.preheader
	s_mov_b32 s3, 0
.LBB1_7:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s3, v3
	s_addk_i32 s3, 0x1000
	s_cmpk_lg_i32 s3, 0x4000
	ds_load_b32 v4, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_nc_u32_e32 v0, s2, v0
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v4, off
	s_cbranch_scc1 .LBB1_7
; %bb.8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7kernelIPiiii
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 6
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7kernelIPiiii, .Lfunc_end1-_Z7kernelIPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 8
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8kernelSDPiiii        ; -- Begin function _Z8kernelSDPiiii
	.globl	_Z8kernelSDPiiii
	.p2align	8
	.type	_Z8kernelSDPiiii,@function
_Z8kernelSDPiiii:                       ; @_Z8kernelSDPiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x10
	s_load_b32 s4, s[0:1], 0x8
	v_bfe_u32 v5, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, v5, 5, v4
	v_lshrrev_b32_e32 v6, 6, v0
	v_and_b32_e32 v7, 63, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 2, v7
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s5, s2, 6
	s_cmp_lg_u32 s15, 0
	s_cselect_b32 s3, -1, 0
	s_cmp_ge_u32 s14, s2
	v_lshl_or_b32 v3, v6, 8, v2
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 0
	s_addc_u32 s2, s14, 0
	s_lshl_b32 s2, s2, 6
	s_cmp_eq_u32 s15, 0
	s_cselect_b32 s6, s5, s2
	s_cselect_b32 s2, s2, s5
	v_add_nc_u32_e32 v1, s6, v6
	s_mov_b32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s4, v1
	v_add3_u32 v0, s2, v1, v7
	s_lshl_b32 s2, s4, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v0
.LBB2_1:                                ; %.preheader121
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[8:9], 2, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v2, v[8:9], off
	v_add_nc_u32_e32 v8, s6, v3
	s_addk_i32 s6, 0x1000
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s6, 0x4000
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v2
	s_cbranch_scc1 .LBB2_1
; %bb.2:                                ; %.preheader119.preheader
	v_add_nc_u32_e32 v1, s5, v6
	v_add_nc_u32_e32 v6, 0x4000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, s4, v1
	s_mov_b32 s4, 0
	v_add3_u32 v1, v1, s5, v7
.LBB2_3:                                ; %.preheader119
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	global_load_b32 v2, v[7:8], off
	v_add_nc_u32_e32 v7, s4, v6
	s_addk_i32 s4, 0x1000
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s4, 0x4000
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v2
	s_cbranch_scc1 .LBB2_3
; %bb.4:
	v_lshlrev_b32_e32 v4, 1, v4
	v_lshlrev_b32_e32 v5, 1, v5
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s3, -1
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v6, 2, v4
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB2_10
; %bb.5:                                ; %.preheader116.preheader
	s_mov_b32 s3, 0
.LBB2_6:                                ; %.preheader116
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_7 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_lshl_add_u32 v1, s3, 8, v6
	s_mov_b32 s4, -1
	s_mov_b32 s5, 0
	ds_load_b64 v[1:2], v1 offset:16384
.LBB2_7:                                ; %.preheader115
                                        ;   Parent Loop BB2_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_or_b32_e32 v7, s5, v5
	s_mov_b32 s5, 1
	s_and_b32 vcc_lo, exec_lo, s4
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v7, 8, v7
	v_lshl_add_u32 v9, s3, 2, v7
	v_lshl_add_u32 v10, v4, 2, v7
	ds_load_b32 v11, v9
	ds_load_b64 v[7:8], v10
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v11, v1, v11
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_min_i32_e32 v7, v7, v11
	ds_store_b32 v10, v7
	ds_load_b32 v7, v9
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v7, v2, v7
	v_min_i32_e32 v7, v8, v7
	ds_store_b32 v10, v7 offset:4
	s_cbranch_vccnz .LBB2_7
; %bb.8:                                ;   in Loop: Header=BB2_6 Depth=1
	s_add_i32 s3, s3, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s3, 64
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_6
; %bb.9:                                ; %Flow
	s_mov_b32 s3, 0
.LBB2_10:                               ; %Flow168
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_15
; %bb.11:                               ; %.preheader113.preheader
	s_mov_b32 s3, 0
.LBB2_12:                               ; %.preheader113
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_13 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_lshl_add_u32 v1, s3, 8, v6
	s_mov_b32 s4, -1
	s_mov_b32 s5, 0
.LBB2_13:                               ; %.preheader112
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, s5, v5
	s_mov_b32 s5, 1
	s_and_b32 vcc_lo, exec_lo, s4
	s_mov_b32 s4, 0
	v_lshlrev_b32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v11, v4, 2, v2
	v_lshl_add_u32 v2, s3, 2, v2
	ds_load_b64 v[7:8], v11
	ds_load_b32 v2, v2 offset:16384
	ds_load_b64 v[9:10], v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v9, v9, v2
	v_add_nc_u32_e32 v2, v10, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_i32_e32 v7, v7, v9
	v_min_i32_e32 v8, v8, v2
	ds_store_b64 v11, v[7:8]
	s_cbranch_vccnz .LBB2_13
; %bb.14:                               ;   in Loop: Header=BB2_12 Depth=1
	s_add_i32 s3, s3, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s3, 64
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_12
.LBB2_15:                               ; %.preheader.preheader
	s_mov_b32 s3, 0
.LBB2_16:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s3, v3
	s_addk_i32 s3, 0x1000
	s_cmpk_lg_i32 s3, 0x4000
	ds_load_b32 v4, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_nc_u32_e32 v0, s2, v0
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v4, off
	s_cbranch_scc1 .LBB2_16
; %bb.17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernelSDPiiii
		.amdhsa_group_segment_fixed_size 32768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8kernelSDPiiii, .Lfunc_end2-_Z8kernelSDPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8kernelDDPiiii        ; -- Begin function _Z8kernelDDPiiii
	.globl	_Z8kernelDDPiiii
	.p2align	8
	.type	_Z8kernelDDPiiii,@function
_Z8kernelDDPiiii:                       ; @_Z8kernelDDPiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s7, s[2:3], 0x10
	s_load_b32 s4, s[2:3], 0x8
	v_bfe_u32 v8, v0, 10, 10
	v_and_b32_e32 v10, 0x3ff, v0
	s_load_b64 s[2:3], s[2:3], 0x0
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v8, 5, v10
	v_lshrrev_b32_e32 v11, 6, v1
	v_and_b32_e32 v5, 63, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 2, v5
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s15, s7
	s_cselect_b32 s5, -1, 0
	v_lshl_or_b32 v4, v11, 8, v2
	s_cmp_lg_u32 s5, 0
	s_addc_u32 s5, s15, 0
	s_cmp_ge_u32 s14, s7
	v_lshl_add_u32 v6, s5, 6, v11
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s5, 0
	v_mul_lo_u32 v9, s4, v6
	s_addc_u32 s5, s14, 0
	s_lshl_b32 s6, s4, 4
	s_lshl_b32 s5, s5, 6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v1, v9, s5, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v1
.LBB3_1:                                ; %.preheader131
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v7, s8, v4
	s_addk_i32 s8, 0x1000
	s_cmpk_lg_i32 s8, 0x4000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[2:3]
	v_add_nc_u32_e32 v2, s6, v2
	v_add_co_u32 v12, vcc_lo, s2, v12
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	global_load_b32 v3, v[12:13], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v3
	s_cbranch_scc1 .LBB3_1
; %bb.2:                                ; %.preheader130
	s_load_b64 s[0:1], s[0:1], 0x4
	v_lshlrev_b32_e32 v2, 3, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_bfe_u32 v0, v0, 20, 10
	v_lshl_add_u32 v7, v8, 9, v2
	ds_load_2addr_b64 v[12:15], v7 offset1:32
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s0, s1
	v_mul_lo_u32 v2, s0, v10
	s_lshl_b32 s0, s7, 6
	v_lshlrev_b32_e32 v10, 1, v10
	v_add_nc_u32_e32 v3, s0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v3, s4, v3
	v_mad_u32_u24 v2, v8, s1, v2
	v_lshlrev_b32_e32 v8, 1, v8
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v2, v2, v0, 4
	v_add_nc_u32_e32 v0, 0x8000, v2
	s_waitcnt lgkmcnt(0)
	ds_store_b128 v2, v[12:15] offset:32768
	v_add3_u32 v2, v3, s5, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_3:                                ; %.preheader129
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[2:3]
	v_add_nc_u32_e32 v2, s6, v2
	v_add_co_u32 v11, vcc_lo, s2, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	global_load_b32 v3, v[11:12], off
	v_add_nc_u32_e32 v11, s1, v4
	s_addk_i32 s1, 0x1000
	s_cmpk_lg_i32 s1, 0x4000
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v3
	s_cbranch_scc1 .LBB3_3
; %bb.4:                                ; %.preheader127.preheader
	v_add3_u32 v2, v9, s0, v5
	v_add_nc_u32_e32 v9, 0x4000, v4
	s_mov_b32 s0, 0
.LBB3_5:                                ; %.preheader127
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[11:12], 2, v[2:3]
	v_add_nc_u32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	global_load_b32 v3, v[11:12], off
	v_add_nc_u32_e32 v11, s0, v9
	s_addk_i32 s0, 0x1000
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s0, 0x4000
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v3
	s_cbranch_scc1 .LBB3_5
; %bb.6:
	v_lshlrev_b32_e32 v9, 2, v10
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_7:                                ; %.preheader126
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_8 Depth 2
	v_lshl_add_u32 v2, s0, 8, v9
	s_mov_b32 s1, -1
	s_mov_b32 s6, 0
	ds_load_b64 v[2:3], v2
.LBB3_8:                                ; %.preheader125
                                        ;   Parent Loop BB3_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_or_b32_e32 v10, s6, v8
	v_lshl_add_u32 v12, s6, 3, v0
	s_mov_b32 s6, 1
	s_and_b32 vcc_lo, exec_lo, s1
	s_mov_b32 s1, 0
	v_lshlrev_b32_e32 v10, 8, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v10, s0, 2, v10
	ds_load_b32 v13, v10 offset:16384
	ds_load_b64 v[10:11], v12
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v14, v2, v13
	v_add_nc_u32_e32 v13, v3, v13
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_i32_e32 v10, v10, v14
	v_min_i32_e32 v11, v11, v13
	ds_store_b64 v12, v[10:11]
	s_cbranch_vccnz .LBB3_8
; %bb.9:                                ;   in Loop: Header=BB3_7 Depth=1
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 64
	s_cbranch_scc0 .LBB3_7
; %bb.10:                               ; %.preheader124
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b128 v[8:11], v0
	v_add_nc_u32_e32 v0, 16, v6
	v_add_nc_u32_e32 v2, 32, v6
	v_add_nc_u32_e32 v3, 48, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, v0, s4
	v_mul_lo_u32 v6, v2, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v13, v3, s4
	v_ashrrev_i32_e32 v2, 31, v1
	v_add3_u32 v0, v0, s5, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v12, v6, s5, v5
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add3_u32 v5, v13, s5, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	ds_store_2addr_b64 v7, v[8:9], v[10:11] offset1:32
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_stride64_b32 v[7:8], v4 offset1:16
	ds_load_2addr_stride64_b32 v[9:10], v4 offset0:32 offset1:48
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[11:12], 2, v[12:13]
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v11, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt lgkmcnt(1)
	s_clause 0x1
	global_store_b32 v[2:3], v7, off
	global_store_b32 v[0:1], v8, off
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v[11:12], v9, off
	global_store_b32 v[4:5], v10, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernelDDPiiii
		.amdhsa_group_segment_fixed_size 49152
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z8kernelDDPiiii, .Lfunc_end3-_Z8kernelDDPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1048
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 49152 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7wakeGPUv
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z7wakeGPUv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7kernelIPiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z7kernelIPiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 32768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernelSDPiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8kernelSDPiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 49152
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernelDDPiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8kernelDDPiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
