#include<stdio.h>

__global__ void computeFutureGen(int* current,int* future,int n){
        int col=threadIdx.x+blockIdx.x*blockDim.x;
        int row=threadIdx.y+blockIdx.y*blockDim.y;
        int index=col+row*n;
        //Computing the number of alive neighbors
        int neighAlive=0;
if(col<n && row<n){     //Computation starts only when the thread is within our matrix row & column limit
        //Different cases have to considered before counting the alive neighbors
        if(col==0 && row==0){   //When current node is at top left corner of the matrix
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index+n];   //Neighbor at the bottom
                neighAlive+=current[index+n+1]; //Neighbor at the bottom right diagonal
        }
        else if(col==0 && row==n-1){    //When current node is at bottom left corner
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n];   //Neighbor directly above
                neighAlive+=current[index-n+1]; //Neighbor at top right diagonal
        }
        else if(col==n-1 && row==0){    //When current node is at top right corner
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+n-1]; //Neighbor at bottom left
                neighAlive+=current[index+n];   //Neighbor exactly below
        }
        else if(col==n-1 && row==n-1){  //When current node is at bottom right corner
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n-1]; //Neighbor at top left diagonally
        }
        else if(row==0 && col>0 && col<n-1){    //When current node is at top wall excluding the corners
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index+n-1]; //Neighbor diagonally left below
                neighAlive+=current[index+n];   //Neighbor exactly below
                neighAlive+=current[index+n+1]; //Neighbor diagonally right below
        }
        else if(row==n-1 && col>0 && col<n-1){  //When current node is on bottom wall excluding the corners
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n+1]; //Neighbor diagonally right on top
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n-1]; //Neighbor diagonally left on top
        }
        else if(col==0 && row>0 && row<n-1){    //When current node is on left wall excluding corners
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n+1]; //Neighbor diagonally right on top
                neighAlive+=current[index+n];   //Neighbor exactly down
                neighAlive+=current[index+n+1]; //Neighbor diagonally right below
        }
        else if(col==n-1 && row>0 && row<n-1){  //When current node is on right wall excluding corners
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n-1]; //Neighbor diagonally left on top
                neighAlive+=current[index+n-1]; //Neighbor diagonally left below
                neighAlive+=current[index+n];   //Neighbor exactly below
        }
        else{   //For all middle elements, within the boundaries described above
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n-1]; //Neighbor diagonally left on top
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n+1]; //Neighbor diagonally right on top
                neighAlive+=current[index+n-1]; //Neighbor diagonally left below
                neighAlive+=current[index+n];   //Neighbor exactly below
                neighAlive+=current[index+n+1]; //Neighbor diagonally right below
        }



        //Code block to decide the alive status of a cell based on the number of alive neighbors
        if(current[index]==1 && neighAlive<2)
                future[index]=0;
        else if(current[index]==1 && (neighAlive==2 || neighAlive==3))
                future[index]=1;
        else if(current[index]==1 && neighAlive>3)
                future[index]=0;
        else if(current[index]==0 && neighAlive==3)
                future[index]=1;
        else
                future[index]=0;
}
}


int main(int argc,char** argv){
        int i,j,k;
        int n=0;
        n=atoi(argv[1]);
        int currentGen[n][n];
        int futureGen[n][n];
        dim3 threadsPerBlock(10,10);
        dim3 numBlocks(n/threadsPerBlock.x,n/threadsPerBlock.x);
        int* current;
        int* future;
        float milliseconds=0;
        cudaError_t err;
        cudaEvent_t start,stop;
        cudaEventCreate(&start);
        cudaEventCreate(&stop);

        /*Populating the input matrix currentGen with random 0's
        and 1's using rand() method*/
        for(i=0;i<n;i++)
                for(j=0;j<n;j++)
                        currentGen[i][j]=rand()%2;

        //Initializing the futureGen matrix with all 0's
        for(i=0;i<n;i++)
                for(j=0;j<n;j++)
                        futureGen[i][j]=0;

        //Allocating memory for device copy of current generation matrix
        cudaMalloc((void **) &current,sizeof(int)*n*n);
        err=cudaGetLastError();
        if(err!=cudaSuccess)
                printf("\nERROR after cudaMalloc of current : %s\n\n",cudaGetErrorString(err));

        //Allocating memory for device copy of future generation matrix
        cudaMalloc((void **) &future,sizeof(int)*n*n);
         err=cudaGetLastError();
        if(err!=cudaSuccess)
                printf("\nERROR after cudaMalloc of future: %s\n\n",cudaGetErrorString(err));


        //Copying current generation matrix from host to device
        cudaMemcpy(current,currentGen,sizeof(int)*n*n,cudaMemcpyHostToDevice);
        err=cudaGetLastError();
        if(err!=cudaSuccess)
                printf("\nERROR after cudaMemcpy of currentGen to current: %s\n\n",cudaGetErrorString(err));


        //Displaying the first 10 rows and columns of currentGen matrix
        printf("\nPrinting the alive state of first 10 rows and columns of %dx%d current generation matrix\n",n,n);
        for(i=0;i<10;i++){
                for(j=0;j<10;j++){
                        printf("%d\t",currentGen[i][j]);
                }
                printf("\n");
        }

        cudaEventRecord(start);
        /*Loop for calculating the alive state of the cells after
        10, 100 and 1000 iterations*/
        for(k=1;k<=1000;k++){

        //Calling the kernel
        if(k==1)
                computeFutureGen<<<numBlocks,threadsPerBlock>>>(current,future,n);
        else
                computeFutureGen<<<numBlocks,threadsPerBlock>>>(future,future,n);

        err=cudaGetLastError();
        if(err!=cudaSuccess)
                printf("\nERROR after kernel call: %s\n\n",cudaGetErrorString(err));
        cudaEventRecord(stop);

        //Copying the result from device to host
        cudaMemcpy(futureGen,future,sizeof(int)*n*n,cudaMemcpyDeviceToHost);
        err=cudaGetLastError();
        if(err!=cudaSuccess)
                printf("\nERROR after cudaMemcpy of future to futureGen: %s\n\n",cudaGetErrorString(err));


        //Displaying the first 10 rows and columns of futureGen matrix
        //Display only after 10th, 100th and 1000th iteration
        if(k==10 || k==100 || k==1000){
        printf("\nPrinting the alive state of first 10 rows and columns of %dx%d future generation matrix after %d iterations\n",n,n,k);
        for(i=0;i<10;i++){
                for(j=0;j<10;j++){
                        printf("%d\t",futureGen[i][j]);
                }
                printf("\n");
        }
        cudaEventElapsedTime(&milliseconds,start,stop);
        printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
        }

        }
        return 0;
}



	.file	"tmpxft_0026a028_00000000-6_conwayCuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i
	.type	_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i, @function
_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z16computeFutureGenPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i, .-_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i
	.globl	_Z16computeFutureGenPiS_i
	.type	_Z16computeFutureGenPiS_i, @function
_Z16computeFutureGenPiS_i:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i
	.cfi_endproc
.LFE2053:
	.size	_Z16computeFutureGenPiS_i, .-_Z16computeFutureGenPiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\nERROR after cudaMalloc of current : %s\n\n"
.LC2:
	.string	"\nERROR after cudaMalloc of future: %s\n\n"
.LC3:
	.string	"\nERROR after cudaMemcpy of currentGen to current: %s\n\n"
.LC4:
	.string	"\nPrinting the alive state of first 10 rows and columns of %dx%d current generation matrix\n"
.LC5:
	.string	"%d\t"
.LC6:
	.string	"\n"
.LC7:
	.string	"\nERROR after kernel call: %s\n\n"
.LC8:
	.string	"\nERROR after cudaMemcpy of future to futureGen: %s\n\n"
.LC9:
	.string	"\nPrinting the alive state of first 10 rows and columns of %dx%d future generation matrix after %d iterations\n"
.LC10:
	.string	"Time taken for this computation = %f milliseconds\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$120, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	8(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	call	atoi@PLT
	movq	%rsp, %rcx
	movslq	%eax, %r12
	movq	%r12, %rbx
	leaq	0(,%r12,4), %r13
	imulq	%r12, %r12
	leaq	0(,%r12,4), %rax
	movq	%rax, -136(%rbp)
	addq	$15, %rax
	movq	%rax, %rsi
	movq	%rax, %rdx
	andq	$-4096, %rsi
	andq	$-16, %rdx
	subq	%rsi, %rcx
.L9:
	cmpq	%rcx, %rsp
	je	.L10
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L9
.L10:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L11
	orq	$0, -8(%rsp,%rdx)
.L11:
	movq	%rsp, -144(%rbp)
	movq	%rax, %rdx
	movq	%rsp, %rcx
	andq	$-4096, %rax
	andq	$-16, %rdx
	subq	%rax, %rcx
.L12:
	cmpq	%rcx, %rsp
	je	.L13
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L12
.L13:
	movq	%rdx, %rax
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L14
	orq	$0, -8(%rsp,%rax)
.L14:
	movl	$2147483653, %eax
	movl	$10, %ecx
	xorl	%edx, %edx
	xorl	%r12d, %r12d
	addq	%rax, %rax
	leaq	-96(%rbp), %rdi
	movq	%rsp, -152(%rbp)
	movq	%rax, -76(%rbp)
	movl	%ebx, %eax
	divl	%ecx
	movl	$1, -60(%rbp)
	movl	$0x00000000, -116(%rbp)
	movl	%eax, -68(%rbp)
	movl	%eax, -64(%rbp)
	call	cudaEventCreate@PLT
	leaq	-88(%rbp), %rdi
	call	cudaEventCreate@PLT
	movq	-144(%rbp), %r14
	movq	%r14, %r15
.L15:
	cmpl	%ebx, %r12d
	jge	.L69
	xorl	%ecx, %ecx
.L16:
	movq	%rcx, -160(%rbp)
	call	rand@PLT
	movl	$2, %ecx
	cltd
	idivl	%ecx
	movq	-160(%rbp), %rcx
	movl	%edx, (%r15,%rcx,4)
	incq	%rcx
	cmpl	%ecx, %ebx
	jg	.L16
	incl	%r12d
	addq	%r13, %r15
	jmp	.L15
.L69:
	leal	-1(%rbx), %eax
	movq	-152(%rbp), %rdx
	xorl	%esi, %esi
	leaq	4(,%rax,4), %r8
	xorl	%eax, %eax
.L17:
	cmpl	%ebx, %esi
	jge	.L70
	movq	%rdx, %rdi
	movq	%r8, %rcx
	incl	%esi
	addq	%r13, %rdx
	rep stosb
	jmp	.L17
.L70:
	movq	-136(%rbp), %rsi
	leaq	-112(%rbp), %rdi
	call	cudaMalloc@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L19
	call	cudaGetErrorString@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	movq	-136(%rbp), %rsi
	leaq	-104(%rbp), %rdi
	call	cudaMalloc@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L20
	call	cudaGetErrorString@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L20:
	movq	-112(%rbp), %rdi
	movq	-136(%rbp), %rdx
	movl	$1, %ecx
	movq	-144(%rbp), %rsi
	call	cudaMemcpy@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L21
	call	cudaGetErrorString@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L21:
	movl	%ebx, %ecx
	movl	%ebx, %edx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	$10, %r15d
	call	__printf_chk@PLT
.L22:
	xorl	%r12d, %r12d
.L23:
	movl	(%r14,%r12,4), %edx
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r12
	call	__printf_chk@PLT
	cmpq	$10, %r12
	jne	.L23
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	%r13, %r14
	call	__printf_chk@PLT
	decl	%r15d
	jne	.L22
	movq	-96(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	-72(%rbp), %ecx
	movq	-68(%rbp), %rdi
	xorl	%r9d, %r9d
	movl	$10, -80(%rbp)
	movl	-60(%rbp), %esi
	xorl	%r8d, %r8d
	movq	-80(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	movq	-104(%rbp), %rsi
	movq	-112(%rbp), %rdi
	movl	%ebx, %edx
	call	_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i
.L68:
	movl	$1, %r14d
.L26:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L28
	call	cudaGetErrorString@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L28:
	movq	-88(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	-152(%rbp), %rdi
	movq	-104(%rbp), %rsi
	movl	$2, %ecx
	movq	-136(%rbp), %rdx
	call	cudaMemcpy@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L29
	call	cudaGetErrorString@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L29:
	cmpl	$10, %r14d
	sete	%al
	cmpl	$100, %r14d
	sete	%dl
	orb	%dl, %al
	jne	.L30
	cmpl	$1000, %r14d
	je	.L30
	incl	%r14d
	jmp	.L31
.L30:
	movl	%r14d, %r8d
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movl	$2, %edi
	leaq	.LC9(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	-152(%rbp), %r15
	movl	$10, -144(%rbp)
.L32:
	xorl	%r12d, %r12d
.L33:
	movl	(%r15,%r12,4), %edx
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r12
	call	__printf_chk@PLT
	cmpq	$10, %r12
	jne	.L33
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	addq	%r13, %r15
	call	__printf_chk@PLT
	decl	-144(%rbp)
	jne	.L32
	movq	-88(%rbp), %rdx
	movq	-96(%rbp), %rsi
	leaq	-116(%rbp), %rdi
	incl	%r14d
	call	cudaEventElapsedTime@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	-116(%rbp), %xmm0
	call	__printf_chk@PLT
	cmpl	$1001, %r14d
	je	.L35
.L31:
	movl	$10, -80(%rbp)
	movl	-72(%rbp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-80(%rbp), %rdx
	movq	-68(%rbp), %rdi
	movl	-60(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	-104(%rbp), %rdi
	movl	%ebx, %edx
	movq	%rdi, %rsi
	call	_Z39__device_stub__Z16computeFutureGenPiS_iPiS_i
	jmp	.L26
.L35:
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z16computeFutureGenPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16computeFutureGenPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>

__global__ void computeFutureGen(int* current,int* future,int n){
        int col=threadIdx.x+blockIdx.x*blockDim.x;
        int row=threadIdx.y+blockIdx.y*blockDim.y;
        int index=col+row*n;
        //Computing the number of alive neighbors
        int neighAlive=0;
if(col<n && row<n){     //Computation starts only when the thread is within our matrix row & column limit
        //Different cases have to considered before counting the alive neighbors
        if(col==0 && row==0){   //When current node is at top left corner of the matrix
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index+n];   //Neighbor at the bottom
                neighAlive+=current[index+n+1]; //Neighbor at the bottom right diagonal
        }
        else if(col==0 && row==n-1){    //When current node is at bottom left corner
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n];   //Neighbor directly above
                neighAlive+=current[index-n+1]; //Neighbor at top right diagonal
        }
        else if(col==n-1 && row==0){    //When current node is at top right corner
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+n-1]; //Neighbor at bottom left
                neighAlive+=current[index+n];   //Neighbor exactly below
        }
        else if(col==n-1 && row==n-1){  //When current node is at bottom right corner
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n-1]; //Neighbor at top left diagonally
        }
        else if(row==0 && col>0 && col<n-1){    //When current node is at top wall excluding the corners
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index+n-1]; //Neighbor diagonally left below
                neighAlive+=current[index+n];   //Neighbor exactly below
                neighAlive+=current[index+n+1]; //Neighbor diagonally right below
        }
        else if(row==n-1 && col>0 && col<n-1){  //When current node is on bottom wall excluding the corners
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n+1]; //Neighbor diagonally right on top
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n-1]; //Neighbor diagonally left on top
        }
        else if(col==0 && row>0 && row<n-1){    //When current node is on left wall excluding corners
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n+1]; //Neighbor diagonally right on top
                neighAlive+=current[index+n];   //Neighbor exactly down
                neighAlive+=current[index+n+1]; //Neighbor diagonally right below
        }
        else if(col==n-1 && row>0 && row<n-1){  //When current node is on right wall excluding corners
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n-1]; //Neighbor diagonally left on top
                neighAlive+=current[index+n-1]; //Neighbor diagonally left below
                neighAlive+=current[index+n];   //Neighbor exactly below
        }
        else{   //For all middle elements, within the boundaries described above
                neighAlive+=current[index-1];   //Neighbor to the left
                neighAlive+=current[index+1];   //Neighbor to the right
                neighAlive+=current[index-n-1]; //Neighbor diagonally left on top
                neighAlive+=current[index-n];   //Neighbor exactly above
                neighAlive+=current[index-n+1]; //Neighbor diagonally right on top
                neighAlive+=current[index+n-1]; //Neighbor diagonally left below
                neighAlive+=current[index+n];   //Neighbor exactly below
                neighAlive+=current[index+n+1]; //Neighbor diagonally right below
        }



        //Code block to decide the alive status of a cell based on the number of alive neighbors
        if(current[index]==1 && neighAlive<2)
                future[index]=0;
        else if(current[index]==1 && (neighAlive==2 || neighAlive==3))
                future[index]=1;
        else if(current[index]==1 && neighAlive>3)
                future[index]=0;
        else if(current[index]==0 && neighAlive==3)
                future[index]=1;
        else
                future[index]=0;
}
}


int main(int argc,char** argv){
        int i,j,k;
        int n=0;
        n=atoi(argv[1]);
        int currentGen[n][n];
        int futureGen[n][n];
        dim3 threadsPerBlock(10,10);
        dim3 numBlocks(n/threadsPerBlock.x,n/threadsPerBlock.x);
        int* current;
        int* future;
        float milliseconds=0;
        hipError_t err;
        hipEvent_t start,stop;
        hipEventCreate(&start);
        hipEventCreate(&stop);

        /*Populating the input matrix currentGen with random 0's
        and 1's using rand() method*/
        for(i=0;i<n;i++)
                for(j=0;j<n;j++)
                        currentGen[i][j]=rand()%2;

        //Initializing the futureGen matrix with all 0's
        for(i=0;i<n;i++)
                for(j=0;j<n;j++)
                        futureGen[i][j]=0;

        //Allocating memory for device copy of current generation matrix
        hipMalloc((void **) &current,sizeof(int)*n*n);
        err=hipGetLastError();
        if(err!=hipSuccess)
                printf("\nERROR after hipMalloc of current : %s\n\n",hipGetErrorString(err));

        //Allocating memory for device copy of future generation matrix
        hipMalloc((void **) &future,sizeof(int)*n*n);
         err=hipGetLastError();
        if(err!=hipSuccess)
                printf("\nERROR after hipMalloc of future: %s\n\n",hipGetErrorString(err));


        //Copying current generation matrix from host to device
        hipMemcpy(current,currentGen,sizeof(int)*n*n,hipMemcpyHostToDevice);
        err=hipGetLastError();
        if(err!=hipSuccess)
                printf("\nERROR after hipMemcpy of currentGen to current: %s\n\n",hipGetErrorString(err));


        //Displaying the first 10 rows and columns of currentGen matrix
        printf("\nPrinting the alive state of first 10 rows and columns of %dx%d current generation matrix\n",n,n);
        for(i=0;i<10;i++){
                for(j=0;j<10;j++){
                        printf("%d\t",currentGen[i][j]);
                }
                printf("\n");
        }

        hipEventRecord(start);
        /*Loop for calculating the alive state of the cells after
        10, 100 and 1000 iterations*/
        for(k=1;k<=1000;k++){

        //Calling the kernel
        if(k==1)
                computeFutureGen<<<numBlocks,threadsPerBlock>>>(current,future,n);
        else
                computeFutureGen<<<numBlocks,threadsPerBlock>>>(future,future,n);

        err=hipGetLastError();
        if(err!=hipSuccess)
                printf("\nERROR after kernel call: %s\n\n",hipGetErrorString(err));
        hipEventRecord(stop);

        //Copying the result from device to host
        hipMemcpy(futureGen,future,sizeof(int)*n*n,hipMemcpyDeviceToHost);
        err=hipGetLastError();
        if(err!=hipSuccess)
                printf("\nERROR after hipMemcpy of future to futureGen: %s\n\n",hipGetErrorString(err));


        //Displaying the first 10 rows and columns of futureGen matrix
        //Display only after 10th, 100th and 1000th iteration
        if(k==10 || k==100 || k==1000){
        printf("\nPrinting the alive state of first 10 rows and columns of %dx%d future generation matrix after %d iterations\n",n,n,k);
        for(i=0;i<10;i++){
                for(j=0;j<10;j++){
                        printf("%d\t",futureGen[i][j]);
                }
                printf("\n");
        }
        hipEventElapsedTime(&milliseconds,start,stop);
        printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
        }

        }
        return 0;
}



	.text
	.file	"conwayCuda.hip"
	.globl	_Z31__device_stub__computeFutureGenPiS_i # -- Begin function _Z31__device_stub__computeFutureGenPiS_i
	.type	_Z31__device_stub__computeFutureGenPiS_i,@function
_Z31__device_stub__computeFutureGenPiS_i: # @_Z31__device_stub__computeFutureGenPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16computeFutureGenPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__computeFutureGenPiS_i, .Lfunc_end0-_Z31__device_stub__computeFutureGenPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r12d
	movl	%eax, %ebx
	movq	%rbx, %rax
	imulq	%rbx, %rax
	movq	%rsp, %r15
	leaq	15(,%rax,4), %rax
	andq	$-16, %rax
	subq	%rax, %r15
	movq	%r15, %rsp
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -72(%rbp)                 # 8-byte Spill
	movq	%rcx, %rsp
	movl	$3435973837, %eax               # imm = 0xCCCCCCCD
	movq	%rax, -56(%rbp)                 # 8-byte Spill
	movl	$0, -60(%rbp)
	leaq	-104(%rbp), %rdi
	callq	hipEventCreate
	leaq	-96(%rbp), %rdi
	callq	hipEventCreate
	testl	%r12d, %r12d
	jle	.LBB1_8
# %bb.1:                                # %.lr.ph.preheader
	leaq	(,%rbx,4), %rax
	movq	%rax, -48(%rbp)                 # 8-byte Spill
	xorl	%r14d, %r14d
	movq	%r15, %r13
.LBB1_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
	xorl	%r12d, %r12d
.LBB1_3:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	andl	$-2, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r13,%r12,4)
	incq	%r12
	cmpq	%r12, %rbx
	jne	.LBB1_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r14
	addq	-48(%rbp), %r13                 # 8-byte Folded Reload
	cmpq	%rbx, %r14
	jne	.LBB1_2
# %bb.5:                                # %.preheader111
	testl	%ebx, %ebx
	movq	-48(%rbp), %r13                 # 8-byte Reload
	jle	.LBB1_8
# %bb.6:                                # %.preheader110.lr.ph
	movq	%rbx, %r12
	movq	-72(%rbp), %r14                 # 8-byte Reload
.LBB1_7:                                # %._crit_edge117
                                        # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	xorl	%esi, %esi
	movq	%r13, %rdx
	callq	memset@PLT
	addq	%r13, %r14
	decq	%r12
	jne	.LBB1_7
.LBB1_8:                                # %._crit_edge119
	movq	-56(%rbp), %rax                 # 8-byte Reload
	imulq	%rbx, %rax
	movq	%rax, -56(%rbp)                 # 8-byte Spill
	movslq	%ebx, %rsi
	imulq	%rsi, %rsi
	shlq	$2, %rsi
	leaq	-112(%rbp), %rdi
	movq	%rsi, -48(%rbp)                 # 8-byte Spill
	callq	hipMalloc
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_10
# %bb.9:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_10:
	shrq	$35, -56(%rbp)                  # 8-byte Folded Spill
	leaq	-80(%rbp), %rdi
	movq	-48(%rbp), %rsi                 # 8-byte Reload
	callq	hipMalloc
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_12
# %bb.11:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_12:
	movq	-56(%rbp), %r14                 # 8-byte Reload
	shlq	$32, %r14
	movq	-112(%rbp), %rdi
	movq	%r15, %rsi
	movq	-48(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_14
# %bb.13:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_14:
	addq	%r14, -56(%rbp)                 # 8-byte Folded Spill
	movl	$.L.str.3, %edi
	movl	%ebx, %esi
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, -88(%rbp)                 # 8-byte Spill
	leaq	(,%rbx,4), %r14
	xorl	%r12d, %r12d
.LBB1_15:                               # %.preheader109
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_16 Depth 2
	xorl	%ebx, %ebx
.LBB1_16:                               #   Parent Loop BB1_15 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r15,%rbx,4), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB1_16
# %bb.17:                               #   in Loop: Header=BB1_15 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r12
	addq	%r14, %r15
	cmpq	$10, %r12
	jne	.LBB1_15
# %bb.18:
	movq	-104(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$1, %r13d
	movq	-88(%rbp), %rbx                 # 8-byte Reload
	movq	-72(%rbp), %r15                 # 8-byte Reload
.LBB1_19:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_33 Depth 2
                                        #       Child Loop BB1_34 Depth 3
	movq	-56(%rbp), %rdi                 # 8-byte Reload
	movl	$1, %esi
	movabsq	$42949672970, %rdx              # imm = 0xA0000000A
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	cmpl	$1, %r13d
	jne	.LBB1_22
# %bb.20:                               #   in Loop: Header=BB1_19 Depth=1
	testl	%eax, %eax
	jne	.LBB1_25
# %bb.21:                               #   in Loop: Header=BB1_19 Depth=1
	movq	-112(%rbp), %rdi
	movq	-80(%rbp), %rsi
	jmp	.LBB1_24
.LBB1_22:                               #   in Loop: Header=BB1_19 Depth=1
	testl	%eax, %eax
	jne	.LBB1_25
# %bb.23:                               #   in Loop: Header=BB1_19 Depth=1
	movq	-80(%rbp), %rdi
	movq	%rdi, %rsi
.LBB1_24:                               #   in Loop: Header=BB1_19 Depth=1
	movl	%ebx, %edx
	callq	_Z31__device_stub__computeFutureGenPiS_i
.LBB1_25:                               #   in Loop: Header=BB1_19 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_27
# %bb.26:                               #   in Loop: Header=BB1_19 Depth=1
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.6, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_27:                               #   in Loop: Header=BB1_19 Depth=1
	movq	-96(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-80(%rbp), %rsi
	movq	%r15, %rdi
	movq	-48(%rbp), %rdx                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_29
# %bb.28:                               #   in Loop: Header=BB1_19 Depth=1
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.7, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB1_29:                               #   in Loop: Header=BB1_19 Depth=1
	cmpl	$10, %r13d
	je	.LBB1_32
# %bb.30:                               #   in Loop: Header=BB1_19 Depth=1
	cmpl	$1000, %r13d                    # imm = 0x3E8
	je	.LBB1_32
# %bb.31:                               #   in Loop: Header=BB1_19 Depth=1
	cmpl	$100, %r13d
	jne	.LBB1_37
.LBB1_32:                               #   in Loop: Header=BB1_19 Depth=1
	movl	$.L.str.8, %edi
	movl	%ebx, %esi
	movl	%ebx, %edx
	movl	%r13d, %ecx
	xorl	%eax, %eax
	callq	printf
	xorl	%r12d, %r12d
.LBB1_33:                               # %.preheader
                                        #   Parent Loop BB1_19 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_34 Depth 3
	xorl	%ebx, %ebx
.LBB1_34:                               #   Parent Loop BB1_19 Depth=1
                                        #     Parent Loop BB1_33 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%r15,%rbx,4), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB1_34
# %bb.35:                               #   in Loop: Header=BB1_33 Depth=2
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r12
	addq	%r14, %r15
	cmpq	$10, %r12
	jne	.LBB1_33
# %bb.36:                               #   in Loop: Header=BB1_19 Depth=1
	movq	-104(%rbp), %rsi
	movq	-96(%rbp), %rdx
	leaq	-60(%rbp), %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	-60(%rbp), %xmm0
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	movq	-88(%rbp), %rbx                 # 8-byte Reload
	movq	-72(%rbp), %r15                 # 8-byte Reload
.LBB1_37:                               #   in Loop: Header=BB1_19 Depth=1
	incl	%r13d
	cmpl	$1001, %r13d                    # imm = 0x3E9
	jne	.LBB1_19
# %bb.38:
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16computeFutureGenPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16computeFutureGenPiS_i,@object # @_Z16computeFutureGenPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z16computeFutureGenPiS_i
	.p2align	3, 0x0
_Z16computeFutureGenPiS_i:
	.quad	_Z31__device_stub__computeFutureGenPiS_i
	.size	_Z16computeFutureGenPiS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\nERROR after hipMalloc of current : %s\n\n"
	.size	.L.str, 41

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\nERROR after hipMalloc of future: %s\n\n"
	.size	.L.str.1, 39

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\nERROR after hipMemcpy of currentGen to current: %s\n\n"
	.size	.L.str.2, 54

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"\nPrinting the alive state of first 10 rows and columns of %dx%d current generation matrix\n"
	.size	.L.str.3, 91

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d\t"
	.size	.L.str.4, 4

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nERROR after kernel call: %s\n\n"
	.size	.L.str.6, 31

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\nERROR after hipMemcpy of future to futureGen: %s\n\n"
	.size	.L.str.7, 52

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"\nPrinting the alive state of first 10 rows and columns of %dx%d future generation matrix after %d iterations\n"
	.size	.L.str.8, 110

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Time taken for this computation = %f milliseconds\n\n"
	.size	.L.str.9, 52

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16computeFutureGenPiS_i"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__computeFutureGenPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16computeFutureGenPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16computeFutureGenPiS_i ; -- Begin function _Z16computeFutureGenPiS_i
	.globl	_Z16computeFutureGenPiS_i
	.p2align	8
	.type	_Z16computeFutureGenPiS_i,@function
_Z16computeFutureGenPiS_i:              ; @_Z16computeFutureGenPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
	v_mad_u64_u32 v[6:7], null, s14, s2, v[1:2]
	s_mov_b32 s2, exec_lo
	v_max_i32_e32 v0, v6, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v0
	s_cbranch_execz .LBB0_49
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_or_b32_e32 v2, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, v4, s6, v[6:7]
                                        ; implicit-def: $vgpr7
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB0_31
; %bb.2:
	s_add_i32 s7, s6, -1
	v_cmp_eq_u32_e64 s0, 0, v6
	v_cmp_eq_u32_e64 s1, s7, v4
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, s1
	s_xor_b32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_xor_b32 s12, exec_lo, s3
	s_cbranch_execz .LBB0_28
; %bb.3:
	v_cmp_eq_u32_e64 s2, 0, v4
	v_cmp_eq_u32_e32 vcc_lo, s7, v6
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_xor_b32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s3
	s_xor_b32 s13, exec_lo, s4
	s_cbranch_execz .LBB0_25
; %bb.4:
	s_and_b32 s3, vcc_lo, s1
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, -1
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s4
	s_cbranch_execz .LBB0_22
; %bb.5:
	v_cmp_lt_i32_e64 s3, 0, v6
	v_cmp_gt_i32_e64 s4, s7, v6
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, -1
	s_and_saveexec_b32 s15, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB0_19
; %bb.6:
	s_and_b32 s1, s3, s1
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s4, s1
	s_xor_b32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_xor_b32 s3, exec_lo, s2
	s_cbranch_execz .LBB0_16
; %bb.7:
	v_cmp_lt_i32_e64 s1, 0, v4
	v_cmp_gt_i32_e64 s2, s7, v4
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr2_vgpr3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s4, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_13
; %bb.8:
	v_ashrrev_i32_e32 v1, 31, v0
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, s0, s8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v5, s0, s9, v3, s0
	s_and_b32 s0, vcc_lo, s1
                                        ; implicit-def: $vgpr2_vgpr3
	s_and_b32 s0, s2, s0
	global_load_b32 v6, v[4:5], off offset:-4
	s_xor_b32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_subrev_nc_u32_e32 v2, s6, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[16:17], s[6:7], 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v10, v[4:5], off offset:4
	global_load_b96 v[7:9], v[2:3], off offset:-4
	v_add_co_u32 v2, vcc_lo, v4, s16
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v5, vcc_lo
	global_load_b64 v[4:5], v[2:3], off offset:-4
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(1)
	v_add3_u32 v6, v10, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v6, v8, v9
	s_waitcnt vmcnt(0)
	v_add3_u32 v7, v6, v4, v5
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr4
.LBB0_10:                               ; %Flow260
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_subrev_nc_u32_e32 v2, s6, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[16:17], s[6:7], 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v7, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v4, s16
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[4:5], v[7:8], off offset:-4
	global_load_b32 v7, v[2:3], off offset:-4
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v5, v5, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v5, v4, v7
.LBB0_12:                               ; %Flow261
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_13:                               ; %Flow262
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshl_b64 s[16:17], s[6:7], 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, v4, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v5, vcc_lo
	s_clause 0x2
	global_load_b32 v4, v[4:5], off offset:4
	global_load_b64 v[2:3], v[2:3], off
	global_load_b32 v5, v[8:9], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v2, v2, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v2, v3, v5
	v_add_co_u32 v2, vcc_lo, v8, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v9, vcc_lo
.LBB0_15:                               ; %Flow263
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_16:                               ; %Flow264
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_18
; %bb.17:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v6, v[4:5], off offset:-4
	global_load_b32 v7, v[4:5], off offset:4
	global_load_b64 v[4:5], v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, -4
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v6, v7, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v6, v5, v4
.LBB0_18:                               ; %Flow265
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_19:                               ; %Flow266
	s_and_not1_saveexec_b32 s0, s15
	s_cbranch_execz .LBB0_21
; %bb.20:
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[2:3], s[6:7], 2
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v6, v[2:3], off offset:-4
	global_load_b32 v7, v[2:3], off offset:4
	global_load_b64 v[2:3], v[4:5], off offset:-4
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v6, v7, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v6, v2, v3
	v_add_co_u32 v2, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
.LBB0_21:                               ; %Flow267
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_22:                               ; %Flow268
	s_and_not1_saveexec_b32 s0, s14
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off offset:-4
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, -4
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v5, v4
.LBB0_24:                               ; %Flow269
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_25:                               ; %Flow270
	s_and_not1_saveexec_b32 s0, s13
	s_cbranch_execz .LBB0_27
; %bb.26:
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[2:3], s[6:7], 2
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v4, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off offset:-4
	global_load_b32 v5, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v5, v4
.LBB0_27:                               ; %Flow271
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_28:                               ; %Flow272
	s_and_not1_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_30
; %bb.29:
	v_subrev_nc_u32_e32 v2, s6, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off offset:4
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v5, v4
.LBB0_30:                               ; %Flow273
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_31:                               ; %Flow274
	s_and_not1_saveexec_b32 s0, s5
	s_cbranch_execz .LBB0_33
; %bb.32:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s7, s6, 31
	s_lshl_b64 s[2:3], s[6:7], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, v2, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off offset:4
	global_load_b32 v3, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v3, v2
	v_add_co_u32 v2, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
.LBB0_33:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s0, 1, v3
	v_cmp_eq_u32_e32 vcc_lo, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, 1, v2
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB0_47
; %bb.34:
	v_and_b32_e32 v4, -2, v2
	s_xor_b32 s1, vcc_lo, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 2, v4
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_44
; %bb.35:
	v_cmp_gt_i32_e32 vcc_lo, 4, v2
	s_or_b32 s0, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s4, exec_lo, s1
	s_cbranch_execz .LBB0_41
; %bb.36:
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cmp_ne_u32_e64 s0, 3, v2
	v_add_co_u32 v0, s1, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, s1, s11, v1, s1
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_38
; %bb.37:
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_38:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_40
; %bb.39:
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB0_40:                               ; %Flow253
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_41:                               ; %Flow254
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_43
; %bb.42:
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
.LBB0_43:                               ; %Flow255
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_44:                               ; %Flow256
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_46
; %bb.45:
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB0_46:                               ; %Flow257
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr0_vgpr1
.LBB0_47:                               ; %Flow258
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_49
; %bb.48:
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
.LBB0_49:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16computeFutureGenPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16computeFutureGenPiS_i, .Lfunc_end0-_Z16computeFutureGenPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2016
; NumSgprs: 20
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16computeFutureGenPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z16computeFutureGenPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
