#include <stdio.h>
#include <stdlib.h>

const int INF = 1000000000;
int V = 20010;
void input(char *inFileName);
void output(char *outFileName);

void block_FW(int B);
int ceil(int a, int b);

int n, m;	// Number of vertices, edges
int* host_ptr = NULL;
size_t pitch;

// for device
int* device_ptr = NULL;
__global__ void gpu_phase1(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch);
__global__ void gpu_phase2(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, int pos, size_t pitch);
__global__ void gpu_phase3(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch);

int main(int argc, char* argv[])
{
	input(argv[1]);
	int B = atoi(argv[3]);

	// allocate memory for device
	cudaMallocPitch(&device_ptr, &pitch, V*sizeof(int), V);
	cudaMemcpy2D(device_ptr, pitch, host_ptr, V*sizeof(int), V*sizeof(int), V, cudaMemcpyHostToDevice);

	block_FW(B);

	cudaMemcpy2D(host_ptr, V*sizeof(int), device_ptr, pitch, V*sizeof(int), V, cudaMemcpyDeviceToHost);
	cudaFree(device_ptr);

	output(argv[2]);
	free(host_ptr);

	return 0;
}

void input(char *inFileName)
{
	FILE *infile = fopen(inFileName, "r");
	fscanf(infile, "%d %d", &n, &m);

	// Malloc host memory
	V = n + 10;
	host_ptr = (int*)malloc((size_t)V * V * sizeof(int));

	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
			if (i == j)	host_ptr[i*V+j] = 0;
			else		host_ptr[i*V+j] = INF;
		}
	}

	while (--m >= 0) {
		int a, b, v;
		fscanf(infile, "%d %d %d", &a, &b, &v);
		host_ptr[a*V+b] = v;
	}
    fclose(infile);
}

void output(char *outFileName)
{
	FILE *outfile = fopen(outFileName, "w");
	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
            if (host_ptr[i*V+j] >= INF)
                host_ptr[i*V+j] = INF;
		}
		fwrite(&host_ptr[i*V], sizeof(int), n, outfile);
	}
    fclose(outfile);
}

int ceil(int a, int b)
{
	return (a + b -1)/b;
}

void block_FW(int B)
{
	int round = ceil(n, B);
	dim3 blocks = {1, 1};
	dim3 threads = {(unsigned int)B, (unsigned int)B};

	printf("B: %d, Round: %d\n", B, round);

	for (unsigned int r = 0; r < round; ++r) {
		if (r % 10 == 0)
        	printf("%d %d\n", r, round);
		/* Phase 1*/
		blocks = {1, 1};
		gpu_phase1<<<blocks, threads, B*B*1*sizeof(int)>>>(device_ptr, B,	r,	r,	r, n, pitch/sizeof(int));

		/* Phase 2*/
		if (r > 0) {
			// left
			blocks = {1, r};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,     r,     0, n, 1, pitch/sizeof(int));

			// up
			blocks = {r, 1};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,     0,     r, n, 0, pitch/sizeof(int));
		}
		if (r < round - 1) {
			// right
			blocks = {1, round - r -1};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,     r,  r +1, n, 1, pitch/sizeof(int));

			// down
			blocks = {round - r -1, 1};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,  r +1,     r, n, 0, pitch/sizeof(int));
		}

		/* Phase 3*/
		if (r == 0) {
			// down right
			blocks = {round - r -1, round - r -1};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,  r +1,  r +1, n, pitch/sizeof(int));

		}
		else if (r == round - 1) {
			// upper left
			blocks = {r, r};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,     0,     0, n, pitch/sizeof(int));
		}
		else {
			// down right
			blocks = {round - r -1, round - r -1};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,  r +1,  r +1, n, pitch/sizeof(int));
			// upper left
			blocks = {r, r};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,     0,     0, n, pitch/sizeof(int));
			// upper right
			blocks = {r, round -r -1};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,     0,  r +1, n, pitch/sizeof(int));
			// down left
			blocks = {round - r -1, r};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,  r +1,     0, n, pitch/sizeof(int));
		}
	}
}

extern __shared__ int shared_mem[];
__global__ void gpu_phase1(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch)
{
	int V = pitch;
	int tid = threadIdx.y * B + threadIdx.x;
	int i = (block_start_x + blockIdx.x) * B + threadIdx.x;
	int j = (block_start_y + blockIdx.y) * B + threadIdx.y;

	// need self block - (b_i, b_j)
	shared_mem[tid] = dist[j*V+i];
	__syncthreads();

	for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
		if (i < n && j < n) {
			//===== change new posision by: =====//
			// new_i = origin_i - B * B_i
			// new_j = origin_j - B * B_j
			//===================================//
			int k_new = k - B * Round;
			int i_new = i - B * Round;
			int j_new = j - B * Round;

			int tmp = shared_mem[k_new*B+i_new] + shared_mem[j_new*B+k_new];

			if (tmp < shared_mem[tid]) {
				shared_mem[tid] = tmp;
			}
		}
		__syncthreads();
	}
	dist[j*V+i] = shared_mem[tid];
}

extern __shared__ int shared_mem[];
__global__ void gpu_phase2(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, int pos, size_t pitch)
{
	int V = pitch;
	int tid = threadIdx.y * B + threadIdx.x;
	int b_i = block_start_x + blockIdx.x;
	int b_j = block_start_y + blockIdx.y;
	int i = b_i * B + threadIdx.x;
	int j = b_j * B + threadIdx.y;

	// need self block - (b_i, b_j) & pivot block - (Round, Round)
	shared_mem[tid+B*B] = dist[j*V+i];
	shared_mem[tid] = dist[(Round*B+threadIdx.y)*V+(Round*B+threadIdx.x)];
	__syncthreads();

	for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
		if (i < n && j < n) {
			// up, down
			if (pos == 1) {
				int k_new_1 = k - B * Round;
				int i_new_1 = i - B * Round;

				int k_new_2 = k - B * b_i;
				int j_new_2 = j - B * b_j;

				int tmp = shared_mem[k_new_1*B+i_new_1] + shared_mem[j_new_2*B+k_new_2+B*B];

				if (tmp < shared_mem[tid+B*B]) {
					shared_mem[tid+B*B] = tmp;
				}
			}
			// left, right
			else {
				int k_new_1 = k - B * Round;
				int j_new_1 = j - B * Round;

				int i_new_2 = i - B * b_i;
				int k_new_2 = k - B * b_j;

				int tmp = shared_mem[k_new_2*B+i_new_2+B*B] + shared_mem[j_new_1*B+k_new_1];

				if (tmp < shared_mem[tid+B*B]) {
					shared_mem[tid+B*B] = tmp;
				}
			}
		}
		__syncthreads();
	}
	dist[j*V+i] = shared_mem[tid+B*B];
}

__global__ void gpu_phase3(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch)
{
	int V = pitch;
	int tid = threadIdx.y * B + threadIdx.x;
	int b_i = block_start_x + blockIdx.x;
	int b_j = block_start_y + blockIdx.y;
	int i = b_i * B + threadIdx.x;
	int j = b_j * B + threadIdx.y;

	// need self block - (b_i, b_j) & row / column block
	shared_mem[tid] = dist[j*V+i];
	shared_mem[tid+B*B] = dist[(b_j*B+threadIdx.y)*V+(Round*B+threadIdx.x)];			// left, right
	shared_mem[tid+B*B*2] = dist[(Round*B+threadIdx.y)*V+(b_i*B+threadIdx.x)];			// up  , down
	__syncthreads();

	for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
		if (i < n && j < n) {
			// left, right
			int i_new_1 = i - B * b_i;
			int k_new_1 = k - B * Round;

			// up, down
			int k_new_2 = k - B * Round;
			int j_new_2 = j - B * b_j;

			int tmp = shared_mem[k_new_1*B+i_new_1+B*B*2] + shared_mem[j_new_2*B+k_new_2+B*B];

			if (tmp < shared_mem[tid]) {
				shared_mem[tid] = tmp;
			}
		}
		__syncthreads();
	}
	dist[j*V+i] = shared_mem[tid];
}

	.file	"tmpxft_002cc957_00000000-6_HW4_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"%d %d"
.LC2:
	.string	"%d %d %d"
	.text
	.globl	_Z5inputPc
	.type	_Z5inputPc, @function
_Z5inputPc:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	leaq	m(%rip), %rcx
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	leaq	n(%rip), %rdx
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	n(%rip), %ebp
	leal	10(%rbp), %r12d
	movslq	%r12d, %rdi
	movl	%r12d, V(%rip)
	imulq	%rdi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	xorl	%edi, %edi
	movq	%rax, host_ptr(%rip)
	movl	$1000000000, %r8d
.L3:
	cmpl	%ecx, %ebp
	jle	.L15
	movslq	%esi, %rdx
	leaq	(%rax,%rdx,4), %r9
	xorl	%edx, %edx
.L5:
	cmpl	%edx, %ecx
	movl	%r8d, %r10d
	cmove	%edi, %r10d
	movl	%r10d, (%r9,%rdx,4)
	incq	%rdx
	cmpl	%edx, %ebp
	jg	.L5
	incl	%ecx
	addl	%r12d, %esi
	jmp	.L3
.L15:
	leaq	.LC2(%rip), %rbp
.L7:
	decl	m(%rip)
	js	.L16
	leaq	16(%rsp), %rcx
	leaq	12(%rsp), %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	leaq	20(%rsp), %r8
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	12(%rsp), %eax
	movl	20(%rsp), %ecx
	imull	V(%rip), %eax
	movq	host_ptr(%rip), %rdx
	addl	16(%rsp), %eax
	cltq
	movl	%ecx, (%rdx,%rax,4)
	jmp	.L7
.L16:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z5inputPc, .-_Z5inputPc
	.section	.rodata.str1.1
.LC3:
	.string	"w"
	.text
	.globl	_Z6outputPc
	.type	_Z6outputPc, @function
_Z6outputPc:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	leaq	.LC3(%rip), %rsi
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rdx
	.cfi_def_cfa_offset 32
	call	fopen@PLT
	movq	%rax, %rbx
.L18:
	cmpl	%ebp, n(%rip)
	jle	.L21
	movq	host_ptr(%rip), %rsi
	xorl	%ecx, %ecx
.L22:
	movl	V(%rip), %eax
	movslq	n(%rip), %rdx
	imull	%ebp, %eax
	cmpl	%ecx, %edx
	jle	.L24
	addl	%ecx, %eax
	cltq
	leaq	(%rsi,%rax,4), %rax
	cmpl	$999999999, (%rax)
	jle	.L19
	movl	$1000000000, (%rax)
.L19:
	incl	%ecx
	jmp	.L22
.L24:
	cltq
	movq	%rbx, %rcx
	incl	%ebp
	leaq	(%rsi,%rax,4), %rdi
	movl	$4, %esi
	call	fwrite@PLT
	jmp	.L18
.L21:
	popq	%rax
	.cfi_def_cfa_offset 24
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z6outputPc, .-_Z6outputPc
	.globl	_Z4ceilii
	.type	_Z4ceilii, @function
_Z4ceilii:
.LFB2030:
	.cfi_startproc
	endbr64
	leal	-1(%rsi,%rdi), %eax
	cltd
	idivl	%esi
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z4ceilii, .-_Z4ceilii
	.globl	_Z36__device_stub__Z10gpu_phase1PiiiiiimPiiiiiim
	.type	_Z36__device_stub__Z10gpu_phase1PiiiiiimPiiiiiim, @function
_Z36__device_stub__Z10gpu_phase1PiiiiiimPiiiiiim:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z10gpu_phase1Piiiiiim(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L26:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z36__device_stub__Z10gpu_phase1PiiiiiimPiiiiiim, .-_Z36__device_stub__Z10gpu_phase1PiiiiiimPiiiiiim
	.globl	_Z10gpu_phase1Piiiiiim
	.type	_Z10gpu_phase1Piiiiiim, @function
_Z10gpu_phase1Piiiiiim:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10gpu_phase1PiiiiiimPiiiiiim
	.cfi_endproc
.LFE2057:
	.size	_Z10gpu_phase1Piiiiiim, .-_Z10gpu_phase1Piiiiiim
	.globl	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim
	.type	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim, @function
_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10gpu_phase2Piiiiiiim(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L31:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim, .-_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim
	.globl	_Z10gpu_phase2Piiiiiiim
	.type	_Z10gpu_phase2Piiiiiiim, @function
_Z10gpu_phase2Piiiiiiim:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim
	.cfi_endproc
.LFE2059:
	.size	_Z10gpu_phase2Piiiiiiim, .-_Z10gpu_phase2Piiiiiiim
	.globl	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim
	.type	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim, @function
_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z10gpu_phase3Piiiiiim(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L36:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim, .-_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim
	.globl	_Z10gpu_phase3Piiiiiim
	.type	_Z10gpu_phase3Piiiiiim, @function
_Z10gpu_phase3Piiiiiim:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim
	.cfi_endproc
.LFE2061:
	.size	_Z10gpu_phase3Piiiiiim, .-_Z10gpu_phase3Piiiiiim
	.section	.rodata.str1.1
.LC4:
	.string	"B: %d, Round: %d\n"
.LC5:
	.string	"%d %d\n"
	.text
	.globl	_Z8block_FWi
	.type	_Z8block_FWi, @function
_Z8block_FWi:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC4(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	n(%rip), %eax
	movl	%edi, 52(%rsp)
	addl	%edi, %eax
	movl	%edi, 56(%rsp)
	decl	%eax
	movl	$1, 48(%rsp)
	cltd
	movl	$1, 60(%rsp)
	idivl	%edi
	movl	%edi, %edx
	movl	$2, %edi
	movl	%eax, %ecx
	movl	%eax, %r15d
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%ebx, %eax
	imull	%ebx, %eax
	movslq	%eax, %rdx
	leaq	0(,%rdx,4), %rsi
	leal	(%rax,%rax), %edx
	leal	(%rax,%rax,2), %eax
	movslq	%edx, %rdx
	movq	%rsi, 24(%rsp)
	cltq
	leaq	0(,%rdx,4), %rdi
	salq	$2, %rax
	movq	%rdi, 8(%rsp)
	movq	%rax, (%rsp)
.L42:
	cmpl	%r15d, %ebp
	je	.L69
	movl	$10, %ecx
	movl	%ebp, %eax
	xorl	%edx, %edx
	divl	%ecx
	testl	%edx, %edx
	jne	.L43
	movl	%r15d, %ecx
	movl	%ebp, %edx
	leaq	.LC5(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
.L43:
	movl	60(%rsp), %ecx
	movq	24(%rsp), %r8
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rdi
	movq	52(%rsp), %rdx
	movl	48(%rsp), %esi
	movq	%rdi, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	%rax
	.cfi_def_cfa_offset 136
	movq	pitch(%rip), %rax
	movl	%ebp, %edx
	movl	%ebp, %r8d
	movl	n(%rip), %r9d
	movq	device_ptr(%rip), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	call	_Z36__device_stub__Z10gpu_phase1PiiiiiimPiiiiiim
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L44:
	testl	%ebp, %ebp
	je	.L46
	movl	60(%rsp), %ecx
	movq	8(%rsp), %r8
	movl	%ebp, 44(%rsp)
	xorl	%r9d, %r9d
	movq	52(%rsp), %rdx
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	movq	pitch(%rip), %rax
	xorl	%r8d, %r8d
	movl	%ebp, %ecx
	movl	%ebp, %edx
	movl	n(%rip), %r9d
	movq	device_ptr(%rip), %rdi
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 136
	pushq	$1
	.cfi_def_cfa_offset 144
	call	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim
	popq	%r14
	.cfi_def_cfa_offset 136
	popq	%rax
	.cfi_def_cfa_offset 128
.L47:
	movl	60(%rsp), %ecx
	movq	8(%rsp), %r8
	movl	%ebp, 40(%rsp)
	xorl	%r9d, %r9d
	movl	$1, 44(%rsp)
	movq	52(%rsp), %rdx
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	movq	pitch(%rip), %rax
	movl	%ebp, %r8d
	xorl	%ecx, %ecx
	movl	%ebp, %edx
	movl	n(%rip), %r9d
	movq	device_ptr(%rip), %rdi
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 136
	pushq	$0
	.cfi_def_cfa_offset 144
	call	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim
	popq	%r11
	.cfi_def_cfa_offset 136
	popq	%r13
	.cfi_def_cfa_offset 128
.L46:
	leal	-1(%r15), %r14d
	movl	60(%rsp), %ecx
	movl	48(%rsp), %esi
	leal	1(%rbp), %r13d
	cmpl	%r14d, %r12d
	movq	52(%rsp), %rdx
	jnb	.L49
	movl	%r15d, %eax
	movl	$1, 40(%rsp)
	movq	8(%rsp), %r8
	xorl	%r9d, %r9d
	subl	%r13d, %eax
	movl	%eax, 44(%rsp)
	movq	40(%rsp), %rdi
	movl	%eax, 20(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	movq	pitch(%rip), %rax
	movl	%r13d, %r8d
	movl	%r12d, %ecx
	movl	%r12d, %edx
	movl	n(%rip), %r9d
	movq	device_ptr(%rip), %rdi
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 136
	pushq	$1
	.cfi_def_cfa_offset 144
	call	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim
	popq	%r9
	.cfi_def_cfa_offset 136
	popq	%r10
	.cfi_def_cfa_offset 128
.L50:
	movl	20(%rsp), %eax
	movl	$1, 44(%rsp)
	xorl	%r9d, %r9d
	movl	60(%rsp), %ecx
	movq	8(%rsp), %r8
	movq	52(%rsp), %rdx
	movl	48(%rsp), %esi
	movl	%eax, 40(%rsp)
	movq	40(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	movq	pitch(%rip), %rax
	movl	%r12d, %r8d
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 136
	pushq	$0
	.cfi_def_cfa_offset 144
	call	_Z37__device_stub__Z10gpu_phase2PiiiiiiimPiiiiiiim
	popq	%rdi
	.cfi_def_cfa_offset 136
	popq	%r8
	.cfi_def_cfa_offset 128
	jmp	.L51
.L49:
	testl	%r12d, %r12d
	jne	.L52
.L61:
	movl	60(%rsp), %ecx
	movq	(%rsp), %r8
	movl	%r14d, 40(%rsp)
	xorl	%r9d, %r9d
	movq	52(%rsp), %rdx
	movl	48(%rsp), %esi
	movl	%r14d, 44(%rsp)
	movq	40(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	movq	pitch(%rip), %rax
	movl	n(%rip), %r9d
	pushq	%rsi
	.cfi_remember_state
	.cfi_def_cfa_offset 136
	xorl	%edx, %edx
	movl	$1, %r8d
	movl	$1, %ecx
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	jmp	.L67
.L52:
	.cfi_restore_state
	cmpl	%r12d, %r14d
	jne	.L55
	movl	%ebp, 40(%rsp)
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	movl	%ebp, 44(%rsp)
	movq	40(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	movq	pitch(%rip), %rax
	movl	n(%rip), %r9d
	pushq	%rcx
	.cfi_remember_state
	.cfi_def_cfa_offset 136
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	jmp	.L68
.L51:
	.cfi_restore_state
	testl	%r12d, %r12d
	je	.L61
.L55:
	movl	%r15d, %r14d
	movl	60(%rsp), %ecx
	movq	(%rsp), %r8
	xorl	%r9d, %r9d
	subl	%r13d, %r14d
	movq	52(%rsp), %rdx
	movl	48(%rsp), %esi
	movl	%r14d, 40(%rsp)
	movl	%r14d, 44(%rsp)
	movq	40(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L57
	pushq	%rax
	.cfi_def_cfa_offset 136
	movq	pitch(%rip), %rax
	movl	%r12d, %edx
	movl	%r13d, %r8d
	movl	n(%rip), %r9d
	movq	device_ptr(%rip), %rdi
	movl	%r13d, %ecx
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	call	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L57:
	movl	60(%rsp), %ecx
	movq	(%rsp), %r8
	movl	%ebp, 40(%rsp)
	xorl	%r9d, %r9d
	movq	52(%rsp), %rdx
	movl	48(%rsp), %esi
	movl	%ebp, 44(%rsp)
	movq	40(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L58
	movq	pitch(%rip), %rax
	pushq	%r9
	.cfi_def_cfa_offset 136
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	movl	n(%rip), %r9d
	movq	device_ptr(%rip), %rdi
	movl	%r12d, %edx
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	call	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim
	popq	%r10
	.cfi_def_cfa_offset 136
	popq	%r11
	.cfi_def_cfa_offset 128
.L58:
	movl	60(%rsp), %ecx
	movq	(%rsp), %r8
	movl	%r14d, 44(%rsp)
	xorl	%r9d, %r9d
	movq	52(%rsp), %rdx
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	movq	pitch(%rip), %rax
	pushq	%rsi
	.cfi_def_cfa_offset 136
	movl	%r13d, %r8d
	xorl	%ecx, %ecx
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movl	%r12d, %edx
	movl	%ebx, %esi
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	call	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim
	popq	%rdi
	.cfi_def_cfa_offset 136
	popq	%r8
	.cfi_def_cfa_offset 128
.L59:
	movl	60(%rsp), %ecx
	movq	(%rsp), %r8
	movl	%r14d, 40(%rsp)
	xorl	%r9d, %r9d
	movq	52(%rsp), %rdx
	movl	48(%rsp), %esi
	movl	%ebp, 44(%rsp)
	movq	40(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	movq	pitch(%rip), %rax
	movl	n(%rip), %r9d
	pushq	%rcx
	.cfi_def_cfa_offset 136
	xorl	%r8d, %r8d
	movl	%r13d, %ecx
	shrq	$2, %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
.L68:
	movl	%r12d, %edx
.L67:
	movq	device_ptr(%rip), %rdi
	movl	%ebx, %esi
	call	_Z36__device_stub__Z10gpu_phase3PiiiiiimPiiiiiim
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L54:
	incl	%r12d
	movl	%r13d, %ebp
	jmp	.L42
.L69:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z8block_FWi, .-_Z8block_FWi
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rsi, %rbx
	pushq	%rax
	.cfi_def_cfa_offset 32
	movq	8(%rsi), %rdi
	call	_Z5inputPc
	movq	24(%rbx), %rdi
	call	atoi@PLT
	movslq	V(%rip), %rcx
	leaq	pitch(%rip), %rsi
	leaq	device_ptr(%rip), %rdi
	movl	%eax, %ebp
	leaq	0(,%rcx,4), %rdx
	call	cudaMallocPitch@PLT
	movslq	V(%rip), %r9
	movq	pitch(%rip), %rsi
	pushq	%rdx
	.cfi_def_cfa_offset 40
	movq	device_ptr(%rip), %rdi
	pushq	$1
	.cfi_def_cfa_offset 48
	leaq	0(,%r9,4), %rcx
	movq	host_ptr(%rip), %rdx
	movq	%rcx, %r8
	call	cudaMemcpy2D@PLT
	popq	%rcx
	.cfi_def_cfa_offset 40
	movl	%ebp, %edi
	popq	%rsi
	.cfi_def_cfa_offset 32
	call	_Z8block_FWi
	movslq	V(%rip), %r9
	movq	pitch(%rip), %rcx
	pushq	%rdi
	.cfi_def_cfa_offset 40
	movq	device_ptr(%rip), %rdx
	pushq	$2
	.cfi_def_cfa_offset 48
	leaq	0(,%r9,4), %rsi
	movq	host_ptr(%rip), %rdi
	movq	%rsi, %r8
	call	cudaMemcpy2D@PLT
	movq	device_ptr(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 40
	popq	%r9
	.cfi_def_cfa_offset 32
	call	cudaFree@PLT
	movq	16(%rbx), %rdi
	call	_Z6outputPc
	movq	host_ptr(%rip), %rdi
	call	free@PLT
	popq	%r10
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z10gpu_phase3Piiiiiim"
.LC7:
	.string	"_Z10gpu_phase2Piiiiiiim"
.LC8:
	.string	"_Z10gpu_phase1Piiiiiim"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10gpu_phase3Piiiiiim(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10gpu_phase2Piiiiiiim(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10gpu_phase1Piiiiiim(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	device_ptr
	.bss
	.align 8
	.type	device_ptr, @object
	.size	device_ptr, 8
device_ptr:
	.zero	8
	.globl	pitch
	.align 8
	.type	pitch, @object
	.size	pitch, 8
pitch:
	.zero	8
	.globl	host_ptr
	.align 8
	.type	host_ptr, @object
	.size	host_ptr, 8
host_ptr:
	.zero	8
	.globl	m
	.align 4
	.type	m, @object
	.size	m, 4
m:
	.zero	4
	.globl	n
	.align 4
	.type	n, @object
	.size	n, 4
n:
	.zero	4
	.globl	V
	.data
	.align 4
	.type	V, @object
	.size	V, 4
V:
	.long	20010
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

const int INF = 1000000000;
int V = 20010;
void input(char *inFileName);
void output(char *outFileName);

void block_FW(int B);
int ceil(int a, int b);

int n, m;	// Number of vertices, edges
int* host_ptr = NULL;
size_t pitch;

// for device
int* device_ptr = NULL;
__global__ void gpu_phase1(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch);
__global__ void gpu_phase2(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, int pos, size_t pitch);
__global__ void gpu_phase3(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch);

int main(int argc, char* argv[])
{
	input(argv[1]);
	int B = atoi(argv[3]);

	// allocate memory for device
	hipMallocPitch(&device_ptr, &pitch, V*sizeof(int), V);
	hipMemcpy2D(device_ptr, pitch, host_ptr, V*sizeof(int), V*sizeof(int), V, hipMemcpyHostToDevice);

	block_FW(B);

	hipMemcpy2D(host_ptr, V*sizeof(int), device_ptr, pitch, V*sizeof(int), V, hipMemcpyDeviceToHost);
	hipFree(device_ptr);

	output(argv[2]);
	free(host_ptr);

	return 0;
}

void input(char *inFileName)
{
	FILE *infile = fopen(inFileName, "r");
	fscanf(infile, "%d %d", &n, &m);

	// Malloc host memory
	V = n + 10;
	host_ptr = (int*)malloc((size_t)V * V * sizeof(int));

	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
			if (i == j)	host_ptr[i*V+j] = 0;
			else		host_ptr[i*V+j] = INF;
		}
	}

	while (--m >= 0) {
		int a, b, v;
		fscanf(infile, "%d %d %d", &a, &b, &v);
		host_ptr[a*V+b] = v;
	}
    fclose(infile);
}

void output(char *outFileName)
{
	FILE *outfile = fopen(outFileName, "w");
	for (int i = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j) {
            if (host_ptr[i*V+j] >= INF)
                host_ptr[i*V+j] = INF;
		}
		fwrite(&host_ptr[i*V], sizeof(int), n, outfile);
	}
    fclose(outfile);
}

int ceil(int a, int b)
{
	return (a + b -1)/b;
}

void block_FW(int B)
{
	int round = ceil(n, B);
	dim3 blocks = {1, 1};
	dim3 threads = {(unsigned int)B, (unsigned int)B};

	printf("B: %d, Round: %d\n", B, round);

	for (unsigned int r = 0; r < round; ++r) {
		if (r % 10 == 0)
        	printf("%d %d\n", r, round);
		/* Phase 1*/
		blocks = {1, 1};
		gpu_phase1<<<blocks, threads, B*B*1*sizeof(int)>>>(device_ptr, B,	r,	r,	r, n, pitch/sizeof(int));

		/* Phase 2*/
		if (r > 0) {
			// left
			blocks = {1, r};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,     r,     0, n, 1, pitch/sizeof(int));

			// up
			blocks = {r, 1};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,     0,     r, n, 0, pitch/sizeof(int));
		}
		if (r < round - 1) {
			// right
			blocks = {1, round - r -1};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,     r,  r +1, n, 1, pitch/sizeof(int));

			// down
			blocks = {round - r -1, 1};
			gpu_phase2<<<blocks, threads, B*B*2*sizeof(int)>>>(device_ptr, B, r,  r +1,     r, n, 0, pitch/sizeof(int));
		}

		/* Phase 3*/
		if (r == 0) {
			// down right
			blocks = {round - r -1, round - r -1};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,  r +1,  r +1, n, pitch/sizeof(int));

		}
		else if (r == round - 1) {
			// upper left
			blocks = {r, r};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,     0,     0, n, pitch/sizeof(int));
		}
		else {
			// down right
			blocks = {round - r -1, round - r -1};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,  r +1,  r +1, n, pitch/sizeof(int));
			// upper left
			blocks = {r, r};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,     0,     0, n, pitch/sizeof(int));
			// upper right
			blocks = {r, round -r -1};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,     0,  r +1, n, pitch/sizeof(int));
			// down left
			blocks = {round - r -1, r};
			gpu_phase3<<<blocks, threads, B*B*3*sizeof(int)>>>(device_ptr, B, r,  r +1,     0, n, pitch/sizeof(int));
		}
	}
}

extern __shared__ int shared_mem[];
__global__ void gpu_phase1(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch)
{
	int V = pitch;
	int tid = threadIdx.y * B + threadIdx.x;
	int i = (block_start_x + blockIdx.x) * B + threadIdx.x;
	int j = (block_start_y + blockIdx.y) * B + threadIdx.y;

	// need self block - (b_i, b_j)
	shared_mem[tid] = dist[j*V+i];
	__syncthreads();

	for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
		if (i < n && j < n) {
			//===== change new posision by: =====//
			// new_i = origin_i - B * B_i
			// new_j = origin_j - B * B_j
			//===================================//
			int k_new = k - B * Round;
			int i_new = i - B * Round;
			int j_new = j - B * Round;

			int tmp = shared_mem[k_new*B+i_new] + shared_mem[j_new*B+k_new];

			if (tmp < shared_mem[tid]) {
				shared_mem[tid] = tmp;
			}
		}
		__syncthreads();
	}
	dist[j*V+i] = shared_mem[tid];
}

extern __shared__ int shared_mem[];
__global__ void gpu_phase2(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, int pos, size_t pitch)
{
	int V = pitch;
	int tid = threadIdx.y * B + threadIdx.x;
	int b_i = block_start_x + blockIdx.x;
	int b_j = block_start_y + blockIdx.y;
	int i = b_i * B + threadIdx.x;
	int j = b_j * B + threadIdx.y;

	// need self block - (b_i, b_j) & pivot block - (Round, Round)
	shared_mem[tid+B*B] = dist[j*V+i];
	shared_mem[tid] = dist[(Round*B+threadIdx.y)*V+(Round*B+threadIdx.x)];
	__syncthreads();

	for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
		if (i < n && j < n) {
			// up, down
			if (pos == 1) {
				int k_new_1 = k - B * Round;
				int i_new_1 = i - B * Round;

				int k_new_2 = k - B * b_i;
				int j_new_2 = j - B * b_j;

				int tmp = shared_mem[k_new_1*B+i_new_1] + shared_mem[j_new_2*B+k_new_2+B*B];

				if (tmp < shared_mem[tid+B*B]) {
					shared_mem[tid+B*B] = tmp;
				}
			}
			// left, right
			else {
				int k_new_1 = k - B * Round;
				int j_new_1 = j - B * Round;

				int i_new_2 = i - B * b_i;
				int k_new_2 = k - B * b_j;

				int tmp = shared_mem[k_new_2*B+i_new_2+B*B] + shared_mem[j_new_1*B+k_new_1];

				if (tmp < shared_mem[tid+B*B]) {
					shared_mem[tid+B*B] = tmp;
				}
			}
		}
		__syncthreads();
	}
	dist[j*V+i] = shared_mem[tid+B*B];
}

__global__ void gpu_phase3(int* dist, int B, int Round, int block_start_x, int block_start_y, int n, size_t pitch)
{
	int V = pitch;
	int tid = threadIdx.y * B + threadIdx.x;
	int b_i = block_start_x + blockIdx.x;
	int b_j = block_start_y + blockIdx.y;
	int i = b_i * B + threadIdx.x;
	int j = b_j * B + threadIdx.y;

	// need self block - (b_i, b_j) & row / column block
	shared_mem[tid] = dist[j*V+i];
	shared_mem[tid+B*B] = dist[(b_j*B+threadIdx.y)*V+(Round*B+threadIdx.x)];			// left, right
	shared_mem[tid+B*B*2] = dist[(Round*B+threadIdx.y)*V+(b_i*B+threadIdx.x)];			// up  , down
	__syncthreads();

	for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
		if (i < n && j < n) {
			// left, right
			int i_new_1 = i - B * b_i;
			int k_new_1 = k - B * Round;

			// up, down
			int k_new_2 = k - B * Round;
			int j_new_2 = j - B * b_j;

			int tmp = shared_mem[k_new_1*B+i_new_1+B*B*2] + shared_mem[j_new_2*B+k_new_2+B*B];

			if (tmp < shared_mem[tid]) {
				shared_mem[tid] = tmp;
			}
		}
		__syncthreads();
	}
	dist[j*V+i] = shared_mem[tid];
}

	.text
	.file	"HW4_cuda.hip"
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	_Z5inputPc
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
	movslq	V(%rip), %rcx
	leaq	(,%rcx,4), %rdx
	movl	$device_ptr, %edi
	movl	$pitch, %esi
	callq	hipMallocPitch
	movq	device_ptr(%rip), %rdi
	movq	pitch(%rip), %rsi
	movq	host_ptr(%rip), %rdx
	movslq	V(%rip), %r9
	leaq	(,%r9,4), %rcx
	movl	$1, (%rsp)
	movq	%rcx, %r8
	callq	hipMemcpy2D
	movl	%ebp, %edi
	callq	_Z8block_FWi
	movq	host_ptr(%rip), %rdi
	movslq	V(%rip), %r9
	leaq	(,%r9,4), %rsi
	movq	device_ptr(%rip), %rdx
	movq	pitch(%rip), %rcx
	movl	$2, (%rsp)
	movq	%rsi, %r8
	callq	hipMemcpy2D
	movq	device_ptr(%rip), %rdi
	callq	hipFree
	movq	16(%rbx), %rdi
	callq	_Z6outputPc
	movq	host_ptr(%rip), %rdi
	callq	free
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z5inputPc                      # -- Begin function _Z5inputPc
	.type	_Z5inputPc,@function
_Z5inputPc:                             # @_Z5inputPc
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$n, %edx
	movl	$m, %ecx
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	n(%rip), %r15
	leaq	10(%r15), %r14
	movl	%r14d, V(%rip)
	movq	%r14, %rdi
	imulq	%r14, %rdi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, host_ptr(%rip)
	testq	%r15, %r15
	jle	.LBB1_5
# %bb.1:                                # %.preheader14.lr.ph
	movl	%r15d, %ecx
	movslq	%ecx, %rdx
	leaq	40(,%rdx,4), %rdx
	xorl	%esi, %esi
	movq	%rax, %rdi
.LBB1_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
	movq	%rsi, %r8
	imulq	%r14, %r8
	leaq	(%rax,%r8,4), %r8
	xorl	%r9d, %r9d
.LBB1_3:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%r9, %rsi
	jne	.LBB1_9
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=2
	movl	$0, (%r8,%rsi,4)
	jmp	.LBB1_10
.LBB1_9:                                #   in Loop: Header=BB1_3 Depth=2
	movl	$1000000000, (%rdi,%r9,4)       # imm = 0x3B9ACA00
.LBB1_10:                               #   in Loop: Header=BB1_3 Depth=2
	incq	%r9
	cmpq	%r9, %rcx
	jne	.LBB1_3
# %bb.11:                               # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%rsi
	addq	%rdx, %rdi
	cmpq	%rcx, %rsi
	jne	.LBB1_2
.LBB1_5:                                # %.preheader
	movl	m(%rip), %eax
	leal	-1(%rax), %ecx
	movl	%ecx, m(%rip)
	testl	%eax, %eax
	jle	.LBB1_8
# %bb.6:
	leaq	20(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	12(%rsp), %r12
.LBB1_7:                                # %.lr.ph17
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	movq	%r12, %r8
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	12(%rsp), %eax
	movq	host_ptr(%rip), %rcx
	movslq	20(%rsp), %rdx
	movslq	V(%rip), %rsi
	imulq	%rdx, %rsi
	movslq	16(%rsp), %rdx
	addq	%rsi, %rdx
	movl	%eax, (%rcx,%rdx,4)
	movl	m(%rip), %eax
	leal	-1(%rax), %ecx
	movl	%ecx, m(%rip)
	testl	%eax, %eax
	jg	.LBB1_7
.LBB1_8:                                # %._crit_edge18
	movq	%rbx, %rdi
	callq	fclose
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z5inputPc, .Lfunc_end1-_Z5inputPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z8block_FWi                    # -- Begin function _Z8block_FWi
	.type	_Z8block_FWi,@function
_Z8block_FWi:                           # @_Z8block_FWi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %esi
	movl	n(%rip), %eax
	addl	%esi, %eax
	decl	%eax
	cltd
	idivl	%edi
	movl	%eax, %ebx
	movl	$.L.str.4, %edi
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
                                        # kill: def $esi killed $esi killed $rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, 32(%rsp)                  # 8-byte Spill
	testl	%ebx, %ebx
	je	.LBB2_33
# %bb.1:                                # %.lr.ph
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movl	%ecx, %eax
	leaq	1(%rdx), %rbx
	imulq	%rax, %rbx
	movl	%ecx, %eax
	imull	%eax, %eax
	leaq	(,%rax,4), %rcx
	movq	%rcx, 88(%rsp)                  # 8-byte Spill
	leal	(%rax,%rax), %r13d
	shlq	$2, %r13
	movq	32(%rsp), %rcx                  # 8-byte Reload
	decl	%ecx
	leal	(%rax,%rax,2), %r14d
	shlq	$2, %r14
	leaq	1(%rdx), %rax
	movq	%rcx, %rdx
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	imulq	%rax, %rdx
	movq	%rdx, 56(%rsp)                  # 8-byte Spill
	movl	$1, %ebp
	xorl	%eax, %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	%rcx, 40(%rsp)                  # 8-byte Spill
	movl	%ecx, %r15d
	xorl	%r12d, %r12d
	movq	%r13, 72(%rsp)                  # 8-byte Spill
	movq	%r14, 24(%rsp)                  # 8-byte Spill
.LBB2_2:                                # =>This Inner Loop Header: Depth=1
	movl	%r12d, %eax
	movl	$3435973837, %ecx               # imm = 0xCCCCCCCD
	imulq	%rcx, %rax
	shrq	$35, %rax
	addl	%eax, %eax
	leal	(%rax,%rax,4), %eax
	cmpl	%eax, %r12d
	jne	.LBB2_4
# %bb.3:                                #   in Loop: Header=BB2_2 Depth=1
	movl	$.L.str.5, %edi
	movl	%r12d, %esi
	movq	32(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	xorl	%eax, %eax
	callq	printf
.LBB2_4:                                #   in Loop: Header=BB2_2 Depth=1
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	88(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:                                #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	movl	%r12d, %ecx
	movl	%r12d, %r8d
	callq	_Z25__device_stub__gpu_phase1Piiiiiim
.LBB2_6:                                #   in Loop: Header=BB2_2 Depth=1
	testq	%r12, %r12
	je	.LBB2_11
# %bb.7:                                #   in Loop: Header=BB2_2 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r13, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, 8(%rsp)
	movl	$1, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	movl	%r12d, %ecx
	xorl	%r8d, %r8d
	callq	_Z25__device_stub__gpu_phase2Piiiiiiim
.LBB2_9:                                #   in Loop: Header=BB2_2 Depth=1
	movabsq	$4294967296, %rax               # imm = 0x100000000
	leaq	(%r12,%rax), %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r13, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_11
# %bb.10:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, 8(%rsp)
	movl	$0, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	xorl	%ecx, %ecx
	movl	%r12d, %r8d
	callq	_Z25__device_stub__gpu_phase2Piiiiiiim
.LBB2_11:                               #   in Loop: Header=BB2_2 Depth=1
	movq	%rbp, 96(%rsp)                  # 8-byte Spill
	movq	%rbx, %r14
	movl	%r15d, %ebp
	cmpq	40(%rsp), %r12                  # 8-byte Folded Reload
	jae	.LBB2_16
# %bb.12:                               #   in Loop: Header=BB2_2 Depth=1
	movq	%rbp, %rdi
	shlq	$32, %rdi
	orq	$1, %rdi
	movl	$1, %esi
	movq	%r14, %rbx
	movq	%r14, %rdx
	movl	$1, %ecx
	movq	%r13, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_14
# %bb.13:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	leal	1(%r12), %r8d
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, 8(%rsp)
	movl	$1, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	movl	%r12d, %ecx
	callq	_Z25__device_stub__gpu_phase2Piiiiiiim
.LBB2_14:                               #   in Loop: Header=BB2_2 Depth=1
	movq	%rbp, %rdi
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r13, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_16
# %bb.15:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	leal	1(%r12), %ecx
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, 8(%rsp)
	movl	$0, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	movl	%r12d, %r8d
	callq	_Z25__device_stub__gpu_phase2Piiiiiiim
.LBB2_16:                               #   in Loop: Header=BB2_2 Depth=1
	testq	%r12, %r12
	je	.LBB2_17
# %bb.19:                               #   in Loop: Header=BB2_2 Depth=1
	cmpq	%r12, 40(%rsp)                  # 8-byte Folded Reload
	jne	.LBB2_22
# %bb.20:                               #   in Loop: Header=BB2_2 Depth=1
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r14, %rbx
	movq	%r14, %rdx
	movl	$1, %ecx
	movq	24(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_32
# %bb.21:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movq	40(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	xorl	%ecx, %ecx
	jmp	.LBB2_30
.LBB2_17:                               #   in Loop: Header=BB2_2 Depth=1
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r14, %rbx
	movq	%r14, %rdx
	movl	$1, %ecx
	movq	24(%rsp), %r8                   # 8-byte Reload
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_32
# %bb.18:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%edx, %edx
	movl	$1, %ecx
	movl	$1, %r8d
	jmp	.LBB2_31
.LBB2_22:                               #   in Loop: Header=BB2_2 Depth=1
	movq	%rbp, %rdi
	shlq	$32, %rdi
	orq	%rbp, %rdi
	movl	$1, %esi
	movq	%r14, %rbx
	movq	%r14, %rdx
	movl	$1, %ecx
	movq	24(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_24
# %bb.23:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	leal	1(%r12), %ecx
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	movl	%ecx, %r8d
	callq	_Z25__device_stub__gpu_phase3Piiiiiim
.LBB2_24:                               #   in Loop: Header=BB2_2 Depth=1
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r14, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_26
# %bb.25:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	callq	_Z25__device_stub__gpu_phase3Piiiiiim
.LBB2_26:                               #   in Loop: Header=BB2_2 Depth=1
	movq	%rbp, %rdi
	shlq	$32, %rdi
	addq	%r12, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r14, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_28
# %bb.27:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	leal	1(%r12), %r8d
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
	xorl	%ecx, %ecx
	callq	_Z25__device_stub__gpu_phase3Piiiiiim
.LBB2_28:                               #   in Loop: Header=BB2_2 Depth=1
	addq	64(%rsp), %rbp                  # 8-byte Folded Reload
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r14, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	72(%rsp), %r13                  # 8-byte Reload
	jne	.LBB2_32
# %bb.29:                               #   in Loop: Header=BB2_2 Depth=1
	movq	device_ptr(%rip), %rdi
	leal	1(%r12), %ecx
	movl	n(%rip), %r9d
	movq	pitch(%rip), %rax
	shrq	$2, %rax
	movq	%rax, (%rsp)
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r12d, %edx
.LBB2_30:                               #   in Loop: Header=BB2_2 Depth=1
	xorl	%r8d, %r8d
.LBB2_31:                               #   in Loop: Header=BB2_2 Depth=1
	callq	_Z25__device_stub__gpu_phase3Piiiiiim
.LBB2_32:                               #   in Loop: Header=BB2_2 Depth=1
	incq	%r12
	decl	%r15d
	movabsq	$4294967296, %rax               # imm = 0x100000000
	movq	96(%rsp), %rbp                  # 8-byte Reload
	addq	%rax, %rbp
	addq	%rax, 64(%rsp)                  # 8-byte Folded Spill
	movq	48(%rsp), %rcx                  # 8-byte Reload
	addq	%rax, %rcx
	incq	%rcx
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
	cmpq	%r12, 32(%rsp)                  # 8-byte Folded Reload
	jne	.LBB2_2
.LBB2_33:                               # %._crit_edge
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z8block_FWi, .Lfunc_end2-_Z8block_FWi
	.cfi_endproc
                                        # -- End function
	.globl	_Z6outputPc                     # -- Begin function _Z6outputPc
	.type	_Z6outputPc,@function
_Z6outputPc:                            # @_Z6outputPc
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	n(%rip), %eax
	testl	%eax, %eax
	jle	.LBB3_8
# %bb.1:                                # %.preheader.preheader
	xorl	%r14d, %r14d
.LBB3_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
	movq	host_ptr(%rip), %rcx
	movl	V(%rip), %edx
	testl	%eax, %eax
	jle	.LBB3_7
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB3_2 Depth=1
	xorl	%esi, %esi
.LBB3_4:                                # %.lr.ph
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r14d, %edi
	imull	%edx, %edi
	movslq	%edi, %rdi
	addq	%rsi, %rdi
	cmpl	$1000000000, (%rcx,%rdi,4)      # imm = 0x3B9ACA00
	jl	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=2
	movl	$1000000000, (%rcx,%rdi,4)      # imm = 0x3B9ACA00
	movl	V(%rip), %edx
	movl	n(%rip), %eax
.LBB3_6:                                #   in Loop: Header=BB3_4 Depth=2
	incq	%rsi
	cmpl	%eax, %esi
	jl	.LBB3_4
.LBB3_7:                                # %._crit_edge
                                        #   in Loop: Header=BB3_2 Depth=1
	imull	%r14d, %edx
	movslq	%edx, %rdx
	leaq	(%rcx,%rdx,4), %rdi
	movslq	%eax, %rdx
	movl	$4, %esi
	movq	%rbx, %rcx
	callq	fwrite
	incl	%r14d
	movl	n(%rip), %eax
	cmpl	%eax, %r14d
	jl	.LBB3_2
.LBB3_8:                                # %._crit_edge15
	movq	%rbx, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end3:
	.size	_Z6outputPc, .Lfunc_end3-_Z6outputPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z4ceilii                       # -- Begin function _Z4ceilii
	.type	_Z4ceilii,@function
_Z4ceilii:                              # @_Z4ceilii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	leal	(%rdi,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
	retq
.Lfunc_end4:
	.size	_Z4ceilii, .Lfunc_end4-_Z4ceilii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpu_phase1Piiiiiim # -- Begin function _Z25__device_stub__gpu_phase1Piiiiiim
	.type	_Z25__device_stub__gpu_phase1Piiiiiim,@function
_Z25__device_stub__gpu_phase1Piiiiiim:  # @_Z25__device_stub__gpu_phase1Piiiiiim
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_phase1Piiiiiim, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z25__device_stub__gpu_phase1Piiiiiim, .Lfunc_end5-_Z25__device_stub__gpu_phase1Piiiiiim
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpu_phase2Piiiiiiim # -- Begin function _Z25__device_stub__gpu_phase2Piiiiiiim
	.type	_Z25__device_stub__gpu_phase2Piiiiiiim,@function
_Z25__device_stub__gpu_phase2Piiiiiiim: # @_Z25__device_stub__gpu_phase2Piiiiiiim
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_phase2Piiiiiiim, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z25__device_stub__gpu_phase2Piiiiiiim, .Lfunc_end6-_Z25__device_stub__gpu_phase2Piiiiiiim
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpu_phase3Piiiiiim # -- Begin function _Z25__device_stub__gpu_phase3Piiiiiim
	.type	_Z25__device_stub__gpu_phase3Piiiiiim,@function
_Z25__device_stub__gpu_phase3Piiiiiim:  # @_Z25__device_stub__gpu_phase3Piiiiiim
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_phase3Piiiiiim, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z25__device_stub__gpu_phase3Piiiiiim, .Lfunc_end7-_Z25__device_stub__gpu_phase3Piiiiiim
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_phase1Piiiiiim, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_phase2Piiiiiiim, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_phase3Piiiiiim, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	V,@object                       # @V
	.data
	.globl	V
	.p2align	2, 0x0
V:
	.long	20010                           # 0x4e2a
	.size	V, 4

	.type	n,@object                       # @n
	.bss
	.globl	n
	.p2align	2, 0x0
n:
	.long	0                               # 0x0
	.size	n, 4

	.type	m,@object                       # @m
	.globl	m
	.p2align	2, 0x0
m:
	.long	0                               # 0x0
	.size	m, 4

	.type	host_ptr,@object                # @host_ptr
	.globl	host_ptr
	.p2align	3, 0x0
host_ptr:
	.quad	0
	.size	host_ptr, 8

	.type	pitch,@object                   # @pitch
	.globl	pitch
	.p2align	3, 0x0
pitch:
	.quad	0                               # 0x0
	.size	pitch, 8

	.type	device_ptr,@object              # @device_ptr
	.globl	device_ptr
	.p2align	3, 0x0
device_ptr:
	.quad	0
	.size	device_ptr, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d %d"
	.size	.L.str.1, 6

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d %d %d"
	.size	.L.str.2, 9

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"w"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"B: %d, Round: %d\n"
	.size	.L.str.4, 18

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d %d\n"
	.size	.L.str.5, 7

	.type	_Z10gpu_phase1Piiiiiim,@object  # @_Z10gpu_phase1Piiiiiim
	.section	.rodata,"a",@progbits
	.globl	_Z10gpu_phase1Piiiiiim
	.p2align	3, 0x0
_Z10gpu_phase1Piiiiiim:
	.quad	_Z25__device_stub__gpu_phase1Piiiiiim
	.size	_Z10gpu_phase1Piiiiiim, 8

	.type	_Z10gpu_phase2Piiiiiiim,@object # @_Z10gpu_phase2Piiiiiiim
	.globl	_Z10gpu_phase2Piiiiiiim
	.p2align	3, 0x0
_Z10gpu_phase2Piiiiiiim:
	.quad	_Z25__device_stub__gpu_phase2Piiiiiiim
	.size	_Z10gpu_phase2Piiiiiiim, 8

	.type	_Z10gpu_phase3Piiiiiim,@object  # @_Z10gpu_phase3Piiiiiim
	.globl	_Z10gpu_phase3Piiiiiim
	.p2align	3, 0x0
_Z10gpu_phase3Piiiiiim:
	.quad	_Z25__device_stub__gpu_phase3Piiiiiim
	.size	_Z10gpu_phase3Piiiiiim, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10gpu_phase1Piiiiiim"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10gpu_phase2Piiiiiiim"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10gpu_phase3Piiiiiim"
	.size	.L__unnamed_3, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__gpu_phase1Piiiiiim
	.addrsig_sym _Z25__device_stub__gpu_phase2Piiiiiiim
	.addrsig_sym _Z25__device_stub__gpu_phase3Piiiiiim
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym n
	.addrsig_sym m
	.addrsig_sym pitch
	.addrsig_sym device_ptr
	.addrsig_sym _Z10gpu_phase1Piiiiiim
	.addrsig_sym _Z10gpu_phase2Piiiiiiim
	.addrsig_sym _Z10gpu_phase3Piiiiiim
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10gpu_phase1Piiiiiim  ; -- Begin function _Z10gpu_phase1Piiiiiim
	.globl	_Z10gpu_phase1Piiiiiim
	.p2align	8
	.type	_Z10gpu_phase1Piiiiiim,@function
_Z10gpu_phase1Piiiiiim:                 ; @_Z10gpu_phase1Piiiiiim
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s8, s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_add_i32 s14, s14, s6
	s_add_i32 s15, s15, s7
	v_mad_u64_u32 v[3:4], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[4:5], null, s15, s4, v[6:7]
	s_mul_i32 s1, s5, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, v6, s4, v[2:3]
	v_mad_u64_u32 v[0:1], null, v4, s8, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v5, v7, 2, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_add_i32 s2, s1, s4
	s_min_i32 s2, s2, s0
	global_load_b32 v9, v[0:1], off
	s_cmp_ge_i32 s1, s2
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v9
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_6
; %bb.1:                                ; %.lr.ph
	v_subrev_nc_u32_e32 v6, s1, v4
	v_max_i32_e32 v3, v3, v4
	s_sub_i32 s3, s14, s5
	v_lshlrev_b32_e32 v2, 2, v2
	s_mul_i32 s3, s4, s3
	v_mul_lo_u32 v4, s4, v6
	s_lshl_b32 s3, s3, 2
	v_cmp_gt_i32_e32 vcc_lo, s0, v3
	v_add3_u32 v2, 0, s3, v2
	s_lshl_b32 s3, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_lshl_add_u32 v3, v4, 2, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_load_b32 v4, v2
	ds_load_b32 v6, v3
	ds_load_b32 v7, v5
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s0, v4, v7
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_store_b32 v5, v4
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v2, s3, v2
	v_add_nc_u32_e32 v3, 4, v3
	s_add_i32 s1, s1, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s1, s2
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_6:                                ; %._crit_edge
	ds_load_b32 v2, v5
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_phase1Piiiiiim
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10gpu_phase1Piiiiiim, .Lfunc_end0-_Z10gpu_phase1Piiiiiim
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10gpu_phase2Piiiiiiim ; -- Begin function _Z10gpu_phase2Piiiiiiim
	.globl	_Z10gpu_phase2Piiiiiiim
	.p2align	8
	.type	_Z10gpu_phase2Piiiiiiim,@function
_Z10gpu_phase2Piiiiiiim:                ; @_Z10gpu_phase2Piiiiiiim
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s3, s[0:1], 0x20
	v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_add_i32 s14, s14, s6
	s_add_i32 s15, s15, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s14, s4, v[2:3]
	s_mul_i32 s2, s5, s4
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x18
	v_mad_u64_u32 v[5:6], null, s15, s4, v[3:4]
	v_add_nc_u32_e32 v6, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, v6, s3
	v_mad_u64_u32 v[0:1], null, v5, s3, v[4:5]
	s_add_i32 s3, s2, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v6, s2, v2, v6
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	s_min_i32 s3, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_ge_i32 s2, s3
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mul_i32 s6, s4, s4
	s_clause 0x1
	global_load_b32 v9, v[0:1], off
	global_load_b32 v10, v[6:7], off
	v_mad_u64_u32 v[7:8], null, v3, s4, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, s6, v7
	v_lshl_add_u32 v7, v7, 2, 0
	v_lshl_add_u32 v6, v6, 2, 0
	s_waitcnt vmcnt(1)
	ds_store_b32 v6, v9
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_11
; %bb.1:                                ; %.lr.ph
	s_cmp_lg_u32 s1, 1
	v_add3_u32 v9, s4, s5, v3
	s_cselect_b32 s1, -1, 0
	s_sub_i32 s7, s15, s5
	s_sub_i32 s8, s14, s5
	v_mad_u64_u32 v[7:8], null, s4, s7, v[3:4]
	v_subrev_nc_u32_e32 v3, s14, v9
	v_max_i32_e32 v4, v4, v5
	s_sub_i32 s7, s5, s15
	v_lshl_add_u32 v2, v2, 2, 0
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v5, s4, v7
	v_mul_lo_u32 v7, s4, v3
	s_mul_i32 s6, s6, s7
	v_cmp_gt_i32_e64 s0, s0, v4
	s_lshl_b32 s5, s6, 2
	s_mul_i32 s6, s4, s8
	s_lshl_b32 s4, s4, 2
	s_lshl_b32 s6, s6, 2
	v_lshl_add_u32 v3, v5, 2, 0
	v_lshl_add_u32 v4, v7, 2, 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s7, s0
	s_cbranch_execz .LBB1_10
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	ds_load_b32 v7, v6
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v5, s5, v2
	s_mov_b32 s9, 0
	ds_load_b32 v5, v5
	ds_load_b32 v8, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, v5, v7
	s_and_b32 s8, vcc_lo, exec_lo
	s_branch .LBB1_6
.LBB1_5:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s9, -1
	s_mov_b32 s8, 0
                                        ; implicit-def: $vgpr5
.LBB1_6:                                ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v5, s6, v2
	s_and_not1_b32 s8, s8, exec_lo
	ds_load_b32 v5, v5
	ds_load_b32 v8, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, v5, v7
	s_and_b32 s9, vcc_lo, exec_lo
	s_or_b32 s8, s8, s9
.LBB1_8:                                ; %Flow135
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s8
	s_cbranch_execz .LBB1_10
; %bb.9:                                ; %.sink.split
                                        ;   in Loop: Header=BB1_2 Depth=1
	ds_store_b32 v6, v5
.LBB1_10:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v2, s4, v2
	v_add_nc_u32_e32 v3, 4, v3
	v_add_nc_u32_e32 v4, 4, v4
	s_add_i32 s2, s2, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s2, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
.LBB1_11:                               ; %._crit_edge
	ds_load_b32 v2, v6
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_phase2Piiiiiiim
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10gpu_phase2Piiiiiiim, .Lfunc_end1-_Z10gpu_phase2Piiiiiiim
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 652
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10gpu_phase3Piiiiiim  ; -- Begin function _Z10gpu_phase3Piiiiiim
	.globl	_Z10gpu_phase3Piiiiiim
	.p2align	8
	.type	_Z10gpu_phase3Piiiiiim,@function
_Z10gpu_phase3Piiiiiim:                 ; @_Z10gpu_phase3Piiiiiim
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s3, s[0:1], 0x20
	v_bfe_u32 v2, v0, 10, 10
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x18
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s15, s7
	s_add_i32 s14, s14, s6
	v_mad_u64_u32 v[4:5], null, s15, s4, v[2:3]
	v_and_b32_e32 v3, 0x3ff, v0
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v8, s2, v2
	s_add_i32 s1, s2, s4
	s_min_i32 s1, s1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, s14, s4, v[3:4]
	v_mul_lo_u32 v0, v4, s3
	v_mad_u64_u32 v[6:7], null, v8, s3, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v7, v1 :: v_dual_add_nc_u32 v8, v0, v5
	v_add3_u32 v0, s2, v3, v0
	s_mul_i32 s3, s4, s4
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_lshl_b32 s5, s3, 2
	s_cmp_ge_i32 s2, s1
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_clause 0x2
	global_load_b32 v8, v[0:1], off
	global_load_b32 v9, v[10:11], off
	global_load_b32 v10, v[6:7], off
	v_mad_u64_u32 v[6:7], null, v2, s4, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v6, v6, 2, 0
	v_add_nc_u32_e32 v7, s5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v11, s5, v7
	s_waitcnt vmcnt(2)
	ds_store_b32 v6, v8
	s_waitcnt vmcnt(1)
	ds_store_b32 v7, v9
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_6
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, s4, v2
	v_max_i32_e32 v4, v5, v4
	v_lshlrev_b32_e32 v3, 2, v3
	s_lshl_b32 s3, s3, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v2, s4, v2
	v_cmp_gt_i32_e32 vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v3, 0, s3, v3
	s_lshl_b32 s3, s4, 2
	v_lshl_add_u32 v2, v2, 2, 0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB2_5
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	ds_load_b32 v4, v3
	ds_load_b32 v5, v2
	ds_load_b32 v7, v6
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v4, v5, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s0, v4, v7
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	ds_store_b32 v6, v4
.LBB2_5:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, 4, v2
	v_add_nc_u32_e32 v3, s3, v3
	s_add_i32 s2, s2, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s2, s1
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_2
.LBB2_6:                                ; %._crit_edge
	ds_load_b32 v2, v6
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_phase3Piiiiiim
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10gpu_phase3Piiiiiim, .Lfunc_end2-_Z10gpu_phase3Piiiiiim
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10gpu_phase1Piiiiiim
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10gpu_phase1Piiiiiim.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10gpu_phase2Piiiiiiim
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10gpu_phase2Piiiiiiim.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10gpu_phase3Piiiiiim
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10gpu_phase3Piiiiiim.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
