#include <iostream>
#include <cstdlib>


// GPU kernel without shared memory usage
__global__
void stencilKernel (int arrSize, float *in, float *out, int wArrSize, float *wArr)
{
    int midIndex = blockDim.x * blockIdx.x + threadIdx.x;
    int radius = wArrSize / 2;
    
    float result = 0;
    for (int i = -1 * radius; i <= radius; i++)
    {
        int arrIndex = midIndex + i;
        if (arrIndex >= 0 && arrIndex < arrSize) result += wArr[i + radius] * in[arrIndex];
    }

    if (midIndex >= 0 && midIndex < arrSize) out[midIndex] = result;
}


// GPU kernel with shared memory usage
__global__
void stencilKernelShared (int arrSize, float *in, float *out, int wArrSize, float *wArr)
{
    int midIndex = blockDim.x * blockIdx.x + threadIdx.x;
    int radius = wArrSize / 2;
    
    // Arrange shared memory
    extern __shared__ float sharedMem[];

    float *sh_in = sharedMem;
    float *sh_wArr = &sh_in[blockDim.x + 2 * radius];


    sh_in[threadIdx.x + radius] = in[midIndex];
    if (threadIdx.x < radius) sh_in[threadIdx.x] = (midIndex - radius < 0 ? 0 : in[midIndex - radius]);
    if (threadIdx.x >= blockDim.x - radius) sh_in[threadIdx.x + 2 * radius] = (midIndex + radius >= arrSize ? 0 : in[midIndex + radius]);
    
    float *wArrPtr;
    if (blockDim.x - 2 * radius >= wArrSize)
    {
        if (threadIdx.x >= radius && threadIdx.x < radius + wArrSize) sh_wArr[threadIdx.x - radius] = wArr[threadIdx.x - radius];
        wArrPtr = sh_wArr;
    }
    else
    {
        wArrPtr = wArr;
    }
    
    __syncthreads();
    
    // calculate output
    float result = 0;
    for (int i = -1 * radius; i <= radius; i++)
    {
        result += wArrPtr[i + radius] * sh_in[threadIdx.x + i + radius];
    }
    
    // write output
    if (midIndex >= 0 && midIndex < arrSize) out[midIndex] = result;
}



int main()
{
    int arrSize = 1000000;
    int wArrSize = 15;

    float *in = (float *) malloc(arrSize * sizeof(float));
    float *out = (float *) malloc(arrSize * sizeof(float));
    float *wArr = (float *) malloc(wArrSize * sizeof(float));

    for (int i=0; i<arrSize; i++) in[i] = i % 2;
    for (int i=0; i<wArrSize; i++) wArr[i] = (float) 1 / wArrSize;
    

    float *d_in, *d_out, *d_wArr;
    cudaMalloc(&d_in, arrSize * sizeof(float));
    cudaMalloc(&d_out, arrSize * sizeof(float));
    cudaMalloc(&d_wArr, wArrSize * sizeof(float));

    cudaMemcpy(d_in, in, arrSize * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_wArr, wArr, wArrSize * sizeof(float), cudaMemcpyHostToDevice);


    int nThread = 128;

    //stencilKernel <<< (arrSize + nThread - 1) / nThread, nThread >>> (arrSize, d_in, d_out, wArrSize, d_wArr);

    int radius = wArrSize / 2;
    int sharedMemSize = (wArrSize + nThread + 2 * radius) * sizeof(float);
    stencilKernelShared <<< (arrSize + nThread - 1) / nThread, nThread, sharedMemSize >>> (arrSize, d_in, d_out, wArrSize, d_wArr);


    cudaMemcpy(out, d_out, arrSize * sizeof(float), cudaMemcpyDeviceToHost);

    for (int i=0; i<10; i++)
    {
        std::cout << out[i] << " ";
    }
    std::cout << std::endl;

    cudaFree(d_in);
    cudaFree(d_out);
    cudaFree(d_wArr);
    free(in);
    free(out);
    free(wArr);

    return 0;
}


	.file	"tmpxft_0038c0b3_00000000-6_oneDStencil.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z13stencilKerneliPfS_iS_iPfS_iS_
	.type	_Z39__device_stub__Z13stencilKerneliPfS_iS_iPfS_iS_, @function
_Z39__device_stub__Z13stencilKerneliPfS_iS_iPfS_iS_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13stencilKerneliPfS_iS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z39__device_stub__Z13stencilKerneliPfS_iS_iPfS_iS_, .-_Z39__device_stub__Z13stencilKerneliPfS_iS_iPfS_iS_
	.globl	_Z13stencilKerneliPfS_iS_
	.type	_Z13stencilKerneliPfS_iS_, @function
_Z13stencilKerneliPfS_iS_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z13stencilKerneliPfS_iS_iPfS_iS_
	.cfi_endproc
.LFE3661:
	.size	_Z13stencilKerneliPfS_iS_, .-_Z13stencilKerneliPfS_iS_
	.globl	_Z45__device_stub__Z19stencilKernelSharediPfS_iS_iPfS_iS_
	.type	_Z45__device_stub__Z19stencilKernelSharediPfS_iS_iPfS_iS_, @function
_Z45__device_stub__Z19stencilKernelSharediPfS_iS_iPfS_iS_:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19stencilKernelSharediPfS_iS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z45__device_stub__Z19stencilKernelSharediPfS_iS_iPfS_iS_, .-_Z45__device_stub__Z19stencilKernelSharediPfS_iS_iPfS_iS_
	.globl	_Z19stencilKernelSharediPfS_iS_
	.type	_Z19stencilKernelSharediPfS_iS_, @function
_Z19stencilKernelSharediPfS_iS_:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z19stencilKernelSharediPfS_iS_iPfS_iS_
	.cfi_endproc
.LFE3663:
	.size	_Z19stencilKernelSharediPfS_iS_, .-_Z19stencilKernelSharediPfS_iS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$4000000, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4000000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$60, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L14:
	movl	%eax, %edx
	andl	$1, %edx
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$1000000, %rax
	jne	.L14
	movss	.LC0(%rip), %xmm0
	xorl	%eax, %eax
.L15:
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$15, %rax
	jne	.L15
	leaq	8(%rsp), %rdi
	movl	$4000000, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4000000, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$60, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$4000000, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$60, %edx
	call	cudaMemcpy@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	movl	$628, %r8d
	salq	$7, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294975109, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	24(%rsp), %r8
	movq	16(%rsp), %rdx
	movl	$15, %ecx
	movl	$1000000, %edi
	movq	8(%rsp), %rsi
	call	_Z45__device_stub__Z19stencilKernelSharediPfS_iS_iPfS_iS_
.L16:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%r13d, %r13d
	movl	$4000000, %edx
	leaq	_ZSt4cout(%rip), %r14
	call	cudaMemcpy@PLT
.L17:
	movq	%r14, %rdi
	cvtss2sd	0(%rbp,%r13,4), %xmm0
	incq	%r13
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$1, %edx
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$10, %r13
	jne	.L17
	movq	%r14, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z19stencilKernelSharediPfS_iS_"
.LC3:
	.string	"_Z13stencilKerneliPfS_iS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19stencilKernelSharediPfS_iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13stencilKerneliPfS_iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1032358025
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>


// GPU kernel without shared memory usage
__global__
void stencilKernel (int arrSize, float *in, float *out, int wArrSize, float *wArr)
{
    int midIndex = blockDim.x * blockIdx.x + threadIdx.x;
    int radius = wArrSize / 2;
    
    float result = 0;
    for (int i = -1 * radius; i <= radius; i++)
    {
        int arrIndex = midIndex + i;
        if (arrIndex >= 0 && arrIndex < arrSize) result += wArr[i + radius] * in[arrIndex];
    }

    if (midIndex >= 0 && midIndex < arrSize) out[midIndex] = result;
}


// GPU kernel with shared memory usage
__global__
void stencilKernelShared (int arrSize, float *in, float *out, int wArrSize, float *wArr)
{
    int midIndex = blockDim.x * blockIdx.x + threadIdx.x;
    int radius = wArrSize / 2;
    
    // Arrange shared memory
    extern __shared__ float sharedMem[];

    float *sh_in = sharedMem;
    float *sh_wArr = &sh_in[blockDim.x + 2 * radius];


    sh_in[threadIdx.x + radius] = in[midIndex];
    if (threadIdx.x < radius) sh_in[threadIdx.x] = (midIndex - radius < 0 ? 0 : in[midIndex - radius]);
    if (threadIdx.x >= blockDim.x - radius) sh_in[threadIdx.x + 2 * radius] = (midIndex + radius >= arrSize ? 0 : in[midIndex + radius]);
    
    float *wArrPtr;
    if (blockDim.x - 2 * radius >= wArrSize)
    {
        if (threadIdx.x >= radius && threadIdx.x < radius + wArrSize) sh_wArr[threadIdx.x - radius] = wArr[threadIdx.x - radius];
        wArrPtr = sh_wArr;
    }
    else
    {
        wArrPtr = wArr;
    }
    
    __syncthreads();
    
    // calculate output
    float result = 0;
    for (int i = -1 * radius; i <= radius; i++)
    {
        result += wArrPtr[i + radius] * sh_in[threadIdx.x + i + radius];
    }
    
    // write output
    if (midIndex >= 0 && midIndex < arrSize) out[midIndex] = result;
}



int main()
{
    int arrSize = 1000000;
    int wArrSize = 15;

    float *in = (float *) malloc(arrSize * sizeof(float));
    float *out = (float *) malloc(arrSize * sizeof(float));
    float *wArr = (float *) malloc(wArrSize * sizeof(float));

    for (int i=0; i<arrSize; i++) in[i] = i % 2;
    for (int i=0; i<wArrSize; i++) wArr[i] = (float) 1 / wArrSize;
    

    float *d_in, *d_out, *d_wArr;
    hipMalloc(&d_in, arrSize * sizeof(float));
    hipMalloc(&d_out, arrSize * sizeof(float));
    hipMalloc(&d_wArr, wArrSize * sizeof(float));

    hipMemcpy(d_in, in, arrSize * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_wArr, wArr, wArrSize * sizeof(float), hipMemcpyHostToDevice);


    int nThread = 128;

    //stencilKernel <<< (arrSize + nThread - 1) / nThread, nThread >>> (arrSize, d_in, d_out, wArrSize, d_wArr);

    int radius = wArrSize / 2;
    int sharedMemSize = (wArrSize + nThread + 2 * radius) * sizeof(float);
    stencilKernelShared <<< (arrSize + nThread - 1) / nThread, nThread, sharedMemSize >>> (arrSize, d_in, d_out, wArrSize, d_wArr);


    hipMemcpy(out, d_out, arrSize * sizeof(float), hipMemcpyDeviceToHost);

    for (int i=0; i<10; i++)
    {
        std::cout << out[i] << " ";
    }
    std::cout << std::endl;

    hipFree(d_in);
    hipFree(d_out);
    hipFree(d_wArr);
    free(in);
    free(out);
    free(wArr);

    return 0;
}


	.text
	.file	"oneDStencil.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z28__device_stub__stencilKerneliPfS_iS_ # -- Begin function _Z28__device_stub__stencilKerneliPfS_iS_
	.type	_Z28__device_stub__stencilKerneliPfS_iS_,@function
_Z28__device_stub__stencilKerneliPfS_iS_: # @_Z28__device_stub__stencilKerneliPfS_iS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13stencilKerneliPfS_iS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__stencilKerneliPfS_iS_, .Lfunc_end0-_Z28__device_stub__stencilKerneliPfS_iS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__stencilKernelSharediPfS_iS_ # -- Begin function _Z34__device_stub__stencilKernelSharediPfS_iS_
	.type	_Z34__device_stub__stencilKernelSharediPfS_iS_,@function
_Z34__device_stub__stencilKernelSharediPfS_iS_: # @_Z34__device_stub__stencilKernelSharediPfS_iS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19stencilKernelSharediPfS_iS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z34__device_stub__stencilKernelSharediPfS_iS_, .Lfunc_end1-_Z34__device_stub__stencilKernelSharediPfS_iS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	malloc
	movq	%rax, %rbx
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	malloc
	movq	%rax, %r14
	movl	$60, %edi
	callq	malloc
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, %ecx
	andl	$1, %ecx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$1000000, %rax                  # imm = 0xF4240
	jne	.LBB2_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB2_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$1032358025, (%r15,%rax,4)      # imm = 0x3D888889
	incq	%rax
	cmpq	$15, %rax
	jne	.LBB2_3
# %bb.4:
	leaq	24(%rsp), %r12
	movl	$4000000, %esi                  # imm = 0x3D0900
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4000000, %esi                  # imm = 0x3D0900
	callq	hipMalloc
	leaq	16(%rsp), %r13
	movl	$60, %esi
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$60, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	7685(%rdx), %rdi
	movl	$628, %r8d                      # imm = 0x274
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	16(%rsp), %r8
	movl	$1000000, %edi                  # imm = 0xF4240
	movl	$15, %ecx
	callq	_Z34__device_stub__stencilKernelSharediPfS_iS_
.LBB2_6:
	movq	8(%rsp), %rsi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
.LBB2_7:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r12,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r12
	cmpq	$10, %r12
	jne	.LBB2_7
# %bb.8:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13stencilKerneliPfS_iS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19stencilKernelSharediPfS_iS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13stencilKerneliPfS_iS_,@object # @_Z13stencilKerneliPfS_iS_
	.section	.rodata,"a",@progbits
	.globl	_Z13stencilKerneliPfS_iS_
	.p2align	3, 0x0
_Z13stencilKerneliPfS_iS_:
	.quad	_Z28__device_stub__stencilKerneliPfS_iS_
	.size	_Z13stencilKerneliPfS_iS_, 8

	.type	_Z19stencilKernelSharediPfS_iS_,@object # @_Z19stencilKernelSharediPfS_iS_
	.globl	_Z19stencilKernelSharediPfS_iS_
	.p2align	3, 0x0
_Z19stencilKernelSharediPfS_iS_:
	.quad	_Z34__device_stub__stencilKernelSharediPfS_iS_
	.size	_Z19stencilKernelSharediPfS_iS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" "
	.size	.L.str, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13stencilKerneliPfS_iS_"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z19stencilKernelSharediPfS_iS_"
	.size	.L__unnamed_2, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__stencilKerneliPfS_iS_
	.addrsig_sym _Z34__device_stub__stencilKernelSharediPfS_iS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13stencilKerneliPfS_iS_
	.addrsig_sym _Z19stencilKernelSharediPfS_iS_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13stencilKerneliPfS_iS_ ; -- Begin function _Z13stencilKerneliPfS_iS_
	.globl	_Z13stencilKerneliPfS_iS_
	.p2align	8
	.type	_Z13stencilKerneliPfS_iS_,@function
_Z13stencilKerneliPfS_iS_:              ; @_Z13stencilKerneliPfS_iS_
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s8, s[0:1], 0x18
	s_load_b32 s10, s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_lt_i32 s8, -1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v0, 0
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[2:3], s[0:1], 0x20
	s_lshr_b32 s0, s8, 31
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, 0
	s_add_i32 s8, s8, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s0, s8, 1
	s_mov_b32 s8, 0
	s_abs_i32 s1, s0
	v_subrev_nc_u32_e32 v4, s0, v1
	s_add_i32 s1, s0, s1
	s_add_i32 s1, s1, 1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s8, v4
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_gt_i32_e64 s0, s10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, vcc_lo, s0
	s_and_saveexec_b32 s0, s9
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_lshl_b64 s[12:13], s[8:9], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s12, s2, s12
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_addc_u32 s13, s3, s13
	s_load_b32 s9, s[12:13], 0x0
	global_load_b32 v2, v[5:6], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s9, v2
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, s8
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %Flow44
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	v_cmp_gt_i32_e64 s0, s10, v1
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13stencilKerneliPfS_iS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13stencilKerneliPfS_iS_, .Lfunc_end0-_Z13stencilKerneliPfS_iS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19stencilKernelSharediPfS_iS_ ; -- Begin function _Z19stencilKernelSharediPfS_iS_
	.globl	_Z19stencilKernelSharediPfS_iS_
	.p2align	8
	.type	_Z19stencilKernelSharediPfS_iS_,@function
_Z19stencilKernelSharediPfS_iS_:        ; @_Z19stencilKernelSharediPfS_iS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s10, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x8
	v_lshl_add_u32 v8, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s2, 0xffff
	s_lshr_b32 s2, s10, 31
	v_mad_u64_u32 v[3:4], null, s15, s11, v[0:1]
	s_add_i32 s2, s10, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s8, s2, 1
	v_lshl_add_u32 v9, s8, 2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v2, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s8, v0
	global_load_b32 v6, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v6
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB1_4
; %bb.1:
	v_subrev_nc_u32_e32 v6, s8, v3
	v_mov_b32_e32 v7, 0
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 -1, v6
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, s2, s4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s2, s5, v7, s2
	global_load_b32 v7, v[6:7], off
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v7
.LBB1_4:                                ; %Flow82
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s4, s[0:1], 0x0
	s_sub_i32 s2, s11, s8
	s_mov_b32 s3, exec_lo
	v_cmpx_le_u32_e64 s2, v0
	s_cbranch_execz .LBB1_8
; %bb.5:
	v_add_nc_u32_e32 v6, s8, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s2, s4, v6
	v_mov_b32_e32 v6, 0
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB1_7
; %bb.6:
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[8:9], 2
	v_add_co_u32 v4, s2, v4, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s2, s13, v5, s2
	global_load_b32 v6, v[4:5], off
.LBB1_7:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v4, s8, 2, v9
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v6
.LBB1_8:                                ; %Flow81
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b64 s[0:1], s[0:1], 0x20
	s_lshl_b32 s2, s8, 3
	s_lshl_b32 s3, s11, 2
	s_add_i32 s5, s2, 0
	s_lshl_b32 s9, s8, 1
	s_add_i32 s5, s5, s3
	s_mov_b64 s[2:3], src_shared_base
	s_cmp_lg_u32 s5, -1
	s_cselect_b32 s2, s5, 0
	s_cselect_b32 s3, s3, 0
	s_sub_i32 s9, s11, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_u32 s9, s10
	s_cselect_b32 s9, -1, 0
	s_and_b32 s11, s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s12, s0, s2
	s_cselect_b32 s13, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
	s_or_b32 s9, vcc_lo, s9
	s_xor_b32 s11, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s11
	s_cbranch_execz .LBB1_12
; %bb.9:
	s_add_i32 s11, s8, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s11, v0
	s_and_saveexec_b32 s11, vcc_lo
	s_cbranch_execz .LBB1_11
; %bb.10:
	v_subrev_nc_u32_e32 v4, s8, v0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_lshl_add_u32 v4, v4, 2, s5
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v0, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v0
.LBB1_11:                               ; %Flow80
	s_or_b32 exec_lo, exec_lo, s11
	v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
.LBB1_12:
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v0, 0
	s_cmp_lt_i32 s10, -1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_15
; %bb.13:                               ; %.lr.ph
	s_abs_i32 s0, s8
	v_mov_b32_e32 v0, 0
	s_add_i32 s2, s8, s0
	s_mov_b32 s0, 0
	s_add_i32 s2, s2, 1
.LBB1_14:                               ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[0:1], 2
	s_add_i32 s0, s0, 1
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_cmp_eq_u32 s2, s0
	flat_load_b32 v6, v[6:7]
	ds_load_b32 v7, v8
	v_add_nc_u32_e32 v8, 4, v8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, v6, v7
	s_cbranch_scc0 .LBB1_14
.LBB1_15:                               ; %Flow79
	v_cmp_lt_i32_e32 vcc_lo, -1, v3
	v_cmp_gt_i32_e64 s0, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_17
; %bb.16:
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB1_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19stencilKernelSharediPfS_iS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19stencilKernelSharediPfS_iS_, .Lfunc_end1-_Z19stencilKernelSharediPfS_iS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 740
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13stencilKerneliPfS_iS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13stencilKerneliPfS_iS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19stencilKernelSharediPfS_iS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19stencilKernelSharediPfS_iS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
