
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <chrono>

using namespace std;
using namespace std::chrono;

int SIZE = 50;
const float BLOCK_WIDTH = 8;

void add_matrix(int* , int* , int* , int, char); //Just work with same sizes matrices.
__global__ void add_matrix_kernel(int*, int*, int*, int);
__global__ void add_matrix_row_kernel(int*, int*, int*, int);
__global__ void add_matrix_col_kernel(int*, int*, int*, int);

void mul_matrix_vec(int*, int*, int*, int);
__global__ void mul_matrix_vec_kernel(int*, int*, int*, int);

//void BlockTranspose(int*, int*, int, int);
//__global__ void BlockTransposeKernel(int*, int, int);

void print_matrix(int*, int, int);
void print_vec(int*, int);



int main()
{
	
	int* m_a = new int[SIZE * SIZE];
	int* m_b = new int[SIZE * SIZE];
	int* m_c = new int[SIZE * SIZE];
	int* m_c2 = new int[SIZE * SIZE];
	int* m_c3 = new int[SIZE * SIZE];

	int* vec1 = new int[SIZE];
	int* vec2 = new int[SIZE];

	for (int i = 0; i < SIZE; i++) {
		for (int j = 0; j < SIZE; j++) {
			int pos = (i * SIZE) + j;
			m_a[pos] = i + j;
			m_b[pos] = i * j;
			m_c[pos] = 0;
			m_c2[pos] = 0;
			m_c3[pos] = 0;
		}
	}

	for (int j = 0; j < SIZE; j++) {
		vec1[j] = j;
		vec2[j] = 0;
	}

	/*
	cout << "Vector" << endl;
	print_vec(vec1, SIZE); cout << endl;
	cout << "Matriz" << endl;
	print_matrix(m_a, SIZE, SIZE); cout << endl;
	cout << "Resultado" << endl;
	mul_matrix_vec(m_a, vec1, vec2, SIZE);
	
	print_vec(vec2, SIZE); 
	*/

	//print_matrix(m_a, SIZE, SIZE); cout << endl;
	//print_matrix(m_b, SIZE, SIZE); cout << endl;

	
	high_resolution_clock::time_point t1 = high_resolution_clock::now();
	//BlockTranspose(m_a, m_c, SIZE, SIZE);
	add_matrix(m_a, m_b, m_c, SIZE, 'n');
	high_resolution_clock::time_point t2 = high_resolution_clock::now();
	//print_matrix(m_c, SIZE, SIZE);
	auto duration1 = duration_cast<microseconds>(t2 - t1).count();

	t1 = high_resolution_clock::now();
	add_matrix(m_a, m_b, m_c2, SIZE, 'r');
	t2 = high_resolution_clock::now();
	//print_matrix(m_c, SIZE, SIZE);
	auto duration2 = duration_cast<microseconds>(t2 - t1).count();

	t1 = high_resolution_clock::now();
	add_matrix(m_a, m_b, m_c3, SIZE, 'c');
	t2 = high_resolution_clock::now();
	//print_matrix(m_c, SIZE, SIZE);
	auto duration3 = duration_cast<microseconds>(t2 - t1).count();

	cout << "Normal 1: " << duration1 << endl;
	cout << "Filas 2: " << duration2 << endl;
	cout << "Columnas 3: " << duration3 << endl;
	

	return 0;	
}


void add_matrix(int* a, int* b, int* c, int size, char ans) {
	int total_size = size * size * sizeof(int);

	int* d_a;
	int* d_b;
	int* d_c;

	cudaMalloc( (void**) &d_a, total_size);
	cudaMalloc( (void**) &d_b, total_size);
	cudaMalloc( (void**) &d_c, total_size);

	cudaMemcpy(d_a, a, total_size, cudaMemcpyHostToDevice);
	cudaMemcpy(d_b, b, total_size, cudaMemcpyHostToDevice);

	float block = 16;
	dim3 grid_size(ceil(size/block), ceil(size/block), 1);
	dim3 block_size(block, block, 1);

	switch (ans)
	{
	case 'n':
		add_matrix_kernel <<< grid_size, block_size >>> (d_a, d_b, d_c, size);
		break;
	case 'r':
		add_matrix_row_kernel <<< grid_size, block_size >>> (d_a, d_b, d_c, size);
		break;
	case 'c':
		add_matrix_col_kernel <<< grid_size, block_size >>> (d_a, d_b, d_c, size);
		break;
	default:
		break;
	}
	cudaMemcpy(c, d_c, total_size, cudaMemcpyDeviceToHost);

	cudaFree(d_a);
	cudaFree(d_b);
	cudaFree(d_c);
}

//normal addition;
__global__ void add_matrix_kernel(int* a, int* b, int* c, int size) {
	int gpu_columna = (blockDim.x * blockIdx.x) + threadIdx.x;
	int gpu_fila = (blockDim.y * blockIdx.y) + threadIdx.y;

	if (gpu_columna < size  && gpu_fila < size) {
		int pos = gpu_fila * size + gpu_columna;
		c[pos] = a[pos] + b[pos];
	}
}

//row addition;
__global__ void add_matrix_col_kernel(int* a, int* b, int* c, int size) {
	int gpu_columna = (blockDim.x * blockIdx.x) + threadIdx.x;
	int gpu_fila = (blockDim.y * blockIdx.y) + threadIdx.y;

	if (gpu_fila == 0){
		for (int i = 0; i < size; i++) {
			int pos = (i *  size + gpu_columna);
			c[pos] = a[pos] + b[pos];
		}
	}
}

//col addition;
__global__ void add_matrix_row_kernel(int* a, int* b, int* c, int size) {
	int gpu_columna = (blockDim.x * blockIdx.x) + threadIdx.x;
	int gpu_fila = (blockDim.y * blockIdx.y) + threadIdx.y;

	if (gpu_columna == 0) {
		for (int i = 0; i < size; i++) {
			int pos = (gpu_fila *  size + i);
			c[pos] = a[pos] + b[pos];
		}
	}
}

/*
void BlockTranspose(int* h_mat, int* out_mat, int columnas, int filas) {
	int* d_mat;
	int m_size = columnas * filas * sizeof(int);

	cudaMalloc((void**) &d_mat, m_size);
	cudaMemcpy(d_mat, h_mat, m_size, cudaMemcpyHostToDevice);

	dim3 gridDim(ceil(columnas/BLOCK_WIDTH), ceil(filas/BLOCK_WIDTH), 1);
	dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH, 1);

	BlockTransposeKernel<<< gridDim, blockDim >>>(d_mat, columnas, filas);

	cudaMemcpy(out_mat, d_mat, m_size, cudaMemcpyDeviceToHost);
	
	cudaFree(d_mat);
}
*/


void mul_matrix_vec(int* h_m, int* h_vec_1, int* h_vec_2, int size) {
	int* d_m;
	int* d_vec_1;
	int* d_vec_2;

	int size_mat = size * size * sizeof(int);
	int size_vec = size * sizeof(int);
	
	cudaMalloc((void**) &d_m, size_mat);
	cudaMalloc((void**) &d_vec_1, size_vec);
	cudaMalloc((void**) &d_vec_2, size_vec);

	cudaMemcpy(d_m, h_m, size_mat, cudaMemcpyHostToDevice);
	cudaMemcpy(d_vec_1, h_vec_1, size_vec, cudaMemcpyHostToDevice);

	dim3 gridDim(ceil(size / BLOCK_WIDTH), ceil(size / BLOCK_WIDTH), 1);
	dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH, 1);
	
	mul_matrix_vec_kernel <<< gridDim, blockDim >>> (d_m, d_vec_1, d_vec_2, size);

	cudaMemcpy(h_vec_2, d_vec_2, size_vec, cudaMemcpyDeviceToHost);
	cudaFree(d_m);
	cudaFree(d_vec_1);
	cudaFree(d_vec_2);
}


//execution order vect(x_1, y_1) x mat(x_2, y_2); y_1 == x_2
__global__ void mul_matrix_vec_kernel(int* h_m, int* h_vec_1, int* h_vec_2, int size) {
	int gpu_columna = (blockIdx.x * blockDim.x) + threadIdx.x;
	int gpu_fila = (blockIdx.y * blockDim.y) + threadIdx.y;
	
	if (gpu_fila == 0) {
		h_vec_2[gpu_columna] = 0; //Index for resultant matrix
		for (int i = 0; i < size; i++) { // To descend in matrix
			h_vec_2[gpu_columna] += h_m[i*size + gpu_columna] * h_vec_1[i];
		}
	}
}



void print_matrix(int* a, int s_1, int s_2) {
	for (int i = 0; i < s_1; i++) {
		for (int j = 0; j < s_2; j++) {
			cout << a[i*s_2 + j] << "  ";
		}
		cout << endl;
	}
}

void print_vec(int* a, int s_1) {
	for (int i = 0; i < s_1; i++) {
		cout << a[i] << "  ";
	}
}

	.file	"tmpxft_0037bd50_00000000-6_kernel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3743:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3743:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"  "
	.text
	.globl	_Z12print_matrixPiii
	.type	_Z12print_matrixPiii, @function
_Z12print_matrixPiii:
.LFB3739:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%esi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
.L3:
	cmpl	%r14d, %r13d
	jge	.L2
	movslq	%r12d, %rax
	xorl	%r15d, %r15d
	leaq	0(%rbp,%rax,4), %rcx
.L6:
	cmpl	%r15d, %ebx
	jle	.L9
	movl	(%rcx,%r15,4), %esi
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rcx, 8(%rsp)
	incq	%r15
	call	_ZNSolsEi@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	8(%rsp), %rcx
	jmp	.L6
.L9:
	leaq	_ZSt4cout(%rip), %rdi
	incl	%r13d
	addl	%ebx, %r12d
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	jmp	.L3
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3739:
	.size	_Z12print_matrixPiii, .-_Z12print_matrixPiii
	.globl	_Z9print_vecPii
	.type	_Z9print_vecPii, @function
_Z9print_vecPii:
.LFB3740:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	_ZSt4cout(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 48
.L11:
	cmpl	%ebx, %ebp
	jle	.L14
	movl	(%r12,%rbx,4), %esi
	movq	%r13, %rdi
	incq	%rbx
	call	_ZNSolsEi@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	jmp	.L11
.L14:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3740:
	.size	_Z9print_vecPii, .-_Z9print_vecPii
	.globl	_Z42__device_stub__Z17add_matrix_kernelPiS_S_iPiS_S_i
	.type	_Z42__device_stub__Z17add_matrix_kernelPiS_S_iPiS_S_i, @function
_Z42__device_stub__Z17add_matrix_kernelPiS_S_iPiS_S_i:
.LFB3765:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17add_matrix_kernelPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3765:
	.size	_Z42__device_stub__Z17add_matrix_kernelPiS_S_iPiS_S_i, .-_Z42__device_stub__Z17add_matrix_kernelPiS_S_iPiS_S_i
	.globl	_Z17add_matrix_kernelPiS_S_i
	.type	_Z17add_matrix_kernelPiS_S_i, @function
_Z17add_matrix_kernelPiS_S_i:
.LFB3766:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z17add_matrix_kernelPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3766:
	.size	_Z17add_matrix_kernelPiS_S_i, .-_Z17add_matrix_kernelPiS_S_i
	.globl	_Z46__device_stub__Z21add_matrix_col_kernelPiS_S_iPiS_S_i
	.type	_Z46__device_stub__Z21add_matrix_col_kernelPiS_S_iPiS_S_i, @function
_Z46__device_stub__Z21add_matrix_col_kernelPiS_S_iPiS_S_i:
.LFB3767:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21add_matrix_col_kernelPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L20:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3767:
	.size	_Z46__device_stub__Z21add_matrix_col_kernelPiS_S_iPiS_S_i, .-_Z46__device_stub__Z21add_matrix_col_kernelPiS_S_iPiS_S_i
	.globl	_Z21add_matrix_col_kernelPiS_S_i
	.type	_Z21add_matrix_col_kernelPiS_S_i, @function
_Z21add_matrix_col_kernelPiS_S_i:
.LFB3768:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z21add_matrix_col_kernelPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3768:
	.size	_Z21add_matrix_col_kernelPiS_S_i, .-_Z21add_matrix_col_kernelPiS_S_i
	.globl	_Z46__device_stub__Z21add_matrix_row_kernelPiS_S_iPiS_S_i
	.type	_Z46__device_stub__Z21add_matrix_row_kernelPiS_S_iPiS_S_i, @function
_Z46__device_stub__Z21add_matrix_row_kernelPiS_S_iPiS_S_i:
.LFB3769:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21add_matrix_row_kernelPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L25:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3769:
	.size	_Z46__device_stub__Z21add_matrix_row_kernelPiS_S_iPiS_S_i, .-_Z46__device_stub__Z21add_matrix_row_kernelPiS_S_iPiS_S_i
	.globl	_Z21add_matrix_row_kernelPiS_S_i
	.type	_Z21add_matrix_row_kernelPiS_S_i, @function
_Z21add_matrix_row_kernelPiS_S_i:
.LFB3770:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z21add_matrix_row_kernelPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3770:
	.size	_Z21add_matrix_row_kernelPiS_S_i, .-_Z21add_matrix_row_kernelPiS_S_i
	.globl	_Z10add_matrixPiS_S_ic
	.type	_Z10add_matrixPiS_S_ic, @function
_Z10add_matrixPiS_S_ic:
.LFB3737:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	imull	%ecx, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	sall	$2, %ebx
	leaq	8(%rsp), %rdi
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC1(%rip), %xmm0
	call	ceilf@PLT
	movabsq	$68719476752, %rdx
	cvttss2siq	%xmm0, %rax
	movl	%eax, 32(%rsp)
	movl	%eax, 36(%rsp)
	cmpb	$110, %r12b
	je	.L31
	cmpb	$114, %r12b
	je	.L32
	cmpb	$99, %r12b
	je	.L33
	jmp	.L34
.L31:
	movq	32(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebp, %ecx
	movq	8(%rsp), %rdi
	call	_Z42__device_stub__Z17add_matrix_kernelPiS_S_iPiS_S_i
	jmp	.L34
.L32:
	movq	32(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebp, %ecx
	movq	8(%rsp), %rdi
	call	_Z46__device_stub__Z21add_matrix_row_kernelPiS_S_iPiS_S_i
	jmp	.L34
.L33:
	movq	32(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebp, %ecx
	movq	8(%rsp), %rdi
	call	_Z46__device_stub__Z21add_matrix_col_kernelPiS_S_iPiS_S_i
.L34:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3737:
	.size	_Z10add_matrixPiS_S_ic, .-_Z10add_matrixPiS_S_ic
	.section	.rodata.str1.1
.LC2:
	.string	"Normal 1: "
.LC3:
	.string	"Filas 2: "
.LC4:
	.string	"Columnas 3: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3734:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movabsq	$2305843009213693950, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movl	SIZE(%rip), %edi
	imull	%edi, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	_Znam@PLT
	movl	SIZE(%rip), %edi
	movq	%rax, 8(%rsp)
	imull	%edi, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	_Znam@PLT
	movl	SIZE(%rip), %edi
	movq	%rax, %rbx
	imull	%edi, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	_Znam@PLT
	movl	SIZE(%rip), %edi
	movq	%rax, %r13
	imull	%edi, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	_Znam@PLT
	movl	SIZE(%rip), %edi
	movq	%rax, %r12
	imull	%edi, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	_Znam@PLT
	movslq	SIZE(%rip), %rdi
	cmpq	%rdi, %r15
	jb	.L40
	salq	$2, %rdi
	movq	%rax, %rbp
	call	_Znam@PLT
	movslq	SIZE(%rip), %rdi
	movq	%rax, %r14
	cmpq	%rdi, %r15
	jnb	.L41
.L40:
	call	__cxa_throw_bad_array_new_length@PLT
.L41:
	salq	$2, %rdi
	call	_Znam@PLT
	xorl	%edx, %edx
	xorl	%r9d, %r9d
	movq	%rax, %r10
	movslq	SIZE(%rip), %rax
	movq	%rax, %r8
	salq	$2, %rax
	movq	%rax, 24(%rsp)
	leal	-1(%r8), %eax
	leaq	4(,%rax,4), %rax
	movq	%rax, 16(%rsp)
	xorl	%eax, %eax
.L42:
	cmpl	%r9d, %r8d
	jle	.L49
	movq	%rdx, %rdi
	xorl	%r11d, %r11d
	xorl	%ecx, %ecx
.L43:
	movq	8(%rsp), %rsi
	leal	(%rcx,%r9), %r15d
	incl	%ecx
	movl	%r11d, (%rbx,%rdi)
	addl	%r9d, %r11d
	movl	%r15d, (%rsi,%rdi)
	addq	$4, %rdi
	cmpl	%ecx, %r8d
	jne	.L43
	leaq	0(%rbp,%rdx), %r11
	movq	16(%rsp), %rcx
	incl	%r9d
	movq	%r11, %rdi
	leaq	0(%r13,%rdx), %r11
	rep stosb
	movq	16(%rsp), %rcx
	movq	%r11, %rdi
	leaq	(%r12,%rdx), %r11
	rep stosb
	movq	16(%rsp), %rcx
	movq	%r11, %rdi
	rep stosb
	movq	24(%rsp), %rcx
	addq	%rcx, %rdx
	jmp	.L42
.L49:
	xorl	%eax, %eax
.L45:
	cmpl	%eax, %r8d
	jle	.L50
	xorl	%edx, %edx
	movl	%eax, (%r14,%rax,4)
	movl	%edx, (%r10,%rax,4)
	incq	%rax
	jmp	.L45
.L50:
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	movl	SIZE(%rip), %ecx
	movl	$110, %r8d
	movq	%rax, %r15
	movl	$1000, %r14d
	call	_Z10add_matrixPiS_S_ic
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	subq	%r15, %rax
	cqto
	idivq	%r14
	movq	%rax, %r13
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	SIZE(%rip), %ecx
	movl	$114, %r8d
	movq	%rax, %r15
	call	_Z10add_matrixPiS_S_ic
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	subq	%r15, %rax
	cqto
	idivq	%r14
	movq	%rax, %r12
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	movl	SIZE(%rip), %ecx
	movl	$99, %r8d
	movq	%rax, %r15
	leaq	_ZSt4cout(%rip), %rbp
	call	_Z10add_matrixPiS_S_ic
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	%rbp, %rdi
	leaq	.LC2(%rip), %rsi
	subq	%r15, %rax
	cqto
	idivq	%r14
	movq	%rax, %rbx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	%rbp, %rdi
	leaq	.LC3(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	%rbp, %rdi
	leaq	.LC4(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3734:
	.size	main, .-main
	.text
	.globl	_Z46__device_stub__Z21mul_matrix_vec_kernelPiS_S_iPiS_S_i
	.type	_Z46__device_stub__Z21mul_matrix_vec_kernelPiS_S_iPiS_S_i, @function
_Z46__device_stub__Z21mul_matrix_vec_kernelPiS_S_iPiS_S_i:
.LFB3771:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21mul_matrix_vec_kernelPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L51:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3771:
	.size	_Z46__device_stub__Z21mul_matrix_vec_kernelPiS_S_iPiS_S_i, .-_Z46__device_stub__Z21mul_matrix_vec_kernelPiS_S_iPiS_S_i
	.globl	_Z21mul_matrix_vec_kernelPiS_S_i
	.type	_Z21mul_matrix_vec_kernelPiS_S_i, @function
_Z21mul_matrix_vec_kernelPiS_S_i:
.LFB3772:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z21mul_matrix_vec_kernelPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3772:
	.size	_Z21mul_matrix_vec_kernelPiS_S_i, .-_Z21mul_matrix_vec_kernelPiS_S_i
	.globl	_Z14mul_matrix_vecPiS_S_i
	.type	_Z14mul_matrix_vecPiS_S_i, @function
_Z14mul_matrix_vecPiS_S_i:
.LFB3738:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	imull	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	leal	0(,%rbx,4), %ebp
	sall	$2, %r12d
	movslq	%ebp, %rbp
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movslq	%r12d, %r12
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%r12, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cvtsi2ssl	%ebx, %xmm0
	mulss	.LC5(%rip), %xmm0
	call	ceilf@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttss2siq	%xmm0, %rax
	movl	$1, %esi
	movabsq	$34359738376, %rdx
	movl	%eax, 32(%rsp)
	movl	%eax, 36(%rsp)
	movq	32(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L57
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebx, %ecx
	movq	8(%rsp), %rdi
	call	_Z46__device_stub__Z21mul_matrix_vec_kernelPiS_S_iPiS_S_i
.L57:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3738:
	.size	_Z14mul_matrix_vecPiS_S_i, .-_Z14mul_matrix_vecPiS_S_i
	.section	.rodata.str1.1
.LC6:
	.string	"_Z21mul_matrix_vec_kernelPiS_S_i"
.LC7:
	.string	"_Z21add_matrix_row_kernelPiS_S_i"
.LC8:
	.string	"_Z21add_matrix_col_kernelPiS_S_i"
.LC9:
	.string	"_Z17add_matrix_kernelPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3774:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21mul_matrix_vec_kernelPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21add_matrix_row_kernelPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21add_matrix_col_kernelPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17add_matrix_kernelPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3774:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	SIZE
	.data
	.align 4
	.type	SIZE, @object
	.size	SIZE, 4
SIZE:
	.long	50
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1031798784
	.align 4
.LC5:
	.long	1040187392
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"

#include <iostream>
#include <chrono>

using namespace std;
using namespace std::chrono;

int SIZE = 50;
const float BLOCK_WIDTH = 8;

void add_matrix(int* , int* , int* , int, char); //Just work with same sizes matrices.
__global__ void add_matrix_kernel(int*, int*, int*, int);
__global__ void add_matrix_row_kernel(int*, int*, int*, int);
__global__ void add_matrix_col_kernel(int*, int*, int*, int);

void mul_matrix_vec(int*, int*, int*, int);
__global__ void mul_matrix_vec_kernel(int*, int*, int*, int);

//void BlockTranspose(int*, int*, int, int);
//__global__ void BlockTransposeKernel(int*, int, int);

void print_matrix(int*, int, int);
void print_vec(int*, int);



int main()
{
	
	int* m_a = new int[SIZE * SIZE];
	int* m_b = new int[SIZE * SIZE];
	int* m_c = new int[SIZE * SIZE];
	int* m_c2 = new int[SIZE * SIZE];
	int* m_c3 = new int[SIZE * SIZE];

	int* vec1 = new int[SIZE];
	int* vec2 = new int[SIZE];

	for (int i = 0; i < SIZE; i++) {
		for (int j = 0; j < SIZE; j++) {
			int pos = (i * SIZE) + j;
			m_a[pos] = i + j;
			m_b[pos] = i * j;
			m_c[pos] = 0;
			m_c2[pos] = 0;
			m_c3[pos] = 0;
		}
	}

	for (int j = 0; j < SIZE; j++) {
		vec1[j] = j;
		vec2[j] = 0;
	}

	/*
	cout << "Vector" << endl;
	print_vec(vec1, SIZE); cout << endl;
	cout << "Matriz" << endl;
	print_matrix(m_a, SIZE, SIZE); cout << endl;
	cout << "Resultado" << endl;
	mul_matrix_vec(m_a, vec1, vec2, SIZE);
	
	print_vec(vec2, SIZE); 
	*/

	//print_matrix(m_a, SIZE, SIZE); cout << endl;
	//print_matrix(m_b, SIZE, SIZE); cout << endl;

	
	high_resolution_clock::time_point t1 = high_resolution_clock::now();
	//BlockTranspose(m_a, m_c, SIZE, SIZE);
	add_matrix(m_a, m_b, m_c, SIZE, 'n');
	high_resolution_clock::time_point t2 = high_resolution_clock::now();
	//print_matrix(m_c, SIZE, SIZE);
	auto duration1 = duration_cast<microseconds>(t2 - t1).count();

	t1 = high_resolution_clock::now();
	add_matrix(m_a, m_b, m_c2, SIZE, 'r');
	t2 = high_resolution_clock::now();
	//print_matrix(m_c, SIZE, SIZE);
	auto duration2 = duration_cast<microseconds>(t2 - t1).count();

	t1 = high_resolution_clock::now();
	add_matrix(m_a, m_b, m_c3, SIZE, 'c');
	t2 = high_resolution_clock::now();
	//print_matrix(m_c, SIZE, SIZE);
	auto duration3 = duration_cast<microseconds>(t2 - t1).count();

	cout << "Normal 1: " << duration1 << endl;
	cout << "Filas 2: " << duration2 << endl;
	cout << "Columnas 3: " << duration3 << endl;
	

	return 0;	
}


void add_matrix(int* a, int* b, int* c, int size, char ans) {
	int total_size = size * size * sizeof(int);

	int* d_a;
	int* d_b;
	int* d_c;

	hipMalloc( (void**) &d_a, total_size);
	hipMalloc( (void**) &d_b, total_size);
	hipMalloc( (void**) &d_c, total_size);

	hipMemcpy(d_a, a, total_size, hipMemcpyHostToDevice);
	hipMemcpy(d_b, b, total_size, hipMemcpyHostToDevice);

	float block = 16;
	dim3 grid_size(ceil(size/block), ceil(size/block), 1);
	dim3 block_size(block, block, 1);

	switch (ans)
	{
	case 'n':
		add_matrix_kernel <<< grid_size, block_size >>> (d_a, d_b, d_c, size);
		break;
	case 'r':
		add_matrix_row_kernel <<< grid_size, block_size >>> (d_a, d_b, d_c, size);
		break;
	case 'c':
		add_matrix_col_kernel <<< grid_size, block_size >>> (d_a, d_b, d_c, size);
		break;
	default:
		break;
	}
	hipMemcpy(c, d_c, total_size, hipMemcpyDeviceToHost);

	hipFree(d_a);
	hipFree(d_b);
	hipFree(d_c);
}

//normal addition;
__global__ void add_matrix_kernel(int* a, int* b, int* c, int size) {
	int gpu_columna = (blockDim.x * blockIdx.x) + threadIdx.x;
	int gpu_fila = (blockDim.y * blockIdx.y) + threadIdx.y;

	if (gpu_columna < size  && gpu_fila < size) {
		int pos = gpu_fila * size + gpu_columna;
		c[pos] = a[pos] + b[pos];
	}
}

//row addition;
__global__ void add_matrix_col_kernel(int* a, int* b, int* c, int size) {
	int gpu_columna = (blockDim.x * blockIdx.x) + threadIdx.x;
	int gpu_fila = (blockDim.y * blockIdx.y) + threadIdx.y;

	if (gpu_fila == 0){
		for (int i = 0; i < size; i++) {
			int pos = (i *  size + gpu_columna);
			c[pos] = a[pos] + b[pos];
		}
	}
}

//col addition;
__global__ void add_matrix_row_kernel(int* a, int* b, int* c, int size) {
	int gpu_columna = (blockDim.x * blockIdx.x) + threadIdx.x;
	int gpu_fila = (blockDim.y * blockIdx.y) + threadIdx.y;

	if (gpu_columna == 0) {
		for (int i = 0; i < size; i++) {
			int pos = (gpu_fila *  size + i);
			c[pos] = a[pos] + b[pos];
		}
	}
}

/*
void BlockTranspose(int* h_mat, int* out_mat, int columnas, int filas) {
	int* d_mat;
	int m_size = columnas * filas * sizeof(int);

	cudaMalloc((void**) &d_mat, m_size);
	cudaMemcpy(d_mat, h_mat, m_size, cudaMemcpyHostToDevice);

	dim3 gridDim(ceil(columnas/BLOCK_WIDTH), ceil(filas/BLOCK_WIDTH), 1);
	dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH, 1);

	BlockTransposeKernel<<< gridDim, blockDim >>>(d_mat, columnas, filas);

	cudaMemcpy(out_mat, d_mat, m_size, cudaMemcpyDeviceToHost);
	
	cudaFree(d_mat);
}
*/


void mul_matrix_vec(int* h_m, int* h_vec_1, int* h_vec_2, int size) {
	int* d_m;
	int* d_vec_1;
	int* d_vec_2;

	int size_mat = size * size * sizeof(int);
	int size_vec = size * sizeof(int);
	
	hipMalloc((void**) &d_m, size_mat);
	hipMalloc((void**) &d_vec_1, size_vec);
	hipMalloc((void**) &d_vec_2, size_vec);

	hipMemcpy(d_m, h_m, size_mat, hipMemcpyHostToDevice);
	hipMemcpy(d_vec_1, h_vec_1, size_vec, hipMemcpyHostToDevice);

	dim3 gridDim(ceil(size / BLOCK_WIDTH), ceil(size / BLOCK_WIDTH), 1);
	dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH, 1);
	
	mul_matrix_vec_kernel <<< gridDim, blockDim >>> (d_m, d_vec_1, d_vec_2, size);

	hipMemcpy(h_vec_2, d_vec_2, size_vec, hipMemcpyDeviceToHost);
	hipFree(d_m);
	hipFree(d_vec_1);
	hipFree(d_vec_2);
}


//execution order vect(x_1, y_1) x mat(x_2, y_2); y_1 == x_2
__global__ void mul_matrix_vec_kernel(int* h_m, int* h_vec_1, int* h_vec_2, int size) {
	int gpu_columna = (blockIdx.x * blockDim.x) + threadIdx.x;
	int gpu_fila = (blockIdx.y * blockDim.y) + threadIdx.y;
	
	if (gpu_fila == 0) {
		h_vec_2[gpu_columna] = 0; //Index for resultant matrix
		for (int i = 0; i < size; i++) { // To descend in matrix
			h_vec_2[gpu_columna] += h_m[i*size + gpu_columna] * h_vec_1[i];
		}
	}
}



void print_matrix(int* a, int s_1, int s_2) {
	for (int i = 0; i < s_1; i++) {
		for (int j = 0; j < s_2; j++) {
			cout << a[i*s_2 + j] << "  ";
		}
		cout << endl;
	}
}

void print_vec(int* a, int s_1) {
	for (int i = 0; i < s_1; i++) {
		cout << a[i] << "  ";
	}
}

	.text
	.file	"kernel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	SIZE(%rip), %r15d
	movl	%r15d, %ebx
	imull	%ebx, %ebx
	shlq	$2, %rbx
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	testl	%r15d, %r15d
	jle	.LBB0_5
# %bb.1:                                # %.preheader60.lr.ph
	leaq	(,%r15,4), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
	movq	48(%rsp), %rbx                  # 8-byte Reload
.LBB0_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_3 Depth 2
	movl	%r12d, %eax
	movq	32(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbp
	movq	40(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %r14
	movl	%r15d, %eax
	imull	%r13d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %rdi
	movq	16(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rcx
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movq	24(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	memset@PLT
	movq	56(%rsp), %rdi                  # 8-byte Reload
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	memset@PLT
	movq	64(%rsp), %rdi                  # 8-byte Reload
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	memset@PLT
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB0_3:                                #   Parent Loop BB0_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rcx,%r13), %edx
	movl	%edx, (%r14,%rcx,4)
	movl	%eax, (%rbp,%rcx,4)
	incq	%rcx
	addl	%r13d, %eax
	cmpq	%rcx, %r15
	jne	.LBB0_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r13
	addl	%r15d, %r12d
	cmpq	%r15, %r13
	jne	.LBB0_2
.LBB0_5:                                # %.preheader
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %rbx
	movl	SIZE(%rip), %ecx
	movq	40(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movq	32(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rsi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movl	$110, %r8d
	callq	_Z10add_matrixPiS_S_ic
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	subq	%rbx, %rax
	movabsq	$2361183241434822607, %r14      # imm = 0x20C49BA5E353F7CF
	imulq	%r14
	movq	%rdx, %r13
	shrq	$63, %r13
	sarq	$7, %rdx
	addq	%rdx, %r13
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %rbx
	movl	SIZE(%rip), %ecx
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$114, %r8d
	callq	_Z10add_matrixPiS_S_ic
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	subq	%rbx, %rax
	imulq	%r14
	movq	%rdx, %r12
	shrq	$63, %r12
	sarq	$7, %rdx
	addq	%rdx, %r12
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %rbx
	movl	SIZE(%rip), %ecx
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$99, %r8d
	callq	_Z10add_matrixPiS_S_ic
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	subq	%rbx, %rax
	imulq	%r14
	movq	%rdx, %rbx
	shrq	$63, %rbx
	sarq	$7, %rdx
	addq	%rdx, %rbx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$10, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%r13, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%r12, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z10add_matrixPiS_S_ic
.LCPI1_0:
	.long	0x3d800000                      # float 0.0625
	.text
	.globl	_Z10add_matrixPiS_S_ic
	.type	_Z10add_matrixPiS_S_ic,@function
_Z10add_matrixPiS_S_ic:                 # @_Z10add_matrixPiS_S_ic
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r15d
	movl	%ecx, %ebx
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rsi, 24(%rsp)                  # 8-byte Spill
	movq	%rdi, %r13
	movl	%ecx, %eax
	imull	%ecx, %eax
	shll	$2, %eax
	movslq	%eax, %r14
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2ss	%ebx, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rdi
	movl	%edi, %eax
	shlq	$32, %rdi
	orq	%rax, %rdi
	cmpl	$99, %r15d
	je	.LBB1_7
# %bb.1:
	cmpl	$114, %r15d
	je	.LBB1_5
# %bb.2:
	cmpl	$110, %r15d
	jne	.LBB1_9
# %bb.3:
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.4:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z32__device_stub__add_matrix_kernelPiS_S_i
	jmp	.LBB1_9
.LBB1_5:
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.6:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z36__device_stub__add_matrix_row_kernelPiS_S_i
	jmp	.LBB1_9
.LBB1_7:
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.8:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z36__device_stub__add_matrix_col_kernelPiS_S_i
.LBB1_9:
	movq	(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z10add_matrixPiS_S_ic, .Lfunc_end1-_Z10add_matrixPiS_S_ic
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__add_matrix_kernelPiS_S_i # -- Begin function _Z32__device_stub__add_matrix_kernelPiS_S_i
	.type	_Z32__device_stub__add_matrix_kernelPiS_S_i,@function
_Z32__device_stub__add_matrix_kernelPiS_S_i: # @_Z32__device_stub__add_matrix_kernelPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17add_matrix_kernelPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__add_matrix_kernelPiS_S_i, .Lfunc_end2-_Z32__device_stub__add_matrix_kernelPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__add_matrix_row_kernelPiS_S_i # -- Begin function _Z36__device_stub__add_matrix_row_kernelPiS_S_i
	.type	_Z36__device_stub__add_matrix_row_kernelPiS_S_i,@function
_Z36__device_stub__add_matrix_row_kernelPiS_S_i: # @_Z36__device_stub__add_matrix_row_kernelPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21add_matrix_row_kernelPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z36__device_stub__add_matrix_row_kernelPiS_S_i, .Lfunc_end3-_Z36__device_stub__add_matrix_row_kernelPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__add_matrix_col_kernelPiS_S_i # -- Begin function _Z36__device_stub__add_matrix_col_kernelPiS_S_i
	.type	_Z36__device_stub__add_matrix_col_kernelPiS_S_i,@function
_Z36__device_stub__add_matrix_col_kernelPiS_S_i: # @_Z36__device_stub__add_matrix_col_kernelPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21add_matrix_col_kernelPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z36__device_stub__add_matrix_col_kernelPiS_S_i, .Lfunc_end4-_Z36__device_stub__add_matrix_col_kernelPiS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z14mul_matrix_vecPiS_S_i
.LCPI5_0:
	.long	0x3e000000                      # float 0.125
	.text
	.globl	_Z14mul_matrix_vecPiS_S_i
	.type	_Z14mul_matrix_vecPiS_S_i,@function
_Z14mul_matrix_vecPiS_S_i:              # @_Z14mul_matrix_vecPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r14d
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rsi, 24(%rsp)                  # 8-byte Spill
	movq	%rdi, %r13
	leal	(,%r14,4), %r15d
	movl	%r15d, %eax
	imull	%ecx, %eax
	movslq	%eax, %rbp
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movslq	%r15d, %r15
	leaq	8(%rsp), %r12
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2ss	%r14d, %xmm0
	mulss	.LCPI5_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rdi
	movl	%edi, %eax
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r14d, %ecx
	callq	_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i
.LBB5_2:
	movq	(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z14mul_matrix_vecPiS_S_i, .Lfunc_end5-_Z14mul_matrix_vecPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i # -- Begin function _Z36__device_stub__mul_matrix_vec_kernelPiS_S_i
	.type	_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i,@function
_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i: # @_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21mul_matrix_vec_kernelPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i, .Lfunc_end6-_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z12print_matrixPiii            # -- Begin function _Z12print_matrixPiii
	.type	_Z12print_matrixPiii,@function
_Z12print_matrixPiii:                   # @_Z12print_matrixPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	testl	%esi, %esi
	jle	.LBB7_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%edx, %ebx
	movl	%esi, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%edx, %r12d
	xorl	%r13d, %r13d
	xorl	%ebp, %ebp
.LBB7_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB7_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB7_2 Depth=1
	movl	%r13d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %r14
	xorl	%r15d, %r15d
.LBB7_4:                                #   Parent Loop BB7_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r14,%r15,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB7_4
.LBB7_5:                                # %._crit_edge
                                        #   in Loop: Header=BB7_2 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	movl	$_ZSt4cout, %eax
	addq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%rbp
	addl	%ebx, %r13d
	cmpq	16(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB7_2
.LBB7_6:                                # %._crit_edge13
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z12print_matrixPiii, .Lfunc_end7-_Z12print_matrixPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9print_vecPii                 # -- Begin function _Z9print_vecPii
	.type	_Z9print_vecPii,@function
_Z9print_vecPii:                        # @_Z9print_vecPii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB8_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB8_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB8_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB8_4:                                # %._crit_edge
	retq
.Lfunc_end8:
	.size	_Z9print_vecPii, .Lfunc_end8-_Z9print_vecPii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17add_matrix_kernelPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21add_matrix_col_kernelPiS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21add_matrix_row_kernelPiS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21mul_matrix_vec_kernelPiS_S_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	SIZE,@object                    # @SIZE
	.data
	.globl	SIZE
	.p2align	2, 0x0
SIZE:
	.long	50                              # 0x32
	.size	SIZE, 4

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Normal 1: "
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Filas 2: "
	.size	.L.str.1, 10

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Columnas 3: "
	.size	.L.str.2, 13

	.type	_Z17add_matrix_kernelPiS_S_i,@object # @_Z17add_matrix_kernelPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z17add_matrix_kernelPiS_S_i
	.p2align	3, 0x0
_Z17add_matrix_kernelPiS_S_i:
	.quad	_Z32__device_stub__add_matrix_kernelPiS_S_i
	.size	_Z17add_matrix_kernelPiS_S_i, 8

	.type	_Z21add_matrix_row_kernelPiS_S_i,@object # @_Z21add_matrix_row_kernelPiS_S_i
	.globl	_Z21add_matrix_row_kernelPiS_S_i
	.p2align	3, 0x0
_Z21add_matrix_row_kernelPiS_S_i:
	.quad	_Z36__device_stub__add_matrix_row_kernelPiS_S_i
	.size	_Z21add_matrix_row_kernelPiS_S_i, 8

	.type	_Z21add_matrix_col_kernelPiS_S_i,@object # @_Z21add_matrix_col_kernelPiS_S_i
	.globl	_Z21add_matrix_col_kernelPiS_S_i
	.p2align	3, 0x0
_Z21add_matrix_col_kernelPiS_S_i:
	.quad	_Z36__device_stub__add_matrix_col_kernelPiS_S_i
	.size	_Z21add_matrix_col_kernelPiS_S_i, 8

	.type	_Z21mul_matrix_vec_kernelPiS_S_i,@object # @_Z21mul_matrix_vec_kernelPiS_S_i
	.globl	_Z21mul_matrix_vec_kernelPiS_S_i
	.p2align	3, 0x0
_Z21mul_matrix_vec_kernelPiS_S_i:
	.quad	_Z36__device_stub__mul_matrix_vec_kernelPiS_S_i
	.size	_Z21mul_matrix_vec_kernelPiS_S_i, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"  "
	.size	.L.str.3, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17add_matrix_kernelPiS_S_i"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z21add_matrix_col_kernelPiS_S_i"
	.size	.L__unnamed_2, 33

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z21add_matrix_row_kernelPiS_S_i"
	.size	.L__unnamed_3, 33

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z21mul_matrix_vec_kernelPiS_S_i"
	.size	.L__unnamed_4, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__add_matrix_kernelPiS_S_i
	.addrsig_sym _Z36__device_stub__add_matrix_row_kernelPiS_S_i
	.addrsig_sym _Z36__device_stub__add_matrix_col_kernelPiS_S_i
	.addrsig_sym _Z36__device_stub__mul_matrix_vec_kernelPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZSt4cout
	.addrsig_sym _Z17add_matrix_kernelPiS_S_i
	.addrsig_sym _Z21add_matrix_row_kernelPiS_S_i
	.addrsig_sym _Z21add_matrix_col_kernelPiS_S_i
	.addrsig_sym _Z21mul_matrix_vec_kernelPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17add_matrix_kernelPiS_S_i ; -- Begin function _Z17add_matrix_kernelPiS_S_i
	.globl	_Z17add_matrix_kernelPiS_S_i
	.p2align	8
	.type	_Z17add_matrix_kernelPiS_S_i,@function
_Z17add_matrix_kernelPiS_S_i:           ; @_Z17add_matrix_kernelPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17add_matrix_kernelPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17add_matrix_kernelPiS_S_i, .Lfunc_end0-_Z17add_matrix_kernelPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21add_matrix_col_kernelPiS_S_i ; -- Begin function _Z21add_matrix_col_kernelPiS_S_i
	.globl	_Z21add_matrix_col_kernelPiS_S_i
	.p2align	8
	.type	_Z21add_matrix_col_kernelPiS_S_i,@function
_Z21add_matrix_col_kernelPiS_S_i:       ; @_Z21add_matrix_col_kernelPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, 0, v1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_cmp_gt_i32 s2, 0
	s_mul_i32 s15, s15, s4
	s_cselect_b32 s4, -1, 0
	v_cmp_eq_u32_e32 vcc_lo, s15, v1
	s_and_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	s_mov_b32 s3, s2
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s3, s3, -1
	s_cmp_lg_u32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_nc_u32_e32 v0, s2, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s0, v1
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[5:6], off
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	global_store_b32 v[1:2], v3, off
	s_cbranch_scc1 .LBB1_2
.LBB1_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21add_matrix_col_kernelPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z21add_matrix_col_kernelPiS_S_i, .Lfunc_end1-_Z21add_matrix_col_kernelPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21add_matrix_row_kernelPiS_S_i ; -- Begin function _Z21add_matrix_row_kernelPiS_S_i
	.globl	_Z21add_matrix_row_kernelPiS_S_i
	.p2align	8
	.type	_Z21add_matrix_row_kernelPiS_S_i,@function
_Z21add_matrix_row_kernelPiS_S_i:       ; @_Z21add_matrix_row_kernelPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x2c
	s_load_b32 s4, s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, 0, v1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_cmp_gt_i32 s4, 0
	s_mul_i32 s14, s14, s5
	s_cselect_b32 s5, -1, 0
	v_cmp_eq_u32_e32 vcc_lo, s14, v1
	s_and_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s5
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s2, s[2:3], 0xc
	v_bfe_u32 v0, v0, 10, 10
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mul_lo_u32 v0, v1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[0:1], off
	global_load_b32 v7, v[2:3], off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s4, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v7, v6
	global_store_b32 v[4:5], v6, off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_cbranch_scc1 .LBB2_2
.LBB2_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21add_matrix_row_kernelPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z21add_matrix_row_kernelPiS_S_i, .Lfunc_end2-_Z21add_matrix_row_kernelPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21mul_matrix_vec_kernelPiS_S_i ; -- Begin function _Z21mul_matrix_vec_kernelPiS_S_i
	.globl	_Z21mul_matrix_vec_kernelPiS_S_i
	.p2align	8
	.type	_Z21mul_matrix_vec_kernelPiS_S_i,@function
_Z21mul_matrix_vec_kernelPiS_S_i:       ; @_Z21mul_matrix_vec_kernelPiS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	v_bfe_u32 v1, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_sub_nc_u32_e32 v1, 0, v1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_mul_i32 s15, s15, s3
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s15, v1
	s_cbranch_execz .LBB3_4
; %bb.1:
	v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v2, 0x3ff, v0
	s_and_b32 s4, s2, 0xffff
	s_load_b64 s[2:3], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	s_load_b32 s4, s[0:1], 0x18
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_cmp_lt_i32 s4, 1
	global_store_b32 v[2:3], v5, off
	s_cbranch_scc1 .LBB3_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v4, 0
	s_mov_b32 s5, s4
.LBB3_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b32 v1, v5, s[2:3]
	global_load_b32 v8, v[6:7], off
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s5, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, v1, v8, v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v6
	global_store_b32 v[2:3], v6, off
	s_cbranch_scc1 .LBB3_3
.LBB3_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21mul_matrix_vec_kernelPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z21mul_matrix_vec_kernelPiS_S_i, .Lfunc_end3-_Z21mul_matrix_vec_kernelPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17add_matrix_kernelPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17add_matrix_kernelPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21add_matrix_col_kernelPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21add_matrix_col_kernelPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21add_matrix_row_kernelPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21add_matrix_row_kernelPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21mul_matrix_vec_kernelPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21mul_matrix_vec_kernelPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
