
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "cuda.h"
#include <math.h>
#include <stdio.h>
//#include <stdlib.h>
#include <string.h>
#include <time.h>

//__shared__ int ipiv[3];
__shared__ int indxc[3],indxr[3];


template<typename Typeval>
__device__ void Swap(Typeval &a,Typeval &b)
//void Swap(Typeval &a,Typeval &b)
{
	Typeval temp;
	temp=a;
	a=b;
	b=temp;
}

__global__ void kernel(double *a)
{
	/*b[0]=2*b[0];
	a[10]=a[10]+b[0];*/

	int x=threadIdx.x+blockIdx.x*blockDim.x;
	int y=threadIdx.y+blockIdx.y*blockDim.y;

	int offset=x+y*blockDim.x*gridDim.x;

	__shared__ float shared[32][32];

	const float period=128.0f;

	
	shared[threadIdx.x][threadIdx.y]=x+y;
	__syncthreads();

	
	a[offset]=255*shared[threadIdx.x][threadIdx.y];
	
	__syncthreads();
	

	


	int aa=0;



}

__global__ void fixRow(double*matrix,double*b,int size,int rowId)
{
	__shared__ double Ri[512];
	__shared__ double Bi[100];
	__shared__ double Aii;
	int colId=threadIdx.x;
	Ri[colId]=matrix[size*rowId+colId];//matrix[size*rowId+colId];

	Bi[colId]=b[size*rowId+0];

	Aii=matrix[size*rowId+rowId];//the diagonal element for ith row
	__syncthreads();

	Ri[colId]=Ri[colId]/Aii;
	matrix[size*rowId+colId]=Ri[colId];

	Bi[colId]=Bi[colId]/Aii;
	b[size*rowId+0]=Bi[colId];
}

__global__ void fixColumn(double *matrix,double *b,int size,int colId)
{
	int i=threadIdx.x;
	int j=blockIdx.x;

	__shared__ double col[512];
	
	__shared__ double AcolIdj;
	__shared__ double BcolIdj;
	__shared__ double colj[512];
	__shared__ double Bj[100];

	col[i]=matrix[i*size+colId];

	if(col[i]!=0)
	{
		colj[i]=matrix[i*size+j];
		Bj[i]=b[i*size+j];

		AcolIdj=matrix[colId*size+j];
		BcolIdj=b[colId*size+j];
		if(i!=colId)
		{
			colj[i]=colj[i]-AcolIdj*col[i];
			Bj[i]=Bj[i]-BcolIdj*col[i];
		}
		matrix[i*size+j]=colj[i];
		b[i*size+j]=Bj[i];

	}
}





extern "C" int
 runGauss(int MatrixSize,double *b,double**a )
{

	int vectorsize=30;
	//int MatrixSize=100;

	double *a_new,*b_new;
	
	a_new=new double[vectorsize];
	b_new=new double[vectorsize];
	//b=new float[vectorsize];
	//ipiv=new int[3];
	for(int i=0;i<MatrixSize;i++)
	{
		b_new[i*MatrixSize]=b[i];
		for(int j=0;j<MatrixSize;j++)
			a_new[i*MatrixSize+j]=a[i][j];
	}
	

	
	 
	 double *a_device,*b_device;
	
	 cudaMalloc((void**)&a_device,vectorsize*sizeof(double));
	 cudaMalloc((void**)&b_device,vectorsize*sizeof(double));
	 
	
	
	 cudaEvent_t start,stop;
	 cudaEventCreate(&start);
	 cudaEventCreate(&stop);
	 cudaEventRecord(start,0);
	 /*clock_t start,end;
	 start = clock();*/
	
		 cudaMemcpy(a_device,a_new,vectorsize*sizeof(double),cudaMemcpyHostToDevice);
	     cudaMemcpy(b_device,b_new,vectorsize*sizeof(double),cudaMemcpyHostToDevice);
		 for(int i=0;i<MatrixSize;i++)
		 {
			 fixRow<<<1,MatrixSize>>>(a_device,b_device,MatrixSize,i);	
			 fixColumn<<<MatrixSize,MatrixSize>>>(a_device,b_device,MatrixSize,i);
		 }
		 
	
	

	 cudaEventRecord(stop,0);
	 cudaEventSynchronize(stop);
	 float elapseTime;
	 cudaEventElapsedTime(&elapseTime,start,stop);
	
	 cudaMemcpy(a_new,a_device,vectorsize*sizeof(double),cudaMemcpyDeviceToHost);
	 cudaMemcpy(b_new,b_device,vectorsize*sizeof(double),cudaMemcpyDeviceToHost);
	 for(int i=0;i<MatrixSize*MatrixSize;i++)
		 printf("%d-%5.3f\n",i+1,a_new[i]);


	 for(int i=0;i<MatrixSize;i++)
	 {
		 b[i]=b_new[i*MatrixSize];
		for(int j=0;j<MatrixSize;j++)
			a[i][j]=a_new[i*MatrixSize+j];
	 }

	 cudaFree((void*)a_device);
	 cudaFree((void*)b_device);

	 free(a_new);
	 free(b_new);
	 
	return 0;
}
	.file	"tmpxft_002d9dad_00000000-6_gauss.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z25__device_stub__Z6kernelPdPd
	.type	_Z25__device_stub__Z6kernelPdPd, @function
_Z25__device_stub__Z6kernelPdPd:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6kernelPd(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z25__device_stub__Z6kernelPdPd, .-_Z25__device_stub__Z6kernelPdPd
	.globl	_Z6kernelPd
	.type	_Z6kernelPd, @function
_Z6kernelPd:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6kernelPdPd
	.cfi_endproc
.LFE2054:
	.size	_Z6kernelPd, .-_Z6kernelPd
	.globl	_Z29__device_stub__Z6fixRowPdS_iiPdS_ii
	.type	_Z29__device_stub__Z6fixRowPdS_iiPdS_ii, @function
_Z29__device_stub__Z6fixRowPdS_iiPdS_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6fixRowPdS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z29__device_stub__Z6fixRowPdS_iiPdS_ii, .-_Z29__device_stub__Z6fixRowPdS_iiPdS_ii
	.globl	_Z6fixRowPdS_ii
	.type	_Z6fixRowPdS_ii, @function
_Z6fixRowPdS_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6fixRowPdS_iiPdS_ii
	.cfi_endproc
.LFE2056:
	.size	_Z6fixRowPdS_ii, .-_Z6fixRowPdS_ii
	.globl	_Z32__device_stub__Z9fixColumnPdS_iiPdS_ii
	.type	_Z32__device_stub__Z9fixColumnPdS_iiPdS_ii, @function
_Z32__device_stub__Z9fixColumnPdS_iiPdS_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9fixColumnPdS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z32__device_stub__Z9fixColumnPdS_iiPdS_ii, .-_Z32__device_stub__Z9fixColumnPdS_iiPdS_ii
	.globl	_Z9fixColumnPdS_ii
	.type	_Z9fixColumnPdS_ii, @function
_Z9fixColumnPdS_ii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9fixColumnPdS_iiPdS_ii
	.cfi_endproc
.LFE2058:
	.size	_Z9fixColumnPdS_ii, .-_Z9fixColumnPdS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d-%5.3f\n"
	.text
	.globl	runGauss
	.type	runGauss, @function
runGauss:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	movl	$240, %edi
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$240, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	xorl	%ecx, %ecx
	movq	%rax, %r12
	movslq	%ebx, %rax
	salq	$3, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
.L19:
	cmpl	%eax, %ebx
	jle	.L35
	movsd	(%r14,%rax,8), %xmm0
	movq	(%r15,%rax,8), %rdi
	xorl	%edx, %edx
	leaq	0(%rbp,%rcx), %rsi
	movsd	%xmm0, (%r12,%rcx)
.L20:
	movsd	(%rdi,%rdx,8), %xmm0
	movsd	%xmm0, (%rsi,%rdx,8)
	incq	%rdx
	cmpl	%edx, %ebx
	jg	.L20
	movq	8(%rsp), %rsi
	incq	%rax
	addq	%rsi, %rcx
	jmp	.L19
.L35:
	leaq	16(%rsp), %rdi
	movl	$240, %esi
	movabsq	$4294967297, %r13
	call	cudaMalloc@PLT
	movl	$240, %esi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$240, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$240, %edx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	movl	%eax, 4(%rsp)
.L22:
	cmpl	%ebx, 4(%rsp)
	jge	.L36
	movq	%r13, 64(%rsp)
	movl	68(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%ebx, 60(%rsp)
	movq	60(%rsp), %rdx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movl	4(%rsp), %ecx
	movq	24(%rsp), %rsi
	movl	%ebx, %edx
	movq	16(%rsp), %rdi
	call	_Z29__device_stub__Z6fixRowPdS_iiPdS_ii
.L23:
	movq	%r13, 64(%rsp)
	movl	68(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, 52(%rsp)
	movl	56(%rsp), %esi
	movl	%ebx, 60(%rsp)
	movq	60(%rsp), %rdx
	movl	%ebx, 48(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movl	4(%rsp), %ecx
	movq	24(%rsp), %rsi
	movl	%ebx, %edx
	movq	16(%rsp), %rdi
	call	_Z32__device_stub__Z9fixColumnPdS_iiPdS_ii
.L24:
	incl	4(%rsp)
	jmp	.L22
.L36:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%r13d, %r13d
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	60(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$240, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$240, %edx
	call	cudaMemcpy@PLT
	movl	%ebx, %eax
	imull	%ebx, %eax
	movl	%eax, 4(%rsp)
.L26:
	cmpl	%r13d, 4(%rsp)
	jle	.L37
	movsd	0(%rbp,%r13,8), %xmm0
	leal	1(%r13), %edx
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC0(%rip), %rsi
	incq	%r13
	call	__printf_chk@PLT
	jmp	.L26
.L37:
	xorl	%ecx, %ecx
	xorl	%eax, %eax
.L28:
	cmpl	%eax, %ebx
	jle	.L38
	movsd	(%r12,%rcx), %xmm0
	movq	(%r15,%rax,8), %rsi
	xorl	%edx, %edx
	leaq	0(%rbp,%rcx), %rdi
	movsd	%xmm0, (%r14,%rax,8)
.L29:
	movsd	(%rdi,%rdx,8), %xmm0
	movsd	%xmm0, (%rsi,%rdx,8)
	incq	%rdx
	cmpl	%edx, %ebx
	jg	.L29
	movq	8(%rsp), %rsi
	incq	%rax
	addq	%rsi, %rcx
	jmp	.L28
.L38:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	runGauss, .-runGauss
	.section	.rodata.str1.1
.LC1:
	.string	"_Z9fixColumnPdS_ii"
.LC2:
	.string	"_Z6fixRowPdS_ii"
.LC3:
	.string	"_Z6kernelPd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9fixColumnPdS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6fixRowPdS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6kernelPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"


#include <math.h>
#include <stdio.h>
//#include <stdlib.h>
#include <string.h>
#include <time.h>

//__shared__ int ipiv[3];
__shared__ int indxc[3],indxr[3];


template<typename Typeval>
__device__ void Swap(Typeval &a,Typeval &b)
//void Swap(Typeval &a,Typeval &b)
{
	Typeval temp;
	temp=a;
	a=b;
	b=temp;
}

__global__ void kernel(double *a)
{
	/*b[0]=2*b[0];
	a[10]=a[10]+b[0];*/

	int x=threadIdx.x+blockIdx.x*blockDim.x;
	int y=threadIdx.y+blockIdx.y*blockDim.y;

	int offset=x+y*blockDim.x*gridDim.x;

	__shared__ float shared[32][32];

	const float period=128.0f;

	
	shared[threadIdx.x][threadIdx.y]=x+y;
	__syncthreads();

	
	a[offset]=255*shared[threadIdx.x][threadIdx.y];
	
	__syncthreads();
	

	


	int aa=0;



}

__global__ void fixRow(double*matrix,double*b,int size,int rowId)
{
	__shared__ double Ri[512];
	__shared__ double Bi[100];
	__shared__ double Aii;
	int colId=threadIdx.x;
	Ri[colId]=matrix[size*rowId+colId];//matrix[size*rowId+colId];

	Bi[colId]=b[size*rowId+0];

	Aii=matrix[size*rowId+rowId];//the diagonal element for ith row
	__syncthreads();

	Ri[colId]=Ri[colId]/Aii;
	matrix[size*rowId+colId]=Ri[colId];

	Bi[colId]=Bi[colId]/Aii;
	b[size*rowId+0]=Bi[colId];
}

__global__ void fixColumn(double *matrix,double *b,int size,int colId)
{
	int i=threadIdx.x;
	int j=blockIdx.x;

	__shared__ double col[512];
	
	__shared__ double AcolIdj;
	__shared__ double BcolIdj;
	__shared__ double colj[512];
	__shared__ double Bj[100];

	col[i]=matrix[i*size+colId];

	if(col[i]!=0)
	{
		colj[i]=matrix[i*size+j];
		Bj[i]=b[i*size+j];

		AcolIdj=matrix[colId*size+j];
		BcolIdj=b[colId*size+j];
		if(i!=colId)
		{
			colj[i]=colj[i]-AcolIdj*col[i];
			Bj[i]=Bj[i]-BcolIdj*col[i];
		}
		matrix[i*size+j]=colj[i];
		b[i*size+j]=Bj[i];

	}
}





extern "C" int
 runGauss(int MatrixSize,double *b,double**a )
{

	int vectorsize=30;
	//int MatrixSize=100;

	double *a_new,*b_new;
	
	a_new=new double[vectorsize];
	b_new=new double[vectorsize];
	//b=new float[vectorsize];
	//ipiv=new int[3];
	for(int i=0;i<MatrixSize;i++)
	{
		b_new[i*MatrixSize]=b[i];
		for(int j=0;j<MatrixSize;j++)
			a_new[i*MatrixSize+j]=a[i][j];
	}
	

	
	 
	 double *a_device,*b_device;
	
	 hipMalloc((void**)&a_device,vectorsize*sizeof(double));
	 hipMalloc((void**)&b_device,vectorsize*sizeof(double));
	 
	
	
	 hipEvent_t start,stop;
	 hipEventCreate(&start);
	 hipEventCreate(&stop);
	 hipEventRecord(start,0);
	 /*clock_t start,end;
	 start = clock();*/
	
		 hipMemcpy(a_device,a_new,vectorsize*sizeof(double),hipMemcpyHostToDevice);
	     hipMemcpy(b_device,b_new,vectorsize*sizeof(double),hipMemcpyHostToDevice);
		 for(int i=0;i<MatrixSize;i++)
		 {
			 fixRow<<<1,MatrixSize>>>(a_device,b_device,MatrixSize,i);	
			 fixColumn<<<MatrixSize,MatrixSize>>>(a_device,b_device,MatrixSize,i);
		 }
		 
	
	

	 hipEventRecord(stop,0);
	 hipEventSynchronize(stop);
	 float elapseTime;
	 hipEventElapsedTime(&elapseTime,start,stop);
	
	 hipMemcpy(a_new,a_device,vectorsize*sizeof(double),hipMemcpyDeviceToHost);
	 hipMemcpy(b_new,b_device,vectorsize*sizeof(double),hipMemcpyDeviceToHost);
	 for(int i=0;i<MatrixSize*MatrixSize;i++)
		 printf("%d-%5.3f\n",i+1,a_new[i]);


	 for(int i=0;i<MatrixSize;i++)
	 {
		 b[i]=b_new[i*MatrixSize];
		for(int j=0;j<MatrixSize;j++)
			a[i][j]=a_new[i*MatrixSize+j];
	 }

	 hipFree((void*)a_device);
	 hipFree((void*)b_device);

	 free(a_new);
	 free(b_new);
	 
	return 0;
}
	.text
	.file	"gauss.hip"
	.globl	_Z21__device_stub__kernelPd     # -- Begin function _Z21__device_stub__kernelPd
	.type	_Z21__device_stub__kernelPd,@function
_Z21__device_stub__kernelPd:            # @_Z21__device_stub__kernelPd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelPd, .Lfunc_end0-_Z21__device_stub__kernelPd
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__fixRowPdS_ii # -- Begin function _Z21__device_stub__fixRowPdS_ii
	.type	_Z21__device_stub__fixRowPdS_ii,@function
_Z21__device_stub__fixRowPdS_ii:        # @_Z21__device_stub__fixRowPdS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6fixRowPdS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__fixRowPdS_ii, .Lfunc_end1-_Z21__device_stub__fixRowPdS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__fixColumnPdS_ii # -- Begin function _Z24__device_stub__fixColumnPdS_ii
	.type	_Z24__device_stub__fixColumnPdS_ii,@function
_Z24__device_stub__fixColumnPdS_ii:     # @_Z24__device_stub__fixColumnPdS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9fixColumnPdS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__fixColumnPdS_ii, .Lfunc_end2-_Z24__device_stub__fixColumnPdS_ii
	.cfi_endproc
                                        # -- End function
	.globl	runGauss                        # -- Begin function runGauss
	.type	runGauss,@function
runGauss:                               # @runGauss
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %r14
	movq	%rsi, %r15
	movl	%edi, %ebp
	movl	$240, %edi
	callq	_Znam
	movq	%rax, %rbx
	movl	$240, %edi
	callq	_Znam
	movq	%rax, %r13
	movl	%ebp, %r12d
	testl	%ebp, %ebp
	jle	.LBB3_5
# %bb.1:                                # %.lr.ph91
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB3_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_3 Depth 2
	movl	%eax, %edx
	leaq	(%rbx,%rdx,8), %rdx
	movsd	(%r15,%rcx,8), %xmm0            # xmm0 = mem[0],zero
	movq	%rcx, %rsi
	imulq	%r12, %rsi
	movsd	%xmm0, (%r13,%rsi,8)
	movq	(%r14,%rcx,8), %rsi
	xorl	%edi, %edi
.LBB3_3:                                #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%rsi,%rdi,8), %xmm0            # xmm0 = mem[0],zero
	movsd	%xmm0, (%rdx,%rdi,8)
	incq	%rdi
	cmpq	%rdi, %r12
	jne	.LBB3_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%rcx
	addl	%ebp, %eax
	cmpq	%r12, %rcx
	jne	.LBB3_2
.LBB3_5:                                # %._crit_edge92
	movq	%r15, 32(%rsp)                  # 8-byte Spill
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	leaq	16(%rsp), %r14
	movl	$240, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$240, %esi
	callq	hipMalloc
	movq	%r13, %r15
	leaq	56(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%r13d, %r13d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r14), %rdi
	movl	$240, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$240, %edx
	movq	%r15, 48(%rsp)                  # 8-byte Spill
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%ebp, %ebp
	jle	.LBB3_12
# %bb.6:                                # %.lr.ph95
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movq	%r12, %r14
	btsq	$32, %r14
	incq	%r15
.LBB3_7:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.8:                                #   in Loop: Header=BB3_7 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%ebp, %edx
	movl	%r13d, %ecx
	callq	_Z21__device_stub__fixRowPdS_ii
.LBB3_9:                                #   in Loop: Header=BB3_7 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_11
# %bb.10:                               #   in Loop: Header=BB3_7 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%ebp, %edx
	movl	%r13d, %ecx
	callq	_Z24__device_stub__fixColumnPdS_ii
.LBB3_11:                               #   in Loop: Header=BB3_7 Depth=1
	incl	%r13d
	cmpl	%r13d, %ebp
	jne	.LBB3_7
.LBB3_12:                               # %._crit_edge96
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	68(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rsi
	movl	$240, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$240, %edx
	movq	48(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%ebp, %ebp
	je	.LBB3_20
# %bb.13:                               # %.lr.ph99.preheader
	movl	%ebp, %r14d
	imull	%r14d, %r14d
	cmpl	$1, %r14d
	adcl	$0, %r14d
	xorl	%r15d, %r15d
.LBB3_14:                               # %.lr.ph99
                                        # =>This Inner Loop Header: Depth=1
	movsd	(%rbx,%r15,8), %xmm0            # xmm0 = mem[0],zero
	incq	%r15
	movl	$.L.str, %edi
	movl	%r15d, %esi
	movb	$1, %al
	callq	printf
	cmpq	%r15, %r14
	jne	.LBB3_14
# %bb.15:                               # %.preheader
	testl	%ebp, %ebp
	movq	40(%rsp), %r8                   # 8-byte Reload
	movq	32(%rsp), %r9                   # 8-byte Reload
	jle	.LBB3_20
# %bb.16:                               # %.lr.ph105
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB3_17:                               # %.lr.ph102
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_18 Depth 2
	movl	%eax, %edx
	leaq	(%rbx,%rdx,8), %rdx
	movq	%rcx, %rsi
	imulq	%r12, %rsi
	movsd	(%r13,%rsi,8), %xmm0            # xmm0 = mem[0],zero
	movsd	%xmm0, (%r9,%rcx,8)
	movq	(%r8,%rcx,8), %rsi
	xorl	%edi, %edi
.LBB3_18:                               #   Parent Loop BB3_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%rdx,%rdi,8), %xmm0            # xmm0 = mem[0],zero
	movsd	%xmm0, (%rsi,%rdi,8)
	incq	%rdi
	cmpq	%rdi, %r12
	jne	.LBB3_18
# %bb.19:                               # %._crit_edge103
                                        #   in Loop: Header=BB3_17 Depth=1
	incq	%rcx
	addl	%ebp, %eax
	cmpq	%r12, %rcx
	jne	.LBB3_17
.LBB3_20:                               # %._crit_edge106
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	runGauss, .Lfunc_end3-runGauss
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6fixRowPdS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9fixColumnPdS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelPd,@object             # @_Z6kernelPd
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPd
	.p2align	3, 0x0
_Z6kernelPd:
	.quad	_Z21__device_stub__kernelPd
	.size	_Z6kernelPd, 8

	.type	_Z6fixRowPdS_ii,@object         # @_Z6fixRowPdS_ii
	.globl	_Z6fixRowPdS_ii
	.p2align	3, 0x0
_Z6fixRowPdS_ii:
	.quad	_Z21__device_stub__fixRowPdS_ii
	.size	_Z6fixRowPdS_ii, 8

	.type	_Z9fixColumnPdS_ii,@object      # @_Z9fixColumnPdS_ii
	.globl	_Z9fixColumnPdS_ii
	.p2align	3, 0x0
_Z9fixColumnPdS_ii:
	.quad	_Z24__device_stub__fixColumnPdS_ii
	.size	_Z9fixColumnPdS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d-%5.3f\n"
	.size	.L.str, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelPd"
	.size	.L__unnamed_1, 12

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6fixRowPdS_ii"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9fixColumnPdS_ii"
	.size	.L__unnamed_3, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPd
	.addrsig_sym _Z21__device_stub__fixRowPdS_ii
	.addrsig_sym _Z24__device_stub__fixColumnPdS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelPd
	.addrsig_sym _Z6fixRowPdS_ii
	.addrsig_sym _Z9fixColumnPdS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPd             ; -- Begin function _Z6kernelPd
	.globl	_Z6kernelPd
	.p2align	8
	.type	_Z6kernelPd,@function
_Z6kernelPd:                            ; @_Z6kernelPd
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	v_lshlrev_b32_e32 v0, 2, v0
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v0, v1, 7, v0
	v_add_nc_u32_e32 v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v4
	ds_store_b32 v0, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v0, v0
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s3, v3, v[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v0, 0x437f0000, v0
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_cvt_f64_f32_e32 v[0:1], v0
	global_store_b64 v[2:3], v[0:1], off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPd
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPd, .Lfunc_end0-_Z6kernelPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6fixRowPdS_ii         ; -- Begin function _Z6fixRowPdS_ii
	.globl	_Z6fixRowPdS_ii
	.p2align	8
	.type	_Z6fixRowPdS_ii,@function
_Z6fixRowPdS_ii:                        ; @_Z6fixRowPdS_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v24, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s6, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s6, v0
	s_ashr_i32 s7, s6, 31
	s_lshl_b64 s[8:9], s[6:7], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_u32 s2, s2, s8
	v_ashrrev_i32_e32 v2, 31, v1
	s_addc_u32 s3, s3, s9
	s_add_i32 s4, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s5, s4, 31
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_lshl_b64 s[4:5], s[4:5], 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	global_load_b64 v[1:2], v[4:5], off
	s_load_b64 s[0:1], s[0:1], 0x0
	s_load_b64 s[4:5], s[2:3], 0x0
	v_lshlrev_b32_e32 v25, 3, v0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
	v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
	ds_store_b64 v24, v[6:7] offset:4896
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b64 v25, v[1:2], v[8:9] offset1:8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_stride64_b64 v[0:3], v25 offset1:8
	ds_load_b64 v[6:7], v24 offset:4896
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[0:1]
	v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
	v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[12:13], v[8:9]
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[20:21], v[12:13]
	v_mul_f64 v[22:23], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
	v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[0:1], v[8:9], v[6:7], v[0:1]
	v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
	global_store_b64 v[4:5], v[0:1], off
	ds_store_2addr_stride64_b64 v25, v[0:1], v[2:3] offset1:8
	s_waitcnt lgkmcnt(0)
	global_store_b64 v24, v[2:3], s[2:3]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6fixRowPdS_ii
		.amdhsa_group_segment_fixed_size 4904
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 10
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6fixRowPdS_ii, .Lfunc_end1-_Z6fixRowPdS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 464
; NumSgprs: 12
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4904 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9fixColumnPdS_ii      ; -- Begin function _Z9fixColumnPdS_ii
	.globl	_Z9fixColumnPdS_ii
	.p2align	8
	.type	_Z9fixColumnPdS_ii,@function
_Z9fixColumnPdS_ii:                     ; @_Z9fixColumnPdS_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v3, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s5, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f64_e32 0, v[1:2]
	s_cbranch_execz .LBB2_4
; %bb.1:
	v_add_nc_u32_e32 v3, s15, v3
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[5:6], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	global_load_b64 v[7:8], v[3:4], off
	global_load_b64 v[9:10], v[5:6], off
	v_cmpx_ne_u32_e64 s5, v0
	s_cbranch_execz .LBB2_3
; %bb.2:
	s_mul_i32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s15
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[4:5], 3
	s_add_u32 s2, s2, s4
	s_addc_u32 s3, s3, s5
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	s_load_b64 s[0:1], s[0:1], 0x0
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fma_f64 v[7:8], -v[1:2], s[0:1], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[9:10], -v[1:2], s[2:3], v[9:10]
.LBB2_3:
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(1)
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[5:6], v[9:10], off
.LBB2_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9fixColumnPdS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9fixColumnPdS_ii, .Lfunc_end2-_Z9fixColumnPdS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPd
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4904
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6fixRowPdS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z6fixRowPdS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9fixColumnPdS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9fixColumnPdS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
