#include<iostream>
#include<cuda.h>
#include<stdio.h>
using namespace std;
#define TILE_WIDTH 4
__global__ void MatrixMulKernel( int* A, int* B, int* C,int m, int n, int k)
{
	__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH];
	__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH];
	int bx = blockIdx.x; int by = blockIdx.y;
	int tx = threadIdx.x; int ty = threadIdx.y;
	int cx = blockIdx.x * blockDim.x; int cy = blockIdx.y * blockDim.y;
	int Cx = cx + tx; int Cy = cy + ty;
	int Row = by * blockDim.y + ty;
	int Col = bx * blockDim.x + tx;
	int Cvalue = 0;
	int total_tiles = (n + TILE_WIDTH - 1) / TILE_WIDTH;
	for (int t = 0; t <  total_tiles; ++t)
	 {
		int Ax = t * TILE_WIDTH + tx; int Ay = cy + ty;
		int Bx = cx + tx; int By = t * TILE_WIDTH + ty;
		
		if (Ax < n && Ay < m) {
      			ds_A[ty][tx] = A[Ay * n + Ax];
   		 }
   		 else {
      			ds_A[ty][tx] = 0;
   		 }
    		if (Bx < n && By < k) {
     			ds_B[ty][tx] = B[By * n + Bx];
    		}
   		 else {
     			 ds_B[ty][tx] = 0;
		}
		__syncthreads();
		for (int i = 0; i < TILE_WIDTH; i++) {
      			Cvalue+= ds_A[ty][i] * ds_B[i][tx];
		}
		__syncthreads();
	}
		 if (Cx < n && Cy < m) {
    			C[Cy * n + Cx] = Cvalue;
  			}
}

int main()
{
int r1=30,r2=30,c1=30,c2 = 30;
int *a= new int[r1*c1];
int *b= new int[r2*c2];
int *c= new int[r1*c2];
for(int i=0;i<r1;i++)
for(int j=0;j<c1;j++)

   { a[i*c1+j] = rand()%100;}

for(int i=0;i<r2;i++)
 { for(int j=0;j<c2;j++)
      { b[i*c2+j]= rand()%100;}}
if(r2!=c1)
{
cout<<"not possible";
return 0;
}
else
{    
int *d_a,*d_b,*d_c;
cudaMalloc((void**)&d_a,sizeof(int)*r1*c1);
cudaMalloc((void**)&d_b,sizeof(int)*r2*c2);
cudaMalloc((void**)&d_c,sizeof(int)*r1*c2);
cudaMemcpy(d_a,a,sizeof(int)*r1*c1,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,sizeof(int)*r2*c2,cudaMemcpyHostToDevice);

const dim3 blocksize((c2/TILE_WIDTH) + 1, (r1/TILE_WIDTH) + 1, 1);//Number of Blocks required
const dim3 gridsize(TILE_WIDTH, TILE_WIDTH, 1);//Number of threads in each block


/*const dim3 blocksize(ceil(r1-1)/16 +1,ceil(c2-1)/16+1,1);
const dim3 gridsize(16,16,1);*/
//matrixmul<<<dim3(50,50),1>>>(d_a,d_b,d_c,r1,c2,r2);
MatrixMulKernel<<<blocksize,gridsize>>>(d_a,d_b,d_c,r1,c2,r2);

cudaMemcpy(c,d_c,sizeof(int)*r1*c2,cudaMemcpyDeviceToHost);

for(int i=0;i<r1;i++)
 { for(int j=0;j<c2;j++)
       { cout<<c[i*c2+j]<<" ";
}
 cout<<endl;}
 cout<<endl;

cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
return 0;


}
   





	.file	"tmpxft_002a521d_00000000-6_tilemult.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
	.type	_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15MatrixMulKernelPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
	.globl	_Z15MatrixMulKernelPiS_S_iii
	.type	_Z15MatrixMulKernelPiS_S_iii, @function
_Z15MatrixMulKernelPiS_S_iii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE3661:
	.size	_Z15MatrixMulKernelPiS_S_iii, .-_Z15MatrixMulKernelPiS_S_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$3600, %edi
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$3600, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$3600, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movq	%rax, %rbp
.L9:
	imulq	$120, %r15, %r14
	xorl	%r13d, %r13d
	addq	%r12, %r14
.L10:
	call	rand@PLT
	movl	$100, %ecx
	cltd
	idivl	%ecx
	movl	%edx, (%r14,%r13,4)
	incq	%r13
	cmpq	$30, %r13
	jne	.L10
	incq	%r15
	cmpq	$30, %r15
	jne	.L9
	xorl	%r15d, %r15d
.L11:
	imulq	$120, %r15, %r14
	xorl	%r13d, %r13d
	addq	%rbx, %r14
.L12:
	call	rand@PLT
	movl	$100, %ecx
	cltd
	idivl	%ecx
	movl	%edx, (%r14,%r13,4)
	incq	%r13
	cmpq	$30, %r13
	jne	.L12
	incq	%r15
	cmpq	$30, %r15
	jne	.L11
	leaq	8(%rsp), %rdi
	movl	$3600, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$3600, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$3600, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$3600, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$3600, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$17179869188, %rdx
	movl	$1, %esi
	movabsq	$34359738376, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$30, %r9d
	movl	$30, %r8d
	movq	8(%rsp), %rdi
	movl	$30, %ecx
	call	_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
.L14:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%r12d, %r12d
	movl	$3600, %edx
	leaq	_ZSt4cout(%rip), %r13
	call	cudaMemcpy@PLT
.L15:
	imulq	$120, %r12, %r14
	xorl	%ebx, %ebx
	addq	%rbp, %r14
.L16:
	movl	(%r14,%rbx,4), %esi
	movq	%r13, %rdi
	incq	%rbx
	call	_ZNSolsEi@PLT
	movl	$1, %edx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$30, %rbx
	jne	.L16
	movq	%r13, %rdi
	incq	%r12
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$30, %r12
	jne	.L15
	movq	%r13, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z15MatrixMulKernelPiS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15MatrixMulKernelPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<iostream>
#include<hip/hip_runtime.h>
#include<stdio.h>
using namespace std;
#define TILE_WIDTH 4
__global__ void MatrixMulKernel( int* A, int* B, int* C,int m, int n, int k)
{
	__shared__ int ds_A[TILE_WIDTH][TILE_WIDTH];
	__shared__ int ds_B[TILE_WIDTH][TILE_WIDTH];
	int bx = blockIdx.x; int by = blockIdx.y;
	int tx = threadIdx.x; int ty = threadIdx.y;
	int cx = blockIdx.x * blockDim.x; int cy = blockIdx.y * blockDim.y;
	int Cx = cx + tx; int Cy = cy + ty;
	int Row = by * blockDim.y + ty;
	int Col = bx * blockDim.x + tx;
	int Cvalue = 0;
	int total_tiles = (n + TILE_WIDTH - 1) / TILE_WIDTH;
	for (int t = 0; t <  total_tiles; ++t)
	 {
		int Ax = t * TILE_WIDTH + tx; int Ay = cy + ty;
		int Bx = cx + tx; int By = t * TILE_WIDTH + ty;
		
		if (Ax < n && Ay < m) {
      			ds_A[ty][tx] = A[Ay * n + Ax];
   		 }
   		 else {
      			ds_A[ty][tx] = 0;
   		 }
    		if (Bx < n && By < k) {
     			ds_B[ty][tx] = B[By * n + Bx];
    		}
   		 else {
     			 ds_B[ty][tx] = 0;
		}
		__syncthreads();
		for (int i = 0; i < TILE_WIDTH; i++) {
      			Cvalue+= ds_A[ty][i] * ds_B[i][tx];
		}
		__syncthreads();
	}
		 if (Cx < n && Cy < m) {
    			C[Cy * n + Cx] = Cvalue;
  			}
}

int main()
{
int r1=30,r2=30,c1=30,c2 = 30;
int *a= new int[r1*c1];
int *b= new int[r2*c2];
int *c= new int[r1*c2];
for(int i=0;i<r1;i++)
for(int j=0;j<c1;j++)

   { a[i*c1+j] = rand()%100;}

for(int i=0;i<r2;i++)
 { for(int j=0;j<c2;j++)
      { b[i*c2+j]= rand()%100;}}
if(r2!=c1)
{
cout<<"not possible";
return 0;
}
else
{    
int *d_a,*d_b,*d_c;
hipMalloc((void**)&d_a,sizeof(int)*r1*c1);
hipMalloc((void**)&d_b,sizeof(int)*r2*c2);
hipMalloc((void**)&d_c,sizeof(int)*r1*c2);
hipMemcpy(d_a,a,sizeof(int)*r1*c1,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,sizeof(int)*r2*c2,hipMemcpyHostToDevice);

const dim3 blocksize((c2/TILE_WIDTH) + 1, (r1/TILE_WIDTH) + 1, 1);//Number of Blocks required
const dim3 gridsize(TILE_WIDTH, TILE_WIDTH, 1);//Number of threads in each block


/*const dim3 blocksize(ceil(r1-1)/16 +1,ceil(c2-1)/16+1,1);
const dim3 gridsize(16,16,1);*/
//matrixmul<<<dim3(50,50),1>>>(d_a,d_b,d_c,r1,c2,r2);
MatrixMulKernel<<<blocksize,gridsize>>>(d_a,d_b,d_c,r1,c2,r2);

hipMemcpy(c,d_c,sizeof(int)*r1*c2,hipMemcpyDeviceToHost);

for(int i=0;i<r1;i++)
 { for(int j=0;j<c2;j++)
       { cout<<c[i*c2+j]<<" ";
}
 cout<<endl;}
 cout<<endl;

hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
return 0;


}
   





	.text
	.file	"tilemult.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__MatrixMulKernelPiS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPiS_S_iii
	.type	_Z30__device_stub__MatrixMulKernelPiS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPiS_S_iii: # @_Z30__device_stub__MatrixMulKernelPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15MatrixMulKernelPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__MatrixMulKernelPiS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$3600, %edi                     # imm = 0xE10
	callq	_Znam
	movq	%rax, %r15
	movl	$3600, %edi                     # imm = 0xE10
	callq	_Znam
	movq	%rax, %r14
	movl	$3600, %edi                     # imm = 0xE10
	callq	_Znam
	movq	%rax, %rbx
	xorl	%r12d, %r12d
	movq	%r15, %r13
.LBB1_1:                                # %.preheader74
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%ebp, %ebp
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r13,%rbp,4)
	incq	%rbp
	cmpq	$30, %rbp
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r12
	addq	$120, %r13
	cmpq	$30, %r12
	jne	.LBB1_1
# %bb.4:                                # %.preheader72.preheader
	xorl	%r12d, %r12d
	movq	%r14, %r13
.LBB1_5:                                # %.preheader72
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_6 Depth 2
	xorl	%ebp, %ebp
.LBB1_6:                                #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r13,%rbp,4)
	incq	%rbp
	cmpq	$30, %rbp
	jne	.LBB1_6
# %bb.7:                                #   in Loop: Header=BB1_5 Depth=1
	incq	%r12
	addq	$120, %r13
	cmpq	$30, %r12
	jne	.LBB1_5
# %bb.8:
	leaq	16(%rsp), %r12
	movl	$3600, %esi                     # imm = 0xE10
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$3600, %esi                     # imm = 0xE10
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$3600, %esi                     # imm = 0xE10
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$3600, %edx                     # imm = 0xE10
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$3600, %edx                     # imm = 0xE10
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$34359738376, %rdi              # imm = 0x800000008
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.9:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	$30, %ecx
	movl	$30, %r8d
	movl	$30, %r9d
	callq	_Z30__device_stub__MatrixMulKernelPiS_S_iii
.LBB1_10:
	movq	(%rsp), %rsi
	movl	$3600, %edx                     # imm = 0xE10
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r14d, %r14d
	movl	$_ZSt4cout, %r15d
.LBB1_11:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_12 Depth 2
	xorl	%r12d, %r12d
.LBB1_12:                               #   Parent Loop BB1_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rbx,%r12,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r12
	cmpq	$30, %r12
	jne	.LBB1_12
# %bb.13:                               #   in Loop: Header=BB1_11 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r14
	addq	$120, %rbx
	cmpq	$30, %r14
	jne	.LBB1_11
# %bb.14:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15MatrixMulKernelPiS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15MatrixMulKernelPiS_S_iii,@object # @_Z15MatrixMulKernelPiS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z15MatrixMulKernelPiS_S_iii
	.p2align	3, 0x0
_Z15MatrixMulKernelPiS_S_iii:
	.quad	_Z30__device_stub__MatrixMulKernelPiS_S_iii
	.size	_Z15MatrixMulKernelPiS_S_iii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15MatrixMulKernelPiS_S_iii"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__MatrixMulKernelPiS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15MatrixMulKernelPiS_S_iii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15MatrixMulKernelPiS_S_iii ; -- Begin function _Z15MatrixMulKernelPiS_S_iii
	.globl	_Z15MatrixMulKernelPiS_S_iii
	.p2align	8
	.type	_Z15MatrixMulKernelPiS_S_iii,@function
_Z15MatrixMulKernelPiS_S_iii:           ; @_Z15MatrixMulKernelPiS_S_iii
; %bb.0:
	s_clause 0x3
	s_load_b32 s12, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s12, 16
	s_and_b32 s1, s12, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s0, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s1, v[4:5]
	s_cmp_lt_i32 s5, 1
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s5, v1
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v2, 2, v4
	v_lshlrev_b32_e32 v5, 4, v3
	v_mul_lo_u32 v7, v0, s5
	s_add_i32 s1, s5, 3
	s_mov_b32 s12, 0
	v_add_nc_u32_e32 v6, 64, v2
	v_add_nc_u32_e32 v8, v5, v2
	v_mov_b32_e32 v2, 0
	s_lshr_b32 s7, s1, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v9, v6, v5
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_lshl_b32 s13, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v11, s13, v4
	v_cmp_gt_i32_e64 s1, s5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, vcc_lo
	s_and_saveexec_b32 s14, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v10, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s8, v10
	v_add_co_ci_u32_e64 v11, s1, s9, v11, s1
	global_load_b32 v10, v[10:11], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s13, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v10
	v_cmp_gt_i32_e64 s1, s6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s13, s1
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, s5, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s10, v10
	v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
	global_load_b32 v12, v[10:11], off
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_mov_b32_e32 v10, v6
	s_mov_b32 s1, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s1, v5
	s_add_i32 s1, s1, 4
	ds_load_b32 v13, v10
	ds_load_b32 v14, v11
	v_add_nc_u32_e32 v10, 16, v10
	s_cmp_eq_u32 s1, 16
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[11:12], null, v13, v14, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v11
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, s7
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_10
.LBB0_9:
	v_mov_b32_e32 v2, 0
.LBB0_10:                               ; %Flow106
	v_cmp_gt_i32_e32 vcc_lo, s5, v1
	v_cmp_gt_i32_e64 s0, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mad_u64_u32 v[3:4], null, v0, s5, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15MatrixMulKernelPiS_S_iii
		.amdhsa_group_segment_fixed_size 128
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15MatrixMulKernelPiS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 568
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 128 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 128
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15MatrixMulKernelPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15MatrixMulKernelPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
