#include <stdio.h>
#include <stdlib.h>
#include <math.h>

#define RAD_CONV_FAC (1.0f/60.0f)*(M_PI/180.0f)
#define DEG_CONV_FAC 180.0f/M_PI

/*

Compile with: nvcc -O3 -Xptxas="-v" -arch=sm_30  galaxy_distribution.cu
Run with: time ./a.out real.txt sim.txt

*/

/* ---------- Device code ---------- */

/*   
     N = number of galaxies (in one list)
     a1 = ascension (alpha) for first galaxy list
     d1 = declination (delta) for first galaxy list
     a2 = ascension for second glaxy list
     d2 = declination for second galaxy list
*/
__global__ void theta_calc(int N, float* a1, float* d1, float* a2, float* d2, int* hist) {
     
     // Thread index
     int i = blockDim.x * blockIdx.x + threadIdx.x;

     if (i < N) {
          float angle, temp;
          int j, bin_nr;
          // Each thread multiplies one value (their index) of the first galaxy list against all the values in the second galaxy list
          for (j = 0; j < N; j++) {
               temp = sinf(d1[i])*sinf(d2[j])+cosf(d1[i])*cosf(d2[j])*cosf(a1[i]-a2[j]);
               angle = acosf(fminf(temp, 1.0f));
               // Convert to degree and determine bin number
               bin_nr = floor((angle*DEG_CONV_FAC)/0.25);
               // Increment histogram
               atomicAdd(&hist[bin_nr], 1);
          }
     }
}

void debug (int* dd, int* dr, int* rr, float* omega_hist, int bins) {

      // Save histograms to files for analysis
     FILE *out_file = fopen("output.txt", "w");
     FILE *out_file2 = fopen("output2.txt", "w");
     FILE *out_file3 = fopen("output3.txt", "w");
     FILE *out_file4 = fopen("output4.txt", "w");
     
     long int dd_tot = 0;
     long int dr_tot = 0;
     long int rr_tot = 0;

     for(int k = 0; k < bins; k++) {
          fprintf(out_file, "%d\n", dd[k]);
          fprintf(out_file2, "%d\n", dr[k]);
          fprintf(out_file3, "%d\n", rr[k]);
          fprintf(out_file4, "%f\n", omega_hist[k]);
          dd_tot += dd[k];
          dr_tot += dr[k];
          rr_tot += rr[k];
     }
     
     printf("Total entries in histogram dd: %ld\n", dd_tot);
     printf("Total entries in histogram dr: %ld\n", dr_tot);
     printf("Total entries in histogram rr: %ld\n", rr_tot);
}

void omega_calc(int* dd, int* dr, int* rr, float* omega_hist, int bins) {
     
     // Calculate omega (difference between two equally big sets) with the three histograms
     for (int m = 0; m < bins; m++) {
          omega_hist[m] = (float)((float)dd[m]-2.0f*(float)dr[m]+(float)rr[m])/(float)rr[m];
          if (m < 15) {
               printf("Omega %d: %f\n", m, omega_hist[m]);
          }
     }
}

/* ---------- Host code ---------- */

int main (int agrc, char *argv[]) {

     // Allocate arrays for the values
     int N = 100000;
     float* real_values_asc;
     float* real_values_dec;
     float* sim_values_asc;
     float* sim_values_dec;

     cudaMallocManaged(&real_values_asc, N*sizeof(float)); 
     cudaMallocManaged(&real_values_dec, N*sizeof(float));      
     cudaMallocManaged(&sim_values_asc, N*sizeof(float));      
     cudaMallocManaged(&sim_values_dec, N*sizeof(float));

     // Allocate arrays for the histograms
     int bins = 180*4;
     int* dd;
     int* dr;
     int* rr;
     float* omega_hist = (float*)malloc(bins*sizeof(float));

     cudaMallocManaged(&dd, bins*sizeof(int));
     cudaMallocManaged(&dr, bins*sizeof(int));
     cudaMallocManaged(&rr, bins*sizeof(int));

     
     // Read values from the files
     FILE * file_real = fopen(argv[1], "r");
     FILE * file_sim = fopen(argv[2], "r");
     if(!file_real || !file_sim) {
          printf("Something went wrong with the file reading...\n");
          exit(-1);
     }
     
     for (int i = 0; i < 2*N; i++) { // The values are read one by one, not in pairs, so we need to double the iteration value
          if(i%2 == 0) { // First column, right ascension
               fscanf(file_real, "%f", &real_values_asc[i/2]);
               // Convert to radians
               real_values_asc[i/2] *= RAD_CONV_FAC;
               fscanf(file_sim, "%f", &sim_values_asc[i/2]);
               // Convert to radians
               sim_values_asc[i/2] *= RAD_CONV_FAC;
          }
          else { // Second column, declination
               fscanf(file_real, "%f", &real_values_dec[i/2]);
               // Convert to radians
               real_values_dec[i/2] *= RAD_CONV_FAC;
               fscanf(file_sim, "%f", &sim_values_dec[i/2]);
               // Convert to radians
               sim_values_dec[i/2] *= RAD_CONV_FAC;
          }

          // Initialize the histograms
          if(i < bins) {
               dd[i] = 0;
               dr[i] = 0;
               rr[i] = 0;
          }
     }
     
     fclose(file_real);
     fclose(file_sim);
     
     int threads_in_block = 512;
     int blocks_in_grid = (N+threads_in_block-1)/threads_in_block;

     // GPU function
     theta_calc<<<blocks_in_grid, threads_in_block>>>(N, real_values_asc, real_values_dec, real_values_asc, real_values_dec, dd);
     theta_calc<<<blocks_in_grid, threads_in_block>>>(N, real_values_asc, real_values_dec, sim_values_asc, sim_values_dec, dr);
     theta_calc<<<blocks_in_grid, threads_in_block>>>(N, sim_values_asc, sim_values_dec, sim_values_asc, sim_values_dec, rr);

     // Wait for GPU to finish
     cudaDeviceSynchronize();

     // Calculate omega values
     omega_calc(dd, dr, rr, omega_hist, bins);
     
     //debug(dd, dr, rr, omega_hist, bins);

     // Free all the things
     cudaFree(real_values_asc);
     cudaFree(real_values_dec);
     cudaFree(sim_values_asc);
     cudaFree(sim_values_dec);
     cudaFree(dd);
     cudaFree(dr);
     cudaFree(rr);
     free(omega_hist);
     
}
	.file	"tmpxft_00371efb_00000000-6_galaxy_distribution.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"w"
.LC1:
	.string	"output.txt"
.LC2:
	.string	"output2.txt"
.LC3:
	.string	"output3.txt"
.LC4:
	.string	"output4.txt"
.LC5:
	.string	"%d\n"
.LC6:
	.string	"%f\n"
.LC7:
	.string	"Total entries in histogram dd: %ld\n"
.LC8:
	.string	"Total entries in histogram dr: %ld\n"
.LC9:
	.string	"Total entries in histogram rr: %ld\n"
	.text
	.globl	_Z5debugPiS_S_Pfi
	.type	_Z5debugPiS_S_Pfi, @function
_Z5debugPiS_S_Pfi:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	leaq	.LC1(%rip), %rdi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leaq	.LC0(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	movq	%r12, %rsi
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	%r8d, 60(%rsp)
	call	fopen@PLT
	movq	%r12, %rsi
	leaq	.LC2(%rip), %rdi
	movq	%rax, 24(%rsp)
	call	fopen@PLT
	movq	%r12, %rsi
	leaq	.LC3(%rip), %rdi
	movq	%rax, 32(%rsp)
	call	fopen@PLT
	movq	%r12, %rsi
	leaq	.LC4(%rip), %rdi
	xorl	%r12d, %r12d
	movq	%rax, 40(%rsp)
	call	fopen@PLT
	movq	%rax, 48(%rsp)
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)
	movq	%rax, 8(%rsp)
.L3:
	cmpl	%r12d, 60(%rsp)
	jle	.L7
	movl	0(%r13,%r12,4), %ecx
	movq	24(%rsp), %rdi
	leaq	.LC5(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	(%rbx,%r12,4), %ecx
	movq	32(%rsp), %rdi
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	0(%rbp,%r12,4), %ecx
	movq	40(%rsp), %rdi
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movq	48(%rsp), %rdi
	leaq	.LC6(%rip), %rdx
	movb	$1, %al
	movl	$2, %esi
	cvtss2sd	(%r15,%r12,4), %xmm0
	call	__fprintf_chk@PLT
	movslq	0(%r13,%r12,4), %rax
	addq	%rax, %r14
	movslq	(%rbx,%r12,4), %rax
	addq	%rax, 8(%rsp)
	movslq	0(%rbp,%r12,4), %rax
	incq	%r12
	addq	%rax, 16(%rsp)
	jmp	.L3
.L7:
	movq	%r14, %rdx
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdx
	leaq	.LC8(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	16(%rsp), %rdx
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	movl	$2, %edi
	popq	%rbx
	.cfi_def_cfa_offset 48
	leaq	.LC9(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z5debugPiS_S_Pfi, .-_Z5debugPiS_S_Pfi
	.section	.rodata.str1.1
.LC10:
	.string	"Omega %d: %f\n"
	.text
	.globl	_Z10omega_calcPiS_S_Pfi
	.type	_Z10omega_calcPiS_S_Pfi, @function
_Z10omega_calcPiS_S_Pfi:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	pushq	%r9
	.cfi_def_cfa_offset 64
.L9:
	cmpl	%ebp, %ebx
	jle	.L13
	cvtsi2ssl	0(%r13,%rbp,4), %xmm1
	cvtsi2ssl	(%r12,%rbp,4), %xmm0
	cvtsi2ssl	(%r14,%rbp,4), %xmm2
	addss	%xmm1, %xmm1
	subss	%xmm1, %xmm0
	addss	%xmm2, %xmm0
	divss	%xmm2, %xmm0
	movss	%xmm0, (%r15,%rbp,4)
	cmpq	$14, %rbp
	ja	.L10
	movl	%ebp, %edx
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
.L10:
	incq	%rbp
	jmp	.L9
.L13:
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10omega_calcPiS_S_Pfi, .-_Z10omega_calcPiS_S_Pfi
	.globl	_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi
	.type	_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi, @function
_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10theta_calciPfS_S_S_Pi(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L14:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi, .-_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi
	.globl	_Z10theta_calciPfS_S_S_Pi
	.type	_Z10theta_calciPfS_S_S_Pi, @function
_Z10theta_calciPfS_S_S_Pi:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi
	.cfi_endproc
.LFE2055:
	.size	_Z10theta_calciPfS_S_S_Pi, .-_Z10theta_calciPfS_S_S_Pi
	.section	.rodata.str1.1
.LC11:
	.string	"r"
.LC12:
	.string	"Something went wrong with the file reading...\n"
.LC13:
	.string	"%f"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1, %edx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC11(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	movl	$400000, %esi
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$400000, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$400000, %esi
	call	cudaMallocManaged@PLT
	movl	$1, %edx
	movl	$400000, %esi
	leaq	32(%rsp), %rdi
	call	cudaMallocManaged@PLT
	movl	$2880, %edi
	call	malloc@PLT
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	movl	$2880, %esi
	movq	%rax, %r13
	call	cudaMallocManaged@PLT
	leaq	48(%rsp), %rdi
	movl	$1, %edx
	movl	$2880, %esi
	call	cudaMallocManaged@PLT
	leaq	56(%rsp), %rdi
	movl	$1, %edx
	movl	$2880, %esi
	call	cudaMallocManaged@PLT
	movq	8(%rbx), %rdi
	movq	%rbp, %rsi
	call	fopen@PLT
	movq	16(%rbx), %rdi
	movq	%rbp, %rsi
	movq	%rax, %r12
	call	fopen@PLT
	testq	%r12, %r12
	je	.L32
	movq	%rax, %rbp
	xorl	%r15d, %r15d
	leaq	.LC13(%rip), %r14
	testq	%rax, %rax
	jne	.L20
.L32:
	movl	$2, %edi
	leaq	.LC12(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L22:
	addq	16(%rsp), %rdx
	movq	%r14, %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movq	16(%rsp), %rax
	movq	%r14, %rsi
	movq	%rbp, %rdi
	movq	32(%rsp), %rdx
	addq	%rbx, %rax
	cvtss2sd	(%rax), %xmm0
	mulsd	.LC14(%rip), %xmm0
	addq	%rbx, %rdx
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax)
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	addq	32(%rsp), %rbx
.L35:
	cvtss2sd	(%rbx), %xmm0
	mulsd	.LC14(%rip), %xmm0
	cmpq	$719, %r15
	leaq	1(%r15), %rax
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx)
	ja	.L24
	movq	40(%rsp), %rdx
	xorl	%ecx, %ecx
	xorl	%esi, %esi
	xorl	%edi, %edi
	movl	%ecx, (%rdx,%r15,4)
	movq	48(%rsp), %rdx
	movl	%esi, (%rdx,%r15,4)
	movq	56(%rsp), %rdx
	movl	%edi, (%rdx,%r15,4)
	movq	%rax, %r15
.L20:
	movl	%r15d, %ebx
	sarl	%ebx
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rdx
	testl	$1, %r15d
	jne	.L22
	addq	8(%rsp), %rdx
	movq	%r14, %rsi
	movq	%r12, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movq	8(%rsp), %rax
	movq	%r14, %rsi
	movq	%rbp, %rdi
	movq	24(%rsp), %rdx
	addq	%rbx, %rax
	cvtss2sd	(%rax), %xmm0
	mulsd	.LC14(%rip), %xmm0
	addq	%rbx, %rdx
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax)
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	addq	24(%rsp), %rbx
	jmp	.L35
.L24:
	movq	%rax, %r15
	cmpq	$200000, %rax
	jne	.L20
	movq	%r12, %rdi
	call	fclose@PLT
	movq	%rbp, %rdi
	call	fclose@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1073741873, %edi
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$2, %rdi
	movq	%rdx, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$100000, %edi
	movq	40(%rsp), %r9
	movq	%rdx, %r8
	movq	%rsi, %rcx
	call	_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi
.L27:
	movl	$8388609, %edx
	movl	$1073741873, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	48(%rsp), %r9
	movq	32(%rsp), %r8
	movl	$100000, %edi
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	call	_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi
.L28:
	movl	$8388609, %edx
	movl	$1073741873, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 76(%rsp)
	movl	$1, 84(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$100000, %edi
	movq	56(%rsp), %r9
	movq	%rdx, %r8
	movq	%rsi, %rcx
	call	_Z39__device_stub__Z10theta_calciPfS_S_S_PiiPfS_S_S_Pi
.L29:
	call	cudaDeviceSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$720, %r8d
	movq	40(%rsp), %rdi
	movq	%r13, %rcx
	call	_Z10omega_calcPiS_S_Pfi
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC15:
	.string	"_Z10theta_calciPfS_S_S_Pi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10theta_calciPfS_S_S_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC14:
	.long	1753077904
	.long	1060311115
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>

#define RAD_CONV_FAC (1.0f/60.0f)*(M_PI/180.0f)
#define DEG_CONV_FAC 180.0f/M_PI

/*

Compile with: nvcc -O3 -Xptxas="-v" -arch=sm_30  galaxy_distribution.cu
Run with: time ./a.out real.txt sim.txt

*/

/* ---------- Device code ---------- */

/*   
     N = number of galaxies (in one list)
     a1 = ascension (alpha) for first galaxy list
     d1 = declination (delta) for first galaxy list
     a2 = ascension for second glaxy list
     d2 = declination for second galaxy list
*/
__global__ void theta_calc(int N, float* a1, float* d1, float* a2, float* d2, int* hist) {
     
     // Thread index
     int i = blockDim.x * blockIdx.x + threadIdx.x;

     if (i < N) {
          float angle, temp;
          int j, bin_nr;
          // Each thread multiplies one value (their index) of the first galaxy list against all the values in the second galaxy list
          for (j = 0; j < N; j++) {
               temp = sinf(d1[i])*sinf(d2[j])+cosf(d1[i])*cosf(d2[j])*cosf(a1[i]-a2[j]);
               angle = acosf(fminf(temp, 1.0f));
               // Convert to degree and determine bin number
               bin_nr = floor((angle*DEG_CONV_FAC)/0.25);
               // Increment histogram
               atomicAdd(&hist[bin_nr], 1);
          }
     }
}

void debug (int* dd, int* dr, int* rr, float* omega_hist, int bins) {

      // Save histograms to files for analysis
     FILE *out_file = fopen("output.txt", "w");
     FILE *out_file2 = fopen("output2.txt", "w");
     FILE *out_file3 = fopen("output3.txt", "w");
     FILE *out_file4 = fopen("output4.txt", "w");
     
     long int dd_tot = 0;
     long int dr_tot = 0;
     long int rr_tot = 0;

     for(int k = 0; k < bins; k++) {
          fprintf(out_file, "%d\n", dd[k]);
          fprintf(out_file2, "%d\n", dr[k]);
          fprintf(out_file3, "%d\n", rr[k]);
          fprintf(out_file4, "%f\n", omega_hist[k]);
          dd_tot += dd[k];
          dr_tot += dr[k];
          rr_tot += rr[k];
     }
     
     printf("Total entries in histogram dd: %ld\n", dd_tot);
     printf("Total entries in histogram dr: %ld\n", dr_tot);
     printf("Total entries in histogram rr: %ld\n", rr_tot);
}

void omega_calc(int* dd, int* dr, int* rr, float* omega_hist, int bins) {
     
     // Calculate omega (difference between two equally big sets) with the three histograms
     for (int m = 0; m < bins; m++) {
          omega_hist[m] = (float)((float)dd[m]-2.0f*(float)dr[m]+(float)rr[m])/(float)rr[m];
          if (m < 15) {
               printf("Omega %d: %f\n", m, omega_hist[m]);
          }
     }
}

/* ---------- Host code ---------- */

int main (int agrc, char *argv[]) {

     // Allocate arrays for the values
     int N = 100000;
     float* real_values_asc;
     float* real_values_dec;
     float* sim_values_asc;
     float* sim_values_dec;

     hipMallocManaged(&real_values_asc, N*sizeof(float)); 
     hipMallocManaged(&real_values_dec, N*sizeof(float));      
     hipMallocManaged(&sim_values_asc, N*sizeof(float));      
     hipMallocManaged(&sim_values_dec, N*sizeof(float));

     // Allocate arrays for the histograms
     int bins = 180*4;
     int* dd;
     int* dr;
     int* rr;
     float* omega_hist = (float*)malloc(bins*sizeof(float));

     hipMallocManaged(&dd, bins*sizeof(int));
     hipMallocManaged(&dr, bins*sizeof(int));
     hipMallocManaged(&rr, bins*sizeof(int));

     
     // Read values from the files
     FILE * file_real = fopen(argv[1], "r");
     FILE * file_sim = fopen(argv[2], "r");
     if(!file_real || !file_sim) {
          printf("Something went wrong with the file reading...\n");
          exit(-1);
     }
     
     for (int i = 0; i < 2*N; i++) { // The values are read one by one, not in pairs, so we need to double the iteration value
          if(i%2 == 0) { // First column, right ascension
               fscanf(file_real, "%f", &real_values_asc[i/2]);
               // Convert to radians
               real_values_asc[i/2] *= RAD_CONV_FAC;
               fscanf(file_sim, "%f", &sim_values_asc[i/2]);
               // Convert to radians
               sim_values_asc[i/2] *= RAD_CONV_FAC;
          }
          else { // Second column, declination
               fscanf(file_real, "%f", &real_values_dec[i/2]);
               // Convert to radians
               real_values_dec[i/2] *= RAD_CONV_FAC;
               fscanf(file_sim, "%f", &sim_values_dec[i/2]);
               // Convert to radians
               sim_values_dec[i/2] *= RAD_CONV_FAC;
          }

          // Initialize the histograms
          if(i < bins) {
               dd[i] = 0;
               dr[i] = 0;
               rr[i] = 0;
          }
     }
     
     fclose(file_real);
     fclose(file_sim);
     
     int threads_in_block = 512;
     int blocks_in_grid = (N+threads_in_block-1)/threads_in_block;

     // GPU function
     theta_calc<<<blocks_in_grid, threads_in_block>>>(N, real_values_asc, real_values_dec, real_values_asc, real_values_dec, dd);
     theta_calc<<<blocks_in_grid, threads_in_block>>>(N, real_values_asc, real_values_dec, sim_values_asc, sim_values_dec, dr);
     theta_calc<<<blocks_in_grid, threads_in_block>>>(N, sim_values_asc, sim_values_dec, sim_values_asc, sim_values_dec, rr);

     // Wait for GPU to finish
     hipDeviceSynchronize();

     // Calculate omega values
     omega_calc(dd, dr, rr, omega_hist, bins);
     
     //debug(dd, dr, rr, omega_hist, bins);

     // Free all the things
     hipFree(real_values_asc);
     hipFree(real_values_dec);
     hipFree(sim_values_asc);
     hipFree(sim_values_dec);
     hipFree(dd);
     hipFree(dr);
     hipFree(rr);
     free(omega_hist);
     
}
	.text
	.file	"galaxy_distribution.hip"
	.globl	_Z25__device_stub__theta_calciPfS_S_S_Pi # -- Begin function _Z25__device_stub__theta_calciPfS_S_S_Pi
	.type	_Z25__device_stub__theta_calciPfS_S_S_Pi,@function
_Z25__device_stub__theta_calciPfS_S_S_Pi: # @_Z25__device_stub__theta_calciPfS_S_S_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10theta_calciPfS_S_S_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__theta_calciPfS_S_S_Pi, .Lfunc_end0-_Z25__device_stub__theta_calciPfS_S_S_Pi
	.cfi_endproc
                                        # -- End function
	.globl	_Z5debugPiS_S_Pfi               # -- Begin function _Z5debugPiS_S_Pfi
	.type	_Z5debugPiS_S_Pfi,@function
_Z5debugPiS_S_Pfi:                      # @_Z5debugPiS_S_Pfi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebx
	movq	%rcx, %r14
	movq	%rdx, %r13
	movq	%rsi, %r15
	movq	%rdi, %r12
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %rbp
	movl	$.L.str.2, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$.L.str.3, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	$.L.str.4, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testl	%ebx, %ebx
	jle	.LBB1_1
# %bb.3:                                # %.lr.ph.preheader
	movl	%ebx, %ecx
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	xorl	%r14d, %r14d
	movq	%r12, (%rsp)                    # 8-byte Spill
	movq	%r15, 32(%rsp)                  # 8-byte Spill
	movq	%r13, 24(%rsp)                  # 8-byte Spill
	xorl	%r12d, %r12d
	movq	%rbp, 16(%rsp)                  # 8-byte Spill
	xorl	%ebp, %ebp
	xorl	%ebx, %ebx
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	32(%rsp), %r15                  # 8-byte Reload
	movq	24(%rsp), %r13                  # 8-byte Reload
.LBB1_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	(%rsp), %rax                    # 8-byte Reload
	movl	(%rax,%r14,4), %edx
	movl	$.L.str.5, %esi
	movq	16(%rsp), %rdi                  # 8-byte Reload
	xorl	%eax, %eax
	callq	fprintf
	movl	(%r15,%r14,4), %edx
	movl	$.L.str.5, %esi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	xorl	%eax, %eax
	callq	fprintf
	movl	(%r13,%r14,4), %edx
	movl	$.L.str.5, %esi
	movq	56(%rsp), %rdi                  # 8-byte Reload
	xorl	%eax, %eax
	callq	fprintf
	movq	40(%rsp), %rax                  # 8-byte Reload
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r14,4), %xmm0
	movl	$.L.str.6, %esi
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movb	$1, %al
	callq	fprintf
	movq	(%rsp), %rax                    # 8-byte Reload
	movslq	(%rax,%r14,4), %rax
	addq	%rax, %rbx
	movslq	(%r15,%r14,4), %rax
	addq	%rax, %rbp
	movslq	(%r13,%r14,4), %rax
	addq	%rax, %r12
	incq	%r14
	cmpq	%r14, 48(%rsp)                  # 8-byte Folded Reload
	jne	.LBB1_4
	jmp	.LBB1_2
.LBB1_1:
	xorl	%ebx, %ebx
	xorl	%ebp, %ebp
	xorl	%r12d, %r12d
.LBB1_2:                                # %._crit_edge
	movl	$.L.str.7, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.8, %edi
	movq	%rbp, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.9, %edi
	movq	%r12, %rsi
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.Lfunc_end1:
	.size	_Z5debugPiS_S_Pfi, .Lfunc_end1-_Z5debugPiS_S_Pfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z10omega_calcPiS_S_Pfi         # -- Begin function _Z10omega_calcPiS_S_Pfi
	.type	_Z10omega_calcPiS_S_Pfi,@function
_Z10omega_calcPiS_S_Pfi:                # @_Z10omega_calcPiS_S_Pfi
	.cfi_startproc
# %bb.0:
	testl	%r8d, %r8d
	jle	.LBB2_6
# %bb.1:                                # %.lr.ph.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	movl	%r8d, %ebp
	xorl	%r13d, %r13d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ssl	(%r12,%r13,4), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ssl	(%r15,%r13,4), %xmm1
	addss	%xmm1, %xmm1
	subss	%xmm1, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ssl	(%r14,%r13,4), %xmm1
	addss	%xmm1, %xmm0
	divss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r13,4)
	cmpq	$14, %r13
	ja	.LBB2_4
# %bb.3:                                #   in Loop: Header=BB2_2 Depth=1
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.10, %edi
	movl	%r13d, %esi
	movb	$1, %al
	callq	printf
.LBB2_4:                                #   in Loop: Header=BB2_2 Depth=1
	incq	%r13
	cmpq	%r13, %rbp
	jne	.LBB2_2
# %bb.5:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB2_6:                                # %._crit_edge
	retq
.Lfunc_end2:
	.size	_Z10omega_calcPiS_S_Pfi, .Lfunc_end2-_Z10omega_calcPiS_S_Pfi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x3f33104b687dd890              # double 2.9088822383672389E-4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r13
	leaq	16(%rsp), %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	56(%rsp), %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	48(%rsp), %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$2880, %edi                     # imm = 0xB40
	callq	malloc
	movq	%rax, %rbx
	leaq	40(%rsp), %rdi
	movl	$2880, %esi                     # imm = 0xB40
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	32(%rsp), %rdi
	movl	$2880, %esi                     # imm = 0xB40
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	24(%rsp), %rdi
	movl	$2880, %esi                     # imm = 0xB40
	movl	$1, %edx
	callq	hipMallocManaged
	movq	8(%r13), %rdi
	movl	$.L.str.11, %esi
	callq	fopen
	movq	%rax, %r12
	movq	16(%r13), %rdi
	movl	$.L.str.11, %esi
	callq	fopen
	testq	%r12, %r12
	je	.LBB3_5
# %bb.1:
	movq	%rax, %r13
	testq	%rax, %rax
	je	.LBB3_5
# %bb.2:                                # %.preheader.preheader
	movq	%rbx, 64(%rsp)                  # 8-byte Spill
	xorl	%ebp, %ebp
	xorl	%ebx, %ebx
.LBB3_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %r14d
	shrl	%r14d
	leaq	(,%r14,4), %rdx
	testb	$1, %bl
	jne	.LBB3_6
# %bb.4:                                #   in Loop: Header=BB3_3 Depth=1
	addq	16(%rsp), %rdx
	movl	$.L.str.13, %esi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	16(%rsp), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r14,4), %xmm0
	movsd	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax,%r14,4)
	leaq	56(%rsp), %r15
	jmp	.LBB3_7
.LBB3_6:                                #   in Loop: Header=BB3_3 Depth=1
	addq	8(%rsp), %rdx
	movl	$.L.str.13, %esi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	8(%rsp), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r14,4), %xmm0
	movsd	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax,%r14,4)
	leaq	48(%rsp), %r15
.LBB3_7:                                #   in Loop: Header=BB3_3 Depth=1
	leaq	(,%r14,4), %rdx
	addq	(%r15), %rdx
	movl	$.L.str.13, %esi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r14,4), %xmm0
	mulsd	.LCPI3_0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rax,%r14,4)
	cmpq	$719, %rbx                      # imm = 0x2CF
	ja	.LBB3_9
# %bb.8:                                #   in Loop: Header=BB3_3 Depth=1
	movq	40(%rsp), %rax
	movl	%ebp, (%rax,%rbx,4)
	movq	32(%rsp), %rax
	movl	%ebp, (%rax,%rbx,4)
	movq	24(%rsp), %rax
	movl	%ebp, (%rax,%rbx,4)
.LBB3_9:                                #   in Loop: Header=BB3_3 Depth=1
	incq	%rbx
	cmpq	$200000, %rbx                   # imm = 0x30D40
	jne	.LBB3_3
# %bb.10:
	movabsq	$4294967492, %r14               # imm = 0x1000000C4
	movq	%r12, %rdi
	callq	fclose
	movq	%r13, %rdi
	callq	fclose
	leaq	316(%r14), %r15
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_12
# %bb.11:
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	movq	40(%rsp), %r9
	movl	$100000, %edi                   # imm = 0x186A0
	movq	%rcx, %rsi
	movq	%rdx, %r8
	callq	_Z25__device_stub__theta_calciPfS_S_S_Pi
.LBB3_12:
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_14
# %bb.13:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rcx
	movq	48(%rsp), %r8
	movq	32(%rsp), %r9
	movl	$100000, %edi                   # imm = 0x186A0
	callq	_Z25__device_stub__theta_calciPfS_S_S_Pi
.LBB3_14:
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_16
# %bb.15:
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	24(%rsp), %r9
	movl	$100000, %edi                   # imm = 0x186A0
	movq	%rcx, %rsi
	movq	%rdx, %r8
	callq	_Z25__device_stub__theta_calciPfS_S_S_Pi
.LBB3_16:
	callq	hipDeviceSynchronize
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	64(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rcx
	movl	$720, %r8d                      # imm = 0x2D0
	callq	_Z10omega_calcPiS_S_Pfi
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_5:
	.cfi_def_cfa_offset 128
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$-1, %edi
	callq	exit
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10theta_calciPfS_S_S_Pi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10theta_calciPfS_S_S_Pi,@object # @_Z10theta_calciPfS_S_S_Pi
	.section	.rodata,"a",@progbits
	.globl	_Z10theta_calciPfS_S_S_Pi
	.p2align	3, 0x0
_Z10theta_calciPfS_S_S_Pi:
	.quad	_Z25__device_stub__theta_calciPfS_S_S_Pi
	.size	_Z10theta_calciPfS_S_S_Pi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"output.txt"
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"w"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"output2.txt"
	.size	.L.str.2, 12

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"output3.txt"
	.size	.L.str.3, 12

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"output4.txt"
	.size	.L.str.4, 12

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d\n"
	.size	.L.str.5, 4

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%f\n"
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Total entries in histogram dd: %ld\n"
	.size	.L.str.7, 36

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Total entries in histogram dr: %ld\n"
	.size	.L.str.8, 36

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Total entries in histogram rr: %ld\n"
	.size	.L.str.9, 36

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Omega %d: %f\n"
	.size	.L.str.10, 14

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"r"
	.size	.L.str.11, 2

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"%f"
	.size	.L.str.13, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10theta_calciPfS_S_S_Pi"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Something went wrong with the file reading..."
	.size	.Lstr, 46

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__theta_calciPfS_S_S_Pi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10theta_calciPfS_S_S_Pi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10theta_calciPfS_S_S_Pi ; -- Begin function _Z10theta_calciPfS_S_S_Pi
	.globl	_Z10theta_calciPfS_S_S_Pi
	.p2align	8
	.type	_Z10theta_calciPfS_S_S_Pi,@function
_Z10theta_calciPfS_S_S_Pi:              ; @_Z10theta_calciPfS_S_S_Pi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s14, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_max_i32_e32 v0, 0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s14, v0
	s_cbranch_execz .LBB0_25
; %bb.1:                                ; %.lr.ph
	s_load_b256 s[4:11], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[2:3], s[0:1], 0x28
	s_mov_b32 s12, 0x54442d18
	s_mov_b32 s15, 0x7fffff
	v_mov_b32_e32 v6, 1
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_mov_b32_e32 v1, 0
	s_mov_b32 s13, 0x400921fb
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_mov_b32 s4, 0xb94c1982
	s_mov_b32 s5, 0x37d75334
	s_mov_b32 s6, 0x3d1c21a7
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v7, v[2:3], off
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0x7fffffff, v7
	v_cmp_ngt_f32_e64 s16, 0x48000000, |v7|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v0, 23, v8
	v_and_or_b32 v15, v8, s15, 0x800000
	v_add_nc_u32_e32 v16, 0xffffff88, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s16
	s_xor_b32 s7, exec_lo, s0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[9:10], null, 0xfe5163ab, v15, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v16
	v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v10
	v_mad_u64_u32 v[10:11], null, 0x3c439041, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v11
	v_mad_u64_u32 v[11:12], null, 0xdb629599, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v12 :: v_dual_cndmask_b32 v9, v11, v9
	v_mad_u64_u32 v[12:13], null, 0xf534ddc0, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, v13
	v_cndmask_b32_e32 v10, v12, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v15, v[0:1]
	v_mov_b32_e32 v0, v14
	v_add_nc_u32_e32 v14, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v15, v[0:1]
	v_cmp_lt_u32_e64 s0, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s0
	v_mov_b32_e32 v0, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v20, v17, v12, vcc_lo
	v_cndmask_b32_e64 v9, v10, v9, s0
	v_add_nc_u32_e32 v14, v19, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v15, v[0:1]
	v_cmp_lt_u32_e64 s1, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, v18, v13, vcc_lo
	v_cndmask_b32_e64 v0, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	v_cndmask_b32_e32 v13, v13, v11, vcc_lo
	v_cndmask_b32_e64 v12, v18, v20, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v0, v0, v14
	v_cndmask_b32_e64 v14, v17, v18, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v20, v13, s0
	v_cndmask_b32_e64 v13, v13, v10, s0
	v_sub_nc_u32_e32 v18, 32, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v14, v12, s1
	v_cndmask_b32_e64 v12, v12, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v13, s1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v9, v13, v9, s1
	v_alignbit_b32 v19, v14, v12, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v11, v12, v17, v18
	v_cndmask_b32_e32 v0, v19, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v11, v12, vcc_lo
	v_alignbit_b32 v14, v17, v9, v18
	v_bfe_u32 v11, v0, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v0, v10, 30
	v_cndmask_b32_e32 v14, v14, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, 0, v11
	v_alignbit_b32 v10, v10, v14, 30
	v_alignbit_b32 v9, v14, v9, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v13
	v_xor_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v13
	v_lshrrev_b32_e32 v13, 29, v0
	v_clz_i32_u32_e32 v17, v12
	v_lshrrev_b32_e32 v0, 30, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v13, 31, v13
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v18, 0.5, v13
	v_sub_nc_u32_e32 v14, 31, v17
	v_lshlrev_b32_e32 v19, 23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v12, v10, v14
	v_alignbit_b32 v9, v10, v9, v14
	v_sub_nc_u32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v10, v12, v9, 9
	v_lshrrev_b32_e32 v12, 9, v12
	v_clz_i32_u32_e32 v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v20, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v10, v9, v20
	v_or_b32_e32 v10, v12, v18
	v_add_lshl_u32 v12, v14, v17, 23
	v_lshrrev_b32_e32 v9, 9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	v_sub_nc_u32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fc90fda, v10, -v14
	v_add_nc_u32_e32 v9, 0x33000000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, 0x33a22168, v10
	v_add_nc_u32_e32 v10, v11, v0
	v_or_b32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0x3fc90fda, v9
	v_add_f32_e32 v9, v14, v12
.LBB0_4:                                ; %Flow90
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s7
	v_mul_f32_e64 v0, 0x3f22f983, |v7|
	s_delay_alu instid0(VALU_DEP_1)
	v_rndne_f32_e32 v0, v0
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0xbfc90fda, v0, |v7|
	v_cvt_i32_f32_e32 v10, v0
	v_fmac_f32_e32 v9, 0xb3a22168, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0xa7c234c4, v0
; %bb.6:                                ; %_ZL4sinff.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v11, v1, s[10:11]
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s17, 0x48000000, |v11|
	v_readfirstlane_b32 s0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s17
	s_and_b32 s7, s0, 0x7fffffff
	s_cbranch_vccz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 s0, s7, 0x7fffff
	s_lshr_b32 s1, s7, 23
	s_bitset1_b32 s0, 23
	s_addk_i32 s1, 0xff88
	s_mul_hi_u32 s18, s0, 0xfe5163ab
	s_mul_i32 s19, s0, 0x3c439041
	s_mul_hi_u32 s20, s0, 0x3c439041
	s_add_u32 s18, s18, s19
	s_addc_u32 s19, 0, s20
	s_mul_i32 s20, s0, 0xdb629599
	s_mul_hi_u32 s21, s0, 0xdb629599
	s_add_u32 s19, s19, s20
	s_addc_u32 s20, 0, s21
	s_mul_i32 s21, s0, 0xf534ddc0
	s_mul_hi_u32 s22, s0, 0xf534ddc0
	s_add_u32 s20, s20, s21
	s_addc_u32 s21, 0, s22
	s_mul_i32 s22, s0, 0xfc2757d1
	s_mul_hi_u32 s23, s0, 0xfc2757d1
	s_add_u32 s21, s21, s22
	s_addc_u32 s22, 0, s23
	s_mul_i32 s23, s0, 0x4e441529
	s_mul_hi_u32 s24, s0, 0x4e441529
	s_add_u32 s22, s22, s23
	s_addc_u32 s23, 0, s24
	s_cmp_gt_u32 s1, 63
	s_mul_i32 s24, s0, 0xfe5163ab
	s_mul_hi_u32 s25, s0, 0xa2f9836e
	s_mul_i32 s0, s0, 0xa2f9836e
	s_cselect_b32 s26, s19, s21
	s_cselect_b32 s18, s18, s20
	s_cselect_b32 s19, s24, s19
	s_add_u32 s0, s23, s0
	s_addc_u32 s23, 0, s25
	s_cmp_gt_u32 s1, 63
	s_cselect_b32 s24, 0xffffffc0, 0
	s_cselect_b32 s20, s20, s22
	s_cselect_b32 s0, s21, s0
	s_cselect_b32 s21, s22, s23
	s_add_i32 s24, s24, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s24, 31
	s_cselect_b32 s1, 0xffffffe0, 0
	s_cselect_b32 s22, s20, s0
	s_cselect_b32 s0, s0, s21
	s_cselect_b32 s20, s26, s20
	s_cselect_b32 s21, s18, s26
	s_cselect_b32 s18, s19, s18
	s_add_i32 s1, s1, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s1, 31
	s_cselect_b32 s19, 0xffffffe0, 0
	s_cselect_b32 s0, s22, s0
	s_cselect_b32 s22, s20, s22
	s_cselect_b32 s20, s21, s20
	s_cselect_b32 s18, s18, s21
	s_add_i32 s19, s19, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s1, 32, s19
	s_cmp_eq_u32 s19, 0
	v_mov_b32_e32 v12, s1
	s_cselect_b32 s19, -1, 0
	v_alignbit_b32 v13, s0, s22, v12
	v_alignbit_b32 v14, s22, s20, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s1, v13
	v_cndmask_b32_e64 v13, v14, s22, s19
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v14, s0, v13, 30
	s_bfe_u32 s1, s0, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s21, 0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v14, s21, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v17, v14
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v19, 23, v17
	v_alignbit_b32 v12, s20, s18, v12
	v_sub_nc_u32_e32 v18, 31, v17
	v_cndmask_b32_e64 v12, v12, s20, s19
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v13, v13, v12, 30
	v_alignbit_b32 v12, v12, s18, 30
	s_lshr_b32 s18, s0, 29
	s_lshr_b32 s0, s0, 30
	s_lshl_b32 s18, s18, 31
	v_xor_b32_e32 v13, s21, v13
	v_xor_b32_e32 v12, s21, v12
	s_or_b32 s19, s18, 0.5
	s_add_i32 s1, s1, s0
	v_sub_nc_u32_e32 v19, s19, v19
	v_alignbit_b32 v14, v14, v13, v18
	v_alignbit_b32 v12, v13, v12, v18
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v13, v14, v12, 9
	v_lshrrev_b32_e32 v14, 9, v14
	v_clz_i32_u32_e32 v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v18, 32, v18
	v_sub_nc_u32_e32 v20, 31, v18
	v_add_nc_u32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v13, v12, v20
	v_or_b32_e32 v13, v14, v19
	v_lshlrev_b32_e32 v14, 23, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v12, 9, v12
	v_mul_f32_e32 v17, 0x3fc90fda, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v12, v14
	v_fma_f32 v14, 0x3fc90fda, v13, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, 0x33000000, v12
	v_fmac_f32_e32 v14, 0x33a22168, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v12, s18, v12
	v_fmac_f32_e32 v14, 0x3fc90fda, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v12, v17, v14
	s_branch .LBB0_9
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr12
.LBB0_9:                                ; %Flow89
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v14, 0x3f22f983, |v11|
	v_mov_b32_e32 v13, s1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_rndne_f32_e32 v18, v14
	s_cbranch_vccnz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0xbfc90fda, v18, |v11|
	v_cvt_i32_f32_e32 v13, v18
	v_fmac_f32_e32 v12, 0xb3a22168, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0xa7c234c4, v18
.LBB0_11:                               ; %_ZL4sinff.exit34
                                        ;   in Loop: Header=BB0_2 Depth=1
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr14
	s_and_saveexec_b32 s0, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s16, exec_lo, s0
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[19:20], null, 0xfe5163ab, v15, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v16
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, v20
	v_add_nc_u32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0x3c439041, v15, v[0:1]
	v_cmp_lt_u32_e64 s0, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v21
	v_mad_u64_u32 v[21:22], null, 0xdb629599, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v22 :: v_dual_cndmask_b32 v19, v21, v19
	v_mad_u64_u32 v[22:23], null, 0xf534ddc0, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v23
	v_mad_u64_u32 v[23:24], null, 0xfc2757d1, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, v24
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v24, v14
	v_cmp_lt_u32_e64 s1, 31, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v17
	v_mad_u64_u32 v[24:25], null, 0xa2f9836e, v15, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v15, v16, v22, vcc_lo
	v_add_nc_u32_e32 v0, v0, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v24, v23 :: v_dual_cndmask_b32 v16, v25, v16
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_cndmask_b32 v14, v22, v20
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v17, v15, s0
	v_cndmask_b32_e64 v16, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v23, s0
	v_sub_nc_u32_e32 v17, 32, v0
	v_cndmask_b32_e64 v22, v23, v14, s0
	v_cndmask_b32_e64 v14, v14, v19, s0
	v_cndmask_b32_e64 v16, v16, v20, s1
	v_cndmask_b32_e64 v20, v20, v15, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v22, s1
	v_cndmask_b32_e64 v14, v22, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v16, v20, v17
	v_alignbit_b32 v21, v20, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v15, v14, v17
	v_cndmask_b32_e32 v0, v23, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v21, v20, vcc_lo
	v_cndmask_b32_e32 v15, v17, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v19, v0, 29, 1
	v_alignbit_b32 v20, v0, v16, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	v_sub_nc_u32_e32 v21, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v20, v20, v21
	v_xor_b32_e32 v15, v16, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v21
	v_clz_i32_u32_e32 v17, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v17, 32, v17
	v_sub_nc_u32_e32 v16, 31, v17
	v_lshlrev_b32_e32 v23, 23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v20, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v0
	v_lshrrev_b32_e32 v0, 30, v0
	v_alignbit_b32 v15, v20, v14, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v20, 9, v20
	v_clz_i32_u32_e32 v21, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v22, 0.5, v16
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v22, v22, v23
	v_sub_nc_u32_e32 v24, 31, v21
	v_add_lshl_u32 v17, v21, v17, 23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v14, v15, v14, v24
	v_or_b32_e32 v15, v20, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v20, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v17
	v_fma_f32 v17, 0x3fc90fda, v15, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmac_f32_e32 v17, 0x33a22168, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v16
	v_fmac_f32_e32 v17, 0x3fc90fda, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v14, v20, v17 :: v_dual_add_nc_u32 v17, v19, v0
                                        ; implicit-def: $vgpr0
.LBB0_13:                               ; %Flow88
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s16
; %bb.14:                               ;   in Loop: Header=BB0_2 Depth=1
	v_fma_f32 v14, 0xbfc90fda, v0, |v7|
	v_cvt_i32_f32_e32 v17, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 0xb3a22168, v0
	v_fmac_f32_e32 v14, 0xa7c234c4, v0
; %bb.15:                               ; %_ZL4cosff.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 s0, s7, 0x7fffff
	s_lshr_b32 s1, s7, 23
	s_bitset1_b32 s0, 23
	s_addk_i32 s1, 0xff88
	s_mul_hi_u32 s16, s0, 0xfe5163ab
	s_mul_i32 s17, s0, 0x3c439041
	s_mul_hi_u32 s18, s0, 0x3c439041
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_mul_i32 s18, s0, 0xdb629599
	s_mul_hi_u32 s19, s0, 0xdb629599
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	s_mul_i32 s19, s0, 0xf534ddc0
	s_mul_hi_u32 s20, s0, 0xf534ddc0
	s_add_u32 s18, s18, s19
	s_addc_u32 s19, 0, s20
	s_mul_i32 s20, s0, 0xfc2757d1
	s_mul_hi_u32 s21, s0, 0xfc2757d1
	s_add_u32 s19, s19, s20
	s_addc_u32 s20, 0, s21
	s_mul_i32 s21, s0, 0x4e441529
	s_mul_hi_u32 s22, s0, 0x4e441529
	s_add_u32 s20, s20, s21
	s_addc_u32 s21, 0, s22
	s_cmp_gt_u32 s1, 63
	s_mul_i32 s22, s0, 0xfe5163ab
	s_mul_hi_u32 s23, s0, 0xa2f9836e
	s_mul_i32 s0, s0, 0xa2f9836e
	s_cselect_b32 s24, s17, s19
	s_cselect_b32 s16, s16, s18
	s_cselect_b32 s17, s22, s17
	s_add_u32 s0, s21, s0
	s_addc_u32 s21, 0, s23
	s_cmp_gt_u32 s1, 63
	s_cselect_b32 s22, 0xffffffc0, 0
	s_cselect_b32 s18, s18, s20
	s_cselect_b32 s0, s19, s0
	s_cselect_b32 s19, s20, s21
	s_add_i32 s22, s22, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s22, 31
	s_cselect_b32 s1, 0xffffffe0, 0
	s_cselect_b32 s20, s18, s0
	s_cselect_b32 s0, s0, s19
	s_cselect_b32 s18, s24, s18
	s_cselect_b32 s19, s16, s24
	s_cselect_b32 s16, s17, s16
	s_add_i32 s1, s1, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s1, 31
	s_cselect_b32 s17, 0xffffffe0, 0
	s_cselect_b32 s0, s20, s0
	s_cselect_b32 s20, s18, s20
	s_cselect_b32 s18, s19, s18
	s_cselect_b32 s16, s16, s19
	s_add_i32 s17, s17, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s1, 32, s17
	s_cmp_eq_u32 s17, 0
	v_mov_b32_e32 v0, s1
	s_cselect_b32 s17, -1, 0
	v_alignbit_b32 v15, s0, s20, v0
	v_alignbit_b32 v16, s20, s18, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s1, v15
	v_cndmask_b32_e64 v15, v16, s20, s17
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v16, s0, v15, 30
	s_bfe_u32 s1, s0, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s19, 0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v16, s19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v19, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v21, 23, v19
	v_alignbit_b32 v0, s18, s16, v0
	v_sub_nc_u32_e32 v20, 31, v19
	v_cndmask_b32_e64 v0, v0, s18, s17
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v15, v15, v0, 30
	v_alignbit_b32 v0, v0, s16, 30
	s_lshr_b32 s16, s0, 29
	s_lshr_b32 s0, s0, 30
	s_lshl_b32 s16, s16, 31
	v_xor_b32_e32 v15, s19, v15
	v_xor_b32_e32 v0, s19, v0
	s_or_b32 s17, s16, 0.5
	s_add_i32 s1, s1, s0
	v_sub_nc_u32_e32 v21, s17, v21
	v_alignbit_b32 v16, v16, v15, v20
	v_alignbit_b32 v0, v15, v0, v20
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v15, v16, v0, 9
	v_lshrrev_b32_e32 v16, 9, v16
	v_clz_i32_u32_e32 v20, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, 31, v20
	v_add_nc_u32_e32 v19, v20, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v0, v15, v0, v22
	v_or_b32_e32 v15, v16, v21
	v_lshlrev_b32_e32 v16, 23, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v0, 9, v0
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v16
	v_fma_f32 v16, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, 0x33000000, v0
	v_fmac_f32_e32 v16, 0x33a22168, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, s16, v0
	v_fmac_f32_e32 v16, 0x3fc90fda, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v16, v19, v16
	s_branch .LBB0_18
.LBB0_17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr16
.LBB0_18:                               ; %Flow86
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, s1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_fma_f32 v16, 0xbfc90fda, v18, |v11|
	v_cvt_i32_f32_e32 v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0xb3a22168, v18
	v_fmac_f32_e32 v16, 0xa7c234c4, v18
.LBB0_20:                               ; %_ZL4cosff.exit45
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v15, v1, s[8:9]
                                        ; implicit-def: $vgpr18
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v15, v0, v15
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e64 0x48000000, |v15|
	s_xor_b32 s16, exec_lo, s1
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v18, 0x7fffffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v28, v18, s15, 0x800000
	v_lshrrev_b32_e32 v18, 23, v18
	v_mad_u64_u32 v[20:21], null, 0xfe5163ab, v28, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v18, 0xffffff88, v18
	v_cmp_lt_u32_e32 vcc_lo, 63, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, v21
	v_cndmask_b32_e64 v26, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[21:22], null, 0x3c439041, v28, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v18, v26, v18
	v_mov_b32_e32 v0, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v18
	v_mad_u64_u32 v[22:23], null, 0xdb629599, v28, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v27, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v18, v27, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v0, v23
	v_cndmask_b32_e32 v20, v22, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v18
	v_mad_u64_u32 v[23:24], null, 0xf534ddc0, v28, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v24
	v_mad_u64_u32 v[24:25], null, 0xfc2757d1, v28, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v25
	v_mad_u64_u32 v[25:26], null, 0x4e441529, v28, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v0, v26
	v_mad_u64_u32 v[26:27], null, 0xa2f9836e, v28, v[0:1]
	v_cndmask_b32_e64 v0, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v28, v25, v23, vcc_lo
	v_add_nc_u32_e32 v0, v0, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v26, v26, v24 :: v_dual_cndmask_b32 v25, v27, v25
	v_cndmask_b32_e32 v24, v24, v22, vcc_lo
	v_cndmask_b32_e32 v18, v23, v21, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v26, v28, s0
	v_cndmask_b32_e64 v23, v25, v26, s0
	v_cndmask_b32_e64 v25, v28, v24, s0
	v_sub_nc_u32_e32 v26, 32, v0
	v_cndmask_b32_e64 v24, v24, v18, s0
	v_cndmask_b32_e64 v18, v18, v20, s0
	v_cndmask_b32_e64 v23, v23, v21, s1
	v_cndmask_b32_e64 v21, v21, v25, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v25, v24, s1
	v_cndmask_b32_e64 v18, v24, v18, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v23, v21, v26
	v_alignbit_b32 v22, v21, v25, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v24, v25, v18, v26
	v_cndmask_b32_e32 v0, v27, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v20, v22, v21, vcc_lo
	v_cndmask_b32_e32 v24, v24, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v21, v0, 29, 1
	v_alignbit_b32 v22, v0, v20, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v20, v20, v24, 30
	v_alignbit_b32 v18, v24, v18, 30
	v_sub_nc_u32_e32 v23, 0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v22, v22, v23
	v_xor_b32_e32 v20, v20, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v18, v18, v23
	v_lshrrev_b32_e32 v23, 29, v0
	v_clz_i32_u32_e32 v25, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v23, 31, v23
	v_min_u32_e32 v25, 32, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v26, 0.5, v23
	v_lshlrev_b32_e32 v27, 23, v25
	v_sub_nc_u32_e32 v24, 31, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, v26, v27
	v_alignbit_b32 v22, v22, v20, v24
	v_alignbit_b32 v18, v20, v18, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v22, v18, 9
	v_lshrrev_b32_e32 v22, 9, v22
	v_clz_i32_u32_e32 v24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v24, 32, v24
	v_sub_nc_u32_e32 v28, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v20, v18, v28
	v_or_b32_e32 v20, v22, v26
	v_add_lshl_u32 v22, v24, v25, 23
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, 0x3fc90fda, v20
	v_sub_nc_u32_e32 v18, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0x3fc90fda, v20, -v24
	v_add_nc_u32_e32 v18, 0x33000000, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, 0x33a22168, v20
	v_or_b32_e32 v18, v18, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, 0x3fc90fda, v18
	v_lshrrev_b32_e32 v18, 30, v0
	v_add_f32_e32 v0, v24, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v18, v21, v18
.LBB0_22:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s16
; %bb.23:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v0, 0x3f22f983, |v15|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v18, v0
	v_fma_f32 v0, 0xbfc90fda, v18, |v15|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, 0xb3a22168, v18
	v_fmac_f32_e32 v0, 0xa7c234c4, v18
	v_cvt_i32_f32_e32 v18, v18
; %bb.24:                               ; %_ZL4cosff.exit51
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v20, v14, v14 :: v_dual_and_b32 v21, 1, v17
	v_dual_mul_f32 v24, v16, v16 :: v_dual_lshlrev_b32 v17, 30, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v22, s4, v20, 0x3c0881c4 :: v_dual_and_b32 v25, 1, v19
	v_dual_fmaak_f32 v23, s5, v20, 0xbab64f3b :: v_dual_mul_f32 v28, v9, v9
	v_lshlrev_b32_e32 v19, 30, v19
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	v_fmaak_f32 v27, s5, v24, 0xbab64f3b
	v_and_b32_e32 v17, 0x80000000, v17
	v_fmaak_f32 v21, s4, v28, 0x3c0881c4
	v_cmp_class_f32_e64 s0, v11, 0x1f8
	v_mul_f32_e32 v22, v20, v22
	v_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	v_fmaak_f32 v27, v24, v27, 0x3d2aabf7
	v_xor_b32_e32 v11, s7, v11
	s_add_i32 s14, s14, -1
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v14, v14, v22 :: v_dual_fmaak_f32 v23, v20, v23, 0xbf000004
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	v_fma_f32 v20, v20, v23, 1.0
	v_fmaak_f32 v23, v24, v27, 0xbf000004
	s_cmp_lg_u32 s14, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, -v14, v20, vcc_lo
	v_fma_f32 v20, v24, v23, 1.0
	v_mul_f32_e32 v23, v0, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v17, v14
	v_fmaak_f32 v17, v28, v21, 0xbe2aaa9d
	v_dual_fmaak_f32 v26, s4, v24, 0x3c0881c4 :: v_dual_mul_f32 v17, v28, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v26, v24, v26, 0xbe2aaa9d :: v_dual_fmac_f32 v9, v9, v17
	v_dual_mul_f32 v22, v24, v26 :: v_dual_and_b32 v19, 0x80000000, v19
	v_and_b32_e32 v17, 1, v10
	v_lshlrev_b32_e32 v10, 30, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v16, v16, v22
	v_fmaak_f32 v22, s5, v28, 0xbab64f3b
	v_cmp_eq_u32_e64 s1, 0, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v10, 0x80000000, v10
	v_cndmask_b32_e64 v16, -v16, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmaak_f32 v20, v28, v22, 0x3d2aabf7
	v_cmp_class_f32_e64 vcc_lo, v7, 0x1f8
	v_xor_b32_e32 v7, v8, v7
	v_xor_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v19, v28, v20, 0xbf000004
	v_mul_f32_e32 v20, v12, v12
	v_cndmask_b32_e64 v16, 0x7fc00000, v16, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v28, v19, 1.0
	v_cndmask_b32_e64 v9, v19, v9, s1
	v_fmaak_f32 v19, s4, v23, 0x3c0881c4
	v_fmaak_f32 v21, s4, v20, 0x3c0881c4
	v_fmaak_f32 v22, s5, v20, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v7, v7, v10, v9
	v_fmaak_f32 v19, v23, v19, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
	v_mul_f32_e32 v8, v23, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, v0, v8
	v_and_b32_e32 v8, 1, v18
	v_dual_fmaak_f32 v17, v20, v21, 0xbe2aaa9d :: v_dual_lshlrev_b32 v18, 30, v18
	v_fmaak_f32 v21, v20, v22, 0x3d2aabf7
	v_fmaak_f32 v22, s5, v23, 0xbab64f3b
	v_cndmask_b32_e32 v14, 0x7fc00000, v14, vcc_lo
	v_cmp_eq_u32_e64 s1, 0, v8
	v_mul_f32_e32 v17, v20, v17
	v_fmaak_f32 v21, v20, v21, 0xbf000004
	v_fmaak_f32 v22, v23, v22, 0x3d2aabf7
	v_and_b32_e32 v8, 0x80000000, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v12, v12, v17
	v_fma_f32 v17, v20, v21, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v19, v23, v22, 0xbf000004 :: v_dual_and_b32 v20, 1, v13
	v_lshlrev_b32_e32 v13, 30, v13
	v_fma_f32 v19, v23, v19, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v13, 0x80000000, v13
	v_cndmask_b32_e64 v0, -v0, v19, s1
	v_cmp_eq_u32_e64 s1, 0, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v11, v11, v13
	v_xor_b32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v17, v12, s1
	v_cmp_class_f32_e64 s1, v15, 0x1f8
	v_mul_f32_e32 v8, v14, v16
	v_xor_b32_e32 v9, v11, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, 0x7fc00000, v0, s1
	v_cndmask_b32_e64 v9, 0x7fc00000, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v8, v0
	v_fmac_f32_e32 v0, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_f32_e32 v0, 1.0, v0
	v_mul_f32_e32 v8, v0, v0
	v_fma_f32 v7, |v0|, -0.5, 0.5
	v_cmp_gt_f32_e64 vcc_lo, |v0|, 0.5
	v_cmp_gt_f32_e64 s0, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v8, v7, vcc_lo
	v_fmaak_f32 v8, s6, v7, 0x3c5fc5da
	v_sqrt_f32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, v7, v8, 0x3d034c3c
	v_fmaak_f32 v8, v7, v8, 0x3d3641b1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, v7, v8, 0x3d999bc8
	v_fmaak_f32 v8, v7, v8, 0x3e2aaaac
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v7, v8
	s_waitcnt_depctr 0xfff
	v_fmac_f32_e32 v9, v9, v7
	v_fmac_f32_e32 v0, v0, v7
	v_add_f32_e32 v8, v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v0, 0x3fc90fdb, v0
	v_sub_f32_e32 v9, 0x40490fdb, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v8, v9, s0
	v_cndmask_b32_e32 v0, v0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, 0x43340000, v0
	v_cvt_f64_f32_e32 v[7:8], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[9:10], null, s[12:13], s[12:13], v[7:8]
	v_div_scale_f64 v[15:16], vcc_lo, v[7:8], s[12:13], v[7:8]
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[7:8], v[9:10], s[12:13], v[7:8]
	v_mul_f64 v[7:8], v[7:8], 4.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f64_e32 v[7:8], v[7:8]
	v_cvt_i32_f64_e32 v7, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_atomic_add_u32 v[7:8], v6, off
	s_cbranch_scc1 .LBB0_2
.LBB0_25:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10theta_calciPfS_S_S_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10theta_calciPfS_S_S_Pi, .Lfunc_end0-_Z10theta_calciPfS_S_S_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5024
; NumSgprs: 29
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10theta_calciPfS_S_S_Pi
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z10theta_calciPfS_S_S_Pi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
