// Simplified attempt
#define STARTING_MATCHING_COST 100.0f
struct pixel {
    float R;
    float G;
    float B;
};

__global__ void computeDisparity(
    const struct pixel * imageR,  // Input pixel array of left image 
                           // array dim: image[image_width][image_height]
    const struct pixel * imageL,  // Input pixel array of right image
    const int window_size, // size of window used for block searching
    const int image_height, // height of the image, in pixels
    const int image_width, // width of the image, in pixels
    const char * foregroundR, // Array of foreground flags for each pixel in imageR
    const char * foregroundL, // Array of foreground flags for each pixel in imageL
    float * disparity_output) // Output array (same dim as imageR/L) of disparity values
{
    // Local variables:
    long int pixel_index = blockIdx.x * blockDim.x + threadIdx.x; // Index of current pixel
    float matching_cost = 0.0;
    float min_matching_cost = STARTING_MATCHING_COST;
    long int min_cost_offset = 0; 
    long int offset_pixel_index = 0;

    while(pixel_index < image_height * image_width) { 
        // while... the thread index hasn't gone outside the image dimensions
        if (true) { //foregroundL[pixel_index] == 1) {
            // Calculate matching cost for this foreground pixel
            // ensure that we are not going over the end of the pixel row
            offset_pixel_index = pixel_index;
            min_matching_cost = STARTING_MATCHING_COST;
            min_cost_offset = 0;
            for (int offset = 0; offset < window_size; offset++) { 
                if ((pixel_index % image_width) + offset >= image_width) {
                    break;
                }
                matching_cost =  powf(imageL[pixel_index].R - imageR[offset_pixel_index].R, 2);
                matching_cost += powf(imageL[pixel_index].G - imageR[offset_pixel_index].G, 2);
                matching_cost += powf(imageL[pixel_index].B - imageR[offset_pixel_index].B, 2);
                if (matching_cost < min_matching_cost) {
                    min_matching_cost = matching_cost; 
                    min_cost_offset = offset;
                }
                offset_pixel_index++;
            }

            if (min_matching_cost == STARTING_MATCHING_COST) {
                disparity_output[pixel_index] = 0;
            } else {
                disparity_output[pixel_index] = powf(min_cost_offset, 2); //  + image_width;
            }
        } else {
            disparity_output[pixel_index] = -1;
        }
        pixel_index += blockDim.x * gridDim.x;
    }
}


	.file	"tmpxft_0026bd3e_00000000-6_compute_disparity.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z56__device_stub__Z16computeDisparityPK5pixelS1_iiiPKcS3_PfPK5pixelS1_iiiPKcS3_Pf
	.type	_Z56__device_stub__Z16computeDisparityPK5pixelS1_iiiPKcS3_PfPK5pixelS1_iiiPKcS3_Pf, @function
_Z56__device_stub__Z16computeDisparityPK5pixelS1_iiiPKcS3_PfPK5pixelS1_iiiPKcS3_Pf:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 44(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 36(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z56__device_stub__Z16computeDisparityPK5pixelS1_iiiPKcS3_PfPK5pixelS1_iiiPKcS3_Pf, .-_Z56__device_stub__Z16computeDisparityPK5pixelS1_iiiPKcS3_PfPK5pixelS1_iiiPKcS3_Pf
	.globl	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.type	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf, @function
_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z16computeDisparityPK5pixelS1_iiiPKcS3_PfPK5pixelS1_iiiPKcS3_Pf
	.cfi_endproc
.LFE2033:
	.size	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf, .-_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// Simplified attempt
#define STARTING_MATCHING_COST 100.0f
struct pixel {
    float R;
    float G;
    float B;
};

__global__ void computeDisparity(
    const struct pixel * imageR,  // Input pixel array of left image 
                           // array dim: image[image_width][image_height]
    const struct pixel * imageL,  // Input pixel array of right image
    const int window_size, // size of window used for block searching
    const int image_height, // height of the image, in pixels
    const int image_width, // width of the image, in pixels
    const char * foregroundR, // Array of foreground flags for each pixel in imageR
    const char * foregroundL, // Array of foreground flags for each pixel in imageL
    float * disparity_output) // Output array (same dim as imageR/L) of disparity values
{
    // Local variables:
    long int pixel_index = blockIdx.x * blockDim.x + threadIdx.x; // Index of current pixel
    float matching_cost = 0.0;
    float min_matching_cost = STARTING_MATCHING_COST;
    long int min_cost_offset = 0; 
    long int offset_pixel_index = 0;

    while(pixel_index < image_height * image_width) { 
        // while... the thread index hasn't gone outside the image dimensions
        if (true) { //foregroundL[pixel_index] == 1) {
            // Calculate matching cost for this foreground pixel
            // ensure that we are not going over the end of the pixel row
            offset_pixel_index = pixel_index;
            min_matching_cost = STARTING_MATCHING_COST;
            min_cost_offset = 0;
            for (int offset = 0; offset < window_size; offset++) { 
                if ((pixel_index % image_width) + offset >= image_width) {
                    break;
                }
                matching_cost =  powf(imageL[pixel_index].R - imageR[offset_pixel_index].R, 2);
                matching_cost += powf(imageL[pixel_index].G - imageR[offset_pixel_index].G, 2);
                matching_cost += powf(imageL[pixel_index].B - imageR[offset_pixel_index].B, 2);
                if (matching_cost < min_matching_cost) {
                    min_matching_cost = matching_cost; 
                    min_cost_offset = offset;
                }
                offset_pixel_index++;
            }

            if (min_matching_cost == STARTING_MATCHING_COST) {
                disparity_output[pixel_index] = 0;
            } else {
                disparity_output[pixel_index] = powf(min_cost_offset, 2); //  + image_width;
            }
        } else {
            disparity_output[pixel_index] = -1;
        }
        pixel_index += blockDim.x * gridDim.x;
    }
}


	.text
	.file	"compute_disparity.hip"
	.globl	_Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf # -- Begin function _Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.type	_Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf,@function
_Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf: # @_Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf, .Lfunc_end0-_Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf,@object # @_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.p2align	3, 0x0
_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf:
	.quad	_Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.size	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf"
	.size	.L__unnamed_1, 43

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf ; -- Begin function _Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.globl	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
	.p2align	8
	.type	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf,@function
_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf: ; @_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x44
	s_load_b128 s[16:19], s[0:1], 0x10
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s12, s18, s17
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_mov_b32_e32 v2, 0
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_i64_e64 s[12:13], v[1:2]
	s_cbranch_execz .LBB0_12
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b32 s2, s[2:3], 0x0
	s_load_b64 s[14:15], s[0:1], 0x30
	s_ashr_i32 s19, s18, 31
	s_cmp_gt_i32 s16, 0
	s_mov_b32 s25, 0x3e76c4e1
	s_cselect_b32 s22, -1, 0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, v1, 12, s[8:9]
	s_mul_i32 s17, s2, s4
	s_mov_b32 s9, 0
	s_mul_hi_u32 s23, s17, 12
	s_mul_i32 s24, s17, 12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_8
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_u32 s2, s18, s19
	s_mov_b32 s0, s19
	s_mov_b32 s1, s19
	s_addc_u32 s3, s19, s19
	s_mov_b64 s[20:21], 0
	s_xor_b64 s[2:3], s[2:3], s[0:1]
	s_mov_b32 s26, 0
	v_cvt_f32_u32_e32 v0, s2
	v_cvt_f32_u32_e32 v5, s3
	s_sub_u32 s0, 0, s2
	s_subb_u32 s1, 0, s3
                                        ; implicit-def: $sgpr27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, 0x4f800000, v5
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0x2f800000, v0
	v_trunc_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, 0xcf800000, v5
	v_cvt_u32_f32_e32 v5, v5
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s0, v5
	v_mul_hi_u32 v7, s0, v0
	v_mul_lo_u32 v8, s1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v7, v6
	v_mul_lo_u32 v7, s0, v0
	v_add_nc_u32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v0, v7
	v_mul_lo_u32 v9, v0, v6
	v_mul_hi_u32 v10, v0, v6
	v_mul_hi_u32 v11, v5, v7
	v_mul_lo_u32 v7, v5, v7
	v_mul_hi_u32 v12, v5, v6
	v_mul_lo_u32 v6, v5, v6
	v_add_co_u32 v8, vcc_lo, v8, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v8, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	v_ashrrev_i32_e32 v12, 31, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v7, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v6, s0, v0
	v_mul_lo_u32 v8, s1, v0
	v_mul_lo_u32 v7, s0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v6, v7
	v_mul_lo_u32 v7, s0, v0
	v_add_nc_u32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v0, v7
	v_mul_lo_u32 v9, v0, v6
	v_mul_hi_u32 v10, v0, v6
	v_mul_hi_u32 v11, v5, v7
	v_mul_lo_u32 v7, v5, v7
	v_mul_hi_u32 v13, v5, v6
	v_mul_lo_u32 v6, v5, v6
	v_add_co_u32 v8, vcc_lo, v8, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v8, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v13, vcc_lo
	v_add_co_u32 v9, vcc_lo, v1, v12
	v_add_co_ci_u32_e32 v10, vcc_lo, v2, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v7, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v11, v9, v12
	v_add_co_u32 v0, vcc_lo, v0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, v5, v7, vcc_lo
	v_xor_b32_e32 v14, v10, v12
	v_mul_hi_u32 v15, v11, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, v11, v13, 0
	v_mad_u64_u32 v[7:8], null, v14, v0, 0
	v_mad_u64_u32 v[9:10], null, v14, v13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v15, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v7
	v_add_co_ci_u32_e32 v0, vcc_lo, v5, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v8, s3, v0
	v_mad_u64_u32 v[5:6], null, s2, v0, 0
	v_mul_lo_u32 v0, s2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v5, vcc_lo, v11, v5
	v_add3_u32 v0, v6, v0, v8
	v_mad_u64_u32 v[7:8], null, v1, 12, s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v14, v0
	v_subrev_co_ci_u32_e64 v6, s0, s3, v6, vcc_lo
	v_sub_co_ci_u32_e32 v10, vcc_lo, v14, v0, vcc_lo
	v_sub_co_u32 v9, vcc_lo, v5, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v11, s0, 0, v6, vcc_lo
	v_cmp_le_u32_e64 s0, s2, v5
	v_subrev_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v10
	v_cndmask_b32_e64 v0, 0, -1, s0
	v_cmp_le_u32_e64 s0, s2, v9
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0, -1, s0
	v_cmp_le_u32_e64 s0, s3, v11
	v_cndmask_b32_e64 v14, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v14, v13, vcc_lo
	v_sub_co_u32 v14, vcc_lo, v9, s2
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	v_cndmask_b32_e64 v13, v15, v0, s0
	v_mov_b32_e32 v0, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v6, v11, v6, vcc_lo
	v_cndmask_b32_e32 v11, v9, v14, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v2, 12, v[0:1]
	v_dual_cndmask_b32 v0, v5, v11 :: v_dual_cndmask_b32 v9, v10, v6
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v0, v12
	v_xor_b32_e32 v9, v9, v12
	v_mov_b32_e32 v0, 0x42c80000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v11, vcc_lo, v10, v12
	v_sub_co_ci_u32_e32 v12, vcc_lo, v9, v12, vcc_lo
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, v11, s20
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v12, vcc_lo
	s_or_b32 s27, s27, exec_lo
	s_mov_b32 s28, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i64_e64 s[18:19], v[13:14]
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	global_load_b96 v[13:15], v[7:8], off
	global_load_b96 v[16:18], v[9:10], off offset:-4
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v13, v13, v16 :: v_dual_sub_f32 v14, v14, v17
	v_sub_f32_e32 v15, v15, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v22, |v13|
	v_frexp_mant_f32_e64 v24, |v14|
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_eq_f32_e64 s1, 1.0, v15
	v_cmp_eq_f32_e64 s0, 1.0, v14
	v_frexp_exp_i32_f32_e32 v25, v14
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v22
	v_cmp_gt_f32_e64 s3, 0x3f2aaaab, v24
	v_cndmask_b32_e64 v20, 2.0, 1.0, s1
	v_cndmask_b32_e64 v19, 2.0, 1.0, s0
	v_frexp_exp_i32_f32_e32 v23, v13
	v_cndmask_b32_e64 v28, 0, 1, s2
	v_cndmask_b32_e64 v31, 0, 1, s3
	v_mul_f32_e32 v36, 0.5, v20
	v_frexp_mant_f32_e64 v26, |v15|
	v_trunc_f32_e32 v32, v19
	v_ldexp_f32 v22, v22, v28
	v_ldexp_f32 v24, v24, v31
	v_subrev_co_ci_u32_e64 v25, s3, 0, v25, s3
	v_cmp_gt_f32_e64 s4, 0x3f2aaaab, v26
	v_cmp_eq_f32_e64 s3, v32, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v31, 1.0, v22 :: v_dual_add_f32 v32, 1.0, v24
	v_frexp_exp_i32_f32_e32 v27, v15
	v_cndmask_b32_e64 v34, 0, 1, s4
	v_trunc_f32_e32 v35, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v39, -1.0, v22 :: v_dual_add_f32 v44, -1.0, v31
	v_rcp_f32_e32 v38, v32
	v_ldexp_f32 v26, v26, v34
	v_add_f32_e32 v41, -1.0, v24
	v_subrev_co_ci_u32_e64 v27, s4, 0, v27, s4
	v_cmp_eq_f32_e64 s4, v35, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(TRANS32_DEP_2)
	v_add_f32_e32 v34, 1.0, v26
	v_rcp_f32_e32 v35, v31
	v_add_f32_e32 v46, -1.0, v32
	v_add_f32_e32 v42, -1.0, v26
	v_mul_f32_e32 v45, v41, v38
	v_rcp_f32_e32 v40, v34
	v_dual_add_f32 v49, -1.0, v34 :: v_dual_sub_f32 v22, v22, v44
	v_subrev_co_ci_u32_e64 v23, s2, 0, v23, s2
	s_delay_alu instid0(TRANS32_DEP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v50, v32, v45 :: v_dual_mul_f32 v43, v39, v35
	v_sub_f32_e32 v24, v24, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v26, v26, v49
	v_cvt_f32_i32_e32 v23, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_fma_f32 v32, v45, v32, -v50
	v_dual_mul_f32 v47, v42, v40 :: v_dual_mul_f32 v48, v31, v43
	v_cvt_f32_i32_e32 v25, v25
	v_cvt_f32_i32_e32 v27, v27
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v32, v45, v24
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v13
	v_fma_f32 v31, v43, v31, -v48
	v_mul_f32_e32 v44, v34, v47
	v_mul_f32_e32 v33, 0.5, v19
	v_add_f32_e32 v49, v50, v32
	v_cndmask_b32_e64 v18, 2.0, 1.0, vcc_lo
	v_fmac_f32_e32 v31, v43, v22
	v_fma_f32 v34, v47, v34, -v44
	v_trunc_f32_e32 v37, v36
	v_sub_f32_e32 v54, v41, v49
	v_sub_f32_e32 v50, v49, v50
	v_trunc_f32_e32 v29, v18
	v_mul_f32_e32 v30, 0.5, v18
	v_cmp_neq_f32_e64 s7, v37, v36
	v_sub_f32_e32 v41, v41, v54
	v_fmac_f32_e32 v34, v47, v26
	v_add_f32_e32 v26, v48, v31
	v_cmp_eq_f32_e64 s2, v29, v18
	v_trunc_f32_e32 v28, v30
	v_trunc_f32_e32 v29, v33
	s_and_b32 s7, s4, s7
	v_dual_sub_f32 v53, v39, v26 :: v_dual_sub_f32 v48, v26, v48
	v_mul_f32_e32 v24, 0x3f317218, v25
	v_cmp_neq_f32_e64 s5, v28, v30
	v_cmp_neq_f32_e64 s6, v29, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v39, v39, v53
	v_dual_sub_f32 v31, v48, v31 :: v_dual_sub_f32 v32, v50, v32
	s_and_b32 s5, s2, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 s6, s3, s6
	v_dual_sub_f32 v26, v39, v26 :: v_dual_sub_f32 v39, v41, v49
	v_add_f32_e32 v52, v44, v34
	v_mul_f32_e32 v22, 0x3f317218, v23
	v_cmp_eq_f32_e64 s1, 0, v15
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v26, v31, v26
	v_fma_f32 v31, 0x3f317218, v25, -v24
	v_sub_f32_e32 v55, v42, v52
	v_fma_f32 v51, 0x3f317218, v23, -v22
	v_cmp_eq_f32_e32 vcc_lo, 0, v13
	v_cmp_eq_f32_e64 s0, 0, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v31, 0xb102e308, v25 :: v_dual_sub_f32 v42, v42, v55
	v_dual_fmac_f32 v51, 0xb102e308, v23 :: v_dual_sub_f32 v44, v52, v44
	v_cndmask_b32_e64 v21, 0x7f800000, 0, s1
	v_cndmask_b32_e64 v16, 0x7f800000, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v41, v42, v52
	v_cndmask_b32_e64 v17, 0x7f800000, 0, s0
	v_sub_f32_e32 v34, v44, v34
	v_cmp_class_f32_e64 s29, v13, 0x204
	v_cmp_class_f32_e64 s30, v14, 0x204
	v_cmp_class_f32_e64 s31, v15, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v34, v34, v41
	s_or_b32 vcc_lo, vcc_lo, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v25, v55, v34
	v_mul_f32_e32 v25, v40, v25
	v_add_f32_e32 v32, v32, v39
	v_mul_f32_e32 v46, 0x3f317218, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v40, v47, v25
	v_dual_add_f32 v26, v53, v26 :: v_dual_add_f32 v23, v54, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, 0x3f317218, v27, -v46
	v_dual_mul_f32 v26, v35, v26 :: v_dual_mul_f32 v23, v38, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v39, 0xb102e308, v27
	v_dual_add_f32 v27, v22, v51 :: v_dual_add_f32 v32, v43, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v35, v45, v23
	v_sub_f32_e32 v41, v32, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v43, v35, v45 :: v_dual_mul_f32 v42, v32, v32
	v_sub_f32_e32 v45, v40, v47
	v_dual_sub_f32 v23, v23, v43 :: v_dual_sub_f32 v26, v26, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v47, v32, v32, -v42
	v_mul_f32_e32 v41, v40, v40
	v_sub_f32_e32 v25, v25, v45
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v49, v23, v23
	v_dual_add_f32 v34, v24, v31 :: v_dual_add_f32 v43, v26, v26
	v_fma_f32 v48, v40, v40, -v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v47, v32, v43
	v_dual_add_f32 v43, v42, v47 :: v_dual_add_f32 v50, v25, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v55, v32, v43
	v_fmac_f32_e32 v48, v40, v50
	v_sub_f32_e32 v42, v43, v42
	v_ldexp_f32 v50, v35, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v53, v41, v48 :: v_dual_mul_f32 v44, v35, v35
	v_sub_f32_e32 v22, v27, v22
	v_sub_f32_e32 v42, v47, v42
	v_fma_f32 v47, v43, v32, -v55
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v41, v53, v41
	v_fma_f32 v45, v35, v35, -v44
	v_dual_add_f32 v38, v46, v39 :: v_dual_mul_f32 v59, v40, v53
	v_dual_fmac_f32 v47, v43, v26 :: v_dual_fmaak_f32 v58, s25, v53, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v45, v35, v49
	v_ldexp_f32 v49, v32, 1
	v_ldexp_f32 v26, v26, 1
	v_dual_fmac_f32 v47, v42, v32 :: v_dual_add_f32 v52, v44, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v57, v35, v52
	v_dual_sub_f32 v24, v34, v24 :: v_dual_sub_f32 v41, v48, v41
	v_fma_f32 v48, v53, v40, -v59
	v_sub_f32_e32 v44, v52, v44
	v_sub_f32_e32 v24, v31, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v48, v53, v25
	v_sub_f32_e32 v44, v45, v44
	v_fma_f32 v45, v52, v35, -v57
	v_ldexp_f32 v25, v25, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v48, v41, v40
	v_dual_fmaak_f32 v58, v53, v58, 0x3ecccdef :: v_dual_fmac_f32 v45, v52, v23
	v_fmaak_f32 v56, s25, v52, 0x3e91f4c4
	v_ldexp_f32 v23, v23, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v62, v53, v58 :: v_dual_fmac_f32 v45, v44, v35
	v_fma_f32 v35, v53, v58, -v62
	v_add_f32_e32 v53, v59, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v56, v52, v56, 0x3ecccdef :: v_dual_fmac_f32 v35, v41, v58
	v_dual_fmaak_f32 v54, s25, v43, 0x3e91f4c4 :: v_dual_mul_f32 v61, v52, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v54, v43, v54, 0x3ecccdef
	v_fma_f32 v32, v52, v56, -v61
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v60, v43, v54
	v_fmac_f32_e32 v32, v44, v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v43, v43, v54, -v60
	v_add_f32_e32 v52, v61, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v61, v52, v61
	v_fmac_f32_e32 v43, v42, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v41, v60, v43
	v_add_f32_e32 v56, 0x3f2aaaaa, v41
	v_sub_f32_e32 v58, v41, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v43, v43, v58 :: v_dual_add_f32 v58, 0xbf2aaaaa, v56
	v_add_f32_e32 v43, 0x31739010, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v41, v41, v58 :: v_dual_sub_f32 v32, v32, v61
	v_dual_add_f32 v41, v43, v41 :: v_dual_add_f32 v60, 0x3f2aaaaa, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v32, 0x31739010, v32
	v_dual_add_f32 v61, 0xbf2aaaaa, v60 :: v_dual_add_f32 v54, v62, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v52, v52, v61
	v_sub_f32_e32 v62, v54, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_add_f32 v32, v32, v52 :: v_dual_sub_f32 v35, v35, v62
	v_add_f32_e32 v44, v57, v45
	v_add_f32_e32 v42, v55, v47
	v_dual_add_f32 v35, 0x31739010, v35 :: v_dual_sub_f32 v52, v44, v57
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v57, v60, v32
	v_sub_f32_e32 v43, v42, v55
	v_sub_f32_e32 v55, v53, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v59, v60, v57
	v_add_f32_e32 v63, 0x3f2aaaaa, v54
	v_sub_f32_e32 v43, v47, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v32, v32, v59
	v_add_f32_e32 v62, 0xbf2aaaaa, v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v54, v54, v62
	v_dual_add_f32 v35, v35, v54 :: v_dual_add_f32 v54, v56, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v47, v63, v35
	v_sub_f32_e32 v61, v63, v47
	v_mul_f32_e32 v62, v53, v47
	v_mul_f32_e32 v60, v44, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v35, v35, v61
	v_fma_f32 v61, v53, v47, -v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v59, v44, v57, -v60
	v_dual_mul_f32 v58, v42, v54 :: v_dual_fmac_f32 v61, v53, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v59, v44, v32
	v_sub_f32_e32 v32, v48, v55
	v_ldexp_f32 v35, v40, 1
	v_fmac_f32_e32 v61, v32, v47
	v_sub_f32_e32 v56, v56, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v41, v41, v56
	v_fma_f32 v56, v42, v54, -v58
	v_fmac_f32_e32 v56, v42, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v56, v43, v54
	v_add_f32_e32 v32, v58, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v43, v49, v32
	v_sub_f32_e32 v41, v45, v52
	v_sub_f32_e32 v49, v43, v49
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v59, v41, v57
	v_add_f32_e32 v41, v62, v61
	v_sub_f32_e32 v47, v41, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v47, v61, v47 :: v_dual_add_f32 v48, v35, v41
	v_add_f32_e32 v25, v25, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v35, v48, v35
	v_sub_f32_e32 v42, v32, v58
	v_dual_sub_f32 v32, v32, v49 :: v_dual_sub_f32 v35, v41, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v42, v56, v42 :: v_dual_add_f32 v25, v25, v35
	v_add_f32_e32 v26, v26, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v26, v26, v32
	v_dual_add_f32 v40, v60, v59 :: v_dual_add_f32 v35, v43, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v45, v50, v40
	v_sub_f32_e32 v44, v40, v60
	v_dual_sub_f32 v32, v38, v46 :: v_dual_add_f32 v41, v27, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v50, v45, v50
	v_sub_f32_e32 v44, v59, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v32, v39, v32 :: v_dual_add_f32 v39, v48, v25
	v_dual_sub_f32 v40, v40, v50 :: v_dual_add_f32 v23, v23, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v44, v39, v48
	v_add_f32_e32 v23, v23, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v40, v35, v43 :: v_dual_sub_f32 v25, v25, v44
	v_add_f32_e32 v31, v45, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v42, v31, v45 :: v_dual_add_f32 v43, v34, v31
	v_add_f32_e32 v45, v38, v39
	v_sub_f32_e32 v23, v23, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v42, v43, v34
	v_sub_f32_e32 v26, v26, v40
	v_dual_sub_f32 v40, v41, v27 :: v_dual_sub_f32 v31, v31, v42
	v_sub_f32_e32 v47, v43, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v35, v35, v40 :: v_dual_sub_f32 v34, v34, v47
	v_dual_sub_f32 v46, v41, v40 :: v_dual_add_f32 v31, v31, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v42, v24, v23 :: v_dual_sub_f32 v27, v27, v46
	v_sub_f32_e32 v22, v51, v22
	v_dual_sub_f32 v44, v45, v38 :: v_dual_sub_f32 v47, v42, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v27, v35, v27 :: v_dual_add_f32 v40, v22, v26
	v_sub_f32_e32 v39, v39, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v48, v45, v44 :: v_dual_sub_f32 v23, v23, v47
	v_sub_f32_e32 v34, v42, v47
	v_dual_add_f32 v31, v42, v31 :: v_dual_sub_f32 v46, v40, v22
	v_add_f32_e32 v27, v40, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v35, v40, v46 :: v_dual_add_f32 v40, v43, v31
	v_sub_f32_e32 v38, v38, v48
	v_sub_f32_e32 v24, v24, v34
	v_add_f32_e32 v44, v32, v25
	v_sub_f32_e32 v22, v22, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v38, v39, v38
	v_add_f32_e32 v23, v23, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v48, v44, v32
	v_dual_add_f32 v35, v44, v38 :: v_dual_add_f32 v38, v41, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v39, v44, v48 :: v_dual_add_f32 v34, v45, v35
	v_sub_f32_e32 v32, v32, v39
	v_sub_f32_e32 v26, v26, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v39, v38, v41
	v_dual_sub_f32 v41, v40, v43 :: v_dual_sub_f32 v24, v34, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v22, v26, v22
	v_sub_f32_e32 v26, v27, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v27, v31, v41
	v_sub_f32_e32 v24, v35, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_add_f32 v22, v22, v26 :: v_dual_add_f32 v23, v23, v27
	v_sub_f32_e32 v25, v25, v48
	v_cndmask_b32_e64 v27, 1.0, v13, s5
	v_add_f32_e32 v25, v25, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v24, v25, v24 :: v_dual_add_f32 v25, v38, v22
	v_dual_add_f32 v26, v40, v23 :: v_dual_sub_f32 v29, v25, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v31, v26, v40 :: v_dual_mul_f32 v32, v19, v26
	v_mul_f32_e32 v30, v18, v25
	v_dual_sub_f32 v22, v22, v29 :: v_dual_sub_f32 v23, v23, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, v19, v26, -v32
	v_fma_f32 v25, v18, v25, -v30
	v_cmp_class_f32_e64 s8, v30, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v26, v19, v23 :: v_dual_fmac_f32 v25, v18, v22
	v_cndmask_b32_e64 v18, 1.0, v14, s6
	v_dual_add_f32 v22, v32, v26 :: v_dual_add_f32 v19, v30, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v29, v22, v32
	v_add_f32_e32 v28, v34, v24
	v_dual_sub_f32 v26, v26, v29 :: v_dual_sub_f32 v33, v28, v34
	v_mul_f32_e32 v34, v20, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v24, v33
	v_fma_f32 v28, v20, v28, -v34
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v28, v20, v24
	v_sub_f32_e32 v24, v19, v30
	v_cndmask_b32_e64 v19, v19, v30, s8
	v_cmp_class_f32_e64 s8, v32, 0x204
	v_cndmask_b32_e64 v20, 1.0, v15, s7
	v_add_f32_e32 v23, v34, v28
	v_sub_f32_e32 v24, v25, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v22, v22, v32, s8
	v_cmp_class_f32_e64 s8, v34, 0x204
	v_cndmask_b32_e64 v30, v23, v34, s8
	v_cmp_eq_f32_e64 s8, 0x42b17218, v19
	v_sub_f32_e32 v23, v23, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v31, 0, 0x37000000, s8
	v_cmp_eq_f32_e64 s8, 0x42b17218, v22
	v_sub_f32_e32 v23, v28, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v35, v19, v31
	v_cndmask_b32_e64 v32, 0, 0x37000000, s8
	v_cmp_eq_f32_e64 s8, 0x42b17218, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v36, 0x3fb8aa3b, v35
	v_sub_f32_e32 v34, v22, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v33, 0, 0x37000000, s8
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v19|
	v_fma_f32 v37, 0x3fb8aa3b, v35, -v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v29, 0x3fb8aa3b, v34
	v_sub_f32_e32 v25, v30, v33
	v_rndne_f32_e32 v38, v36
	v_cndmask_b32_e64 v19, 0, v24, s8
	v_fmac_f32_e32 v37, 0x32a5705f, v35
	v_fma_f32 v39, 0x3fb8aa3b, v34, -v29
	v_mul_f32_e32 v28, 0x3fb8aa3b, v25
	v_rndne_f32_e32 v40, v29
	v_sub_f32_e32 v36, v36, v38
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v22|
	v_fmac_f32_e32 v39, 0x32a5705f, v34
	v_fma_f32 v41, 0x3fb8aa3b, v25, -v28
	v_rndne_f32_e32 v42, v28
	v_dual_sub_f32 v29, v29, v40 :: v_dual_add_f32 v24, v36, v37
	v_cndmask_b32_e64 v22, 0, v26, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v41, 0x32a5705f, v25 :: v_dual_sub_f32 v28, v28, v42
	v_add_f32_e32 v29, v29, v39
	s_delay_alu instid0(VALU_DEP_4)
	v_exp_f32_e32 v24, v24
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v30|
	v_cvt_i32_f32_e32 v30, v40
	v_add_f32_e32 v28, v28, v41
	v_exp_f32_e32 v26, v29
	v_cvt_i32_f32_e32 v29, v38
	v_cndmask_b32_e64 v23, 0, v23, s8
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v35
	v_exp_f32_e32 v28, v28
	v_add_f32_e32 v19, v31, v19
	v_ldexp_f32 v24, v24, v29
	v_cvt_i32_f32_e32 v31, v42
	v_dual_add_f32 v22, v32, v22 :: v_dual_add_f32 v23, v33, v23
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f32 v26, v26, v30
	v_cndmask_b32_e64 v24, 0, v24, s8
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v34
	v_cndmask_b32_e64 v29, 0, v14, s6
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f32 v28, v28, v31
	v_cndmask_b32_e64 v26, 0, v26, s8
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v17, 0x7fffffff, v17, v29
	v_cndmask_b32_e64 v28, 0, v28, s8
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v24, 0x7f800000, v24, s8
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v34
	v_fma_f32 v19, v24, v19, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, 0x7f800000, v26, s8
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v25
	v_fma_f32 v22, v26, v22, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, 0x7f800000, v28, s8
	v_cndmask_b32_e64 v28, 0, v13, s5
	v_cmp_eq_f32_e64 s5, 0x7f800000, v24
	v_fma_f32 v23, v25, v23, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v16, 0x7fffffff, v16, v28
	v_cndmask_b32_e64 v19, v19, v24, s5
	v_cmp_eq_f32_e64 s5, 0x7f800000, v26
	v_cndmask_b32_e64 v24, 0, v15, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v19, 0x7fffffff, v19, v27
	v_cndmask_b32_e64 v22, v22, v26, s5
	v_cmp_eq_f32_e64 s5, 0x7f800000, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v21, 0x7fffffff, v21, v24
	v_bfi_b32 v18, 0x7fffffff, v22, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v23, v23, v25, s5
	v_cndmask_b32_e64 v22, 0x7fc00000, v19, s2
	v_cmp_gt_f32_e64 s2, 0, v13
	v_bfi_b32 v20, 0x7fffffff, v23, v20
	v_cndmask_b32_e64 v23, 0x7fc00000, v18, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v19, v22, s2
	v_cmp_gt_f32_e64 s2, 0, v14
	v_cndmask_b32_e64 v24, 0x7fc00000, v20, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v19, v16, vcc_lo
	v_cndmask_b32_e64 v18, v18, v23, s2
	v_cmp_gt_f32_e64 s2, 0, v15
	s_or_b32 vcc_lo, s0, s30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v18, v17, vcc_lo
	v_cndmask_b32_e64 v20, v20, v24, s2
	s_or_b32 vcc_lo, s1, s31
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v18, v20, v21, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v13, v13
	v_cndmask_b32_e32 v13, 0x7fc00000, v16, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v14, v14
	v_cndmask_b32_e32 v14, 0x7fc00000, v17, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v13, v14
	v_cndmask_b32_e32 v15, 0x7fc00000, v18, vcc_lo
	v_add_f32_e32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, v13, v0
	v_cndmask_b32_e64 v5, v5, s20, vcc_lo
	s_add_u32 s20, s20, 1
	v_cndmask_b32_e64 v6, v6, s21, vcc_lo
	s_addc_u32 s21, s21, 0
	s_cmp_eq_u32 s16, s20
	v_cndmask_b32_e32 v0, v0, v13, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, 12
	s_cselect_b32 s0, -1, 0
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_and_not1_b32 s1, s27, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s27, s1, s0
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s27
	s_or_b32 s26, s0, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_4
; %bb.7:                                ; %Flow80
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_branch .LBB0_9
.LBB0_8:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v0, 0x42c80000
	v_mov_b32_e32 v6, 0
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_neq_f32_e32 vcc_lo, 0x42c80000, v0
	v_mov_b32_e32 v0, 0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	v_xor_b32_e32 v0, v5, v6
	v_cls_i32_e32 v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v0
	v_add_nc_u32_e32 v7, -1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 32, v0
	v_min_u32_e32 v0, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], v0, v[5:6]
	v_sub_nc_u32_e32 v0, 32, v0
	v_min_u32_e32 v7, 1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v7, v8, v7
	v_cvt_f32_i32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v7, v0
	v_frexp_mant_f32_e64 v7, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v7
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, 1.0, v7
	v_add_f32_e32 v10, -1.0, v7
	v_add_f32_e32 v12, -1.0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v12
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v10, v9
	v_mul_f32_e32 v13, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v11, v8, -v13
	v_fmac_f32_e32 v8, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v13, v8
	v_sub_f32_e32 v12, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v12 :: v_dual_sub_f32 v13, v7, v13
	v_dual_sub_f32 v7, v10, v7 :: v_dual_sub_f32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v8, v7
	v_add_f32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v9, v7
	v_add_f32_e32 v8, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v8, v11
	v_dual_mul_f32 v10, v8, v8 :: v_dual_sub_f32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, v8, v8, -v10
	v_add_f32_e32 v11, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v8, v11
	v_add_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, s25, v11, 0x3e91f4c4
	v_sub_f32_e32 v10, v11, v10
	v_dual_fmaak_f32 v12, v11, v12, 0x3ecccdef :: v_dual_sub_f32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v11, v12
	v_fma_f32 v10, v11, v12, -v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v9, v12 :: v_dual_mul_f32 v15, v8, v11
	v_add_f32_e32 v12, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, v11, v8, -v15
	v_dual_sub_f32 v13, v12, v13 :: v_dual_fmac_f32 v16, v11, v7
	v_add_f32_e32 v14, 0x3f2aaaaa, v12
	v_ldexp_f32 v7, v7, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v10, v13
	v_fmac_f32_e32 v16, v9, v8
	v_ldexp_f32 v8, v8, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, 0x31739010, v10
	v_add_f32_e32 v13, 0xbf2aaaaa, v14
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v12
	v_add_f32_e32 v9, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v15, v16 :: v_dual_sub_f32 v12, v14, v9
	v_mul_f32_e32 v13, v11, v9
	v_sub_f32_e32 v14, v11, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v10, v12
	v_fma_f32 v12, v11, v9, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v16, v14
	v_fmac_f32_e32 v12, v11, v10
	v_frexp_exp_i32_f32_e32 v10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v14, v9
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_cmp_eq_u64_e32 vcc_lo, 1, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v13, v12
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v10, v13
	v_add_f32_e32 v11, v8, v10
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, 0x3f317218, v9 :: v_dual_add_f32 v7, v7, v12
	v_fma_f32 v13, 0x3f317218, v9, -v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v13, 0xb102e308, v9 :: v_dual_sub_f32 v8, v11, v8
	v_sub_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v8
	v_dual_add_f32 v9, v11, v7 :: v_dual_add_f32 v8, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v9, v11 :: v_dual_add_f32 v10, v8, v9
	v_dual_sub_f32 v7, v7, v11 :: v_dual_sub_f32 v12, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v9, v9, v12 :: v_dual_sub_f32 v14, v8, v14
	v_sub_f32_e32 v15, v10, v12
	v_sub_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, v13, v7
	v_sub_f32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v9, v8 :: v_dual_sub_f32 v9, v11, v13
	v_sub_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v11, v8
	v_sub_f32_e32 v11, v11, v9
	v_dual_sub_f32 v9, v13, v11 :: v_dual_add_f32 v12, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v7, v7, v9 :: v_dual_sub_f32 v10, v12, v10
	v_cndmask_b32_e64 v9, 2.0, 1.0, vcc_lo
	v_sub_f32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v8
	v_add_f32_e32 v8, v12, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v8, v12
	v_sub_f32_e32 v7, v7, v10
	v_mul_f32_e32 v11, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, v9, v8, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	v_fmac_f32_e32 v8, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v11, v8
	v_cndmask_b32_e32 v10, v7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	v_sub_f32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, 0x3fb8aa3b, v13
	v_fma_f32 v15, 0x3fb8aa3b, v13, -v14
	v_rndne_f32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v15, 0x32a5705f, v13 :: v_dual_sub_f32 v14, v14, v16
	v_add_f32_e32 v14, v14, v15
	v_sub_f32_e32 v7, v7, v11
	v_cvt_i32_f32_e32 v11, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v14, v14
	v_sub_f32_e32 v7, v8, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v14, v11
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	v_trunc_f32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_dual_mul_f32 v10, 0.5, v9 :: v_dual_add_f32 v7, v12, v7
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v12, v10
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s0, v12, v10
	v_fma_f32 v7, v8, v7, v8
	v_cmp_eq_f32_e64 s1, 0x7f800000, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	v_cndmask_b32_e64 v0, 1.0, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v7, v8, s1
	v_bfi_b32 v0, 0x7fffffff, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0x7fc00000, v0, vcc_lo
	v_cmp_gt_i64_e32 vcc_lo, 0, v[5:6]
	v_cndmask_b32_e32 v0, v0, v7, vcc_lo
	v_cmp_ne_u64_e32 vcc_lo, 0, v[5:6]
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
.LBB0_11:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, v1, s17
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	v_add_co_u32 v3, s0, v3, s24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v6, vcc_lo
	v_cmp_le_i64_e32 vcc_lo, s[12:13], v[1:2]
	v_add_co_ci_u32_e64 v4, s0, s23, v4, s0
	global_store_b32 v[5:6], v0, off
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_2
.LBB0_12:                               ; %._crit_edge56
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 64
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf, .Lfunc_end0-_Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5500
; NumSgprs: 34
; NumVgprs: 64
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 64
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z16computeDisparityPK5pixelS1_iiiPKcS3_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     64
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
