#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <iostream>

using namespace std;

__global__
void gpu_matrix_mult(float *d_a, float *d_b, float *d_c, int m, int n, int k)
{
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    if ((col < k) && (row < m))
    {
        float sum = 0.0;
        for (int i = 0; i < n; i++)
        {
            sum += d_a[row * n + i] * d_b[i * k + col];
        }
        d_c[row * k + col] = sum;
    }
}

void SaveMatrixToCsvFile(float *matrix, int m, int n, char *fileName)
{
    FILE *f = fopen(fileName, "w");

    for (int i = 0; i < m; ++i)
    {
        for (int j = 0; j < n; ++j)
        {
            fprintf(f, "%f,", matrix[i * n + j]);
        }
        long currentPos = ftell(f);
        fseek(f, currentPos - 1, SEEK_SET);
        fprintf(f, "\n");
    }

    fclose(f);
}

int main(int argc, char** argv)
{
    /*
       Execute on CPU
       Matrix h_a = host matrix A, size: m*n
       Matrix h_b = host matrix B, size: n*k
       Matrix h_c = host matrix C, size: m*k, is result of h_a * h_b
       Execute on GPU
       Matrix d_a = device matrix A, size: m*n
       Matrix d_b = device matrix B, size: n*k
       Matrix d_c = device matrix C, size: m*k, is result of d_a * d_b
    */

    // Matrices sizes:
    int m = 1024;
    int n = 5012;
    int k = 1024;

    // Host memory allocation
    float *h_a, *h_b, *h_c;
    h_a = (float*)malloc(m * n * sizeof(float)); // Host matrix A
    h_b = (float*)malloc(n * k * sizeof(float)); // Host matrix B

    // Random value initialization of host matrix A
    for (int i = 0; i < m; i++) {
        for (int j = 0; j < n; j++) {
            h_a[i * n + j] = rand() % 1024;
        }
    }

    // Random value initialization of host matrix B
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < k; j++) {
            h_b[i * k + j] = rand() % 1024;
        }
    }

    printf("\nMatrix initalized.");

    // Device memory allocation
    float *d_a, *d_b, *d_c;
    cudaMalloc((void **) &d_a, m * n * sizeof(float)); // Device matrix A
    cudaMalloc((void **) &d_b, n * k * sizeof(float)); // Device matrix B
    cudaMalloc((void **) &d_c, m * k * sizeof(float)); // Device matrix C (result)

    printf("\nMemory allocated in device");

    // Copy matrixes from host to device memory
    cudaMemcpy(d_a, h_a, sizeof(float)*m*n, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, sizeof(float)*n*k, cudaMemcpyHostToDevice);

    printf("\nData copyed to device");

    int block_size = 32;
    dim3 dimBlock(block_size, block_size, 1);
    dim3 dimGrid(ceil((float)k / block_size), ceil((float)m / block_size), 1);

    printf("\nBlocks asigned");

    // Launch Kernel
    gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
    cudaDeviceSynchronize();

    printf("\nKernel launched.");

    // Copy result from device to host
    h_c = (float*)malloc(m * k * sizeof(float)); // Host matrix C (result)
    cudaMemcpy(h_c, d_c, sizeof(float)*m*k, cudaMemcpyDeviceToHost);

    SaveMatrixToCsvFile(h_a, m, n, "matrix_a");
    SaveMatrixToCsvFile(h_b, n, k, "matrix_b");
    SaveMatrixToCsvFile(h_c, m, k, "matrix_c");

    cudaFree(d_a);
    cudaFree(d_b);
    cudaFree(d_c);
    cudaFreeHost(h_a);
    cudaFreeHost(h_b);
    cudaFreeHost(h_c);
    return 0;
}
	.file	"tmpxft_003b3c4c_00000000-6_mulMatrixCUDA.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"w"
.LC1:
	.string	"%f,"
.LC2:
	.string	"\n"
	.text
	.globl	_Z19SaveMatrixToCsvFilePfiiPc
	.type	_Z19SaveMatrixToCsvFilePfiiPc, @function
_Z19SaveMatrixToCsvFilePfiiPc:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%esi, %r14d
	leaq	.LC0(%rip), %rsi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	movq	%rcx, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	fopen@PLT
	movq	%rax, (%rsp)
.L3:
	cmpl	%r14d, %r13d
	jge	.L5
	movslq	%r12d, %rax
	xorl	%r15d, %r15d
	leaq	0(%rbp,%rax,4), %r8
.L6:
	cmpl	%r15d, %ebx
	jle	.L9
	movq	(%rsp), %rdi
	movl	$2, %esi
	movb	$1, %al
	movq	%r8, 8(%rsp)
	leaq	.LC1(%rip), %rdx
	cvtss2sd	(%r8,%r15,4), %xmm0
	incq	%r15
	call	__fprintf_chk@PLT
	movq	8(%rsp), %r8
	jmp	.L6
.L9:
	movq	(%rsp), %rdi
	incl	%r13d
	addl	%ebx, %r12d
	call	ftell@PLT
	movq	(%rsp), %rdi
	xorl	%edx, %edx
	leaq	-1(%rax), %rsi
	call	fseek@PLT
	movq	(%rsp), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rdx
	call	__fprintf_chk@PLT
	jmp	.L3
.L5:
	movq	(%rsp), %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z19SaveMatrixToCsvFilePfiiPc, .-_Z19SaveMatrixToCsvFilePfiiPc
	.globl	_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
	.type	_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15gpu_matrix_multPfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
	.globl	_Z15gpu_matrix_multPfS_S_iii
	.type	_Z15gpu_matrix_multPfS_S_iii, @function
_Z15gpu_matrix_multPfS_S_iii:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE3662:
	.size	_Z15gpu_matrix_multPfS_S_iii, .-_Z15gpu_matrix_multPfS_S_iii
	.section	.rodata.str1.1
.LC3:
	.string	"\nMatrix initalized."
.LC4:
	.string	"\nMemory allocated in device"
.LC5:
	.string	"\nData copyed to device"
.LC6:
	.string	"\nBlocks asigned"
.LC7:
	.string	"\nKernel launched."
.LC8:
	.string	"matrix_a"
.LC9:
	.string	"matrix_b"
.LC10:
	.string	"matrix_c"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$20529152, %edi
	movl	$1024, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$20529152, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %rbx
.L16:
	imulq	$20048, %r13, %r14
	xorl	%r12d, %r12d
	addq	%rbp, %r14
.L17:
	call	rand@PLT
	cltd
	idivl	%r15d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%r12
	cmpq	$5012, %r12
	jne	.L17
	incq	%r13
	cmpq	$1024, %r13
	jne	.L16
	xorl	%r13d, %r13d
	movl	$1024, %r15d
.L18:
	movq	%r13, %r14
	xorl	%r12d, %r12d
	salq	$12, %r14
	addq	%rbx, %r14
.L19:
	call	rand@PLT
	cltd
	idivl	%r15d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%r12
	cmpq	$1024, %r12
	jne	.L19
	incq	%r13
	cmpq	$5012, %r13
	jne	.L18
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	8(%rsp), %rdi
	movl	$20529152, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$20529152, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$20529152, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$20529152, %edx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	movabsq	$137438953504, %rax
	movl	$2, %edi
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	xorl	%eax, %eax
	movl	$1, 40(%rsp)
	movl	$1, 52(%rsp)
	call	__printf_chk@PLT
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	movq	32(%rsp), %rdx
	movq	44(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1024, %r9d
	movl	$5012, %r8d
	movq	8(%rsp), %rdi
	movl	$1024, %ecx
	call	_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
.L21:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$4194304, %edi
	call	malloc@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$4194304, %edx
	movq	%rax, %rdi
	movq	%rax, %r12
	call	cudaMemcpy@PLT
	leaq	.LC8(%rip), %rcx
	movl	$5012, %edx
	movq	%rbp, %rdi
	movl	$1024, %esi
	call	_Z19SaveMatrixToCsvFilePfiiPc
	leaq	.LC9(%rip), %rcx
	movl	$1024, %edx
	movq	%rbx, %rdi
	movl	$5012, %esi
	call	_Z19SaveMatrixToCsvFilePfiiPc
	leaq	.LC10(%rip), %rcx
	movl	$1024, %edx
	movq	%r12, %rdi
	movl	$1024, %esi
	call	_Z19SaveMatrixToCsvFilePfiiPc
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	cudaFreeHost@PLT
	movq	%rbx, %rdi
	call	cudaFreeHost@PLT
	movq	%r12, %rdi
	call	cudaFreeHost@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z15gpu_matrix_multPfS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15gpu_matrix_multPfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>

using namespace std;

__global__
void gpu_matrix_mult(float *d_a, float *d_b, float *d_c, int m, int n, int k)
{
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;
    if ((col < k) && (row < m))
    {
        float sum = 0.0;
        for (int i = 0; i < n; i++)
        {
            sum += d_a[row * n + i] * d_b[i * k + col];
        }
        d_c[row * k + col] = sum;
    }
}

void SaveMatrixToCsvFile(float *matrix, int m, int n, char *fileName)
{
    FILE *f = fopen(fileName, "w");

    for (int i = 0; i < m; ++i)
    {
        for (int j = 0; j < n; ++j)
        {
            fprintf(f, "%f,", matrix[i * n + j]);
        }
        long currentPos = ftell(f);
        fseek(f, currentPos - 1, SEEK_SET);
        fprintf(f, "\n");
    }

    fclose(f);
}

int main(int argc, char** argv)
{
    /*
       Execute on CPU
       Matrix h_a = host matrix A, size: m*n
       Matrix h_b = host matrix B, size: n*k
       Matrix h_c = host matrix C, size: m*k, is result of h_a * h_b
       Execute on GPU
       Matrix d_a = device matrix A, size: m*n
       Matrix d_b = device matrix B, size: n*k
       Matrix d_c = device matrix C, size: m*k, is result of d_a * d_b
    */

    // Matrices sizes:
    int m = 1024;
    int n = 5012;
    int k = 1024;

    // Host memory allocation
    float *h_a, *h_b, *h_c;
    h_a = (float*)malloc(m * n * sizeof(float)); // Host matrix A
    h_b = (float*)malloc(n * k * sizeof(float)); // Host matrix B

    // Random value initialization of host matrix A
    for (int i = 0; i < m; i++) {
        for (int j = 0; j < n; j++) {
            h_a[i * n + j] = rand() % 1024;
        }
    }

    // Random value initialization of host matrix B
    for (int i = 0; i < n; i++) {
        for (int j = 0; j < k; j++) {
            h_b[i * k + j] = rand() % 1024;
        }
    }

    printf("\nMatrix initalized.");

    // Device memory allocation
    float *d_a, *d_b, *d_c;
    hipMalloc((void **) &d_a, m * n * sizeof(float)); // Device matrix A
    hipMalloc((void **) &d_b, n * k * sizeof(float)); // Device matrix B
    hipMalloc((void **) &d_c, m * k * sizeof(float)); // Device matrix C (result)

    printf("\nMemory allocated in device");

    // Copy matrixes from host to device memory
    hipMemcpy(d_a, h_a, sizeof(float)*m*n, hipMemcpyHostToDevice);
    hipMemcpy(d_b, h_b, sizeof(float)*n*k, hipMemcpyHostToDevice);

    printf("\nData copyed to device");

    int block_size = 32;
    dim3 dimBlock(block_size, block_size, 1);
    dim3 dimGrid(ceil((float)k / block_size), ceil((float)m / block_size), 1);

    printf("\nBlocks asigned");

    // Launch Kernel
    gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
    hipDeviceSynchronize();

    printf("\nKernel launched.");

    // Copy result from device to host
    h_c = (float*)malloc(m * k * sizeof(float)); // Host matrix C (result)
    hipMemcpy(h_c, d_c, sizeof(float)*m*k, hipMemcpyDeviceToHost);

    SaveMatrixToCsvFile(h_a, m, n, "matrix_a");
    SaveMatrixToCsvFile(h_b, n, k, "matrix_b");
    SaveMatrixToCsvFile(h_c, m, k, "matrix_c");

    hipFree(d_a);
    hipFree(d_b);
    hipFree(d_c);
    hipHostFree(h_a);
    hipHostFree(h_b);
    hipHostFree(h_c);
    return 0;
}
	.text
	.file	"mulMatrixCUDA.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__gpu_matrix_multPfS_S_iii # -- Begin function _Z30__device_stub__gpu_matrix_multPfS_S_iii
	.type	_Z30__device_stub__gpu_matrix_multPfS_S_iii,@function
_Z30__device_stub__gpu_matrix_multPfS_S_iii: # @_Z30__device_stub__gpu_matrix_multPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15gpu_matrix_multPfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__gpu_matrix_multPfS_S_iii, .Lfunc_end0-_Z30__device_stub__gpu_matrix_multPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19SaveMatrixToCsvFilePfiiPc   # -- Begin function _Z19SaveMatrixToCsvFilePfiiPc
	.type	_Z19SaveMatrixToCsvFilePfiiPc,@function
_Z19SaveMatrixToCsvFilePfiiPc:          # @_Z19SaveMatrixToCsvFilePfiiPc
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movl	%esi, %ebp
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	movl	$.L.str, %esi
	movq	%rcx, %rdi
	callq	fopen
	movq	%rax, %r15
	testl	%ebp, %ebp
	jle	.LBB1_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%ebp, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%ebx, %r13d
	xorl	%ebp, %ebp
	xorl	%r14d, %r14d
	movl	%ebx, 4(%rsp)                   # 4-byte Spill
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB1_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%ebp, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %r12
	xorl	%ebx, %ebx
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12,%rbx,4), %xmm0
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%rbx
	cmpq	%rbx, %r13
	jne	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	movq	%r15, %rdi
	callq	ftell
	leaq	-1(%rax), %rsi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	fseek
	movl	$10, %edi
	movq	%r15, %rsi
	callq	fputc@PLT
	incq	%r14
	movl	4(%rsp), %ebx                   # 4-byte Reload
	addl	%ebx, %ebp
	cmpq	16(%rsp), %r14                  # 8-byte Folded Reload
	jne	.LBB1_2
.LBB1_6:                                # %._crit_edge20
	movq	%r15, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end1:
	.size	_Z19SaveMatrixToCsvFilePfiiPc, .Lfunc_end1-_Z19SaveMatrixToCsvFilePfiiPc
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$20529152, %edi                 # imm = 0x1394000
	callq	malloc
	movq	%rax, %rbx
	movl	$20529152, %edi                 # imm = 0x1394000
	callq	malloc
	movq	%rax, %r14
	xorl	%r15d, %r15d
	movq	%rbx, %r12
.LBB2_1:                                # %.preheader74
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	xorl	%r13d, %r13d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r12,%r13,4)
	incq	%r13
	cmpq	$5012, %r13                     # imm = 0x1394
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%r15
	addq	$20048, %r12                    # imm = 0x4E50
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB2_1
# %bb.4:                                # %.preheader.preheader
	xorl	%r15d, %r15d
	movq	%r14, %r12
.LBB2_5:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	xorl	%r13d, %r13d
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	1023(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-1024, %ecx                    # imm = 0xFC00
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r12,%r13,4)
	incq	%r13
	cmpq	$1024, %r13                     # imm = 0x400
	jne	.LBB2_6
# %bb.7:                                #   in Loop: Header=BB2_5 Depth=1
	incq	%r15
	addq	$4096, %r12                     # imm = 0x1000
	cmpq	$5012, %r15                     # imm = 0x1394
	jne	.LBB2_5
# %bb.8:
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	24(%rsp), %r15
	movl	$20529152, %esi                 # imm = 0x1394000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r12
	movl	$20529152, %esi                 # imm = 0x1394000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movq	(%r15), %rdi
	movl	$20529152, %edx                 # imm = 0x1394000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$20529152, %edx                 # imm = 0x1394000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	movabsq	$137438953504, %rdi             # imm = 0x2000000020
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$5012, %r8d                     # imm = 0x1394
	movl	$1024, %r9d                     # imm = 0x400
	callq	_Z30__device_stub__gpu_matrix_multPfS_S_iii
.LBB2_10:
	callq	hipDeviceSynchronize
	movl	$.L.str.7, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %r15
	movq	8(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.8, %ecx
	movq	%rbx, %rdi
	movl	$1024, %esi                     # imm = 0x400
	movl	$5012, %edx                     # imm = 0x1394
	callq	_Z19SaveMatrixToCsvFilePfiiPc
	movl	$.L.str.9, %ecx
	movq	%r14, %rdi
	movl	$5012, %esi                     # imm = 0x1394
	movl	$1024, %edx                     # imm = 0x400
	callq	_Z19SaveMatrixToCsvFilePfiiPc
	movl	$.L.str.10, %ecx
	movq	%r15, %rdi
	movl	$1024, %esi                     # imm = 0x400
	movl	$1024, %edx                     # imm = 0x400
	callq	_Z19SaveMatrixToCsvFilePfiiPc
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	hipHostFree
	movq	%r14, %rdi
	callq	hipHostFree
	movq	%r15, %rdi
	callq	hipHostFree
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15gpu_matrix_multPfS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15gpu_matrix_multPfS_S_iii,@object # @_Z15gpu_matrix_multPfS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z15gpu_matrix_multPfS_S_iii
	.p2align	3, 0x0
_Z15gpu_matrix_multPfS_S_iii:
	.quad	_Z30__device_stub__gpu_matrix_multPfS_S_iii
	.size	_Z15gpu_matrix_multPfS_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"w"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%f,"
	.size	.L.str.1, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"\nMatrix initalized."
	.size	.L.str.3, 20

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\nMemory allocated in device"
	.size	.L.str.4, 28

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"\nData copyed to device"
	.size	.L.str.5, 23

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nBlocks asigned"
	.size	.L.str.6, 16

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\nKernel launched."
	.size	.L.str.7, 18

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"matrix_a"
	.size	.L.str.8, 9

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"matrix_b"
	.size	.L.str.9, 9

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"matrix_c"
	.size	.L.str.10, 9

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15gpu_matrix_multPfS_S_iii"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__gpu_matrix_multPfS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15gpu_matrix_multPfS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15gpu_matrix_multPfS_S_iii ; -- Begin function _Z15gpu_matrix_multPfS_S_iii
	.globl	_Z15gpu_matrix_multPfS_S_iii
	.p2align	8
	.type	_Z15gpu_matrix_multPfS_S_iii,@function
_Z15gpu_matrix_multPfS_S_iii:           ; @_Z15gpu_matrix_multPfS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v1, s5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s5, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v6, 0
.LBB0_5:                                ; %Flow54
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15gpu_matrix_multPfS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15gpu_matrix_multPfS_S_iii, .Lfunc_end0-_Z15gpu_matrix_multPfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15gpu_matrix_multPfS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15gpu_matrix_multPfS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
