#include <cuda_runtime_api.h>
#include <stdio.h>
#include "cputime.h"

// float *accnew_gpu;
// float *velnew_gpu;
float *parforce_gpu;
float *parpot_gpu;
float *parvel_gpu;
float *acc_gpu;
float *force_gpu;
float *pos_gpu;
float *vel_gpu;

/*
extern "C"
double cputime()
{
	struct timeval tp;
	int rtn;
	rtn=gettimeofday(&tp, NULL);
	return ((double)tp.tv_sec+(1.e-6)*tp.tv_usec);
}
*/

extern "C"
void allocMemOnGPU(int nd, int np)
{
	// cudaMalloc ((void**)(&accnew_gpu), nd*np*sizeof(float));
	// cudaMalloc ((void**)(&velnew_gpu), nd*np*sizeof(float));
	cudaMalloc ((void**)(&parforce_gpu), nd*np*sizeof(float));
	cudaMalloc ((void**)(&parpot_gpu), np*sizeof(float));
	cudaMalloc ((void**)(&parvel_gpu), nd*np*sizeof(float));
	cudaMalloc ((void**)(&acc_gpu), nd*np*sizeof(float));
	cudaMalloc ((void**)(&force_gpu), nd*np*sizeof(float));
	cudaMalloc ((void**)(&pos_gpu), nd*np*sizeof(float));
	cudaMalloc ((void**)(&vel_gpu), nd*np*sizeof(float));
}

extern "C"
void copyDataToGPU(float *h_acc, float *h_force, float *h_vel, float *h_pos, int nd, int np)
{
	cudaMemcpy(acc_gpu, h_acc, nd*np*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(force_gpu, h_force, nd*np*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(vel_gpu, h_vel, nd*np*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(pos_gpu, h_pos, nd*np*sizeof(float), cudaMemcpyHostToDevice);
}


__global__ void dummyCopy(float *g_idata, float *g_odata)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;

	g_odata[idx] = g_idata[idx];
	__syncthreads();
}

// START K1 - Compute Force on Particle
__global__ void GPU_compute_forceonparticle_KERNEL(int np, int numberOfThreads, int currentMoleculeIndex, const float PI2,
													float * pos_gpu, float * parforce_gpu, float * parpot_gpu)
{
	float posx, posy, posz, dist, dist2;
    __shared__ float currentposx,currentposy,currentposz;

    int idx = blockIdx.x * blockDim.x + threadIdx.x ;

    if (idx >= numberOfThreads) return ;

    posx = pos_gpu[idx];
    posy = pos_gpu[idx+np];
    posz = pos_gpu[idx+np+np];
    currentposx = pos_gpu[currentMoleculeIndex];
    currentposy = pos_gpu[currentMoleculeIndex+np];
    currentposz = pos_gpu[currentMoleculeIndex+np+np];

    posx = currentposx - posx;
    posy = currentposy - posy;
    posz = currentposz - posz;

    dist = posx*posx + posy*posy + posz*posz;
    dist = sqrt(dist);


    dist2 = (dist < PI2) ? dist : PI2;

    if(idx==currentMoleculeIndex){
			posx=0.0;
    	posy=0.0;
    	posz=0.0;
    	dist=0.0;
    }else{
    	posx= - (posx * sin(2.0 * dist2) / dist);
    	posy= - (posy * sin(2.0 * dist2) / dist);
    	posz= - (posz * sin(2.0 * dist2) / dist);
    	dist= 0.5 * sin(dist2) * sin(dist2);
    }

    parforce_gpu[idx] = posx;
    parforce_gpu[idx+np] = posy;
    parforce_gpu[idx+np+np] = posz;
    parpot_gpu[idx] = dist;
}


extern "C"
void GPU_compute_forceonparticle(int nd, int np, int currentMoleculeIndex, const float PI2, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step == 4)
	{
		for(i=0; i<iter; i++)
		{
			//printf("Molecule index is %d in iter %d\n",currentMoleculeIndex, i);
			t0=cputime();
			GPU_compute_forceonparticle_KERNEL<<<dimGrid,dimBlock>>>(np, numberOfThreads, currentMoleculeIndex, PI2, pos_gpu, parforce_gpu, parpot_gpu);
			cudaThreadSynchronize();
			t1=cputime();
			time_sum += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum/iter;
	}
	else
*/	{
		//t0=cputime();
		//printf("Molecule index is %d in step %d\n", currentMoleculeIndex, step);
		GPU_compute_forceonparticle_KERNEL<<<dimGrid,dimBlock>>>(np, numberOfThreads, currentMoleculeIndex, PI2, pos_gpu, parforce_gpu, parpot_gpu);
		cudaThreadSynchronize();
		//t1=cputime();
		//*time_elapsed = (t1-t0);
	}
}

//END K1 - Compute Force on Particle

//START - GENERAL REDUCTION KERNEL THAT USES SHARED MEMORY
template<class T>
struct SharedMemory
{
    __device__ inline operator       T*()
    {
        extern __shared__ int __smem[];
        return (T*)__smem;
    }

    __device__ inline operator const T*() const
    {
        extern __shared__ int __smem[];
        return (T*)__smem;
    }
};

template <class T>
__global__ void reduce_wShrdMem(T *g_idata, T *g_odata, unsigned int n)
{
    T *sdata = SharedMemory<T>();

    // load shared mem
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;

    sdata[tid] = (i < n) ? g_idata[i] : 0;

    __syncthreads();

    // do reduction in shared mem
    for(unsigned int s=blockDim.x/2; s>0; s>>=1)
    {
        if (tid < s)
        {
            sdata[tid] += sdata[tid + s];
        }
        __syncthreads();
    }

    // write result for this block to global mem
	if (tid == 0)
		g_odata[blockIdx.x] = sdata[0];
	__syncthreads();
}
//END - GENERAL REDUCTION KERNEL THAT USES SHARED MEMORY

float GPU_accumulate_parpot_wShrdMem(int nd, int np, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
    	float *parpot, sum;

	dim3 dimBlock = dim3(BLOCK_SIZE, 1, 1);
	dim3 dimGrid;
	int smemSize = (BLOCK_SIZE <= 32) ? 2 * BLOCK_SIZE * sizeof(float) : BLOCK_SIZE * sizeof(float);


/*	if(step==4)
	{
		numBlocksT = numBlocks;
		numberOfThreadsT = numberOfThreads;
		cudaMalloc ((void**)(&parpotT_gpu), np*sizeof(float));
		cudaMemcpy(parpotT_gpu, parpot_gpu, np *sizeof(float), cudaMemcpyDeviceToDevice);
		for(i=0; i<iter; i++)
		{
			cudaMemcpy(parpot_gpu, parpotT_gpu, np *sizeof(float), cudaMemcpyDeviceToDevice);
			numBlocks = numBlocksT;
			numberOfThreads = numberOfThreadsT;
			t0=cputime();
			while(numberOfThreads>512)
			{
				dimGrid = dim3(numBlocks, 1, 1);
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parpot_gpu, parpot_gpu, numberOfThreads);
				cudaThreadSynchronize();
				numberOfThreads = numBlocks;
				numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
			}
			t1=cputime();
			time_sum1 += (t1-t0)*iCPS*1000*1000;
		}
		cudaFree(parpotT_gpu);

		parpot = (float*) malloc(numberOfThreads * sizeof (float));
		cudaMemcpy(parpot, parpot_gpu, numberOfThreads*sizeof(float), cudaMemcpyDeviceToHost);

		for(i=0; i<iter; i++)
		{
			sum = 0.0;
			t0=cputime();
			for(int j=0; j<numberOfThreads; j++)
				sum += parpot[j];
			t1=cputime();
			time_sum2 += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum1/iter + time_sum2/iter;
	}
	else
*/	{
		while(numBlocks > 1)
		//while(numberOfThreads>512)
		{
			dimGrid = dim3(numBlocks, 1, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parpot_gpu, parpot_gpu, numberOfThreads);
			cudaThreadSynchronize();
			numberOfThreads = numBlocks;
			numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
		}

		parpot = (float*) malloc(numberOfThreads * sizeof (float));
		cudaMemcpy(parpot, parpot_gpu, numberOfThreads*sizeof(float), cudaMemcpyDeviceToHost);
		sum = 0.0;
		for(int i=0; i<numberOfThreads; i++)
			sum += parpot[i];
	}
	free(parpot);
	return sum;
}

//END K2 - Accumulate PE with/without shared memory


//START K3 - Accumulate Force with/without shared memory
void GPU_accumulate_parforce_wShrdMem(int nd, int np, int currentMoleculeIndex, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
	int smemSize = (BLOCK_SIZE <= 32) ? 2 * BLOCK_SIZE * sizeof(float) : BLOCK_SIZE * sizeof(float);

	dim3 dimBlock = dim3(BLOCK_SIZE, 1, 1);
	dim3 dimGrid;


/*	if(step ==4)
	{
		numBlocksT = numBlocks;
		numberOfThreadsT = numberOfThreads;
		cudaMalloc ((void**)(&parforceT_gpu), nd*np*sizeof(float));
		cudaMemcpy(parforceT_gpu, parforce_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
		for(i=0; i<iter; i++)
		{
			numBlocks = numBlocksT;
			numberOfThreads = numberOfThreadsT;
			cudaMemcpy(parforce_gpu, parforceT_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
			t0=cputime();
			while(numberOfThreads>1)
			{
				dimGrid = dim3(numBlocks, 1);
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, parforce_gpu, 													numberOfThreads);
				cudaThreadSynchronize();
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), parforce_gpu+(np), 												numberOfThreads);
				cudaThreadSynchronize();
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2),
											parforce_gpu+(np*2),numberOfThreads);
				cudaThreadSynchronize();
				numberOfThreads = numBlocks;
				numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1);
			}

			dimGrid = dim3(numBlocks, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, force_gpu+currentMoleculeIndex, 											numberOfThreads);
			cudaThreadSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), force_gpu+
										(np+currentMoleculeIndex), numberOfThreads);
			cudaThreadSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2), force_gpu+
										(np+np+currentMoleculeIndex), numberOfThreads);
			cudaThreadSynchronize();
			t1=cputime();
			time_sum += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum/iter;
		cudaFree(parforceT_gpu);
	}
	else
*/	{
		while(numBlocks > 1)
		//while(numberOfThreads>1)
		{
			dimGrid = dim3(numBlocks, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, parforce_gpu, 												numberOfThreads);
			cudaThreadSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), parforce_gpu+(np), 											numberOfThreads);
			cudaThreadSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2),
										parforce_gpu+(np*2),numberOfThreads);
			cudaThreadSynchronize();
			numberOfThreads = numBlocks;
			numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1);
		}

		dimGrid = dim3(numBlocks, 1);
		reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, force_gpu+currentMoleculeIndex, 										numberOfThreads);
		// float x;
		// cudaMemcpy(&x,force_gpu + currentMoleculeIndex,sizeof(float),cudaMemcpyDeviceToHost);
		// printf("%f \n",x);
		cudaThreadSynchronize();
		reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), force_gpu+
									(np+currentMoleculeIndex), numberOfThreads);
		cudaThreadSynchronize();
		reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2), force_gpu+
									(np+np+currentMoleculeIndex), numberOfThreads);
		cudaThreadSynchronize();

	}
}
//END K3 - Accumulate Force with/without shared memory

//Accumulates PE and Force using K2 and K3
extern "C"
float GPU_seq_wShrdMem_accumulate_parpot_and_parforce(int nd, int np, int currentMoleculeIndex, int step, double *time_elap1, double *time_elap2)
{
	GPU_accumulate_parforce_wShrdMem(nd,np,currentMoleculeIndex, step, time_elap1);
	return GPU_accumulate_parpot_wShrdMem(nd, np, step, time_elap2);
}

//START K4 - Compute and accumulate KE without shared memory
//Compute KE with shared memory
template <class T>
__global__ void  GPU_compute_KE_wShrdMem(T *g_idata, T *g_odata, unsigned int n)
{
    T *sdata = SharedMemory<T>();

    // load shared mem
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;

    sdata[tid] = (i < n) ? g_idata[i] : 0;
    __syncthreads();

    sdata[tid] *= sdata[tid];
	__syncthreads();
    // do reduction in shared mem
    for(unsigned int s=blockDim.x/2; s>0; s>>=1)
    {
        if (tid < s)
        {
            sdata[tid] += sdata[tid + s];
        }
        __syncthreads();
    }

    // write result for this block to global mem
	if (tid == 0)
		g_odata[blockIdx.x] = sdata[0];
	__syncthreads();
}

extern "C"
float GPU_accumulate_KE_wShrdMem(int nd, int np, float mass, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
	float* parvel, sum;
	dim3 dimBlock = dim3(BLOCK_SIZE, 1, 1);
	dim3 dimGrid;
	int smemSize = (BLOCK_SIZE <= 32) ? 2 * BLOCK_SIZE * sizeof(double) : BLOCK_SIZE * sizeof(double);
	dimGrid = dim3(numBlocks, 1, 1);
	float val[100];
	cudaMemcpy(val,vel_gpu,100*sizeof(float),cudaMemcpyDeviceToHost);


/*	if(step == 4)
	{
		t0 = cputime();
		for(i=0; i<iter; i++)
		{
			GPU_compute_KE_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(vel_gpu, parvel_gpu, numberOfThreads);
			cudaThreadSynchronize();

		}
		t1=cputime();
		time_sum1 = (t1-t0)*iCPS*1000*1000/iter;
		numberOfThreads = numBlocks;
		numberOfThreadsT = numberOfThreads;
		numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
		numBlocksT = numBlocks;
		cudaMalloc ((void**)(&parvelT_gpu), nd*np*sizeof(float));
		cudaMemcpy(parvelT_gpu, parvel_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
		for(i=0; i<iter; i++)
		{
			numBlocks = numBlocksT;
			numberOfThreads = numberOfThreadsT;
			cudaMemcpy(parvel_gpu, parvelT_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
			t0=cputime();
			while(numBlocks>1)
			{
				dimGrid = dim3(numBlocks, 1, 1);
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parvel_gpu, parvel_gpu, numberOfThreads);
				cudaThreadSynchronize();
				numberOfThreads = numBlocks;
				numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
			}
			t1=cputime();
			time_sum2 += (t1-t0)*iCPS*1000*1000;
		}
		cudaFree(parvelT_gpu);

		parvel = (float*) malloc(numberOfThreads * sizeof (float));
		cudaMemcpy(parvel, parvel_gpu, numberOfThreads*sizeof(float), cudaMemcpyDeviceToHost);

		for(i=0; i<iter; i++)
		{
			t0=cputime();
			sum = 0.0;
			for(int j=0; j<numberOfThreads; j++)
			{
				sum += parvel[j];
			}
			t1=cputime();
			time_sum3 += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum1 + time_sum2/iter + time_sum3/iter;
	}
	else
*/	{
		GPU_compute_KE_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(vel_gpu, parvel_gpu, numberOfThreads);
		cudaThreadSynchronize();

		numberOfThreads = numBlocks;
		numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

		while(numBlocks>1)
		{
			dimGrid = dim3(numBlocks, 1, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parvel_gpu, parvel_gpu, numberOfThreads);
			cudaThreadSynchronize();
			numberOfThreads = numBlocks;
			numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
		}

		parvel = (float*) malloc(numberOfThreads * sizeof (float));
		cudaMemcpy(parvel, parvel_gpu, numberOfThreads*sizeof(float), cudaMemcpyDeviceToHost);

		sum = 0.0;
		for(int i=0; i<numberOfThreads; i++)
			sum += parvel[i];
	}
	free(parvel);
	return 0.5 * mass * sum;
}

//END K4 - Compute and accumulate KE with shared memory


//START K5 - Update position
__global__ void GPU_updatePos(int numberOfThreads, float dt, float * pos_gpu, const float * vel_gpu, const float * acc_gpu)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;
	if (idx >= numberOfThreads)
		return ;
	pos_gpu[idx] += vel_gpu[idx] * dt + 0.5 * acc_gpu[idx] * dt * dt;
}

extern "C"
void GPU_updatePos(int nd, int np, float dt, int step, double *time_elapsedCPU, float *time_elapsedGPU)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step==4)
	{
		cudaEvent_t start, stop;
		cudaEventCreate(&start);
		cudaEventCreate(&stop);
		cudaMalloc ((void**)(&posT_gpu), nd*np*sizeof(float));
		for(i=0; i<iter; i++)
		{
			dummyCopy<<<dimGrid,dimBlock>>>(pos_gpu, posT_gpu); //(input, output)
			t0=cputime();
			//cudaEventRecord(start,0);
			GPU_updatePos<<<dimGrid,dimBlock>>>(numberOfThreads, dt, pos_gpu, vel_gpu, acc_gpu);
			cudaThreadSynchronize();
			//cudaEventRecord(stop,0);
			//cudaEventSynchronize(stop);
			t1=cputime();
			//cudaEventElapsedTime(&time_diff, start, stop);
			if(i<(iter-1))
				dummyCopy<<<dimGrid,dimBlock>>>(posT_gpu, pos_gpu);
			time_sumCPU += (t1-t0)*iCPS*1000*1000;
			//time_diff /= 1000;
			//time_sumGPU += time_diff;
		}
		*time_elapsedCPU=time_sumCPU/iter;
		//*time_elapsedGPU=time_sumGPU/iter;
		cudaFree(posT_gpu);
		cudaEventDestroy(start);
		cudaEventDestroy(stop);
	}
	else
*/	{
		GPU_updatePos<<<dimGrid,dimBlock>>>(numberOfThreads, dt, pos_gpu, vel_gpu, acc_gpu) ;
		cudaThreadSynchronize();
	}
}
//END K5 - Update position


//START K6 - Update velocity
__global__ void GPU_updateVel(int numberOfThreads, float dt, float rmass, float * vel_gpu, const float * force_gpu, const float * acc_gpu)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;
	if (idx >= numberOfThreads)
		return ;
	vel_gpu[idx] += 0.5 * dt * (force_gpu[idx] * rmass + acc_gpu[idx]);
}

extern "C"
void GPU_updateVel(int nd, int np, float dt, float rmass, int step, double *time_elapsedCPU, float *time_elapsedGPU)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step==4)
	{
		cudaEvent_t start, stop;
		cudaEventCreate(&start);
		cudaEventCreate(&stop);
		cudaMalloc ((void**)(&velT_gpu), nd*np*sizeof(float));
		for(i=0; i<iter; i++)
		{
			dummyCopy<<<dimGrid,dimBlock>>>(vel_gpu, velT_gpu); //(input, output)
			t0=cputime();
			//cudaEventRecord(start,0);
			GPU_updateVel<<<dimGrid,dimBlock>>>(numberOfThreads, dt, rmass, vel_gpu, force_gpu, acc_gpu) ;
			cudaThreadSynchronize();
			//cudaEventRecord(stop,0);
			//cudaEventSynchronize(stop);
			t1=cputime();
			//cudaEventElapsedTime(&time_diff, start, stop);
			if(i<(iter-1))
				dummyCopy<<<dimGrid,dimBlock>>>(velT_gpu, vel_gpu);
			time_sumCPU += (t1-t0)*iCPS*1000*1000;
			//time_diff /= 1000;
			//time_sumGPU += time_diff;
		}
		*time_elapsedCPU=time_sumCPU/iter;
		//*time_elapsedGPU=time_sumGPU/iter;
		cudaFree(velT_gpu);
		cudaEventDestroy(start);
		cudaEventDestroy(stop);
	}
	else
*/	{
		GPU_updateVel<<<dimGrid,dimBlock>>>(numberOfThreads, dt, rmass, vel_gpu, force_gpu, acc_gpu) ;
		cudaThreadSynchronize();
	}
}
//END K6 - Update velocity


//START K7 - Update acceleration
__global__ void GPU_updateAcc(int numberOfThreads, float rmass, float * acc_gpu, const float * force_gpu)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;
	if (idx >= numberOfThreads)
		return ;
	acc_gpu[idx] = force_gpu[idx] * rmass;
}

extern "C"
void GPU_updateAcc(int nd, int np, float rmass, int step, double *time_elapsedCPU, float *time_elapsedGPU)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step==4)
	{
		cudaEvent_t start, stop;
		cudaEventCreate(&start);
		cudaEventCreate(&stop);
		for(i=0; i<iter; i++)
		{
			t0=cputime();
			//cudaEventRecord(start,0);
			GPU_updateAcc<<<dimGrid,dimBlock>>>(numberOfThreads, rmass, acc_gpu, force_gpu) ;
			cudaThreadSynchronize();
			//cudaEventRecord(stop,0);
			//cudaEventSynchronize(stop);
			t1=cputime();
			//cudaEventElapsedTime(&time_diff, start, stop);
			time_sumCPU += (t1-t0)*iCPS*1000*1000;
			//time_diff /= 1000;
			//time_sumGPU += time_diff;
		}
		*time_elapsedCPU=time_sumCPU/iter;
		//*time_elapsedGPU = time_sumGPU/iter;
		cudaEventDestroy(start);
		cudaEventDestroy(stop);
	}
	else
*/	{
		GPU_updateAcc<<<dimGrid,dimBlock>>>(numberOfThreads, rmass, acc_gpu, force_gpu) ;
		cudaThreadSynchronize();
	}
}
//END K7 - Update acceleration

	.file	"tmpxft_00308867_00000000-6_MD_kernel_perfsig.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2046:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2046:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0, @function
_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0:
.LFB2201:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	leaq	32(%rsp), %rdx
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15reduce_wShrdMemIfEvPT_S1_j(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2201:
	.size	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0, .-_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
	.section	.text._Z15reduce_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z15reduce_wShrdMemIfEvPT_S1_j,comdat
	.weak	_Z15reduce_wShrdMemIfEvPT_S1_j
	.type	_Z15reduce_wShrdMemIfEvPT_S1_j, @function
_Z15reduce_wShrdMemIfEvPT_S1_j:
.LFB2129:
	.cfi_startproc
	endbr64
	jmp	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
	.cfi_endproc
.LFE2129:
	.size	_Z15reduce_wShrdMemIfEvPT_S1_j, .-_Z15reduce_wShrdMemIfEvPT_S1_j
	.text
	.type	_ZL52__device_stub__Z23GPU_compute_KE_wShrdMemIfEvPT_S1_jPfS_j, @function
_ZL52__device_stub__Z23GPU_compute_KE_wShrdMemIfEvPT_S1_jPfS_j:
.LFB2074:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2074:
	.size	_ZL52__device_stub__Z23GPU_compute_KE_wShrdMemIfEvPT_S1_jPfS_j, .-_ZL52__device_stub__Z23GPU_compute_KE_wShrdMemIfEvPT_S1_jPfS_j
	.section	.text._Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,comdat
	.weak	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.type	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j, @function
_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j:
.LFB2130:
	.cfi_startproc
	endbr64
	jmp	_ZL52__device_stub__Z23GPU_compute_KE_wShrdMemIfEvPT_S1_jPfS_j
	.cfi_endproc
.LFE2130:
	.size	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j, .-_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.text
	.globl	allocMemOnGPU
	.type	allocMemOnGPU, @function
allocMemOnGPU:
.LFB2028:
	.cfi_startproc
	endbr64
	imull	%esi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rax
	.cfi_def_cfa_offset 32
	movslq	%edi, %rbx
	leaq	parforce_gpu(%rip), %rdi
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movslq	%ebp, %rsi
	leaq	parpot_gpu(%rip), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	parvel_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	acc_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	force_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	pos_gpu(%rip), %rdi
	call	cudaMalloc@PLT
	popq	%rdx
	.cfi_def_cfa_offset 24
	movq	%rbx, %rsi
	leaq	vel_gpu(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2028:
	.size	allocMemOnGPU, .-allocMemOnGPU
	.globl	copyDataToGPU
	.type	copyDataToGPU, @function
copyDataToGPU:
.LFB2029:
	.cfi_startproc
	endbr64
	imull	%r9d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rsi, %r13
	movq	%rdi, %rsi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rcx, %rbp
	movl	$1, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movslq	%r8d, %rbx
	pushq	%rax
	.cfi_def_cfa_offset 48
	salq	$2, %rbx
	movq	acc_gpu(%rip), %rdi
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	movq	force_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	movq	vel_gpu(%rip), %rdi
	call	cudaMemcpy@PLT
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	movq	pos_gpu(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	cudaMemcpy@PLT
	.cfi_endproc
.LFE2029:
	.size	copyDataToGPU, .-copyDataToGPU
	.globl	_Z30GPU_accumulate_parpot_wShrdMemiiiPd
	.type	_Z30GPU_accumulate_parpot_wShrdMemiiiPd, @function
_Z30GPU_accumulate_parpot_wShrdMemiiiPd:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	%esi, %eax
	movl	$128, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%esi, %ebx
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	testl	$127, %esi
	setne	%bpl
	cltd
	movl	$1, 32(%rsp)
	idivl	%ecx
	addl	%eax, %ebp
	movl	$33554433, %eax
	salq	$7, %rax
	movq	%rax, 24(%rsp)
	subq	$127, %rax
	movq	%rax, 40(%rsp)
.L18:
	cmpl	$1, %ebp
	jle	.L24
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	movl	%ebp, 36(%rsp)
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	movl	$512, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	parpot_gpu(%rip), %rdi
	movl	%ebx, %edx
	movq	%rdi, %rsi
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L19:
	call	cudaThreadSynchronize@PLT
	movl	%ebp, %edx
	movl	%ebp, %eax
	movl	%ebp, %ebx
	andl	$127, %edx
	sarl	$7, %eax
	cmpl	$1, %edx
	sbbl	$-1, %eax
	movl	%eax, %ebp
	jmp	.L18
.L24:
	movslq	%ebx, %r12
	salq	$2, %r12
	movq	%r12, %rdi
	call	malloc@PLT
	movq	parpot_gpu(%rip), %rsi
	movl	$2, %ecx
	movq	%r12, %rdx
	movq	%rax, %rdi
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L21:
	cmpl	%eax, %ebx
	jle	.L25
	addss	0(%rbp,%rax,4), %xmm0
	incq	%rax
	jmp	.L21
.L25:
	movq	%rbp, %rdi
	movss	%xmm0, 12(%rsp)
	call	free@PLT
	movss	12(%rsp), %xmm0
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z30GPU_accumulate_parpot_wShrdMemiiiPd, .-_Z30GPU_accumulate_parpot_wShrdMemiiiPd
	.globl	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd
	.type	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd, @function
_Z32GPU_accumulate_parforce_wShrdMemiiiiPd:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$128, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movslq	%esi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r14d, %eax
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r14, %rbx
	leal	(%rbx,%rbx), %r15d
	movl	%ebx, %r13d
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	testl	$127, %r14d
	setne	%r12b
	cltd
	movl	$1, 32(%rsp)
	salq	$2, %r14
	idivl	%ecx
	addl	%eax, %r12d
	movl	$33554433, %eax
	salq	$7, %rax
	movq	%rax, 24(%rsp)
	subq	$127, %rax
	movq	%rax, 40(%rsp)
	movslq	%r15d, %rax
	salq	$2, %rax
	movq	%rax, 8(%rsp)
.L27:
	cmpl	$1, %r12d
	movl	%r12d, 36(%rsp)
	movq	24(%rsp), %rdx
	movl	$0, %r9d
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	movl	$512, %r8d
	movq	36(%rsp), %rdi
	jle	.L36
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	parforce_gpu(%rip), %rdi
	movl	%r13d, %edx
	movq	%rdi, %rsi
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L28:
	call	cudaThreadSynchronize@PLT
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	$512, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	parforce_gpu(%rip), %rdi
	movl	%r13d, %edx
	addq	%r14, %rdi
	movq	%rdi, %rsi
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L29:
	call	cudaThreadSynchronize@PLT
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	$512, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	8(%rsp), %rdi
	addq	parforce_gpu(%rip), %rdi
	movl	%r13d, %edx
	movq	%rdi, %rsi
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L30:
	call	cudaThreadSynchronize@PLT
	movl	%r12d, %edx
	movl	%r12d, %eax
	movl	%r12d, %r13d
	andl	$127, %edx
	sarl	$7, %eax
	cmpl	$1, %edx
	sbbl	$-1, %eax
	movl	%eax, %r12d
	jmp	.L27
.L36:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	force_gpu(%rip), %rdx
	movslq	%ebp, %rax
	movq	parforce_gpu(%rip), %rdi
	leaq	(%rdx,%rax,4), %rsi
	movl	%r13d, %edx
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L32:
	call	cudaThreadSynchronize@PLT
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	$512, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	force_gpu(%rip), %rax
	movq	parforce_gpu(%rip), %rdi
	addl	%ebp, %ebx
	movl	%r13d, %edx
	movslq	%ebx, %rbx
	leaq	(%rax,%rbx,4), %rsi
	addq	%r14, %rdi
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L33:
	call	cudaThreadSynchronize@PLT
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	$512, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	force_gpu(%rip), %rax
	addl	%r15d, %ebp
	movslq	%r15d, %r15
	movl	%r13d, %edx
	movslq	%ebp, %rbp
	leaq	(%rax,%rbp,4), %rsi
	movq	parforce_gpu(%rip), %rax
	leaq	(%rax,%r15,4), %rdi
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L34:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaThreadSynchronize@PLT
	.cfi_endproc
.LFE2036:
	.size	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd, .-_Z32GPU_accumulate_parforce_wShrdMemiiiiPd
	.globl	GPU_seq_wShrdMem_accumulate_parpot_and_parforce
	.type	GPU_seq_wShrdMem_accumulate_parpot_and_parforce, @function
GPU_seq_wShrdMem_accumulate_parpot_and_parforce:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%r9, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%ecx, %r12d
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%esi, 12(%rsp)
	movl	%edi, 8(%rsp)
	call	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd
	movl	12(%rsp), %esi
	movl	8(%rsp), %edi
	movq	%r13, %rcx
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	movl	%r12d, %edx
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z30GPU_accumulate_parpot_wShrdMemiiiPd
	.cfi_endproc
.LFE2037:
	.size	GPU_seq_wShrdMem_accumulate_parpot_and_parforce, .-GPU_seq_wShrdMem_accumulate_parpot_and_parforce
	.globl	GPU_accumulate_KE_wShrdMem
	.type	GPU_accumulate_KE_wShrdMem, @function
GPU_accumulate_KE_wShrdMem:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	imull	%esi, %edi
	movl	$128, %ecx
	movd	%xmm0, %r14d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	movl	%edi, %ebp
	subq	$456, %rsp
	.cfi_def_cfa_offset 496
	movq	vel_gpu(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 440(%rsp)
	xorl	%eax, %eax
	testl	$127, %edi
	movl	%edi, %eax
	leaq	40(%rsp), %rdi
	setne	%bl
	cltd
	movl	$1, 24(%rsp)
	idivl	%ecx
	movl	$2, %ecx
	movl	$400, %edx
	addl	%eax, %ebx
	movl	$33554433, %eax
	salq	$7, %rax
	movl	%ebx, 28(%rsp)
	movq	%rax, 16(%rsp)
	subq	$127, %rax
	movq	%rax, 32(%rsp)
	call	cudaMemcpy@PLT
	movl	24(%rsp), %ecx
	movl	36(%rsp), %esi
	xorl	%r9d, %r9d
	movq	16(%rsp), %rdx
	movq	28(%rsp), %rdi
	movl	$1024, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	parvel_gpu(%rip), %rsi
	movq	vel_gpu(%rip), %rdi
	movl	%ebp, %edx
	call	_ZL52__device_stub__Z23GPU_compute_KE_wShrdMemIfEvPT_S1_jPfS_j
.L40:
	call	cudaThreadSynchronize@PLT
	movl	%ebx, %eax
	movl	$128, %ecx
	cltd
	idivl	%ecx
	movl	%ebx, %edx
	andl	$127, %edx
.L48:
	cmpl	$1, %edx
	sbbl	$-1, %eax
	movl	%eax, %ebp
	cmpl	$1, %eax
	jle	.L49
	movl	24(%rsp), %ecx
	movq	16(%rsp), %rdx
	movl	%ebp, 28(%rsp)
	xorl	%r9d, %r9d
	movq	28(%rsp), %rdi
	movl	36(%rsp), %esi
	movl	$1024, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	parvel_gpu(%rip), %rdi
	movl	%ebx, %edx
	movq	%rdi, %rsi
	call	_Z38__wrapper__device_stub_reduce_wShrdMemIfEvRPT_S2_Rj.isra.0
.L42:
	call	cudaThreadSynchronize@PLT
	movl	%ebp, %eax
	movl	%ebp, %edx
	movl	%ebp, %ebx
	sarl	$7, %eax
	andl	$127, %edx
	jmp	.L48
.L49:
	movslq	%ebx, %r12
	salq	$2, %r12
	movq	%r12, %rdi
	call	malloc@PLT
	movq	parvel_gpu(%rip), %rsi
	movl	$2, %ecx
	movq	%r12, %rdx
	movq	%rax, %rdi
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	xorps	%xmm1, %xmm1
.L44:
	cmpl	%eax, %ebx
	jle	.L50
	addss	0(%rbp,%rax,4), %xmm1
	incq	%rax
	jmp	.L44
.L50:
	movq	%rbp, %rdi
	movss	%xmm1, 12(%rsp)
	call	free@PLT
	movd	%r14d, %xmm2
	movss	12(%rsp), %xmm1
	cvtss2sd	%xmm2, %xmm0
	mulsd	.LC1(%rip), %xmm0
	cvtss2sd	%xmm1, %xmm1
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movq	440(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$456, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	GPU_accumulate_KE_wShrdMem, .-GPU_accumulate_KE_wShrdMem
	.globl	_Z30__device_stub__Z9dummyCopyPfS_PfS_
	.type	_Z30__device_stub__Z9dummyCopyPfS_PfS_, @function
_Z30__device_stub__Z9dummyCopyPfS_PfS_:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9dummyCopyPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L51:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z30__device_stub__Z9dummyCopyPfS_PfS_, .-_Z30__device_stub__Z9dummyCopyPfS_PfS_
	.globl	_Z9dummyCopyPfS_
	.type	_Z9dummyCopyPfS_, @function
_Z9dummyCopyPfS_:
.LFB2069:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z9dummyCopyPfS_PfS_
	.cfi_endproc
.LFE2069:
	.size	_Z9dummyCopyPfS_, .-_Z9dummyCopyPfS_
	.globl	_Z62__device_stub__Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_iiifPfS_S_
	.type	_Z62__device_stub__Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_iiifPfS_S_, @function
_Z62__device_stub__Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_iiifPfS_S_:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L56:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z62__device_stub__Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_iiifPfS_S_, .-_Z62__device_stub__Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_iiifPfS_S_
	.globl	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.type	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_, @function
_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_iiifPfS_S_
	.cfi_endproc
.LFE2071:
	.size	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_, .-_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.globl	GPU_compute_forceonparticle
	.type	GPU_compute_forceonparticle, @function
GPU_compute_forceonparticle:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%ecx, %ecx
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%esi, %ebx
	movl	%ebx, %eax
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	andl	$127, %esi
	movl	$128, %esi
	setne	%cl
	cltd
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	idivl	%esi
	movss	%xmm0, 12(%rsp)
	movl	$33554433, %edx
	salq	$7, %rdx
	addl	%eax, %ecx
	movabsq	$4294967297, %rax
	movl	%ecx, 24(%rsp)
	movl	$1, %ecx
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L62
	movq	parpot_gpu(%rip), %r9
	movl	%ebp, %edx
	movl	%ebx, %esi
	movl	%ebx, %edi
	movq	parforce_gpu(%rip), %r8
	movq	pos_gpu(%rip), %rcx
	call	_Z62__device_stub__Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_iiifPfS_S_
.L62:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	cudaThreadSynchronize@PLT
	.cfi_endproc
.LFE2030:
	.size	GPU_compute_forceonparticle, .-GPU_compute_forceonparticle
	.globl	_Z41__device_stub__Z13GPU_updatePosifPfPKfS1_ifPfPKfS1_
	.type	_Z41__device_stub__Z13GPU_updatePosifPfPKfS1_ifPfPKfS1_, @function
_Z41__device_stub__Z13GPU_updatePosifPfPKfS1_ifPfPKfS1_:
.LFB2076:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13GPU_updatePosifPfPKfS1_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L64:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2076:
	.size	_Z41__device_stub__Z13GPU_updatePosifPfPKfS1_ifPfPKfS1_, .-_Z41__device_stub__Z13GPU_updatePosifPfPKfS1_ifPfPKfS1_
	.globl	_Z13GPU_updatePosifPfPKfS1_
	.type	_Z13GPU_updatePosifPfPKfS1_, @function
_Z13GPU_updatePosifPfPKfS1_:
.LFB2077:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z13GPU_updatePosifPfPKfS1_ifPfPKfS1_
	.cfi_endproc
.LFE2077:
	.size	_Z13GPU_updatePosifPfPKfS1_, .-_Z13GPU_updatePosifPfPKfS1_
	.globl	GPU_updatePos
	.type	GPU_updatePos, @function
GPU_updatePos:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edi, %ebx
	xorl	%ecx, %ecx
	imull	%esi, %ebx
	movl	$128, %esi
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	movl	%ebx, %eax
	testb	$127, %bl
	movss	%xmm0, 12(%rsp)
	setne	%cl
	cltd
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	idivl	%esi
	movl	$33554433, %edx
	salq	$7, %rdx
	addl	%eax, %ecx
	movabsq	$4294967297, %rax
	movl	%ecx, 24(%rsp)
	movl	$1, %ecx
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L70
	movq	acc_gpu(%rip), %rcx
	movq	vel_gpu(%rip), %rdx
	movl	%ebx, %edi
	movq	pos_gpu(%rip), %rsi
	call	_Z41__device_stub__Z13GPU_updatePosifPfPKfS1_ifPfPKfS1_
.L70:
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	cudaThreadSynchronize@PLT
	.cfi_endproc
.LFE2041:
	.size	GPU_updatePos, .-GPU_updatePos
	.globl	_Z42__device_stub__Z13GPU_updateVeliffPfPKfS1_iffPfPKfS1_
	.type	_Z42__device_stub__Z13GPU_updateVeliffPfPKfS1_iffPfPKfS1_, @function
_Z42__device_stub__Z13GPU_updateVeliffPfPKfS1_iffPfPKfS1_:
.LFB2078:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	64(%rsp), %rcx
	movss	%xmm0, 40(%rsp)
	movss	%xmm1, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z13GPU_updateVeliffPfPKfS1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L72:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L74
	call	__stack_chk_fail@PLT
.L74:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2078:
	.size	_Z42__device_stub__Z13GPU_updateVeliffPfPKfS1_iffPfPKfS1_, .-_Z42__device_stub__Z13GPU_updateVeliffPfPKfS1_iffPfPKfS1_
	.globl	_Z13GPU_updateVeliffPfPKfS1_
	.type	_Z13GPU_updateVeliffPfPKfS1_, @function
_Z13GPU_updateVeliffPfPKfS1_:
.LFB2079:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z13GPU_updateVeliffPfPKfS1_iffPfPKfS1_
	.cfi_endproc
.LFE2079:
	.size	_Z13GPU_updateVeliffPfPKfS1_, .-_Z13GPU_updateVeliffPfPKfS1_
	.globl	GPU_updateVel
	.type	GPU_updateVel, @function
GPU_updateVel:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edi, %ebx
	xorl	%ecx, %ecx
	imull	%esi, %ebx
	movl	$128, %esi
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	movl	%ebx, %eax
	testb	$127, %bl
	movss	%xmm0, 12(%rsp)
	setne	%cl
	cltd
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	idivl	%esi
	movss	%xmm1, 8(%rsp)
	movl	$33554433, %edx
	salq	$7, %rdx
	addl	%eax, %ecx
	movabsq	$4294967297, %rax
	movl	%ecx, 24(%rsp)
	movl	$1, %ecx
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L78
	movq	acc_gpu(%rip), %rcx
	movq	force_gpu(%rip), %rdx
	movl	%ebx, %edi
	movq	vel_gpu(%rip), %rsi
	call	_Z42__device_stub__Z13GPU_updateVeliffPfPKfS1_iffPfPKfS1_
.L78:
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	cudaThreadSynchronize@PLT
	.cfi_endproc
.LFE2042:
	.size	GPU_updateVel, .-GPU_updateVel
	.globl	_Z38__device_stub__Z13GPU_updateAccifPfPKfifPfPKf
	.type	_Z38__device_stub__Z13GPU_updateAccifPfPKfifPfPKf, @function
_Z38__device_stub__Z13GPU_updateAccifPfPKfifPfPKf:
.LFB2080:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movss	%xmm0, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L80
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13GPU_updateAccifPfPKf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L80:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L82
	call	__stack_chk_fail@PLT
.L82:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2080:
	.size	_Z38__device_stub__Z13GPU_updateAccifPfPKfifPfPKf, .-_Z38__device_stub__Z13GPU_updateAccifPfPKfifPfPKf
	.globl	_Z13GPU_updateAccifPfPKf
	.type	_Z13GPU_updateAccifPfPKf, @function
_Z13GPU_updateAccifPfPKf:
.LFB2081:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13GPU_updateAccifPfPKfifPfPKf
	.cfi_endproc
.LFE2081:
	.size	_Z13GPU_updateAccifPfPKf, .-_Z13GPU_updateAccifPfPKf
	.globl	GPU_updateAcc
	.type	GPU_updateAcc, @function
GPU_updateAcc:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edi, %ebx
	xorl	%ecx, %ecx
	imull	%esi, %ebx
	movl	$128, %esi
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	movl	%ebx, %eax
	testb	$127, %bl
	movss	%xmm0, 12(%rsp)
	setne	%cl
	cltd
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	idivl	%esi
	movl	$33554433, %edx
	salq	$7, %rdx
	addl	%eax, %ecx
	movabsq	$4294967297, %rax
	movl	%ecx, 24(%rsp)
	movl	$1, %ecx
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L86
	movq	force_gpu(%rip), %rdx
	movq	acc_gpu(%rip), %rsi
	movl	%ebx, %edi
	call	_Z38__device_stub__Z13GPU_updateAccifPfPKfifPfPKf
.L86:
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	cudaThreadSynchronize@PLT
	.cfi_endproc
.LFE2043:
	.size	GPU_updateAcc, .-GPU_updateAcc
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z13GPU_updateAccifPfPKf"
.LC3:
	.string	"_Z13GPU_updateVeliffPfPKfS1_"
.LC4:
	.string	"_Z13GPU_updatePosifPfPKfS1_"
.LC5:
	.string	"_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j"
.LC6:
	.string	"_Z15reduce_wShrdMemIfEvPT_S1_j"
.LC7:
	.string	"_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_"
.LC8:
	.string	"_Z9dummyCopyPfS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13GPU_updateAccifPfPKf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13GPU_updateVeliffPfPKfS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13GPU_updatePosifPfPKfS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15reduce_wShrdMemIfEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9dummyCopyPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2083:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	vel_gpu
	.bss
	.align 8
	.type	vel_gpu, @object
	.size	vel_gpu, 8
vel_gpu:
	.zero	8
	.globl	pos_gpu
	.align 8
	.type	pos_gpu, @object
	.size	pos_gpu, 8
pos_gpu:
	.zero	8
	.globl	force_gpu
	.align 8
	.type	force_gpu, @object
	.size	force_gpu, 8
force_gpu:
	.zero	8
	.globl	acc_gpu
	.align 8
	.type	acc_gpu, @object
	.size	acc_gpu, 8
acc_gpu:
	.zero	8
	.globl	parvel_gpu
	.align 8
	.type	parvel_gpu, @object
	.size	parvel_gpu, 8
parvel_gpu:
	.zero	8
	.globl	parpot_gpu
	.align 8
	.type	parpot_gpu, @object
	.size	parpot_gpu, 8
parpot_gpu:
	.zero	8
	.globl	parforce_gpu
	.align 8
	.type	parforce_gpu, @object
	.size	parforce_gpu, 8
parforce_gpu:
	.zero	8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1071644672
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include "cputime.h"

// float *accnew_gpu;
// float *velnew_gpu;
float *parforce_gpu;
float *parpot_gpu;
float *parvel_gpu;
float *acc_gpu;
float *force_gpu;
float *pos_gpu;
float *vel_gpu;

/*
extern "C"
double cputime()
{
	struct timeval tp;
	int rtn;
	rtn=gettimeofday(&tp, NULL);
	return ((double)tp.tv_sec+(1.e-6)*tp.tv_usec);
}
*/

extern "C"
void allocMemOnGPU(int nd, int np)
{
	// cudaMalloc ((void**)(&accnew_gpu), nd*np*sizeof(float));
	// cudaMalloc ((void**)(&velnew_gpu), nd*np*sizeof(float));
	hipMalloc ((void**)(&parforce_gpu), nd*np*sizeof(float));
	hipMalloc ((void**)(&parpot_gpu), np*sizeof(float));
	hipMalloc ((void**)(&parvel_gpu), nd*np*sizeof(float));
	hipMalloc ((void**)(&acc_gpu), nd*np*sizeof(float));
	hipMalloc ((void**)(&force_gpu), nd*np*sizeof(float));
	hipMalloc ((void**)(&pos_gpu), nd*np*sizeof(float));
	hipMalloc ((void**)(&vel_gpu), nd*np*sizeof(float));
}

extern "C"
void copyDataToGPU(float *h_acc, float *h_force, float *h_vel, float *h_pos, int nd, int np)
{
	hipMemcpy(acc_gpu, h_acc, nd*np*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(force_gpu, h_force, nd*np*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(vel_gpu, h_vel, nd*np*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(pos_gpu, h_pos, nd*np*sizeof(float), hipMemcpyHostToDevice);
}


__global__ void dummyCopy(float *g_idata, float *g_odata)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;

	g_odata[idx] = g_idata[idx];
	__syncthreads();
}

// START K1 - Compute Force on Particle
__global__ void GPU_compute_forceonparticle_KERNEL(int np, int numberOfThreads, int currentMoleculeIndex, const float PI2,
													float * pos_gpu, float * parforce_gpu, float * parpot_gpu)
{
	float posx, posy, posz, dist, dist2;
    __shared__ float currentposx,currentposy,currentposz;

    int idx = blockIdx.x * blockDim.x + threadIdx.x ;

    if (idx >= numberOfThreads) return ;

    posx = pos_gpu[idx];
    posy = pos_gpu[idx+np];
    posz = pos_gpu[idx+np+np];
    currentposx = pos_gpu[currentMoleculeIndex];
    currentposy = pos_gpu[currentMoleculeIndex+np];
    currentposz = pos_gpu[currentMoleculeIndex+np+np];

    posx = currentposx - posx;
    posy = currentposy - posy;
    posz = currentposz - posz;

    dist = posx*posx + posy*posy + posz*posz;
    dist = sqrt(dist);


    dist2 = (dist < PI2) ? dist : PI2;

    if(idx==currentMoleculeIndex){
			posx=0.0;
    	posy=0.0;
    	posz=0.0;
    	dist=0.0;
    }else{
    	posx= - (posx * sin(2.0 * dist2) / dist);
    	posy= - (posy * sin(2.0 * dist2) / dist);
    	posz= - (posz * sin(2.0 * dist2) / dist);
    	dist= 0.5 * sin(dist2) * sin(dist2);
    }

    parforce_gpu[idx] = posx;
    parforce_gpu[idx+np] = posy;
    parforce_gpu[idx+np+np] = posz;
    parpot_gpu[idx] = dist;
}


extern "C"
void GPU_compute_forceonparticle(int nd, int np, int currentMoleculeIndex, const float PI2, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step == 4)
	{
		for(i=0; i<iter; i++)
		{
			//printf("Molecule index is %d in iter %d\n",currentMoleculeIndex, i);
			t0=cputime();
			GPU_compute_forceonparticle_KERNEL<<<dimGrid,dimBlock>>>(np, numberOfThreads, currentMoleculeIndex, PI2, pos_gpu, parforce_gpu, parpot_gpu);
			cudaThreadSynchronize();
			t1=cputime();
			time_sum += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum/iter;
	}
	else
*/	{
		//t0=cputime();
		//printf("Molecule index is %d in step %d\n", currentMoleculeIndex, step);
		GPU_compute_forceonparticle_KERNEL<<<dimGrid,dimBlock>>>(np, numberOfThreads, currentMoleculeIndex, PI2, pos_gpu, parforce_gpu, parpot_gpu);
		hipDeviceSynchronize();
		//t1=cputime();
		//*time_elapsed = (t1-t0);
	}
}

//END K1 - Compute Force on Particle

//START - GENERAL REDUCTION KERNEL THAT USES SHARED MEMORY
template<class T>
struct SharedMemory
{
    __device__ inline operator       T*()
    {
        extern __shared__ int __smem[];
        return (T*)__smem;
    }

    __device__ inline operator const T*() const
    {
        extern __shared__ int __smem[];
        return (T*)__smem;
    }
};

template <class T>
__global__ void reduce_wShrdMem(T *g_idata, T *g_odata, unsigned int n)
{
    T *sdata = SharedMemory<T>();

    // load shared mem
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;

    sdata[tid] = (i < n) ? g_idata[i] : 0;

    __syncthreads();

    // do reduction in shared mem
    for(unsigned int s=blockDim.x/2; s>0; s>>=1)
    {
        if (tid < s)
        {
            sdata[tid] += sdata[tid + s];
        }
        __syncthreads();
    }

    // write result for this block to global mem
	if (tid == 0)
		g_odata[blockIdx.x] = sdata[0];
	__syncthreads();
}
//END - GENERAL REDUCTION KERNEL THAT USES SHARED MEMORY

float GPU_accumulate_parpot_wShrdMem(int nd, int np, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
    	float *parpot, sum;

	dim3 dimBlock = dim3(BLOCK_SIZE, 1, 1);
	dim3 dimGrid;
	int smemSize = (BLOCK_SIZE <= 32) ? 2 * BLOCK_SIZE * sizeof(float) : BLOCK_SIZE * sizeof(float);


/*	if(step==4)
	{
		numBlocksT = numBlocks;
		numberOfThreadsT = numberOfThreads;
		cudaMalloc ((void**)(&parpotT_gpu), np*sizeof(float));
		cudaMemcpy(parpotT_gpu, parpot_gpu, np *sizeof(float), cudaMemcpyDeviceToDevice);
		for(i=0; i<iter; i++)
		{
			cudaMemcpy(parpot_gpu, parpotT_gpu, np *sizeof(float), cudaMemcpyDeviceToDevice);
			numBlocks = numBlocksT;
			numberOfThreads = numberOfThreadsT;
			t0=cputime();
			while(numberOfThreads>512)
			{
				dimGrid = dim3(numBlocks, 1, 1);
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parpot_gpu, parpot_gpu, numberOfThreads);
				cudaThreadSynchronize();
				numberOfThreads = numBlocks;
				numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
			}
			t1=cputime();
			time_sum1 += (t1-t0)*iCPS*1000*1000;
		}
		cudaFree(parpotT_gpu);

		parpot = (float*) malloc(numberOfThreads * sizeof (float));
		cudaMemcpy(parpot, parpot_gpu, numberOfThreads*sizeof(float), cudaMemcpyDeviceToHost);

		for(i=0; i<iter; i++)
		{
			sum = 0.0;
			t0=cputime();
			for(int j=0; j<numberOfThreads; j++)
				sum += parpot[j];
			t1=cputime();
			time_sum2 += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum1/iter + time_sum2/iter;
	}
	else
*/	{
		while(numBlocks > 1)
		//while(numberOfThreads>512)
		{
			dimGrid = dim3(numBlocks, 1, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parpot_gpu, parpot_gpu, numberOfThreads);
			hipDeviceSynchronize();
			numberOfThreads = numBlocks;
			numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
		}

		parpot = (float*) malloc(numberOfThreads * sizeof (float));
		hipMemcpy(parpot, parpot_gpu, numberOfThreads*sizeof(float), hipMemcpyDeviceToHost);
		sum = 0.0;
		for(int i=0; i<numberOfThreads; i++)
			sum += parpot[i];
	}
	free(parpot);
	return sum;
}

//END K2 - Accumulate PE with/without shared memory


//START K3 - Accumulate Force with/without shared memory
void GPU_accumulate_parforce_wShrdMem(int nd, int np, int currentMoleculeIndex, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
	int smemSize = (BLOCK_SIZE <= 32) ? 2 * BLOCK_SIZE * sizeof(float) : BLOCK_SIZE * sizeof(float);

	dim3 dimBlock = dim3(BLOCK_SIZE, 1, 1);
	dim3 dimGrid;


/*	if(step ==4)
	{
		numBlocksT = numBlocks;
		numberOfThreadsT = numberOfThreads;
		cudaMalloc ((void**)(&parforceT_gpu), nd*np*sizeof(float));
		cudaMemcpy(parforceT_gpu, parforce_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
		for(i=0; i<iter; i++)
		{
			numBlocks = numBlocksT;
			numberOfThreads = numberOfThreadsT;
			cudaMemcpy(parforce_gpu, parforceT_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
			t0=cputime();
			while(numberOfThreads>1)
			{
				dimGrid = dim3(numBlocks, 1);
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, parforce_gpu, 													numberOfThreads);
				cudaThreadSynchronize();
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), parforce_gpu+(np), 												numberOfThreads);
				cudaThreadSynchronize();
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2),
											parforce_gpu+(np*2),numberOfThreads);
				cudaThreadSynchronize();
				numberOfThreads = numBlocks;
				numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1);
			}

			dimGrid = dim3(numBlocks, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, force_gpu+currentMoleculeIndex, 											numberOfThreads);
			cudaThreadSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), force_gpu+
										(np+currentMoleculeIndex), numberOfThreads);
			cudaThreadSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2), force_gpu+
										(np+np+currentMoleculeIndex), numberOfThreads);
			cudaThreadSynchronize();
			t1=cputime();
			time_sum += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum/iter;
		cudaFree(parforceT_gpu);
	}
	else
*/	{
		while(numBlocks > 1)
		//while(numberOfThreads>1)
		{
			dimGrid = dim3(numBlocks, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, parforce_gpu, 												numberOfThreads);
			hipDeviceSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), parforce_gpu+(np), 											numberOfThreads);
			hipDeviceSynchronize();
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2),
										parforce_gpu+(np*2),numberOfThreads);
			hipDeviceSynchronize();
			numberOfThreads = numBlocks;
			numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1);
		}

		dimGrid = dim3(numBlocks, 1);
		reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu, force_gpu+currentMoleculeIndex, 										numberOfThreads);
		// float x;
		// cudaMemcpy(&x,force_gpu + currentMoleculeIndex,sizeof(float),cudaMemcpyDeviceToHost);
		// printf("%f \n",x);
		hipDeviceSynchronize();
		reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np), force_gpu+
									(np+currentMoleculeIndex), numberOfThreads);
		hipDeviceSynchronize();
		reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parforce_gpu+(np*2), force_gpu+
									(np+np+currentMoleculeIndex), numberOfThreads);
		hipDeviceSynchronize();

	}
}
//END K3 - Accumulate Force with/without shared memory

//Accumulates PE and Force using K2 and K3
extern "C"
float GPU_seq_wShrdMem_accumulate_parpot_and_parforce(int nd, int np, int currentMoleculeIndex, int step, double *time_elap1, double *time_elap2)
{
	GPU_accumulate_parforce_wShrdMem(nd,np,currentMoleculeIndex, step, time_elap1);
	return GPU_accumulate_parpot_wShrdMem(nd, np, step, time_elap2);
}

//START K4 - Compute and accumulate KE without shared memory
//Compute KE with shared memory
template <class T>
__global__ void  GPU_compute_KE_wShrdMem(T *g_idata, T *g_odata, unsigned int n)
{
    T *sdata = SharedMemory<T>();

    // load shared mem
    unsigned int tid = threadIdx.x;
    unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;

    sdata[tid] = (i < n) ? g_idata[i] : 0;
    __syncthreads();

    sdata[tid] *= sdata[tid];
	__syncthreads();
    // do reduction in shared mem
    for(unsigned int s=blockDim.x/2; s>0; s>>=1)
    {
        if (tid < s)
        {
            sdata[tid] += sdata[tid + s];
        }
        __syncthreads();
    }

    // write result for this block to global mem
	if (tid == 0)
		g_odata[blockIdx.x] = sdata[0];
	__syncthreads();
}

extern "C"
float GPU_accumulate_KE_wShrdMem(int nd, int np, float mass, int step, double *time_elapsed)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
	float* parvel, sum;
	dim3 dimBlock = dim3(BLOCK_SIZE, 1, 1);
	dim3 dimGrid;
	int smemSize = (BLOCK_SIZE <= 32) ? 2 * BLOCK_SIZE * sizeof(double) : BLOCK_SIZE * sizeof(double);
	dimGrid = dim3(numBlocks, 1, 1);
	float val[100];
	hipMemcpy(val,vel_gpu,100*sizeof(float),hipMemcpyDeviceToHost);


/*	if(step == 4)
	{
		t0 = cputime();
		for(i=0; i<iter; i++)
		{
			GPU_compute_KE_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(vel_gpu, parvel_gpu, numberOfThreads);
			cudaThreadSynchronize();

		}
		t1=cputime();
		time_sum1 = (t1-t0)*iCPS*1000*1000/iter;
		numberOfThreads = numBlocks;
		numberOfThreadsT = numberOfThreads;
		numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
		numBlocksT = numBlocks;
		cudaMalloc ((void**)(&parvelT_gpu), nd*np*sizeof(float));
		cudaMemcpy(parvelT_gpu, parvel_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
		for(i=0; i<iter; i++)
		{
			numBlocks = numBlocksT;
			numberOfThreads = numberOfThreadsT;
			cudaMemcpy(parvel_gpu, parvelT_gpu, nd * np *sizeof(float), cudaMemcpyDeviceToDevice);
			t0=cputime();
			while(numBlocks>1)
			{
				dimGrid = dim3(numBlocks, 1, 1);
				reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parvel_gpu, parvel_gpu, numberOfThreads);
				cudaThreadSynchronize();
				numberOfThreads = numBlocks;
				numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
			}
			t1=cputime();
			time_sum2 += (t1-t0)*iCPS*1000*1000;
		}
		cudaFree(parvelT_gpu);

		parvel = (float*) malloc(numberOfThreads * sizeof (float));
		cudaMemcpy(parvel, parvel_gpu, numberOfThreads*sizeof(float), cudaMemcpyDeviceToHost);

		for(i=0; i<iter; i++)
		{
			t0=cputime();
			sum = 0.0;
			for(int j=0; j<numberOfThreads; j++)
			{
				sum += parvel[j];
			}
			t1=cputime();
			time_sum3 += (t1-t0)*iCPS*1000*1000;
		}
		*time_elapsed = time_sum1 + time_sum2/iter + time_sum3/iter;
	}
	else
*/	{
		GPU_compute_KE_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(vel_gpu, parvel_gpu, numberOfThreads);
		hipDeviceSynchronize();

		numberOfThreads = numBlocks;
		numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

		while(numBlocks>1)
		{
			dimGrid = dim3(numBlocks, 1, 1);
			reduce_wShrdMem<float><<< dimGrid, dimBlock, smemSize >>>(parvel_gpu, parvel_gpu, numberOfThreads);
			hipDeviceSynchronize();
			numberOfThreads = numBlocks;
			numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;
		}

		parvel = (float*) malloc(numberOfThreads * sizeof (float));
		hipMemcpy(parvel, parvel_gpu, numberOfThreads*sizeof(float), hipMemcpyDeviceToHost);

		sum = 0.0;
		for(int i=0; i<numberOfThreads; i++)
			sum += parvel[i];
	}
	free(parvel);
	return 0.5 * mass * sum;
}

//END K4 - Compute and accumulate KE with shared memory


//START K5 - Update position
__global__ void GPU_updatePos(int numberOfThreads, float dt, float * pos_gpu, const float * vel_gpu, const float * acc_gpu)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;
	if (idx >= numberOfThreads)
		return ;
	pos_gpu[idx] += vel_gpu[idx] * dt + 0.5 * acc_gpu[idx] * dt * dt;
}

extern "C"
void GPU_updatePos(int nd, int np, float dt, int step, double *time_elapsedCPU, float *time_elapsedGPU)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step==4)
	{
		cudaEvent_t start, stop;
		cudaEventCreate(&start);
		cudaEventCreate(&stop);
		cudaMalloc ((void**)(&posT_gpu), nd*np*sizeof(float));
		for(i=0; i<iter; i++)
		{
			dummyCopy<<<dimGrid,dimBlock>>>(pos_gpu, posT_gpu); //(input, output)
			t0=cputime();
			//cudaEventRecord(start,0);
			GPU_updatePos<<<dimGrid,dimBlock>>>(numberOfThreads, dt, pos_gpu, vel_gpu, acc_gpu);
			cudaThreadSynchronize();
			//cudaEventRecord(stop,0);
			//cudaEventSynchronize(stop);
			t1=cputime();
			//cudaEventElapsedTime(&time_diff, start, stop);
			if(i<(iter-1))
				dummyCopy<<<dimGrid,dimBlock>>>(posT_gpu, pos_gpu);
			time_sumCPU += (t1-t0)*iCPS*1000*1000;
			//time_diff /= 1000;
			//time_sumGPU += time_diff;
		}
		*time_elapsedCPU=time_sumCPU/iter;
		//*time_elapsedGPU=time_sumGPU/iter;
		cudaFree(posT_gpu);
		cudaEventDestroy(start);
		cudaEventDestroy(stop);
	}
	else
*/	{
		GPU_updatePos<<<dimGrid,dimBlock>>>(numberOfThreads, dt, pos_gpu, vel_gpu, acc_gpu) ;
		hipDeviceSynchronize();
	}
}
//END K5 - Update position


//START K6 - Update velocity
__global__ void GPU_updateVel(int numberOfThreads, float dt, float rmass, float * vel_gpu, const float * force_gpu, const float * acc_gpu)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;
	if (idx >= numberOfThreads)
		return ;
	vel_gpu[idx] += 0.5 * dt * (force_gpu[idx] * rmass + acc_gpu[idx]);
}

extern "C"
void GPU_updateVel(int nd, int np, float dt, float rmass, int step, double *time_elapsedCPU, float *time_elapsedGPU)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step==4)
	{
		cudaEvent_t start, stop;
		cudaEventCreate(&start);
		cudaEventCreate(&stop);
		cudaMalloc ((void**)(&velT_gpu), nd*np*sizeof(float));
		for(i=0; i<iter; i++)
		{
			dummyCopy<<<dimGrid,dimBlock>>>(vel_gpu, velT_gpu); //(input, output)
			t0=cputime();
			//cudaEventRecord(start,0);
			GPU_updateVel<<<dimGrid,dimBlock>>>(numberOfThreads, dt, rmass, vel_gpu, force_gpu, acc_gpu) ;
			cudaThreadSynchronize();
			//cudaEventRecord(stop,0);
			//cudaEventSynchronize(stop);
			t1=cputime();
			//cudaEventElapsedTime(&time_diff, start, stop);
			if(i<(iter-1))
				dummyCopy<<<dimGrid,dimBlock>>>(velT_gpu, vel_gpu);
			time_sumCPU += (t1-t0)*iCPS*1000*1000;
			//time_diff /= 1000;
			//time_sumGPU += time_diff;
		}
		*time_elapsedCPU=time_sumCPU/iter;
		//*time_elapsedGPU=time_sumGPU/iter;
		cudaFree(velT_gpu);
		cudaEventDestroy(start);
		cudaEventDestroy(stop);
	}
	else
*/	{
		GPU_updateVel<<<dimGrid,dimBlock>>>(numberOfThreads, dt, rmass, vel_gpu, force_gpu, acc_gpu) ;
		hipDeviceSynchronize();
	}
}
//END K6 - Update velocity


//START K7 - Update acceleration
__global__ void GPU_updateAcc(int numberOfThreads, float rmass, float * acc_gpu, const float * force_gpu)
{
	int idx = blockIdx.x * blockDim.x + threadIdx.x ;
	if (idx >= numberOfThreads)
		return ;
	acc_gpu[idx] = force_gpu[idx] * rmass;
}

extern "C"
void GPU_updateAcc(int nd, int np, float rmass, int step, double *time_elapsedCPU, float *time_elapsedGPU)
{
	int BLOCK_SIZE = 128;
	int numberOfThreads = nd*np;
	int numBlocks = numberOfThreads / BLOCK_SIZE + (numberOfThreads % BLOCK_SIZE == 0 ? 0 : 1) ;

	dim3 dimGrid(numBlocks) ;
	dim3 dimBlock(BLOCK_SIZE) ;


/*	if(step==4)
	{
		cudaEvent_t start, stop;
		cudaEventCreate(&start);
		cudaEventCreate(&stop);
		for(i=0; i<iter; i++)
		{
			t0=cputime();
			//cudaEventRecord(start,0);
			GPU_updateAcc<<<dimGrid,dimBlock>>>(numberOfThreads, rmass, acc_gpu, force_gpu) ;
			cudaThreadSynchronize();
			//cudaEventRecord(stop,0);
			//cudaEventSynchronize(stop);
			t1=cputime();
			//cudaEventElapsedTime(&time_diff, start, stop);
			time_sumCPU += (t1-t0)*iCPS*1000*1000;
			//time_diff /= 1000;
			//time_sumGPU += time_diff;
		}
		*time_elapsedCPU=time_sumCPU/iter;
		//*time_elapsedGPU = time_sumGPU/iter;
		cudaEventDestroy(start);
		cudaEventDestroy(stop);
	}
	else
*/	{
		GPU_updateAcc<<<dimGrid,dimBlock>>>(numberOfThreads, rmass, acc_gpu, force_gpu) ;
		hipDeviceSynchronize();
	}
}
//END K7 - Update acceleration

	.text
	.file	"MD_kernel_perfsig.hip"
	.globl	allocMemOnGPU                   # -- Begin function allocMemOnGPU
	.type	allocMemOnGPU,@function
allocMemOnGPU:                          # @allocMemOnGPU
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	imull	%esi, %edi
	movslq	%edi, %rbx
	shlq	$2, %rbx
	movl	$parforce_gpu, %edi
	movq	%rbx, %rsi
	callq	hipMalloc
	movslq	%ebp, %rsi
	shlq	$2, %rsi
	movl	$parpot_gpu, %edi
	callq	hipMalloc
	movl	$parvel_gpu, %edi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$acc_gpu, %edi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$force_gpu, %edi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$pos_gpu, %edi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$vel_gpu, %edi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipMalloc                       # TAILCALL
.Lfunc_end0:
	.size	allocMemOnGPU, .Lfunc_end0-allocMemOnGPU
	.cfi_endproc
                                        # -- End function
	.globl	copyDataToGPU                   # -- Begin function copyDataToGPU
	.type	copyDataToGPU,@function
copyDataToGPU:                          # @copyDataToGPU
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %rsi
	movq	acc_gpu(%rip), %rdi
	imull	%r9d, %r8d
	movslq	%r8d, %r12
	shlq	$2, %r12
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	force_gpu(%rip), %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	vel_gpu(%rip), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	pos_gpu(%rip), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end1:
	.size	copyDataToGPU, .Lfunc_end1-copyDataToGPU
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__dummyCopyPfS_ # -- Begin function _Z24__device_stub__dummyCopyPfS_
	.type	_Z24__device_stub__dummyCopyPfS_,@function
_Z24__device_stub__dummyCopyPfS_:       # @_Z24__device_stub__dummyCopyPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9dummyCopyPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__dummyCopyPfS_, .Lfunc_end2-_Z24__device_stub__dummyCopyPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_ # -- Begin function _Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.type	_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_,@function
_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_: # @_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	56(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_, .Lfunc_end3-_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	GPU_compute_forceonparticle     # -- Begin function GPU_compute_forceonparticle
	.type	GPU_compute_forceonparticle,@function
GPU_compute_forceonparticle:            # @GPU_compute_forceonparticle
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	%esi, %ebx
	leal	127(%rbx), %edi
	testl	%esi, %esi
	cmovnsl	%esi, %edi
	sarl	$7, %edi
	movl	%esi, %eax
	andl	$127, %eax
	cmpl	$1, %eax
	sbbl	$-1, %edi
	movl	%edx, %ebp
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$128, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	pos_gpu(%rip), %rcx
	movq	parforce_gpu(%rip), %r8
	movq	parpot_gpu(%rip), %r9
	movl	%ebx, %edi
	movl	%ebx, %esi
	movl	%ebp, %edx
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_
.LBB4_2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end4:
	.size	GPU_compute_forceonparticle, .Lfunc_end4-GPU_compute_forceonparticle
	.cfi_endproc
                                        # -- End function
	.globl	_Z30GPU_accumulate_parpot_wShrdMemiiiPd # -- Begin function _Z30GPU_accumulate_parpot_wShrdMemiiiPd
	.type	_Z30GPU_accumulate_parpot_wShrdMemiiiPd,@function
_Z30GPU_accumulate_parpot_wShrdMemiiiPd: # @_Z30GPU_accumulate_parpot_wShrdMemiiiPd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebx
	leal	127(%rbx), %eax
	testl	%esi, %esi
	cmovnsl	%esi, %eax
	sarl	$7, %eax
	movl	%esi, %ecx
	andl	$127, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	cmpl	$2, %eax
	jl	.LBB5_1
# %bb.2:                                # %.lr.ph.preheader
	movabsq	$4294967296, %r15               # imm = 0x100000000
	leaq	128(%r15), %r14
.LBB5_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %ebp
	movl	%eax, %edi
	orq	%r15, %rdi
	movl	$512, %r8d                      # imm = 0x200
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_5
# %bb.4:                                #   in Loop: Header=BB5_3 Depth=1
	movq	parpot_gpu(%rip), %rdi
	movq	%rdi, %rsi
	movl	%ebx, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB5_5:                                #   in Loop: Header=BB5_3 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	$7, %eax
	movl	%ebp, %ecx
	andl	$127, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movl	%ebp, %ebx
	cmpl	$1, %eax
	ja	.LBB5_3
	jmp	.LBB5_6
.LBB5_1:
	movl	%ebx, %ebp
.LBB5_6:                                # %._crit_edge
	movslq	%ebp, %r15
	leaq	(,%r15,4), %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	parpot_gpu(%rip), %rsi
	movq	%rax, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%r15d, %r15d
	jle	.LBB5_7
# %bb.9:                                # %.lr.ph51.preheader
	movl	%ebp, %eax
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB5_10:                               # %.lr.ph51
                                        # =>This Inner Loop Header: Depth=1
	addss	(%rbx,%rcx,4), %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB5_10
	jmp	.LBB5_8
.LBB5_7:
	xorps	%xmm0, %xmm0
.LBB5_8:                                # %._crit_edge52
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%rbx, %rdi
	callq	free
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z30GPU_accumulate_parpot_wShrdMemiiiPd, .Lfunc_end5-_Z30GPU_accumulate_parpot_wShrdMemiiiPd
	.cfi_endproc
                                        # -- End function
	.section	.text._Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j,comdat
	.weak	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j # -- Begin function _Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
	.type	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j,@function
_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j: # @_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15reduce_wShrdMemIfEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j, .Lfunc_end6-_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.text
	.globl	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd # -- Begin function _Z32GPU_accumulate_parforce_wShrdMemiiiiPd
	.type	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd,@function
_Z32GPU_accumulate_parforce_wShrdMemiiiiPd: # @_Z32GPU_accumulate_parforce_wShrdMemiiiiPd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $edx killed $edx def $rdx
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
                                        # kill: def $esi killed $esi def $rsi
	leal	127(%rsi), %eax
	testl	%esi, %esi
	cmovnsl	%esi, %eax
	movabsq	$4294967424, %r15               # imm = 0x100000080
	sarl	$7, %eax
	movl	%esi, %ecx
	andl	$127, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	cmpl	$2, %eax
	movq	%rsi, 8(%rsp)                   # 8-byte Spill
	jl	.LBB7_1
# %bb.2:                                # %.lr.ph
	movslq	%esi, %rbx
	leal	(%rsi,%rsi), %ecx
	movslq	%ecx, %r14
	shlq	$2, %rbx
	shlq	$2, %r14
	movl	%esi, %r12d
.LBB7_3:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, %ebp
	movl	%eax, %eax
	leaq	(%r15,%rax), %r13
	addq	$-128, %r13
	movl	$512, %r8d                      # imm = 0x200
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_5
# %bb.4:                                #   in Loop: Header=BB7_3 Depth=1
	movq	parforce_gpu(%rip), %rdi
	movq	%rdi, %rsi
	movl	%r12d, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB7_5:                                #   in Loop: Header=BB7_3 Depth=1
	callq	hipDeviceSynchronize
	movl	$512, %r8d                      # imm = 0x200
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_7
# %bb.6:                                #   in Loop: Header=BB7_3 Depth=1
	movq	parforce_gpu(%rip), %rdi
	addq	%rbx, %rdi
	movq	%rdi, %rsi
	movl	%r12d, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB7_7:                                #   in Loop: Header=BB7_3 Depth=1
	callq	hipDeviceSynchronize
	movl	$512, %r8d                      # imm = 0x200
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_9
# %bb.8:                                #   in Loop: Header=BB7_3 Depth=1
	movq	parforce_gpu(%rip), %rdi
	addq	%r14, %rdi
	movq	%rdi, %rsi
	movl	%r12d, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB7_9:                                #   in Loop: Header=BB7_3 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	$7, %eax
	movl	%ebp, %ecx
	andl	$127, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movl	%ebp, %r12d
	cmpl	$1, %eax
	ja	.LBB7_3
	jmp	.LBB7_10
.LBB7_1:
	movl	%esi, %ebp
.LBB7_10:                               # %._crit_edge
	movl	%eax, %eax
	leaq	(%r15,%rax), %r12
	addq	$-128, %r12
	movl	$512, %r8d                      # imm = 0x200
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	16(%rsp), %rbx                  # 8-byte Reload
	jne	.LBB7_12
# %bb.11:
	movq	parforce_gpu(%rip), %rdi
	movslq	%ebx, %rsi
	shlq	$2, %rsi
	addq	force_gpu(%rip), %rsi
	movl	%ebp, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB7_12:
	callq	hipDeviceSynchronize
	movl	$512, %r8d                      # imm = 0x200
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	8(%rsp), %r14                   # 8-byte Reload
	jne	.LBB7_14
# %bb.13:
	movslq	%r14d, %rdi
	shlq	$2, %rdi
	addq	parforce_gpu(%rip), %rdi
	leal	(%rbx,%r14), %eax
	movslq	%eax, %rsi
	shlq	$2, %rsi
	addq	force_gpu(%rip), %rsi
	movl	%ebp, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB7_14:
	callq	hipDeviceSynchronize
	movl	$512, %r8d                      # imm = 0x200
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_16
# %bb.15:
	leal	(%r14,%r14), %eax
	movslq	%eax, %rdi
	shlq	$2, %rdi
	addq	parforce_gpu(%rip), %rdi
	leal	(%rbx,%r14,2), %eax
	movslq	%eax, %rsi
	shlq	$2, %rsi
	addq	force_gpu(%rip), %rsi
	movl	%ebp, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB7_16:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end7:
	.size	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd, .Lfunc_end7-_Z32GPU_accumulate_parforce_wShrdMemiiiiPd
	.cfi_endproc
                                        # -- End function
	.globl	GPU_seq_wShrdMem_accumulate_parpot_and_parforce # -- Begin function GPU_seq_wShrdMem_accumulate_parpot_and_parforce
	.type	GPU_seq_wShrdMem_accumulate_parpot_and_parforce,@function
GPU_seq_wShrdMem_accumulate_parpot_and_parforce: # @GPU_seq_wShrdMem_accumulate_parpot_and_parforce
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%esi, %ebx
	callq	_Z32GPU_accumulate_parforce_wShrdMemiiiiPd
	movl	%ebx, %esi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_Z30GPU_accumulate_parpot_wShrdMemiiiPd # TAILCALL
.Lfunc_end8:
	.size	GPU_seq_wShrdMem_accumulate_parpot_and_parforce, .Lfunc_end8-GPU_seq_wShrdMem_accumulate_parpot_and_parforce
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function GPU_accumulate_KE_wShrdMem
.LCPI9_0:
	.quad	0x3fe0000000000000              # double 0.5
	.text
	.globl	GPU_accumulate_KE_wShrdMem
	.type	GPU_accumulate_KE_wShrdMem,@function
GPU_accumulate_KE_wShrdMem:             # @GPU_accumulate_KE_wShrdMem
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$416, %rsp                      # imm = 0x1A0
	.cfi_def_cfa_offset 464
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	%edi, %r14d
	imull	%esi, %r14d
	leal	127(%r14), %ebx
	testl	%r14d, %r14d
	cmovnsl	%r14d, %ebx
	sarl	$7, %ebx
	movl	%r14d, %eax
	andl	$127, %eax
	cmpl	$1, %eax
	sbbl	$-1, %ebx
	movabsq	$4294967296, %r12               # imm = 0x100000000
	movq	%rbx, %r15
	btsq	$32, %r15
	movq	vel_gpu(%rip), %rsi
	leaq	16(%rsp), %rdi
	movl	$400, %edx                      # imm = 0x190
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	128(%r12), %rdx
	movl	$1024, %r8d                     # imm = 0x400
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_2
# %bb.1:
	movq	vel_gpu(%rip), %rdi
	movq	parvel_gpu(%rip), %rsi
	movl	%r14d, %edx
	callq	_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j
.LBB9_2:
	callq	hipDeviceSynchronize
	leal	127(%rbx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	sarl	$7, %eax
	movl	%ebx, %ecx
	andl	$127, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	cmpl	$2, %eax
	jl	.LBB9_3
# %bb.4:                                # %.lr.ph.preheader
	leaq	128(%r12), %r14
.LBB9_5:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %ebp
	movl	%eax, %edi
	orq	%r12, %rdi
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_7
# %bb.6:                                #   in Loop: Header=BB9_5 Depth=1
	movq	parvel_gpu(%rip), %rdi
	movq	%rdi, %rsi
	movl	%ebx, %edx
	callq	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
.LBB9_7:                                #   in Loop: Header=BB9_5 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	$7, %eax
	movl	%ebp, %ecx
	andl	$127, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %eax
	movl	%ebp, %ebx
	cmpl	$1, %eax
	ja	.LBB9_5
	jmp	.LBB9_8
.LBB9_3:
	movl	%ebx, %ebp
.LBB9_8:                                # %._crit_edge
	movslq	%ebp, %r15
	leaq	(,%r15,4), %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	parvel_gpu(%rip), %rsi
	movq	%rax, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%r15d, %r15d
	jle	.LBB9_9
# %bb.12:                               # %.lr.ph85.preheader
	movl	%ebp, %eax
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB9_13:                               # %.lr.ph85
                                        # =>This Inner Loop Header: Depth=1
	addss	(%rbx,%rcx,4), %xmm0
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB9_13
# %bb.10:                               # %._crit_edge86.loopexit
	cvtss2sd	%xmm0, %xmm0
	jmp	.LBB9_11
.LBB9_9:
	xorps	%xmm0, %xmm0
.LBB9_11:                               # %._crit_edge86
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	free
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	mulsd	.LCPI9_0(%rip), %xmm0
	mulsd	8(%rsp), %xmm0                  # 8-byte Folded Reload
	cvtsd2ss	%xmm0, %xmm0
	addq	$416, %rsp                      # imm = 0x1A0
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	GPU_accumulate_KE_wShrdMem, .Lfunc_end9-GPU_accumulate_KE_wShrdMem
	.cfi_endproc
                                        # -- End function
	.section	.text._Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j,comdat
	.weak	_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j # -- Begin function _Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.type	_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j,@function
_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j: # @_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j, .Lfunc_end10-_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.text
	.globl	_Z28__device_stub__GPU_updatePosifPfPKfS1_ # -- Begin function _Z28__device_stub__GPU_updatePosifPfPKfS1_
	.type	_Z28__device_stub__GPU_updatePosifPfPKfS1_,@function
_Z28__device_stub__GPU_updatePosifPfPKfS1_: # @_Z28__device_stub__GPU_updatePosifPfPKfS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	movq	%rsp, %rdi
	movss	%xmm0, (%rdi)
	leaq	40(%rsp), %r8
	movq	%rsi, (%r8)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r8, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13GPU_updatePosifPfPKfS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z28__device_stub__GPU_updatePosifPfPKfS1_, .Lfunc_end11-_Z28__device_stub__GPU_updatePosifPfPKfS1_
	.cfi_endproc
                                        # -- End function
	.globl	GPU_updatePos                   # -- Begin function GPU_updatePos
	.type	GPU_updatePos,@function
GPU_updatePos:                          # @GPU_updatePos
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movl	%edi, %ebx
	imull	%esi, %ebx
	leal	127(%rbx), %edi
	testl	%ebx, %ebx
	cmovnsl	%ebx, %edi
	sarl	$7, %edi
	movl	%ebx, %eax
	andl	$127, %eax
	cmpl	$1, %eax
	sbbl	$-1, %edi
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$128, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_2
# %bb.1:
	movq	pos_gpu(%rip), %rsi
	movq	vel_gpu(%rip), %rdx
	movq	acc_gpu(%rip), %rcx
	movl	%ebx, %edi
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z28__device_stub__GPU_updatePosifPfPKfS1_
.LBB12_2:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end12:
	.size	GPU_updatePos, .Lfunc_end12-GPU_updatePos
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__GPU_updateVeliffPfPKfS1_ # -- Begin function _Z28__device_stub__GPU_updateVeliffPfPKfS1_
	.type	_Z28__device_stub__GPU_updateVeliffPfPKfS1_,@function
_Z28__device_stub__GPU_updateVeliffPfPKfS1_: # @_Z28__device_stub__GPU_updateVeliffPfPKfS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movss	%xmm0, (%rdi)
	leaq	12(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	56(%rsp), %r9
	movq	%rsi, (%r9)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r8, 16(%rbx)
	movq	%r9, 24(%rbx)
	movq	%rsi, 32(%rbx)
	movq	%rdx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13GPU_updateVeliffPfPKfS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z28__device_stub__GPU_updateVeliffPfPKfS1_, .Lfunc_end13-_Z28__device_stub__GPU_updateVeliffPfPKfS1_
	.cfi_endproc
                                        # -- End function
	.globl	GPU_updateVel                   # -- Begin function GPU_updateVel
	.type	GPU_updateVel,@function
GPU_updateVel:                          # @GPU_updateVel
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movl	%edi, %ebx
	imull	%esi, %ebx
	leal	127(%rbx), %edi
	testl	%ebx, %ebx
	cmovnsl	%ebx, %edi
	sarl	$7, %edi
	movl	%ebx, %eax
	andl	$127, %eax
	cmpl	$1, %eax
	sbbl	$-1, %edi
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$128, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_2
# %bb.1:
	movq	vel_gpu(%rip), %rsi
	movq	force_gpu(%rip), %rdx
	movq	acc_gpu(%rip), %rcx
	movl	%ebx, %edi
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	callq	_Z28__device_stub__GPU_updateVeliffPfPKfS1_
.LBB14_2:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end14:
	.size	GPU_updateVel, .Lfunc_end14-GPU_updateVel
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__GPU_updateAccifPfPKf # -- Begin function _Z28__device_stub__GPU_updateAccifPfPKf
	.type	_Z28__device_stub__GPU_updateAccifPfPKf,@function
_Z28__device_stub__GPU_updateAccifPfPKf: # @_Z28__device_stub__GPU_updateAccifPfPKf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13GPU_updateAccifPfPKf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z28__device_stub__GPU_updateAccifPfPKf, .Lfunc_end15-_Z28__device_stub__GPU_updateAccifPfPKf
	.cfi_endproc
                                        # -- End function
	.globl	GPU_updateAcc                   # -- Begin function GPU_updateAcc
	.type	GPU_updateAcc,@function
GPU_updateAcc:                          # @GPU_updateAcc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movl	%edi, %ebx
	imull	%esi, %ebx
	leal	127(%rbx), %edi
	testl	%ebx, %ebx
	cmovnsl	%ebx, %edi
	sarl	$7, %edi
	movl	%ebx, %eax
	andl	$127, %eax
	cmpl	$1, %eax
	sbbl	$-1, %edi
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$128, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB16_2
# %bb.1:
	movq	acc_gpu(%rip), %rsi
	movq	force_gpu(%rip), %rdx
	movl	%ebx, %edi
	movss	12(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z28__device_stub__GPU_updateAccifPfPKf
.LBB16_2:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end16:
	.size	GPU_updateAcc, .Lfunc_end16-GPU_updateAcc
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB17_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB17_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9dummyCopyPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13GPU_updatePosifPfPKfS1_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13GPU_updateVeliffPfPKfS1_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13GPU_updateAccifPfPKf, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15reduce_wShrdMemIfEvPT_S1_j, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end17:
	.size	__hip_module_ctor, .Lfunc_end17-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB18_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB18_2:
	retq
.Lfunc_end18:
	.size	__hip_module_dtor, .Lfunc_end18-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	parforce_gpu,@object            # @parforce_gpu
	.bss
	.globl	parforce_gpu
	.p2align	3, 0x0
parforce_gpu:
	.quad	0
	.size	parforce_gpu, 8

	.type	parpot_gpu,@object              # @parpot_gpu
	.globl	parpot_gpu
	.p2align	3, 0x0
parpot_gpu:
	.quad	0
	.size	parpot_gpu, 8

	.type	parvel_gpu,@object              # @parvel_gpu
	.globl	parvel_gpu
	.p2align	3, 0x0
parvel_gpu:
	.quad	0
	.size	parvel_gpu, 8

	.type	acc_gpu,@object                 # @acc_gpu
	.globl	acc_gpu
	.p2align	3, 0x0
acc_gpu:
	.quad	0
	.size	acc_gpu, 8

	.type	force_gpu,@object               # @force_gpu
	.globl	force_gpu
	.p2align	3, 0x0
force_gpu:
	.quad	0
	.size	force_gpu, 8

	.type	pos_gpu,@object                 # @pos_gpu
	.globl	pos_gpu
	.p2align	3, 0x0
pos_gpu:
	.quad	0
	.size	pos_gpu, 8

	.type	vel_gpu,@object                 # @vel_gpu
	.globl	vel_gpu
	.p2align	3, 0x0
vel_gpu:
	.quad	0
	.size	vel_gpu, 8

	.type	_Z9dummyCopyPfS_,@object        # @_Z9dummyCopyPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z9dummyCopyPfS_
	.p2align	3, 0x0
_Z9dummyCopyPfS_:
	.quad	_Z24__device_stub__dummyCopyPfS_
	.size	_Z9dummyCopyPfS_, 8

	.type	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_,@object # @_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.globl	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.p2align	3, 0x0
_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_:
	.quad	_Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.size	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_, 8

	.type	_Z15reduce_wShrdMemIfEvPT_S1_j,@object # @_Z15reduce_wShrdMemIfEvPT_S1_j
	.section	.rodata._Z15reduce_wShrdMemIfEvPT_S1_j,"aG",@progbits,_Z15reduce_wShrdMemIfEvPT_S1_j,comdat
	.weak	_Z15reduce_wShrdMemIfEvPT_S1_j
	.p2align	3, 0x0
_Z15reduce_wShrdMemIfEvPT_S1_j:
	.quad	_Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
	.size	_Z15reduce_wShrdMemIfEvPT_S1_j, 8

	.type	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,@object # @_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.section	.rodata._Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,"aG",@progbits,_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,comdat
	.weak	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.p2align	3, 0x0
_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j:
	.quad	_Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.size	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j, 8

	.type	_Z13GPU_updatePosifPfPKfS1_,@object # @_Z13GPU_updatePosifPfPKfS1_
	.section	.rodata,"a",@progbits
	.globl	_Z13GPU_updatePosifPfPKfS1_
	.p2align	3, 0x0
_Z13GPU_updatePosifPfPKfS1_:
	.quad	_Z28__device_stub__GPU_updatePosifPfPKfS1_
	.size	_Z13GPU_updatePosifPfPKfS1_, 8

	.type	_Z13GPU_updateVeliffPfPKfS1_,@object # @_Z13GPU_updateVeliffPfPKfS1_
	.globl	_Z13GPU_updateVeliffPfPKfS1_
	.p2align	3, 0x0
_Z13GPU_updateVeliffPfPKfS1_:
	.quad	_Z28__device_stub__GPU_updateVeliffPfPKfS1_
	.size	_Z13GPU_updateVeliffPfPKfS1_, 8

	.type	_Z13GPU_updateAccifPfPKf,@object # @_Z13GPU_updateAccifPfPKf
	.globl	_Z13GPU_updateAccifPfPKf
	.p2align	3, 0x0
_Z13GPU_updateAccifPfPKf:
	.quad	_Z28__device_stub__GPU_updateAccifPfPKf
	.size	_Z13GPU_updateAccifPfPKf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9dummyCopyPfS_"
	.size	.L__unnamed_1, 17

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_"
	.size	.L__unnamed_2, 49

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13GPU_updatePosifPfPKfS1_"
	.size	.L__unnamed_3, 28

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z13GPU_updateVeliffPfPKfS1_"
	.size	.L__unnamed_4, 29

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z13GPU_updateAccifPfPKf"
	.size	.L__unnamed_5, 25

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z15reduce_wShrdMemIfEvPT_S1_j"
	.size	.L__unnamed_6, 31

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j"
	.size	.L__unnamed_7, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__dummyCopyPfS_
	.addrsig_sym _Z49__device_stub__GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.addrsig_sym _Z30__device_stub__reduce_wShrdMemIfEvPT_S1_j
	.addrsig_sym _Z38__device_stub__GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.addrsig_sym _Z28__device_stub__GPU_updatePosifPfPKfS1_
	.addrsig_sym _Z28__device_stub__GPU_updateVeliffPfPKfS1_
	.addrsig_sym _Z28__device_stub__GPU_updateAccifPfPKf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym parforce_gpu
	.addrsig_sym parpot_gpu
	.addrsig_sym parvel_gpu
	.addrsig_sym acc_gpu
	.addrsig_sym force_gpu
	.addrsig_sym pos_gpu
	.addrsig_sym vel_gpu
	.addrsig_sym _Z9dummyCopyPfS_
	.addrsig_sym _Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.addrsig_sym _Z15reduce_wShrdMemIfEvPT_S1_j
	.addrsig_sym _Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.addrsig_sym _Z13GPU_updatePosifPfPKfS1_
	.addrsig_sym _Z13GPU_updateVeliffPfPKfS1_
	.addrsig_sym _Z13GPU_updateAccifPfPKf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9dummyCopyPfS_        ; -- Begin function _Z9dummyCopyPfS_
	.globl	_Z9dummyCopyPfS_
	.p2align	8
	.type	_Z9dummyCopyPfS_,@function
_Z9dummyCopyPfS_:                       ; @_Z9dummyCopyPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9dummyCopyPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9dummyCopyPfS_, .Lfunc_end0-_Z9dummyCopyPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 128
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_ ; -- Begin function _Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.globl	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
	.p2align	8
	.type	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_,@function
_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_: ; @_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s5, v1
	s_cbranch_execz .LBB1_24
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[12:13], s[0:1], 0x20
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_ne_u32_e32 vcc_lo, s6, v1
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_ashr_i32 s5, s4, 31
	s_and_saveexec_b32 s14, vcc_lo
	s_cbranch_execz .LBB1_23
; %bb.2:
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	s_lshl_b64 s[0:1], s[4:5], 2
	s_ashr_i32 s3, s6, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	s_mov_b32 s2, s6
	s_clause 0x1
	global_load_b32 v6, v[2:3], off
	global_load_b32 v7, v[4:5], off
	v_add_co_u32 v2, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
	s_lshl_b64 s[2:3], s[2:3], 2
                                        ; implicit-def: $vgpr29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s8, s2
	global_load_b32 v2, v[2:3], off
	s_addc_u32 s3, s9, s3
	s_add_u32 s8, s2, s0
	s_addc_u32 s9, s3, s1
	s_clause 0x1
	s_load_b32 s6, s[8:9], 0x0
	s_load_b32 s2, s[2:3], 0x0
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_dual_sub_f32 v25, s2, v6 :: v_dual_sub_f32 v26, s6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v26, v26
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v28, s0, v2 :: v_dual_fmac_f32 v3, v25, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v28, v28
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
	v_mul_f32_e32 v2, 0x4f800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v5, 1, v3
	v_add_nc_u32_e32 v4, -1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v3, v2
	v_fma_f32 v6, -v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v6
	v_cndmask_b32_e64 v3, v3, v4, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v7
                                        ; implicit-def: $vgpr6_vgpr7
	v_cndmask_b32_e64 v3, v3, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x37800000, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
                                        ; implicit-def: $vgpr4_vgpr5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v27, v3, v2, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, s7, v27
	v_cndmask_b32_e32 v24, s7, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[2:3], v24
	v_add_f64 v[2:3], v[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s1, 0x41d00000, |v[2:3]|
	v_trig_preop_f64 v[20:21], |v[2:3]|, 0
	v_trig_preop_f64 v[18:19], |v[2:3]|, 1
	v_ldexp_f64 v[22:23], |v[2:3]|, 0xffffff80
	v_trig_preop_f64 v[16:17], |v[2:3]|, 2
	v_and_b32_e32 v32, 0x7fffffff, v3
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_mov_b32_e32 v39, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v5, v32, v23 :: v_dual_cndmask_b32 v4, v2, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[6:7], v[20:21], v[4:5]
	v_mul_f64 v[8:9], v[18:19], v[4:5]
	v_mul_f64 v[35:36], v[16:17], v[4:5]
	v_fma_f64 v[10:11], v[20:21], v[4:5], -v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[37:38], v[18:19], v[4:5], -v[8:9]
	v_fma_f64 v[4:5], v[16:17], v[4:5], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[8:9], v[10:11]
	v_add_f64 v[14:15], v[12:13], -v[8:9]
	v_add_f64 v[33:34], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[12:13], -v[14:15]
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_ldexp_f64 v[14:15], v[33:34], -2
	v_add_f64 v[6:7], v[33:34], -v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[8:9], v[8:9], -v[29:30]
	v_add_f64 v[29:30], v[35:36], v[37:38]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	v_add_f64 v[8:9], v[10:11], v[8:9]
	v_fract_f64_e32 v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[29:30], v[8:9]
	v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[10:11], v[10:11], 2
	v_add_f64 v[14:15], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[14:15], v[10:11]
	v_add_f64 v[6:7], v[14:15], -v[6:7]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[33:34]
	v_add_f64 v[33:34], v[29:30], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	v_cndmask_b32_e64 v40, 0, 0x40100000, vcc_lo
	v_add_f64 v[44:45], v[29:30], -v[33:34]
	v_add_f64 v[33:34], v[37:38], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], v[39:40]
	v_add_f64 v[40:41], v[12:13], -v[29:30]
	v_add_f64 v[37:38], v[35:36], -v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[14:15], v[10:11]
	v_add_f64 v[46:47], v[12:13], -v[40:41]
	v_add_f64 v[8:9], v[8:9], -v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[33:34], v[37:38]
	v_cvt_i32_f64_e32 v42, v[42:43]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[29:30], -v[46:47]
	v_cvt_f64_i32_e32 v[40:41], v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[29:30]
	v_add_f64 v[10:11], v[10:11], -v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[33:34], v[8:9]
	v_add_f64 v[30:31], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[8:9], v[30:31], -v[10:11]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_add_f64 v[6:7], v[14:15], -v[8:9]
	v_cndmask_b32_e64 v40, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v29, s0, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[30:31], -v[39:40]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[6:7], v[4:5]
	v_mul_f64 v[10:11], v[8:9], s[6:7]
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[8:9], s[6:7], -v[10:11]
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[8:9], s[8:9], v[12:13]
	v_fma_f64 v[6:7], v[4:5], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[10:11], v[6:7]
	v_add_f64 v[8:9], v[4:5], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[8:9]
.LBB1_4:                                ; %Flow114
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_6
; %bb.5:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[4:5], |v[2:3]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[8:9], v[4:5]
	v_fma_f64 v[4:5], v[8:9], s[2:3], |v[2:3]|
	v_mul_f64 v[6:7], v[8:9], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v29, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[8:9], s[6:7], v[4:5]
	v_add_f64 v[10:11], v[4:5], v[6:7]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_fma_f64 v[6:7], v[8:9], s[6:7], v[6:7]
	v_add_f64 v[4:5], v[10:11], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_fma_f64 v[6:7], v[8:9], s[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[12:13], v[6:7]
	v_add_f64 v[10:11], v[4:5], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
.LBB1_6:                                ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr10_vgpr11
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_mov_b32_e32 v43, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v9, v32, v23 :: v_dual_cndmask_b32 v8, v2, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[10:11], v[20:21], v[8:9]
	v_mul_f64 v[12:13], v[18:19], v[8:9]
	v_mul_f64 v[39:40], v[16:17], v[8:9]
	v_fma_f64 v[14:15], v[20:21], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[41:42], v[18:19], v[8:9], -v[12:13]
	v_fma_f64 v[8:9], v[16:17], v[8:9], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[30:31], v[12:13], v[14:15]
	v_add_f64 v[33:34], v[30:31], -v[12:13]
	v_add_f64 v[37:38], v[10:11], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[30:31], -v[33:34]
	v_add_f64 v[14:15], v[14:15], -v[33:34]
	v_ldexp_f64 v[33:34], v[37:38], -2
	v_add_f64 v[10:11], v[37:38], -v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], -v[35:36]
	v_add_f64 v[35:36], v[39:40], v[41:42]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[33:34]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[30:31], -v[10:11]
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_fract_f64_e32 v[14:15], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[35:36], v[12:13]
	v_dual_cndmask_b32 v15, 0, v15 :: v_dual_cndmask_b32 v14, 0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[14:15], v[14:15], 2
	v_add_f64 v[33:34], v[10:11], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[37:38], v[33:34], v[14:15]
	v_add_f64 v[10:11], v[33:34], -v[10:11]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[37:38]
	v_add_f64 v[37:38], v[35:36], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[30:31], -v[10:11]
	v_cndmask_b32_e64 v44, 0, 0x40100000, vcc_lo
	v_add_f64 v[48:49], v[35:36], -v[37:38]
	v_add_f64 v[37:38], v[41:42], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[14:15], v[43:44]
	v_add_f64 v[44:45], v[30:31], -v[35:36]
	v_add_f64 v[41:42], v[39:40], -v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[46:47], v[33:34], v[14:15]
	v_add_f64 v[50:51], v[30:31], -v[44:45]
	v_add_f64 v[12:13], v[12:13], -v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[37:38], v[37:38], v[41:42]
	v_cvt_i32_f64_e32 v46, v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[35:36], -v[50:51]
	v_cvt_f64_i32_e32 v[44:45], v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[35:36]
	v_add_f64 v[14:15], v[14:15], -v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[37:38], v[12:13]
	v_add_f64 v[35:36], v[33:34], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[12:13]
	v_add_f64 v[12:13], v[35:36], -v[14:15]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[10:11], v[8:9]
	v_add_f64 v[10:11], v[33:34], -v[12:13]
	v_cndmask_b32_e64 v44, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v30, s0, 0, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_f64 v[10:11], v[35:36], -v[43:44]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[10:11], v[8:9]
	v_mul_f64 v[14:15], v[12:13], s[6:7]
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[33:34], v[12:13], s[6:7], -v[14:15]
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[12:13], s[8:9], v[33:34]
	v_fma_f64 v[10:11], v[8:9], s[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[14:15], v[10:11]
	v_add_f64 v[12:13], v[8:9], -v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], -v[12:13]
.LBB1_8:                                ; %Flow113
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_10
; %bb.9:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[8:9], |v[2:3]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[12:13], v[8:9]
	v_fma_f64 v[8:9], v[12:13], s[2:3], |v[2:3]|
	v_mul_f64 v[10:11], v[12:13], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[12:13], s[6:7], v[8:9]
	v_add_f64 v[14:15], v[8:9], v[10:11]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], -v[14:15]
	v_add_f64 v[14:15], v[14:15], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_fma_f64 v[10:11], v[12:13], s[6:7], v[10:11]
	v_add_f64 v[8:9], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	v_fma_f64 v[10:11], v[12:13], s[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[30:31], v[10:11]
	v_add_f64 v[14:15], v[8:9], -v[30:31]
	v_cvt_i32_f64_e32 v30, v[12:13]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
.LBB1_10:                               ; %_ZL3sind.exit72
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB1_12
; %bb.11:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_mov_b32_e32 v41, 0
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v13, v32, v23 :: v_dual_cndmask_b32 v12, v2, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[20:21], v[12:13]
	v_mul_f64 v[22:23], v[18:19], v[12:13]
	v_mul_f64 v[39:40], v[16:17], v[12:13]
	v_fma_f64 v[20:21], v[20:21], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[18:19], v[12:13], -v[22:23]
	v_fma_f64 v[12:13], v[16:17], v[12:13], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[31:32], v[22:23], v[20:21]
	v_add_f64 v[33:34], v[31:32], -v[22:23]
	v_add_f64 v[37:38], v[14:15], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[31:32], -v[33:34]
	v_add_f64 v[20:21], v[20:21], -v[33:34]
	v_ldexp_f64 v[33:34], v[37:38], -2
	v_add_f64 v[14:15], v[37:38], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[35:36]
	v_add_f64 v[35:36], v[39:40], v[18:19]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[33:34]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[31:32], -v[14:15]
	v_add_f64 v[20:21], v[20:21], v[22:23]
	v_fract_f64_e32 v[22:23], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[35:36], v[20:21]
	v_dual_cndmask_b32 v23, 0, v23 :: v_dual_cndmask_b32 v22, 0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[22:23], v[22:23], 2
	v_add_f64 v[33:34], v[14:15], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[37:38], v[33:34], v[22:23]
	v_add_f64 v[14:15], v[33:34], -v[14:15]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[37:38]
	v_add_f64 v[37:38], v[35:36], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[31:32], -v[14:15]
	v_cndmask_b32_e64 v42, 0, 0x40100000, vcc_lo
	v_add_f64 v[46:47], v[35:36], -v[37:38]
	v_add_f64 v[18:19], v[18:19], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], v[41:42]
	v_add_f64 v[42:43], v[31:32], -v[35:36]
	v_add_f64 v[37:38], v[39:40], -v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[44:45], v[33:34], v[22:23]
	v_add_f64 v[48:49], v[31:32], -v[42:43]
	v_add_f64 v[20:21], v[20:21], -v[42:43]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[37:38]
	v_cvt_i32_f64_e32 v44, v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[35:36], -v[48:49]
	v_cvt_f64_i32_e32 v[42:43], v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[35:36]
	v_add_f64 v[22:23], v[22:23], -v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[18:19], v[20:21]
	v_add_f64 v[18:19], v[33:34], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_add_f64 v[16:17], v[18:19], -v[22:23]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_add_f64 v[14:15], v[33:34], -v[16:17]
	v_cndmask_b32_e64 v42, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v31, s0, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_add_f64 v[14:15], v[18:19], -v[41:42]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[14:15], v[12:13]
	v_mul_f64 v[18:19], v[16:17], s[2:3]
	v_add_f64 v[14:15], v[16:17], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[16:17], s[2:3], -v[18:19]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], s[6:7], v[20:21]
	v_fma_f64 v[14:15], v[12:13], s[2:3], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[18:19], v[14:15]
	v_add_f64 v[16:17], v[12:13], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], -v[16:17]
.LBB1_12:                               ; %Flow112
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_14
; %bb.13:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[12:13], |v[2:3]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[16:17], v[12:13]
	v_fma_f64 v[12:13], v[16:17], s[2:3], |v[2:3]|
	v_mul_f64 v[14:15], v[16:17], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v31, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[16:17], s[6:7], v[12:13]
	v_add_f64 v[18:19], v[12:13], v[14:15]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_fma_f64 v[14:15], v[16:17], s[6:7], v[14:15]
	v_add_f64 v[12:13], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_fma_f64 v[14:15], v[16:17], s[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[20:21], v[14:15]
	v_add_f64 v[18:19], v[12:13], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], -v[18:19]
.LBB1_14:                               ; %_ZL3sind.exit77
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v16, 0x7fffffff, v24
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v24|
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v21, 23, v16
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_16
; %bb.15:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v19, 0
	v_and_or_b32 v20, v16, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0xfe5163ab, v20, 0
	v_mad_u64_u32 v[22:23], null, 0x3c439041, v20, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v18, v23 :: v_dual_add_nc_u32 v23, 0xffffff88, v21
	v_mad_u64_u32 v[32:33], null, 0xdb629599, v20, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v23
	v_cndmask_b32_e64 v36, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v18, v33 :: v_dual_cndmask_b32 v17, v32, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v23, v36, v23
	v_mad_u64_u32 v[33:34], null, 0xf534ddc0, v20, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v23
	v_mov_b32_e32 v18, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v37, 0, 0xffffffe0, s0
	v_cndmask_b32_e32 v22, v33, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[34:35], null, 0xfc2757d1, v20, v[18:19]
	v_add_nc_u32_e32 v23, v37, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v22, v17, s0
	v_cmp_lt_u32_e64 s1, 31, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v35
	v_mad_u64_u32 v[35:36], null, 0x4e441529, v20, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v36
	v_mad_u64_u32 v[36:37], null, 0xa2f9836e, v20, v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v19, v35, v33, vcc_lo
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v20, v36, v34 :: v_dual_cndmask_b32 v35, v37, v35
	v_cndmask_b32_e32 v34, v34, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, v18, v23
	v_cndmask_b32_e64 v23, v20, v19, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v35, v20, s0
	v_cndmask_b32_e64 v19, v19, v34, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v33, 32, v18
	v_cndmask_b32_e64 v34, v34, v22, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v20, v20, v23, s1
	v_cndmask_b32_e64 v23, v23, v19, s1
	v_cndmask_b32_e64 v19, v19, v34, s1
	v_cndmask_b32_e64 v17, v34, v17, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v35, v20, v23, v33
	v_alignbit_b32 v32, v23, v19, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v33, v19, v17, v33
	v_cndmask_b32_e32 v18, v35, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v20, v32, v23, vcc_lo
	v_cndmask_b32_e32 v19, v33, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v22, v18, 29, 1
	v_alignbit_b32 v23, v18, v20, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v20, v20, v19, 30
	v_alignbit_b32 v17, v19, v17, 30
	v_sub_nc_u32_e32 v32, 0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v23, v23, v32
	v_xor_b32_e32 v19, v20, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v17, v17, v32
	v_clz_i32_u32_e32 v33, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v33, 32, v33
	v_sub_nc_u32_e32 v20, 31, v33
	v_lshlrev_b32_e32 v35, 23, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v23, v19, v20
	v_alignbit_b32 v17, v19, v17, v20
	v_lshrrev_b32_e32 v20, 29, v18
	v_lshrrev_b32_e32 v18, 30, v18
	v_alignbit_b32 v19, v23, v17, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v20, 31, v20
	v_lshrrev_b32_e32 v23, 9, v23
	v_add_nc_u32_e32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_clz_i32_u32_e32 v32, v19
	v_or_b32_e32 v34, 0.5, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v32, 32, v32
	v_sub_nc_u32_e32 v34, v34, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v36, 31, v32
	v_alignbit_b32 v17, v19, v17, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v19, v23, v34
	v_add_lshl_u32 v23, v32, v33, 23
	v_lshrrev_b32_e32 v17, 9, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v32, 0x3fc90fda, v19
	v_sub_nc_u32_e32 v17, v17, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, 0x3fc90fda, v19, -v32
	v_add_nc_u32_e32 v17, 0x33000000, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v19, v19, 0x33a22168, v23
	v_or_b32_e32 v17, v17, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, 0x3fc90fda, v17
	v_add_f32_e32 v17, v32, v19
.LBB1_16:                               ; %Flow111
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v22, 0x3f22f983, |v24|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.17:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v18, v22
	v_fma_f32 v17, 0xbfc90fda, v18, |v24|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v17, v18, 0xb3a22168, v17
	v_fmamk_f32 v17, v18, 0xa7c234c4, v17
	v_cvt_i32_f32_e32 v18, v18
; %bb.18:                               ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_20
; %bb.19:
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v38, v16, s0, 0x800000
	v_mad_u64_u32 v[19:20], null, 0xfe5163ab, v38, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v22, v20
	v_mad_u64_u32 v[32:33], null, 0x3c439041, v38, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v22, v33
	v_mad_u64_u32 v[33:34], null, 0xdb629599, v38, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v22, v34
	v_mad_u64_u32 v[34:35], null, 0xf534ddc0, v38, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v22, v35 :: v_dual_add_nc_u32 v35, 0xffffff88, v21
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v38, v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v35
	v_cndmask_b32_e64 v36, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v22, v21
	v_cndmask_b32_e32 v19, v33, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v21, v36, v35
	v_mad_u64_u32 v[35:36], null, 0x4e441529, v38, v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v21
	v_mov_b32_e32 v22, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v37, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v21, v37, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[36:37], null, 0xa2f9836e, v38, v[22:23]
	v_cndmask_b32_e32 v23, v35, v34, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v35, v37, v35, vcc_lo
	v_cndmask_b32_e64 v22, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v36, v36, v20, vcc_lo
	v_cndmask_b32_e32 v20, v20, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v21, v22, v21
	v_cndmask_b32_e32 v22, v34, v32, vcc_lo
	v_cndmask_b32_e64 v32, v36, v23, s0
	v_cndmask_b32_e64 v34, v35, v36, s0
	v_cndmask_b32_e64 v23, v23, v20, s0
	v_sub_nc_u32_e32 v35, 32, v21
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v34, v32, s1
	v_cndmask_b32_e64 v32, v32, v23, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v36, v34, v32, v35
	v_cndmask_b32_e32 v21, v36, v34, vcc_lo
	v_cndmask_b32_e64 v20, v20, v22, s0
	v_cndmask_b32_e64 v19, v22, v19, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, v23, v20, s1
	v_cndmask_b32_e64 v19, v20, v19, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v33, v32, v23, v35
	v_alignbit_b32 v34, v23, v19, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v22, v33, v32 :: v_dual_cndmask_b32 v23, v34, v23
	v_bfe_u32 v32, v21, 29, 1
	v_alignbit_b32 v20, v21, v22, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v22, v23, 30
	v_sub_nc_u32_e32 v33, 0, v32
	v_alignbit_b32 v19, v23, v19, 30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v20, v20, v33
	v_xor_b32_e32 v22, v22, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v19, v19, v33
	v_clz_i32_u32_e32 v34, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v34, 32, v34
	v_sub_nc_u32_e32 v23, 31, v34
	v_lshlrev_b32_e32 v36, 23, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v20, v22, v23
	v_alignbit_b32 v19, v22, v19, v23
	v_lshrrev_b32_e32 v23, 29, v21
	v_lshrrev_b32_e32 v21, 30, v21
	v_alignbit_b32 v22, v20, v19, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v23, 31, v23
	v_lshrrev_b32_e32 v20, 9, v20
	v_clz_i32_u32_e32 v33, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v35, 0.5, v23
	v_min_u32_e32 v33, 32, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v35, v35, v36
	v_sub_nc_u32_e32 v37, 31, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v20, v20, v35
	v_alignbit_b32 v19, v22, v19, v37
	v_add_lshl_u32 v22, v33, v34, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v33, 0x3fc90fda, v20
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, v19, v22
	v_fma_f32 v22, 0x3fc90fda, v20, -v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, 0x33000000, v19
	v_fmamk_f32 v20, v20, 0x33a22168, v22
                                        ; implicit-def: $vgpr22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v19, v19, v23
	v_fmac_f32_e32 v20, 0x3fc90fda, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v19, v33, v20 :: v_dual_add_nc_u32 v20, v32, v21
.LBB1_20:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s2
; %bb.21:
	v_rndne_f32_e32 v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, 0xbfc90fda, v20, |v24|
	v_fmamk_f32 v19, v20, 0xb3a22168, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v19, v20, 0xa7c234c4, v19
	v_cvt_i32_f32_e32 v20, v20
; %bb.22:                               ; %_ZL3sinf.exit85
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[21:22], v[12:13], v[12:13]
	v_mul_f64 v[32:33], v[8:9], v[8:9]
	v_mul_f64 v[34:35], v[4:5], v[4:5]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s2, 0xf9a43bb8
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s3, 0x3de5e0b2
	s_mov_b32 s6, 0x9037ab78
	s_mov_b32 s7, 0x3e21eeb6
	v_mul_f64 v[60:61], v[14:15], 0.5
	v_mul_f64 v[66:67], v[10:11], 0.5
	v_mul_f64 v[68:69], v[6:7], 0.5
	v_fma_f64 v[36:37], v[21:22], s[2:3], s[0:1]
	v_fma_f64 v[38:39], v[32:33], s[2:3], s[0:1]
	v_fma_f64 v[40:41], v[34:35], s[2:3], s[0:1]
	s_mov_b32 s0, 0x46cc5e42
	s_mov_b32 s2, 0x796cde01
	s_mov_b32 s1, 0xbda907db
	s_mov_b32 s3, 0x3ec71de3
	v_fma_f64 v[42:43], v[21:22], s[0:1], s[6:7]
	v_mul_f64 v[44:45], v[21:22], 0.5
	v_mul_f64 v[46:47], v[32:33], 0.5
	v_fma_f64 v[48:49], v[32:33], s[0:1], s[6:7]
	v_mul_f64 v[50:51], v[34:35], 0.5
	v_fma_f64 v[52:53], v[34:35], s[0:1], s[6:7]
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s1, 0xbe927e4f
	s_mov_b32 s6, 0x19f4ec90
	s_mov_b32 s7, 0x3efa01a0
	v_mul_f64 v[62:63], v[12:13], -v[21:22]
	v_mul_f64 v[70:71], v[8:9], -v[32:33]
	v_mul_f64 v[72:73], v[4:5], -v[34:35]
	v_fma_f64 v[36:37], v[21:22], v[36:37], s[2:3]
	v_fma_f64 v[38:39], v[32:33], v[38:39], s[2:3]
	v_fma_f64 v[40:41], v[34:35], v[40:41], s[2:3]
	s_mov_b32 s2, 0x19e83e5c
	s_mov_b32 s3, 0xbf2a01a0
	v_fma_f64 v[42:43], v[21:22], v[42:43], s[0:1]
	v_add_f64 v[54:55], -v[44:45], 1.0
	v_add_f64 v[56:57], -v[46:47], 1.0
	v_fma_f64 v[48:49], v[32:33], v[48:49], s[0:1]
	v_add_f64 v[58:59], -v[50:51], 1.0
	v_fma_f64 v[52:53], v[34:35], v[52:53], s[0:1]
	s_mov_b32 s0, 0x11110bb3
	s_mov_b32 s1, 0x3f811111
	v_fma_f64 v[36:37], v[21:22], v[36:37], s[2:3]
	v_fma_f64 v[38:39], v[32:33], v[38:39], s[2:3]
	v_fma_f64 v[40:41], v[34:35], v[40:41], s[2:3]
	s_mov_b32 s3, 0xb94c1982
	v_fma_f64 v[42:43], v[21:22], v[42:43], s[6:7]
	v_add_f64 v[64:65], -v[54:55], 1.0
	v_add_f64 v[74:75], -v[56:57], 1.0
	v_fma_f64 v[48:49], v[32:33], v[48:49], s[6:7]
	v_add_f64 v[76:77], -v[58:59], 1.0
	v_fma_f64 v[52:53], v[34:35], v[52:53], s[6:7]
	s_mov_b32 s6, 0x37d75334
	v_fma_f64 v[36:37], v[21:22], v[36:37], s[0:1]
	v_fma_f64 v[38:39], v[32:33], v[38:39], s[0:1]
	v_fma_f64 v[40:41], v[34:35], v[40:41], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	s_delay_alu instid0(SALU_CYCLE_1)
	v_fma_f64 v[42:43], v[21:22], v[42:43], s[0:1]
	v_add_f64 v[44:45], v[64:65], -v[44:45]
	v_add_f64 v[46:47], v[74:75], -v[46:47]
	v_fma_f64 v[48:49], v[32:33], v[48:49], s[0:1]
	v_add_f64 v[50:51], v[76:77], -v[50:51]
	v_fma_f64 v[52:53], v[34:35], v[52:53], s[0:1]
	s_mov_b32 s0, 0x55555555
	s_mov_b32 s1, 0x3fa55555
	v_fma_f64 v[36:37], v[62:63], v[36:37], v[60:61]
	v_fma_f64 v[38:39], v[70:71], v[38:39], v[66:67]
	v_fma_f64 v[40:41], v[72:73], v[40:41], v[68:69]
	v_mul_f64 v[60:61], v[21:22], v[21:22]
	v_fma_f64 v[42:43], v[21:22], v[42:43], s[0:1]
	v_fma_f64 v[44:45], v[12:13], -v[14:15], v[44:45]
	v_fma_f64 v[46:47], v[8:9], -v[10:11], v[46:47]
	v_fma_f64 v[48:49], v[32:33], v[48:49], s[0:1]
	v_fma_f64 v[52:53], v[34:35], v[52:53], s[0:1]
	s_mov_b32 s1, 0xbfc55555
	v_fma_f64 v[14:15], v[21:22], v[36:37], -v[14:15]
	v_mul_f64 v[21:22], v[32:33], v[32:33]
	v_fma_f64 v[10:11], v[32:33], v[38:39], -v[10:11]
	v_mul_f64 v[36:37], v[34:35], v[34:35]
	v_fma_f64 v[32:33], v[4:5], -v[6:7], v[50:51]
	v_fma_f64 v[6:7], v[34:35], v[40:41], -v[6:7]
	v_fma_f64 v[34:35], v[60:61], v[42:43], v[44:45]
	v_lshlrev_b32_e32 v43, 30, v18
	v_and_b32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v43, 0x80000000, v43
	v_cmp_eq_u32_e64 s2, 0, v18
	v_fma_f64 v[14:15], v[62:63], s[0:1], v[14:15]
	v_fma_f64 v[21:22], v[21:22], v[48:49], v[46:47]
	v_fma_f64 v[10:11], v[70:71], s[0:1], v[10:11]
	v_fma_f64 v[32:33], v[36:37], v[52:53], v[32:33]
	v_fma_f64 v[6:7], v[72:73], s[0:1], v[6:7]
	v_cmp_class_f64_e64 s0, v[2:3], 0x1f8
	v_add_f64 v[34:35], v[54:55], v[34:35]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_add_f64 v[14:15], v[56:57], v[21:22]
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	v_and_b32_e32 v23, 1, v31
	v_add_f64 v[10:11], v[58:59], v[32:33]
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_cvt_f64_f32_e32 v[6:7], v28
	v_cvt_f64_f32_e32 v[21:22], v26
	v_cmp_eq_u32_e32 vcc_lo, 0, v23
	v_lshlrev_b32_e32 v23, 30, v30
	v_and_b32_e32 v30, 1, v30
	v_lshlrev_b32_e32 v2, 30, v31
	v_cvt_f64_f32_e32 v[25:26], v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v23, v23, v3
	v_cmp_eq_u32_e64 s1, 0, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v2, v2, v3
	v_and_b32_e32 v23, 0x80000000, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, 0x80000000, v2
	v_cndmask_b32_e32 v12, v34, v12, vcc_lo
	v_cndmask_b32_e64 v9, v15, v9, s1
	v_cndmask_b32_e64 v8, v14, v8, s1
	v_xor_b32_e32 v9, v9, v23
	v_mul_f32_e32 v23, v17, v17
	v_lshlrev_b32_e32 v28, 30, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, 0, v8, s0
	v_cndmask_b32_e64 v9, 0x7ff80000, v9, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmaak_f32 v41, s3, v23, 0x3c0881c4
	v_fmaak_f32 v42, s6, v23, 0xbab64f3b
	v_xor_b32_e32 v3, v28, v3
	v_and_b32_e32 v28, 1, v29
	v_fmaak_f32 v41, v23, v41, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v29, 0x80000000, v3
	v_cndmask_b32_e32 v3, v35, v13, vcc_lo
	v_mul_f32_e32 v41, v23, v41
	v_fmaak_f32 v42, v23, v42, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v13, v3, v2
	v_cvt_f64_f32_e32 v[2:3], v27
	v_dual_fmac_f32 v17, v17, v41 :: v_dual_fmaak_f32 v42, v23, v42, 0xbf000004
	v_xor_b32_e32 v41, v16, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, v23, v42, 1.0
	v_cndmask_b32_e64 v17, v23, v17, s2
	v_mul_f32_e32 v23, v19, v19
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	v_cmp_class_f32_e64 s2, v24, 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v17, v41, v17, v24
	v_fmaak_f32 v18, s3, v23, 0x3c0881c4
	v_dual_cndmask_b32 v11, v11, v5 :: v_dual_cndmask_b32 v10, v10, v4
	v_cndmask_b32_e64 v4, 0, v12, s0
	v_cndmask_b32_e64 v5, 0x7ff80000, v13, s0
	v_cndmask_b32_e64 v17, 0x7fc00000, v17, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_xor_b32_e32 v11, v11, v29
	v_cndmask_b32_e64 v10, 0, v10, s0
	v_fmaak_f32 v41, s6, v23, 0xbab64f3b
	v_mul_f64 v[4:5], v[6:7], -v[4:5]
	v_mul_f64 v[6:7], v[21:22], -v[8:9]
	v_cndmask_b32_e64 v11, 0x7ff80000, v11, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[8:9], v[25:26], -v[10:11]
	v_div_scale_f64 v[10:11], null, v[2:3], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[12:13], null, v[2:3], v[2:3], v[6:7]
	v_div_scale_f64 v[35:36], vcc_lo, v[4:5], v[2:3], v[4:5]
	v_div_scale_f64 v[14:15], null, v[2:3], v[2:3], v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[21:22], v[10:11]
	v_rcp_f64_e32 v[25:26], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[27:28], v[14:15]
	v_fma_f64 v[29:30], -v[10:11], v[21:22], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[31:32], -v[12:13], v[25:26], 1.0
	v_fma_f64 v[33:34], -v[14:15], v[27:28], 1.0
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[25:26], v[31:32], v[25:26]
	v_fma_f64 v[27:28], v[27:28], v[33:34], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], -v[10:11], v[21:22], 1.0
	v_fma_f64 v[31:32], -v[12:13], v[25:26], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], -v[14:15], v[27:28], 1.0
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
	v_div_scale_f64 v[29:30], s0, v[6:7], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[25:26], v[25:26], v[31:32], v[25:26]
	v_div_scale_f64 v[31:32], s1, v[8:9], v[2:3], v[8:9]
	v_fma_f64 v[27:28], v[27:28], v[33:34], v[27:28]
	v_mul_f64 v[33:34], v[35:36], v[21:22]
	v_mul_f64 v[37:38], v[29:30], v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[39:40], v[31:32], v[27:28]
	v_fma_f64 v[10:11], -v[10:11], v[33:34], v[35:36]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[12:13], -v[12:13], v[37:38], v[29:30]
	v_fmaak_f32 v29, v23, v18, 0xbe2aaa9d
	v_cvt_f64_f32_e32 v[17:18], v17
	v_fma_f64 v[14:15], -v[14:15], v[39:40], v[31:32]
	v_lshlrev_b32_e32 v31, 30, v20
	v_and_b32_e32 v20, 1, v20
	v_fmaak_f32 v30, v23, v41, 0x3d2aabf7
	v_mul_f32_e32 v29, v23, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v31, 0x80000000, v31
	v_cmp_eq_u32_e64 s3, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v30, v23, v30, 0xbf000004
	v_fmac_f32_e32 v19, v19, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v16, v16, v31
	v_fma_f32 v23, v23, v30, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v23, v19, s3
	v_xor3_b32 v16, v16, v19, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v16, 0x7fc00000, v16, s2
	v_div_fmas_f64 v[10:11], v[10:11], v[21:22], v[33:34]
	s_mov_b32 vcc_lo, s0
	v_cvt_f64_f32_e32 v[19:20], v16
	v_div_fmas_f64 v[12:13], v[12:13], v[25:26], v[37:38]
	s_mov_b32 vcc_lo, s1
	v_mul_f64 v[16:17], v[17:18], 0.5
	v_div_fmas_f64 v[14:15], v[14:15], v[27:28], v[39:40]
	v_div_fixup_f64 v[4:5], v[10:11], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[6:7], v[12:13], v[2:3], v[6:7]
	v_div_fixup_f64 v[2:3], v[14:15], v[2:3], v[8:9]
	v_mul_f64 v[8:9], v[16:17], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_f64_e32 v5, v[4:5]
	v_cvt_f32_f64_e32 v4, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_f64_e32 v3, v[2:3]
	v_cvt_f32_f64_e32 v2, v[8:9]
.LBB1_23:                               ; %Flow115
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v8, vcc_lo, v6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v9, vcc_lo
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	s_clause 0x2
	global_store_b32 v[6:7], v3, off
	global_store_b32 v[8:9], v4, off
	global_store_b32 v[10:11], v5, off
	global_store_b32 v[0:1], v2, off
.LBB1_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 78
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_, .Lfunc_end1-_Z34GPU_compute_forceonparticle_KERNELiiifPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6604
; NumSgprs: 18
; NumVgprs: 78
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 78
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13GPU_updatePosifPfPKfS1_ ; -- Begin function _Z13GPU_updatePosifPfPKfS1_
	.globl	_Z13GPU_updatePosifPfPKfS1_
	.p2align	8
	.type	_Z13GPU_updatePosifPfPKfS1_,@function
_Z13GPU_updatePosifPfPKfS1_:            ; @_Z13GPU_updatePosifPfPKfS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[4:5], s[0:1], 0x18
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	s_load_b128 s[4:7], s[0:1], 0x8
	global_load_b32 v4, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b32 v8, v[0:1], off
	s_waitcnt vmcnt(2)
	v_cvt_f64_f32_e32 v[2:3], v4
	v_cvt_f64_f32_e32 v[4:5], s3
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v6, s3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f64_f32_e32 v[6:7], v6
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[4:5], v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_cvt_f32_f64_e32 v2, v[2:3]
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13GPU_updatePosifPfPKfS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13GPU_updatePosifPfPKfS1_, .Lfunc_end2-_Z13GPU_updatePosifPfPKfS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13GPU_updateVeliffPfPKfS1_ ; -- Begin function _Z13GPU_updateVeliffPfPKfS1_
	.globl	_Z13GPU_updateVeliffPfPKfS1_
	.p2align	8
	.type	_Z13GPU_updateVeliffPfPKfS1_,@function
_Z13GPU_updateVeliffPfPKfS1_:           ; @_Z13GPU_updateVeliffPfPKfS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x20
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	global_load_b32 v6, v[2:3], off
	global_load_b32 v4, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_cvt_f64_f32_e32 v[2:3], s5
	global_load_b32 v7, v[0:1], off
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v4, s6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[4:5], v4
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[6:7], v7
	v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v2, v[2:3]
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13GPU_updateVeliffPfPKfS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z13GPU_updateVeliffPfPKfS1_, .Lfunc_end3-_Z13GPU_updateVeliffPfPKfS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13GPU_updateAccifPfPKf ; -- Begin function _Z13GPU_updateAccifPfPKf
	.globl	_Z13GPU_updateAccifPfPKf
	.p2align	8
	.type	_Z13GPU_updateAccifPfPKf,@function
_Z13GPU_updateAccifPfPKf:               ; @_Z13GPU_updateAccifPfPKf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, s3, v2
	global_store_b32 v[0:1], v2, off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13GPU_updateAccifPfPKf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z13GPU_updateAccifPfPKf, .Lfunc_end4-_Z13GPU_updateAccifPfPKf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z15reduce_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z15reduce_wShrdMemIfEvPT_S1_j,comdat
	.protected	_Z15reduce_wShrdMemIfEvPT_S1_j ; -- Begin function _Z15reduce_wShrdMemIfEvPT_S1_j
	.globl	_Z15reduce_wShrdMemIfEvPT_S1_j
	.p2align	8
	.type	_Z15reduce_wShrdMemIfEvPT_S1_j,@function
_Z15reduce_wShrdMemIfEvPT_S1_j:         ; @_Z15reduce_wShrdMemIfEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB5_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB5_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB5_3:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB5_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB5_3 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB5_6
; %bb.5:                                ;   in Loop: Header=BB5_3 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB5_6:                                ;   in Loop: Header=BB5_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB5_3
.LBB5_7:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[4:5], 2
	s_add_u32 s2, s2, s4
	ds_load_b32 v1, v0
	s_addc_u32 s3, s3, s5
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[2:3]
.LBB5_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15reduce_wShrdMemIfEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z15reduce_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z15reduce_wShrdMemIfEvPT_S1_j,comdat
.Lfunc_end5:
	.size	_Z15reduce_wShrdMemIfEvPT_S1_j, .Lfunc_end5-_Z15reduce_wShrdMemIfEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,comdat
	.protected	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j ; -- Begin function _Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.globl	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
	.p2align	8
	.type	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,@function
_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j: ; @_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB6_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB6_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v2, v2, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB6_3:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB6_3 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB6_6
; %bb.5:                                ;   in Loop: Header=BB6_3 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB6_6:                                ;   in Loop: Header=BB6_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB6_3
.LBB6_7:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[4:5], 2
	s_add_u32 s2, s2, s4
	ds_load_b32 v1, v0
	s_addc_u32 s3, s3, s5
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[2:3]
.LBB6_9:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,"axG",@progbits,_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j,comdat
.Lfunc_end6:
	.size	_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j, .Lfunc_end6-_Z23GPU_compute_KE_wShrdMemIfEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 364
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9dummyCopyPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9dummyCopyPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
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...

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