#include "cuda.h"
#include "stdio.h"
#include "stdlib.h"
#define LBLK 8

__device__ int get_index(int N, int C, int H, int W, int a, int b, int c, int d) {
    return a * C * H * W + b * W * H + c * W + d;
}

__device__ int RM(int i, int j, int N) {
    return i * N + j;
}

__global__ void conv_kernel(float *weight, float *inp, float *bias, float *out, int N, int C, int H, int W, int num_filter, int filter_depth, int filter_H, int filter_W, int out_size, int stride) {
    int h = blockIdx.y * blockDim.y + threadIdx.y;
    int w = blockIdx.x * blockDim.x + threadIdx.x;
    int k_d = blockIdx.z * blockDim.z + threadIdx.z;
    int n, c, k_h, k_w;
    if (h < out_size && w < out_size && k_d < num_filter) {
        float my_bias = bias[k_d];
        int kernel_x = w * stride;
        int kernel_y = h * stride;
        for (n = 0; n < N; n ++) {
            float cur_val = my_bias;
            for (c = 0; c < filter_depth; c ++) { 
                for (k_h = 0; k_h < filter_H; k_h ++) {
                    for (k_w = 0; k_w < filter_W; k_w ++) {
                        float target_weight = weight[get_index(num_filter, filter_depth, filter_H, filter_W, k_d, c, k_h, k_w)];
                        float target_inp = inp[get_index(N, C, H, W, n, c, kernel_y + k_h, kernel_x + k_w)];
                        cur_val += target_inp * target_weight;
                    }
                }
            }
            out[get_index(N, num_filter, out_size, out_size, n, k_d, h, w)] = cur_val; 
        }
    }
}

__global__ void matmul_kernel(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
    int i = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    int bi = threadIdx.y;
    int bj = threadIdx.x;
    __shared__ float subA[LBLK * LBLK];
    __shared__ float subB[LBLK * LBLK];

    float sum = 0.0;
    int k;

    for (k = 0; k < An; k += LBLK) {
        if (i < Am && k + bj < An) {
            subA[RM(bi, bj, LBLK)] = A[RM(i, k + bj, An)];
        } else {
            subA[RM(bi, bj, LBLK)] = 0.0;
        }
        if (k + bi < Bm && j < Bn) {
            subB[RM(bi, bj, LBLK)] = B[RM(k + bi, j, Bn)];
        } else {
            subB[RM(bi, bj, LBLK)] = 0.0;
        }
        __syncthreads();
        
        for (int bk = 0; bk < LBLK; bk++) {
            sum += subA[RM(bi, bk, LBLK)] * subB[RM(bk, bj, LBLK)];
        }
        __syncthreads();
    }

    if (i < Am && j < Bn) {
        out[RM(i, j, Bn)] = sum;
    }
    
}

extern "C" int conv_CUDA_main(float *inp, float *weight, float *bias, float *out, int stride, float *dims) {
    int N = (int)dims[0];
    int C = (int)dims[1];
    int H = (int)dims[2];
    int W = (int)dims[3];
    int num_filter = (int)dims[4];
    int filter_depth = (int)dims[5];
    int filter_H = (int)dims[6];
    int filter_W = (int)dims[7];
    int out_size = (int)dims[8];

    float *dev_weight, *dev_inp, *dev_bias, *dev_out;

    cudaMalloc(&dev_weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float));
    cudaMalloc(&dev_inp, N * C * H * W * sizeof(float));
    cudaMalloc(&dev_bias, num_filter * sizeof(float));
    cudaMalloc(&dev_out, N * num_filter * out_size * out_size * sizeof(float));

    cudaMemcpy(dev_weight, weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(dev_inp, inp, N * C * H * W * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(dev_bias, bias, num_filter * sizeof(float), cudaMemcpyHostToDevice);

    dim3 blockDim(8, 8, 8);
    dim3 gridDim((out_size + blockDim.x - 1) / blockDim.x, (out_size + blockDim.y - 1) / blockDim.y, (num_filter + blockDim.z - 1) / blockDim.z);

    conv_kernel<<<gridDim, blockDim>>>(dev_weight, dev_inp, dev_bias, dev_out, N, C, H, W, num_filter, filter_depth, filter_H, filter_W, out_size, stride);
    
    cudaMemcpy(out, dev_out, N * num_filter * out_size * out_size * sizeof(float), cudaMemcpyDeviceToHost);

    cudaFree(dev_weight);
    cudaFree(dev_inp);
    cudaFree(dev_bias);
    cudaFree(dev_out);

    return 0;
}

extern "C" int matmul_CUDA_main(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
    float *dev_A, *dev_B, *dev_bias, *dev_out;   

    cudaMalloc(&dev_A, Am * An * sizeof(float));
    cudaMalloc(&dev_B, Bm * Bn * sizeof(float));
    cudaMalloc(&dev_out, Am * Bn * sizeof(float));

    cudaMemcpy(dev_A, A, Am * An * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(dev_B, B, Bm * Bn * sizeof(float), cudaMemcpyHostToDevice);

    dim3 blockDim(8, 8);
    dim3 gridDim((Bn + blockDim.x - 1) / blockDim.x, (Am + blockDim.y - 1) / blockDim.y);

    matmul_kernel<<<gridDim, blockDim>>>(dev_A, dev_B, dev_out, Am, An, Bm, Bn);
    
    cudaMemcpy(out, dev_out, Am * Bn * sizeof(float), cudaMemcpyDeviceToHost);

    cudaFree(dev_A);
    cudaFree(dev_B);
    cudaFree(dev_out);

    return 0;
}
	.file	"tmpxft_0023421e_00000000-6_cuda_blockadd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9get_indexiiiiiiii
	.type	_Z9get_indexiiiiiiii, @function
_Z9get_indexiiiiiiii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z9get_indexiiiiiiii, .-_Z9get_indexiiiiiiii
	.globl	_Z2RMiii
	.type	_Z2RMiii, @function
_Z2RMiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z2RMiii, .-_Z2RMiii
	.globl	_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
	.type	_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii, @function
_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	64(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z11conv_kernelPfS_S_S_iiiiiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 272
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L6:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii, .-_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
	.globl	_Z11conv_kernelPfS_S_S_iiiiiiiiii
	.type	_Z11conv_kernelPfS_S_S_iiiiiiiiii, @function
_Z11conv_kernelPfS_S_S_iiiiiiiiii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
	.cfi_endproc
.LFE2056:
	.size	_Z11conv_kernelPfS_S_S_iiiiiiiiii, .-_Z11conv_kernelPfS_S_S_iiiiiiiiii
	.globl	conv_CUDA_main
	.type	conv_CUDA_main, @function
conv_CUDA_main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	cvttss2sil	16(%r9), %ebx
	cvttss2sil	20(%r9), %r15d
	movq	%rdx, 40(%rsp)
	cvttss2sil	24(%r9), %r10d
	movl	%r8d, 60(%rsp)
	cvttss2sil	28(%r9), %r11d
	movq	%rcx, 48(%rsp)
	movl	%ebx, %edx
	movq	%rdi, 24(%rsp)
	cvttss2sil	(%r9), %r12d
	leaq	80(%rsp), %rdi
	imull	%r15d, %edx
	movq	%rsi, 32(%rsp)
	cvttss2sil	32(%r9), %ebp
	cvttss2sil	8(%r9), %r13d
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	imull	%r10d, %edx
	movl	%r10d, 76(%rsp)
	cvttss2sil	4(%r9), %eax
	cvttss2sil	12(%r9), %r14d
	imull	%r11d, %edx
	movl	%eax, 56(%rsp)
	movslq	%edx, %rdx
	movl	%r11d, 72(%rsp)
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 64(%rsp)
	call	cudaMalloc@PLT
	movl	56(%rsp), %eax
	leaq	88(%rsp), %rdi
	imull	%r12d, %eax
	imull	%r13d, %eax
	imull	%r14d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movslq	%ebx, %rax
	leaq	96(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movl	%r12d, %eax
	leaq	104(%rsp), %rdi
	imull	%ebx, %eax
	imull	%ebp, %eax
	imull	%ebp, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	movq	64(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	80(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	88(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	96(%rsp), %rdi
	call	cudaMemcpy@PLT
	leal	7(%rbp), %eax
	leal	7(%rbx), %esi
	xorl	%r9d, %r9d
	shrl	$3, %eax
	shrl	$3, %esi
	xorl	%r8d, %r8d
	movl	$8, %ecx
	movabsq	$34359738376, %rdx
	movl	%eax, 124(%rsp)
	movl	%eax, 128(%rsp)
	movq	124(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movl	72(%rsp), %r11d
	movl	76(%rsp), %r10d
	testl	%eax, %eax
	jne	.L13
	movl	60(%rsp), %eax
	movl	%r12d, %r8d
	pushq	%rax
	.cfi_def_cfa_offset 216
	pushq	%rbp
	.cfi_def_cfa_offset 224
	pushq	%r11
	.cfi_def_cfa_offset 232
	pushq	%r10
	.cfi_def_cfa_offset 240
	pushq	%r15
	.cfi_def_cfa_offset 248
	pushq	%rbx
	.cfi_def_cfa_offset 256
	pushq	%r14
	.cfi_def_cfa_offset 264
	pushq	%r13
	.cfi_def_cfa_offset 272
	movl	120(%rsp), %r9d
	movq	168(%rsp), %rcx
	movq	160(%rsp), %rdx
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
	addq	$64, %rsp
	.cfi_def_cfa_offset 208
.L13:
	movq	16(%rsp), %rdx
	movq	104(%rsp), %rsi
	movl	$2, %ecx
	movq	48(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	conv_CUDA_main, .-conv_CUDA_main
	.globl	_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
	.type	_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z13matmul_kernelPfS_S_iiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L16:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii, .-_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
	.globl	_Z13matmul_kernelPfS_S_iiii
	.type	_Z13matmul_kernelPfS_S_iiii, @function
_Z13matmul_kernelPfS_S_iiii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
	.cfi_endproc
.LFE2058:
	.size	_Z13matmul_kernelPfS_S_iiii, .-_Z13matmul_kernelPfS_S_iiii
	.globl	matmul_CUDA_main
	.type	matmul_CUDA_main, @function
matmul_CUDA_main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdx, 16(%rsp)
	movl	%ecx, %edx
	leaq	40(%rsp), %rdi
	movl	160(%rsp), %r12d
	imull	%r8d, %edx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movslq	%edx, %rdx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 24(%rsp)
	call	cudaMalloc@PLT
	movl	%ebp, %eax
	leaq	48(%rsp), %rdi
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movl	%ebx, %eax
	leaq	56(%rsp), %rdi
	imull	%r12d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdx
	movq	40(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	7(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$3, %eax
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$34359738376, %rdx
	movl	%eax, 76(%rsp)
	leal	7(%rbx), %eax
	shrl	$3, %eax
	movl	%eax, 80(%rsp)
	movq	76(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	%rax
	.cfi_def_cfa_offset 168
	movl	%ebx, %ecx
	movl	%ebp, %r9d
	movl	%r13d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 176
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
	popq	%rdx
	.cfi_def_cfa_offset 168
	popq	%rcx
	.cfi_def_cfa_offset 160
.L22:
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	matmul_CUDA_main, .-matmul_CUDA_main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13matmul_kernelPfS_S_iiii"
.LC1:
	.string	"_Z11conv_kernelPfS_S_S_iiiiiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13matmul_kernelPfS_S_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11conv_kernelPfS_S_S_iiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"
#include "stdio.h"
#include "stdlib.h"
#define LBLK 8

__device__ int get_index(int N, int C, int H, int W, int a, int b, int c, int d) {
    return a * C * H * W + b * W * H + c * W + d;
}

__device__ int RM(int i, int j, int N) {
    return i * N + j;
}

__global__ void conv_kernel(float *weight, float *inp, float *bias, float *out, int N, int C, int H, int W, int num_filter, int filter_depth, int filter_H, int filter_W, int out_size, int stride) {
    int h = blockIdx.y * blockDim.y + threadIdx.y;
    int w = blockIdx.x * blockDim.x + threadIdx.x;
    int k_d = blockIdx.z * blockDim.z + threadIdx.z;
    int n, c, k_h, k_w;
    if (h < out_size && w < out_size && k_d < num_filter) {
        float my_bias = bias[k_d];
        int kernel_x = w * stride;
        int kernel_y = h * stride;
        for (n = 0; n < N; n ++) {
            float cur_val = my_bias;
            for (c = 0; c < filter_depth; c ++) { 
                for (k_h = 0; k_h < filter_H; k_h ++) {
                    for (k_w = 0; k_w < filter_W; k_w ++) {
                        float target_weight = weight[get_index(num_filter, filter_depth, filter_H, filter_W, k_d, c, k_h, k_w)];
                        float target_inp = inp[get_index(N, C, H, W, n, c, kernel_y + k_h, kernel_x + k_w)];
                        cur_val += target_inp * target_weight;
                    }
                }
            }
            out[get_index(N, num_filter, out_size, out_size, n, k_d, h, w)] = cur_val; 
        }
    }
}

__global__ void matmul_kernel(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
    int i = blockIdx.y * blockDim.y + threadIdx.y;
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    int bi = threadIdx.y;
    int bj = threadIdx.x;
    __shared__ float subA[LBLK * LBLK];
    __shared__ float subB[LBLK * LBLK];

    float sum = 0.0;
    int k;

    for (k = 0; k < An; k += LBLK) {
        if (i < Am && k + bj < An) {
            subA[RM(bi, bj, LBLK)] = A[RM(i, k + bj, An)];
        } else {
            subA[RM(bi, bj, LBLK)] = 0.0;
        }
        if (k + bi < Bm && j < Bn) {
            subB[RM(bi, bj, LBLK)] = B[RM(k + bi, j, Bn)];
        } else {
            subB[RM(bi, bj, LBLK)] = 0.0;
        }
        __syncthreads();
        
        for (int bk = 0; bk < LBLK; bk++) {
            sum += subA[RM(bi, bk, LBLK)] * subB[RM(bk, bj, LBLK)];
        }
        __syncthreads();
    }

    if (i < Am && j < Bn) {
        out[RM(i, j, Bn)] = sum;
    }
    
}

extern "C" int conv_CUDA_main(float *inp, float *weight, float *bias, float *out, int stride, float *dims) {
    int N = (int)dims[0];
    int C = (int)dims[1];
    int H = (int)dims[2];
    int W = (int)dims[3];
    int num_filter = (int)dims[4];
    int filter_depth = (int)dims[5];
    int filter_H = (int)dims[6];
    int filter_W = (int)dims[7];
    int out_size = (int)dims[8];

    float *dev_weight, *dev_inp, *dev_bias, *dev_out;

    hipMalloc(&dev_weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float));
    hipMalloc(&dev_inp, N * C * H * W * sizeof(float));
    hipMalloc(&dev_bias, num_filter * sizeof(float));
    hipMalloc(&dev_out, N * num_filter * out_size * out_size * sizeof(float));

    hipMemcpy(dev_weight, weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(dev_inp, inp, N * C * H * W * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(dev_bias, bias, num_filter * sizeof(float), hipMemcpyHostToDevice);

    dim3 blockDim(8, 8, 8);
    dim3 gridDim((out_size + blockDim.x - 1) / blockDim.x, (out_size + blockDim.y - 1) / blockDim.y, (num_filter + blockDim.z - 1) / blockDim.z);

    conv_kernel<<<gridDim, blockDim>>>(dev_weight, dev_inp, dev_bias, dev_out, N, C, H, W, num_filter, filter_depth, filter_H, filter_W, out_size, stride);
    
    hipMemcpy(out, dev_out, N * num_filter * out_size * out_size * sizeof(float), hipMemcpyDeviceToHost);

    hipFree(dev_weight);
    hipFree(dev_inp);
    hipFree(dev_bias);
    hipFree(dev_out);

    return 0;
}

extern "C" int matmul_CUDA_main(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
    float *dev_A, *dev_B, *dev_bias, *dev_out;   

    hipMalloc(&dev_A, Am * An * sizeof(float));
    hipMalloc(&dev_B, Bm * Bn * sizeof(float));
    hipMalloc(&dev_out, Am * Bn * sizeof(float));

    hipMemcpy(dev_A, A, Am * An * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(dev_B, B, Bm * Bn * sizeof(float), hipMemcpyHostToDevice);

    dim3 blockDim(8, 8);
    dim3 gridDim((Bn + blockDim.x - 1) / blockDim.x, (Am + blockDim.y - 1) / blockDim.y);

    matmul_kernel<<<gridDim, blockDim>>>(dev_A, dev_B, dev_out, Am, An, Bm, Bn);
    
    hipMemcpy(out, dev_out, Am * Bn * sizeof(float), hipMemcpyDeviceToHost);

    hipFree(dev_A);
    hipFree(dev_B);
    hipFree(dev_out);

    return 0;
}
	.text
	.file	"cuda_blockadd.hip"
	.globl	_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii # -- Begin function _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
	.type	_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii,@function
_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii: # @_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11conv_kernelPfS_S_S_iiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii, .Lfunc_end0-_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__matmul_kernelPfS_S_iiii # -- Begin function _Z28__device_stub__matmul_kernelPfS_S_iiii
	.type	_Z28__device_stub__matmul_kernelPfS_S_iiii,@function
_Z28__device_stub__matmul_kernelPfS_S_iiii: # @_Z28__device_stub__matmul_kernelPfS_S_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13matmul_kernelPfS_S_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__matmul_kernelPfS_S_iiii, .Lfunc_end1-_Z28__device_stub__matmul_kernelPfS_S_iiii
	.cfi_endproc
                                        # -- End function
	.globl	conv_CUDA_main                  # -- Begin function conv_CUDA_main
	.type	conv_CUDA_main,@function
conv_CUDA_main:                         # @conv_CUDA_main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cvttss2si	(%r9), %r14d
	cvttss2si	4(%r9), %ebp
	cvttss2si	8(%r9), %ebx
	cvttss2si	12(%r9), %r15d
	cvttss2si	16(%r9), %r12d
                                        # kill: def $r8d killed $r8d def $r8
	movq	%r8, 48(%rsp)                   # 8-byte Spill
	cvttss2si	20(%r9), %eax
	movq	%rcx, 128(%rsp)                 # 8-byte Spill
	cvttss2si	24(%r9), %ecx
	movq	%rdx, 120(%rsp)                 # 8-byte Spill
	cvttss2si	28(%r9), %edx
	movq	%rsi, 104(%rsp)                 # 8-byte Spill
	cvttss2si	32(%r9), %esi
	movq	%rsi, 96(%rsp)                  # 8-byte Spill
	movq	%rdi, 112(%rsp)                 # 8-byte Spill
	movq	%rax, 72(%rsp)                  # 8-byte Spill
                                        # kill: def $eax killed $eax killed $rax
	imull	%r12d, %eax
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
                                        # kill: def $ecx killed $ecx killed $rcx
	movq	%rdx, 56(%rsp)                  # 8-byte Spill
	imull	%edx, %ecx
	imull	%eax, %ecx
	movslq	%ecx, %r13
	shlq	$2, %r13
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movl	%ebp, 32(%rsp)                  # 4-byte Spill
	movl	%ebp, %eax
	imull	%r14d, %eax
	movq	%rbx, 88(%rsp)                  # 8-byte Spill
	movl	%ebx, %ecx
	movq	%r15, 80(%rsp)                  # 8-byte Spill
	imull	%r15d, %ecx
	imull	%eax, %ecx
	movslq	%ecx, %rbp
	shlq	$2, %rbp
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movslq	%r12d, %r15
	leaq	(,%r15,4), %rbx
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r12, 40(%rsp)                  # 8-byte Spill
	movl	%r12d, %eax
	movl	%r14d, 36(%rsp)                 # 4-byte Spill
	imull	%r14d, %eax
	movq	96(%rsp), %r14                  # 8-byte Reload
	movl	%r14d, %ecx
	imull	%r14d, %ecx
	imull	%eax, %ecx
	movslq	%ecx, %r12
	shlq	$2, %r12
	movq	%rsp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	112(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	120(%rsp), %rsi                 # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	7(%r14), %eax
	shrl	$3, %eax
	addl	$7, %r15d
	shrl	$3, %r15d
	movq	%rax, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	%r15d, %esi
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	36(%rsp), %r8d                  # 4-byte Reload
	movl	32(%rsp), %r9d                  # 4-byte Reload
	pushq	48(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	128(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	144(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB2_2:
	movq	(%rsp), %rsi
	movq	128(%rsp), %rdi                 # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	conv_CUDA_main, .Lfunc_end2-conv_CUDA_main
	.cfi_endproc
                                        # -- End function
	.globl	matmul_CUDA_main                # -- Begin function matmul_CUDA_main
	.type	matmul_CUDA_main,@function
matmul_CUDA_main:                       # @matmul_CUDA_main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r14d
	movl	%ecx, %r15d
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, %r13
	movl	112(%rsp), %ebx
	movl	%r8d, 32(%rsp)                  # 4-byte Spill
	movl	%r8d, %eax
	imull	%ecx, %eax
	movslq	%eax, %rbp
	shlq	$2, %rbp
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	%ebx, %eax
	movl	%r14d, 36(%rsp)                 # 4-byte Spill
	imull	%r14d, %eax
	movslq	%eax, %r14
	shlq	$2, %r14
	leaq	16(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	%ebx, %eax
	imull	%r15d, %eax
	movslq	%eax, %r12
	shlq	$2, %r12
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	7(%rbx), %eax
	shrl	$3, %eax
	leal	7(%r15), %edi
	shrl	$3, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%ebx, (%rsp)
	movl	%r15d, %ecx
	movl	32(%rsp), %r8d                  # 4-byte Reload
	movl	36(%rsp), %r9d                  # 4-byte Reload
	callq	_Z28__device_stub__matmul_kernelPfS_S_iiii
.LBB3_2:
	movq	8(%rsp), %rsi
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	matmul_CUDA_main, .Lfunc_end3-matmul_CUDA_main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11conv_kernelPfS_S_S_iiiiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13matmul_kernelPfS_S_iiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11conv_kernelPfS_S_S_iiiiiiiiii,@object # @_Z11conv_kernelPfS_S_S_iiiiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z11conv_kernelPfS_S_S_iiiiiiiiii
	.p2align	3, 0x0
_Z11conv_kernelPfS_S_S_iiiiiiiiii:
	.quad	_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
	.size	_Z11conv_kernelPfS_S_S_iiiiiiiiii, 8

	.type	_Z13matmul_kernelPfS_S_iiii,@object # @_Z13matmul_kernelPfS_S_iiii
	.globl	_Z13matmul_kernelPfS_S_iiii
	.p2align	3, 0x0
_Z13matmul_kernelPfS_S_iiii:
	.quad	_Z28__device_stub__matmul_kernelPfS_S_iiii
	.size	_Z13matmul_kernelPfS_S_iiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11conv_kernelPfS_S_S_iiiiiiiiii"
	.size	.L__unnamed_1, 34

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13matmul_kernelPfS_S_iiii"
	.size	.L__unnamed_2, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
	.addrsig_sym _Z28__device_stub__matmul_kernelPfS_S_iiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11conv_kernelPfS_S_S_iiiiiiiiii
	.addrsig_sym _Z13matmul_kernelPfS_S_iiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11conv_kernelPfS_S_S_iiiiiiiiii ; -- Begin function _Z11conv_kernelPfS_S_S_iiiiiiiiii
	.globl	_Z11conv_kernelPfS_S_S_iiiiiiiiii
	.p2align	8
	.type	_Z11conv_kernelPfS_S_S_iiiiiiiiii,@function
_Z11conv_kernelPfS_S_S_iiiiiiiiii:      ; @_Z11conv_kernelPfS_S_S_iiiiiiiiii
; %bb.0:
	s_clause 0x2
	s_load_b64 s[16:17], s[0:1], 0x54
	s_load_b64 s[20:21], s[0:1], 0x40
	s_load_b256 s[4:11], s[0:1], 0x20
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s16, 16
	s_and_b32 s3, s16, 0xffff
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	s_mul_i32 s3, s13, s3
	s_and_b32 s2, s17, 0xffff
	v_add_nc_u32_e32 v1, s3, v4
	v_mad_u64_u32 v[2:3], null, s15, s2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v3, v0, v1
	v_cmp_gt_i32_e64 s2, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s20, v3
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s2
	s_cbranch_execz .LBB0_12
; %bb.1:
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_12
; %bb.2:                                ; %.preheader86.lr.ph
	s_load_b256 s[12:19], s[0:1], 0x0
	v_ashrrev_i32_e32 v3, 31, v2
	s_mul_i32 s1, s11, s10
	s_cmp_gt_i32 s9, 0
	s_mul_i32 s6, s7, s6
	s_cselect_b32 s0, -1, 0
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_mul_lo_u32 v3, s7, v0
	s_cmp_gt_i32 s10, 0
	s_mul_i32 s5, s6, s5
	s_cselect_b32 s2, -1, 0
	s_cmp_gt_i32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, v4, v3, s3
	s_mul_i32 s3, s1, s9
	v_mul_lo_u32 v8, s3, v2
	s_cselect_b32 s3, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	v_mul_lo_u32 v9, s21, v3
	s_mov_b32 s16, 0
	global_load_b32 v7, v[5:6], off
.LBB0_3:                                ; %.preheader86
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v10, v7
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_11
; %bb.4:                                ; %.preheader85.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, v8
	v_mov_b32_e32 v10, v7
	s_mov_b32 s17, 0
.LBB0_5:                                ; %.preheader85
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_10
; %bb.6:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v14, v12
	s_mov_b32 s21, 0
.LBB0_7:                                ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_8 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v13
	v_mov_b32_e32 v5, v14
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s22, s11
	s_cbranch_vccnz .LBB0_9
.LBB0_8:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s22, s22, -1
	s_cmp_lg_u32 s22, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], 2, v[5:6]
	v_lshlrev_b64 v[17:18], 2, v[3:4]
	v_add_nc_u32_e32 v3, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s12, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v17, vcc_lo, s14, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s15, v18, vcc_lo
	global_load_b32 v4, v[15:16], off
	global_load_b32 v6, v[17:18], off
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v10, v4, v6 :: v_dual_add_nc_u32 v5, 1, v5
	s_cbranch_scc1 .LBB0_8
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_7 Depth=3
	v_add_nc_u32_e32 v14, s11, v14
	v_add_nc_u32_e32 v13, s7, v13
	s_add_i32 s21, s21, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s21, s10
	s_cbranch_scc1 .LBB0_7
.LBB0_10:                               ; %._crit_edge91
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v12, s1, v12
	v_add_nc_u32_e32 v11, s6, v11
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s9
	s_cbranch_scc1 .LBB0_5
.LBB0_11:                               ; %._crit_edge95
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mad_u64_u32 v[3:4], null, s16, s8, v[2:3]
	v_add_nc_u32_e32 v9, s5, v9
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s16, s4
	v_mad_u64_u32 v[4:5], null, v3, s20, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v4, s20, v[1:2]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	v_add_co_u32 v3, vcc_lo, s18, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_store_b32 v[3:4], v10, off
	s_cbranch_scc1 .LBB0_3
.LBB0_12:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11conv_kernelPfS_S_S_iiiiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11conv_kernelPfS_S_S_iiiiiiiiii, .Lfunc_end0-_Z11conv_kernelPfS_S_S_iiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 604
; NumSgprs: 25
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z13matmul_kernelPfS_S_iiii ; -- Begin function _Z13matmul_kernelPfS_S_iiii
	.globl	_Z13matmul_kernelPfS_S_iiii
	.p2align	8
	.type	_Z13matmul_kernelPfS_S_iiii,@function
_Z13matmul_kernelPfS_S_iiii:            ; @_Z13matmul_kernelPfS_S_iiii
; %bb.0:
	s_clause 0x3
	s_load_b32 s12, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s12, 16
	s_and_b32 s1, s12, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s0, v[3:4]
	v_mad_u64_u32 v[1:2], null, s14, s1, v[4:5]
	s_cmp_lt_i32 s5, 1
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s7, v1
	s_cbranch_scc1 .LBB1_11
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v2, 3, v3
	v_mul_lo_u32 v6, v0, s5
	v_lshl_add_u32 v7, v4, 2, 0x100
	v_lshlrev_b32_e32 v8, 5, v3
	s_mov_b32 s12, 0
	v_add_lshl_u32 v5, v2, v4, 2
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, 0x100, v5
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB1_6
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v11, s12, v4
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s5, v11
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v10, v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s8, v10
	v_add_co_ci_u32_e64 v11, s1, s9, v11, s1
	global_load_b32 v10, v[10:11], off
.LBB1_5:                                ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s13
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s12, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v10
	v_cmp_gt_i32_e64 s1, s6, v11
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s13, s1
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, s7, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[10:11], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s10, v10
	v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
	global_load_b32 v12, v[10:11], off
.LBB1_8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_mov_b32_e32 v10, v7
	s_mov_b32 s1, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_9:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, s1, v8
	s_add_i32 s1, s1, 4
	ds_load_b32 v12, v10
	ds_load_b32 v11, v11
	v_add_nc_u32_e32 v10, 32, v10
	s_cmp_eq_u32 s1, 32
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v11, v12
	s_cbranch_scc0 .LBB1_9
; %bb.10:                               ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s12, s12, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s12, s5
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_2
	s_branch .LBB1_12
.LBB1_11:
	v_mov_b32_e32 v2, 0
.LBB1_12:                               ; %._crit_edge
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s0, s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_14
; %bb.13:
	v_mad_u64_u32 v[3:4], null, v0, s7, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13matmul_kernelPfS_S_iiii
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13matmul_kernelPfS_S_iiii, .Lfunc_end1-_Z13matmul_kernelPfS_S_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11conv_kernelPfS_S_S_iiiiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z11conv_kernelPfS_S_S_iiiiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 512
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13matmul_kernelPfS_S_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13matmul_kernelPfS_S_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
