#include "includes.h"
__device__ void Device_FloodFillZPlane(int zPlane, int L, int M, int N, unsigned char* vol)
{
long idx, idxS, idxN, ts;
bool anyChange = false;
int x, y;

ts = L*M*N;
// set point (0,0) to OUTSIZE_1
idx = zPlane*L*M /* + 0*L + 0 */;
vol[idx] = OUTSIDE_1;

anyChange = true;
while(anyChange) {

anyChange = false;
// loop from left to right and top to bottom
for(x=0; x < L; x++) {
for(y=0; y < M; y++) {
idxS = idx + y*L + x;
// if the point is set to OUTSIDE_1, the set all empty neightbors
// to OUTSIDE_1
if(vol[idxS] == OUTSIDE_1) {

idxN = idxS + L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS + 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}
}
}
}

if(anyChange) {
// same loop but bottom to top and right to left
anyChange = false;
// loop from left to right and top to bottom
for(x=L-1; x >=0; x--) {
for(y=M-1; y >=0; y--) {
idxS = idx + y*L + x;
// if the point is set to OUTSIDE_1, the set all empty neightbors
// to OUTSIDE_1
if(vol[idxS] == OUTSIDE_1) {

idxN = idxS + L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS + 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}
}
}
}
}
}


}
__global__ void kernel_for_z_planes(unsigned char *d_vol,int L,int M,int N)
{
Device_FloodFillZPlane(threadIdx.x,L,M,N,d_vol);
}
	.file	"tmpxft_00333919_00000000-6_kernel_for_z_planes.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z22Device_FloodFillZPlaneiiiiPh
	.type	_Z22Device_FloodFillZPlaneiiiiPh, @function
_Z22Device_FloodFillZPlaneiiiiPh:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z22Device_FloodFillZPlaneiiiiPh, .-_Z22Device_FloodFillZPlaneiiiiPh
	.globl	_Z42__device_stub__Z19kernel_for_z_planesPhiiiPhiii
	.type	_Z42__device_stub__Z19kernel_for_z_planesPhiiiPhiii, @function
_Z42__device_stub__Z19kernel_for_z_planesPhiiiPhiii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19kernel_for_z_planesPhiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z42__device_stub__Z19kernel_for_z_planesPhiiiPhiii, .-_Z42__device_stub__Z19kernel_for_z_planesPhiiiPhiii
	.globl	_Z19kernel_for_z_planesPhiii
	.type	_Z19kernel_for_z_planesPhiii, @function
_Z19kernel_for_z_planesPhiii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z19kernel_for_z_planesPhiiiPhiii
	.cfi_endproc
.LFE2034:
	.size	_Z19kernel_for_z_planesPhiii, .-_Z19kernel_for_z_planesPhiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19kernel_for_z_planesPhiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19kernel_for_z_planesPhiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ void Device_FloodFillZPlane(int zPlane, int L, int M, int N, unsigned char* vol)
{
long idx, idxS, idxN, ts;
bool anyChange = false;
int x, y;

ts = L*M*N;
// set point (0,0) to OUTSIZE_1
idx = zPlane*L*M /* + 0*L + 0 */;
vol[idx] = OUTSIDE_1;

anyChange = true;
while(anyChange) {

anyChange = false;
// loop from left to right and top to bottom
for(x=0; x < L; x++) {
for(y=0; y < M; y++) {
idxS = idx + y*L + x;
// if the point is set to OUTSIDE_1, the set all empty neightbors
// to OUTSIDE_1
if(vol[idxS] == OUTSIDE_1) {

idxN = idxS + L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS + 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}
}
}
}

if(anyChange) {
// same loop but bottom to top and right to left
anyChange = false;
// loop from left to right and top to bottom
for(x=L-1; x >=0; x--) {
for(y=M-1; y >=0; y--) {
idxS = idx + y*L + x;
// if the point is set to OUTSIDE_1, the set all empty neightbors
// to OUTSIDE_1
if(vol[idxS] == OUTSIDE_1) {

idxN = idxS + L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - L;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS + 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}

idxN = idxS - 1;
if((idxN >= 0) && (idxN < ts) && (vol[idxN] == 0)) {
vol[idxN] = OUTSIDE_1;
anyChange = true;
}
}
}
}
}
}


}
__global__ void kernel_for_z_planes(unsigned char *d_vol,int L,int M,int N)
{
Device_FloodFillZPlane(threadIdx.x,L,M,N,d_vol);
}
	.text
	.file	"kernel_for_z_planes.hip"
	.globl	_Z34__device_stub__kernel_for_z_planesPhiii # -- Begin function _Z34__device_stub__kernel_for_z_planesPhiii
	.type	_Z34__device_stub__kernel_for_z_planesPhiii,@function
_Z34__device_stub__kernel_for_z_planesPhiii: # @_Z34__device_stub__kernel_for_z_planesPhiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19kernel_for_z_planesPhiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__kernel_for_z_planesPhiii, .Lfunc_end0-_Z34__device_stub__kernel_for_z_planesPhiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19kernel_for_z_planesPhiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19kernel_for_z_planesPhiii,@object # @_Z19kernel_for_z_planesPhiii
	.section	.rodata,"a",@progbits
	.globl	_Z19kernel_for_z_planesPhiii
	.p2align	3, 0x0
_Z19kernel_for_z_planesPhiii:
	.quad	_Z34__device_stub__kernel_for_z_planesPhiii
	.size	_Z19kernel_for_z_planesPhiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19kernel_for_z_planesPhiii"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__kernel_for_z_planesPhiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19kernel_for_z_planesPhiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19kernel_for_z_planesPhiii ; -- Begin function _Z19kernel_for_z_planesPhiii
	.globl	_Z19kernel_for_z_planesPhiii
	.p2align	8
	.type	_Z19kernel_for_z_planesPhiii,@function
_Z19kernel_for_z_planesPhiii:           ; @_Z19kernel_for_z_planesPhiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mov_b32_e32 v6, 2
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s5, s4
	s_mov_b32 s11, s4
	v_mul_lo_u32 v7, s0, v0
	s_mul_i32 s6, s0, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_ashr_i32 s7, s6, 31
	s_cmp_gt_i32 s4, 0
	s_cselect_b32 s10, -1, 0
	s_cmp_gt_i32 s5, 0
	v_ashrrev_i32_e32 v8, 31, v7
	s_cselect_b32 s12, -1, 0
	s_ashr_i32 s13, s4, 31
	s_cmp_lt_i32 s4, 1
	v_add_co_u32 v0, vcc_lo, s2, v7
	s_cselect_b32 s14, -1, 0
	s_add_u32 s8, s6, -1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v8, vcc_lo
	s_addc_u32 s9, s7, -1
	s_add_i32 s0, s5, -1
	s_add_i32 s15, s5, 1
	s_mul_i32 s16, s4, s0
	global_store_b8 v[0:1], v6, off
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;     Child Loop BB0_27 Depth 2
                                        ;       Child Loop BB0_29 Depth 3
	v_mov_b32_e32 v9, 0
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_25
; %bb.2:                                ; %.preheader124.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s17, 0
.LBB0_3:                                ; %.preheader124.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_5 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_24
; %bb.4:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	v_add_co_u32 v10, vcc_lo, s17, v7
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v8, vcc_lo
	s_mov_b32 s18, 0
	s_mov_b32 s19, s5
.LBB0_5:                                ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s18
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	global_load_u8 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 2, v4
	s_cbranch_execz .LBB0_23
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=3
	v_add_co_u32 v4, vcc_lo, v2, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i64_e32 vcc_lo, -1, v[4:5]
	v_cmp_gt_i64_e64 s0, s[6:7], v[4:5]
	s_and_b32 s21, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s21
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=3
	v_add_co_u32 v4, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v1, vcc_lo
	s_mov_b32 s21, exec_lo
	global_load_u8 v12, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v12
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[4:5], v6, off
.LBB0_9:                                ; %Flow37
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_10:                               ;   in Loop: Header=BB0_5 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_co_u32 v4, vcc_lo, v2, s11
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
	v_cmp_lt_i64_e32 vcc_lo, -1, v[4:5]
	v_cmp_gt_i64_e64 s0, s[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s21, vcc_lo, s0
	s_and_saveexec_b32 s0, s21
	s_cbranch_execz .LBB0_14
; %bb.11:                               ;   in Loop: Header=BB0_5 Depth=3
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_mov_b32 s21, exec_lo
	global_load_u8 v12, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v12
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_5 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[4:5], v6, off
.LBB0_13:                               ; %Flow36
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_14:                               ;   in Loop: Header=BB0_5 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_i64_e32 vcc_lo, -2, v[2:3]
	v_cmp_gt_i64_e64 s0, s[8:9], v[2:3]
	s_and_b32 s21, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s21
	s_cbranch_execz .LBB0_18
; %bb.15:                               ;   in Loop: Header=BB0_5 Depth=3
	global_load_u8 v4, v[0:1], off offset:1
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v4
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_5 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[0:1], v6, off offset:1
.LBB0_17:                               ; %Flow35
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_18:                               ;   in Loop: Header=BB0_5 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
	v_cmp_ge_i64_e64 s0, s[6:7], v[2:3]
	s_and_b32 s21, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s21
	s_cbranch_execz .LBB0_22
; %bb.19:                               ;   in Loop: Header=BB0_5 Depth=3
	global_load_u8 v2, v[0:1], off offset:-1
	s_mov_b32 s21, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v2
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_5 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[0:1], v6, off offset:-1
.LBB0_21:                               ; %Flow33
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_22:                               ; %Flow34
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_23:                               ; %Flow38
                                        ;   in Loop: Header=BB0_5 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
	s_add_i32 s19, s19, -1
	s_add_i32 s18, s18, s4
	s_cmp_lg_u32 s19, 0
	s_cbranch_scc1 .LBB0_5
.LBB0_24:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s4
	s_cbranch_scc1 .LBB0_3
.LBB0_25:                               ; %._crit_edge131.i
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 1, v9
	v_cmp_eq_u16_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	s_or_b32 s0, s14, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_50
; %bb.26:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v9, 0
	s_mov_b32 s18, s4
.LBB0_27:                               ; %.preheader.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_29 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_add_i32 s19, s18, -1
	s_cbranch_vccnz .LBB0_48
; %bb.28:                               ; %.lr.ph136.i
                                        ;   in Loop: Header=BB0_27 Depth=2
	v_add_co_u32 v10, vcc_lo, s19, v7
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v8, vcc_lo
	s_mov_b32 s20, s16
	s_mov_b32 s21, s15
.LBB0_29:                               ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_27 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_ashr_i32 s0, s20, 31
	v_add_co_u32 v2, vcc_lo, v10, s20
	v_add_co_ci_u32_e32 v3, vcc_lo, s0, v11, vcc_lo
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	global_load_u8 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 2, v4
	s_cbranch_execz .LBB0_47
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=3
	v_add_co_u32 v4, vcc_lo, v2, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i64_e32 vcc_lo, -1, v[4:5]
	v_cmp_gt_i64_e64 s0, s[6:7], v[4:5]
	s_and_b32 s23, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s23
	s_cbranch_execz .LBB0_34
; %bb.31:                               ;   in Loop: Header=BB0_29 Depth=3
	v_add_co_u32 v4, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v1, vcc_lo
	s_mov_b32 s23, exec_lo
	global_load_u8 v12, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v12
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_29 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[4:5], v6, off
.LBB0_33:                               ; %Flow27
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_34:                               ;   in Loop: Header=BB0_29 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_co_u32 v4, vcc_lo, v2, s11
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
	v_cmp_lt_i64_e32 vcc_lo, -1, v[4:5]
	v_cmp_gt_i64_e64 s0, s[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s23, vcc_lo, s0
	s_and_saveexec_b32 s0, s23
	s_cbranch_execz .LBB0_38
; %bb.35:                               ;   in Loop: Header=BB0_29 Depth=3
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_mov_b32 s23, exec_lo
	global_load_u8 v12, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v12
	s_cbranch_execz .LBB0_37
; %bb.36:                               ;   in Loop: Header=BB0_29 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[4:5], v6, off
.LBB0_37:                               ; %Flow26
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_38:                               ;   in Loop: Header=BB0_29 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_i64_e32 vcc_lo, -2, v[2:3]
	v_cmp_gt_i64_e64 s0, s[8:9], v[2:3]
	s_and_b32 s23, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s23
	s_cbranch_execz .LBB0_42
; %bb.39:                               ;   in Loop: Header=BB0_29 Depth=3
	global_load_u8 v4, v[0:1], off offset:1
	s_mov_b32 s23, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v4
	s_cbranch_execz .LBB0_41
; %bb.40:                               ;   in Loop: Header=BB0_29 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[0:1], v6, off offset:1
.LBB0_41:                               ; %Flow25
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_42:                               ;   in Loop: Header=BB0_29 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
	v_cmp_ge_i64_e64 s0, s[6:7], v[2:3]
	s_and_b32 s23, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s23
	s_cbranch_execz .LBB0_46
; %bb.43:                               ;   in Loop: Header=BB0_29 Depth=3
	global_load_u8 v2, v[0:1], off offset:-1
	s_mov_b32 s23, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v2
	s_cbranch_execz .LBB0_45
; %bb.44:                               ;   in Loop: Header=BB0_29 Depth=3
	v_mov_b32_e32 v9, 1
	global_store_b8 v[0:1], v6, off offset:-1
.LBB0_45:                               ; %Flow
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_46:                               ; %Flow24
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_47:                               ; %Flow28
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	s_add_i32 s21, s21, -1
	s_sub_i32 s20, s20, s4
	s_cmp_lt_u32 s21, 2
	s_cbranch_scc0 .LBB0_29
.LBB0_48:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_27 Depth=2
	s_cmp_lt_i32 s18, 2
	s_cbranch_scc1 .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_27 Depth=2
	s_mov_b32 s18, s19
	s_branch .LBB0_27
.LBB0_50:                               ; %Flow32
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_and_b32_e32 v0, 1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u16_e32 vcc_lo, 0, v0
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_1
; %bb.51:                               ; %_Z22Device_FloodFillZPlaneiiiiPh.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19kernel_for_z_planesPhiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19kernel_for_z_planesPhiii, .Lfunc_end0-_Z19kernel_for_z_planesPhiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1196
; NumSgprs: 26
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19kernel_for_z_planesPhiii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z19kernel_for_z_planesPhiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
