/**
 * block loading rho calculation. should be much faster
 * system('nvcc -ptx citydist_rho4.cu')
 * iA is multiple of CHUNK (16)
*/

#include <cuda_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC (1+6*2) // number of Channels
#define CHUNK 16 //previously defined as CHUNK
#define SINGLE_INF (3.402E+38)

/** Main entry point.
 * Works out where the current thread should read/write to global memory
 * and calls doIterations to do the actual work.
 * Step through one B at a time
 */
__global__ void citydist_sorted_delta(float const *A, unsigned int const *I, float *D, unsigned int *N, int const nA, int const nneigh, int const nC){
    // int iA = blockIdx.x * CHUNK;    
    int iA = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK;
    int iA1;
    int tx = threadIdx.x;
    float vr_minDist1[CHUNK];
    unsigned int vi_minIdx1[CHUNK];
    __shared__ unsigned int svi_I_A1[CHUNK];
    __shared__ float smr_A1[NC][CHUNK];
    __shared__ float smr_delta1[NTHREADS][CHUNK];
    __shared__ unsigned int smi_nneigh1[NTHREADS][CHUNK]; 
    
    // cache A
    int iC = tx;    
    if (iC < nC){ //use tx as iC
        for (iA1 = 0; iA1 < CHUNK; ++iA1){
            if (iA + iA1 < nA){
                smr_A1[iC][iA1] = A[iC + (iA+iA1)*nC];
            }else{
                smr_A1[iC][iA1] = SINGLE_INF;
            }   
        }
    }
    
    iA1 = tx; // batch index
    if (iA1 < CHUNK){
        if (iA + iA1 < nA){
            svi_I_A1[iA1] = I[iA + iA1];  
        }else{
            svi_I_A1[iA1] = nA + 1;  // out of range
        }
    }
    for (iA1 = 0; iA1 < CHUNK; ++iA1){
        vr_minDist1[iA1] = SINGLE_INF;
        vi_minIdx1[iA1] = iA + iA1;
    }    
    __syncthreads();

    // fill in the shared memory A
    int iB_min = MAX(iA - nneigh, 0);
    int iB_max = MIN(iA + nneigh + CHUNK - 1, nA-1);
    if (nneigh==0){
        iB_min = 0; 
        iB_max = nA-1;
    }      
    int iB = iB_min + tx;  
    while (iB <= iB_max){
        float vr_dist1[CHUNK];
        for (iA1 = 0; iA1 < CHUNK; ++iA1) vr_dist1[iA1] = 0.0f;
        for (iC = 0; iC < nC; ++iC){
            float Btemp = A[iC + iB*nC];
            for (iA1 = 0; iA1 < CHUNK; ++iA1){
                float temp = Btemp - smr_A1[iC][iA1];
                vr_dist1[iA1] += ABS(temp);
            }            
        }          
        unsigned int IiB = I[iB];
        for (iA1 = 0; iA1 < CHUNK; ++iA1){            
            if (vr_dist1[iA1] < vr_minDist1[iA1]){
                if (IiB < svi_I_A1[iA1]){                
            //if (vr_dist1[iA1] < vr_minDist1[iA1] && vr_dist1[iA1]>0){
                //if (IiB < svi_I_A1[iA1] && iB != iA+iA1){
                    int dab = ABS(iA + iA1 - iB);
                    if (dab <= nneigh || nneigh==0){
                        vr_minDist1[iA1] = vr_dist1[iA1];
                        vi_minIdx1[iA1] = iB;
                    }
                }
            }
        }
        iB += blockDim.x;
    } // while
    
    // collect result from each thread
    for (iA1 = 0; iA1 < CHUNK; ++iA1){        
        smr_delta1[tx][iA1] = vr_minDist1[iA1];
        smi_nneigh1[tx][iA1] = vi_minIdx1[iA1];
    }
    __syncthreads();    
    
    // final count    
    iA1 = tx;
    if (iA1 < CHUNK && iA + iA1 < nA){
        float minDist1 = SINGLE_INF;
        unsigned int minIdx1 = iA + iA1;
        for (int tx1=0; tx1<blockDim.x; ++tx1){
            if (smr_delta1[tx1][iA1] < minDist1){
                minDist1 = smr_delta1[tx1][iA1];
                minIdx1 = smi_nneigh1[tx1][iA1];
            }
        }
        D[iA + iA1] = sqrtf(minDist1);
        N[iA + iA1] = minIdx1;        
    }

} // func
	.file	"tmpxft_002bfc8f_00000000-6_citydist_sorted_delta.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z21citydist_sorted_deltaPKfPKjPfPjiiiPKfPKjPfPjiii
	.type	_Z52__device_stub__Z21citydist_sorted_deltaPKfPKjPfPjiiiPKfPKjPfPjiii, @function
_Z52__device_stub__Z21citydist_sorted_deltaPKfPKjPfPjiiiPKfPKjPfPjiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21citydist_sorted_deltaPKfPKjPfPjiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z52__device_stub__Z21citydist_sorted_deltaPKfPKjPfPjiiiPKfPKjPfPjiii, .-_Z52__device_stub__Z21citydist_sorted_deltaPKfPKjPfPjiiiPKfPKjPfPjiii
	.globl	_Z21citydist_sorted_deltaPKfPKjPfPjiii
	.type	_Z21citydist_sorted_deltaPKfPKjPfPjiii, @function
_Z21citydist_sorted_deltaPKfPKjPfPjiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z21citydist_sorted_deltaPKfPKjPfPjiiiPKfPKjPfPjiii
	.cfi_endproc
.LFE2033:
	.size	_Z21citydist_sorted_deltaPKfPKjPfPjiii, .-_Z21citydist_sorted_deltaPKfPKjPfPjiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21citydist_sorted_deltaPKfPKjPfPjiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21citydist_sorted_deltaPKfPKjPfPjiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * block loading rho calculation. should be much faster
 * system('nvcc -ptx citydist_rho4.cu')
 * iA is multiple of CHUNK (16)
*/

#include <hip/hip_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC (1+6*2) // number of Channels
#define CHUNK 16 //previously defined as CHUNK
#define SINGLE_INF (3.402E+38)

/** Main entry point.
 * Works out where the current thread should read/write to global memory
 * and calls doIterations to do the actual work.
 * Step through one B at a time
 */
__global__ void citydist_sorted_delta(float const *A, unsigned int const *I, float *D, unsigned int *N, int const nA, int const nneigh, int const nC){
    // int iA = blockIdx.x * CHUNK;    
    int iA = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK;
    int iA1;
    int tx = threadIdx.x;
    float vr_minDist1[CHUNK];
    unsigned int vi_minIdx1[CHUNK];
    __shared__ unsigned int svi_I_A1[CHUNK];
    __shared__ float smr_A1[NC][CHUNK];
    __shared__ float smr_delta1[NTHREADS][CHUNK];
    __shared__ unsigned int smi_nneigh1[NTHREADS][CHUNK]; 
    
    // cache A
    int iC = tx;    
    if (iC < nC){ //use tx as iC
        for (iA1 = 0; iA1 < CHUNK; ++iA1){
            if (iA + iA1 < nA){
                smr_A1[iC][iA1] = A[iC + (iA+iA1)*nC];
            }else{
                smr_A1[iC][iA1] = SINGLE_INF;
            }   
        }
    }
    
    iA1 = tx; // batch index
    if (iA1 < CHUNK){
        if (iA + iA1 < nA){
            svi_I_A1[iA1] = I[iA + iA1];  
        }else{
            svi_I_A1[iA1] = nA + 1;  // out of range
        }
    }
    for (iA1 = 0; iA1 < CHUNK; ++iA1){
        vr_minDist1[iA1] = SINGLE_INF;
        vi_minIdx1[iA1] = iA + iA1;
    }    
    __syncthreads();

    // fill in the shared memory A
    int iB_min = MAX(iA - nneigh, 0);
    int iB_max = MIN(iA + nneigh + CHUNK - 1, nA-1);
    if (nneigh==0){
        iB_min = 0; 
        iB_max = nA-1;
    }      
    int iB = iB_min + tx;  
    while (iB <= iB_max){
        float vr_dist1[CHUNK];
        for (iA1 = 0; iA1 < CHUNK; ++iA1) vr_dist1[iA1] = 0.0f;
        for (iC = 0; iC < nC; ++iC){
            float Btemp = A[iC + iB*nC];
            for (iA1 = 0; iA1 < CHUNK; ++iA1){
                float temp = Btemp - smr_A1[iC][iA1];
                vr_dist1[iA1] += ABS(temp);
            }            
        }          
        unsigned int IiB = I[iB];
        for (iA1 = 0; iA1 < CHUNK; ++iA1){            
            if (vr_dist1[iA1] < vr_minDist1[iA1]){
                if (IiB < svi_I_A1[iA1]){                
            //if (vr_dist1[iA1] < vr_minDist1[iA1] && vr_dist1[iA1]>0){
                //if (IiB < svi_I_A1[iA1] && iB != iA+iA1){
                    int dab = ABS(iA + iA1 - iB);
                    if (dab <= nneigh || nneigh==0){
                        vr_minDist1[iA1] = vr_dist1[iA1];
                        vi_minIdx1[iA1] = iB;
                    }
                }
            }
        }
        iB += blockDim.x;
    } // while
    
    // collect result from each thread
    for (iA1 = 0; iA1 < CHUNK; ++iA1){        
        smr_delta1[tx][iA1] = vr_minDist1[iA1];
        smi_nneigh1[tx][iA1] = vi_minIdx1[iA1];
    }
    __syncthreads();    
    
    // final count    
    iA1 = tx;
    if (iA1 < CHUNK && iA + iA1 < nA){
        float minDist1 = SINGLE_INF;
        unsigned int minIdx1 = iA + iA1;
        for (int tx1=0; tx1<blockDim.x; ++tx1){
            if (smr_delta1[tx1][iA1] < minDist1){
                minDist1 = smr_delta1[tx1][iA1];
                minIdx1 = smi_nneigh1[tx1][iA1];
            }
        }
        D[iA + iA1] = sqrtf(minDist1);
        N[iA + iA1] = minIdx1;        
    }

} // func
	.text
	.file	"citydist_sorted_delta.hip"
	.globl	_Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii # -- Begin function _Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii
	.type	_Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii,@function
_Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii: # @_Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21citydist_sorted_deltaPKfPKjPfPjiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii, .Lfunc_end0-_Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21citydist_sorted_deltaPKfPKjPfPjiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21citydist_sorted_deltaPKfPKjPfPjiii,@object # @_Z21citydist_sorted_deltaPKfPKjPfPjiii
	.section	.rodata,"a",@progbits
	.globl	_Z21citydist_sorted_deltaPKfPKjPfPjiii
	.p2align	3, 0x0
_Z21citydist_sorted_deltaPKfPKjPfPjiii:
	.quad	_Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii
	.size	_Z21citydist_sorted_deltaPKfPKjPfPjiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21citydist_sorted_deltaPKfPKjPfPjiii"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__citydist_sorted_deltaPKfPKjPfPjiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21citydist_sorted_deltaPKfPKjPfPjiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21citydist_sorted_deltaPKfPKjPfPjiii ; -- Begin function _Z21citydist_sorted_deltaPKfPKjPfPjiii
	.globl	_Z21citydist_sorted_deltaPKfPKjPfPjiii
	.p2align	8
	.type	_Z21citydist_sorted_deltaPKfPKjPfPjiii,@function
_Z21citydist_sorted_deltaPKfPKjPfPjiii: ; @_Z21citydist_sorted_deltaPKfPKjPfPjiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s12, s[0:1], 0x30
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s12, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s1, s14
	s_lshl_b32 s15, s12, 4
	v_cmpx_gt_i32_e64 s18, v0
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.preheader171.preheader
	s_mul_i32 s12, s18, s12
	v_lshl_add_u32 v3, v0, 6, 0x4000
	v_lshl_add_u32 v1, s12, 4, v0
	s_mov_b32 s12, 0
	s_mov_b32 s13, s15
.LBB0_2:                                ; %.preheader171
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 0x7f7ff023
	s_cmp_ge_i32 s13, s16
	s_cbranch_scc1 .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v4, s12, v3
	v_add_nc_u32_e32 v1, s18, v1
	s_add_i32 s12, s12, 4
	s_add_i32 s13, s13, 1
	s_cmp_lg_u32 s12, 64
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
	s_cbranch_scc1 .LBB0_2
.LBB0_5:                                ; %Flow330
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_u32_e64 s0, 16, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_11
; %bb.6:
	v_or_b32_e32 v1, s15, v0
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $sgpr19
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 s16, v1
	s_xor_b32 s13, exec_lo, s13
; %bb.7:
	s_add_i32 s19, s16, 1
                                        ; implicit-def: $vgpr1
; %bb.8:                                ; %Flow327
	s_or_saveexec_b32 s13, s13
	v_mov_b32_e32 v2, s19
	s_xor_b32 exec_lo, exec_lo, s13
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB0_10:                               ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s13
	v_lshlrev_b32_e32 v1, 2, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2 offset:17216
.LBB0_11:                               ; %Flow328
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b32 s1, s1, 4
	s_lshl_b32 s12, s14, 4
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s1, s1, s12
	s_mov_b64 s[12:13], 0
.LBB0_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s14, s1, s12
	s_mov_b32 m0, s12
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s12, 16
	v_movreld_b32_e32 v1, 0x7f7ff023
	v_movreld_b32_e32 v17, s14
	s_cbranch_scc1 .LBB0_12
; %bb.13:
	s_add_i32 s12, s17, s15
	s_sub_i32 s13, s15, s17
	s_add_i32 s12, s12, 15
	s_add_i32 s19, s16, -1
	s_max_i32 s13, s13, 0
	s_min_i32 s20, s12, s19
	s_cmp_eq_u32 s17, 0
	s_mov_b32 s21, 0
	s_cselect_b32 s14, -1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s14, exec_lo
	s_cselect_b32 s12, 0, s13
	s_cselect_b32 s19, s19, s20
	v_add_nc_u32_e32 v81, s12, v0
	s_mov_b32 s20, exec_lo
	s_barrier
	buffer_gl0_inv
	v_cmpx_ge_i32_e64 s19, v81
	s_cbranch_execz .LBB0_30
; %bb.14:                               ; %.preheader170.lr.ph
	s_load_b32 s13, s[2:3], 0xc
	s_cmp_gt_i32 s18, 0
	v_mov_b32_e32 v84, 0
	s_cselect_b32 s22, -1, 0
	s_sub_i32 s1, s1, s12
                                        ; implicit-def: $vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_sub_nc_u32_e32 v83, s1, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s23, s13, 0xffff
	s_sub_i32 s24, 0, s23
.LBB0_15:                               ; %.preheader170
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_16 Depth 2
                                        ;     Child Loop BB0_19 Depth 2
                                        ;       Child Loop BB0_20 Depth 3
                                        ;     Child Loop BB0_23 Depth 2
	s_mov_b64 s[12:13], 0
.LBB0_16:                               ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 m0, s12
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_eq_u32 s12, 16
	v_movreld_b32_e32 v33, 0
	s_cbranch_scc0 .LBB0_16
; %bb.17:                               ; %.preheader169
                                        ;   in Loop: Header=BB0_15 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_22
; %bb.18:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_15 Depth=1
	v_mul_lo_u32 v49, v81, s18
	s_mov_b32 s1, 0
	s_movk_i32 s25, 0x4000
.LBB0_19:                               ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_20 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v50, s1, v49
	s_mov_b64 s[12:13], 0
	s_mov_b32 s26, s25
	v_ashrrev_i32_e32 v51, 31, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[50:51], 2, v[50:51]
	v_add_co_u32 v50, vcc_lo, s4, v50
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v51, vcc_lo, s5, v51, vcc_lo
	global_load_b32 v50, v[50:51], off
.LBB0_20:                               ;   Parent Loop BB0_15 Depth=1
                                        ;     Parent Loop BB0_19 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v51, s26
	s_mov_b32 m0, s12
	s_add_u32 s12, s12, 1
	v_movrels_b32_e32 v52, v33
	s_addc_u32 s13, s13, 0
	ds_load_b32 v51, v51
	s_add_i32 s26, s26, 4
	s_cmp_lg_u32 s12, 16
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v51, v50, v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0, v51
	v_cndmask_b32_e64 v51, v51, -v51, vcc_lo
	v_add_f32_e32 v51, v52, v51
	s_delay_alu instid0(VALU_DEP_1)
	v_movreld_b32_e32 v33, v51
	s_cbranch_scc1 .LBB0_20
; %bb.21:                               ;   in Loop: Header=BB0_19 Depth=2
	s_add_i32 s1, s1, 1
	s_add_i32 s25, s25, 64
	s_cmp_lg_u32 s1, s18
	s_cbranch_scc1 .LBB0_19
.LBB0_22:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_15 Depth=1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v82, 31, v81
	s_mov_b64 s[12:13], 0
	s_movk_i32 s1, 0x4340
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[49:50], 2, v[81:82]
	v_add_co_u32 v49, vcc_lo, s6, v49
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v50, vcc_lo, s7, v50, vcc_lo
	global_load_b32 v82, v[49:50], off
.LBB0_23:                               ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 m0, s12
	s_mov_b32 s25, exec_lo
	v_movrels_b32_e32 v85, v33
	v_movrels_b32_e32 v49, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f32_e32 v85, v49
	s_cbranch_execz .LBB0_27
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=2
	v_mov_b32_e32 v49, s1
	s_mov_b32 s26, exec_lo
	ds_load_b32 v49, v49
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_lt_u32_e64 v82, v49
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_23 Depth=2
	v_add_nc_u32_e32 v86, s12, v83
	v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v61, v13
	v_dual_mov_b32 v63, v15 :: v_dual_mov_b32 v80, v32
	v_mov_b32_e32 v77, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v87, 0, v86
	v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v49, v1
	v_dual_mov_b32 v68, v20 :: v_dual_mov_b32 v65, v17
	v_max_i32_e32 v86, v86, v87
	s_mov_b32 m0, s12
	v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v59, v11
	v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v57, v9
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ge_i32_e32 vcc_lo, s17, v86
	v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v55, v7
	v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v53, v5
	s_or_b32 vcc_lo, s14, vcc_lo
	v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v51, v3
	v_dual_mov_b32 v50, v2 :: v_dual_mov_b32 v79, v31
	v_dual_mov_b32 v78, v30 :: v_dual_mov_b32 v75, v27
	v_dual_mov_b32 v76, v28 :: v_dual_mov_b32 v73, v25
	v_dual_mov_b32 v74, v26 :: v_dual_mov_b32 v71, v23
	v_dual_mov_b32 v72, v24 :: v_dual_mov_b32 v69, v21
	v_dual_mov_b32 v70, v22 :: v_dual_mov_b32 v67, v19
	v_mov_b32_e32 v66, v18
	v_movreld_b32_e32 v49, v85
	v_movreld_b32_e32 v65, v81
	v_dual_cndmask_b32 v31, v31, v79 :: v_dual_cndmask_b32 v32, v32, v80
	v_dual_cndmask_b32 v29, v29, v77 :: v_dual_cndmask_b32 v30, v30, v78
	v_dual_cndmask_b32 v27, v27, v75 :: v_dual_cndmask_b32 v28, v28, v76
	v_dual_cndmask_b32 v25, v25, v73 :: v_dual_cndmask_b32 v26, v26, v74
	v_dual_cndmask_b32 v23, v23, v71 :: v_dual_cndmask_b32 v24, v24, v72
	v_dual_cndmask_b32 v21, v21, v69 :: v_dual_cndmask_b32 v22, v22, v70
	v_dual_cndmask_b32 v19, v19, v67 :: v_dual_cndmask_b32 v20, v20, v68
	v_dual_cndmask_b32 v17, v17, v65 :: v_dual_cndmask_b32 v18, v18, v66
	v_dual_cndmask_b32 v15, v15, v63 :: v_dual_cndmask_b32 v16, v16, v64
	v_dual_cndmask_b32 v13, v13, v61 :: v_dual_cndmask_b32 v14, v14, v62
	v_dual_cndmask_b32 v11, v11, v59 :: v_dual_cndmask_b32 v12, v12, v60
	v_dual_cndmask_b32 v9, v9, v57 :: v_dual_cndmask_b32 v10, v10, v58
	v_dual_cndmask_b32 v7, v7, v55 :: v_dual_cndmask_b32 v8, v8, v56
	v_dual_cndmask_b32 v5, v5, v53 :: v_dual_cndmask_b32 v6, v6, v54
	v_dual_cndmask_b32 v3, v3, v51 :: v_dual_cndmask_b32 v4, v4, v52
	v_dual_cndmask_b32 v1, v1, v49 :: v_dual_cndmask_b32 v2, v2, v50
.LBB0_26:                               ; %Flow322
                                        ;   in Loop: Header=BB0_23 Depth=2
	s_or_b32 exec_lo, exec_lo, s26
.LBB0_27:                               ;   in Loop: Header=BB0_23 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s25
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_add_i32 s1, s1, 4
	s_cmp_lg_u32 s12, 16
	s_cbranch_scc1 .LBB0_23
; %bb.28:                               ;   in Loop: Header=BB0_15 Depth=1
	v_add_nc_u32_e32 v81, s23, v81
	v_add_co_u32 v83, s1, v83, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v84, s1, 0, v84, s1
	v_cmp_lt_i32_e32 vcc_lo, s19, v81
	s_or_b32 s21, vcc_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_15
; %bb.29:                               ; %Flow325
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_30:                               ; %Flow326
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
	v_lshlrev_b32_e32 v33, 6, v0
	s_mov_b64 s[4:5], 0
.LBB0_31:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 m0, s4
	s_add_u32 s4, s4, 1
	v_movrels_b32_e32 v34, v1
	v_movrels_b32_e32 v35, v17
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 16
	ds_store_2addr_stride64_b32 v33, v34, v35 offset1:32
	v_add_nc_u32_e32 v33, 4, v33
	s_cbranch_scc1 .LBB0_31
; %bb.32:
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_41
; %bb.33:
	v_or_b32_e32 v1, s15, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s16, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_41
; %bb.34:                               ; %.preheader
	s_load_b32 s0, s[2:3], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB0_39
; %bb.35:                               ; %.lr.ph196.preheader
	v_dual_mov_b32 v2, 0x7f7ff023 :: v_dual_lshlrev_b32 v3, 2, v0
	v_mov_b32_e32 v0, v1
.LBB0_36:                               ; %.lr.ph196
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v4, v3
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_f32_e32 v4, v2
	s_cbranch_execz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_36 Depth=1
	ds_load_b32 v0, v3 offset:8192
	v_mov_b32_e32 v2, v4
.LBB0_38:                               ;   in Loop: Header=BB0_36 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v3, 64, v3
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc0 .LBB0_36
	s_branch .LBB0_40
.LBB0_39:
	v_mov_b32_e32 v2, 0x7f7ff023
	v_mov_b32_e32 v0, v1
.LBB0_40:                               ; %Flow320
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_cndmask_b32_e32 v5, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v2, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, 1, v2
	v_add_nc_u32_e32 v3, -1, v2
	v_fma_f32 v7, -v4, v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v3, v2, v5
	v_cmp_ge_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v2, v2, v3, s0
	v_cmp_lt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v2, v4, s0
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_f32_e32 v4, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_cndmask_b32_e32 v6, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v6, v5, vcc_lo
	v_add_co_u32 v1, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	global_store_b32 v[3:4], v5, off
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v0, off
.LBB0_41:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21citydist_sorted_deltaPKfPKjPfPjiii
		.amdhsa_group_segment_fixed_size 17280
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 88
		.amdhsa_next_free_sgpr 27
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21citydist_sorted_deltaPKfPKjPfPjiii, .Lfunc_end0-_Z21citydist_sorted_deltaPKfPKjPfPjiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1652
; NumSgprs: 29
; NumVgprs: 88
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 17280 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 10
; NumSGPRsForWavesPerEU: 29
; NumVGPRsForWavesPerEU: 88
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 17280
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21citydist_sorted_deltaPKfPKjPfPjiii
    .private_segment_fixed_size: 0
    .sgpr_count:     29
    .sgpr_spill_count: 0
    .symbol:         _Z21citydist_sorted_deltaPKfPKjPfPjiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     88
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
