/*==========================================================================
                                MD5 KERNEL

* Copyright (c) 2008, NetSysLab at the University of British Columbia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*     * Redistributions of source code must retain the above copyright
*       notice, this list of conditions and the following disclaimer.
*     * Redistributions in binary form must reproduce the above copyright
*       notice, this list of conditions and the following disclaimer in the
*       documentation and/or other materials provided with the distribution.
*     * Neither the name of the University nor the
*       names of its contributors may be used to endorse or promote products
*       derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY NetSysLab ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NetSysLab BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

DESCRIPTION
  CPU version of the storeGPU library.


==========================================================================*/

/*==========================================================================

                                  INCLUDES

==========================================================================*/
#include <string.h>
#include <stdio.h>
#include "cust.h"

/*==========================================================================

                             DATA DECLARATIONS

==========================================================================*/

/*--------------------------------------------------------------------------
                              TYPE DEFINITIONS
--------------------------------------------------------------------------*/
typedef struct {
  unsigned long total[2];     /*!< number of bytes processed  */
  unsigned long state[4];     /*!< intermediate digest state  */
  unsigned char buffer[64];   /*!< data block being processed */
} md5_context;

/*--------------------------------------------------------------------------
                             FUNCTION PROTOTYPES
--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------
                                  CONSTANTS
--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------
                              GLOBAL VARIABLES
--------------------------------------------------------------------------*/

__device__
const unsigned char md5_padding[64] =
{
  0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};

/*--------------------------------------------------------------------------
                                    MACROS
--------------------------------------------------------------------------*/
// 32-bit integer manipulation macros (little endian)
#ifndef GET_UINT32_LE
#define GET_UINT32_LE(n,b,i)                            \
{                                                       \
    (n) = ( (unsigned long) (b)[(i)    ]       )        \
        | ( (unsigned long) (b)[(i) + 1] <<  8 )        \
        | ( (unsigned long) (b)[(i) + 2] << 16 )        \
        | ( (unsigned long) (b)[(i) + 3] << 24 );       \
}
#endif

#ifndef PUT_UINT32_LE
#define PUT_UINT32_LE(n,b,i)                            \
{                                                       \
    (b)[(i)    ] = (unsigned char) ( (n)       );       \
    (b)[(i) + 1] = (unsigned char) ( (n) >>  8 );       \
    (b)[(i) + 2] = (unsigned char) ( (n) >> 16 );       \
    (b)[(i) + 3] = (unsigned char) ( (n) >> 24 );       \
}
#endif

#ifdef FEATURE_SHARED_MEMORY
// current thread stride.
#define SHARED_MEMORY_INDEX(index) (32 * (index) + (threadIdx.x & 0x1F))
#endif /* FEATURE_SHARED_MEMORY */



/*==========================================================================

                                  FUNCTIONS

==========================================================================*/

/*--------------------------------------------------------------------------
                                    LOCAL FUNCTIONS
--------------------------------------------------------------------------*/


#ifndef FEATURE_SHARED_MEMORY
/*===========================================================================

FUNCTION <Name>

DESCRIPTION
  MD5 context setup

DEPENDENCIES
  <dep.>

RETURN VALUE
  <return>

===========================================================================*/
__device__
static void md5_starts( md5_context *ctx ) {
  ctx->total[0] = 0;
  ctx->total[1] = 0;
  
  ctx->state[0] = 0x67452301;
  ctx->state[1] = 0xEFCDAB89;
  ctx->state[2] = 0x98BADCFE;
  ctx->state[3] = 0x10325476;
}

/*===========================================================================

FUNCTION MD5_PROCESS

DESCRIPTION
  <Desc.>

DEPENDENCIES
  <dep.>

RETURN VALUE
  <return>

===========================================================================*/
__device__
static void md5_process( md5_context *ctx, unsigned char data[64] ) {

  unsigned long A, B, C, D;
  unsigned long *X = (unsigned long *)data;


  GET_UINT32_LE( X[ 0], data,  0 );
  GET_UINT32_LE( X[ 1], data,  4 );
  GET_UINT32_LE( X[ 2], data,  8 );
  GET_UINT32_LE( X[ 3], data, 12 );
  GET_UINT32_LE( X[ 4], data, 16 );
  GET_UINT32_LE( X[ 5], data, 20 );
  GET_UINT32_LE( X[ 6], data, 24 );
  GET_UINT32_LE( X[ 7], data, 28 );
  GET_UINT32_LE( X[ 8], data, 32 );
  GET_UINT32_LE( X[ 9], data, 36 );
  GET_UINT32_LE( X[10], data, 40 );
  GET_UINT32_LE( X[11], data, 44 );
  GET_UINT32_LE( X[12], data, 48 );
  GET_UINT32_LE( X[13], data, 52 );
  GET_UINT32_LE( X[14], data, 56 );
  GET_UINT32_LE( X[15], data, 60 );
  
#undef S
#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
  
#undef P
#define P(a,b,c,d,k,s,t) {                            \
    a += F(b,c,d) + X[k] + t; a = S(a,s) + b;         \
  }						      \
  
  A = ctx->state[0];
  B = ctx->state[1];
  C = ctx->state[2];
  D = ctx->state[3];
  
#define F(x,y,z) (z ^ (x & (y ^ z)))
  
  P( A, B, C, D,  0,  7, 0xD76AA478 );
  P( D, A, B, C,  1, 12, 0xE8C7B756 );
  P( C, D, A, B,  2, 17, 0x242070DB );
  P( B, C, D, A,  3, 22, 0xC1BDCEEE );
  P( A, B, C, D,  4,  7, 0xF57C0FAF );
  P( D, A, B, C,  5, 12, 0x4787C62A );
  P( C, D, A, B,  6, 17, 0xA8304613 );
  P( B, C, D, A,  7, 22, 0xFD469501 );
  P( A, B, C, D,  8,  7, 0x698098D8 );
  P( D, A, B, C,  9, 12, 0x8B44F7AF );
  P( C, D, A, B, 10, 17, 0xFFFF5BB1 );
  P( B, C, D, A, 11, 22, 0x895CD7BE );
  P( A, B, C, D, 12,  7, 0x6B901122 );
  P( D, A, B, C, 13, 12, 0xFD987193 );
  P( C, D, A, B, 14, 17, 0xA679438E );
  P( B, C, D, A, 15, 22, 0x49B40821 );
  
#undef F
  
#define F(x,y,z) (y ^ (z & (x ^ y)))
  
  P( A, B, C, D,  1,  5, 0xF61E2562 );
  P( D, A, B, C,  6,  9, 0xC040B340 );
  P( C, D, A, B, 11, 14, 0x265E5A51 );
  P( B, C, D, A,  0, 20, 0xE9B6C7AA );
  P( A, B, C, D,  5,  5, 0xD62F105D );
  P( D, A, B, C, 10,  9, 0x02441453 );
  P( C, D, A, B, 15, 14, 0xD8A1E681 );
  P( B, C, D, A,  4, 20, 0xE7D3FBC8 );
  P( A, B, C, D,  9,  5, 0x21E1CDE6 );
  P( D, A, B, C, 14,  9, 0xC33707D6 );
  P( C, D, A, B,  3, 14, 0xF4D50D87 );
  P( B, C, D, A,  8, 20, 0x455A14ED );
  P( A, B, C, D, 13,  5, 0xA9E3E905 );
  P( D, A, B, C,  2,  9, 0xFCEFA3F8 );
  P( C, D, A, B,  7, 14, 0x676F02D9 );
  P( B, C, D, A, 12, 20, 0x8D2A4C8A );
  
#undef F
  
#define F(x,y,z) (x ^ y ^ z)
  
  P( A, B, C, D,  5,  4, 0xFFFA3942 );
  P( D, A, B, C,  8, 11, 0x8771F681 );
  P( C, D, A, B, 11, 16, 0x6D9D6122 );
  P( B, C, D, A, 14, 23, 0xFDE5380C );
  P( A, B, C, D,  1,  4, 0xA4BEEA44 );
  P( D, A, B, C,  4, 11, 0x4BDECFA9 );
  P( C, D, A, B,  7, 16, 0xF6BB4B60 );
  P( B, C, D, A, 10, 23, 0xBEBFBC70 );
  P( A, B, C, D, 13,  4, 0x289B7EC6 );
  P( D, A, B, C,  0, 11, 0xEAA127FA );
  P( C, D, A, B,  3, 16, 0xD4EF3085 );
  P( B, C, D, A,  6, 23, 0x04881D05 );
  P( A, B, C, D,  9,  4, 0xD9D4D039 );
  P( D, A, B, C, 12, 11, 0xE6DB99E5 );
  P( C, D, A, B, 15, 16, 0x1FA27CF8 );
  P( B, C, D, A,  2, 23, 0xC4AC5665 );
  
#undef F
  
#define F(x,y,z) (y ^ (x | ~z))
  
  P( A, B, C, D,  0,  6, 0xF4292244 );
  P( D, A, B, C,  7, 10, 0x432AFF97 );
  P( C, D, A, B, 14, 15, 0xAB9423A7 );
  P( B, C, D, A,  5, 21, 0xFC93A039 );
  P( A, B, C, D, 12,  6, 0x655B59C3 );
  P( D, A, B, C,  3, 10, 0x8F0CCC92 );
  P( C, D, A, B, 10, 15, 0xFFEFF47D );
  P( B, C, D, A,  1, 21, 0x85845DD1 );
  P( A, B, C, D,  8,  6, 0x6FA87E4F );
  P( D, A, B, C, 15, 10, 0xFE2CE6E0 );
  P( C, D, A, B,  6, 15, 0xA3014314 );
  P( B, C, D, A, 13, 21, 0x4E0811A1 );
  P( A, B, C, D,  4,  6, 0xF7537E82 );
  P( D, A, B, C, 11, 10, 0xBD3AF235 );
  P( C, D, A, B,  2, 15, 0x2AD7D2BB );
  P( B, C, D, A,  9, 21, 0xEB86D391 );
  
#undef F
  
  ctx->state[0] += A;
  ctx->state[1] += B;
  ctx->state[2] += C;
  ctx->state[3] += D;
}

/*===========================================================================

FUNCTION MD5_UPDATE

DESCRIPTION
  MD5 process buffer

DEPENDENCIES
  <dep.>

RETURN VALUE
  <return>

===========================================================================*/
__device__
static void md5_update( md5_context *ctx, unsigned char *input, int ilen ) {
  int fill;
  unsigned long left;
  
  if( ilen <= 0 )
    return;
  
  left = ctx->total[0] & 0x3F;
  fill = 64 - left;
  
  ctx->total[0] += ilen;
  ctx->total[0] &= 0xFFFFFFFF;
  
  if( ctx->total[0] < (unsigned long) ilen )
    ctx->total[1]++;
  
  if( left && ilen >= fill ) {
    
    //<ELSN>
    /*memcpy( (void *) (ctx->buffer + left),
      (void *) input, fill );*/
    for (int i = 0; i < fill; i++) {
      ctx->buffer[i+left] = input[i];
    }
    //</ELSN>
    
    md5_process( ctx, ctx->buffer );
    input += fill;
    ilen  -= fill;
    left = 0;
  }
  
  while( ilen >= 64 ) {
    md5_process( ctx, input );
    input += 64;
    ilen  -= 64;
  }
  
  if( ilen > 0 ) {	
    
    //<ELSN>
    /*	memcpy( (void *) (ctx->buffer + left),
	(void *) input, ilen );*/
    for (int i = 0; i < ilen; i++) {
      ctx->buffer[i+left] = input[i];
    }
    //</ELSN>
    
  }
}

/*===========================================================================

FUNCTION MD5_FINISH

DESCRIPTION
  MD5 final digest

DEPENDENCIES
  None.

RETURN VALUE
  <return>

===========================================================================*/
__device__
void md5_finish( md5_context *ctx, unsigned char *output ) {

  unsigned long last, padn;
  unsigned long high, low;
  unsigned char msglen[8];
  
  high = ( ctx->total[0] >> 29 ) | ( ctx->total[1] <<  3 );
  low  = ( ctx->total[0] <<  3 );
  
  PUT_UINT32_LE( low,  msglen, 0 );
  PUT_UINT32_LE( high, msglen, 4 );
  
  last = ctx->total[0] & 0x3F;
  padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
  
  md5_update( ctx, (unsigned char *) md5_padding, padn );
  md5_update( ctx, msglen, 8 );
  

  PUT_UINT32_LE( ctx->state[0], output,  0 );
#ifndef FEATURE_REDUCED_HASH_SIZE
  PUT_UINT32_LE( ctx->state[1], output,  4 );
  PUT_UINT32_LE( ctx->state[2], output,  8 );
  PUT_UINT32_LE( ctx->state[3], output, 12 );
#endif
}

/*===========================================================================

FUNCTION MD5_INTERNAL

DESCRIPTION
  Does the real md5 algorithm

DEPENDENCIES
  None

RETURN VALUE
  output is the hash result

===========================================================================*/
__device__
static void md5_internal( unsigned char *input, int ilen, 
			  unsigned char *output ) {
  md5_context ctx;
  
  md5_starts( &ctx );
  md5_update( &ctx, input, ilen );
  md5_finish( &ctx, output );
  
}
#endif /* #ifndef FEATURE_SHARED_MEMORY */

#ifdef FEATURE_SHARED_MEMORY
/*===========================================================================

FUNCTION MD5_INTERNAL

DESCRIPTION
  Does the real md5 algorithm.

DEPENDENCIES
  None

RETURN VALUE
  output is the hash result

===========================================================================*/

__device__
static void md5_internal( unsigned int *input, unsigned int *sharedMemory, 
			  int chunkSize, unsigned char *output ) {

  /* Number of passes (512 bit blocks) we have to do */
  int numberOfPasses = chunkSize / 64 + 1;
  /* Used during the hashing process */
  unsigned long A, B, C, D;
  /* Needed to do the little endian stuff */
  unsigned char *data = (unsigned char *)sharedMemory;

  /* Will hold the hash value through the 
     intermediate stages of MD5 algorithm */
  unsigned int state0 = 0x67452301;
  unsigned int state1 = 0xEFCDAB89;
  unsigned int state2 = 0x98BADCFE;
  unsigned int state3 = 0x10325476;


  /* Used to cache the shared memory index calculations, but testing showed 
     that it has no performance effect. */
  int x0 = SHARED_MEMORY_INDEX(0);
  int x1 = SHARED_MEMORY_INDEX(1);
  int x2 = SHARED_MEMORY_INDEX(2);
  int x3 = SHARED_MEMORY_INDEX(3);
  int x4 = SHARED_MEMORY_INDEX(4);
  int x5 = SHARED_MEMORY_INDEX(5);
  int x6 = SHARED_MEMORY_INDEX(6);
  int x7 = SHARED_MEMORY_INDEX(7);
  int x8 = SHARED_MEMORY_INDEX(8);
  int x9 = SHARED_MEMORY_INDEX(9);
  int x10 = SHARED_MEMORY_INDEX(10);
  int x11 = SHARED_MEMORY_INDEX(11);
  int x12 = SHARED_MEMORY_INDEX(12);
  int x13 = SHARED_MEMORY_INDEX(13);
  int x14 = SHARED_MEMORY_INDEX(14);
  int x15 = SHARED_MEMORY_INDEX(15);

#undef GET_CACHED_INDEX
#define GET_CACHED_INDEX(index) (x##index)


  for( int index = 0 ; index < (numberOfPasses) ; index++ ) {

    /* Move data to the thread's shared memory space */
    sharedMemory[GET_CACHED_INDEX(0)] = input[0 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(1)] = input[1 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(2)] = input[2 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(3)] = input[3 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(4)] = input[4 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(5)] = input[5 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(6)] = input[6 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(7)] = input[7 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(8)] = input[8 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(9)] = input[9 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(10)] = input[10 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(11)] = input[11 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(12)] = input[12 + 16 * index];

    /* Testing the code with and without this if statement shows that
       it has no effect on performance. */
    if(index == numberOfPasses -1 ) {
      /* The last pass will contain the size of the chunk size (according to
	 official MD5 algorithm). */
      sharedMemory[GET_CACHED_INDEX(13)] = 0x00000080;
      sharedMemory[GET_CACHED_INDEX(14)] = chunkSize << 3;
      sharedMemory[GET_CACHED_INDEX(15)] = chunkSize >> 29;
    } else {
      sharedMemory[GET_CACHED_INDEX(13)] = input[13 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(14)] = input[14 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(15)] = input[15 + 16 * index];
    }

	   /* Get the little endian stuff done. */
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(0)], 
		   data, GET_CACHED_INDEX(0) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(1)], 
		   data, GET_CACHED_INDEX(1) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(2)], 
		   data, GET_CACHED_INDEX(2) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(3)], 
		   data, GET_CACHED_INDEX(3) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(4)], 
		   data, GET_CACHED_INDEX(4) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(5)], 
		   data, GET_CACHED_INDEX(5) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(6)], 
		   data, GET_CACHED_INDEX(6) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(7)], 
		   data, GET_CACHED_INDEX(7) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(8)], 
		   data, GET_CACHED_INDEX(8) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(9)], 
		   data, GET_CACHED_INDEX(9) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(10)], 
		   data, GET_CACHED_INDEX(10) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(11)], 
		   data, GET_CACHED_INDEX(11) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(12)], 
		   data, GET_CACHED_INDEX(12) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(13)], 
		   data, GET_CACHED_INDEX(13) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(14)], 
		   data, GET_CACHED_INDEX(14) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(15)], 
		   data, GET_CACHED_INDEX(15) * 4 );


    /* Start the MD5 permutations */
#undef S
#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
#undef P  
#define P(a,b,c,d,k,s,t) {						\
      a += F(b,c,d) + sharedMemory[GET_CACHED_INDEX(k)] + t; a = S(a,s) + b; \
    }									\
    
    A = state0;
    B = state1;
    C = state2;
    D = state3;
    
#undef F
    
#define F(x,y,z) (z ^ (x & (y ^ z)))
    
    P( A, B, C, D,  0,  7, 0xD76AA478 );
    P( D, A, B, C,  1, 12, 0xE8C7B756 );
    P( C, D, A, B,  2, 17, 0x242070DB );
    P( B, C, D, A,  3, 22, 0xC1BDCEEE );
    P( A, B, C, D,  4,  7, 0xF57C0FAF );
    P( D, A, B, C,  5, 12, 0x4787C62A );
    P( C, D, A, B,  6, 17, 0xA8304613 );
    P( B, C, D, A,  7, 22, 0xFD469501 );
    P( A, B, C, D,  8,  7, 0x698098D8 );
    P( D, A, B, C,  9, 12, 0x8B44F7AF );
    P( C, D, A, B, 10, 17, 0xFFFF5BB1 );
    P( B, C, D, A, 11, 22, 0x895CD7BE );
    P( A, B, C, D, 12,  7, 0x6B901122 );
    P( D, A, B, C, 13, 12, 0xFD987193 );
    P( C, D, A, B, 14, 17, 0xA679438E );
    P( B, C, D, A, 15, 22, 0x49B40821 );
    
#undef F
    
#define F(x,y,z) (y ^ (z & (x ^ y)))
    
    P( A, B, C, D,  1,  5, 0xF61E2562 );
    P( D, A, B, C,  6,  9, 0xC040B340 );
    P( C, D, A, B, 11, 14, 0x265E5A51 );
    P( B, C, D, A,  0, 20, 0xE9B6C7AA );
    P( A, B, C, D,  5,  5, 0xD62F105D );
    P( D, A, B, C, 10,  9, 0x02441453 );
    P( C, D, A, B, 15, 14, 0xD8A1E681 );
    P( B, C, D, A,  4, 20, 0xE7D3FBC8 );
    P( A, B, C, D,  9,  5, 0x21E1CDE6 );
    P( D, A, B, C, 14,  9, 0xC33707D6 );
    P( C, D, A, B,  3, 14, 0xF4D50D87 );
    P( B, C, D, A,  8, 20, 0x455A14ED );
    P( A, B, C, D, 13,  5, 0xA9E3E905 );
    P( D, A, B, C,  2,  9, 0xFCEFA3F8 );
    P( C, D, A, B,  7, 14, 0x676F02D9 );
    P( B, C, D, A, 12, 20, 0x8D2A4C8A );
    
#undef F
    
#define F(x,y,z) (x ^ y ^ z)
    
    P( A, B, C, D,  5,  4, 0xFFFA3942 );
    P( D, A, B, C,  8, 11, 0x8771F681 );
    P( C, D, A, B, 11, 16, 0x6D9D6122 );
    P( B, C, D, A, 14, 23, 0xFDE5380C );
    P( A, B, C, D,  1,  4, 0xA4BEEA44 );
    P( D, A, B, C,  4, 11, 0x4BDECFA9 );
    P( C, D, A, B,  7, 16, 0xF6BB4B60 );
    P( B, C, D, A, 10, 23, 0xBEBFBC70 );
    P( A, B, C, D, 13,  4, 0x289B7EC6 );
    P( D, A, B, C,  0, 11, 0xEAA127FA );
    P( C, D, A, B,  3, 16, 0xD4EF3085 );
    P( B, C, D, A,  6, 23, 0x04881D05 );
    P( A, B, C, D,  9,  4, 0xD9D4D039 );
    P( D, A, B, C, 12, 11, 0xE6DB99E5 );
    P( C, D, A, B, 15, 16, 0x1FA27CF8 );
    P( B, C, D, A,  2, 23, 0xC4AC5665 );
    
#undef F
    
#define F(x,y,z) (y ^ (x | ~z))
    
    P( A, B, C, D,  0,  6, 0xF4292244 );
    P( D, A, B, C,  7, 10, 0x432AFF97 );
    P( C, D, A, B, 14, 15, 0xAB9423A7 );
    P( B, C, D, A,  5, 21, 0xFC93A039 );
    P( A, B, C, D, 12,  6, 0x655B59C3 );
    P( D, A, B, C,  3, 10, 0x8F0CCC92 );
    P( C, D, A, B, 10, 15, 0xFFEFF47D );
    P( B, C, D, A,  1, 21, 0x85845DD1 );
    P( A, B, C, D,  8,  6, 0x6FA87E4F );
    P( D, A, B, C, 15, 10, 0xFE2CE6E0 );
    P( C, D, A, B,  6, 15, 0xA3014314 );
    P( B, C, D, A, 13, 21, 0x4E0811A1 );
    P( A, B, C, D,  4,  6, 0xF7537E82 );
    P( D, A, B, C, 11, 10, 0xBD3AF235 );
    P( C, D, A, B,  2, 15, 0x2AD7D2BB );
    P( B, C, D, A,  9, 21, 0xEB86D391 );
    
#undef F
    
    state0 += A;
    state1 += B;
    state2 += C;
    state3 += D;
  }

  /* Got the hash, store it in the output buffer. */
  PUT_UINT32_LE( state0, output,  0 );
#ifndef FEATURE_REDUCED_HASH_SIZE
  PUT_UINT32_LE( state1, output,  4 );
  PUT_UINT32_LE( state2, output,  8 );
  PUT_UINT32_LE( state3, output, 12 );
#endif
  
}

__device__
static void md5_internal_overlap( unsigned int *input, unsigned int *sharedMemory, 
			  int chunkSize, unsigned char *output ) {

  /* Number of passes (512 bit blocks) we have to do */
  int numberOfPasses = chunkSize / 64 + 1;
  /* Used during the hashing process */
  unsigned long A, B, C, D;
  /* Needed to do the little endian stuff */
  unsigned char *data = (unsigned char *)sharedMemory;
  // number of padding bytes.
  int numPadBytes = 0;
  int numPadInt = 0;
  //int numPadRemain = 0;

  /* Will hold the hash value through the 
     intermediate stages of MD5 algorithm */
  unsigned int state0 = 0x67452301;
  unsigned int state1 = 0xEFCDAB89;
  unsigned int state2 = 0x98BADCFE;
  unsigned int state3 = 0x10325476;


  /* Used to cache the shared memory index calculations, but testing showed 
     that it has no performance effect. */
  int x0 = SHARED_MEMORY_INDEX(0);
  int x1 = SHARED_MEMORY_INDEX(1);
  int x2 = SHARED_MEMORY_INDEX(2);
  int x3 = SHARED_MEMORY_INDEX(3);
  int x4 = SHARED_MEMORY_INDEX(4);
  int x5 = SHARED_MEMORY_INDEX(5);
  int x6 = SHARED_MEMORY_INDEX(6);
  int x7 = SHARED_MEMORY_INDEX(7);
  int x8 = SHARED_MEMORY_INDEX(8);
  int x9 = SHARED_MEMORY_INDEX(9);
  int x10 = SHARED_MEMORY_INDEX(10);
  int x11 = SHARED_MEMORY_INDEX(11);
  int x12 = SHARED_MEMORY_INDEX(12);
  int x13 = SHARED_MEMORY_INDEX(13);
  int x14 = SHARED_MEMORY_INDEX(14);
  int x15 = SHARED_MEMORY_INDEX(15);

#undef GET_CACHED_INDEX
#define GET_CACHED_INDEX(index) (x##index)


  for( int index = 0 ; index < (numberOfPasses) ; index++ ) {
    
    if(index == numberOfPasses - 1 ) {
      
      numPadBytes = (64-12) - (chunkSize - (numberOfPasses-1)*64);
      numPadInt = numPadBytes/sizeof(int);
      /*numPadRemain = numPadBytes-numPadInt*sizeof(int);
      printf("\nLast loop chunkSize = %d, numberOfPasses= %d and \nnumPadBytes = %d, numPadInt =%d, numPadRemain = %d\n",
	     chunkSize,numberOfPasses,numPadBytes,numPadInt,numPadRemain);*/
      
      int i=0;
      for(i = 0 ; i < numPadInt ; i++){
	sharedMemory[SHARED_MEMORY_INDEX(13-i)] = 0;
      }

      int j=0;
      for(j=0;j<(16-3-numPadInt);j++){
	//printf("j= %d\n",j);
	sharedMemory[SHARED_MEMORY_INDEX(j)] = input[j + 16 * index];
      }
      
      
      /* The last pass will contain the size of the chunk size (according to
	 official MD5 algorithm). */
      sharedMemory[SHARED_MEMORY_INDEX(13-i)] = 0x00000080;
      //printf("the last one at %d\n",13-i);
      
      sharedMemory[GET_CACHED_INDEX(14)] = chunkSize << 3;
      sharedMemory[GET_CACHED_INDEX(15)] = chunkSize >> 29;
    } else {
      /* Move data to the thread's shared memory space */
      //printf("Not last loop\n");
      sharedMemory[GET_CACHED_INDEX(0)] = input[0 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(1)] = input[1 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(2)] = input[2 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(3)] = input[3 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(4)] = input[4 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(5)] = input[5 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(6)] = input[6 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(7)] = input[7 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(8)] = input[8 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(9)] = input[9 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(10)] = input[10 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(11)] = input[11 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(12)] = input[12 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(13)] = input[13 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(14)] = input[14 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(15)] = input[15 + 16 * index];
    }
    
    /* Get the little endian stuff done. */
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(0)], 
		   data, GET_CACHED_INDEX(0) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(1)], 
		   data, GET_CACHED_INDEX(1) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(2)], 
		   data, GET_CACHED_INDEX(2) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(3)], 
		   data, GET_CACHED_INDEX(3) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(4)], 
		   data, GET_CACHED_INDEX(4) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(5)], 
		   data, GET_CACHED_INDEX(5) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(6)], 
		   data, GET_CACHED_INDEX(6) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(7)], 
		   data, GET_CACHED_INDEX(7) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(8)], 
		   data, GET_CACHED_INDEX(8) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(9)], 
		   data, GET_CACHED_INDEX(9) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(10)], 
		   data, GET_CACHED_INDEX(10) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(11)], 
		   data, GET_CACHED_INDEX(11) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(12)], 
		   data, GET_CACHED_INDEX(12) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(13)], 
		   data, GET_CACHED_INDEX(13) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(14)], 
		   data, GET_CACHED_INDEX(14) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(15)], 
		   data, GET_CACHED_INDEX(15) * 4 );


    /* Start the MD5 permutations */
#undef S
#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
#undef P  
#define P(a,b,c,d,k,s,t) {						\
      a += F(b,c,d) + sharedMemory[GET_CACHED_INDEX(k)] + t; a = S(a,s) + b; \
    }									\
    
    A = state0;
    B = state1;
    C = state2;
    D = state3;
    
#undef F
    
#define F(x,y,z) (z ^ (x & (y ^ z)))
    
    P( A, B, C, D,  0,  7, 0xD76AA478 );
    P( D, A, B, C,  1, 12, 0xE8C7B756 );
    P( C, D, A, B,  2, 17, 0x242070DB );
    P( B, C, D, A,  3, 22, 0xC1BDCEEE );
    P( A, B, C, D,  4,  7, 0xF57C0FAF );
    P( D, A, B, C,  5, 12, 0x4787C62A );
    P( C, D, A, B,  6, 17, 0xA8304613 );
    P( B, C, D, A,  7, 22, 0xFD469501 );
    P( A, B, C, D,  8,  7, 0x698098D8 );
    P( D, A, B, C,  9, 12, 0x8B44F7AF );
    P( C, D, A, B, 10, 17, 0xFFFF5BB1 );
    P( B, C, D, A, 11, 22, 0x895CD7BE );
    P( A, B, C, D, 12,  7, 0x6B901122 );
    P( D, A, B, C, 13, 12, 0xFD987193 );
    P( C, D, A, B, 14, 17, 0xA679438E );
    P( B, C, D, A, 15, 22, 0x49B40821 );
    
#undef F
    
#define F(x,y,z) (y ^ (z & (x ^ y)))
    
    P( A, B, C, D,  1,  5, 0xF61E2562 );
    P( D, A, B, C,  6,  9, 0xC040B340 );
    P( C, D, A, B, 11, 14, 0x265E5A51 );
    P( B, C, D, A,  0, 20, 0xE9B6C7AA );
    P( A, B, C, D,  5,  5, 0xD62F105D );
    P( D, A, B, C, 10,  9, 0x02441453 );
    P( C, D, A, B, 15, 14, 0xD8A1E681 );
    P( B, C, D, A,  4, 20, 0xE7D3FBC8 );
    P( A, B, C, D,  9,  5, 0x21E1CDE6 );
    P( D, A, B, C, 14,  9, 0xC33707D6 );
    P( C, D, A, B,  3, 14, 0xF4D50D87 );
    P( B, C, D, A,  8, 20, 0x455A14ED );
    P( A, B, C, D, 13,  5, 0xA9E3E905 );
    P( D, A, B, C,  2,  9, 0xFCEFA3F8 );
    P( C, D, A, B,  7, 14, 0x676F02D9 );
    P( B, C, D, A, 12, 20, 0x8D2A4C8A );
    
#undef F
    
#define F(x,y,z) (x ^ y ^ z)
    
    P( A, B, C, D,  5,  4, 0xFFFA3942 );
    P( D, A, B, C,  8, 11, 0x8771F681 );
    P( C, D, A, B, 11, 16, 0x6D9D6122 );
    P( B, C, D, A, 14, 23, 0xFDE5380C );
    P( A, B, C, D,  1,  4, 0xA4BEEA44 );
    P( D, A, B, C,  4, 11, 0x4BDECFA9 );
    P( C, D, A, B,  7, 16, 0xF6BB4B60 );
    P( B, C, D, A, 10, 23, 0xBEBFBC70 );
    P( A, B, C, D, 13,  4, 0x289B7EC6 );
    P( D, A, B, C,  0, 11, 0xEAA127FA );
    P( C, D, A, B,  3, 16, 0xD4EF3085 );
    P( B, C, D, A,  6, 23, 0x04881D05 );
    P( A, B, C, D,  9,  4, 0xD9D4D039 );
    P( D, A, B, C, 12, 11, 0xE6DB99E5 );
    P( C, D, A, B, 15, 16, 0x1FA27CF8 );
    P( B, C, D, A,  2, 23, 0xC4AC5665 );
    
#undef F
    
#define F(x,y,z) (y ^ (x | ~z))
    
    P( A, B, C, D,  0,  6, 0xF4292244 );
    P( D, A, B, C,  7, 10, 0x432AFF97 );
    P( C, D, A, B, 14, 15, 0xAB9423A7 );
    P( B, C, D, A,  5, 21, 0xFC93A039 );
    P( A, B, C, D, 12,  6, 0x655B59C3 );
    P( D, A, B, C,  3, 10, 0x8F0CCC92 );
    P( C, D, A, B, 10, 15, 0xFFEFF47D );
    P( B, C, D, A,  1, 21, 0x85845DD1 );
    P( A, B, C, D,  8,  6, 0x6FA87E4F );
    P( D, A, B, C, 15, 10, 0xFE2CE6E0 );
    P( C, D, A, B,  6, 15, 0xA3014314 );
    P( B, C, D, A, 13, 21, 0x4E0811A1 );
    P( A, B, C, D,  4,  6, 0xF7537E82 );
    P( D, A, B, C, 11, 10, 0xBD3AF235 );
    P( C, D, A, B,  2, 15, 0x2AD7D2BB );
    P( B, C, D, A,  9, 21, 0xEB86D391 );
    
#undef F
    
    state0 += A;
    state1 += B;
    state2 += C;
    state3 += D;
  }

  /* Got the hash, store it in the output buffer. */
  PUT_UINT32_LE( state0, output,  0 );
#ifndef FEATURE_REDUCED_HASH_SIZE
  PUT_UINT32_LE( state1, output,  4 );
  PUT_UINT32_LE( state2, output,  8 );
  PUT_UINT32_LE( state3, output, 12 );
#endif
  
}
#endif

/*--------------------------------------------------------------------------
                                    GLOBAL FUNCTIONS
--------------------------------------------------------------------------*/

/*===========================================================================

FUNCTION MD5

DESCRIPTION
  Main md5 hash function

DEPENDENCIES
  GPU must be initialized

RETURN VALUE
  output: the hash result

===========================================================================*/
__global__
void md5( unsigned char *input, int chunkSize, int totalThreads,
          int padSize, unsigned char *scratch) {
  
  int threadIndex = threadIdx.x + blockDim.x * blockIdx.x;
  int chunkIndex = threadIndex * chunkSize;
  int hashIndex  = threadIndex * MD5_HASH_SIZE;

  if(threadIndex >= totalThreads)
    return;
  
  if ((threadIndex == (totalThreads - 1)) && (padSize > 0)) {
    for(int i = 0 ; i < padSize ; i++)
      input[chunkIndex + chunkSize - padSize + i] = 0;
  }


#ifdef FEATURE_SHARED_MEMORY
  
  __shared__ unsigned int sharedMemory[4 * 1024 - 32];
  
  // 512 words are allocated for every warp of 32 threads
  unsigned int *sharedMemoryIndex = sharedMemory + ((threadIdx.x >> 5) * 512);
  unsigned int *inputIndex = (unsigned int *)(input + chunkIndex);
  
  md5_internal(inputIndex, sharedMemoryIndex, chunkSize, 
	       scratch + hashIndex );

#else
  md5_internal(input + chunkIndex, chunkSize, scratch + hashIndex );
#endif /* FEATURE_SHARED_MEMORY */

}


__global__
void md5_overlap( unsigned char *input, int chunkSize, int offset,
		  int totalThreads, int padSize, unsigned char *output ) {

  int threadIndex = threadIdx.x + blockDim.x * blockIdx.x;
  int chunkIndex = threadIndex * offset;
  int hashIndex  = threadIndex * MD5_HASH_SIZE;


  if(threadIndex >= totalThreads)
    return;
  
  if ((threadIndex == (totalThreads - 1))) {
    chunkSize-= padSize;
  }


#ifdef FEATURE_SHARED_MEMORY
  
  __shared__ unsigned int sharedMemory[4 * 1024 - 32];
  
  unsigned int *sharedMemoryIndex = sharedMemory + ((threadIdx.x >> 5) * 512);
  unsigned int *inputIndex = (unsigned int *)(input + chunkIndex);
  
  md5_internal_overlap(inputIndex, sharedMemoryIndex, chunkSize, 
	       output + hashIndex );

#else
  md5_internal(input + chunkIndex, chunkSize, output + hashIndex );
#endif /* FEATURE_SHARED_MEMORY */


}


	.file	"tmpxft_002262e5_00000000-6_md5_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z27__device_stub__Z3md5PhiiiS_PhiiiS_
	.type	_Z27__device_stub__Z3md5PhiiiS_PhiiiS_, @function
_Z27__device_stub__Z3md5PhiiiS_PhiiiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3md5PhiiiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z27__device_stub__Z3md5PhiiiS_PhiiiS_, .-_Z27__device_stub__Z3md5PhiiiS_PhiiiS_
	.globl	_Z3md5PhiiiS_
	.type	_Z3md5PhiiiS_, @function
_Z3md5PhiiiS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3md5PhiiiS_PhiiiS_
	.cfi_endproc
.LFE2054:
	.size	_Z3md5PhiiiS_, .-_Z3md5PhiiiS_
	.globl	_Z37__device_stub__Z11md5_overlapPhiiiiS_PhiiiiS_
	.type	_Z37__device_stub__Z11md5_overlapPhiiiiS_PhiiiiS_, @function
_Z37__device_stub__Z11md5_overlapPhiiiiS_PhiiiiS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z11md5_overlapPhiiiiS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L8:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z37__device_stub__Z11md5_overlapPhiiiiS_PhiiiiS_, .-_Z37__device_stub__Z11md5_overlapPhiiiiS_PhiiiiS_
	.globl	_Z11md5_overlapPhiiiiS_
	.type	_Z11md5_overlapPhiiiiS_, @function
_Z11md5_overlapPhiiiiS_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z11md5_overlapPhiiiiS_PhiiiiS_
	.cfi_endproc
.LFE2056:
	.size	_Z11md5_overlapPhiiiiS_, .-_Z11md5_overlapPhiiiiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11md5_overlapPhiiiiS_"
.LC1:
	.string	"_Z3md5PhiiiS_"
.LC2:
	.string	"md5_padding"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11md5_overlapPhiiiiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3md5PhiiiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movl	$64, %r9d
	leaq	_ZL11md5_padding(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata
	.align 32
	.type	_ZL11md5_padding, @object
	.size	_ZL11md5_padding, 64
_ZL11md5_padding:
	.string	"\200"
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.string	""
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*==========================================================================
                                MD5 KERNEL

* Copyright (c) 2008, NetSysLab at the University of British Columbia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*     * Redistributions of source code must retain the above copyright
*       notice, this list of conditions and the following disclaimer.
*     * Redistributions in binary form must reproduce the above copyright
*       notice, this list of conditions and the following disclaimer in the
*       documentation and/or other materials provided with the distribution.
*     * Neither the name of the University nor the
*       names of its contributors may be used to endorse or promote products
*       derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY NetSysLab ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NetSysLab BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

DESCRIPTION
  CPU version of the storeGPU library.


==========================================================================*/

/*==========================================================================

                                  INCLUDES

==========================================================================*/

#include <hip/hip_runtime.h>
#include <string.h>
#include <stdio.h>
#include "cust.h"

/*==========================================================================

                             DATA DECLARATIONS

==========================================================================*/

/*--------------------------------------------------------------------------
                              TYPE DEFINITIONS
--------------------------------------------------------------------------*/
typedef struct {
  unsigned long total[2];     /*!< number of bytes processed  */
  unsigned long state[4];     /*!< intermediate digest state  */
  unsigned char buffer[64];   /*!< data block being processed */
} md5_context;

/*--------------------------------------------------------------------------
                             FUNCTION PROTOTYPES
--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------
                                  CONSTANTS
--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------
                              GLOBAL VARIABLES
--------------------------------------------------------------------------*/

__device__
const unsigned char md5_padding[64] =
{
  0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};

/*--------------------------------------------------------------------------
                                    MACROS
--------------------------------------------------------------------------*/
// 32-bit integer manipulation macros (little endian)
#ifndef GET_UINT32_LE
#define GET_UINT32_LE(n,b,i)                            \
{                                                       \
    (n) = ( (unsigned long) (b)[(i)    ]       )        \
        | ( (unsigned long) (b)[(i) + 1] <<  8 )        \
        | ( (unsigned long) (b)[(i) + 2] << 16 )        \
        | ( (unsigned long) (b)[(i) + 3] << 24 );       \
}
#endif

#ifndef PUT_UINT32_LE
#define PUT_UINT32_LE(n,b,i)                            \
{                                                       \
    (b)[(i)    ] = (unsigned char) ( (n)       );       \
    (b)[(i) + 1] = (unsigned char) ( (n) >>  8 );       \
    (b)[(i) + 2] = (unsigned char) ( (n) >> 16 );       \
    (b)[(i) + 3] = (unsigned char) ( (n) >> 24 );       \
}
#endif

#ifdef FEATURE_SHARED_MEMORY
// current thread stride.
#define SHARED_MEMORY_INDEX(index) (32 * (index) + (threadIdx.x & 0x1F))
#endif /* FEATURE_SHARED_MEMORY */



/*==========================================================================

                                  FUNCTIONS

==========================================================================*/

/*--------------------------------------------------------------------------
                                    LOCAL FUNCTIONS
--------------------------------------------------------------------------*/


#ifndef FEATURE_SHARED_MEMORY
/*===========================================================================

FUNCTION <Name>

DESCRIPTION
  MD5 context setup

DEPENDENCIES
  <dep.>

RETURN VALUE
  <return>

===========================================================================*/
__device__
static void md5_starts( md5_context *ctx ) {
  ctx->total[0] = 0;
  ctx->total[1] = 0;
  
  ctx->state[0] = 0x67452301;
  ctx->state[1] = 0xEFCDAB89;
  ctx->state[2] = 0x98BADCFE;
  ctx->state[3] = 0x10325476;
}

/*===========================================================================

FUNCTION MD5_PROCESS

DESCRIPTION
  <Desc.>

DEPENDENCIES
  <dep.>

RETURN VALUE
  <return>

===========================================================================*/
__device__
static void md5_process( md5_context *ctx, unsigned char data[64] ) {

  unsigned long A, B, C, D;
  unsigned long *X = (unsigned long *)data;


  GET_UINT32_LE( X[ 0], data,  0 );
  GET_UINT32_LE( X[ 1], data,  4 );
  GET_UINT32_LE( X[ 2], data,  8 );
  GET_UINT32_LE( X[ 3], data, 12 );
  GET_UINT32_LE( X[ 4], data, 16 );
  GET_UINT32_LE( X[ 5], data, 20 );
  GET_UINT32_LE( X[ 6], data, 24 );
  GET_UINT32_LE( X[ 7], data, 28 );
  GET_UINT32_LE( X[ 8], data, 32 );
  GET_UINT32_LE( X[ 9], data, 36 );
  GET_UINT32_LE( X[10], data, 40 );
  GET_UINT32_LE( X[11], data, 44 );
  GET_UINT32_LE( X[12], data, 48 );
  GET_UINT32_LE( X[13], data, 52 );
  GET_UINT32_LE( X[14], data, 56 );
  GET_UINT32_LE( X[15], data, 60 );
  
#undef S
#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
  
#undef P
#define P(a,b,c,d,k,s,t) {                            \
    a += F(b,c,d) + X[k] + t; a = S(a,s) + b;         \
  }						      \
  
  A = ctx->state[0];
  B = ctx->state[1];
  C = ctx->state[2];
  D = ctx->state[3];
  
#define F(x,y,z) (z ^ (x & (y ^ z)))
  
  P( A, B, C, D,  0,  7, 0xD76AA478 );
  P( D, A, B, C,  1, 12, 0xE8C7B756 );
  P( C, D, A, B,  2, 17, 0x242070DB );
  P( B, C, D, A,  3, 22, 0xC1BDCEEE );
  P( A, B, C, D,  4,  7, 0xF57C0FAF );
  P( D, A, B, C,  5, 12, 0x4787C62A );
  P( C, D, A, B,  6, 17, 0xA8304613 );
  P( B, C, D, A,  7, 22, 0xFD469501 );
  P( A, B, C, D,  8,  7, 0x698098D8 );
  P( D, A, B, C,  9, 12, 0x8B44F7AF );
  P( C, D, A, B, 10, 17, 0xFFFF5BB1 );
  P( B, C, D, A, 11, 22, 0x895CD7BE );
  P( A, B, C, D, 12,  7, 0x6B901122 );
  P( D, A, B, C, 13, 12, 0xFD987193 );
  P( C, D, A, B, 14, 17, 0xA679438E );
  P( B, C, D, A, 15, 22, 0x49B40821 );
  
#undef F
  
#define F(x,y,z) (y ^ (z & (x ^ y)))
  
  P( A, B, C, D,  1,  5, 0xF61E2562 );
  P( D, A, B, C,  6,  9, 0xC040B340 );
  P( C, D, A, B, 11, 14, 0x265E5A51 );
  P( B, C, D, A,  0, 20, 0xE9B6C7AA );
  P( A, B, C, D,  5,  5, 0xD62F105D );
  P( D, A, B, C, 10,  9, 0x02441453 );
  P( C, D, A, B, 15, 14, 0xD8A1E681 );
  P( B, C, D, A,  4, 20, 0xE7D3FBC8 );
  P( A, B, C, D,  9,  5, 0x21E1CDE6 );
  P( D, A, B, C, 14,  9, 0xC33707D6 );
  P( C, D, A, B,  3, 14, 0xF4D50D87 );
  P( B, C, D, A,  8, 20, 0x455A14ED );
  P( A, B, C, D, 13,  5, 0xA9E3E905 );
  P( D, A, B, C,  2,  9, 0xFCEFA3F8 );
  P( C, D, A, B,  7, 14, 0x676F02D9 );
  P( B, C, D, A, 12, 20, 0x8D2A4C8A );
  
#undef F
  
#define F(x,y,z) (x ^ y ^ z)
  
  P( A, B, C, D,  5,  4, 0xFFFA3942 );
  P( D, A, B, C,  8, 11, 0x8771F681 );
  P( C, D, A, B, 11, 16, 0x6D9D6122 );
  P( B, C, D, A, 14, 23, 0xFDE5380C );
  P( A, B, C, D,  1,  4, 0xA4BEEA44 );
  P( D, A, B, C,  4, 11, 0x4BDECFA9 );
  P( C, D, A, B,  7, 16, 0xF6BB4B60 );
  P( B, C, D, A, 10, 23, 0xBEBFBC70 );
  P( A, B, C, D, 13,  4, 0x289B7EC6 );
  P( D, A, B, C,  0, 11, 0xEAA127FA );
  P( C, D, A, B,  3, 16, 0xD4EF3085 );
  P( B, C, D, A,  6, 23, 0x04881D05 );
  P( A, B, C, D,  9,  4, 0xD9D4D039 );
  P( D, A, B, C, 12, 11, 0xE6DB99E5 );
  P( C, D, A, B, 15, 16, 0x1FA27CF8 );
  P( B, C, D, A,  2, 23, 0xC4AC5665 );
  
#undef F
  
#define F(x,y,z) (y ^ (x | ~z))
  
  P( A, B, C, D,  0,  6, 0xF4292244 );
  P( D, A, B, C,  7, 10, 0x432AFF97 );
  P( C, D, A, B, 14, 15, 0xAB9423A7 );
  P( B, C, D, A,  5, 21, 0xFC93A039 );
  P( A, B, C, D, 12,  6, 0x655B59C3 );
  P( D, A, B, C,  3, 10, 0x8F0CCC92 );
  P( C, D, A, B, 10, 15, 0xFFEFF47D );
  P( B, C, D, A,  1, 21, 0x85845DD1 );
  P( A, B, C, D,  8,  6, 0x6FA87E4F );
  P( D, A, B, C, 15, 10, 0xFE2CE6E0 );
  P( C, D, A, B,  6, 15, 0xA3014314 );
  P( B, C, D, A, 13, 21, 0x4E0811A1 );
  P( A, B, C, D,  4,  6, 0xF7537E82 );
  P( D, A, B, C, 11, 10, 0xBD3AF235 );
  P( C, D, A, B,  2, 15, 0x2AD7D2BB );
  P( B, C, D, A,  9, 21, 0xEB86D391 );
  
#undef F
  
  ctx->state[0] += A;
  ctx->state[1] += B;
  ctx->state[2] += C;
  ctx->state[3] += D;
}

/*===========================================================================

FUNCTION MD5_UPDATE

DESCRIPTION
  MD5 process buffer

DEPENDENCIES
  <dep.>

RETURN VALUE
  <return>

===========================================================================*/
__device__
static void md5_update( md5_context *ctx, unsigned char *input, int ilen ) {
  int fill;
  unsigned long left;
  
  if( ilen <= 0 )
    return;
  
  left = ctx->total[0] & 0x3F;
  fill = 64 - left;
  
  ctx->total[0] += ilen;
  ctx->total[0] &= 0xFFFFFFFF;
  
  if( ctx->total[0] < (unsigned long) ilen )
    ctx->total[1]++;
  
  if( left && ilen >= fill ) {
    
    //<ELSN>
    /*memcpy( (void *) (ctx->buffer + left),
      (void *) input, fill );*/
    for (int i = 0; i < fill; i++) {
      ctx->buffer[i+left] = input[i];
    }
    //</ELSN>
    
    md5_process( ctx, ctx->buffer );
    input += fill;
    ilen  -= fill;
    left = 0;
  }
  
  while( ilen >= 64 ) {
    md5_process( ctx, input );
    input += 64;
    ilen  -= 64;
  }
  
  if( ilen > 0 ) {	
    
    //<ELSN>
    /*	memcpy( (void *) (ctx->buffer + left),
	(void *) input, ilen );*/
    for (int i = 0; i < ilen; i++) {
      ctx->buffer[i+left] = input[i];
    }
    //</ELSN>
    
  }
}

/*===========================================================================

FUNCTION MD5_FINISH

DESCRIPTION
  MD5 final digest

DEPENDENCIES
  None.

RETURN VALUE
  <return>

===========================================================================*/
__device__
void md5_finish( md5_context *ctx, unsigned char *output ) {

  unsigned long last, padn;
  unsigned long high, low;
  unsigned char msglen[8];
  
  high = ( ctx->total[0] >> 29 ) | ( ctx->total[1] <<  3 );
  low  = ( ctx->total[0] <<  3 );
  
  PUT_UINT32_LE( low,  msglen, 0 );
  PUT_UINT32_LE( high, msglen, 4 );
  
  last = ctx->total[0] & 0x3F;
  padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
  
  md5_update( ctx, (unsigned char *) md5_padding, padn );
  md5_update( ctx, msglen, 8 );
  

  PUT_UINT32_LE( ctx->state[0], output,  0 );
#ifndef FEATURE_REDUCED_HASH_SIZE
  PUT_UINT32_LE( ctx->state[1], output,  4 );
  PUT_UINT32_LE( ctx->state[2], output,  8 );
  PUT_UINT32_LE( ctx->state[3], output, 12 );
#endif
}

/*===========================================================================

FUNCTION MD5_INTERNAL

DESCRIPTION
  Does the real md5 algorithm

DEPENDENCIES
  None

RETURN VALUE
  output is the hash result

===========================================================================*/
__device__
static void md5_internal( unsigned char *input, int ilen, 
			  unsigned char *output ) {
  md5_context ctx;
  
  md5_starts( &ctx );
  md5_update( &ctx, input, ilen );
  md5_finish( &ctx, output );
  
}
#endif /* #ifndef FEATURE_SHARED_MEMORY */

#ifdef FEATURE_SHARED_MEMORY
/*===========================================================================

FUNCTION MD5_INTERNAL

DESCRIPTION
  Does the real md5 algorithm.

DEPENDENCIES
  None

RETURN VALUE
  output is the hash result

===========================================================================*/

__device__
static void md5_internal( unsigned int *input, unsigned int *sharedMemory, 
			  int chunkSize, unsigned char *output ) {

  /* Number of passes (512 bit blocks) we have to do */
  int numberOfPasses = chunkSize / 64 + 1;
  /* Used during the hashing process */
  unsigned long A, B, C, D;
  /* Needed to do the little endian stuff */
  unsigned char *data = (unsigned char *)sharedMemory;

  /* Will hold the hash value through the 
     intermediate stages of MD5 algorithm */
  unsigned int state0 = 0x67452301;
  unsigned int state1 = 0xEFCDAB89;
  unsigned int state2 = 0x98BADCFE;
  unsigned int state3 = 0x10325476;


  /* Used to cache the shared memory index calculations, but testing showed 
     that it has no performance effect. */
  int x0 = SHARED_MEMORY_INDEX(0);
  int x1 = SHARED_MEMORY_INDEX(1);
  int x2 = SHARED_MEMORY_INDEX(2);
  int x3 = SHARED_MEMORY_INDEX(3);
  int x4 = SHARED_MEMORY_INDEX(4);
  int x5 = SHARED_MEMORY_INDEX(5);
  int x6 = SHARED_MEMORY_INDEX(6);
  int x7 = SHARED_MEMORY_INDEX(7);
  int x8 = SHARED_MEMORY_INDEX(8);
  int x9 = SHARED_MEMORY_INDEX(9);
  int x10 = SHARED_MEMORY_INDEX(10);
  int x11 = SHARED_MEMORY_INDEX(11);
  int x12 = SHARED_MEMORY_INDEX(12);
  int x13 = SHARED_MEMORY_INDEX(13);
  int x14 = SHARED_MEMORY_INDEX(14);
  int x15 = SHARED_MEMORY_INDEX(15);

#undef GET_CACHED_INDEX
#define GET_CACHED_INDEX(index) (x##index)


  for( int index = 0 ; index < (numberOfPasses) ; index++ ) {

    /* Move data to the thread's shared memory space */
    sharedMemory[GET_CACHED_INDEX(0)] = input[0 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(1)] = input[1 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(2)] = input[2 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(3)] = input[3 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(4)] = input[4 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(5)] = input[5 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(6)] = input[6 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(7)] = input[7 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(8)] = input[8 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(9)] = input[9 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(10)] = input[10 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(11)] = input[11 + 16 * index];
    sharedMemory[GET_CACHED_INDEX(12)] = input[12 + 16 * index];

    /* Testing the code with and without this if statement shows that
       it has no effect on performance. */
    if(index == numberOfPasses -1 ) {
      /* The last pass will contain the size of the chunk size (according to
	 official MD5 algorithm). */
      sharedMemory[GET_CACHED_INDEX(13)] = 0x00000080;
      sharedMemory[GET_CACHED_INDEX(14)] = chunkSize << 3;
      sharedMemory[GET_CACHED_INDEX(15)] = chunkSize >> 29;
    } else {
      sharedMemory[GET_CACHED_INDEX(13)] = input[13 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(14)] = input[14 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(15)] = input[15 + 16 * index];
    }

	   /* Get the little endian stuff done. */
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(0)], 
		   data, GET_CACHED_INDEX(0) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(1)], 
		   data, GET_CACHED_INDEX(1) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(2)], 
		   data, GET_CACHED_INDEX(2) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(3)], 
		   data, GET_CACHED_INDEX(3) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(4)], 
		   data, GET_CACHED_INDEX(4) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(5)], 
		   data, GET_CACHED_INDEX(5) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(6)], 
		   data, GET_CACHED_INDEX(6) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(7)], 
		   data, GET_CACHED_INDEX(7) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(8)], 
		   data, GET_CACHED_INDEX(8) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(9)], 
		   data, GET_CACHED_INDEX(9) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(10)], 
		   data, GET_CACHED_INDEX(10) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(11)], 
		   data, GET_CACHED_INDEX(11) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(12)], 
		   data, GET_CACHED_INDEX(12) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(13)], 
		   data, GET_CACHED_INDEX(13) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(14)], 
		   data, GET_CACHED_INDEX(14) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(15)], 
		   data, GET_CACHED_INDEX(15) * 4 );


    /* Start the MD5 permutations */
#undef S
#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
#undef P  
#define P(a,b,c,d,k,s,t) {						\
      a += F(b,c,d) + sharedMemory[GET_CACHED_INDEX(k)] + t; a = S(a,s) + b; \
    }									\
    
    A = state0;
    B = state1;
    C = state2;
    D = state3;
    
#undef F
    
#define F(x,y,z) (z ^ (x & (y ^ z)))
    
    P( A, B, C, D,  0,  7, 0xD76AA478 );
    P( D, A, B, C,  1, 12, 0xE8C7B756 );
    P( C, D, A, B,  2, 17, 0x242070DB );
    P( B, C, D, A,  3, 22, 0xC1BDCEEE );
    P( A, B, C, D,  4,  7, 0xF57C0FAF );
    P( D, A, B, C,  5, 12, 0x4787C62A );
    P( C, D, A, B,  6, 17, 0xA8304613 );
    P( B, C, D, A,  7, 22, 0xFD469501 );
    P( A, B, C, D,  8,  7, 0x698098D8 );
    P( D, A, B, C,  9, 12, 0x8B44F7AF );
    P( C, D, A, B, 10, 17, 0xFFFF5BB1 );
    P( B, C, D, A, 11, 22, 0x895CD7BE );
    P( A, B, C, D, 12,  7, 0x6B901122 );
    P( D, A, B, C, 13, 12, 0xFD987193 );
    P( C, D, A, B, 14, 17, 0xA679438E );
    P( B, C, D, A, 15, 22, 0x49B40821 );
    
#undef F
    
#define F(x,y,z) (y ^ (z & (x ^ y)))
    
    P( A, B, C, D,  1,  5, 0xF61E2562 );
    P( D, A, B, C,  6,  9, 0xC040B340 );
    P( C, D, A, B, 11, 14, 0x265E5A51 );
    P( B, C, D, A,  0, 20, 0xE9B6C7AA );
    P( A, B, C, D,  5,  5, 0xD62F105D );
    P( D, A, B, C, 10,  9, 0x02441453 );
    P( C, D, A, B, 15, 14, 0xD8A1E681 );
    P( B, C, D, A,  4, 20, 0xE7D3FBC8 );
    P( A, B, C, D,  9,  5, 0x21E1CDE6 );
    P( D, A, B, C, 14,  9, 0xC33707D6 );
    P( C, D, A, B,  3, 14, 0xF4D50D87 );
    P( B, C, D, A,  8, 20, 0x455A14ED );
    P( A, B, C, D, 13,  5, 0xA9E3E905 );
    P( D, A, B, C,  2,  9, 0xFCEFA3F8 );
    P( C, D, A, B,  7, 14, 0x676F02D9 );
    P( B, C, D, A, 12, 20, 0x8D2A4C8A );
    
#undef F
    
#define F(x,y,z) (x ^ y ^ z)
    
    P( A, B, C, D,  5,  4, 0xFFFA3942 );
    P( D, A, B, C,  8, 11, 0x8771F681 );
    P( C, D, A, B, 11, 16, 0x6D9D6122 );
    P( B, C, D, A, 14, 23, 0xFDE5380C );
    P( A, B, C, D,  1,  4, 0xA4BEEA44 );
    P( D, A, B, C,  4, 11, 0x4BDECFA9 );
    P( C, D, A, B,  7, 16, 0xF6BB4B60 );
    P( B, C, D, A, 10, 23, 0xBEBFBC70 );
    P( A, B, C, D, 13,  4, 0x289B7EC6 );
    P( D, A, B, C,  0, 11, 0xEAA127FA );
    P( C, D, A, B,  3, 16, 0xD4EF3085 );
    P( B, C, D, A,  6, 23, 0x04881D05 );
    P( A, B, C, D,  9,  4, 0xD9D4D039 );
    P( D, A, B, C, 12, 11, 0xE6DB99E5 );
    P( C, D, A, B, 15, 16, 0x1FA27CF8 );
    P( B, C, D, A,  2, 23, 0xC4AC5665 );
    
#undef F
    
#define F(x,y,z) (y ^ (x | ~z))
    
    P( A, B, C, D,  0,  6, 0xF4292244 );
    P( D, A, B, C,  7, 10, 0x432AFF97 );
    P( C, D, A, B, 14, 15, 0xAB9423A7 );
    P( B, C, D, A,  5, 21, 0xFC93A039 );
    P( A, B, C, D, 12,  6, 0x655B59C3 );
    P( D, A, B, C,  3, 10, 0x8F0CCC92 );
    P( C, D, A, B, 10, 15, 0xFFEFF47D );
    P( B, C, D, A,  1, 21, 0x85845DD1 );
    P( A, B, C, D,  8,  6, 0x6FA87E4F );
    P( D, A, B, C, 15, 10, 0xFE2CE6E0 );
    P( C, D, A, B,  6, 15, 0xA3014314 );
    P( B, C, D, A, 13, 21, 0x4E0811A1 );
    P( A, B, C, D,  4,  6, 0xF7537E82 );
    P( D, A, B, C, 11, 10, 0xBD3AF235 );
    P( C, D, A, B,  2, 15, 0x2AD7D2BB );
    P( B, C, D, A,  9, 21, 0xEB86D391 );
    
#undef F
    
    state0 += A;
    state1 += B;
    state2 += C;
    state3 += D;
  }

  /* Got the hash, store it in the output buffer. */
  PUT_UINT32_LE( state0, output,  0 );
#ifndef FEATURE_REDUCED_HASH_SIZE
  PUT_UINT32_LE( state1, output,  4 );
  PUT_UINT32_LE( state2, output,  8 );
  PUT_UINT32_LE( state3, output, 12 );
#endif
  
}

__device__
static void md5_internal_overlap( unsigned int *input, unsigned int *sharedMemory, 
			  int chunkSize, unsigned char *output ) {

  /* Number of passes (512 bit blocks) we have to do */
  int numberOfPasses = chunkSize / 64 + 1;
  /* Used during the hashing process */
  unsigned long A, B, C, D;
  /* Needed to do the little endian stuff */
  unsigned char *data = (unsigned char *)sharedMemory;
  // number of padding bytes.
  int numPadBytes = 0;
  int numPadInt = 0;
  //int numPadRemain = 0;

  /* Will hold the hash value through the 
     intermediate stages of MD5 algorithm */
  unsigned int state0 = 0x67452301;
  unsigned int state1 = 0xEFCDAB89;
  unsigned int state2 = 0x98BADCFE;
  unsigned int state3 = 0x10325476;


  /* Used to cache the shared memory index calculations, but testing showed 
     that it has no performance effect. */
  int x0 = SHARED_MEMORY_INDEX(0);
  int x1 = SHARED_MEMORY_INDEX(1);
  int x2 = SHARED_MEMORY_INDEX(2);
  int x3 = SHARED_MEMORY_INDEX(3);
  int x4 = SHARED_MEMORY_INDEX(4);
  int x5 = SHARED_MEMORY_INDEX(5);
  int x6 = SHARED_MEMORY_INDEX(6);
  int x7 = SHARED_MEMORY_INDEX(7);
  int x8 = SHARED_MEMORY_INDEX(8);
  int x9 = SHARED_MEMORY_INDEX(9);
  int x10 = SHARED_MEMORY_INDEX(10);
  int x11 = SHARED_MEMORY_INDEX(11);
  int x12 = SHARED_MEMORY_INDEX(12);
  int x13 = SHARED_MEMORY_INDEX(13);
  int x14 = SHARED_MEMORY_INDEX(14);
  int x15 = SHARED_MEMORY_INDEX(15);

#undef GET_CACHED_INDEX
#define GET_CACHED_INDEX(index) (x##index)


  for( int index = 0 ; index < (numberOfPasses) ; index++ ) {
    
    if(index == numberOfPasses - 1 ) {
      
      numPadBytes = (64-12) - (chunkSize - (numberOfPasses-1)*64);
      numPadInt = numPadBytes/sizeof(int);
      /*numPadRemain = numPadBytes-numPadInt*sizeof(int);
      printf("\nLast loop chunkSize = %d, numberOfPasses= %d and \nnumPadBytes = %d, numPadInt =%d, numPadRemain = %d\n",
	     chunkSize,numberOfPasses,numPadBytes,numPadInt,numPadRemain);*/
      
      int i=0;
      for(i = 0 ; i < numPadInt ; i++){
	sharedMemory[SHARED_MEMORY_INDEX(13-i)] = 0;
      }

      int j=0;
      for(j=0;j<(16-3-numPadInt);j++){
	//printf("j= %d\n",j);
	sharedMemory[SHARED_MEMORY_INDEX(j)] = input[j + 16 * index];
      }
      
      
      /* The last pass will contain the size of the chunk size (according to
	 official MD5 algorithm). */
      sharedMemory[SHARED_MEMORY_INDEX(13-i)] = 0x00000080;
      //printf("the last one at %d\n",13-i);
      
      sharedMemory[GET_CACHED_INDEX(14)] = chunkSize << 3;
      sharedMemory[GET_CACHED_INDEX(15)] = chunkSize >> 29;
    } else {
      /* Move data to the thread's shared memory space */
      //printf("Not last loop\n");
      sharedMemory[GET_CACHED_INDEX(0)] = input[0 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(1)] = input[1 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(2)] = input[2 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(3)] = input[3 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(4)] = input[4 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(5)] = input[5 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(6)] = input[6 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(7)] = input[7 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(8)] = input[8 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(9)] = input[9 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(10)] = input[10 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(11)] = input[11 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(12)] = input[12 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(13)] = input[13 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(14)] = input[14 + 16 * index];
      sharedMemory[GET_CACHED_INDEX(15)] = input[15 + 16 * index];
    }
    
    /* Get the little endian stuff done. */
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(0)], 
		   data, GET_CACHED_INDEX(0) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(1)], 
		   data, GET_CACHED_INDEX(1) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(2)], 
		   data, GET_CACHED_INDEX(2) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(3)], 
		   data, GET_CACHED_INDEX(3) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(4)], 
		   data, GET_CACHED_INDEX(4) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(5)], 
		   data, GET_CACHED_INDEX(5) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(6)], 
		   data, GET_CACHED_INDEX(6) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(7)], 
		   data, GET_CACHED_INDEX(7) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(8)], 
		   data, GET_CACHED_INDEX(8) * 4 );
    GET_UINT32_LE( sharedMemory[ GET_CACHED_INDEX(9)], 
		   data, GET_CACHED_INDEX(9) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(10)], 
		   data, GET_CACHED_INDEX(10) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(11)], 
		   data, GET_CACHED_INDEX(11) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(12)], 
		   data, GET_CACHED_INDEX(12) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(13)], 
		   data, GET_CACHED_INDEX(13) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(14)], 
		   data, GET_CACHED_INDEX(14) * 4 );
    GET_UINT32_LE( sharedMemory[GET_CACHED_INDEX(15)], 
		   data, GET_CACHED_INDEX(15) * 4 );


    /* Start the MD5 permutations */
#undef S
#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
#undef P  
#define P(a,b,c,d,k,s,t) {						\
      a += F(b,c,d) + sharedMemory[GET_CACHED_INDEX(k)] + t; a = S(a,s) + b; \
    }									\
    
    A = state0;
    B = state1;
    C = state2;
    D = state3;
    
#undef F
    
#define F(x,y,z) (z ^ (x & (y ^ z)))
    
    P( A, B, C, D,  0,  7, 0xD76AA478 );
    P( D, A, B, C,  1, 12, 0xE8C7B756 );
    P( C, D, A, B,  2, 17, 0x242070DB );
    P( B, C, D, A,  3, 22, 0xC1BDCEEE );
    P( A, B, C, D,  4,  7, 0xF57C0FAF );
    P( D, A, B, C,  5, 12, 0x4787C62A );
    P( C, D, A, B,  6, 17, 0xA8304613 );
    P( B, C, D, A,  7, 22, 0xFD469501 );
    P( A, B, C, D,  8,  7, 0x698098D8 );
    P( D, A, B, C,  9, 12, 0x8B44F7AF );
    P( C, D, A, B, 10, 17, 0xFFFF5BB1 );
    P( B, C, D, A, 11, 22, 0x895CD7BE );
    P( A, B, C, D, 12,  7, 0x6B901122 );
    P( D, A, B, C, 13, 12, 0xFD987193 );
    P( C, D, A, B, 14, 17, 0xA679438E );
    P( B, C, D, A, 15, 22, 0x49B40821 );
    
#undef F
    
#define F(x,y,z) (y ^ (z & (x ^ y)))
    
    P( A, B, C, D,  1,  5, 0xF61E2562 );
    P( D, A, B, C,  6,  9, 0xC040B340 );
    P( C, D, A, B, 11, 14, 0x265E5A51 );
    P( B, C, D, A,  0, 20, 0xE9B6C7AA );
    P( A, B, C, D,  5,  5, 0xD62F105D );
    P( D, A, B, C, 10,  9, 0x02441453 );
    P( C, D, A, B, 15, 14, 0xD8A1E681 );
    P( B, C, D, A,  4, 20, 0xE7D3FBC8 );
    P( A, B, C, D,  9,  5, 0x21E1CDE6 );
    P( D, A, B, C, 14,  9, 0xC33707D6 );
    P( C, D, A, B,  3, 14, 0xF4D50D87 );
    P( B, C, D, A,  8, 20, 0x455A14ED );
    P( A, B, C, D, 13,  5, 0xA9E3E905 );
    P( D, A, B, C,  2,  9, 0xFCEFA3F8 );
    P( C, D, A, B,  7, 14, 0x676F02D9 );
    P( B, C, D, A, 12, 20, 0x8D2A4C8A );
    
#undef F
    
#define F(x,y,z) (x ^ y ^ z)
    
    P( A, B, C, D,  5,  4, 0xFFFA3942 );
    P( D, A, B, C,  8, 11, 0x8771F681 );
    P( C, D, A, B, 11, 16, 0x6D9D6122 );
    P( B, C, D, A, 14, 23, 0xFDE5380C );
    P( A, B, C, D,  1,  4, 0xA4BEEA44 );
    P( D, A, B, C,  4, 11, 0x4BDECFA9 );
    P( C, D, A, B,  7, 16, 0xF6BB4B60 );
    P( B, C, D, A, 10, 23, 0xBEBFBC70 );
    P( A, B, C, D, 13,  4, 0x289B7EC6 );
    P( D, A, B, C,  0, 11, 0xEAA127FA );
    P( C, D, A, B,  3, 16, 0xD4EF3085 );
    P( B, C, D, A,  6, 23, 0x04881D05 );
    P( A, B, C, D,  9,  4, 0xD9D4D039 );
    P( D, A, B, C, 12, 11, 0xE6DB99E5 );
    P( C, D, A, B, 15, 16, 0x1FA27CF8 );
    P( B, C, D, A,  2, 23, 0xC4AC5665 );
    
#undef F
    
#define F(x,y,z) (y ^ (x | ~z))
    
    P( A, B, C, D,  0,  6, 0xF4292244 );
    P( D, A, B, C,  7, 10, 0x432AFF97 );
    P( C, D, A, B, 14, 15, 0xAB9423A7 );
    P( B, C, D, A,  5, 21, 0xFC93A039 );
    P( A, B, C, D, 12,  6, 0x655B59C3 );
    P( D, A, B, C,  3, 10, 0x8F0CCC92 );
    P( C, D, A, B, 10, 15, 0xFFEFF47D );
    P( B, C, D, A,  1, 21, 0x85845DD1 );
    P( A, B, C, D,  8,  6, 0x6FA87E4F );
    P( D, A, B, C, 15, 10, 0xFE2CE6E0 );
    P( C, D, A, B,  6, 15, 0xA3014314 );
    P( B, C, D, A, 13, 21, 0x4E0811A1 );
    P( A, B, C, D,  4,  6, 0xF7537E82 );
    P( D, A, B, C, 11, 10, 0xBD3AF235 );
    P( C, D, A, B,  2, 15, 0x2AD7D2BB );
    P( B, C, D, A,  9, 21, 0xEB86D391 );
    
#undef F
    
    state0 += A;
    state1 += B;
    state2 += C;
    state3 += D;
  }

  /* Got the hash, store it in the output buffer. */
  PUT_UINT32_LE( state0, output,  0 );
#ifndef FEATURE_REDUCED_HASH_SIZE
  PUT_UINT32_LE( state1, output,  4 );
  PUT_UINT32_LE( state2, output,  8 );
  PUT_UINT32_LE( state3, output, 12 );
#endif
  
}
#endif

/*--------------------------------------------------------------------------
                                    GLOBAL FUNCTIONS
--------------------------------------------------------------------------*/

/*===========================================================================

FUNCTION MD5

DESCRIPTION
  Main md5 hash function

DEPENDENCIES
  GPU must be initialized

RETURN VALUE
  output: the hash result

===========================================================================*/
__global__
void md5( unsigned char *input, int chunkSize, int totalThreads,
          int padSize, unsigned char *scratch) {
  
  int threadIndex = threadIdx.x + blockDim.x * blockIdx.x;
  int chunkIndex = threadIndex * chunkSize;
  int hashIndex  = threadIndex * MD5_HASH_SIZE;

  if(threadIndex >= totalThreads)
    return;
  
  if ((threadIndex == (totalThreads - 1)) && (padSize > 0)) {
    for(int i = 0 ; i < padSize ; i++)
      input[chunkIndex + chunkSize - padSize + i] = 0;
  }


#ifdef FEATURE_SHARED_MEMORY
  
  __shared__ unsigned int sharedMemory[4 * 1024 - 32];
  
  // 512 words are allocated for every warp of 32 threads
  unsigned int *sharedMemoryIndex = sharedMemory + ((threadIdx.x >> 5) * 512);
  unsigned int *inputIndex = (unsigned int *)(input + chunkIndex);
  
  md5_internal(inputIndex, sharedMemoryIndex, chunkSize, 
	       scratch + hashIndex );

#else
  md5_internal(input + chunkIndex, chunkSize, scratch + hashIndex );
#endif /* FEATURE_SHARED_MEMORY */

}


__global__
void md5_overlap( unsigned char *input, int chunkSize, int offset,
		  int totalThreads, int padSize, unsigned char *output ) {

  int threadIndex = threadIdx.x + blockDim.x * blockIdx.x;
  int chunkIndex = threadIndex * offset;
  int hashIndex  = threadIndex * MD5_HASH_SIZE;


  if(threadIndex >= totalThreads)
    return;
  
  if ((threadIndex == (totalThreads - 1))) {
    chunkSize-= padSize;
  }


#ifdef FEATURE_SHARED_MEMORY
  
  __shared__ unsigned int sharedMemory[4 * 1024 - 32];
  
  unsigned int *sharedMemoryIndex = sharedMemory + ((threadIdx.x >> 5) * 512);
  unsigned int *inputIndex = (unsigned int *)(input + chunkIndex);
  
  md5_internal_overlap(inputIndex, sharedMemoryIndex, chunkSize, 
	       output + hashIndex );

#else
  md5_internal(input + chunkIndex, chunkSize, output + hashIndex );
#endif /* FEATURE_SHARED_MEMORY */


}


	.text
	.file	"md5_kernel.hip"
	.globl	_Z18__device_stub__md5PhiiiS_   # -- Begin function _Z18__device_stub__md5PhiiiS_
	.type	_Z18__device_stub__md5PhiiiS_,@function
_Z18__device_stub__md5PhiiiS_:          # @_Z18__device_stub__md5PhiiiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3md5PhiiiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__md5PhiiiS_, .Lfunc_end0-_Z18__device_stub__md5PhiiiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__md5_overlapPhiiiiS_ # -- Begin function _Z26__device_stub__md5_overlapPhiiiiS_
	.type	_Z26__device_stub__md5_overlapPhiiiiS_,@function
_Z26__device_stub__md5_overlapPhiiiiS_: # @_Z26__device_stub__md5_overlapPhiiiiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11md5_overlapPhiiiiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__md5_overlapPhiiiiS_, .Lfunc_end1-_Z26__device_stub__md5_overlapPhiiiiS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3md5PhiiiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11md5_overlapPhiiiiS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3md5PhiiiS_,@object           # @_Z3md5PhiiiS_
	.section	.rodata,"a",@progbits
	.globl	_Z3md5PhiiiS_
	.p2align	3, 0x0
_Z3md5PhiiiS_:
	.quad	_Z18__device_stub__md5PhiiiS_
	.size	_Z3md5PhiiiS_, 8

	.type	_Z11md5_overlapPhiiiiS_,@object # @_Z11md5_overlapPhiiiiS_
	.globl	_Z11md5_overlapPhiiiiS_
	.p2align	3, 0x0
_Z11md5_overlapPhiiiiS_:
	.quad	_Z26__device_stub__md5_overlapPhiiiiS_
	.size	_Z11md5_overlapPhiiiiS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z3md5PhiiiS_"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11md5_overlapPhiiiiS_"
	.size	.L__unnamed_2, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__md5PhiiiS_
	.addrsig_sym _Z26__device_stub__md5_overlapPhiiiiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3md5PhiiiS_
	.addrsig_sym _Z11md5_overlapPhiiiiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3md5PhiiiS_           ; -- Begin function _Z3md5PhiiiS_
	.globl	_Z3md5PhiiiS_
	.p2align	8
	.type	_Z3md5PhiiiS_,@function
_Z3md5PhiiiS_:                          ; @_Z3md5PhiiiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s5, v11
	s_cbranch_execz .LBB0_11
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x0
	s_add_i32 s5, s5, -1
	s_cmp_gt_i32 s6, 0
	v_cmp_eq_u32_e32 vcc_lo, s5, v11
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, s5, vcc_lo
	s_and_saveexec_b32 s5, s7
	s_cbranch_execz .LBB0_4
; %bb.2:                                ; %.preheader
	v_mad_u64_u32 v[1:2], null, s4, v11, s[4:5]
	s_sub_i32 s6, 0, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s6
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v1, v2
	v_add_co_u32 v2, s6, v2, 1
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s6
	global_store_b8 v[4:5], v3, off
	s_cbranch_vccnz .LBB0_3
.LBB0_4:                                ; %Flow193
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v20, 0x67452301
	s_cmpk_lt_i32 s4, 0xffc1
	s_cbranch_scc1 .LBB0_10
; %bb.5:                                ; %.lr.ph.i
	v_mul_lo_u32 v1, v11, s4
	v_dual_mov_b32 v17, 0xefcdab89 :: v_dual_lshlrev_b32 v2, 6, v0
	v_and_b32_e32 v0, 31, v0
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(VALU_DEP_2)
	v_and_b32_e32 v2, 0xf800, v2
	v_mov_b32_e32 v14, 0x98badcfe
	v_ashrrev_i32_e32 v3, 31, v1
	v_dual_mov_b32 v15, 0 :: v_dual_lshlrev_b32 v0, 2, v0
	v_mov_b32_e32 v15, 0x10325476
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, v1, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_or_b32_e32 v19, v2, v0
	v_or_b32_e32 v4, 0x80, v0
	v_or_b32_e32 v5, 0x100, v0
	v_or_b32_e32 v6, 0x180, v0
	v_or_b32_e32 v7, 0x200, v0
	v_or_b32_e32 v8, 0x280, v0
	v_or_b32_e32 v9, 0x300, v0
	v_or_b32_e32 v10, 0x380, v0
	v_or_b32_e32 v27, 0x400, v0
	v_or_b32_e32 v28, 0x480, v0
	v_or_b32_e32 v29, 0x500, v0
	v_or_b32_e32 v30, 0x580, v0
	v_or_b32_e32 v31, 0x600, v0
	v_or_b32_e32 v32, 0x680, v0
	v_or_b32_e32 v33, 0x700, v0
	v_or_b32_e32 v34, 0x780, v0
	s_lshr_b32 s5, s5, 26
	v_add_co_u32 v12, vcc_lo, v1, 60
	s_add_i32 s5, s4, s5
	v_dual_mov_b32 v18, 0 :: v_dual_add_nc_u32 v23, v2, v7
	v_dual_mov_b32 v16, 0 :: v_dual_add_nc_u32 v27, v2, v27
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v3, vcc_lo
	v_dual_mov_b32 v20, 0x67452301 :: v_dual_add_nc_u32 v21, v2, v5
	v_add_nc_u32_e32 v16, v2, v0
	v_add_nc_u32_e32 v18, v2, v4
	v_add_nc_u32_e32 v22, v2, v6
	v_add_nc_u32_e32 v24, v2, v8
	v_add_nc_u32_e32 v25, v2, v9
	v_add_nc_u32_e32 v26, v2, v10
	v_add_nc_u32_e32 v28, v2, v28
	v_add_nc_u32_e32 v29, v2, v29
	v_add_nc_u32_e32 v30, v2, v30
	v_add_nc_u32_e32 v31, v2, v31
	v_add_nc_u32_e32 v32, v2, v32
	v_add_nc_u32_e32 v33, v2, v33
	v_add_nc_u32_e32 v34, v2, v34
	v_add_nc_u32_e32 v35, 0x400, v19
	s_ashr_i32 s5, s5, 6
	s_lshl_b32 s3, s4, 3
	s_sub_i32 s2, 0, s5
	s_ashr_i32 s4, s4, 29
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	s_clause 0x3
	global_load_b128 v[4:7], v[12:13], off offset:-60
	global_load_b128 v[0:3], v[12:13], off offset:-44
	global_load_b128 v[36:39], v[12:13], off offset:-28
	global_load_b32 v8, v[12:13], off offset:-12
	s_cmp_eq_u32 s2, 0
	s_waitcnt vmcnt(3)
	ds_store_2addr_b32 v19, v4, v5 offset1:32
	ds_store_2addr_b32 v19, v6, v7 offset0:64 offset1:96
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v19, v0, v1 offset0:128 offset1:160
	ds_store_2addr_b32 v19, v2, v3 offset0:192 offset1:224
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v35, v36, v37 offset1:32
	ds_store_2addr_b32 v35, v38, v39 offset0:64 offset1:96
	s_waitcnt vmcnt(0)
	ds_store_b32 v19, v8 offset:1536
	s_cbranch_scc1 .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	global_load_b96 v[8:10], v[12:13], off offset:-8
	s_branch .LBB0_9
.LBB0_8:                                ;   in Loop: Header=BB0_6 Depth=1
	v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v10, s4
	v_mov_b32_e32 v8, 0x80
.LBB0_9:                                ;   in Loop: Header=BB0_6 Depth=1
	ds_load_u16 v36, v16 offset:2
	ds_load_u8 v37, v16 offset:1
	v_xor_b32_e32 v38, v15, v14
	ds_load_u8 v39, v18 offset:1
	ds_load_u16 v40, v18 offset:2
	ds_load_u8 v41, v21 offset:1
	ds_load_u16 v42, v21 offset:2
	ds_load_u8 v43, v22 offset:1
	ds_load_u16 v44, v22 offset:2
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s2, 1
	v_and_b32_e32 v38, v38, v17
	v_xor_b32_e32 v38, v38, v15
	s_waitcnt lgkmcnt(5)
	v_perm_b32 v5, v39, v5, 0x6050400
	s_waitcnt lgkmcnt(4)
	v_lshrrev_b16 v39, 8, v40
	v_and_b32_e32 v45, 0xff, v36
	v_lshrrev_b16 v36, 8, v36
	v_perm_b32 v4, v37, v4, 0x6050400
	v_and_b32_e32 v40, 0xff, v40
	s_waitcnt lgkmcnt(3)
	v_perm_b32 v6, v41, v6, 0x6050400
	v_lshlrev_b32_e32 v37, 16, v45
	v_lshlrev_b32_e32 v36, 24, v36
	v_xor_b32_e32 v45, v14, v17
	s_waitcnt lgkmcnt(2)
	v_lshrrev_b16 v41, 8, v42
	s_waitcnt lgkmcnt(1)
	v_perm_b32 v7, v43, v7, 0x6050400
	s_waitcnt lgkmcnt(0)
	v_lshrrev_b16 v43, 8, v44
	v_or3_b32 v4, v4, v37, v36
	v_add_co_u32 v36, s5, v20, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v37, null, 0, 0, s5
	v_lshlrev_b32_e32 v41, 24, v41
	v_add_co_u32 v36, vcc_lo, v36, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	v_lshlrev_b32_e32 v43, 24, v43
	v_add_co_u32 v36, vcc_lo, 0xd76aa478, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	v_lshlrev_b64 v[37:38], 7, v[36:37]
	v_lshrrev_b32_e32 v36, 25, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v37, vcc_lo, v37, v17
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v46, vcc_lo, v37, v36
	v_lshlrev_b32_e32 v36, 16, v40
	v_lshlrev_b32_e32 v37, 24, v39
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_and_b32_e32 v38, v46, v45
	v_and_b32_e32 v40, 0xff, v42
	v_or3_b32 v5, v5, v36, v37
	ds_load_u8 v45, v23 offset:1
	ds_load_u16 v47, v23 offset:2
	v_xor_b32_e32 v36, v38, v14
	v_lshlrev_b32_e32 v40, 16, v40
	v_add_co_u32 v37, s5, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v38, null, 0, 0, s5
	v_or3_b32 v6, v6, v40, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v36, vcc_lo, v37, v36
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v36, vcc_lo, 0xe8c7b756, v36
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	s_waitcnt lgkmcnt(1)
	v_perm_b32 v0, v45, v0, 0x6050400
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v53, 0xff, v47
	v_lshlrev_b64 v[37:38], 12, v[36:37]
	v_lshrrev_b32_e32 v36, 20, v36
	v_lshrrev_b16 v45, 8, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v47, 16, v53
	v_add_co_u32 v37, vcc_lo, v37, v46
	v_add_co_ci_u32_e32 v38, vcc_lo, v38, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v45, 24, v45
	v_add_co_u32 v42, vcc_lo, v37, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v40, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, s5, v14, v6
	v_bfi_b32 v36, v42, v46, v17
	v_add_co_ci_u32_e64 v38, null, 0, 0, s5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v41, v40, v39, 0
	v_or3_b32 v0, v0, v47, v45
	v_add_co_u32 v36, vcc_lo, v37, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v37, vcc_lo, v38, v41, vcc_lo
	v_add_co_u32 v36, vcc_lo, 0x242070db, v36
	v_and_b32_e32 v41, 0xff, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	v_lshlrev_b32_e32 v41, 16, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[37:38], 17, v[36:37]
	v_lshrrev_b32_e32 v36, 15, v36
	v_or3_b32 v7, v7, v41, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v37, vcc_lo, v37, v42
	v_add_co_ci_u32_e32 v38, vcc_lo, v38, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v44, vcc_lo, v37, v36
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, s5, v17, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v36, v44, v42, v46
	v_add_co_ci_u32_e64 v38, null, 0, 0, s5
	v_bfi_b32 v43, v41, v40, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v36, vcc_lo, v37, v36
	v_add_co_ci_u32_e32 v37, vcc_lo, v38, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v36, vcc_lo, 0xc1bdceee, v36
	ds_load_u8 v43, v24 offset:1
	ds_load_u16 v48, v24 offset:2
	ds_load_u8 v49, v25 offset:1
	ds_load_u16 v50, v25 offset:2
	ds_load_u8 v51, v26 offset:1
	ds_load_u16 v52, v26 offset:2
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[37:38], 22, v[36:37]
	v_lshrrev_b32_e32 v36, 10, v36
	v_add_co_u32 v37, vcc_lo, v37, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v38, vcc_lo, v38, v41, vcc_lo
	s_waitcnt lgkmcnt(5)
	v_perm_b32 v1, v43, v1, 0x6050400
	v_add_co_u32 v53, vcc_lo, v37, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, v46, v0
	v_bfi_b32 v36, v53, v44, v42
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_bfi_b32 v39, v45, v41, v40
	s_waitcnt lgkmcnt(4)
	v_lshrrev_b16 v43, 8, v48
	v_add_co_u32 v36, vcc_lo, v37, v36
	s_waitcnt lgkmcnt(3)
	v_perm_b32 v2, v49, v2, 0x6050400
	v_add_co_ci_u32_e32 v37, vcc_lo, v38, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v36, vcc_lo, 0xf57c0faf, v36
	v_and_b32_e32 v39, 0xff, v48
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	v_lshlrev_b32_e32 v43, 24, v43
	s_waitcnt lgkmcnt(1)
	v_perm_b32 v3, v51, v3, 0x6050400
	v_lshlrev_b32_e32 v39, 16, v39
	v_lshlrev_b64 v[37:38], 7, v[36:37]
	v_lshrrev_b32_e32 v36, 25, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or3_b32 v1, v1, v39, v43
	v_add_co_u32 v37, vcc_lo, v37, v53
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v38, vcc_lo, v38, v45, vcc_lo
	v_add_co_u32 v46, vcc_lo, v37, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, v42, v1
	v_bfi_b32 v36, v46, v53, v44
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v39, v43, v45, v41
	v_lshrrev_b16 v40, 8, v50
	v_add_co_u32 v36, vcc_lo, v37, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v37, vcc_lo, v38, v39, vcc_lo
	v_add_co_u32 v36, vcc_lo, 0x4787c62a, v36
	v_and_b32_e32 v39, 0xff, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	v_lshlrev_b32_e32 v40, 24, v40
	v_lshlrev_b32_e32 v39, 16, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[37:38], 12, v[36:37]
	v_lshrrev_b32_e32 v36, 20, v36
	v_or3_b32 v2, v2, v39, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v37, vcc_lo, v37, v46
	v_add_co_ci_u32_e32 v38, vcc_lo, v38, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, v37, v36
	v_add_co_ci_u32_e32 v40, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, v44, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v36, v47, v46, v53
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v41, vcc_lo
	v_bfi_b32 v39, v40, v43, v45
	s_waitcnt lgkmcnt(0)
	v_lshrrev_b16 v41, 8, v52
	v_add_co_u32 v36, vcc_lo, v37, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v37, vcc_lo, v38, v39, vcc_lo
	v_add_co_u32 v36, vcc_lo, 0xa8304613, v36
	v_and_b32_e32 v39, 0xff, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v37, vcc_lo
	v_lshlrev_b32_e32 v41, 24, v41
	v_lshlrev_b32_e32 v39, 16, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[37:38], 17, v[36:37]
	v_lshrrev_b32_e32 v36, 15, v36
	v_or3_b32 v3, v3, v39, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v37, vcc_lo, v37, v47
	v_add_co_ci_u32_e32 v38, vcc_lo, v38, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v48, vcc_lo, v37, v36
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, v53, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v36, v48, v47, v46
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v45, vcc_lo
	v_bfi_b32 v39, v49, v40, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v36, vcc_lo, v37, v36
	v_add_co_ci_u32_e32 v38, vcc_lo, v38, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v37, vcc_lo, 0xfd469501, v36
	ds_load_b32 v36, v27
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v38, vcc_lo
	v_lshlrev_b64 v[38:39], 22, v[37:38]
	v_lshrrev_b32_e32 v37, 10, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v38, vcc_lo, v38, v48
	v_add_co_ci_u32_e32 v42, vcc_lo, v39, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v45, vcc_lo, v38, v37
	v_add_co_ci_u32_e32 v50, vcc_lo, 0, v42, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v44, vcc_lo, v46, v36
	s_delay_alu instid0(VALU_DEP_3)
	v_bfi_b32 v42, v45, v48, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_bfi_b32 v46, v50, v49, v40
	ds_load_b32 v39, v28
	ds_load_b32 v37, v29
	ds_load_b32 v38, v30
	ds_load_b32 v41, v31
	v_add_co_u32 v42, vcc_lo, v44, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x698098d8, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 7, v[42:43]
	v_lshrrev_b32_e32 v42, 25, v42
	v_add_co_u32 v43, vcc_lo, v43, v45
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v50, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	ds_store_2addr_b32 v35, v41, v8 offset0:128 offset1:160
	v_add_co_u32 v46, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v47, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v46, v45, v48
	v_add_co_ci_u32_e32 v40, vcc_lo, 0, v40, vcc_lo
	v_bfi_b32 v44, v51, v50, v49
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v40, vcc_lo, v40, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x8b44f7af, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v40, 20, v42
	v_lshlrev_b64 v[43:44], 12, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v46
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, v42, v40
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v42, vcc_lo, v48, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v40, v47, v46, v45
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v49, vcc_lo
	v_bfi_b32 v44, v52, v51, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v40, vcc_lo, v42, v40
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xffff5bb1, v40
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v40, 15, v42
	v_lshlrev_b64 v[43:44], 17, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v48, vcc_lo, v42, v40
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v42, vcc_lo, v45, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v40, v48, v47, v46
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v50, vcc_lo
	v_bfi_b32 v44, v49, v52, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v40, vcc_lo, v42, v40
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x895cd7be, v40
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v40, 10, v42
	v_lshlrev_b64 v[43:44], 22, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v48
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v45, vcc_lo, v42, v40
	v_add_co_ci_u32_e32 v50, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v42, vcc_lo, v46, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v40, v45, v48, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v51, vcc_lo
	v_bfi_b32 v44, v50, v49, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v40, vcc_lo, v42, v40
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x6b901122, v40
	ds_load_b32 v40, v32
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshrrev_b32_e32 v8, 25, v42
	v_lshlrev_b64 v[43:44], 7, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v45
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v46, vcc_lo, v42, v8
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v43, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v42, vcc_lo, v40, v47
	s_delay_alu instid0(VALU_DEP_3)
	v_bfi_b32 v8, v46, v45, v48
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v52, vcc_lo
	v_bfi_b32 v44, v51, v50, v49
	ds_store_2addr_b32 v35, v40, v9 offset0:160 offset1:192
	v_add_co_u32 v8, vcc_lo, v42, v8
	ds_load_b32 v9, v33
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xfd987193, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshrrev_b32_e32 v8, 20, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[43:44], 12, v[42:43]
	v_add_co_u32 v42, vcc_lo, v43, v46
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v51, vcc_lo
	s_waitcnt lgkmcnt(0)
	ds_store_2addr_b32 v35, v9, v10 offset0:192 offset1:224
	v_add_co_u32 v47, vcc_lo, v42, v8
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v42, vcc_lo, v9, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v8, v47, v46, v45
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v49, vcc_lo
	v_bfi_b32 v44, v52, v51, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v42, v8
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xa679438e, v8
	ds_load_b32 v8, v34
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshrrev_b32_e32 v10, 15, v42
	ds_store_2addr_b32 v19, v4, v5 offset1:32
	ds_store_2addr_b32 v19, v6, v7 offset0:64 offset1:96
	ds_store_2addr_b32 v19, v0, v1 offset0:128 offset1:160
	ds_store_2addr_b32 v19, v2, v3 offset0:192 offset1:224
	v_lshlrev_b64 v[43:44], 17, v[42:43]
	ds_store_2addr_b32 v35, v36, v39 offset1:32
	ds_store_2addr_b32 v35, v37, v38 offset0:64 offset1:96
	s_waitcnt lgkmcnt(6)
	ds_store_b32 v19, v8 offset:1920
	v_add_co_u32 v42, vcc_lo, v43, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v43, vcc_lo, v8, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v10, v47, v46
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v50, vcc_lo
	v_bfi_b32 v45, v48, v52, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v45, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x49b40821, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 22, v[42:43]
	v_lshrrev_b32_e32 v42, 10, v42
	v_add_co_u32 v43, vcc_lo, v43, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v48, vcc_lo
	v_add_co_u32 v45, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v5, v46
	v_bfi_b32 v42, v47, v45, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v46, v52, v49, v48
	v_add_co_u32 v42, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v46, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xf61e2562, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshlrev_b64 v[43:44], 5, v[42:43]
	v_lshrrev_b32_e32 v42, 27, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v45
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v46, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v50, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v2, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v10, v46, v45
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v52, vcc_lo
	v_bfi_b32 v47, v48, v50, v49
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xc040b340, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 9, v[42:43]
	v_lshrrev_b32_e32 v42, 23, v42
	v_add_co_u32 v43, vcc_lo, v43, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v50, vcc_lo
	v_add_co_u32 v47, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v10, vcc_lo, v38, v10
	v_bfi_b32 v42, v45, v47, v46
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v44, v49, v51, v50
	v_add_co_u32 v10, vcc_lo, v10, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x265e5a51, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshrrev_b32_e32 v10, 18, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[43:44], 14, v[42:43]
	v_add_co_u32 v42, vcc_lo, v43, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v51, vcc_lo
	v_add_co_u32 v10, vcc_lo, v42, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v43, vcc_lo, v4, v45
	v_bfi_b32 v42, v46, v10, v47
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v45, v50, v48, v51
	v_add_co_u32 v42, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v45, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xe9b6c7aa, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshlrev_b64 v[43:44], 20, v[42:43]
	v_lshrrev_b32_e32 v42, 12, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v45, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v1, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v47, v45, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v50, vcc_lo
	v_bfi_b32 v46, v51, v49, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xd62f105d, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 5, v[42:43]
	v_lshrrev_b32_e32 v42, 27, v42
	v_add_co_u32 v43, vcc_lo, v43, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	v_add_co_u32 v46, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v50, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v37, v47
	v_bfi_b32 v42, v10, v46, v45
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v47, v48, v50, v49
	v_add_co_u32 v42, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v47, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x2441453, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshlrev_b64 v[43:44], 9, v[42:43]
	v_lshrrev_b32_e32 v42, 23, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v46
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v45, v47, v46
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v48, vcc_lo
	v_bfi_b32 v44, v49, v51, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xd8a1e681, v10
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v10, 18, v42
	v_lshlrev_b64 v[43:44], 14, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v43, vcc_lo, v0, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v46, v10, v47
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v49, vcc_lo
	v_bfi_b32 v45, v50, v48, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v45, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xe7d3fbc8, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 20, v[42:43]
	v_lshrrev_b32_e32 v42, 12, v42
	v_add_co_u32 v43, vcc_lo, v43, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v48, vcc_lo
	v_add_co_u32 v45, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v39, v46
	v_bfi_b32 v42, v47, v45, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v46, v51, v49, v48
	v_add_co_u32 v42, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v46, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x21e1cde6, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshlrev_b64 v[43:44], 5, v[42:43]
	v_lshrrev_b32_e32 v42, 27, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v45
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v46, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v50, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v9, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v10, v46, v45
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v51, vcc_lo
	v_bfi_b32 v47, v48, v50, v49
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xc33707d6, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 9, v[42:43]
	v_lshrrev_b32_e32 v42, 23, v42
	v_add_co_u32 v43, vcc_lo, v43, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v50, vcc_lo
	v_add_co_u32 v47, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v10, vcc_lo, v7, v10
	v_bfi_b32 v42, v45, v47, v46
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v44, v49, v51, v50
	v_add_co_u32 v10, vcc_lo, v10, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xf4d50d87, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshrrev_b32_e32 v10, 18, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[43:44], 14, v[42:43]
	v_add_co_u32 v42, vcc_lo, v43, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v51, vcc_lo
	v_add_co_u32 v10, vcc_lo, v42, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v43, vcc_lo, v36, v45
	v_bfi_b32 v42, v46, v10, v47
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v45, v50, v48, v51
	v_add_co_u32 v42, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v45, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x455a14ed, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshlrev_b64 v[43:44], 20, v[42:43]
	v_lshrrev_b32_e32 v42, 12, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v45, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v40, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v47, v45, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v50, vcc_lo
	v_bfi_b32 v46, v51, v49, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xa9e3e905, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 5, v[42:43]
	v_lshrrev_b32_e32 v42, 27, v42
	v_add_co_u32 v43, vcc_lo, v43, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	v_add_co_u32 v46, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v50, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v6, v47
	v_bfi_b32 v42, v10, v46, v45
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v47, v48, v50, v49
	v_add_co_u32 v42, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v47, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xfcefa3f8, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshlrev_b64 v[43:44], 9, v[42:43]
	v_lshrrev_b32_e32 v42, 23, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v46
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v10, vcc_lo, v3, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v45, v47, v46
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v48, vcc_lo
	v_bfi_b32 v44, v49, v51, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x676f02d9, v10
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v10, 18, v42
	v_lshlrev_b64 v[43:44], 14, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v43, vcc_lo
	v_add_co_u32 v43, vcc_lo, v41, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v42, v46, v10, v47
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v49, vcc_lo
	v_bfi_b32 v45, v50, v48, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v45, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0x8d2a4c8a, v42
	v_xor_b32_e32 v45, v10, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 20, v[42:43]
	v_lshrrev_b32_e32 v42, 12, v42
	v_add_co_u32 v43, vcc_lo, v43, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v48, vcc_lo
	v_add_co_u32 v49, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v48, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v44, vcc_lo
	v_xor_b32_e32 v43, v49, v45
	v_add_co_u32 v44, vcc_lo, v1, v46
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v52, v42
	v_add_co_u32 v43, vcc_lo, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v45, v42, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xfffa3942, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	v_lshlrev_b64 v[43:44], 4, v[42:43]
	v_lshrrev_b32_e32 v42, 28, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v49
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v45, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v43, vcc_lo, v36, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v50, v45, v49
	v_xor_b32_e32 v53, v46, v52
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v50, v10
	v_xor_b32_e32 v47, v53, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x8771f681, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 11, v[42:43]
	v_lshrrev_b32_e32 v42, 21, v42
	v_add_co_u32 v43, vcc_lo, v45, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v44, vcc_lo
	v_add_co_u32 v47, vcc_lo, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v10, vcc_lo, v38, v10
	v_xor_b32_e32 v42, v50, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v44, v53, v51
	v_add_co_u32 v10, vcc_lo, v10, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x6d9d6122, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshrrev_b32_e32 v10, 16, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[43:44], 16, v[42:43]
	v_add_co_u32 v42, vcc_lo, v43, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v51, vcc_lo
	v_xor_b32_e32 v43, v47, v45
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_xor_b32_e32 v42, v51, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v44, vcc_lo
	v_xor_b32_e32 v43, v43, v10
	v_add_co_u32 v44, vcc_lo, v9, v49
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v42, v48
	v_add_co_u32 v43, vcc_lo, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v49, v42, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xfde5380c, v43
	v_xor_b32_e32 v49, v10, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	v_lshlrev_b64 v[43:44], 23, v[42:43]
	v_lshrrev_b32_e32 v42, 9, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v50, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v48, v51
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v49, v50
	v_add_co_u32 v44, vcc_lo, v5, v45
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v46, vcc_lo
	v_xor_b32_e32 v42, v42, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v44, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, v45, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0xa4beea44, v43
	v_xor_b32_e32 v45, v50, v10
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 4, v[42:43]
	v_lshrrev_b32_e32 v42, 28, v42
	v_add_co_u32 v43, vcc_lo, v43, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v52, vcc_lo
	v_add_co_u32 v46, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v52, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	v_xor_b32_e32 v43, v45, v46
	v_add_co_u32 v44, vcc_lo, v0, v47
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v42, v49
	v_add_co_u32 v43, vcc_lo, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v45, v42, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x4bdecfa9, v43
	v_xor_b32_e32 v45, v46, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	v_lshlrev_b64 v[43:44], 11, v[42:43]
	v_lshrrev_b32_e32 v42, 21, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v46
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v47, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v49, v52
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v45, v47
	v_add_co_u32 v10, vcc_lo, v3, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v48, vcc_lo
	v_xor_b32_e32 v42, v42, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v43
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0xf6bb4b60, v10
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v10, 16, v42
	v_lshlrev_b64 v[43:44], 16, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v47
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v51, vcc_lo
	v_xor_b32_e32 v43, v47, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_xor_b32_e32 v42, v51, v49
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v43, v10
	v_add_co_u32 v44, vcc_lo, v37, v50
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v52, vcc_lo
	v_xor_b32_e32 v42, v42, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v44, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, v48, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0xbebfbc70, v43
	v_xor_b32_e32 v48, v10, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 23, v[42:43]
	v_lshrrev_b32_e32 v42, 9, v42
	v_add_co_u32 v43, vcc_lo, v43, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v45, vcc_lo
	v_add_co_u32 v50, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v45, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v44, vcc_lo
	v_xor_b32_e32 v43, v48, v50
	v_add_co_u32 v44, vcc_lo, v40, v46
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v42, v52
	v_add_co_u32 v43, vcc_lo, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x289b7ec6, v43
	v_xor_b32_e32 v46, v50, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	v_lshlrev_b64 v[43:44], 4, v[42:43]
	v_lshrrev_b32_e32 v42, 28, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v50
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v48, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v52, v45
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v46, v48
	v_add_co_u32 v44, vcc_lo, v4, v47
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v51, vcc_lo
	v_xor_b32_e32 v42, v42, v49
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v44, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0xeaa127fa, v43
	v_xor_b32_e32 v46, v48, v50
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 11, v[42:43]
	v_lshrrev_b32_e32 v42, 21, v42
	v_add_co_u32 v43, vcc_lo, v43, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	v_add_co_u32 v47, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v49, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	v_xor_b32_e32 v43, v46, v47
	v_add_co_u32 v10, vcc_lo, v7, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v45, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v42, v51
	v_add_co_u32 v10, vcc_lo, v10, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v42, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xd4ef3085, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_lshrrev_b32_e32 v10, 16, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[43:44], 16, v[42:43]
	v_add_co_u32 v42, vcc_lo, v43, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v51, vcc_lo
	v_xor_b32_e32 v43, v47, v48
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_xor_b32_e32 v42, v51, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v44, vcc_lo
	v_xor_b32_e32 v43, v43, v10
	v_add_co_u32 v44, vcc_lo, v2, v50
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v42, v45
	v_add_co_u32 v43, vcc_lo, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x4881d05, v43
	v_xor_b32_e32 v46, v10, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	v_lshlrev_b64 v[43:44], 23, v[42:43]
	v_lshrrev_b32_e32 v42, 9, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v45, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v50, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v45, v51
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v46, v50
	v_add_co_u32 v44, vcc_lo, v39, v48
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v49, vcc_lo
	v_xor_b32_e32 v42, v42, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v44, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0xd9d4d039, v43
	v_xor_b32_e32 v46, v50, v10
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 4, v[42:43]
	v_lshrrev_b32_e32 v42, 28, v42
	v_add_co_u32 v43, vcc_lo, v43, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v52, vcc_lo
	v_add_co_u32 v48, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v52, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	v_xor_b32_e32 v43, v46, v48
	v_add_co_u32 v44, vcc_lo, v41, v47
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v42, v42, v49
	v_add_co_u32 v43, vcc_lo, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0xe6db99e5, v43
	v_xor_b32_e32 v46, v48, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	v_lshlrev_b64 v[43:44], 11, v[42:43]
	v_lshrrev_b32_e32 v42, 21, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v48
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v47, vcc_lo, v43, v42
	v_xor_b32_e32 v42, v49, v52
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v46, v47
	v_add_co_u32 v10, vcc_lo, v8, v10
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v45, vcc_lo
	v_xor_b32_e32 v42, v42, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v43
	v_add_co_ci_u32_e32 v43, vcc_lo, v44, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, 0x1fa27cf8, v10
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v10, 16, v42
	v_lshlrev_b64 v[43:44], 16, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v42, vcc_lo, v43, v47
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v51, vcc_lo
	v_xor_b32_e32 v43, v47, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_xor_b32_e32 v42, v51, v49
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v43, v10
	v_add_co_u32 v44, vcc_lo, v6, v50
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v52, vcc_lo
	v_xor_b32_e32 v42, v42, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v44, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0xc4ac5665, v43
	v_not_b32_e32 v46, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 23, v[42:43]
	v_lshrrev_b32_e32 v42, 9, v42
	v_add_co_u32 v43, vcc_lo, v43, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v45, vcc_lo
	v_add_co_u32 v50, vcc_lo, v43, v42
	v_not_b32_e32 v42, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v52, vcc_lo, 0, v44, vcc_lo
	v_or_b32_e32 v43, v50, v46
	v_add_co_u32 v44, vcc_lo, v4, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v42, v52, v42
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v49, vcc_lo
	v_xor_b32_e32 v43, v43, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v42, v42, v45
	v_add_co_u32 v43, vcc_lo, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	v_not_b32_e32 v46, v10
	v_add_co_u32 v42, vcc_lo, 0xf4292244, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	v_lshlrev_b64 v[43:44], 6, v[42:43]
	v_lshrrev_b32_e32 v42, 26, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v43, vcc_lo, v43, v50
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v48, vcc_lo, v43, v42
	v_not_b32_e32 v42, v45
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v43, v48, v46
	v_add_co_u32 v44, vcc_lo, v3, v47
	v_or_b32_e32 v42, v49, v42
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v51, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v43, v43, v50
	v_xor_b32_e32 v42, v42, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, v44, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, v46, v42, vcc_lo
	v_not_b32_e32 v46, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0x432aff97, v43
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 10, v[42:43]
	v_lshrrev_b32_e32 v42, 22, v42
	v_add_co_u32 v43, vcc_lo, v43, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v44, vcc_lo, v44, v49, vcc_lo
	v_add_co_u32 v47, vcc_lo, v43, v42
	v_not_b32_e32 v42, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v44, vcc_lo, 0, v44, vcc_lo
	v_or_b32_e32 v43, v47, v46
	v_add_co_u32 v9, vcc_lo, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v42, v44, v42
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v45, vcc_lo
	v_xor_b32_e32 v43, v43, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v42, v42, v49
	v_add_co_u32 v9, vcc_lo, v9, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v10, v42, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0xab9423a7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_lshlrev_b64 v[42:43], 15, v[9:10]
	v_lshrrev_b32_e32 v9, 17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v42, v47
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v44, vcc_lo
	v_not_b32_e32 v42, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v45, vcc_lo, v10, v9
	v_not_b32_e32 v9, v49
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v45, v42
	v_add_co_u32 v42, vcc_lo, v1, v50
	v_or_b32_e32 v9, v46, v9
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v52, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v47
	v_xor_b32_e32 v9, v9, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v42, v10
	v_add_co_ci_u32_e32 v42, vcc_lo, v43, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, 0xfc93a039, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[42:43], 21, v[9:10]
	v_lshrrev_b32_e32 v9, 11, v9
	v_add_co_u32 v10, vcc_lo, v42, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v43, vcc_lo, v43, v46, vcc_lo
	v_not_b32_e32 v42, v47
	v_add_co_u32 v50, vcc_lo, v10, v9
	v_not_b32_e32 v9, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v43, vcc_lo
	v_or_b32_e32 v10, v50, v42
	v_add_co_u32 v41, vcc_lo, v41, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v9, v43, v9
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v49, vcc_lo
	v_xor_b32_e32 v10, v10, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v46
	v_add_co_u32 v10, vcc_lo, v41, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v41, vcc_lo, v42, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0x655b59c3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	v_lshlrev_b64 v[41:42], 6, v[9:10]
	v_lshrrev_b32_e32 v9, 26, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v41, v50
	v_add_co_ci_u32_e32 v42, vcc_lo, v42, v43, vcc_lo
	v_not_b32_e32 v41, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v10, v9
	v_not_b32_e32 v9, v46
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v48, v41
	v_add_co_u32 v41, vcc_lo, v7, v47
	v_or_b32_e32 v9, v49, v9
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v50
	v_xor_b32_e32 v9, v9, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v41, v10
	v_add_co_ci_u32_e32 v41, vcc_lo, v42, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, 0x8f0ccc92, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[41:42], 10, v[9:10]
	v_lshrrev_b32_e32 v9, 22, v9
	v_add_co_u32 v10, vcc_lo, v41, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v42, vcc_lo, v42, v49, vcc_lo
	v_not_b32_e32 v41, v50
	v_add_co_u32 v44, vcc_lo, v10, v9
	v_not_b32_e32 v9, v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v42, vcc_lo
	v_or_b32_e32 v10, v44, v41
	v_add_co_u32 v41, vcc_lo, v37, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v9, v47, v9
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v46, vcc_lo
	v_xor_b32_e32 v10, v10, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v49
	v_add_co_u32 v10, vcc_lo, v41, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v41, vcc_lo, v42, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0xffeff47d, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	v_lshlrev_b64 v[41:42], 15, v[9:10]
	v_lshrrev_b32_e32 v9, 17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v41, v44
	v_add_co_ci_u32_e32 v42, vcc_lo, v42, v47, vcc_lo
	v_not_b32_e32 v41, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v45, vcc_lo, v10, v9
	v_not_b32_e32 v9, v49
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v45, v41
	v_add_co_u32 v41, vcc_lo, v5, v50
	v_or_b32_e32 v9, v46, v9
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v44
	v_xor_b32_e32 v9, v9, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v41, v10
	v_add_co_ci_u32_e32 v41, vcc_lo, v42, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, 0x85845dd1, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[41:42], 21, v[9:10]
	v_lshrrev_b32_e32 v9, 11, v9
	v_add_co_u32 v10, vcc_lo, v41, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v42, vcc_lo, v42, v46, vcc_lo
	v_not_b32_e32 v41, v44
	v_add_co_u32 v43, vcc_lo, v10, v9
	v_not_b32_e32 v9, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v50, vcc_lo, 0, v42, vcc_lo
	v_or_b32_e32 v10, v43, v41
	v_add_co_u32 v41, vcc_lo, v36, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v9, v50, v9
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v49, vcc_lo
	v_xor_b32_e32 v10, v10, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v46
	v_add_co_u32 v10, vcc_lo, v41, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v41, vcc_lo, v42, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0x6fa87e4f, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	v_lshlrev_b64 v[41:42], 6, v[9:10]
	v_lshrrev_b32_e32 v9, 26, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v41, v43
	v_add_co_ci_u32_e32 v42, vcc_lo, v42, v50, vcc_lo
	v_not_b32_e32 v41, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v10, v9
	v_not_b32_e32 v9, v46
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v48, v41
	v_add_co_u32 v41, vcc_lo, v8, v44
	v_or_b32_e32 v9, v49, v9
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v43
	v_xor_b32_e32 v9, v9, v50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v41, v10
	v_add_co_ci_u32_e32 v41, vcc_lo, v42, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, 0xfe2ce6e0, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[41:42], 10, v[9:10]
	v_lshrrev_b32_e32 v9, 22, v9
	v_add_co_u32 v10, vcc_lo, v41, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v42, vcc_lo, v42, v49, vcc_lo
	v_not_b32_e32 v41, v43
	v_add_co_u32 v44, vcc_lo, v10, v9
	v_not_b32_e32 v9, v50
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v42, vcc_lo
	v_or_b32_e32 v10, v44, v41
	v_add_co_u32 v41, vcc_lo, v2, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v9, v47, v9
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v46, vcc_lo
	v_xor_b32_e32 v10, v10, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v49
	v_add_co_u32 v10, vcc_lo, v41, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v41, vcc_lo, v42, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0xa3014314, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	v_lshlrev_b64 v[41:42], 15, v[9:10]
	v_lshrrev_b32_e32 v9, 17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v41, v44
	v_add_co_ci_u32_e32 v42, vcc_lo, v42, v47, vcc_lo
	v_not_b32_e32 v41, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v45, vcc_lo, v10, v9
	v_not_b32_e32 v9, v49
	v_add_co_ci_u32_e32 v42, vcc_lo, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v45, v41
	v_add_co_u32 v40, vcc_lo, v40, v43
	v_or_b32_e32 v9, v42, v9
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v44
	v_xor_b32_e32 v9, v9, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v40, v10
	v_add_co_ci_u32_e32 v40, vcc_lo, v41, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, 0x4e0811a1, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[40:41], 21, v[9:10]
	v_lshrrev_b32_e32 v9, 11, v9
	v_add_co_u32 v10, vcc_lo, v40, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v41, vcc_lo, v41, v42, vcc_lo
	v_not_b32_e32 v40, v44
	v_add_co_u32 v43, vcc_lo, v10, v9
	v_not_b32_e32 v9, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v46, vcc_lo, 0, v41, vcc_lo
	v_or_b32_e32 v10, v43, v40
	v_add_co_u32 v40, vcc_lo, v0, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v9, v46, v9
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v49, vcc_lo
	v_xor_b32_e32 v10, v10, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v42
	v_add_co_u32 v10, vcc_lo, v40, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v40, vcc_lo, v41, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0xf7537e82, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v40, vcc_lo
	v_lshlrev_b64 v[40:41], 6, v[9:10]
	v_lshrrev_b32_e32 v9, 26, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v40, v43
	v_add_co_ci_u32_e32 v41, vcc_lo, v41, v46, vcc_lo
	v_not_b32_e32 v40, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v48, vcc_lo, v10, v9
	v_not_b32_e32 v9, v42
	v_add_co_ci_u32_e32 v49, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v48, v40
	v_add_co_u32 v40, vcc_lo, v38, v44
	v_or_b32_e32 v9, v49, v9
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v10, v43
	v_add_nc_u32_e32 v20, v20, v48
	v_xor_b32_e32 v9, v9, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v40, v10
	v_add_co_ci_u32_e32 v40, vcc_lo, v41, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, 0xbd3af235, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[40:41], 10, v[9:10]
	v_lshrrev_b32_e32 v9, 22, v9
	v_add_co_u32 v10, vcc_lo, v40, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v41, vcc_lo, v41, v49, vcc_lo
	v_not_b32_e32 v40, v43
	v_add_co_u32 v44, vcc_lo, v10, v9
	v_not_b32_e32 v9, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v41, vcc_lo
	v_or_b32_e32 v10, v44, v40
	v_add_co_u32 v40, vcc_lo, v6, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v9, v47, v9
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v42, vcc_lo
	v_xor_b32_e32 v10, v10, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v49
	v_add_co_u32 v10, vcc_lo, v40, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v40, vcc_lo, v41, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0x2ad7d2bb, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v40, vcc_lo
	v_lshlrev_b64 v[40:41], 15, v[9:10]
	v_lshrrev_b32_e32 v9, 17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v40, v44
	v_add_co_ci_u32_e32 v41, vcc_lo, v41, v47, vcc_lo
	v_not_b32_e32 v40, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v42, vcc_lo, v10, v9
	v_not_b32_e32 v9, v49
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v40, v42, v40
	v_or_b32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v40, v44
	v_add_co_u32 v40, vcc_lo, v39, v43
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v46, vcc_lo
	v_xor_b32_e32 v9, v9, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v40, v10
	v_add_co_ci_u32_e32 v40, vcc_lo, v41, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, 0xeb86d391, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v2, 11, v9
	v_add_co_u32 v15, vcc_lo, v44, v15
	v_lshlrev_b64 v[0:1], 21, v[9:10]
	v_add_co_u32 v1, vcc_lo, v42, v17
	v_add_co_u32 v14, vcc_lo, v42, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, vcc_lo, v1, v0
	v_add_co_u32 v17, vcc_lo, v0, v2
	v_add_co_u32 v12, vcc_lo, v12, 64
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	s_cbranch_scc1 .LBB0_6
.LBB0_10:                               ; %_ZL12md5_internalPjS_iPh.exit
	s_load_b64 s[0:1], s[0:1], 0x18
	v_lshlrev_b32_e32 v0, 2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v20, off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3md5PhiiiS_
		.amdhsa_group_segment_fixed_size 16256
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 54
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3md5PhiiiS_, .Lfunc_end0-_Z3md5PhiiiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8976
; NumSgprs: 18
; NumVgprs: 54
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16256 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 54
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11md5_overlapPhiiiiS_ ; -- Begin function _Z11md5_overlapPhiiiiS_
	.globl	_Z11md5_overlapPhiiiiS_
	.p2align	8
	.type	_Z11md5_overlapPhiiiiS_,@function
_Z11md5_overlapPhiiiiS_:                ; @_Z11md5_overlapPhiiiiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s6, v8
	s_cbranch_execz .LBB1_17
; %bb.1:
	s_add_i32 s2, s6, -1
	v_mov_b32_e32 v9, 0x67452301
	v_cmp_eq_u32_e32 vcc_lo, s2, v8
	s_mov_b32 s8, exec_lo
	v_cndmask_b32_e64 v1, 0, s7, vcc_lo
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, s4, v1
	v_cmpx_lt_i32_e32 0xffffffc0, v1
	s_cbranch_execz .LBB1_16
; %bb.2:                                ; %.lr.ph905.i
	v_ashrrev_i32_e32 v2, 31, v1
	v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v3, 6, v0
	v_and_b32_e32 v0, 31, v0
	s_load_b64 s[10:11], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3)
	v_lshrrev_b32_e32 v2, 26, v2
	v_mul_lo_u32 v4, v8, s5
	v_and_b32_e32 v19, 0xf800, v3
	v_lshlrev_b32_e32 v20, 2, v0
	v_lshlrev_b32_e32 v18, 3, v1
	v_dual_mov_b32 v13, 0x98badcfe :: v_dual_add_nc_u32 v2, v1, v2
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v14, 0x10325476
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v15, 0 :: v_dual_and_b32 v0, 0xffffffc0, v2
	v_ashrrev_i32_e32 v29, 6, v2
	v_ashrrev_i32_e32 v21, 29, v1
	v_ashrrev_i32_e32 v3, 31, v4
	v_or_b32_e32 v22, v19, v20
	v_sub_nc_u32_e32 v0, v0, v1
	v_dual_mov_b32 v16, 0xefcdab89 :: v_dual_lshlrev_b32 v9, 4, v29
	v_or_b32_e32 v5, 0x380, v20
	v_or_b32_e32 v6, 0x400, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v15, 0x80 :: v_dual_add_nc_u32 v0, 52, v0
	v_or_b32_e32 v2, 0x480, v20
	v_or_b32_e32 v7, 0x500, v20
	v_or_b32_e32 v39, 0x580, v20
	v_ashrrev_i32_e32 v31, 2, v0
	v_lshlrev_b64 v[0:1], 2, v[9:10]
	v_or_b32_e32 v40, 0x600, v20
	v_or_b32_e32 v41, 0x680, v20
	v_or_b32_e32 v42, 0x700, v20
	v_or_b32_e32 v43, 0x780, v20
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v32, vcc_lo, s10, v4
	v_add_co_u32 v0, s3, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, s3, v1, v3, s3
	v_add_co_ci_u32_e32 v33, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v11, s3, s10, v0
	v_mov_b32_e32 v17, 0
	v_or_b32_e32 v23, 0x80, v20
	v_or_b32_e32 v24, 0x100, v20
	v_or_b32_e32 v25, 0x180, v20
	v_or_b32_e32 v26, 0x200, v20
	v_or_b32_e32 v27, 0x280, v20
	v_or_b32_e32 v28, 0x300, v20
	v_or_b32_e32 v30, 0x680, v22
	v_cmp_lt_i32_e32 vcc_lo, 0, v31
	v_sub_nc_u32_e32 v34, 13, v31
	v_cmp_gt_i32_e64 s2, 13, v31
	v_sub_nc_u32_e32 v35, 0, v31
	v_add_co_ci_u32_e64 v12, s3, s11, v1, s3
	v_mov_b32_e32 v9, 0x67452301
	v_add_nc_u32_e32 v17, v19, v5
	v_add_nc_u32_e32 v36, v19, v6
	v_add_nc_u32_e32 v37, v19, v2
	v_add_nc_u32_e32 v38, v19, v7
	v_add_nc_u32_e32 v39, v19, v39
	v_add_nc_u32_e32 v40, v19, v40
	v_add_nc_u32_e32 v41, v19, v41
	v_add_nc_u32_e32 v42, v19, v42
	v_add_nc_u32_e32 v43, v19, v43
	v_add_nc_u32_e32 v44, 0x400, v22
	s_mov_b32 s9, 0
	s_mov_b32 s10, 0
.LBB1_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_8 Depth 2
                                        ;     Child Loop BB1_12 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_eq_u32_e64 s3, s10, v29
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr0
	v_cmpx_ne_u32_e64 s10, v29
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=1
	s_lshl_b32 s6, s10, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[6:7], 2
	v_add_co_u32 v49, s4, v32, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v50, s4, s13, v33, s4
	s_clause 0x3
	global_load_b128 v[4:7], v[49:50], off
	global_load_b128 v[0:3], v[49:50], off offset:16
	global_load_b128 v[45:48], v[49:50], off offset:32
	global_load_b128 v[49:52], v[49:50], off offset:48
	s_waitcnt vmcnt(3)
	ds_store_2addr_b32 v22, v4, v5 offset1:32
	ds_store_2addr_b32 v22, v6, v7 offset0:64 offset1:96
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v22, v0, v1 offset0:128 offset1:160
	ds_store_2addr_b32 v22, v2, v3 offset0:192 offset1:224
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v44, v45, v46 offset1:32
	ds_store_2addr_b32 v44, v47, v48 offset0:64 offset1:96
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v44, v49, v50 offset0:128 offset1:160
	ds_store_2addr_b32 v44, v51, v52 offset0:192 offset1:224
.LBB1_5:                                ; %Flow190
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_and_not1_saveexec_b32 s6, s5
	s_cbranch_execz .LBB1_14
; %bb.6:                                ;   in Loop: Header=BB1_3 Depth=1
	v_mov_b32_e32 v2, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_10
; %bb.7:                                ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v0, v30 :: v_dual_mov_b32 v1, v31
	s_mov_b32 s11, 0
.LBB1_8:                                ; %.lr.ph.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, -1, v1
	ds_store_b32 v0, v10
	v_add_nc_u32_e32 v0, 0xffffff80, v0
	v_cmp_eq_u32_e64 s4, 0, v1
	s_or_b32 s11, s4, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_8
; %bb.9:                                ; %Flow188
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v2, v35
.LBB1_10:                               ; %Flow189
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s11, s2
	s_cbranch_execz .LBB1_13
; %bb.11:                               ; %.lr.ph896.i.preheader
                                        ;   in Loop: Header=BB1_3 Depth=1
	v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
	v_mov_b32_e32 v3, v22
	s_mov_b32 s12, 0
	s_mov_b32 s13, 0
.LBB1_12:                               ; %.lr.ph896.i
                                        ;   Parent Loop BB1_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v4, v[0:1], off
	s_add_i32 s13, s13, 1
	v_add_co_u32 v0, s4, v0, 4
	v_cmp_ge_i32_e64 s5, s13, v34
	v_add_co_ci_u32_e64 v1, s4, 0, v1, s4
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s12, s5, s12
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	v_add_nc_u32_e32 v3, 0x80, v3
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_12
.LBB1_13:                               ; %Flow187
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_lshl_add_u32 v0, v2, 7, v30
	v_add_nc_u32_e32 v1, v19, v20
	v_add_nc_u32_e32 v2, v19, v23
	v_add_nc_u32_e32 v3, v19, v24
	v_add_nc_u32_e32 v7, v19, v25
	ds_store_b32 v0, v15
	v_add_nc_u32_e32 v0, v19, v26
	v_add_nc_u32_e32 v45, v19, v27
	v_add_nc_u32_e32 v46, v19, v28
	ds_load_u8 v4, v1
	ds_load_u8 v5, v2
	ds_load_u8 v6, v3
	ds_load_u8 v7, v7
	ds_load_u8 v0, v0
	ds_load_u8 v1, v45
	ds_load_u8 v2, v46
	ds_store_2addr_b32 v44, v18, v21 offset0:192 offset1:224
.LBB1_14:                               ; %Flow191
                                        ;   in Loop: Header=BB1_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v3, v19, v20
	v_add_nc_u32_e32 v46, v19, v23
	v_xor_b32_e32 v49, v14, v13
	v_add_nc_u32_e32 v47, v19, v24
	v_add_nc_u32_e32 v48, v19, v25
	ds_load_u16 v45, v3 offset:2
	ds_load_u8 v3, v3 offset:1
	ds_load_u8 v50, v46 offset:1
	ds_load_u16 v51, v46 offset:2
	ds_load_u8 v52, v47 offset:1
	ds_load_u16 v53, v47 offset:2
	ds_load_u8 v54, v48 offset:1
	ds_load_u16 v48, v48 offset:2
	v_and_b32_e32 v47, v49, v16
	s_and_b32 s3, exec_lo, s3
	v_add_nc_u32_e32 v57, v19, v28
	s_or_b32 s9, s3, s9
	s_add_i32 s10, s10, 1
	s_waitcnt lgkmcnt(5)
	v_perm_b32 v5, v50, v5, 0x6050400
	s_waitcnt lgkmcnt(4)
	v_lshrrev_b16 v49, 8, v51
	v_and_b32_e32 v50, 0xff, v51
	v_and_b32_e32 v46, 0xff, v45
	v_lshrrev_b16 v45, 8, v45
	v_perm_b32 v3, v3, v4, 0x6050400
	s_waitcnt lgkmcnt(3)
	v_perm_b32 v6, v52, v6, 0x6050400
	s_waitcnt lgkmcnt(1)
	v_perm_b32 v7, v54, v7, 0x6050400
	v_lshlrev_b32_e32 v4, 16, v46
	v_lshlrev_b32_e32 v45, 24, v45
	v_xor_b32_e32 v46, v47, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v3, v3, v4, v45
	v_add_co_u32 v4, s3, v9, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v45, null, 0, 0, s3
	v_add_co_u32 v4, s3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v46, s3, 0, v45, s3
	v_add_co_u32 v45, s3, 0xd76aa478, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v46, s3, 0, v46, s3
	v_xor_b32_e32 v4, v13, v16
	v_lshlrev_b64 v[46:47], 7, v[45:46]
	v_lshrrev_b32_e32 v45, 25, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, v46, v16
	v_add_co_ci_u32_e64 v47, s3, 0, v47, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v51, s3, v46, v45
	v_lshlrev_b32_e32 v45, 16, v50
	v_lshlrev_b32_e32 v46, 24, v49
	v_add_co_ci_u32_e64 v49, s3, 0, v47, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_and_b32_e32 v47, v51, v4
	v_lshrrev_b16 v50, 8, v53
	v_or3_b32 v4, v5, v45, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v47, v13
	v_lshlrev_b32_e32 v50, 24, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v45, s3, v14, v4
	v_add_co_ci_u32_e64 v46, null, 0, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s3, v45, v5
	v_add_co_ci_u32_e64 v46, s3, 0, v46, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v45, s3, 0xe8c7b756, v5
	v_add_co_ci_u32_e64 v46, s3, 0, v46, s3
	v_and_b32_e32 v5, 0xff, v53
	v_add_nc_u32_e32 v53, v19, v26
	ds_load_u8 v55, v53 offset:1
	ds_load_u16 v53, v53 offset:2
	v_lshlrev_b64 v[46:47], 12, v[45:46]
	v_lshlrev_b32_e32 v5, 16, v5
	v_lshrrev_b32_e32 v45, 20, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, v46, v51
	v_add_co_ci_u32_e64 v47, s3, v47, v49, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or3_b32 v5, v6, v5, v50
	v_add_co_u32 v52, s3, v46, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v50, s3, 0, v47, s3
	v_add_co_u32 v45, s3, v13, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v6, v52, v51, v16
	v_add_co_ci_u32_e64 v46, null, 0, 0, s3
	v_bfi_b32 v47, v50, v49, 0
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v61, 0xff, v53
	v_add_co_u32 v6, s3, v45, v6
	v_lshrrev_b16 v53, 8, v53
	v_add_co_ci_u32_e64 v46, s3, v46, v47, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v45, s3, 0x242070db, v6
	v_and_b32_e32 v6, 0xff, v48
	v_add_co_ci_u32_e64 v46, s3, 0, v46, s3
	v_lshrrev_b16 v48, 8, v48
	v_perm_b32 v0, v55, v0, 0x6050400
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v6, 16, v6
	v_lshlrev_b64 v[46:47], 17, v[45:46]
	v_lshrrev_b32_e32 v45, 15, v45
	v_lshlrev_b32_e32 v48, 24, v48
	v_lshlrev_b32_e32 v55, 16, v61
	v_lshlrev_b32_e32 v53, 24, v53
	v_add_co_u32 v46, s3, v46, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v47, s3, v47, v50, s3
	v_or3_b32 v6, v7, v6, v48
	v_add_co_u32 v54, s3, v46, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v56, s3, 0, v47, s3
	v_add_co_u32 v45, s3, v16, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v7, v54, v52, v51
	v_add_co_ci_u32_e64 v46, null, 0, 0, s3
	v_bfi_b32 v47, v56, v50, v49
	v_add_nc_u32_e32 v48, v19, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, s3, v45, v7
	v_or3_b32 v0, v0, v55, v53
	v_add_co_ci_u32_e64 v45, s3, v46, v47, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, 0xc1bdceee, v7
	v_add_co_ci_u32_e64 v47, s3, 0, v45, s3
	ds_load_u8 v58, v48 offset:1
	ds_load_u16 v59, v48 offset:2
	ds_load_u8 v60, v57 offset:1
	ds_load_u16 v57, v57 offset:2
	ds_load_b32 v7, v17
	ds_load_b32 v45, v36
	v_lshlrev_b64 v[47:48], 22, v[46:47]
	v_lshrrev_b32_e32 v46, 10, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v47, s3, v47, v54
	v_add_co_ci_u32_e64 v48, s3, v48, v56, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v61, s3, v47, v46
	v_add_co_ci_u32_e64 v53, s3, 0, v48, s3
	v_add_co_u32 v47, s3, v51, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v46, v61, v54, v52
	v_add_co_ci_u32_e64 v48, s3, 0, v49, s3
	v_bfi_b32 v49, v53, v56, v50
	s_waitcnt lgkmcnt(4)
	v_lshrrev_b16 v51, 8, v59
	v_add_co_u32 v46, s3, v47, v46
	v_perm_b32 v1, v58, v1, 0x6050400
	v_add_co_ci_u32_e64 v47, s3, v48, v49, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v46, s3, 0xf57c0faf, v46
	v_and_b32_e32 v49, 0xff, v59
	v_add_co_ci_u32_e64 v47, s3, 0, v47, s3
	v_lshlrev_b32_e32 v51, 24, v51
	s_waitcnt lgkmcnt(3)
	v_perm_b32 v2, v60, v2, 0x6050400
	v_lshlrev_b32_e32 v49, 16, v49
	v_lshlrev_b64 v[47:48], 7, v[46:47]
	v_lshrrev_b32_e32 v46, 25, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_or3_b32 v1, v1, v49, v51
	s_waitcnt lgkmcnt(2)
	v_lshrrev_b16 v51, 8, v57
	v_add_co_u32 v47, s3, v47, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v48, s3, v48, v53, s3
	v_lshlrev_b32_e32 v51, 24, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v55, s3, v47, v46
	v_add_co_ci_u32_e64 v49, s3, 0, v48, s3
	v_add_co_u32 v47, s3, v52, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v46, v55, v61, v54
	v_add_co_ci_u32_e64 v48, s3, 0, v50, s3
	v_bfi_b32 v50, v49, v53, v56
	ds_load_b32 v52, v37
	v_add_co_u32 v46, s3, v47, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v47, s3, v48, v50, s3
	v_add_co_u32 v46, s3, 0x4787c62a, v46
	v_and_b32_e32 v50, 0xff, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v47, s3, 0, v47, s3
	v_lshlrev_b32_e32 v50, 16, v50
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[47:48], 12, v[46:47]
	v_lshrrev_b32_e32 v46, 20, v46
	v_or3_b32 v2, v2, v50, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v47, s3, v47, v55
	v_add_co_ci_u32_e64 v48, s3, v48, v49, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v57, s3, v47, v46
	v_add_co_ci_u32_e64 v58, s3, 0, v48, s3
	v_add_co_u32 v47, s3, v54, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v46, v57, v55, v61
	v_add_co_ci_u32_e64 v48, s3, 0, v56, s3
	v_bfi_b32 v50, v58, v49, v53
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, v47, v46
	v_add_co_ci_u32_e64 v47, s3, v48, v50, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, 0xa8304613, v46
	v_add_co_ci_u32_e64 v47, s3, 0, v47, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[47:48], 17, v[46:47]
	v_lshrrev_b32_e32 v46, 15, v46
	v_add_co_u32 v47, s3, v47, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v48, s3, v48, v58, s3
	v_add_co_u32 v56, s3, v47, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v59, s3, 0, v48, s3
	s_waitcnt lgkmcnt(2)
	v_add_co_u32 v47, s3, v61, v7
	v_bfi_b32 v46, v56, v57, v55
	v_add_co_ci_u32_e64 v48, s3, 0, v53, s3
	v_bfi_b32 v50, v59, v58, v49
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, v47, v46
	v_add_co_ci_u32_e64 v47, s3, v48, v50, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, 0xfd469501, v46
	v_add_co_ci_u32_e64 v47, s3, 0, v47, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[47:48], 22, v[46:47]
	v_lshrrev_b32_e32 v46, 10, v46
	v_add_co_u32 v47, s3, v47, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v48, s3, v48, v59, s3
	v_add_co_u32 v60, s3, v47, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v61, s3, 0, v48, s3
	s_waitcnt lgkmcnt(1)
	v_add_co_u32 v47, s3, v55, v45
	v_bfi_b32 v46, v60, v56, v57
	v_add_co_ci_u32_e64 v48, s3, 0, v49, s3
	v_bfi_b32 v49, v61, v59, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, v47, v46
	v_add_co_ci_u32_e64 v47, s3, v48, v49, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v46, s3, 0x698098d8, v46
	v_add_co_ci_u32_e64 v47, s3, 0, v47, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[47:48], 7, v[46:47]
	v_lshrrev_b32_e32 v46, 25, v46
	v_add_co_u32 v47, s3, v47, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v53, s3, v48, v61, s3
	v_add_co_u32 v62, s3, v47, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v63, s3, 0, v53, s3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v54, s3, v57, v52
	v_bfi_b32 v53, v62, v60, v56
	v_add_co_ci_u32_e64 v55, s3, 0, v58, s3
	v_bfi_b32 v57, v63, v61, v59
	ds_load_b32 v46, v38
	ds_load_b32 v48, v39
	ds_load_b32 v49, v40
	ds_load_b32 v51, v41
	ds_load_b32 v47, v42
	ds_load_b32 v50, v43
	v_add_co_u32 v53, s3, v54, v53
	ds_store_2addr_b32 v44, v45, v52 offset1:32
	ds_store_2addr_b32 v22, v3, v4 offset1:32
	ds_store_2addr_b32 v22, v5, v6 offset0:64 offset1:96
	v_add_co_ci_u32_e64 v54, s3, v55, v57, s3
	v_add_co_u32 v53, s3, 0x8b44f7af, v53
	ds_store_2addr_b32 v22, v0, v1 offset0:128 offset1:160
	ds_store_2addr_b32 v22, v2, v7 offset0:192 offset1:224
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_waitcnt lgkmcnt(9)
	ds_store_2addr_b32 v44, v46, v48 offset0:64 offset1:96
	s_waitcnt lgkmcnt(8)
	ds_store_2addr_b32 v44, v49, v51 offset0:128 offset1:160
	v_lshlrev_b64 v[54:55], 12, v[53:54]
	v_lshrrev_b32_e32 v53, 20, v53
	s_waitcnt lgkmcnt(7)
	ds_store_2addr_b32 v44, v47, v50 offset0:192 offset1:224
	v_add_co_u32 v54, s3, v54, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v57, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v56, v46
	v_bfi_b32 v53, v57, v62, v60
	v_add_co_ci_u32_e64 v55, s3, 0, v59, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v56, v58, v63, v61
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v56, s3
	v_add_co_u32 v53, s3, 0xffff5bb1, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 17, v[53:54]
	v_lshrrev_b32_e32 v53, 15, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s3, v54, v53
	v_add_co_ci_u32_e64 v59, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v60, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v56, v57, v62
	v_add_co_ci_u32_e64 v55, s3, 0, v61, s3
	v_bfi_b32 v60, v59, v58, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v60, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x895cd7be, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 22, v[53:54]
	v_lshrrev_b32_e32 v53, 10, v53
	v_add_co_u32 v54, s3, v54, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v59, s3
	v_add_co_u32 v60, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v61, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v62, v49
	v_bfi_b32 v53, v60, v56, v57
	v_add_co_ci_u32_e64 v55, s3, 0, v63, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v62, v61, v59, v58
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v62, s3
	v_add_co_u32 v53, s3, 0x6b901122, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 7, v[53:54]
	v_lshrrev_b32_e32 v53, 25, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v60
	v_add_co_ci_u32_e64 v55, s3, v55, v61, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v62, s3, v54, v53
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v57, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v62, v60, v56
	v_add_co_ci_u32_e64 v55, s3, 0, v58, s3
	v_bfi_b32 v57, v63, v61, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v57, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xfd987193, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 12, v[53:54]
	v_lshrrev_b32_e32 v53, 20, v53
	v_add_co_u32 v54, s3, v54, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v57, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v47, v56
	v_bfi_b32 v53, v57, v62, v60
	v_add_co_ci_u32_e64 v55, s3, 0, v59, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v56, v58, v63, v61
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v56, s3
	v_add_co_u32 v53, s3, 0xa679438e, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 17, v[53:54]
	v_lshrrev_b32_e32 v53, 15, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s3, v54, v53
	v_add_co_ci_u32_e64 v59, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v50, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v56, v57, v62
	v_add_co_ci_u32_e64 v55, s3, 0, v61, s3
	v_bfi_b32 v60, v59, v58, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v60, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x49b40821, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 22, v[53:54]
	v_lshrrev_b32_e32 v53, 10, v53
	v_add_co_u32 v54, s3, v54, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v59, s3
	v_add_co_u32 v60, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v61, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v4, v62
	v_bfi_b32 v53, v57, v60, v56
	v_add_co_ci_u32_e64 v55, s3, 0, v63, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v62, v58, v61, v59
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v62, s3
	v_add_co_u32 v53, s3, 0xf61e2562, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 5, v[53:54]
	v_lshrrev_b32_e32 v53, 27, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v60
	v_add_co_ci_u32_e64 v55, s3, v55, v61, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v62, s3, v54, v53
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v2, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v56, v62, v60
	v_add_co_ci_u32_e64 v55, s3, 0, v58, s3
	v_bfi_b32 v57, v59, v63, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v57, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xc040b340, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 9, v[53:54]
	v_lshrrev_b32_e32 v53, 23, v53
	v_add_co_u32 v54, s3, v54, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v57, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v48, v56
	v_bfi_b32 v53, v60, v57, v62
	v_add_co_ci_u32_e64 v55, s3, 0, v59, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v56, v61, v58, v63
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v56, s3
	v_add_co_u32 v53, s3, 0x265e5a51, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 14, v[53:54]
	v_lshrrev_b32_e32 v53, 18, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s3, v54, v53
	v_add_co_ci_u32_e64 v59, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v3, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v62, v56, v57
	v_add_co_ci_u32_e64 v55, s3, 0, v61, s3
	v_bfi_b32 v60, v63, v59, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v60, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xe9b6c7aa, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 20, v[53:54]
	v_lshrrev_b32_e32 v53, 12, v53
	v_add_co_u32 v54, s3, v54, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v59, s3
	v_add_co_u32 v60, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v61, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v1, v62
	v_bfi_b32 v53, v57, v60, v56
	v_add_co_ci_u32_e64 v55, s3, 0, v63, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v62, v58, v61, v59
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v62, s3
	v_add_co_u32 v53, s3, 0xd62f105d, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 5, v[53:54]
	v_lshrrev_b32_e32 v53, 27, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v60
	v_add_co_ci_u32_e64 v55, s3, v55, v61, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v62, s3, v54, v53
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v46, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v56, v62, v60
	v_add_co_ci_u32_e64 v55, s3, 0, v58, s3
	v_bfi_b32 v57, v59, v63, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v57, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x2441453, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 9, v[53:54]
	v_lshrrev_b32_e32 v53, 23, v53
	v_add_co_u32 v54, s3, v54, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v57, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v50, v56
	v_bfi_b32 v53, v60, v57, v62
	v_add_co_ci_u32_e64 v55, s3, 0, v59, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v56, v61, v58, v63
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v56, s3
	v_add_co_u32 v53, s3, 0xd8a1e681, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 14, v[53:54]
	v_lshrrev_b32_e32 v53, 18, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s3, v54, v53
	v_add_co_ci_u32_e64 v59, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v0, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v62, v56, v57
	v_add_co_ci_u32_e64 v55, s3, 0, v61, s3
	v_bfi_b32 v60, v63, v59, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v60, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xe7d3fbc8, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 20, v[53:54]
	v_lshrrev_b32_e32 v53, 12, v53
	v_add_co_u32 v54, s3, v54, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v59, s3
	v_add_co_u32 v60, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v61, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v52, v62
	v_bfi_b32 v53, v57, v60, v56
	v_add_co_ci_u32_e64 v55, s3, 0, v63, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v62, v58, v61, v59
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v62, s3
	v_add_co_u32 v53, s3, 0x21e1cde6, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 5, v[53:54]
	v_lshrrev_b32_e32 v53, 27, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v60
	v_add_co_ci_u32_e64 v55, s3, v55, v61, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v62, s3, v54, v53
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v47, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v56, v62, v60
	v_add_co_ci_u32_e64 v55, s3, 0, v58, s3
	v_bfi_b32 v57, v59, v63, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v57, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xc33707d6, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 9, v[53:54]
	v_lshrrev_b32_e32 v53, 23, v53
	v_add_co_u32 v54, s3, v54, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v57, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v6, v56
	v_bfi_b32 v53, v60, v57, v62
	v_add_co_ci_u32_e64 v55, s3, 0, v59, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v56, v61, v58, v63
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v56, s3
	v_add_co_u32 v53, s3, 0xf4d50d87, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 14, v[53:54]
	v_lshrrev_b32_e32 v53, 18, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s3, v54, v53
	v_add_co_ci_u32_e64 v59, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v45, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v62, v56, v57
	v_add_co_ci_u32_e64 v55, s3, 0, v61, s3
	v_bfi_b32 v60, v63, v59, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v60, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x455a14ed, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 20, v[53:54]
	v_lshrrev_b32_e32 v53, 12, v53
	v_add_co_u32 v54, s3, v54, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v59, s3
	v_add_co_u32 v60, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v61, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v51, v62
	v_bfi_b32 v53, v57, v60, v56
	v_add_co_ci_u32_e64 v55, s3, 0, v63, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v62, v58, v61, v59
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v62, s3
	v_add_co_u32 v53, s3, 0xa9e3e905, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 5, v[53:54]
	v_lshrrev_b32_e32 v53, 27, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v60
	v_add_co_ci_u32_e64 v55, s3, v55, v61, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v62, s3, v54, v53
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v5, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v56, v62, v60
	v_add_co_ci_u32_e64 v55, s3, 0, v58, s3
	v_bfi_b32 v57, v59, v63, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v57, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xfcefa3f8, v53
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 9, v[53:54]
	v_lshrrev_b32_e32 v53, 23, v53
	v_add_co_u32 v54, s3, v54, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v57, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v7, v56
	v_bfi_b32 v53, v60, v57, v62
	v_add_co_ci_u32_e64 v55, s3, 0, v59, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v56, v61, v58, v63
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v56, s3
	v_add_co_u32 v53, s3, 0x676f02d9, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 14, v[53:54]
	v_lshrrev_b32_e32 v53, 18, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v56, s3, v54, v53
	v_add_co_ci_u32_e64 v59, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v49, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v53, v62, v56, v57
	v_add_co_ci_u32_e64 v55, s3, 0, v61, s3
	v_bfi_b32 v60, v63, v59, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v60, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0x8d2a4c8a, v53
	v_xor_b32_e32 v60, v56, v57
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 20, v[53:54]
	v_lshrrev_b32_e32 v53, 12, v53
	v_add_co_u32 v54, s3, v54, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v59, s3
	v_add_co_u32 v61, s3, v54, v53
	v_xor_b32_e32 v53, v59, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_xor_b32_e32 v54, v61, v60
	v_add_co_u32 v55, s3, v1, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v60, s3, 0, v63, s3
	v_xor_b32_e32 v53, v64, v53
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v60, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xfffa3942, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 4, v[53:54]
	v_lshrrev_b32_e32 v53, 28, v53
	v_add_co_u32 v54, s3, v54, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	v_add_co_u32 v60, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v45, v57
	v_xor_b32_e32 v63, v60, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v65, v62, v64
	v_add_co_ci_u32_e64 v55, s3, 0, v58, s3
	v_xor_b32_e32 v53, v63, v56
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v57, v65, v59
	v_add_co_u32 v53, s3, v54, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, v55, v57, s3
	v_add_co_u32 v53, s3, 0x8771f681, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	v_lshlrev_b64 v[54:55], 11, v[53:54]
	v_lshrrev_b32_e32 v53, 21, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v60, v54
	v_add_co_ci_u32_e64 v55, s3, v62, v55, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v57, s3, v54, v53
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_add_co_u32 v54, s3, v48, v56
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v53, v63, v57
	v_add_co_ci_u32_e64 v55, s3, 0, v59, s3
	v_xor_b32_e32 v56, v65, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, v54, v53
	v_add_co_ci_u32_e64 v54, s3, v55, v56, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0x6d9d6122, v53
	v_xor_b32_e32 v56, v57, v60
	v_add_co_ci_u32_e64 v54, s3, 0, v54, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 16, v[53:54]
	v_lshrrev_b32_e32 v53, 16, v53
	v_add_co_u32 v54, s3, v54, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	v_add_co_u32 v59, s3, v54, v53
	v_xor_b32_e32 v53, v58, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v59
	v_add_co_u32 v55, s3, v47, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	v_xor_b32_e32 v53, v53, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xfde5380c, v54
	v_xor_b32_e32 v56, v59, v57
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 23, v[53:54]
	v_lshrrev_b32_e32 v53, 9, v53
	v_add_co_u32 v54, s3, v54, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v61, s3, v54, v53
	v_xor_b32_e32 v53, v63, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v61
	v_add_co_u32 v55, s3, v4, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v62, s3
	v_xor_b32_e32 v53, v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xa4beea44, v54
	v_xor_b32_e32 v56, v61, v59
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 4, v[53:54]
	v_lshrrev_b32_e32 v53, 28, v53
	v_add_co_u32 v54, s3, v54, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	v_add_co_u32 v60, s3, v54, v53
	v_xor_b32_e32 v53, v64, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v60
	v_add_co_u32 v55, s3, v0, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v58, s3
	v_xor_b32_e32 v53, v53, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0x4bdecfa9, v54
	v_xor_b32_e32 v56, v60, v61
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 11, v[53:54]
	v_lshrrev_b32_e32 v53, 21, v53
	v_add_co_u32 v54, s3, v54, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v62, s3
	v_add_co_u32 v57, s3, v54, v53
	v_xor_b32_e32 v53, v62, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v57
	v_add_co_u32 v55, s3, v7, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v63, s3
	v_xor_b32_e32 v53, v53, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xf6bb4b60, v54
	v_xor_b32_e32 v56, v57, v60
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 16, v[53:54]
	v_lshrrev_b32_e32 v53, 16, v53
	v_add_co_u32 v54, s3, v54, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	v_add_co_u32 v59, s3, v54, v53
	v_xor_b32_e32 v53, v58, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v59
	v_add_co_u32 v55, s3, v46, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	v_xor_b32_e32 v53, v53, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xbebfbc70, v54
	v_xor_b32_e32 v56, v59, v57
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 23, v[53:54]
	v_lshrrev_b32_e32 v53, 9, v53
	v_add_co_u32 v54, s3, v54, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v61, s3, v54, v53
	v_xor_b32_e32 v53, v63, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v61
	v_add_co_u32 v55, s3, v51, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v62, s3
	v_xor_b32_e32 v53, v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0x289b7ec6, v54
	v_xor_b32_e32 v56, v61, v59
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 4, v[53:54]
	v_lshrrev_b32_e32 v53, 28, v53
	v_add_co_u32 v54, s3, v54, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	v_add_co_u32 v60, s3, v54, v53
	v_xor_b32_e32 v53, v64, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v60
	v_add_co_u32 v55, s3, v3, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v58, s3
	v_xor_b32_e32 v53, v53, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xeaa127fa, v54
	v_xor_b32_e32 v56, v60, v61
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 11, v[53:54]
	v_lshrrev_b32_e32 v53, 21, v53
	v_add_co_u32 v54, s3, v54, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v62, s3
	v_add_co_u32 v57, s3, v54, v53
	v_xor_b32_e32 v53, v62, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v57
	v_add_co_u32 v55, s3, v6, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v63, s3
	v_xor_b32_e32 v53, v53, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xd4ef3085, v54
	v_xor_b32_e32 v56, v57, v60
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 16, v[53:54]
	v_lshrrev_b32_e32 v53, 16, v53
	v_add_co_u32 v54, s3, v54, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	v_add_co_u32 v59, s3, v54, v53
	v_xor_b32_e32 v53, v58, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v59
	v_add_co_u32 v55, s3, v2, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	v_xor_b32_e32 v53, v53, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0x4881d05, v54
	v_xor_b32_e32 v56, v59, v57
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 23, v[53:54]
	v_lshrrev_b32_e32 v53, 9, v53
	v_add_co_u32 v54, s3, v54, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v61, s3, v54, v53
	v_xor_b32_e32 v53, v63, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v61
	v_add_co_u32 v55, s3, v52, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v62, s3
	v_xor_b32_e32 v53, v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xd9d4d039, v54
	v_xor_b32_e32 v56, v61, v59
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 4, v[53:54]
	v_lshrrev_b32_e32 v53, 28, v53
	v_add_co_u32 v54, s3, v54, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	v_add_co_u32 v60, s3, v54, v53
	v_xor_b32_e32 v53, v64, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v60
	v_add_co_u32 v55, s3, v49, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v58, s3
	v_xor_b32_e32 v53, v53, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xe6db99e5, v54
	v_xor_b32_e32 v56, v60, v61
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 11, v[53:54]
	v_lshrrev_b32_e32 v53, 21, v53
	v_add_co_u32 v54, s3, v54, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v62, s3
	v_add_co_u32 v57, s3, v54, v53
	v_xor_b32_e32 v53, v62, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v57
	v_add_co_u32 v55, s3, v50, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v63, s3
	v_xor_b32_e32 v53, v53, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0x1fa27cf8, v54
	v_xor_b32_e32 v56, v57, v60
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 16, v[53:54]
	v_lshrrev_b32_e32 v53, 16, v53
	v_add_co_u32 v54, s3, v54, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	v_add_co_u32 v59, s3, v54, v53
	v_xor_b32_e32 v53, v58, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	v_xor_b32_e32 v54, v56, v59
	v_add_co_u32 v55, s3, v5, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	v_xor_b32_e32 v53, v53, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v53, s3, 0xc4ac5665, v54
	v_not_b32_e32 v56, v57
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 23, v[53:54]
	v_lshrrev_b32_e32 v53, 9, v53
	v_add_co_u32 v54, s3, v54, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v61, s3, v54, v53
	v_not_b32_e32 v53, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_or_b32_e32 v54, v61, v56
	v_add_co_u32 v55, s3, v3, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v64, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v62, s3
	v_xor_b32_e32 v54, v54, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v63
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v59
	v_add_co_u32 v53, s3, 0xf4292244, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 6, v[53:54]
	v_lshrrev_b32_e32 v53, 26, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v61
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v60, s3, v54, v53
	v_not_b32_e32 v53, v63
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v54, v60, v56
	v_add_co_u32 v55, s3, v7, v57
	v_or_b32_e32 v53, v62, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v58, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v54, v54, v61
	v_xor_b32_e32 v53, v53, v64
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x432aff97, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 10, v[53:54]
	v_lshrrev_b32_e32 v53, 22, v53
	v_add_co_u32 v54, s3, v54, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v62, s3
	v_add_co_u32 v57, s3, v54, v53
	v_not_b32_e32 v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_or_b32_e32 v54, v57, v56
	v_add_co_u32 v55, s3, v47, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v58, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v63, s3
	v_xor_b32_e32 v54, v54, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v62
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v60
	v_add_co_u32 v53, s3, 0xab9423a7, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 15, v[53:54]
	v_lshrrev_b32_e32 v53, 17, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v59, s3, v54, v53
	v_not_b32_e32 v53, v62
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v54, v59, v56
	v_add_co_u32 v55, s3, v1, v61
	v_or_b32_e32 v53, v63, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v54, v54, v57
	v_xor_b32_e32 v53, v53, v58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xfc93a039, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 21, v[53:54]
	v_lshrrev_b32_e32 v53, 11, v53
	v_add_co_u32 v54, s3, v54, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v61, s3, v54, v53
	v_not_b32_e32 v53, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_or_b32_e32 v54, v61, v56
	v_add_co_u32 v55, s3, v49, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v64, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v62, s3
	v_xor_b32_e32 v54, v54, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v63
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v59
	v_add_co_u32 v53, s3, 0x655b59c3, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 6, v[53:54]
	v_lshrrev_b32_e32 v53, 26, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v61
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v60, s3, v54, v53
	v_not_b32_e32 v53, v63
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v54, v60, v56
	v_add_co_u32 v55, s3, v6, v57
	v_or_b32_e32 v53, v62, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v58, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v54, v54, v61
	v_xor_b32_e32 v53, v53, v64
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x8f0ccc92, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 10, v[53:54]
	v_lshrrev_b32_e32 v53, 22, v53
	v_add_co_u32 v54, s3, v54, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v62, s3
	v_add_co_u32 v57, s3, v54, v53
	v_not_b32_e32 v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_or_b32_e32 v54, v57, v56
	v_add_co_u32 v55, s3, v46, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v58, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v63, s3
	v_xor_b32_e32 v54, v54, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v62
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v60
	v_add_co_u32 v53, s3, 0xffeff47d, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 15, v[53:54]
	v_lshrrev_b32_e32 v53, 17, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v59, s3, v54, v53
	v_not_b32_e32 v53, v62
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v54, v59, v56
	v_add_co_u32 v55, s3, v4, v61
	v_or_b32_e32 v53, v63, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v54, v54, v57
	v_xor_b32_e32 v53, v53, v58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x85845dd1, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 21, v[53:54]
	v_lshrrev_b32_e32 v53, 11, v53
	v_add_co_u32 v54, s3, v54, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v61, s3, v54, v53
	v_not_b32_e32 v53, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_or_b32_e32 v54, v61, v56
	v_add_co_u32 v55, s3, v45, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v64, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v62, s3
	v_xor_b32_e32 v54, v54, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v63
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v59
	v_add_co_u32 v53, s3, 0x6fa87e4f, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 6, v[53:54]
	v_lshrrev_b32_e32 v53, 26, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v61
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v60, s3, v54, v53
	v_not_b32_e32 v53, v63
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v54, v60, v56
	v_add_co_u32 v55, s3, v50, v57
	v_or_b32_e32 v53, v62, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v58, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v54, v54, v61
	v_xor_b32_e32 v53, v53, v64
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xfe2ce6e0, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 10, v[53:54]
	v_lshrrev_b32_e32 v53, 22, v53
	v_add_co_u32 v54, s3, v54, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v62, s3
	v_add_co_u32 v57, s3, v54, v53
	v_not_b32_e32 v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_or_b32_e32 v54, v57, v56
	v_add_co_u32 v55, s3, v2, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v58, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v63, s3
	v_xor_b32_e32 v54, v54, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v62
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v60
	v_add_co_u32 v53, s3, 0xa3014314, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 15, v[53:54]
	v_lshrrev_b32_e32 v53, 17, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v59, s3, v54, v53
	v_not_b32_e32 v53, v62
	v_add_co_ci_u32_e64 v63, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v54, v59, v56
	v_add_co_u32 v55, s3, v51, v61
	v_or_b32_e32 v53, v63, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v54, v54, v57
	v_xor_b32_e32 v53, v53, v58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0x4e0811a1, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 21, v[53:54]
	v_lshrrev_b32_e32 v53, 11, v53
	v_add_co_u32 v54, s3, v54, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v63, s3
	v_add_co_u32 v61, s3, v54, v53
	v_not_b32_e32 v53, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v64, s3, 0, v55, s3
	v_or_b32_e32 v54, v61, v56
	v_add_co_u32 v55, s3, v0, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v64, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v62, s3
	v_xor_b32_e32 v54, v54, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v63
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v59
	v_add_co_u32 v53, s3, 0xf7537e82, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 6, v[53:54]
	v_lshrrev_b32_e32 v53, 26, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v61
	v_add_co_ci_u32_e64 v55, s3, v55, v64, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v60, s3, v54, v53
	v_not_b32_e32 v53, v63
	v_add_co_ci_u32_e64 v62, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v54, v60, v56
	v_add_co_u32 v55, s3, v48, v57
	v_or_b32_e32 v53, v62, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v58, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v54, v54, v61
	v_add_nc_u32_e32 v9, v9, v60
	v_xor_b32_e32 v53, v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v55, v54
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v53, s3, 0xbd3af235, v54
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[54:55], 10, v[53:54]
	v_lshrrev_b32_e32 v53, 22, v53
	v_add_co_u32 v54, s3, v54, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v55, v62, s3
	v_add_co_u32 v57, s3, v54, v53
	v_not_b32_e32 v53, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v58, s3, 0, v55, s3
	v_or_b32_e32 v54, v57, v56
	v_add_co_u32 v55, s3, v5, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_or_b32_e32 v53, v58, v53
	v_add_co_ci_u32_e64 v56, s3, 0, v63, s3
	v_xor_b32_e32 v54, v54, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v53, v53, v62
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_not_b32_e32 v56, v60
	v_add_co_u32 v53, s3, 0x2ad7d2bb, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshlrev_b64 v[54:55], 15, v[53:54]
	v_lshrrev_b32_e32 v53, 17, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v54, s3, v54, v57
	v_add_co_ci_u32_e64 v55, s3, v55, v58, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v59, s3, v54, v53
	v_not_b32_e32 v53, v62
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v55, v59, v56
	v_or_b32_e32 v53, v54, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v54, v55, v57
	v_add_co_u32 v55, s3, v52, v61
	v_add_co_ci_u32_e64 v56, s3, 0, v64, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v53, v53, v58
	v_add_co_u32 v54, s3, v55, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v55, s3, v56, v53, s3
	v_add_co_u32 v53, s3, 0xeb86d391, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v54, s3, 0, v55, s3
	v_lshrrev_b32_e32 v0, 11, v53
	v_add_co_u32 v13, s3, v59, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 21, v[53:54]
	v_add_co_u32 v4, s3, v59, v16
	v_add_co_u32 v14, s3, v57, v14
	v_add_co_u32 v1, s3, v4, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v16, s3, v1, v0
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_3
; %bb.15:                               ; %Flow192
	s_or_b32 exec_lo, exec_lo, s9
.LBB1_16:                               ; %Flow193
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b64 s[0:1], s[0:1], 0x18
	v_lshlrev_b32_e32 v0, 2, v8
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v9, off
.LBB1_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11md5_overlapPhiiiiS_
		.amdhsa_group_segment_fixed_size 16256
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 66
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11md5_overlapPhiiiiS_, .Lfunc_end1-_Z11md5_overlapPhiiiiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10536
; NumSgprs: 18
; NumVgprs: 66
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16256 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 66
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16256
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3md5PhiiiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3md5PhiiiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     54
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16256
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11md5_overlapPhiiiiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11md5_overlapPhiiiiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     66
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
