#include <stdio.h>
#include <assert.h>
#include <time.h>
#include <cuda.h>

#define BLOCK_LOW(id,p,n) ((id)*(n)/(p))l;
#define BLOCK_HIGH(id,p,n) (BLOCK_LOW((id)+1,p,n)-1);
#define BLOCK_SIZE(id,p,n) (BLOCK_LOW((id)+1,p,n)-BLOCK_LOW(id,p,n));
#define BLOCK_OWNER(index,p,n) (((p)*((index)+1)-1)/(n));
int inputvalues[8] = {12010991,3059810,17756755,7362131,25485528,4134948,15051971,16947626};
//int inputvalues[8] = {100,3059810,17756755,7362131,25485528,4134948,15051971,16947626};
 
__global__ void seive(int *d_marked,int prime)
{
	
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int width=256;
	int idx=threadIdx.x;
	/*
	__shared__ int low_value =  blockIdx.x * blockDim.x + 0;
	__shared__ int high_value =  blockIdx.x * blockDim.x + blockDim.x;
	__shared__ int first;
	
    if (prime * prime > low_value)
         first = prime * prime - low_value;
      else {
         if (!(low_value % prime)) first = 0;
         else first = prime - (low_value % prime);
      }*/
	
	 __shared__ int  my_marked[256];
	
	 if( idx<width)	my_marked[idx]=d_marked[tid];

	
	
	  //if ((d_marked[tid]%prime)==0) d_marked[tid]=0 ;
	  if ((my_marked[idx]%prime)==0) d_marked[tid]=0 ;
	
	
}

int main (int argc, char** argv)
{
	int *h_marked;
	int *d_marked;
	int size;
	int i,ii,jj;
	int count=0;
	int prime=2;
	double t1, t2;
	FILE *f; 
	f =fopen("seive_CUDA_results.txt","w");
	fprintf(f,"index,counter,number,time,result\n");
	for (ii = 0;ii<8;ii++) 
	{
		size = inputvalues[ii];
		for(jj = 0;jj<10;jj++)
		{
	// Allocate host memory
	t1=clock();
	h_marked = (int *)malloc (size*sizeof(int));
	
	for (i = 0; i < size; i++) {h_marked[i] = i;}
	 
	
	
	// Allocate device memory
	cudaMalloc((void **) &d_marked, size*sizeof(int));
	
	// Copy host data to device
	cudaMemcpy(d_marked,h_marked, size*sizeof(int),cudaMemcpyHostToDevice);
	///------------------------------
	int myn;
   myn=sqrt(size)+1;
   
   	int *intarray = (int *) malloc(myn * sizeof(int));
	int *primearray = NULL;
	int  j = 0;
	int primecounter = 0;
	
	for(i = 0; i < myn; i++)
		intarray[i] = 0;
		
	/* at positions where there are multiples of i, mark as zero */
  for( i = 2; i * i < myn; i++ )
	if( intarray[i]==0 )
	  for( j = i + i; j < myn; j += i )
		intarray[j] = 1;

	  /* count all values that haven't been marked */
  for( j = 2; j < myn; j++ )
	if(intarray[j]==0)
	  primecounter++;
  
  primearray = (int *) malloc(primecounter  * sizeof(int));
  
  for(i = 0; i < primecounter; i++)
		primearray[i] = i;
		
   /* store all prime numbers from intarray into primearray */
  i=0;
  for( j = 2; j < myn; j++ )
	if(intarray[j]==0)	  {primearray[i] = j; i++;}
	///-----------------------------------
	// Launch Kernel

	/*dim3 dimGrid(1,1);
	dim3 dimBlock(128,1);
	
	seive <<< dimGrid,dimBlock >>> (d_marked,prime); */
   int block_size = 256;
   int n_blocks = size/block_size + (size%block_size == 0 ? 0:1);
   for(i=0;i<primecounter;i++){
   prime=primearray[i];
   seive <<< n_blocks, block_size >>> (d_marked, prime);
	}
	// Copy device data to host
	cudaMemcpy(h_marked,d_marked,size*sizeof(int),cudaMemcpyDeviceToHost);
	
	//for (i = 0; i < size; i++) printf("  %d ",h_marked[i]);
	count=0;
	for (i = 4; i < size; i++) if(h_marked[i]!=0) count++;
	t2 = clock();
	
	// Free memory locations
	cudaFree(d_marked); free(h_marked) ;
	
	fprintf(f,"%d,%d,%d,%.6f,%d\n",ii,jj,size,(t2-t1)/CLOCKS_PER_SEC,count+primecounter);
					 
	printf("%d,%d,%d %.6f seconds ",ii,jj,size,(t2-t1)/CLOCKS_PER_SEC);
  	printf(" # of primes is %d\n",count+primecounter);
					  
		}
	}
	fclose(f);
	
}




	.file	"tmpxft_0021bd89_00000000-6_prime_number.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z25__device_stub__Z5seivePiiPii
	.type	_Z25__device_stub__Z5seivePiiPii, @function
_Z25__device_stub__Z5seivePiiPii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5seivePii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z25__device_stub__Z5seivePiiPii, .-_Z25__device_stub__Z5seivePiiPii
	.globl	_Z5seivePii
	.type	_Z5seivePii, @function
_Z5seivePii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z5seivePiiPii
	.cfi_endproc
.LFE2053:
	.size	_Z5seivePii, .-_Z5seivePii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"w"
.LC1:
	.string	"seive_CUDA_results.txt"
.LC2:
	.string	"index,counter,number,time,result\n"
.LC5:
	.string	"%d,%d,%d,%.6f,%d\n"
.LC6:
	.string	"%d,%d,%d %.6f seconds "
.LC7:
	.string	" # of primes is %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	leaq	.LC1(%rip), %rdi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	leaq	.LC2(%rip), %rdx
	movl	$2, %esi
	movq	%rax, 8(%rsp)
	movq	%rax, %rdi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L34:
	leaq	inputvalues(%rip), %rax
	xorl	%esi, %esi
	movl	$256, %ecx
	movl	%r13d, 20(%rsp)
	movslq	(%rax,%r13,4), %rax
	movq	%rax, %rbx
	salq	$2, %rax
	movq	%rax, (%rsp)
	testb	%bl, %bl
	movl	%ebx, %eax
	setne	%sil
	cltd
	xorl	%edi, %edi
	idivl	%ecx
	movl	%edi, 16(%rsp)
	addl	%esi, %eax
	movl	%eax, 40(%rsp)
.L33:
	call	clock@PLT
	movq	(%rsp), %rdi
	cvtsi2sdq	%rax, %xmm1
	movsd	%xmm1, 24(%rsp)
	call	malloc@PLT
	movq	%rax, %rbp
	xorl	%eax, %eax
.L9:
	cmpl	%eax, %ebx
	jle	.L39
	movl	%eax, 0(%rbp,%rax,4)
	incq	%rax
	jmp	.L9
.L39:
	movq	(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cvtsi2sdl	%ebx, %xmm0
	call	sqrt@PLT
	addsd	.LC3(%rip), %xmm0
	cvttsd2sil	%xmm0, %r15d
	movslq	%r15d, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, %rdx
	xorl	%eax, %eax
.L11:
	cmpl	%eax, %r15d
	jle	.L40
	xorl	%esi, %esi
	movl	%esi, (%rdx,%rax,4)
	incq	%rax
	jmp	.L11
.L40:
	movl	$2, %eax
.L13:
	movl	%eax, %esi
	imull	%eax, %esi
	cmpl	%r15d, %esi
	jge	.L41
	cmpl	$0, (%rdx,%rax,4)
	je	.L14
.L17:
	incq	%rax
	jmp	.L13
.L14:
	leal	(%rax,%rax), %esi
	movslq	%esi, %rsi
.L15:
	cmpl	%esi, %r15d
	jle	.L17
	movl	$1, (%rdx,%rsi,4)
	addq	%rax, %rsi
	jmp	.L15
.L41:
	movl	$2, %eax
	xorl	%r12d, %r12d
.L19:
	cmpl	%eax, %r15d
	jle	.L42
	cmpl	$0, (%rdx,%rax,4)
	jne	.L20
	incl	%r12d
.L20:
	incq	%rax
	jmp	.L19
.L42:
	movslq	%r12d, %rdi
	movq	%rdx, 32(%rsp)
	salq	$2, %rdi
	call	malloc@PLT
	movq	32(%rsp), %rdx
	movq	%rax, %r14
	xorl	%eax, %eax
.L22:
	cmpl	%eax, %r12d
	jle	.L43
	movl	%eax, (%r14,%rax,4)
	incq	%rax
	jmp	.L22
.L43:
	movl	$2, %eax
	xorl	%esi, %esi
.L24:
	cmpl	%eax, %r15d
	jle	.L44
	cmpl	$0, (%rdx,%rax,4)
	jne	.L25
	movslq	%esi, %rdi
	incl	%esi
	movl	%eax, (%r14,%rdi,4)
.L25:
	incq	%rax
	jmp	.L24
.L44:
	xorl	%r15d, %r15d
.L27:
	cmpl	%r15d, %r12d
	jle	.L45
	movl	(%r14,%r15,4), %eax
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	movl	$1, %ecx
	movl	%eax, 32(%rsp)
	movl	40(%rsp), %eax
	movl	%eax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movl	32(%rsp), %esi
	movq	56(%rsp), %rdi
	call	_Z25__device_stub__Z5seivePiiPii
.L28:
	incq	%r15
	jmp	.L27
.L45:
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movl	$4, %eax
	xorl	%edx, %edx
.L30:
	cmpl	%eax, %ebx
	jle	.L46
	cmpl	$0, 0(%rbp,%rax,4)
	je	.L31
	incl	%edx
.L31:
	incq	%rax
	jmp	.L30
.L46:
	movl	%edx, 44(%rsp)
	call	clock@PLT
	movq	56(%rsp), %rdi
	cvtsi2sdq	%rax, %xmm0
	movsd	%xmm0, 32(%rsp)
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movl	44(%rsp), %edx
	movsd	32(%rsp), %xmm0
	movl	%ebx, %r9d
	subsd	24(%rsp), %xmm0
	pushq	%rax
	.cfi_def_cfa_offset 168
	movb	$1, %al
	movl	$2, %esi
	addl	%edx, %r12d
	leaq	.LC5(%rip), %rdx
	divsd	.LC4(%rip), %xmm0
	pushq	%r12
	.cfi_def_cfa_offset 176
	movl	32(%rsp), %r8d
	movq	24(%rsp), %rdi
	movl	36(%rsp), %ecx
	movsd	%xmm0, 40(%rsp)
	call	__fprintf_chk@PLT
	popq	%rdx
	.cfi_def_cfa_offset 168
	popq	%rcx
	.cfi_def_cfa_offset 160
	movl	%ebx, %r8d
	movl	16(%rsp), %ecx
	movl	20(%rsp), %edx
	movl	$2, %edi
	movb	$1, %al
	movsd	24(%rsp), %xmm0
	leaq	.LC6(%rip), %rsi
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	%r12d, %edx
	movl	$2, %edi
	leaq	.LC7(%rip), %rsi
	call	__printf_chk@PLT
	incl	16(%rsp)
	cmpl	$10, 16(%rsp)
	jne	.L33
	incq	%r13
	cmpq	$8, %r13
	jne	.L34
	movq	8(%rsp), %rdi
	call	fclose@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z5seivePii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5seivePii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	inputvalues
	.data
	.align 32
	.type	inputvalues, @object
	.size	inputvalues, 32
inputvalues:
	.long	12010991
	.long	3059810
	.long	17756755
	.long	7362131
	.long	25485528
	.long	4134948
	.long	15051971
	.long	16947626
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1072693248
	.align 8
.LC4:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <assert.h>
#include <time.h>
#include <hip/hip_runtime.h>

#define BLOCK_LOW(id,p,n) ((id)*(n)/(p))l;
#define BLOCK_HIGH(id,p,n) (BLOCK_LOW((id)+1,p,n)-1);
#define BLOCK_SIZE(id,p,n) (BLOCK_LOW((id)+1,p,n)-BLOCK_LOW(id,p,n));
#define BLOCK_OWNER(index,p,n) (((p)*((index)+1)-1)/(n));
int inputvalues[8] = {12010991,3059810,17756755,7362131,25485528,4134948,15051971,16947626};
//int inputvalues[8] = {100,3059810,17756755,7362131,25485528,4134948,15051971,16947626};
 
__global__ void seive(int *d_marked,int prime)
{
	
    int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int width=256;
	int idx=threadIdx.x;
	/*
	__shared__ int low_value =  blockIdx.x * blockDim.x + 0;
	__shared__ int high_value =  blockIdx.x * blockDim.x + blockDim.x;
	__shared__ int first;
	
    if (prime * prime > low_value)
         first = prime * prime - low_value;
      else {
         if (!(low_value % prime)) first = 0;
         else first = prime - (low_value % prime);
      }*/
	
	 __shared__ int  my_marked[256];
	
	 if( idx<width)	my_marked[idx]=d_marked[tid];

	
	
	  //if ((d_marked[tid]%prime)==0) d_marked[tid]=0 ;
	  if ((my_marked[idx]%prime)==0) d_marked[tid]=0 ;
	
	
}

int main (int argc, char** argv)
{
	int *h_marked;
	int *d_marked;
	int size;
	int i,ii,jj;
	int count=0;
	int prime=2;
	double t1, t2;
	FILE *f; 
	f =fopen("seive_CUDA_results.txt","w");
	fprintf(f,"index,counter,number,time,result\n");
	for (ii = 0;ii<8;ii++) 
	{
		size = inputvalues[ii];
		for(jj = 0;jj<10;jj++)
		{
	// Allocate host memory
	t1=clock();
	h_marked = (int *)malloc (size*sizeof(int));
	
	for (i = 0; i < size; i++) {h_marked[i] = i;}
	 
	
	
	// Allocate device memory
	hipMalloc((void **) &d_marked, size*sizeof(int));
	
	// Copy host data to device
	hipMemcpy(d_marked,h_marked, size*sizeof(int),hipMemcpyHostToDevice);
	///------------------------------
	int myn;
   myn=sqrt(size)+1;
   
   	int *intarray = (int *) malloc(myn * sizeof(int));
	int *primearray = NULL;
	int  j = 0;
	int primecounter = 0;
	
	for(i = 0; i < myn; i++)
		intarray[i] = 0;
		
	/* at positions where there are multiples of i, mark as zero */
  for( i = 2; i * i < myn; i++ )
	if( intarray[i]==0 )
	  for( j = i + i; j < myn; j += i )
		intarray[j] = 1;

	  /* count all values that haven't been marked */
  for( j = 2; j < myn; j++ )
	if(intarray[j]==0)
	  primecounter++;
  
  primearray = (int *) malloc(primecounter  * sizeof(int));
  
  for(i = 0; i < primecounter; i++)
		primearray[i] = i;
		
   /* store all prime numbers from intarray into primearray */
  i=0;
  for( j = 2; j < myn; j++ )
	if(intarray[j]==0)	  {primearray[i] = j; i++;}
	///-----------------------------------
	// Launch Kernel

	/*dim3 dimGrid(1,1);
	dim3 dimBlock(128,1);
	
	seive <<< dimGrid,dimBlock >>> (d_marked,prime); */
   int block_size = 256;
   int n_blocks = size/block_size + (size%block_size == 0 ? 0:1);
   for(i=0;i<primecounter;i++){
   prime=primearray[i];
   seive <<< n_blocks, block_size >>> (d_marked, prime);
	}
	// Copy device data to host
	hipMemcpy(h_marked,d_marked,size*sizeof(int),hipMemcpyDeviceToHost);
	
	//for (i = 0; i < size; i++) printf("  %d ",h_marked[i]);
	count=0;
	for (i = 4; i < size; i++) if(h_marked[i]!=0) count++;
	t2 = clock();
	
	// Free memory locations
	hipFree(d_marked); free(h_marked) ;
	
	fprintf(f,"%d,%d,%d,%.6f,%d\n",ii,jj,size,(t2-t1)/CLOCKS_PER_SEC,count+primecounter);
					 
	printf("%d,%d,%d %.6f seconds ",ii,jj,size,(t2-t1)/CLOCKS_PER_SEC);
  	printf(" # of primes is %d\n",count+primecounter);
					  
		}
	}
	fclose(f);
	
}




	.text
	.file	"prime_number.hip"
	.globl	_Z20__device_stub__seivePii     # -- Begin function _Z20__device_stub__seivePii
	.type	_Z20__device_stub__seivePii,@function
_Z20__device_stub__seivePii:            # @_Z20__device_stub__seivePii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5seivePii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__seivePii, .Lfunc_end0-_Z20__device_stub__seivePii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x3ff0000000000000              # double 1
.LCPI1_1:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI1_2:
	.quad	0x0000000000000000              # double 0
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movl	$.L.str.2, %edi
	movl	$33, %esi
	movl	$1, %edx
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	%rax, %rcx
	callq	fwrite@PLT
	xorl	%ebx, %ebx
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
                                        #       Child Loop BB1_4 Depth 3
                                        #       Child Loop BB1_11 Depth 3
                                        #         Child Loop BB1_14 Depth 4
                                        #       Child Loop BB1_18 Depth 3
                                        #       Child Loop BB1_22 Depth 3
                                        #       Child Loop BB1_25 Depth 3
                                        #       Child Loop BB1_30 Depth 3
                                        #       Child Loop BB1_35 Depth 3
	movl	inputvalues(,%rbx,4), %r15d
	movslq	%r15d, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	leal	255(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%r15d, %ecx
	sarl	$8, %ecx
	cmpb	$1, %r15b
	sbbl	$-1, %ecx
	leaq	(,%rax,4), %r12
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rcx
	movq	%rcx, 80(%rsp)                  # 8-byte Spill
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
	sqrtsd	%xmm0, %xmm0
	movsd	%xmm0, 40(%rsp)                 # 8-byte Spill
	xorl	%r14d, %r14d
	movq	%rbx, 64(%rsp)                  # 8-byte Spill
	movq	%r15, 56(%rsp)                  # 8-byte Spill
	movq	%r12, 48(%rsp)                  # 8-byte Spill
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_4 Depth 3
                                        #       Child Loop BB1_11 Depth 3
                                        #         Child Loop BB1_14 Depth 4
                                        #       Child Loop BB1_18 Depth 3
                                        #       Child Loop BB1_22 Depth 3
                                        #       Child Loop BB1_25 Depth 3
                                        #       Child Loop BB1_30 Depth 3
                                        #       Child Loop BB1_35 Depth 3
	callq	clock
	movq	%rax, (%rsp)                    # 8-byte Spill
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %rbx
	testl	%r15d, %r15d
	jle	.LBB1_5
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	xorl	%eax, %eax
.LBB1_4:                                # %.lr.ph
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%eax, (%rbx,%rax,4)
	incq	%rax
	cmpq	%rax, %r15
	jne	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=2
	movl	%r14d, 20(%rsp)                 # 4-byte Spill
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	8(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movsd	32(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	ucomisd	.LCPI1_2(%rip), %xmm0
	movsd	40(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	jae	.LBB1_7
# %bb.6:                                # %call.sqrt
                                        #   in Loop: Header=BB1_2 Depth=2
	movsd	32(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	sqrt
.LBB1_7:                                # %._crit_edge.split
                                        #   in Loop: Header=BB1_2 Depth=2
	addsd	.LCPI1_0(%rip), %xmm0
	cvttsd2si	%xmm0, %r13d
	movslq	%r13d, %r14
	leaq	(,%r14,4), %rdi
	callq	malloc
	movq	%rax, %r15
	testl	%r14d, %r14d
	jle	.LBB1_8
# %bb.9:                                # %.preheader115
                                        #   in Loop: Header=BB1_2 Depth=2
	movl	%r13d, %ebp
	leaq	(,%rbp,4), %rdx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	cmpl	$5, %r13d
	jb	.LBB1_16
# %bb.10:                               # %.lr.ph124.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	movq	%r15, %rax
	addq	$16, %rax
	movl	$2, %ecx
	movl	$8, %edx
	movl	$4, %esi
.LBB1_11:                               # %.lr.ph124
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB1_14 Depth 4
	cmpl	$0, (%r15,%rcx,4)
	jne	.LBB1_15
# %bb.12:                               # %.lr.ph124
                                        #   in Loop: Header=BB1_11 Depth=3
	leal	(%rcx,%rcx), %edi
	cmpl	%r13d, %edi
	jge	.LBB1_15
# %bb.13:                               # %.lr.ph122.preheader
                                        #   in Loop: Header=BB1_11 Depth=3
	movl	%esi, %edi
	movq	%rax, %r8
.LBB1_14:                               # %.lr.ph122
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        #       Parent Loop BB1_11 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movl	$1, (%r8)
	addq	%rdx, %r8
	addl	%ecx, %edi
	cmpl	%r13d, %edi
	jl	.LBB1_14
.LBB1_15:                               # %.loopexit
                                        #   in Loop: Header=BB1_11 Depth=3
	incq	%rcx
	movq	%rcx, %rdi
	imulq	%rcx, %rdi
	addq	$8, %rax
	addq	$4, %rdx
	addl	$2, %esi
	cmpq	%r14, %rdi
	jl	.LBB1_11
.LBB1_16:                               # %.preheader114
                                        #   in Loop: Header=BB1_2 Depth=2
	xorl	%ecx, %ecx
	movl	$0, %r14d
	cmpl	$3, %r13d
	setge	%al
	jl	.LBB1_20
# %bb.17:                               # %.lr.ph127.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	xorl	%r14d, %r14d
	movl	$2, %ecx
.LBB1_18:                               # %.lr.ph127
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	cmpl	$1, (%r15,%rcx,4)
	adcl	$0, %r14d
	incq	%rcx
	cmpq	%rcx, %rbp
	jne	.LBB1_18
# %bb.19:                               #   in Loop: Header=BB1_2 Depth=2
	movl	%eax, %ecx
	jmp	.LBB1_20
.LBB1_8:                                #   in Loop: Header=BB1_2 Depth=2
	xorl	%ecx, %ecx
	xorl	%r14d, %r14d
.LBB1_20:                               # %._crit_edge128
                                        #   in Loop: Header=BB1_2 Depth=2
	movl	%ecx, 16(%rsp)                  # 4-byte Spill
	movslq	%r14d, %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	leaq	(,%rax,4), %rdi
	callq	malloc
	movq	%rax, %rbp
	movl	%r14d, %r12d
	cmpl	$0, 72(%rsp)                    # 4-byte Folded Reload
	jle	.LBB1_23
# %bb.21:                               # %.lr.ph131.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	xorl	%eax, %eax
.LBB1_22:                               # %.lr.ph131
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%eax, (%rbp,%rax,4)
	incq	%rax
	cmpq	%rax, %r12
	jne	.LBB1_22
.LBB1_23:                               # %.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	cmpb	$0, 16(%rsp)                    # 1-byte Folded Reload
	je	.LBB1_28
# %bb.24:                               # %.lr.ph134.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	movl	%r13d, %eax
	xorl	%ecx, %ecx
	movl	$2, %edx
.LBB1_25:                               # %.lr.ph134
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	cmpl	$0, (%r15,%rdx,4)
	jne	.LBB1_27
# %bb.26:                               #   in Loop: Header=BB1_25 Depth=3
	movslq	%ecx, %rcx
	movl	%edx, (%rbp,%rcx,4)
	incl	%ecx
.LBB1_27:                               #   in Loop: Header=BB1_25 Depth=3
	incq	%rdx
	cmpq	%rdx, %rax
	jne	.LBB1_25
.LBB1_28:                               # %._crit_edge135
                                        #   in Loop: Header=BB1_2 Depth=2
	testl	%r14d, %r14d
	jle	.LBB1_33
# %bb.29:                               # %.lr.ph138.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	xorl	%r13d, %r13d
.LBB1_30:                               # %.lr.ph138
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%rbp,%r13,4), %r15d
	movabsq	$4294967296, %rax               # imm = 0x100000000
	leaq	256(%rax), %rdx
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_32
# %bb.31:                               #   in Loop: Header=BB1_30 Depth=3
	movq	8(%rsp), %rdi
	movl	%r15d, %esi
	callq	_Z20__device_stub__seivePii
.LBB1_32:                               #   in Loop: Header=BB1_30 Depth=3
	incq	%r13
	cmpq	%r13, %r12
	jne	.LBB1_30
.LBB1_33:                               # %._crit_edge139
                                        #   in Loop: Header=BB1_2 Depth=2
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	48(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebp, %ebp
	movq	56(%rsp), %r15                  # 8-byte Reload
	cmpl	$5, %r15d
	jl	.LBB1_36
# %bb.34:                               # %.lr.ph143.preheader
                                        #   in Loop: Header=BB1_2 Depth=2
	xorl	%ebp, %ebp
	movl	$4, %eax
.LBB1_35:                               # %.lr.ph143
                                        #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	cmpl	$1, (%rbx,%rax,4)
	sbbl	$-1, %ebp
	incq	%rax
	cmpq	%rax, %r15
	jne	.LBB1_35
.LBB1_36:                               # %._crit_edge144
                                        #   in Loop: Header=BB1_2 Depth=2
	xorps	%xmm0, %xmm0
	cvtsi2sdq	(%rsp), %xmm0           # 8-byte Folded Reload
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	callq	clock
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	subsd	(%rsp), %xmm0                   # 8-byte Folded Reload
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	.LCPI1_1(%rip), %xmm0
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	addl	%r14d, %ebp
	movl	$.L.str.3, %esi
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	64(%rsp), %rbx                  # 8-byte Reload
	movl	%ebx, %edx
	movl	20(%rsp), %r14d                 # 4-byte Reload
	movl	%r14d, %ecx
	movl	%r15d, %r8d
	movl	%ebp, %r9d
	movb	$1, %al
	callq	fprintf
	movl	$.L.str.4, %edi
	movl	%ebx, %esi
	movl	%r14d, %edx
	movl	%r15d, %ecx
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.L.str.5, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	incl	%r14d
	cmpl	$10, %r14d
	jne	.LBB1_2
# %bb.37:                               #   in Loop: Header=BB1_1 Depth=1
	incq	%rbx
	cmpq	$8, %rbx
	jne	.LBB1_1
# %bb.38:
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	fclose
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5seivePii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	inputvalues,@object             # @inputvalues
	.data
	.globl	inputvalues
	.p2align	4, 0x0
inputvalues:
	.long	12010991                        # 0xb745ef
	.long	3059810                         # 0x2eb062
	.long	17756755                        # 0x10ef253
	.long	7362131                         # 0x705653
	.long	25485528                        # 0x184e0d8
	.long	4134948                         # 0x3f1824
	.long	15051971                        # 0xe5acc3
	.long	16947626                        # 0x10299aa
	.size	inputvalues, 32

	.type	_Z5seivePii,@object             # @_Z5seivePii
	.section	.rodata,"a",@progbits
	.globl	_Z5seivePii
	.p2align	3, 0x0
_Z5seivePii:
	.quad	_Z20__device_stub__seivePii
	.size	_Z5seivePii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"seive_CUDA_results.txt"
	.size	.L.str, 23

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"w"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"index,counter,number,time,result\n"
	.size	.L.str.2, 34

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d,%d,%d,%.6f,%d\n"
	.size	.L.str.3, 18

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d,%d,%d %.6f seconds "
	.size	.L.str.4, 23

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	" # of primes is %d\n"
	.size	.L.str.5, 20

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5seivePii"
	.size	.L__unnamed_1, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__seivePii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5seivePii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5seivePii             ; -- Begin function _Z5seivePii
	.globl	_Z5seivePii
	.p2align	8
	.type	_Z5seivePii,@function
_Z5seivePii:                            ; @_Z5seivePii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x0
	v_cmp_lt_u32_e32 vcc_lo, 0xff, v0
	v_lshlrev_b32_e32 v3, 2, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s4, vcc_lo
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_2
; %bb.1:                                ; %._crit_edge
	ds_load_b32 v0, v3
                                        ; implicit-def: $vgpr3
.LBB0_2:                                ; %Flow
	s_or_saveexec_b32 s4, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_xor_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v0
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s4
	s_load_b32 s0, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v5
	v_xor_b32_e32 v0, v0, v5
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s1
	s_xor_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s0
	s_sub_i32 s1, 0, s0
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_mul_lo_u32 v3, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v3
	v_subrev_nc_u32_e32 v3, s0, v0
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_subrev_nc_u32_e32 v3, s0, v0
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5seivePii
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5seivePii, .Lfunc_end0-_Z5seivePii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 388
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5seivePii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5seivePii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
