#include<cuda.h>
#include<stdio.h>

__global__ void VecAdd(float *A, float *B, float *C)
{
  int i = threadIdx.x;
  for(int j = 0; j < 1000; j++)
  C[i] = A[i] + B[i];
}

__global__ void VecMul(float *A, float *B, float *C)
{
  int i = threadIdx.x;
  for(int j = 0; j < 1000; j++)
  C[i] = A[i] * B[i];
}



int main()
{
  int N = 1024 * 10;
  dim3 threadPerBlock(256);
  dim3 numBlocks(N/threadPerBlock.x);

  cudaStream_t stream1, stream2;
  cudaStreamCreate(&stream1);
  cudaStreamCreate(&stream2);
  //cudaStreamCreateWithFlags(&stream1, cudaStreamNonBlocking);
  //cudaStreamCreateWithFlags(&stream2, cudaStreamNonBlocking);

  // Host memory.
  float *hA, *hB, *hC, *hAMul, *hBMul, *hCMul;
#if 0
  hA = (float*) malloc (sizeof(float) * N);
  hB = (float*) malloc (sizeof(float) * N);
  hC = (float*) malloc (sizeof(float) * N);
  hAMul = (float*) malloc (sizeof(float) * N);
  hBMul = (float*) malloc (sizeof(float) * N);
  hCMul = (float*) malloc (sizeof(float) * N);
#endif
  cudaMallocHost((void**)&hA, sizeof(float) * N); 
  cudaMallocHost((void**)&hB, sizeof(float) * N); 
  cudaMallocHost((void**)&hC, sizeof(float) * N); 
  cudaMallocHost((void**)&hAMul, sizeof(float) * N); 
  cudaMallocHost((void**)&hBMul, sizeof(float) * N); 
  cudaMallocHost((void**)&hCMul, sizeof(float) * N); 
  for(int i = 0; i < N; i++){
    hA[i] = i;
    hB[i] = i + 1;
    hC[i] = 0.0f;
    hAMul[i] = i % 10;
    hBMul[i] = i % 10;
    hCMul[i] = 0.0f;

  }

  // Device memory.
  float *A, *B, *C, *AMul, *BMul, *CMul;
  cudaMalloc((void**)&A, sizeof(float) * N); 
  cudaMalloc((void**)&B, sizeof(float) * N); 
  cudaMalloc((void**)&C, sizeof(float) * N); 
  cudaMalloc((void**)&AMul, sizeof(float) * N); 
  cudaMalloc((void**)&BMul, sizeof(float) * N); 
  cudaMalloc((void**)&CMul, sizeof(float) * N); 

  // Host->Device
  cudaMemcpyAsync(A, hA, sizeof(float)*N, cudaMemcpyHostToDevice, stream1);
  cudaMemcpyAsync(B, hB, sizeof(float)*N, cudaMemcpyHostToDevice, stream1);
  //cudaMemcpyAsync(C, hC, sizeof(float)*N, cudaMemcpyHostToDevice, stream1);
  VecAdd<<<numBlocks, threadPerBlock, 0, stream1>>>(A, B, C);

  cudaMemcpyAsync(AMul, hAMul, sizeof(float)*N, cudaMemcpyHostToDevice, stream2);
  cudaMemcpyAsync(BMul, hBMul, sizeof(float)*N, cudaMemcpyHostToDevice, stream2);
  VecMul<<<numBlocks, threadPerBlock, 0, stream2>>>(AMul, BMul, CMul);
  cudaMemcpyAsync(hC, C, sizeof(float)*N, cudaMemcpyDeviceToHost, stream1);
  cudaMemcpyAsync(hCMul, CMul, sizeof(float)*N, cudaMemcpyDeviceToHost, stream2);

  //cudaMemcpyAsync(BMul, hBMul, sizeof(float)*N, cudaMemcpyHostToDevice, stream2);
  //cudaMemcpyAsync(CMul, hCMul, sizeof(float)*N, cudaMemcpyHostToDevice, stream2);
  //cudaMemcpyAsync(hCMul, CMul, sizeof(float)*N, cudaMemcpyDeviceToDevice, stream2);
  cudaStreamSynchronize(stream1);
  cudaStreamSynchronize(stream2);

  printf("hC = %f, hCMul = %f \n", hC[10], hCMul[12]);
  return 0;
}

	.file	"tmpxft_0033c3f6_00000000-6_stream.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
	.type	_Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6VecAddPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
	.globl	_Z6VecAddPfS_S_
	.type	_Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
	.globl	_Z29__device_stub__Z6VecMulPfS_S_PfS_S_
	.type	_Z29__device_stub__Z6VecMulPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecMulPfS_S_PfS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6VecMulPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z29__device_stub__Z6VecMulPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecMulPfS_S_PfS_S_
	.globl	_Z6VecMulPfS_S_
	.type	_Z6VecMulPfS_S_, @function
_Z6VecMulPfS_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6VecMulPfS_S_PfS_S_
	.cfi_endproc
.LFE2055:
	.size	_Z6VecMulPfS_S_, .-_Z6VecMulPfS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"hC = %f, hCMul = %f \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	subq	$144, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsp, %rdi
	movl	$1, 132(%rsp)
	movq	%rax, 116(%rsp)
	addq	$39, %rax
	movq	%rax, 124(%rsp)
	call	cudaStreamCreate@PLT
	leaq	8(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	16(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMallocHost@PLT
	leaq	24(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMallocHost@PLT
	leaq	32(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMallocHost@PLT
	leaq	40(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMallocHost@PLT
	leaq	48(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMallocHost@PLT
	leaq	56(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMallocHost@PLT
	movq	16(%rsp), %rbx
	movq	24(%rsp), %r11
	xorl	%ecx, %ecx
	movq	32(%rsp), %r10
	movq	40(%rsp), %r9
	movl	$10, %esi
	movq	48(%rsp), %r8
	movq	56(%rsp), %rdi
.L14:
	cvtsi2ssl	%ecx, %xmm0
	leal	1(%rcx), %eax
	movss	%xmm0, (%rbx,%rcx,4)
	cvtsi2ssl	%eax, %xmm0
	movl	%ecx, %eax
	cltd
	idivl	%esi
	movss	%xmm0, (%r11,%rcx,4)
	movl	$0x00000000, (%r10,%rcx,4)
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r9,%rcx,4)
	movss	%xmm0, (%r8,%rcx,4)
	movl	$0x00000000, (%rdi,%rcx,4)
	incq	%rcx
	cmpq	$10240, %rcx
	jne	.L14
	leaq	64(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMalloc@PLT
	leaq	88(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMalloc@PLT
	leaq	96(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMalloc@PLT
	leaq	104(%rsp), %rdi
	movl	$40960, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %r8
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	64(%rsp), %rdi
	movl	$40960, %edx
	call	cudaMemcpyAsync@PLT
	movq	(%rsp), %r8
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	movl	$40960, %edx
	call	cudaMemcpyAsync@PLT
	movl	120(%rsp), %ecx
	movq	(%rsp), %r9
	xorl	%r8d, %r8d
	movl	$256, 112(%rsp)
	movq	124(%rsp), %rdi
	movq	112(%rsp), %rdx
	movl	132(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.L15:
	movq	8(%rsp), %r8
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movl	$40960, %edx
	movq	88(%rsp), %rdi
	call	cudaMemcpyAsync@PLT
	movq	8(%rsp), %r8
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	96(%rsp), %rdi
	movl	$40960, %edx
	call	cudaMemcpyAsync@PLT
	movl	120(%rsp), %ecx
	movq	8(%rsp), %r9
	xorl	%r8d, %r8d
	movq	112(%rsp), %rdx
	movq	124(%rsp), %rdi
	movl	132(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	movq	88(%rsp), %rdi
	call	_Z29__device_stub__Z6VecMulPfS_S_PfS_S_
.L16:
	movq	(%rsp), %r8
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movl	$40960, %edx
	movq	32(%rsp), %rdi
	call	cudaMemcpyAsync@PLT
	movq	104(%rsp), %rsi
	movq	8(%rsp), %r8
	movl	$2, %ecx
	movq	56(%rsp), %rdi
	movl	$40960, %edx
	call	cudaMemcpyAsync@PLT
	movq	(%rsp), %rdi
	call	cudaStreamSynchronize@PLT
	movq	8(%rsp), %rdi
	call	cudaStreamSynchronize@PLT
	movq	32(%rsp), %rax
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	cvtss2sd	40(%rax), %xmm0
	movq	56(%rsp), %rax
	cvtss2sd	48(%rax), %xmm1
	movb	$2, %al
	call	__printf_chk@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$144, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z6VecMulPfS_S_"
.LC3:
	.string	"_Z6VecAddPfS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6VecMulPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6VecAddPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<hip/hip_runtime.h>
#include<stdio.h>

__global__ void VecAdd(float *A, float *B, float *C)
{
  int i = threadIdx.x;
  for(int j = 0; j < 1000; j++)
  C[i] = A[i] + B[i];
}

__global__ void VecMul(float *A, float *B, float *C)
{
  int i = threadIdx.x;
  for(int j = 0; j < 1000; j++)
  C[i] = A[i] * B[i];
}



int main()
{
  int N = 1024 * 10;
  dim3 threadPerBlock(256);
  dim3 numBlocks(N/threadPerBlock.x);

  hipStream_t stream1, stream2;
  hipStreamCreate(&stream1);
  hipStreamCreate(&stream2);
  //cudaStreamCreateWithFlags(&stream1, cudaStreamNonBlocking);
  //cudaStreamCreateWithFlags(&stream2, cudaStreamNonBlocking);

  // Host memory.
  float *hA, *hB, *hC, *hAMul, *hBMul, *hCMul;
#if 0
  hA = (float*) malloc (sizeof(float) * N);
  hB = (float*) malloc (sizeof(float) * N);
  hC = (float*) malloc (sizeof(float) * N);
  hAMul = (float*) malloc (sizeof(float) * N);
  hBMul = (float*) malloc (sizeof(float) * N);
  hCMul = (float*) malloc (sizeof(float) * N);
#endif
  hipHostMalloc((void**)&hA, sizeof(float) * N, hipHostMallocDefault); 
  hipHostMalloc((void**)&hB, sizeof(float) * N, hipHostMallocDefault); 
  hipHostMalloc((void**)&hC, sizeof(float) * N, hipHostMallocDefault); 
  hipHostMalloc((void**)&hAMul, sizeof(float) * N, hipHostMallocDefault); 
  hipHostMalloc((void**)&hBMul, sizeof(float) * N, hipHostMallocDefault); 
  hipHostMalloc((void**)&hCMul, sizeof(float) * N, hipHostMallocDefault); 
  for(int i = 0; i < N; i++){
    hA[i] = i;
    hB[i] = i + 1;
    hC[i] = 0.0f;
    hAMul[i] = i % 10;
    hBMul[i] = i % 10;
    hCMul[i] = 0.0f;

  }

  // Device memory.
  float *A, *B, *C, *AMul, *BMul, *CMul;
  hipMalloc((void**)&A, sizeof(float) * N); 
  hipMalloc((void**)&B, sizeof(float) * N); 
  hipMalloc((void**)&C, sizeof(float) * N); 
  hipMalloc((void**)&AMul, sizeof(float) * N); 
  hipMalloc((void**)&BMul, sizeof(float) * N); 
  hipMalloc((void**)&CMul, sizeof(float) * N); 

  // Host->Device
  hipMemcpyAsync(A, hA, sizeof(float)*N, hipMemcpyHostToDevice, stream1);
  hipMemcpyAsync(B, hB, sizeof(float)*N, hipMemcpyHostToDevice, stream1);
  //cudaMemcpyAsync(C, hC, sizeof(float)*N, cudaMemcpyHostToDevice, stream1);
  VecAdd<<<numBlocks, threadPerBlock, 0, stream1>>>(A, B, C);

  hipMemcpyAsync(AMul, hAMul, sizeof(float)*N, hipMemcpyHostToDevice, stream2);
  hipMemcpyAsync(BMul, hBMul, sizeof(float)*N, hipMemcpyHostToDevice, stream2);
  VecMul<<<numBlocks, threadPerBlock, 0, stream2>>>(AMul, BMul, CMul);
  hipMemcpyAsync(hC, C, sizeof(float)*N, hipMemcpyDeviceToHost, stream1);
  hipMemcpyAsync(hCMul, CMul, sizeof(float)*N, hipMemcpyDeviceToHost, stream2);

  //cudaMemcpyAsync(BMul, hBMul, sizeof(float)*N, cudaMemcpyHostToDevice, stream2);
  //cudaMemcpyAsync(CMul, hCMul, sizeof(float)*N, cudaMemcpyHostToDevice, stream2);
  //cudaMemcpyAsync(hCMul, CMul, sizeof(float)*N, cudaMemcpyDeviceToDevice, stream2);
  hipStreamSynchronize(stream1);
  hipStreamSynchronize(stream2);

  printf("hC = %f, hCMul = %f \n", hC[10], hCMul[12]);
  return 0;
}

	.text
	.file	"stream.hip"
	.globl	_Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
	.type	_Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_:        # @_Z21__device_stub__VecAddPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6VecAddPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__VecMulPfS_S_ # -- Begin function _Z21__device_stub__VecMulPfS_S_
	.type	_Z21__device_stub__VecMulPfS_S_,@function
_Z21__device_stub__VecMulPfS_S_:        # @_Z21__device_stub__VecMulPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6VecMulPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__VecMulPfS_S_, .Lfunc_end1-_Z21__device_stub__VecMulPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	16(%rsp), %rdi
	callq	hipStreamCreate
	leaq	8(%rsp), %rdi
	callq	hipStreamCreate
	leaq	72(%rsp), %rdi
	xorl	%ebx, %ebx
	movl	$40960, %esi                    # imm = 0xA000
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	112(%rsp), %r14
	movl	$40960, %esi                    # imm = 0xA000
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	64(%rsp), %r15
	movl	$40960, %esi                    # imm = 0xA000
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	104(%rsp), %r12
	movl	$40960, %esi                    # imm = 0xA000
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	96(%rsp), %r13
	movl	$40960, %esi                    # imm = 0xA000
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	56(%rsp), %rbp
	movl	$40960, %esi                    # imm = 0xA000
	movq	%rbp, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	72(%rsp), %rax
	movq	(%rax), %rax
	movq	(%r14), %rcx
	movq	(%r15), %rdx
	movq	(%r12), %rsi
	movq	(%r13), %rdi
	movq	(%rbp), %r8
	movl	$65535, %r9d                    # imm = 0xFFFF
	xorl	%r10d, %r10d
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	%r10d, %r11d
	andl	%r9d, %r11d
	imull	$52429, %r11d, %r11d            # imm = 0xCCCD
	shrl	$18, %r11d
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r10d, %xmm0
	andl	$-2, %r11d
	leal	(%r11,%r11,4), %r11d
	movss	%xmm0, (%rax,%r10,4)
	leaq	1(%r10), %r14
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r14d, %xmm0
	movss	%xmm0, (%rcx,%r10,4)
	movl	%ebx, (%rdx,%r10,4)
	movl	%r10d, %ebp
	subl	%r11d, %ebp
	andl	%r9d, %ebp
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebp, %xmm0
	movss	%xmm0, (%rsi,%r10,4)
	movss	%xmm0, (%rdi,%r10,4)
	movl	%ebx, (%r8,%r10,4)
	movq	%r14, %r10
	cmpq	$10240, %r14                    # imm = 0x2800
	jne	.LBB2_1
# %bb.2:
	movabsq	$4294967336, %rbx               # imm = 0x100000028
	leaq	88(%rsp), %r15
	movl	$40960, %esi                    # imm = 0xA000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	80(%rsp), %r14
	movl	$40960, %esi                    # imm = 0xA000
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$40960, %esi                    # imm = 0xA000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$40960, %esi                    # imm = 0xA000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$40960, %esi                    # imm = 0xA000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$40960, %esi                    # imm = 0xA000
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	72(%rsp), %rsi
	movq	16(%rsp), %r8
	movl	$40960, %edx                    # imm = 0xA000
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%r14), %rdi
	movq	112(%rsp), %rsi
	movq	16(%rsp), %r8
	movl	$40960, %edx                    # imm = 0xA000
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	16(%rsp), %r9
	leaq	216(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	88(%rsp), %rdi
	movq	80(%rsp), %rsi
	movq	48(%rsp), %rdx
	callq	_Z21__device_stub__VecAddPfS_S_
.LBB2_4:
	movq	40(%rsp), %rdi
	movq	104(%rsp), %rsi
	movq	8(%rsp), %r8
	movl	$40960, %edx                    # imm = 0xA000
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	32(%rsp), %rdi
	movq	96(%rsp), %rsi
	movq	8(%rsp), %r8
	movl	$40960, %edx                    # imm = 0xA000
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	8(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	callq	_Z21__device_stub__VecMulPfS_S_
.LBB2_6:
	movq	64(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	16(%rsp), %r8
	movl	$40960, %edx                    # imm = 0xA000
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movq	56(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	8(%rsp), %r8
	movl	$40960, %edx                    # imm = 0xA000
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movq	16(%rsp), %rdi
	callq	hipStreamSynchronize
	movq	8(%rsp), %rdi
	callq	hipStreamSynchronize
	movq	64(%rsp), %rax
	cvtss2sd	40(%rax), %xmm0
	movq	56(%rsp), %rax
	cvtss2sd	48(%rax), %xmm1
	movl	$.L.str, %edi
	movb	$2, %al
	callq	printf
	xorl	%eax, %eax
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6VecAddPfS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6VecMulPfS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6VecAddPfS_S_,@object         # @_Z6VecAddPfS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z6VecAddPfS_S_
	.p2align	3, 0x0
_Z6VecAddPfS_S_:
	.quad	_Z21__device_stub__VecAddPfS_S_
	.size	_Z6VecAddPfS_S_, 8

	.type	_Z6VecMulPfS_S_,@object         # @_Z6VecMulPfS_S_
	.globl	_Z6VecMulPfS_S_
	.p2align	3, 0x0
_Z6VecMulPfS_S_:
	.quad	_Z21__device_stub__VecMulPfS_S_
	.size	_Z6VecMulPfS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"hC = %f, hCMul = %f \n"
	.size	.L.str, 22

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6VecAddPfS_S_"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6VecMulPfS_S_"
	.size	.L__unnamed_2, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__VecAddPfS_S_
	.addrsig_sym _Z21__device_stub__VecMulPfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6VecAddPfS_S_
	.addrsig_sym _Z6VecMulPfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6VecAddPfS_S_         ; -- Begin function _Z6VecAddPfS_S_
	.globl	_Z6VecAddPfS_S_
	.p2align	8
	.type	_Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:                        ; @_Z6VecAddPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_lshlrev_b32_e32 v4, 2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s2, s4, v4
	v_add_co_ci_u32_e64 v1, null, s5, 0, s2
	v_add_co_u32 v2, s2, s6, v4
	v_add_co_u32 v4, s0, s0, v4
	v_add_co_ci_u32_e64 v3, null, s7, 0, s2
	v_add_co_ci_u32_e64 v5, null, s1, 0, s0
	s_movk_i32 s0, 0x3e8
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[0:1], off
	global_load_b32 v7, v[2:3], off
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v7
	global_store_b32 v[4:5], v6, off
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6VecAddPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 8
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 8
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6VecMulPfS_S_         ; -- Begin function _Z6VecMulPfS_S_
	.globl	_Z6VecMulPfS_S_
	.p2align	8
	.type	_Z6VecMulPfS_S_,@function
_Z6VecMulPfS_S_:                        ; @_Z6VecMulPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_lshlrev_b32_e32 v4, 2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s2, s4, v4
	v_add_co_ci_u32_e64 v1, null, s5, 0, s2
	v_add_co_u32 v2, s2, s6, v4
	v_add_co_u32 v4, s0, s0, v4
	v_add_co_ci_u32_e64 v3, null, s7, 0, s2
	v_add_co_ci_u32_e64 v5, null, s1, 0, s0
	s_movk_i32 s0, 0x3e8
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[0:1], off
	global_load_b32 v7, v[2:3], off
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v6, v6, v7
	global_store_b32 v[4:5], v6, off
	s_cbranch_scc0 .LBB1_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6VecMulPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 8
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6VecMulPfS_S_, .Lfunc_end1-_Z6VecMulPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 8
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6VecAddPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z6VecAddPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6VecMulPfS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z6VecMulPfS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
