#include <stdio.h>
#include <iostream>
#include <vector>

__global__
void sum(int n, double *x, double *y, double *z)
{
  
 
  int i = blockIdx.x*blockDim.x + threadIdx.x;

  if(i<n){
    z[i]=x[i]+y[i];
    printf("check from function i= %d %f + %f = %f\n",i,x[i],y[i],z[i]);
  }
  //blockIdx variabile di tipo dim3, contiene l'indice del blocco
  //threadIdx variabile di tipo dim3, contiene l'indice del thread
}




int main(void ) {

  const int Nfix=10;//fixed dimension
  double *a[Nfix],*b[Nfix],*c[Nfix]; //for the host
  double *da[Nfix],*db[Nfix],*dc[Nfix]; //for the device

    
  int Nvar[Nfix]; //dynamic dimension
  
  //then I allocate the memory
  
  for(int i=0;i<Nfix;i++){

    Nvar[i]=3*(i+1);
    
    a[i]=(double*)malloc(Nvar[i]*sizeof(double));
    b[i]=(double*)malloc(Nvar[i]*sizeof(double));
    c[i]=(double*)malloc(Nvar[i]*sizeof(double));
    
  

    for(int k=0;k<Nvar[i];k++){
      a[i][k]=k+(i+1);
      b[i][k]=k+2*(i+1);
    } 
    
    //and for the device
    cudaMalloc(&da[i],Nvar[i]*sizeof(double));
    cudaMalloc(&db[i],Nvar[i]*sizeof(double));
    cudaMalloc(&dc[i],Nvar[i]*sizeof(double));
    
    //the I copy the memory 
    
    cudaMemcpy(da[i],a[i],Nvar[i]*sizeof(double),cudaMemcpyHostToDevice);
    cudaMemcpy(db[i],b[i],Nvar[i]*sizeof(double),cudaMemcpyHostToDevice);

    sum<<<1,Nvar[i]>>>(Nvar[i],da[i],db[i],dc[i]);
    cudaMemcpy(c[i],dc[i],Nvar[i]*sizeof(double),cudaMemcpyDeviceToHost);

    for(int k=0;k<Nvar[i];k++)std::cout<<"i= "<<k<<" "<<a[i][k]<<" + "<<b[i][k]<<" = "<<c[i][k]<<std::endl;

    cudaFree(da[i]);
    cudaFree(db[i]);
    cudaFree(dc[i]);
    free(a[i]);
    free(b[i]);
    free(c[i]);

    
  }
  
}



	.file	"tmpxft_002f9714_00000000-6_prova2d.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4001:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4001:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z27__device_stub__Z3sumiPdS_S_iPdS_S_
	.type	_Z27__device_stub__Z3sumiPdS_S_iPdS_S_, @function
_Z27__device_stub__Z3sumiPdS_S_iPdS_S_:
.LFB4023:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3sumiPdS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4023:
	.size	_Z27__device_stub__Z3sumiPdS_S_iPdS_S_, .-_Z27__device_stub__Z3sumiPdS_S_iPdS_S_
	.globl	_Z3sumiPdS_S_
	.type	_Z3sumiPdS_S_, @function
_Z3sumiPdS_S_:
.LFB4024:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3sumiPdS_S_iPdS_S_
	.cfi_endproc
.LFE4024:
	.size	_Z3sumiPdS_S_, .-_Z3sumiPdS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"i= "
.LC1:
	.string	" "
.LC2:
	.string	" + "
.LC3:
	.string	" = "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3998:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$312, %rsp
	.cfi_def_cfa_offset 368
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	movl	$3, 12(%rsp)
	leaq	56(%rsp), %r14
	leaq	136(%rsp), %r13
	leaq	216(%rsp), %r12
.L12:
	leaq	1(%rbp), %rax
	imulq	$24, %rax, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r15
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movl	%ebp, %esi
	leal	1(%rbp,%rbp), %ecx
	movq	%rax, 24(%rsp)
	movl	$1, %eax
.L9:
	leal	(%rsi,%rax), %edx
	cvtsi2sdl	%edx, %xmm0
	leal	(%rcx,%rax), %edx
	movsd	%xmm0, -8(%r15,%rax,8)
	cvtsi2sdl	%edx, %xmm0
	movq	16(%rsp), %rdx
	movsd	%xmm0, -8(%rdx,%rax,8)
	incq	%rax
	leal	-1(%rax), %edx
	cmpl	%edx, 12(%rsp)
	jg	.L9
	movq	%rbx, %rsi
	movq	%r14, %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	movq	%r13, %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	movq	%r12, %rdi
	call	cudaMalloc@PLT
	movq	(%r14), %rdi
	movl	$1, %ecx
	movq	%rbx, %rdx
	movq	%r15, %rsi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	0(%r13), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	12(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	$1, 40(%rsp)
	movl	%eax, 44(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	52(%rsp), %ecx
	movq	%rax, %rdi
	movq	44(%rsp), %rdx
	movq	%rax, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	(%r12), %rcx
	movq	0(%r13), %rdx
	movq	(%r14), %rsi
	movl	12(%rsp), %edi
	call	_Z27__device_stub__Z3sumiPdS_S_iPdS_S_
.L10:
	movq	(%r12), %rsi
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	xorl	%ebx, %ebx
	call	cudaMemcpy@PLT
.L11:
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	(%r15,%rbx,8), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	16(%rsp), %rax
	movsd	(%rax,%rbx,8), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	24(%rsp), %rax
	movsd	(%rax,%rbx,8), %xmm0
	incq	%rbx
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpl	%ebx, 12(%rsp)
	jg	.L11
	movq	(%r14), %rdi
	incq	%rbp
	addq	$8, %r14
	addq	$8, %r13
	addq	$8, %r12
	call	cudaFree@PLT
	movq	-8(%r13), %rdi
	call	cudaFree@PLT
	movq	-8(%r12), %rdi
	call	cudaFree@PLT
	movq	%r15, %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	addl	$3, 12(%rsp)
	cmpq	$10, %rbp
	jne	.L12
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$312, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3998:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z3sumiPdS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4026:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3sumiPdS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4026:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <vector>

__global__
void sum(int n, double *x, double *y, double *z)
{
  
 
  int i = blockIdx.x*blockDim.x + threadIdx.x;

  if(i<n){
    z[i]=x[i]+y[i];
    printf("check from function i= %d %f + %f = %f\n",i,x[i],y[i],z[i]);
  }
  //blockIdx variabile di tipo dim3, contiene l'indice del blocco
  //threadIdx variabile di tipo dim3, contiene l'indice del thread
}




int main(void ) {

  const int Nfix=10;//fixed dimension
  double *a[Nfix],*b[Nfix],*c[Nfix]; //for the host
  double *da[Nfix],*db[Nfix],*dc[Nfix]; //for the device

    
  int Nvar[Nfix]; //dynamic dimension
  
  //then I allocate the memory
  
  for(int i=0;i<Nfix;i++){

    Nvar[i]=3*(i+1);
    
    a[i]=(double*)malloc(Nvar[i]*sizeof(double));
    b[i]=(double*)malloc(Nvar[i]*sizeof(double));
    c[i]=(double*)malloc(Nvar[i]*sizeof(double));
    
  

    for(int k=0;k<Nvar[i];k++){
      a[i][k]=k+(i+1);
      b[i][k]=k+2*(i+1);
    } 
    
    //and for the device
    hipMalloc(&da[i],Nvar[i]*sizeof(double));
    hipMalloc(&db[i],Nvar[i]*sizeof(double));
    hipMalloc(&dc[i],Nvar[i]*sizeof(double));
    
    //the I copy the memory 
    
    hipMemcpy(da[i],a[i],Nvar[i]*sizeof(double),hipMemcpyHostToDevice);
    hipMemcpy(db[i],b[i],Nvar[i]*sizeof(double),hipMemcpyHostToDevice);

    sum<<<1,Nvar[i]>>>(Nvar[i],da[i],db[i],dc[i]);
    hipMemcpy(c[i],dc[i],Nvar[i]*sizeof(double),hipMemcpyDeviceToHost);

    for(int k=0;k<Nvar[i];k++)std::cout<<"i= "<<k<<" "<<a[i][k]<<" + "<<b[i][k]<<" = "<<c[i][k]<<std::endl;

    hipFree(da[i]);
    hipFree(db[i]);
    hipFree(dc[i]);
    free(a[i]);
    free(b[i]);
    free(c[i]);

    
  }
  
}



	.text
	.file	"prova2d.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__sumiPdS_S_   # -- Begin function _Z18__device_stub__sumiPdS_S_
	.type	_Z18__device_stub__sumiPdS_S_,@function
_Z18__device_stub__sumiPdS_S_:          # @_Z18__device_stub__sumiPdS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3sumiPdS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__sumiPdS_S_, .Lfunc_end0-_Z18__device_stub__sumiPdS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$312, %rsp                      # imm = 0x138
	.cfi_def_cfa_offset 368
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967296, %rax               # imm = 0x100000000
	movl	$3, %ebx
	movl	$2, %ecx
	movl	$1, %edx
	xorl	%ebp, %ebp
	incq	%rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
                                        #     Child Loop BB1_6 Depth 2
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	leaq	1(%rbp), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	leaq	(%rax,%rax,2), %rax
	movq	%rax, (%rsp)                    # 8-byte Spill
	leaq	8(,%rbp,8), %rax
	leaq	(%rax,%rax,2), %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r13, %rdi
	callq	malloc
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movq	%rax, %r12
	xorl	%eax, %eax
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rsi,%rax), %ecx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%ecx, %xmm0
	leal	(%rdx,%rax), %ecx
	xorps	%xmm1, %xmm1
	cvtsi2sd	%ecx, %xmm1
	movsd	%xmm0, (%r14,%rax,8)
	movsd	%xmm1, (%r15,%rax,8)
	incq	%rax
	cmpq	%rax, %rbx
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	leaq	(%rsp,%rbp,8), %rdi
	addq	$224, %rdi
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	(%rsp,%rbp,8), %rdi
	addq	$144, %rdi
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	(%rsp,%rbp,8), %rbp
	addq	$64, %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	16(%rsp), %rax                  # 8-byte Reload
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rax                   # 8-byte Reload
	movq	(%rax), %rdi
	movq	%r15, %rsi
	movq	%r13, 48(%rsp)                  # 8-byte Spill
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %r13                    # 8-byte Reload
	movq	%r13, %rdx
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdx
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_1 Depth=1
	movq	16(%rsp), %rax                  # 8-byte Reload
	movq	(%rax), %rsi
	movq	8(%rsp), %rax                   # 8-byte Reload
	movq	(%rax), %rdx
	movq	(%rbp), %rcx
	movl	%r13d, %edi
	callq	_Z18__device_stub__sumiPdS_S_
.LBB1_5:                                #   in Loop: Header=BB1_1 Depth=1
	movq	%rbp, (%rsp)                    # 8-byte Spill
	movq	(%rbp), %rsi
	movq	%r12, %rdi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r13d, %r13d
.LBB1_6:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$3, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbp
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	(%r14,%r13,8), %xmm0            # xmm0 = mem[0],zero
	movq	%rbp, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbp
	movl	$.L.str.2, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	(%r15,%r13,8), %xmm0            # xmm0 = mem[0],zero
	movq	%rbp, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbp
	movl	$.L.str.3, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	(%r12,%r13,8), %xmm0            # xmm0 = mem[0],zero
	movq	%rbp, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbp
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbp, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbp, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r13
	cmpq	%r13, %rbx
	jne	.LBB1_6
# %bb.7:                                #   in Loop: Header=BB1_1 Depth=1
	movq	16(%rsp), %rax                  # 8-byte Reload
	movq	(%rax), %rdi
	callq	hipFree
	movq	8(%rsp), %rax                   # 8-byte Reload
	movq	(%rax), %rdi
	callq	hipFree
	movq	(%rsp), %rax                    # 8-byte Reload
	movq	(%rax), %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	addq	$3, %rbx
	movq	32(%rsp), %rcx                  # 8-byte Reload
	addq	$2, %rcx
	movq	24(%rsp), %rdx                  # 8-byte Reload
	incq	%rdx
	movq	56(%rsp), %rax                  # 8-byte Reload
	movq	%rax, %rbp
	cmpq	$10, %rax
	jne	.LBB1_1
# %bb.8:
	xorl	%eax, %eax
	addq	$312, %rsp                      # imm = 0x138
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3sumiPdS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3sumiPdS_S_,@object           # @_Z3sumiPdS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z3sumiPdS_S_
	.p2align	3, 0x0
_Z3sumiPdS_S_:
	.quad	_Z18__device_stub__sumiPdS_S_
	.size	_Z3sumiPdS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"i= "
	.size	.L.str, 4

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" + "
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" = "
	.size	.L.str.3, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3sumiPdS_S_"
	.size	.L__unnamed_1, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__sumiPdS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3sumiPdS_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3sumiPdS_S_           ; -- Begin function _Z3sumiPdS_S_
	.globl	_Z3sumiPdS_S_
	.p2align	8
	.type	_Z3sumiPdS_S_,@function
_Z3sumiPdS_S_:                          ; @_Z3sumiPdS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s5, s[0:1], 0x0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s5, v1
	s_cbranch_execz .LBB0_252
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x18
	v_mbcnt_lo_u32_b32 v40, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[1:2]
	v_mov_b32_e32 v16, v40
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	global_load_b64 v[2:3], v[6:7], off
	global_load_b64 v[10:11], v[8:9], off
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[10:11]
	global_store_b64 v[4:5], v[2:3], off
	global_load_b64 v[10:11], v[6:7], off
	global_load_b64 v[6:7], v[8:9], off
	s_load_b64 s[2:3], s[2:3], 0x50
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v16
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_7
; %bb.2:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[14:15], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v0, s[2:3] offset:40
	global_load_b64 v[8:9], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v15
	v_and_b32_e32 v4, v4, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v12, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v12, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[12:13], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[14:15]
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_4:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	global_load_b64 v[12:13], v0, s[2:3]
	v_dual_mov_b32 v15, v5 :: v_dual_mov_b32 v14, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[12:13]
	v_and_b32_e32 v12, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[12:13], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[14:15]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow489
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_6:                                ; %Flow491
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_7:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v17, 0
	v_readfirstlane_b32 s4, v4
	v_readfirstlane_b32 s5, v5
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v17, s[2:3] offset:40
	global_load_b128 v[12:15], v17, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_dual_mov_b32 v18, s10 :: v_dual_mov_b32 v19, v17
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v13, vcc_lo
	v_dual_mov_b32 v20, 2 :: v_dual_mov_b32 v21, 1
	global_store_b128 v[4:5], v[18:21], off offset:8
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[16:17]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v14, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v15, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v0, v4
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_add_co_ci_u32_e32 v5, vcc_lo, v8, v5, vcc_lo
	v_dual_mov_b32 v16, 33 :: v_dual_mov_b32 v19, v17
	v_dual_mov_b32 v18, v17 :: v_dual_mov_b32 v23, s15
	v_dual_mov_b32 v22, s14 :: v_dual_mov_b32 v21, s13
	v_mov_b32_e32 v20, s12
	s_clause 0x3
	global_store_b128 v[4:5], v[16:19], off
	global_store_b128 v[4:5], v[20:23], off offset:16
	global_store_b128 v[4:5], v[20:23], off offset:32
	global_store_b128 v[4:5], v[20:23], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_17
; %bb.10:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[18:19], v0, s[2:3] offset:32 glc
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	v_dual_mov_b32 v17, s5 :: v_dual_mov_b32 v16, s4
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, s5, v9
	v_and_b32_e32 v8, s4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v9, 24
	v_mul_hi_u32 v14, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v14, v9
	v_add_co_u32 v8, vcc_lo, v12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo
	global_store_b64 v[8:9], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v0, v[16:19], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[16:17], v[18:19]
	s_cbranch_execz .LBB0_13
; %bb.11:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB0_12:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v14, s4 :: v_dual_mov_b32 v15, s5
	s_sleep 1
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v0, v[14:17], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[16:17]
	v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_12
.LBB0_13:                               ; %Flow487
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v15, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v0, s10, 0
	global_load_b64 v[8:9], v15, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_15
; %bb.14:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v14, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[14:15], off offset:8
.LBB0_15:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[14:15], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	s_cbranch_vccnz .LBB0_17
; %bb.16:
	global_load_b32 v8, v[8:9], off offset:24
	v_mov_b32_e32 v9, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v8
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[14:15], v[8:9], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_17:                               ; %Flow488
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v9, vcc_lo, s8, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB0_18:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=1
	global_load_b32 v0, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB0_20:                               ;   in Loop: Header=BB0_18 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_18 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_23
.LBB0_22:                               ;   in Loop: Header=BB0_18 Depth=1
	s_mov_b32 s1, -1
.LBB0_23:                               ; %Flow482
                                        ;   in Loop: Header=BB0_18 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_18
; %bb.24:
	global_load_b64 v[12:13], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_28
; %bb.25:
	v_mov_b32_e32 v0, 0
	s_clause 0x2
	global_load_b64 v[4:5], v0, s[2:3] offset:40
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	global_load_b64 v[16:17], v0, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v18, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v18, s4
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v19 :: v_dual_cndmask_b32 v14, v14, v18
	v_and_b32_e32 v5, v15, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v14, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v18, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v18, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v16, v4
	v_mov_b32_e32 v16, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, v17, v5, vcc_lo
	v_mov_b32_e32 v17, v9
	global_store_b64 v[4:5], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v0, v[14:17], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_28
; %bb.26:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_27:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v0, v[14:17], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[16:17]
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v16, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_27
.LBB0_28:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB0_114
; %bb.29:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 2, v12
	v_dual_mov_b32 v15, v13 :: v_dual_and_b32 v14, -3, v12
	v_dual_mov_b32 v18, 2 :: v_dual_mov_b32 v19, 1
	s_mov_b64 s[6:7], 40
.LBB0_30:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_33 Depth 2
                                        ;     Child Loop BB0_40 Depth 2
                                        ;     Child Loop BB0_48 Depth 2
                                        ;     Child Loop BB0_56 Depth 2
                                        ;     Child Loop BB0_64 Depth 2
                                        ;     Child Loop BB0_72 Depth 2
                                        ;     Child Loop BB0_80 Depth 2
                                        ;     Child Loop BB0_88 Depth 2
                                        ;     Child Loop BB0_96 Depth 2
                                        ;     Child Loop BB0_102 Depth 2
                                        ;     Child Loop BB0_111 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $sgpr15
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_35
; %bb.31:                               ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_34
; %bb.32:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB0_33:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v5, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s10, v[4:5]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v22, v8, v22
	v_or_b32_e32 v23, v9, v23
	s_cbranch_scc1 .LBB0_33
.LBB0_34:                               ; %Flow458
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s15, 0
.LBB0_35:                               ; %Flow460
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB0_37
; %bb.36:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[22:23], v5, s[4:5]
	s_add_i32 s15, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB0_37:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_42
; %bb.38:                               ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_41
; %bb.39:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_40:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v5, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s10, v[4:5]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v24, v8, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v25, v9, v25
	s_cbranch_scc1 .LBB0_40
.LBB0_41:                               ; %Flow453
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_43
.LBB0_42:                               ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $sgpr14
.LBB0_43:                               ; %Flow455
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_45
; %bb.44:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[24:25], v5, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_45:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_50
; %bb.46:                               ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_49
; %bb.47:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_48:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v5, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s10, v[4:5]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v26, v8, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v27, v9, v27
	s_cbranch_scc1 .LBB0_48
.LBB0_49:                               ; %Flow448
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_51
.LBB0_50:                               ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_51:                               ; %Flow450
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_53
; %bb.52:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[26:27], v5, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_53:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_58
; %bb.54:                               ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v28, 0
	v_mov_b32_e32 v29, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_57
; %bb.55:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_56:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v5, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s10, v[4:5]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v28, v8, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v29, v9, v29
	s_cbranch_scc1 .LBB0_56
.LBB0_57:                               ; %Flow443
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_59
.LBB0_58:                               ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $sgpr14
.LBB0_59:                               ; %Flow445
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_61
; %bb.60:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[28:29], v5, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_61:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_66
; %bb.62:                               ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v30, 0
	v_mov_b32_e32 v31, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_65
; %bb.63:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_64:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v5, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s10, v[4:5]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v30, v8, v30
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v31, v9, v31
	s_cbranch_scc1 .LBB0_64
.LBB0_65:                               ; %Flow438
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_67
.LBB0_66:                               ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_67:                               ; %Flow440
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_69
; %bb.68:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[30:31], v5, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_69:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_74
; %bb.70:                               ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v32, 0
	v_mov_b32_e32 v33, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_73
; %bb.71:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_72:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v5, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s10, v[4:5]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v32, v8, v32
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v33, v9, v33
	s_cbranch_scc1 .LBB0_72
.LBB0_73:                               ; %Flow433
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_75
.LBB0_74:                               ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $sgpr14
.LBB0_75:                               ; %Flow435
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[32:33], v5, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_77:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_82
; %bb.78:                               ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v34, 0
	v_mov_b32_e32 v35, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_81
; %bb.79:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB0_80:                               ; %.preheader.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v5, s[12:13]
	s_add_i32 s14, s14, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], s10, v[4:5]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 0
	v_or_b32_e32 v34, v8, v34
	v_or_b32_e32 v35, v9, v35
	s_cbranch_scc1 .LBB0_80
.LBB0_81:                               ; %Flow428
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB0_83
.LBB0_82:                               ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s10, -1
.LBB0_83:                               ; %Flow430
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_85
; %bb.84:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[34:35], v5, s[0:1]
.LBB0_85:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	v_mov_b32_e32 v4, v40
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v4
	v_cmp_eq_u32_e64 s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_91
; %bb.86:                               ;   in Loop: Header=BB0_30 Depth=1
	global_load_b64 v[38:39], v5, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b64 v[16:17], v5, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, v9, v39
	v_and_b32_e32 v8, v8, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v9, 24
	v_mul_hi_u32 v20, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v20, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v16, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v17, v9, vcc_lo
	global_load_b64 v[36:37], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v5, v[36:39], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[38:39]
	s_cbranch_execz .LBB0_90
; %bb.87:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s11, 0
.LBB0_88:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[16:17], v5, s[2:3] offset:40
	global_load_b64 v[20:21], v5, s[2:3]
	v_dual_mov_b32 v39, v9 :: v_dual_mov_b32 v38, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v16, v16, v38
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v16, 24, v[20:21]
	v_and_b32_e32 v20, v17, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, v20, 24, v[9:10]
	v_mov_b32_e32 v9, v16
	global_load_b64 v[36:37], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v5, v[36:39], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[38:39]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_88
; %bb.89:                               ; %Flow423
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_90:                               ; %Flow425
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_91:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[16:17], v5, s[2:3] offset:40
	global_load_b128 v[36:39], v5, s[2:3]
	v_readfirstlane_b32 s10, v8
	v_readfirstlane_b32 s11, v9
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v16
	v_readfirstlane_b32 s13, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_93
; %bb.92:                               ;   in Loop: Header=BB0_30 Depth=1
	v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, v5
	s_add_i32 s16, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v36, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s16, v37, vcc_lo
	global_store_b128 v[8:9], v[16:19], off offset:8
.LBB0_93:                               ;   in Loop: Header=BB0_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v8, 0, v15
	v_or_b32_e32 v9, v14, v0
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s16, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, 28
	v_dual_cndmask_b32 v21, v8, v15 :: v_dual_cndmask_b32 v14, v9, v14
	v_lshlrev_b64 v[8:9], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v38, s12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v39, vcc_lo
	s_and_b32 s16, s16, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v4, v8
	v_and_or_b32 v20, 0xffffff1f, v14, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, v15, v9, vcc_lo
	s_clause 0x3
	global_store_b128 v[8:9], v[20:23], off
	global_store_b128 v[8:9], v[24:27], off offset:16
	global_store_b128 v[8:9], v[28:31], off offset:32
	global_store_b128 v[8:9], v[32:35], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_101
; %bb.94:                               ;   in Loop: Header=BB0_30 Depth=1
	s_clause 0x1
	global_load_b64 v[24:25], v5, s[2:3] offset:32 glc
	global_load_b64 v[14:15], v5, s[2:3] offset:40
	v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v14
	v_readfirstlane_b32 s17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v20, vcc_lo, v36, s16
	v_add_co_ci_u32_e32 v21, vcc_lo, s17, v37, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[20:21], v[24:25], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v5, v[22:25], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[16:17], v[24:25]
	s_cbranch_execz .LBB0_97
; %bb.95:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s16, 0
.LBB0_96:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, s11
	s_sleep 1
	global_store_b64 v[20:21], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v5, v[14:17], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[16:17]
	v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_96
.LBB0_97:                               ; %Flow421
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[14:15], v5, s[2:3] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v4, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_99
; %bb.98:                               ;   in Loop: Header=BB0_30 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[14:15], v[4:5], off offset:8
.LBB0_99:                               ;   in Loop: Header=BB0_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[16:17], v[14:15], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[16:17]
	s_cbranch_vccnz .LBB0_101
; %bb.100:                              ;   in Loop: Header=BB0_30 Depth=1
	global_load_b32 v4, v[14:15], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[16:17], v[4:5], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_101:                              ; %Flow422
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v4, vcc_lo, v36, s15
	v_add_co_ci_u32_e32 v15, vcc_lo, s14, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
.LBB0_102:                              ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_102 Depth=2
	global_load_b32 v4, v[14:15], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB0_104:                              ;   in Loop: Header=BB0_102 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_102 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_107
.LBB0_106:                              ;   in Loop: Header=BB0_102 Depth=2
	s_mov_b32 s1, -1
.LBB0_107:                              ; %Flow416
                                        ;   in Loop: Header=BB0_102 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_102
; %bb.108:                              ;   in Loop: Header=BB0_30 Depth=1
	global_load_b128 v[14:17], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_112
; %bb.109:                              ;   in Loop: Header=BB0_30 Depth=1
	s_clause 0x2
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b64 v[16:17], v5, s[2:3] offset:24 glc
	global_load_b64 v[22:23], v5, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v4, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v21, vcc_lo, s11, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[20:21]
	v_cndmask_b32_e32 v21, v21, v24, vcc_lo
	v_cndmask_b32_e32 v20, v20, v4, vcc_lo
	v_and_b32_e32 v4, v21, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v8, v20, v8
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v8, 24
	v_mul_lo_u32 v8, v8, 24
	v_add_nc_u32_e32 v4, v9, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v22, v8
	v_mov_b32_e32 v22, v16
	v_add_co_ci_u32_e32 v9, vcc_lo, v23, v4, vcc_lo
	v_mov_b32_e32 v23, v17
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[22:23], v5, v[20:23], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[22:23], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_112
; %bb.110:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_mov_b32 s0, 0
.LBB0_111:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[8:9], v[22:23], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v5, v[20:23], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[22:23]
	v_dual_mov_b32 v23, v17 :: v_dual_mov_b32 v22, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_111
.LBB0_112:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc1 .LBB0_30
; %bb.113:                              ; %Flow461
	s_mov_b32 s0, 0
	s_branch .LBB0_115
.LBB0_114:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
.LBB0_115:                              ; %Flow476
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_144
; %bb.116:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v14, v40
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v14
	v_cmp_eq_u32_e64 s0, s0, v14
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_122
; %bb.117:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[17:18], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v0, s[2:3] offset:40
	global_load_b64 v[8:9], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v18
	v_and_b32_e32 v4, v4, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v15, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v15, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[15:16], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[17:18]
	s_cbranch_execz .LBB0_121
; %bb.118:                              ; %.preheader3.i.i.i22.preheader
	s_mov_b32 s5, 0
.LBB0_119:                              ; %.preheader3.i.i.i22
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	global_load_b64 v[15:16], v0, s[2:3]
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v17, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v17
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[15:16]
	v_and_b32_e32 v15, v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v15, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[15:16], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[17:18]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_119
; %bb.120:                              ; %Flow473
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_121:                              ; %Flow475
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_122:                              ; %.loopexit4.i.i.i17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v15, 0
	v_readfirstlane_b32 s4, v4
	v_readfirstlane_b32 s5, v5
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[8:9], v15, s[2:3] offset:40
	global_load_b128 v[16:19], v15, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_124
; %bb.123:
	v_dual_mov_b32 v20, s10 :: v_dual_mov_b32 v21, v15
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v16, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v17, vcc_lo
	v_dual_mov_b32 v22, 2 :: v_dual_mov_b32 v23, 1
	global_store_b128 v[4:5], v[20:23], off offset:8
.LBB0_124:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[14:15]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v18, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v19, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v0, v4
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v12, 0xffffff1f, v12, 32
	v_add_co_ci_u32_e32 v5, vcc_lo, v8, v5, vcc_lo
	v_dual_mov_b32 v14, v15 :: v_dual_mov_b32 v21, s15
	v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v19, s13
	v_mov_b32_e32 v18, s12
	s_clause 0x3
	global_store_b128 v[4:5], v[12:15], off
	global_store_b128 v[4:5], v[18:21], off offset:16
	global_store_b128 v[4:5], v[18:21], off offset:32
	global_store_b128 v[4:5], v[18:21], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_132
; %bb.125:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v19, s5
	v_mov_b32_e32 v18, s4
	s_clause 0x1
	global_load_b64 v[20:21], v0, s[2:3] offset:32 glc
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v8
	v_readfirstlane_b32 s11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v8, vcc_lo, v16, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v17, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[8:9], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v0, v[18:21], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[20:21]
	s_cbranch_execz .LBB0_128
; %bb.126:                              ; %.preheader1.i.i.i20.preheader
	s_mov_b32 s10, 0
.LBB0_127:                              ; %.preheader1.i.i.i20
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
	s_sleep 1
	global_store_b64 v[8:9], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v0, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_127
.LBB0_128:                              ; %Flow471
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v13, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v0, s10, 0
	global_load_b64 v[8:9], v13, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_130
; %bb.129:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v12, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[12:13], off offset:8
.LBB0_130:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB0_132
; %bb.131:
	global_load_b32 v8, v[8:9], off offset:24
	v_mov_b32_e32 v9, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v8
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[8:9], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_132:                              ; %Flow472
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v16, s9
	v_add_co_ci_u32_e32 v9, vcc_lo, s8, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB0_133:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_135
; %bb.134:                              ;   in Loop: Header=BB0_133 Depth=1
	global_load_b32 v0, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB0_135:                              ;   in Loop: Header=BB0_133 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_137
; %bb.136:                              ;   in Loop: Header=BB0_133 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_138
.LBB0_137:                              ;   in Loop: Header=BB0_133 Depth=1
	s_mov_b32 s1, -1
.LBB0_138:                              ; %Flow466
                                        ;   in Loop: Header=BB0_133 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_133
; %bb.139:
	global_load_b128 v[14:17], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_143
; %bb.140:
	v_mov_b32_e32 v0, 0
	s_clause 0x2
	global_load_b64 v[4:5], v0, s[2:3] offset:40
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	global_load_b64 v[12:13], v0, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v18, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v18, s4
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[16:17]
	v_dual_cndmask_b32 v17, v17, v19 :: v_dual_cndmask_b32 v16, v16, v18
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v19, v9
	v_and_b32_e32 v5, v17, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v16, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v18, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_dual_mov_b32 v18, v8 :: v_dual_add_nc_u32 v5, v18, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v13, v5, vcc_lo
	global_store_b64 v[4:5], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v0, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[18:19], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_143
; %bb.141:                              ; %.preheader.i.i.i19.preheader
	s_mov_b32 s0, 0
.LBB0_142:                              ; %.preheader.i.i.i19
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v0, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[18:19]
	v_dual_mov_b32 v19, v9 :: v_dual_mov_b32 v18, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_142
.LBB0_143:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_144:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v16, v40
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v16
	v_cmp_eq_u32_e64 s0, s0, v16
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_150
; %bb.145:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[19:20], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v0, s[2:3] offset:40
	global_load_b64 v[8:9], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v20
	v_and_b32_e32 v4, v4, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v12, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v12, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[17:18], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[17:20], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[19:20]
	s_cbranch_execz .LBB0_149
; %bb.146:                              ; %.preheader3.i.i.i29.preheader
	s_mov_b32 s5, 0
.LBB0_147:                              ; %.preheader3.i.i.i29
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	global_load_b64 v[12:13], v0, s[2:3]
	v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v19
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[12:13]
	v_and_b32_e32 v12, v9, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v12, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[17:18], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v0, v[17:20], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[19:20]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_147
; %bb.148:                              ; %Flow409
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_149:                              ; %Flow411
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_150:                              ; %.loopexit4.i.i.i23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v17, 0
	v_readfirstlane_b32 s4, v4
	v_readfirstlane_b32 s5, v5
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[8:9], v17, s[2:3] offset:40
	global_load_b128 v[18:21], v17, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_152
; %bb.151:
	v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, v17
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v18, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v19, vcc_lo
	v_dual_mov_b32 v24, 2 :: v_dual_mov_b32 v25, 1
	global_store_b128 v[4:5], v[22:25], off offset:8
.LBB0_152:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[16:17]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v20, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v21, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v0, v4
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v14, 0xffffff1f, v14, 32
	v_add_co_ci_u32_e32 v5, vcc_lo, v8, v5, vcc_lo
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v23, s15
	v_dual_mov_b32 v22, s14 :: v_dual_mov_b32 v21, s13
	v_mov_b32_e32 v20, s12
	s_clause 0x3
	global_store_b128 v[4:5], v[14:17], off
	global_store_b128 v[4:5], v[20:23], off offset:16
	global_store_b128 v[4:5], v[20:23], off offset:32
	global_store_b128 v[4:5], v[20:23], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_160
; %bb.153:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v15, s5
	v_mov_b32_e32 v14, s4
	s_clause 0x1
	global_load_b64 v[16:17], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v0, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v19, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[0:1], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v8, v[14:17], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[16:17]
	s_cbranch_execz .LBB0_156
; %bb.154:                              ; %.preheader1.i.i.i27.preheader
	s_mov_b32 s10, 0
.LBB0_155:                              ; %.preheader1.i.i.i27
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
	s_sleep 1
	global_store_b64 v[0:1], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v8, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_155
.LBB0_156:                              ; %Flow407
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v9, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v8, s10, 0
	global_load_b64 v[0:1], v9, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB0_158
; %bb.157:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[8:9], off offset:8
.LBB0_158:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB0_160
; %bb.159:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_160:                              ; %Flow408
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v18, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_161:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v8, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_163
; %bb.162:                              ;   in Loop: Header=BB0_161 Depth=1
	global_load_b32 v8, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v8, 1, v8
.LBB0_163:                              ;   in Loop: Header=BB0_161 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v8
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_165
; %bb.164:                              ;   in Loop: Header=BB0_161 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_166
.LBB0_165:                              ;   in Loop: Header=BB0_161 Depth=1
	s_mov_b32 s1, -1
.LBB0_166:                              ; %Flow402
                                        ;   in Loop: Header=BB0_161 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_161
; %bb.167:
	global_load_b64 v[8:9], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_171
; %bb.168:
	v_mov_b32_e32 v4, 0
	s_clause 0x2
	global_load_b64 v[0:1], v4, s[2:3] offset:40
	global_load_b64 v[16:17], v4, s[2:3] offset:24 glc
	global_load_b64 v[14:15], v4, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v5, s4
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v5
	v_and_b32_e32 v1, v13, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, v12, v0
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, vcc_lo, v14, v0
	v_mov_b32_e32 v14, v16
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo
	v_mov_b32_e32 v15, v17
	global_store_b64 v[0:1], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v4, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_171
; %bb.169:                              ; %.preheader.i.i.i26.preheader
	s_mov_b32 s0, 0
.LBB0_170:                              ; %.preheader.i.i.i26
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v4, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[14:15]
	v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_170
.LBB0_171:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v0, v40
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_177
; %bb.172:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[14:15], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v1, s[2:3] offset:40
	global_load_b64 v[12:13], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v14
	v_and_b32_e32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v16, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v16, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v13, v5, vcc_lo
	global_load_b64 v[12:13], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v1, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[14:15]
	s_cbranch_execz .LBB0_176
; %bb.173:                              ; %.preheader3.i.i.i36.preheader
	s_mov_b32 s5, 0
.LBB0_174:                              ; %.preheader3.i.i.i36
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[12:13], v1, s[2:3] offset:40
	global_load_b64 v[16:17], v1, s[2:3]
	v_dual_mov_b32 v15, v5 :: v_dual_mov_b32 v14, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v12, v12, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v12, 24, v[16:17]
	v_and_b32_e32 v16, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v16, 24, v[5:6]
	v_mov_b32_e32 v5, v12
	global_load_b64 v[12:13], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v1, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[14:15]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_174
; %bb.175:                              ; %Flow395
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_176:                              ; %Flow397
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_177:                              ; %.loopexit4.i.i.i30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	v_readfirstlane_b32 s4, v4
	v_readfirstlane_b32 s5, v5
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[16:17], v1, s[2:3] offset:40
	global_load_b128 v[12:15], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v16
	v_readfirstlane_b32 s7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_179
; %bb.178:
	v_dual_mov_b32 v16, s10 :: v_dual_mov_b32 v17, v1
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v13, vcc_lo
	v_dual_mov_b32 v18, 2 :: v_dual_mov_b32 v19, 1
	global_store_b128 v[4:5], v[16:19], off offset:8
.LBB0_179:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v14, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v15, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v8, 0xffffff1f, v8, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
	v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
	s_clause 0x3
	global_store_b128 v[0:1], v[8:11], off
	global_store_b128 v[0:1], v[14:17], off offset:16
	global_store_b128 v[0:1], v[14:17], off offset:32
	global_store_b128 v[0:1], v[14:17], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_187
; %bb.180:
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v15, s4
	v_mov_b32_e32 v16, s5
	s_clause 0x1
	global_load_b64 v[17:18], v14, s[2:3] offset:32 glc
	global_load_b64 v[4:5], v14, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v4, vcc_lo, v12, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v13, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[4:5], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v14, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[10:11], v[17:18]
	s_cbranch_execz .LBB0_183
; %bb.181:                              ; %.preheader1.i.i.i34.preheader
	s_mov_b32 s10, 0
.LBB0_182:                              ; %.preheader1.i.i.i34
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v9, s5
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v14, v[8:11], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_182
.LBB0_183:                              ; %Flow393
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v9, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v8, s10, 0
	global_load_b64 v[4:5], v9, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB0_185
; %bb.184:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[8:9], off offset:8
.LBB0_185:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB0_187
; %bb.186:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[4:5], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_187:                              ; %Flow394
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v4, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_188:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v8, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_190
; %bb.189:                              ;   in Loop: Header=BB0_188 Depth=1
	global_load_b32 v8, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v8, 1, v8
.LBB0_190:                              ;   in Loop: Header=BB0_188 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v8
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_192
; %bb.191:                              ;   in Loop: Header=BB0_188 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_193
.LBB0_192:                              ;   in Loop: Header=BB0_188 Depth=1
	s_mov_b32 s1, -1
.LBB0_193:                              ; %Flow388
                                        ;   in Loop: Header=BB0_188 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_188
; %bb.194:
	global_load_b64 v[4:5], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_198
; %bb.195:
	v_mov_b32_e32 v12, 0
	s_clause 0x2
	global_load_b64 v[0:1], v12, s[2:3] offset:40
	global_load_b64 v[13:14], v12, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v12, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v15, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v15, s4
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v16 :: v_dual_cndmask_b32 v8, v8, v15
	v_and_b32_e32 v1, v9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v8, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v15, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v15, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v10, v0
	v_mov_b32_e32 v10, v13
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	v_mov_b32_e32 v11, v14
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v12, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_198
; %bb.196:                              ; %.preheader.i.i.i33.preheader
	s_mov_b32 s0, 0
.LBB0_197:                              ; %.preheader.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v12, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[10:11]
	v_dual_mov_b32 v10, v13 :: v_dual_mov_b32 v11, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_197
.LBB0_198:                              ; %__ockl_printf_append_args.exit37
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v0, v40
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_204
; %bb.199:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[10:11], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v1, s[2:3] offset:40
	global_load_b64 v[12:13], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v10
	v_and_b32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v14, v8, 24
	v_mul_lo_u32 v9, v9, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v14, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[12:13], v1, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[12:13], v[10:11]
	s_cbranch_execz .LBB0_203
; %bb.200:                              ; %.preheader3.i.i.i44.preheader
	s_mov_b32 s5, 0
.LBB0_201:                              ; %.preheader3.i.i.i44
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v1, s[2:3] offset:40
	global_load_b64 v[14:15], v1, s[2:3]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v8, v8, v10
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v8, 24, v[14:15]
	v_mov_b32_e32 v8, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, v9, 24, v[8:9]
	global_load_b64 v[8:9], v[12:13], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[12:13], v1, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_201
; %bb.202:                              ; %Flow381
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_203:                              ; %Flow383
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_204:                              ; %.loopexit4.i.i.i38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	v_readfirstlane_b32 s4, v12
	v_readfirstlane_b32 s5, v13
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v1, s[2:3] offset:40
	global_load_b128 v[8:11], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v14
	v_readfirstlane_b32 s7, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_206
; %bb.205:
	v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, v1
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v16, vcc_lo, v8, s9
	v_add_co_ci_u32_e32 v17, vcc_lo, s10, v9, vcc_lo
	v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1
	global_store_b128 v[16:17], v[12:15], off offset:8
.LBB0_206:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v4, 0xffffff1f, v4, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v13, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[4:7], off
	global_store_b128 v[0:1], v[10:13], off offset:16
	global_store_b128 v[0:1], v[10:13], off offset:32
	global_store_b128 v[0:1], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_214
; %bb.207:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s4
	v_mov_b32_e32 v14, s5
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[2:3] offset:32 glc
	global_load_b64 v[4:5], v12, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v10, vcc_lo, v8, s10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v9, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[10:11], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[15:16]
	s_cbranch_execz .LBB0_210
; %bb.208:                              ; %.preheader1.i.i.i42.preheader
	s_mov_b32 s10, 0
.LBB0_209:                              ; %.preheader1.i.i.i42
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
	s_sleep 1
	global_store_b64 v[10:11], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v12, v[4:7], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_209
.LBB0_210:                              ; %Flow379
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v7, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v6, s10, 0
	global_load_b64 v[4:5], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB0_212
; %bb.211:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[6:7], off offset:8
.LBB0_212:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB0_214
; %bb.213:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[4:5], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_214:                              ; %Flow380
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v4, vcc_lo, v8, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_215:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_217
; %bb.216:                              ;   in Loop: Header=BB0_215 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_217:                              ;   in Loop: Header=BB0_215 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_219
; %bb.218:                              ;   in Loop: Header=BB0_215 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_220
.LBB0_219:                              ;   in Loop: Header=BB0_215 Depth=1
	s_mov_b32 s1, -1
.LBB0_220:                              ; %Flow374
                                        ;   in Loop: Header=BB0_215 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_215
; %bb.221:
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_225
; %bb.222:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[6:7], v10, s[2:3] offset:40
	global_load_b64 v[11:12], v10, s[2:3] offset:24 glc
	global_load_b64 v[8:9], v10, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v13, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v14 :: v_dual_cndmask_b32 v4, v4, v13
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v4, v6
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v6, 24
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v7, v13, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v12
	global_store_b64 v[8:9], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v10, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_225
; %bb.223:                              ; %.preheader.i.i.i41.preheader
	s_mov_b32 s0, 0
.LBB0_224:                              ; %.preheader.i.i.i41
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[6:7]
	v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v7, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_224
.LBB0_225:                              ; %__ockl_printf_append_args.exit45
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v40
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v40
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_231
; %bb.226:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[10:11], v4, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[2:3] offset:40
	global_load_b64 v[7:8], v4, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v10
	v_and_b32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v5, 24
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v9, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v7, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v8, v6, vcc_lo
	global_load_b64 v[8:9], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v4, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[10:11]
	s_cbranch_execz .LBB0_230
; %bb.227:                              ; %.preheader3.i.i.i52.preheader
	s_mov_b32 s5, 0
.LBB0_228:                              ; %.preheader3.i.i.i52
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[2:3] offset:40
	global_load_b64 v[12:13], v4, s[2:3]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v5, 24, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v8 :: v_dual_and_b32 v6, v6, v11
	v_mad_u64_u32 v[8:9], null, v6, 24, v[5:6]
	global_load_b64 v[8:9], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v4, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_228
; %bb.229:                              ; %Flow367
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_230:                              ; %Flow369
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_231:                              ; %.loopexit4.i.i.i46
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v41, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v41, s[2:3] offset:40
	global_load_b128 v[4:7], v41, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_233
; %bb.232:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v41
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_233:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	s_mov_b32 s12, 0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
	v_lshlrev_b64 v[6:7], 6, v[40:41]
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v8, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, v9, v7, vcc_lo
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13
	v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, s15
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_241
; %bb.234:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v6, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB0_237
; %bb.235:                              ; %.preheader1.i.i.i50.preheader
	s_mov_b32 s10, 0
.LBB0_236:                              ; %.preheader1.i.i.i50
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_236
.LBB0_237:                              ; %Flow365
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_239
; %bb.238:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_239:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_241
; %bb.240:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_241:                              ; %Flow366
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_242:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_244
; %bb.243:                              ;   in Loop: Header=BB0_242 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_244:                              ;   in Loop: Header=BB0_242 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_246
; %bb.245:                              ;   in Loop: Header=BB0_242 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_247
.LBB0_246:                              ;   in Loop: Header=BB0_242 Depth=1
	s_mov_b32 s1, -1
.LBB0_247:                              ; %Flow360
                                        ;   in Loop: Header=BB0_242 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_242
; %bb.248:
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_252
; %bb.249:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_252
; %bb.250:                              ; %.preheader.i.i.i49.preheader
	s_mov_b32 s0, 0
.LBB0_251:                              ; %.preheader.i.i.i49
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_251
.LBB0_252:                              ; %__ockl_printf_append_args.exit53
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3sumiPdS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 42
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3sumiPdS_S_, .Lfunc_end0-_Z3sumiPdS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10908
; NumSgprs: 20
; NumVgprs: 42
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 42
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"check from function i= %d %f + %f = %f\n"
	.size	.str, 40

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3sumiPdS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z3sumiPdS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     42
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
