//
//  CasAES128_CUDA.c
//  CasAES128_CUDA
//  Created by Carter McCardwell on 11/11/14.
//

#include <stdint.h>
#include <stdio.h>
#include <time.h>
#include <string.h>

#include <cuda_runtime.h>

struct timing_pair{
	long time;
	long times[4];
	char cipher[16];
	char hits[10][4][4];
	//long memory_usage;
	//int ctx_delta;
	//unsigned long tp_delta;
	//unsigned short cp_delta;
};

const int Nb_h = 4;
const int Nr_h = 10;
const int Nk_h = 4;

const uint8_t s_h[256]=
{
		0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
		0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
		0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
		0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
		0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
		0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
		0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
		0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
		0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
		0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
		0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
		0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
		0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
		0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
		0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
		0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
};

uint8_t Rcon_h[256] = {
		0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a,
		0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39,
		0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a,
		0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
		0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef,
		0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc,
		0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b,
		0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3,
		0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94,
		0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20,
		0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35,
		0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f,
		0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04,
		0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63,
		0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd,
		0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d
};

__constant__ uint8_t s[256];
__constant__ int Nb;
__constant__ int Nr;
__constant__ int Nk;
__constant__ uint32_t ek[44];

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void cudaDevAssist(cudaError_t code, int line, bool abort=true)
{
	if (code != cudaSuccess)
	{
		fprintf(stderr,"cudaDevAssistant: %s %d\n", cudaGetErrorString(code), line);
		if (abort) exit(code);
	}
}

uint32_t sw(uint32_t word)
{
	union {
		uint32_t word;
		uint8_t bytes[4];
	} subWord  __attribute__ ((aligned));
	subWord.word = word;

	subWord.bytes[3] = s_h[subWord.bytes[3]];
	subWord.bytes[2] = s_h[subWord.bytes[2]];
	subWord.bytes[1] = s_h[subWord.bytes[1]];
	subWord.bytes[0] = s_h[subWord.bytes[0]];

	return subWord.word;
}

__device__ void sb(uint8_t* in)
{
	for (int i = 0; i < 16; i++) { in[i] = s[in[i]]; }
}

__device__ void mc(uint8_t* arr)
{
	for (int i = 0; i < 4; i++)
	{
		uint8_t a[4];
		uint8_t b[4];
		uint8_t c;
		uint8_t h;
		for(c=0;c<4;c++) {
			a[c] = arr[(4*c+i)];
			h = (uint8_t)((signed char)arr[(4*c+i)] >> 7);
			b[c] = arr[(4*c+i)] << 1;
			b[c] ^= 0x1B & h;
		}
		arr[(i)] = b[0] ^ a[3] ^ a[2] ^ b[1] ^ a[1];
		arr[(4+i)] = b[1] ^ a[0] ^ a[3] ^ b[2] ^ a[2];
		arr[(8+i)] = b[2] ^ a[1] ^ a[0] ^ b[3] ^ a[3];
		arr[(12+i)] = b[3] ^ a[2] ^ a[1] ^ b[0] ^ a[0];
	}

}

__device__ void sr(uint8_t* arr)
{
	uint8_t out[16];
	//On per-row basis (+1 shift ea row)
	//Row 1
	out[0] = arr[0];
	out[1] = arr[1];
	out[2] = arr[2];
	out[3] = arr[3];
	//Row 2
	out[4] = arr[5];
	out[5] = arr[6];
	out[6] = arr[7];
	out[7] = arr[4];
	//Row 3
	out[8] = arr[10];
	out[9] = arr[11];
	out[10] = arr[8];
	out[11] = arr[9];
	//Row 4
	out[12] = arr[15];
	out[13] = arr[12];
	out[14] = arr[13];
	out[15] = arr[14];

	for (int i = 0; i < 16; i++)
	{
		arr[i] = out[i];
	}
}

uint32_t rw(uint32_t word)
{
	union {
		uint8_t bytes[4];
		uint32_t word;
	} subWord  __attribute__ ((aligned));
	subWord.word = word;

	uint8_t B0 = subWord.bytes[3], B1 = subWord.bytes[2], B2 = subWord.bytes[1], B3 = subWord.bytes[0];
	subWord.bytes[3] = B1; //0
	subWord.bytes[2] = B2; //1
	subWord.bytes[1] = B3; //2
	subWord.bytes[0] = B0; //3

	return subWord.word;
}

	void K_Exp(uint8_t* pk, uint32_t* out)
	{
		int i = 0;
		union {
			uint8_t bytes[4];
			uint32_t word;
		} temp __attribute__ ((aligned));
		union {
			uint8_t bytes[4];
			uint32_t word;
		} univar[44] __attribute__ ((aligned));

		for (i = 0; i < Nk_h; i++)
		{
			univar[i].bytes[3] = pk[i*4];
			univar[i].bytes[2] = pk[i*4+1];
			univar[i].bytes[1] = pk[i*4+2];
			univar[i].bytes[0] = pk[i*4+3];
		}

		for (i = Nk_h; i < Nb_h*(Nr_h+1); i++)
		{
			temp.word = univar[i-1].word;
			if (i % Nk_h == 0)
			{
				temp.word = (sw(rw(temp.word)));
				temp.bytes[3] = temp.bytes[3] ^ (Rcon_h[i/Nk_h]);
			}
			else if (Nk_h > 6 && i % Nk_h == 4)
			{
				temp.word = sw(temp.word);
			}
			if (i-4 % Nk_h == 0)
			{
				temp.word = sw(temp.word);
			}
			univar[i].word = univar[i-Nk_h].word ^ temp.word;
		}
		for (i = 0; i < 44; i++)
		{
			out[i] = univar[i].word;
		}
	}


__device__ void ark(uint8_t* state, int strD)
{
    union {
	    	uint32_t word;
	    	uint8_t bytes[4];
	  } zero __attribute__ ((aligned));
    union {
        uint32_t word;
        uint8_t bytes[4];
    } one __attribute__ ((aligned));
    union {
        uint32_t word;
        uint8_t bytes[4];
    } two __attribute__ ((aligned));
    union {
        uint32_t word;
        uint8_t bytes[4];
    } three __attribute__ ((aligned));

	  zero.word = ek[strD];
	  one.word = ek[strD+1];
	  two.word = ek[strD+2];
	  three.word = ek[strD+3];

    state[0] = state[0] ^ zero.bytes[3];
    state[4] = state[4] ^ zero.bytes[2];
    state[8] = state[8] ^ zero.bytes[1];
    state[12] = state[12] ^ zero.bytes[0];

    state[1] = state[1] ^ one.bytes[3];
    state[5] = state[5] ^ one.bytes[2];
    state[9] = state[9] ^ one.bytes[1];
    state[13] = state[13] ^ one.bytes[0];

    state[2] = state[2] ^ two.bytes[3];
    state[6] = state[6] ^ two.bytes[2];
    state[10] = state[10] ^ two.bytes[1];
    state[14] = state[14] ^ two.bytes[0];

    state[3] = state[3] ^ three.bytes[3];
    state[7] = state[7] ^ three.bytes[2];
    state[11] = state[11] ^ three.bytes[1];
    state[15] = state[15] ^ three.bytes[0];

}

__global__ void cudaRunner(uint8_t *in)
{
	uint8_t state[16];
  int localid = blockDim.x * blockIdx.x + threadIdx.x; //Data is shifted by 16 * ID of worker
  for (int i = 0; i < 16; i++) { state[i] = in[(localid*16)+i]; }

	ark(state, 0);
	for (int i = 1; i < Nr; i++)
	{
		sb(state);
		sr(state);
		mc(state);
		ark(state, i*Nb);
	}

	sb(state);
	sr(state);
	ark(state, Nr*Nb);

	for (int i = 0; i < 16; i++) { in[(localid*16)+i] = state[i]; }
}

long AES_CUDA(char* in_cypher, char* cypher, char* in_key)
{
	clock_t c_start, c_stop;
	c_start = clock();

	uint8_t key[16];
	uint32_t ek_h[44];
	uint8_t states[16] = { 0x00 };

	for (int i = 0; i < 16; i++)
	{
		states[i] = in_cypher[i];
		key[i] = in_key[i];
	}

	K_Exp(key, ek_h);

	//send constants to GPU
	cudaSetDevice(0);
	cudaDevAssist(cudaMemcpyToSymbol(Nk, &Nk_h, sizeof(int), 0, cudaMemcpyHostToDevice), 535, true);
	cudaDevAssist(cudaMemcpyToSymbol(Nr, &Nr_h, sizeof(int), 0, cudaMemcpyHostToDevice), 543, true);
	cudaDevAssist(cudaMemcpyToSymbol(Nb, &Nb_h, sizeof(int), 0, cudaMemcpyHostToDevice), 903, true);
	cudaDevAssist(cudaMemcpyToSymbol(s, &s_h, 256*sizeof(uint8_t), 0, cudaMemcpyHostToDevice), 920, true);
	cudaDevAssist(cudaMemcpyToSymbol(ek, &ek_h, 44*sizeof(uint32_t), 0, cudaMemcpyHostToDevice), 823, true);
	cudaThreadSynchronize();


	uint8_t *devState = NULL;
	cudaDevAssist(cudaMalloc((void**)&devState, 16*sizeof(uint8_t)), 425, true);
		//arrange data correctly
			uint8_t temp[16];
			memcpy(&temp[0], &states[0], sizeof(uint8_t));
			memcpy(&temp[4], &states[1], sizeof(uint8_t));
			memcpy(&temp[8], &states[2], sizeof(uint8_t));
			memcpy(&temp[12], &states[3], sizeof(uint8_t));
			memcpy(&temp[1], &states[4], sizeof(uint8_t));
			memcpy(&temp[5], &states[5], sizeof(uint8_t));
			memcpy(&temp[9], &states[6], sizeof(uint8_t));
			memcpy(&temp[13], &states[7], sizeof(uint8_t));
			memcpy(&temp[2], &states[8], sizeof(uint8_t));
			memcpy(&temp[6], &states[9], sizeof(uint8_t));
			memcpy(&temp[10], &states[10], sizeof(uint8_t));
			memcpy(&temp[14], &states[11], sizeof(uint8_t));
			memcpy(&temp[3], &states[12], sizeof(uint8_t));
			memcpy(&temp[7], &states[13], sizeof(uint8_t));
			memcpy(&temp[11], &states[14], sizeof(uint8_t));
			memcpy(&temp[15], &states[15], sizeof(uint8_t));
			for (int c = 0; c < 16; c++) { memcpy(&states[c], &temp[c], sizeof(uint8_t)); }

		cudaDevAssist(cudaMemcpy(devState, states, 16*sizeof(uint8_t), cudaMemcpyHostToDevice), 426, true);
		cudaDevAssist(cudaDeviceSynchronize(), 268, true);
		cudaRunner<<<1,1>>>(devState);

		cudaDevAssist(cudaDeviceSynchronize(), 270, true);
		cudaDevAssist(cudaMemcpy(states, devState, 16*sizeof(uint8_t), cudaMemcpyDeviceToHost), 431, true);

			memcpy(&cypher[0], &states[0], sizeof(uint8_t));
			memcpy(&cypher[4], &states[1], sizeof(uint8_t));
			memcpy(&cypher[8], &states[2], sizeof(uint8_t));
			memcpy(&cypher[12], &states[3], sizeof(uint8_t));
			memcpy(&cypher[1], &states[4], sizeof(uint8_t));
			memcpy(&cypher[5], &states[5], sizeof(uint8_t));
			memcpy(&cypher[9], &states[6], sizeof(uint8_t));
			memcpy(&cypher[13], &states[7], sizeof(uint8_t));
			memcpy(&cypher[2], &states[8], sizeof(uint8_t));
			memcpy(&cypher[6], &states[9], sizeof(uint8_t));
			memcpy(&cypher[10], &states[10], sizeof(uint8_t));
			memcpy(&cypher[14], &states[11], sizeof(uint8_t));
			memcpy(&cypher[3], &states[12], sizeof(uint8_t));
			memcpy(&cypher[7], &states[13], sizeof(uint8_t));
			memcpy(&cypher[11], &states[14], sizeof(uint8_t));
			memcpy(&cypher[15], &states[15], sizeof(uint8_t));

  c_stop = clock();
  float diff = (((float)c_stop - (float)c_start) / CLOCKS_PER_SEC ) * 1000;
	cudaFree(devState);
	cudaDeviceReset();
	return diff;
}

	.file	"tmpxft_00360858_00000000-6_CasAES128_CUDA_NOUNAR_asFUNCT.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z13cudaDevAssist9cudaErrorib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cudaDevAssistant: %s %d\n"
	.section	.text._Z13cudaDevAssist9cudaErrorib,"axG",@progbits,_Z13cudaDevAssist9cudaErrorib,comdat
	.weak	_Z13cudaDevAssist9cudaErrorib
	.type	_Z13cudaDevAssist9cudaErrorib, @function
_Z13cudaDevAssist9cudaErrorib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%esi, 12(%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r8d
	movl	$2, %esi
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	leaq	.LC0(%rip), %rdx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z13cudaDevAssist9cudaErrorib, .-_Z13cudaDevAssist9cudaErrorib
	.text
	.globl	_Z2swj
	.type	_Z2swj, @function
_Z2swj:
.LFB2028:
	.cfi_startproc
	endbr64
	movl	%edi, %esi
	movl	%edi, %eax
	leaq	_ZL3s_h(%rip), %rcx
	movl	%edi, %edx
	shrl	$16, %esi
	shrl	$24, %eax
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	popq	%rbx
	.cfi_def_cfa_offset 8
	movzbl	%sil, %esi
	movzbl	(%rcx,%rax), %eax
	movzbl	(%rcx,%rsi), %esi
	sall	$24, %eax
	sall	$16, %esi
	orl	%esi, %eax
	movzbl	%dh, %esi
	movzbl	%dil, %edx
	movb	(%rcx,%rsi), %ah
	movb	(%rcx,%rdx), %al
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z2swj, .-_Z2swj
	.globl	_Z2sbPh
	.type	_Z2sbPh, @function
_Z2sbPh:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z2sbPh, .-_Z2sbPh
	.globl	_Z2mcPh
	.type	_Z2mcPh, @function
_Z2mcPh:
.LFB2184:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2sbPh
	.cfi_endproc
.LFE2184:
	.size	_Z2mcPh, .-_Z2mcPh
	.globl	_Z2srPh
	.type	_Z2srPh, @function
_Z2srPh:
.LFB2186:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z2sbPh
	.cfi_endproc
.LFE2186:
	.size	_Z2srPh, .-_Z2srPh
	.globl	_Z2rwj
	.type	_Z2rwj, @function
_Z2rwj:
.LFB2032:
	.cfi_startproc
	endbr64
	movl	%edi, %eax
	movzwl	%di, %edx
	shrl	$24, %edi
	shrl	$16, %eax
	sall	$8, %edx
	sall	$24, %eax
	orl	%edx, %eax
	movb	%dil, %al
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z2rwj, .-_Z2rwj
	.globl	_Z5K_ExpPhPj
	.type	_Z5K_ExpPhPj, @function
_Z5K_ExpPhPj:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rsi, %r9
	leaq	16(%rdi), %rdx
	subq	$192, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %r8
	movq	%r8, %rax
	movq	%r8, %r11
.L22:
	movb	(%rdi), %cl
	addq	$4, %rdi
	addq	$4, %rax
	movb	%cl, -1(%rax)
	movb	-3(%rdi), %cl
	movb	%cl, -2(%rax)
	movb	-2(%rdi), %cl
	movb	%cl, -3(%rax)
	movb	-1(%rdi), %cl
	movb	%cl, -4(%rax)
	cmpq	%rdx, %rdi
	jne	.L22
	movl	$4, %r10d
	leaq	Rcon_h(%rip), %rbx
.L25:
	movl	12(%r8), %edi
	movl	%edi, %eax
	testl	$3, %r10d
	jne	.L24
	call	_Z2rwj
	movl	%eax, %edi
	call	_Z2swj
	movl	%r10d, %ecx
	sarl	$2, %ecx
	movl	%eax, %edx
	andl	$16777215, %eax
	movslq	%ecx, %rcx
	shrl	$24, %edx
	xorb	(%rbx,%rcx), %dl
	sall	$24, %edx
	orl	%edx, %eax
.L24:
	xorl	(%r8), %eax
	incl	%r10d
	addq	$4, %r8
	movl	%eax, 12(%r8)
	cmpl	$44, %r10d
	jne	.L25
	movl	$44, %ecx
	movq	%r9, %rdi
	movq	%r11, %rsi
	rep movsl
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$192, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z5K_ExpPhPj, .-_Z5K_ExpPhPj
	.globl	_Z3arkPhi
	.type	_Z3arkPhi, @function
_Z3arkPhi:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2034:
	.size	_Z3arkPhi, .-_Z3arkPhi
	.globl	_Z30__device_stub__Z10cudaRunnerPhPh
	.type	_Z30__device_stub__Z10cudaRunnerPhPh, @function
_Z30__device_stub__Z10cudaRunnerPhPh:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10cudaRunnerPh(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L32:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z30__device_stub__Z10cudaRunnerPhPh, .-_Z30__device_stub__Z10cudaRunnerPhPh
	.globl	_Z10cudaRunnerPh
	.type	_Z10cudaRunnerPh, @function
_Z10cudaRunnerPh:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10cudaRunnerPhPh
	.cfi_endproc
.LFE2061:
	.size	_Z10cudaRunnerPh, .-_Z10cudaRunnerPh
	.globl	_Z8AES_CUDAPcS_S_
	.type	_Z8AES_CUDAPcS_S_, @function
_Z8AES_CUDAPcS_S_:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$272, %rsp
	.cfi_def_cfa_offset 320
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	248(%rsp), %rbp
	call	clock@PLT
	xorps	%xmm0, %xmm0
	movq	%rax, %rbx
	movups	%xmm0, 248(%rsp)
	xorl	%eax, %eax
.L38:
	movb	(%r14,%rax), %dl
	leaq	232(%rsp), %rdi
	movb	%dl, (%rax,%rbp)
	movb	0(%r13,%rax), %dl
	movb	%dl, 232(%rsp,%rax)
	incq	%rax
	cmpq	$16, %rax
	jne	.L38
	leaq	56(%rsp), %r13
	movq	%r13, %rsi
	call	_Z5K_ExpPhPj
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movl	$4, %edx
	leaq	_ZL4Nk_h(%rip), %rsi
	leaq	_ZL2Nk(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$1, %edx
	movl	$535, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movl	$4, %edx
	leaq	_ZL4Nr_h(%rip), %rsi
	leaq	_ZL2Nr(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$1, %edx
	movl	$543, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movl	$4, %edx
	leaq	_ZL4Nb_h(%rip), %rsi
	leaq	_ZL2Nb(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$1, %edx
	movl	$903, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movl	$256, %edx
	leaq	_ZL3s_h(%rip), %rsi
	leaq	_ZL1s(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$1, %edx
	movl	$920, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%r13, %rsi
	movl	$176, %edx
	leaq	_ZL2ek(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	$1, %edx
	movl	$823, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	call	cudaThreadSynchronize@PLT
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	movl	$16, %esi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %edx
	movl	$425, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	movzbl	249(%rsp), %edx
	movzbl	248(%rsp), %eax
	movabsq	$-280375465082881, %rdi
	movzbl	250(%rsp), %ecx
	movzbl	255(%rsp), %esi
	salq	$32, %rdx
	orq	%rdx, %rax
	movzbl	251(%rsp), %edx
	movb	252(%rsp), %ah
	salq	$40, %rsi
	salq	$32, %rdx
	andq	%rdi, %rax
	orq	%rdx, %rcx
	movzbl	253(%rsp), %edx
	movb	254(%rsp), %ch
	salq	$40, %rdx
	andq	%rdi, %rcx
	movabsq	$-4278190081, %rdi
	orq	%rdx, %rax
	movq	%rcx, %rdx
	movzbl	256(%rsp), %ecx
	orq	%rsi, %rdx
	movabsq	$-71776119061217281, %rsi
	salq	$16, %rcx
	andq	$-16711681, %rax
	andq	$-16711681, %rdx
	orq	%rcx, %rax
	movzbl	257(%rsp), %ecx
	andq	%rsi, %rax
	salq	$48, %rcx
	orq	%rcx, %rax
	movzbl	258(%rsp), %ecx
	andq	%rdi, %rax
	salq	$16, %rcx
	orq	%rcx, %rdx
	movzbl	259(%rsp), %ecx
	andq	%rsi, %rdx
	movabsq	$72057594037927935, %rsi
	salq	$48, %rcx
	orq	%rcx, %rdx
	movzbl	260(%rsp), %ecx
	andq	%rdi, %rdx
	movq	24(%rsp), %rdi
	salq	$24, %rcx
	orq	%rcx, %rax
	movzbl	261(%rsp), %ecx
	andq	%rsi, %rax
	salq	$56, %rcx
	orq	%rcx, %rax
	movzbl	262(%rsp), %ecx
	movq	%rax, 248(%rsp)
	salq	$24, %rcx
	orq	%rcx, %rdx
	movzbl	263(%rsp), %ecx
	andq	%rsi, %rdx
	movq	%rbp, %rsi
	salq	$56, %rcx
	orq	%rcx, %rdx
	movl	$1, %ecx
	movq	%rdx, 256(%rsp)
	movl	$16, %edx
	call	cudaMemcpy@PLT
	movl	$1, %edx
	movl	$426, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %edx
	movl	$268, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	movq	24(%rsp), %rdi
	call	_Z30__device_stub__Z10cudaRunnerPhPh
.L39:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %edx
	movl	$270, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$16, %edx
	call	cudaMemcpy@PLT
	movl	$1, %edx
	movl	$431, %esi
	movl	%eax, %edi
	call	_Z13cudaDevAssist9cudaErrorib
	movb	248(%rsp), %al
	movb	%al, (%r12)
	movb	249(%rsp), %al
	movb	%al, 4(%r12)
	movb	250(%rsp), %al
	movb	%al, 8(%r12)
	movb	251(%rsp), %al
	movb	%al, 12(%r12)
	movb	252(%rsp), %al
	movb	%al, 1(%r12)
	movb	253(%rsp), %al
	movb	%al, 5(%r12)
	movb	254(%rsp), %al
	movb	%al, 9(%r12)
	movb	255(%rsp), %al
	movb	%al, 13(%r12)
	movb	256(%rsp), %al
	movb	%al, 2(%r12)
	movb	257(%rsp), %al
	movb	%al, 6(%r12)
	movb	258(%rsp), %al
	movb	%al, 10(%r12)
	movb	259(%rsp), %al
	movb	%al, 14(%r12)
	movb	260(%rsp), %al
	movb	%al, 3(%r12)
	movb	261(%rsp), %al
	movb	%al, 7(%r12)
	movb	262(%rsp), %al
	movb	%al, 11(%r12)
	movb	263(%rsp), %al
	movb	%al, 15(%r12)
	call	clock@PLT
	cvtsi2ssq	%rbx, %xmm1
	movq	24(%rsp), %rdi
	cvtsi2ssq	%rax, %xmm0
	subss	%xmm1, %xmm0
	divss	.LC1(%rip), %xmm0
	mulss	.LC2(%rip), %xmm0
	movss	%xmm0, 12(%rsp)
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	movss	12(%rsp), %xmm0
	cvttss2siq	%xmm0, %rax
	movq	264(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$272, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z8AES_CUDAPcS_S_, .-_Z8AES_CUDAPcS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"_Z10cudaRunnerPh"
.LC5:
	.string	"s"
.LC6:
	.string	"Nb"
.LC7:
	.string	"Nr"
.LC8:
	.string	"Nk"
.LC9:
	.string	"ek"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10cudaRunnerPh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movl	$256, %r9d
	leaq	_ZL1s(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL2Nb(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL2Nr(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL2Nk(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$176, %r9d
	movq	%rdx, %rcx
	leaq	_ZL2ek(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL2ek
	.comm	_ZL2ek,176,32
	.local	_ZL2Nk
	.comm	_ZL2Nk,4,4
	.local	_ZL2Nr
	.comm	_ZL2Nr,4,4
	.local	_ZL2Nb
	.comm	_ZL2Nb,4,4
	.local	_ZL1s
	.comm	_ZL1s,256,32
	.globl	Rcon_h
	.data
	.align 32
	.type	Rcon_h, @object
	.size	Rcon_h, 256
Rcon_h:
	.ascii	"\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\227"
	.ascii	"5j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314"
	.ascii	"\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253"
	.ascii	"M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275"
	.ascii	"a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020"
	.ascii	" @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305"
	.ascii	"\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215"
	.ascii	"\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j"
	.ascii	"\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314"
	.ascii	"\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253"
	.ascii	"M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275"
	.ascii	"a\302\237%J\2243f\314\203\035:t\350\313\215"
	.section	.rodata
	.align 32
	.type	_ZL3s_h, @object
	.size	_ZL3s_h, 256
_ZL3s_h:
	.string	"c|w{\362ko\3050\001g+\376\327\253v\312\202\311}\372YG\360\255\324\242\257\234\244r\300\267\375\223&6?\367\3144\245\345\361q\3301\025\004\307#\303\030\226\005\232\007\022\200\342\353'\262u\t\203,\032\033nZ\240R;\326\263)\343/\204S\321"
	.ascii	"\355 \374\261[j\313\2769JLX\317\320\357\252\373CM3\205E\371\002"
	.ascii	"\177P<\237\250Q\243@\217\222\2358\365\274\266\332!\020\377\363"
	.ascii	"\322\315\f\023\354_\227D\027\304\247~=d]\031s`\201O\334\"*\220"
	.ascii	"\210F\356\270\024\336^\013\333\3402:\nI\006$\\\302\323\254b\221"
	.ascii	"\225\344y\347\3107m\215\325N\251lV\364\352ez\256\b\272x%.\034"
	.ascii	"\246\264\306\350\335t\037K\275\213\212p>\265fH\003\366\016a5"
	.ascii	"W\271\206\301\035\236\341\370\230\021i\331\216\224\233\036\207"
	.ascii	"\351\316U(\337\214\241\211\r\277\346BhA\231-\017\260T\273\026"
	.align 4
	.type	_ZL4Nk_h, @object
	.size	_ZL4Nk_h, 4
_ZL4Nk_h:
	.long	4
	.align 4
	.type	_ZL4Nr_h, @object
	.size	_ZL4Nr_h, 4
_ZL4Nr_h:
	.long	10
	.align 4
	.type	_ZL4Nb_h, @object
	.size	_ZL4Nb_h, 4
_ZL4Nb_h:
	.long	4
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1232348160
	.align 4
.LC2:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//
//  CasAES128_CUDA.c
//  CasAES128_CUDA
//  Created by Carter McCardwell on 11/11/14.
//

#include <stdint.h>
#include <stdio.h>
#include <time.h>
#include <string.h>

#include <hip/hip_runtime.h>

struct timing_pair{
	long time;
	long times[4];
	char cipher[16];
	char hits[10][4][4];
	//long memory_usage;
	//int ctx_delta;
	//unsigned long tp_delta;
	//unsigned short cp_delta;
};

const int Nb_h = 4;
const int Nr_h = 10;
const int Nk_h = 4;

const uint8_t s_h[256]=
{
		0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
		0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
		0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
		0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
		0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
		0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
		0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
		0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
		0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
		0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
		0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
		0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
		0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
		0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
		0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
		0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
};

uint8_t Rcon_h[256] = {
		0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a,
		0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39,
		0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a,
		0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
		0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef,
		0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc,
		0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b,
		0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3,
		0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94,
		0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20,
		0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35,
		0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f,
		0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04,
		0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63,
		0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd,
		0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d
};

__constant__ uint8_t s[256];
__constant__ int Nb;
__constant__ int Nr;
__constant__ int Nk;
__constant__ uint32_t ek[44];

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void cudaDevAssist(hipError_t code, int line, bool abort=true)
{
	if (code != hipSuccess)
	{
		fprintf(stderr,"cudaDevAssistant: %s %d\n", hipGetErrorString(code), line);
		if (abort) exit(code);
	}
}

uint32_t sw(uint32_t word)
{
	union {
		uint32_t word;
		uint8_t bytes[4];
	} subWord  __attribute__ ((aligned));
	subWord.word = word;

	subWord.bytes[3] = s_h[subWord.bytes[3]];
	subWord.bytes[2] = s_h[subWord.bytes[2]];
	subWord.bytes[1] = s_h[subWord.bytes[1]];
	subWord.bytes[0] = s_h[subWord.bytes[0]];

	return subWord.word;
}

__device__ void sb(uint8_t* in)
{
	for (int i = 0; i < 16; i++) { in[i] = s[in[i]]; }
}

__device__ void mc(uint8_t* arr)
{
	for (int i = 0; i < 4; i++)
	{
		uint8_t a[4];
		uint8_t b[4];
		uint8_t c;
		uint8_t h;
		for(c=0;c<4;c++) {
			a[c] = arr[(4*c+i)];
			h = (uint8_t)((signed char)arr[(4*c+i)] >> 7);
			b[c] = arr[(4*c+i)] << 1;
			b[c] ^= 0x1B & h;
		}
		arr[(i)] = b[0] ^ a[3] ^ a[2] ^ b[1] ^ a[1];
		arr[(4+i)] = b[1] ^ a[0] ^ a[3] ^ b[2] ^ a[2];
		arr[(8+i)] = b[2] ^ a[1] ^ a[0] ^ b[3] ^ a[3];
		arr[(12+i)] = b[3] ^ a[2] ^ a[1] ^ b[0] ^ a[0];
	}

}

__device__ void sr(uint8_t* arr)
{
	uint8_t out[16];
	//On per-row basis (+1 shift ea row)
	//Row 1
	out[0] = arr[0];
	out[1] = arr[1];
	out[2] = arr[2];
	out[3] = arr[3];
	//Row 2
	out[4] = arr[5];
	out[5] = arr[6];
	out[6] = arr[7];
	out[7] = arr[4];
	//Row 3
	out[8] = arr[10];
	out[9] = arr[11];
	out[10] = arr[8];
	out[11] = arr[9];
	//Row 4
	out[12] = arr[15];
	out[13] = arr[12];
	out[14] = arr[13];
	out[15] = arr[14];

	for (int i = 0; i < 16; i++)
	{
		arr[i] = out[i];
	}
}

uint32_t rw(uint32_t word)
{
	union {
		uint8_t bytes[4];
		uint32_t word;
	} subWord  __attribute__ ((aligned));
	subWord.word = word;

	uint8_t B0 = subWord.bytes[3], B1 = subWord.bytes[2], B2 = subWord.bytes[1], B3 = subWord.bytes[0];
	subWord.bytes[3] = B1; //0
	subWord.bytes[2] = B2; //1
	subWord.bytes[1] = B3; //2
	subWord.bytes[0] = B0; //3

	return subWord.word;
}

	void K_Exp(uint8_t* pk, uint32_t* out)
	{
		int i = 0;
		union {
			uint8_t bytes[4];
			uint32_t word;
		} temp __attribute__ ((aligned));
		union {
			uint8_t bytes[4];
			uint32_t word;
		} univar[44] __attribute__ ((aligned));

		for (i = 0; i < Nk_h; i++)
		{
			univar[i].bytes[3] = pk[i*4];
			univar[i].bytes[2] = pk[i*4+1];
			univar[i].bytes[1] = pk[i*4+2];
			univar[i].bytes[0] = pk[i*4+3];
		}

		for (i = Nk_h; i < Nb_h*(Nr_h+1); i++)
		{
			temp.word = univar[i-1].word;
			if (i % Nk_h == 0)
			{
				temp.word = (sw(rw(temp.word)));
				temp.bytes[3] = temp.bytes[3] ^ (Rcon_h[i/Nk_h]);
			}
			else if (Nk_h > 6 && i % Nk_h == 4)
			{
				temp.word = sw(temp.word);
			}
			if (i-4 % Nk_h == 0)
			{
				temp.word = sw(temp.word);
			}
			univar[i].word = univar[i-Nk_h].word ^ temp.word;
		}
		for (i = 0; i < 44; i++)
		{
			out[i] = univar[i].word;
		}
	}


__device__ void ark(uint8_t* state, int strD)
{
    union {
	    	uint32_t word;
	    	uint8_t bytes[4];
	  } zero __attribute__ ((aligned));
    union {
        uint32_t word;
        uint8_t bytes[4];
    } one __attribute__ ((aligned));
    union {
        uint32_t word;
        uint8_t bytes[4];
    } two __attribute__ ((aligned));
    union {
        uint32_t word;
        uint8_t bytes[4];
    } three __attribute__ ((aligned));

	  zero.word = ek[strD];
	  one.word = ek[strD+1];
	  two.word = ek[strD+2];
	  three.word = ek[strD+3];

    state[0] = state[0] ^ zero.bytes[3];
    state[4] = state[4] ^ zero.bytes[2];
    state[8] = state[8] ^ zero.bytes[1];
    state[12] = state[12] ^ zero.bytes[0];

    state[1] = state[1] ^ one.bytes[3];
    state[5] = state[5] ^ one.bytes[2];
    state[9] = state[9] ^ one.bytes[1];
    state[13] = state[13] ^ one.bytes[0];

    state[2] = state[2] ^ two.bytes[3];
    state[6] = state[6] ^ two.bytes[2];
    state[10] = state[10] ^ two.bytes[1];
    state[14] = state[14] ^ two.bytes[0];

    state[3] = state[3] ^ three.bytes[3];
    state[7] = state[7] ^ three.bytes[2];
    state[11] = state[11] ^ three.bytes[1];
    state[15] = state[15] ^ three.bytes[0];

}

__global__ void cudaRunner(uint8_t *in)
{
	uint8_t state[16];
  int localid = blockDim.x * blockIdx.x + threadIdx.x; //Data is shifted by 16 * ID of worker
  for (int i = 0; i < 16; i++) { state[i] = in[(localid*16)+i]; }

	ark(state, 0);
	for (int i = 1; i < Nr; i++)
	{
		sb(state);
		sr(state);
		mc(state);
		ark(state, i*Nb);
	}

	sb(state);
	sr(state);
	ark(state, Nr*Nb);

	for (int i = 0; i < 16; i++) { in[(localid*16)+i] = state[i]; }
}

long AES_CUDA(char* in_cypher, char* cypher, char* in_key)
{
	clock_t c_start, c_stop;
	c_start = clock();

	uint8_t key[16];
	uint32_t ek_h[44];
	uint8_t states[16] = { 0x00 };

	for (int i = 0; i < 16; i++)
	{
		states[i] = in_cypher[i];
		key[i] = in_key[i];
	}

	K_Exp(key, ek_h);

	//send constants to GPU
	hipSetDevice(0);
	cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nk), &Nk_h, sizeof(int), 0, hipMemcpyHostToDevice), 535, true);
	cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nr), &Nr_h, sizeof(int), 0, hipMemcpyHostToDevice), 543, true);
	cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(Nb), &Nb_h, sizeof(int), 0, hipMemcpyHostToDevice), 903, true);
	cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(s), &s_h, 256*sizeof(uint8_t), 0, hipMemcpyHostToDevice), 920, true);
	cudaDevAssist(hipMemcpyToSymbol(HIP_SYMBOL(ek), &ek_h, 44*sizeof(uint32_t), 0, hipMemcpyHostToDevice), 823, true);
	hipDeviceSynchronize();


	uint8_t *devState = NULL;
	cudaDevAssist(hipMalloc((void**)&devState, 16*sizeof(uint8_t)), 425, true);
		//arrange data correctly
			uint8_t temp[16];
			memcpy(&temp[0], &states[0], sizeof(uint8_t));
			memcpy(&temp[4], &states[1], sizeof(uint8_t));
			memcpy(&temp[8], &states[2], sizeof(uint8_t));
			memcpy(&temp[12], &states[3], sizeof(uint8_t));
			memcpy(&temp[1], &states[4], sizeof(uint8_t));
			memcpy(&temp[5], &states[5], sizeof(uint8_t));
			memcpy(&temp[9], &states[6], sizeof(uint8_t));
			memcpy(&temp[13], &states[7], sizeof(uint8_t));
			memcpy(&temp[2], &states[8], sizeof(uint8_t));
			memcpy(&temp[6], &states[9], sizeof(uint8_t));
			memcpy(&temp[10], &states[10], sizeof(uint8_t));
			memcpy(&temp[14], &states[11], sizeof(uint8_t));
			memcpy(&temp[3], &states[12], sizeof(uint8_t));
			memcpy(&temp[7], &states[13], sizeof(uint8_t));
			memcpy(&temp[11], &states[14], sizeof(uint8_t));
			memcpy(&temp[15], &states[15], sizeof(uint8_t));
			for (int c = 0; c < 16; c++) { memcpy(&states[c], &temp[c], sizeof(uint8_t)); }

		cudaDevAssist(hipMemcpy(devState, states, 16*sizeof(uint8_t), hipMemcpyHostToDevice), 426, true);
		cudaDevAssist(hipDeviceSynchronize(), 268, true);
		cudaRunner<<<1,1>>>(devState);

		cudaDevAssist(hipDeviceSynchronize(), 270, true);
		cudaDevAssist(hipMemcpy(states, devState, 16*sizeof(uint8_t), hipMemcpyDeviceToHost), 431, true);

			memcpy(&cypher[0], &states[0], sizeof(uint8_t));
			memcpy(&cypher[4], &states[1], sizeof(uint8_t));
			memcpy(&cypher[8], &states[2], sizeof(uint8_t));
			memcpy(&cypher[12], &states[3], sizeof(uint8_t));
			memcpy(&cypher[1], &states[4], sizeof(uint8_t));
			memcpy(&cypher[5], &states[5], sizeof(uint8_t));
			memcpy(&cypher[9], &states[6], sizeof(uint8_t));
			memcpy(&cypher[13], &states[7], sizeof(uint8_t));
			memcpy(&cypher[2], &states[8], sizeof(uint8_t));
			memcpy(&cypher[6], &states[9], sizeof(uint8_t));
			memcpy(&cypher[10], &states[10], sizeof(uint8_t));
			memcpy(&cypher[14], &states[11], sizeof(uint8_t));
			memcpy(&cypher[3], &states[12], sizeof(uint8_t));
			memcpy(&cypher[7], &states[13], sizeof(uint8_t));
			memcpy(&cypher[11], &states[14], sizeof(uint8_t));
			memcpy(&cypher[15], &states[15], sizeof(uint8_t));

  c_stop = clock();
  float diff = (((float)c_stop - (float)c_start) / CLOCKS_PER_SEC ) * 1000;
	hipFree(devState);
	hipDeviceReset();
	return diff;
}

	.text
	.file	"CasAES128_CUDA_NOUNAR_asFUNCT.hip"
	.globl	_Z2swj                          # -- Begin function _Z2swj
	.type	_Z2swj,@function
_Z2swj:                                 # @_Z2swj
	.cfi_startproc
# %bb.0:
                                        # kill: def $edi killed $edi def $rdi
	movl	%edi, %eax
	shrl	$8, %eax
	movl	%edi, %ecx
	shrl	$16, %ecx
	movl	%edi, %edx
	shrl	$24, %edx
	movl	$255, %esi
	andl	%esi, %ecx
	movzbl	_ZL3s_h(%rcx), %ecx
	andl	%esi, %eax
	movzbl	_ZL3s_h(%rax), %eax
	andl	%esi, %edi
	movzbl	_ZL3s_h(%rdi), %esi
	movzbl	_ZL3s_h(%rdx), %edx
	shll	$24, %edx
	shll	$16, %ecx
	orl	%edx, %ecx
	shll	$8, %eax
	orl	%ecx, %eax
	orl	%esi, %eax
	retq
.Lfunc_end0:
	.size	_Z2swj, .Lfunc_end0-_Z2swj
	.cfi_endproc
                                        # -- End function
	.globl	_Z2rwj                          # -- Begin function _Z2rwj
	.type	_Z2rwj,@function
_Z2rwj:                                 # @_Z2rwj
	.cfi_startproc
# %bb.0:
	movl	%edi, %eax
	roll	$8, %eax
	retq
.Lfunc_end1:
	.size	_Z2rwj, .Lfunc_end1-_Z2rwj
	.cfi_endproc
                                        # -- End function
	.globl	_Z5K_ExpPhPj                    # -- Begin function _Z5K_ExpPhPj
	.type	_Z5K_ExpPhPj,@function
_Z5K_ExpPhPj:                           # @_Z5K_ExpPhPj
	.cfi_startproc
# %bb.0:
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rsi, %rax
	xorl	%ecx, %ecx
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movb	(%rdi,%rcx,4), %dl
	movb	%dl, 3(%rsp,%rcx,4)
	movb	1(%rdi,%rcx,4), %dl
	movb	%dl, 2(%rsp,%rcx,4)
	movb	2(%rdi,%rcx,4), %dl
	movb	%dl, 1(%rsp,%rcx,4)
	movb	3(%rdi,%rcx,4), %dl
	movb	%dl, (%rsp,%rcx,4)
	incq	%rcx
	cmpq	$4, %rcx
	jne	.LBB2_1
# %bb.2:                                # %.preheader53.preheader
	movl	$4, %ecx
	movl	12(%rsp), %esi
	movl	$255, %edx
.LBB2_3:                                # %.preheader53
                                        # =>This Inner Loop Header: Depth=1
	testb	$3, %cl
	je	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_3 Depth=1
	movl	%esi, %edi
	shrl	$24, %edi
	jmp	.LBB2_6
.LBB2_5:                                #   in Loop: Header=BB2_3 Depth=1
	roll	$8, %esi
	movl	%esi, %edi
	shrl	$8, %edi
	movl	%esi, %r8d
	shrl	$16, %r8d
	movl	%esi, %r9d
	shrl	$24, %r9d
	andl	%edx, %r8d
	movzbl	_ZL3s_h(%r8), %r8d
	andl	%edx, %edi
	movzbl	_ZL3s_h(%rdi), %r10d
	andl	%edx, %esi
	movzbl	_ZL3s_h(%rsi), %esi
	shll	$16, %r8d
	orl	%esi, %r8d
	shll	$8, %r10d
	orl	%r8d, %r10d
	movl	%ecx, %esi
	shrl	$2, %esi
	movb	Rcon_h(%rsi), %dil
	xorb	_ZL3s_h(%r9), %dil
	movl	%r10d, %esi
.LBB2_6:                                #   in Loop: Header=BB2_3 Depth=1
	movzbl	%dil, %edi
	shll	$24, %edi
	andl	$16777215, %esi                 # imm = 0xFFFFFF
	orl	%edi, %esi
	xorl	-16(%rsp,%rcx,4), %esi
	movl	%esi, (%rsp,%rcx,4)
	incq	%rcx
	cmpq	$44, %rcx
	jne	.LBB2_3
# %bb.7:                                # %.preheader.preheader
	movq	%rsp, %rsi
	movl	$176, %edx
	movq	%rax, %rdi
	callq	memcpy@PLT
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z5K_ExpPhPj, .Lfunc_end2-_Z5K_ExpPhPj
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__cudaRunnerPh # -- Begin function _Z25__device_stub__cudaRunnerPh
	.type	_Z25__device_stub__cudaRunnerPh,@function
_Z25__device_stub__cudaRunnerPh:        # @_Z25__device_stub__cudaRunnerPh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10cudaRunnerPh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z25__device_stub__cudaRunnerPh, .Lfunc_end3-_Z25__device_stub__cudaRunnerPh
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z8AES_CUDAPcS_S_
.LCPI4_0:
	.long	0x49742400                      # float 1.0E+6
.LCPI4_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	_Z8AES_CUDAPcS_S_
	.type	_Z8AES_CUDAPcS_S_,@function
_Z8AES_CUDAPcS_S_:                      # @_Z8AES_CUDAPcS_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$232, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %r15
	movq	%rsi, %r14
	movq	%rdi, %r12
	callq	clock
	movq	%rax, %rbx
	movups	(%r12), %xmm0
	movaps	%xmm0, (%rsp)
	movups	(%r15), %xmm0
	leaq	32(%rsp), %rdi
	movaps	%xmm0, (%rdi)
	leaq	48(%rsp), %rsi
	callq	_Z5K_ExpPhPj
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	$Nk, %edi
	movl	$_ZL4Nk_h, %esi
	movl	$4, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB4_1
# %bb.3:                                # %_Z13cudaDevAssist10hipError_tib.exit
	movl	$Nr, %edi
	movl	$_ZL4Nr_h, %esi
	movl	$4, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.5:                                # %_Z13cudaDevAssist10hipError_tib.exit34
	movl	$Nb, %edi
	movl	$_ZL4Nb_h, %esi
	movl	$4, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.7:                                # %_Z13cudaDevAssist10hipError_tib.exit36
	movl	$s, %edi
	movl	$_ZL3s_h, %esi
	movl	$256, %edx                      # imm = 0x100
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.9:                                # %_Z13cudaDevAssist10hipError_tib.exit38
	leaq	48(%rsp), %rsi
	movl	$ek, %edi
	movl	$176, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.11:                               # %_Z13cudaDevAssist10hipError_tib.exit40
	callq	hipDeviceSynchronize
	leaq	16(%rsp), %rdi
	movq	$0, (%rdi)
	movl	$16, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_12
# %bb.13:                               # %_Z13cudaDevAssist10hipError_tib.exit42
	movq	%rsp, %rsi
	movb	1(%rsi), %al
	movb	2(%rsi), %cl
	movb	3(%rsi), %dl
	movb	4(%rsi), %dil
	movb	6(%rsi), %r8b
	movb	7(%rsi), %r9b
	movb	8(%rsi), %r10b
	movb	9(%rsi), %r11b
	movb	11(%rsi), %bpl
	movb	12(%rsi), %r15b
	movb	13(%rsi), %r12b
	movb	14(%rsi), %r13b
	movb	%dil, 1(%rsi)
	movb	%r10b, 2(%rsi)
	movb	%r15b, 3(%rsi)
	movb	%al, 4(%rsi)
	movb	%r11b, 6(%rsi)
	movb	%r12b, 7(%rsi)
	movb	%cl, 8(%rsi)
	movb	%r8b, 9(%rsi)
	movb	%r13b, 11(%rsi)
	movb	%dl, 12(%rsi)
	movb	%r9b, 13(%rsi)
	movb	%bpl, 14(%rsi)
	movq	16(%rsp), %rdi
	movl	$16, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.15:                               # %_Z13cudaDevAssist10hipError_tib.exit44
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB4_16
# %bb.17:                               # %_Z13cudaDevAssist10hipError_tib.exit46
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_19
# %bb.18:
	movq	16(%rsp), %rdi
	callq	_Z25__device_stub__cudaRunnerPh
.LBB4_19:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB4_20
# %bb.21:                               # %_Z13cudaDevAssist10hipError_tib.exit48
	movq	16(%rsp), %rsi
	movq	%rsp, %rdi
	movl	$16, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_22
# %bb.23:                               # %_Z13cudaDevAssist10hipError_tib.exit50
	movb	(%rsp), %al
	movb	%al, (%r14)
	movb	1(%rsp), %al
	movb	%al, 4(%r14)
	movb	2(%rsp), %al
	movb	%al, 8(%r14)
	movb	3(%rsp), %al
	movb	%al, 12(%r14)
	movb	4(%rsp), %al
	movb	%al, 1(%r14)
	movb	5(%rsp), %al
	movb	%al, 5(%r14)
	movb	6(%rsp), %al
	movb	%al, 9(%r14)
	movb	7(%rsp), %al
	movb	%al, 13(%r14)
	movb	8(%rsp), %al
	movb	%al, 2(%r14)
	movb	9(%rsp), %al
	movb	%al, 6(%r14)
	movb	10(%rsp), %al
	movb	%al, 10(%r14)
	movb	11(%rsp), %al
	movb	%al, 14(%r14)
	movb	12(%rsp), %al
	movb	%al, 3(%r14)
	movb	13(%rsp), %al
	movb	%al, 7(%r14)
	movb	14(%rsp), %al
	movb	%al, 11(%r14)
	movb	15(%rsp), %al
	movb	%al, 15(%r14)
	callq	clock
	cvtsi2ss	%rax, %xmm1
	cvtsi2ss	%rbx, %xmm0
	subss	%xmm0, %xmm1
	divss	.LCPI4_0(%rip), %xmm1
	mulss	.LCPI4_1(%rip), %xmm1
	movss	%xmm1, 28(%rsp)                 # 4-byte Spill
	movq	16(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	cvttss2si	28(%rsp), %rax          # 4-byte Folded Reload
	addq	$232, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_1:
	.cfi_def_cfa_offset 288
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$535, %ecx                      # imm = 0x217
	jmp	.LBB4_2
.LBB4_4:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$543, %ecx                      # imm = 0x21F
	jmp	.LBB4_2
.LBB4_6:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$903, %ecx                      # imm = 0x387
	jmp	.LBB4_2
.LBB4_8:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$920, %ecx                      # imm = 0x398
	jmp	.LBB4_2
.LBB4_10:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$823, %ecx                      # imm = 0x337
	jmp	.LBB4_2
.LBB4_12:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$425, %ecx                      # imm = 0x1A9
	jmp	.LBB4_2
.LBB4_14:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$426, %ecx                      # imm = 0x1AA
	jmp	.LBB4_2
.LBB4_16:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$268, %ecx                      # imm = 0x10C
	jmp	.LBB4_2
.LBB4_20:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$270, %ecx                      # imm = 0x10E
	jmp	.LBB4_2
.LBB4_22:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$431, %ecx                      # imm = 0x1AF
.LBB4_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.Lfunc_end4:
	.size	_Z8AES_CUDAPcS_S_, .Lfunc_end4-_Z8AES_CUDAPcS_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10cudaRunnerPh, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$s, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$Nb, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$Nr, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$Nk, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ek, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$176, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	Rcon_h,@object                  # @Rcon_h
	.data
	.globl	Rcon_h
	.p2align	4, 0x0
Rcon_h:
	.ascii	"\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215\001\002\004\b\020 @\200\0336l\330\253M\232/^\274c\306\2275j\324\263}\372\357\305\2219r\344\323\275a\302\237%J\2243f\314\203\035:t\350\313\215"
	.size	Rcon_h, 256

	.type	s,@object                       # @s
	.local	s
	.comm	s,256,16
	.type	Nb,@object                      # @Nb
	.local	Nb
	.comm	Nb,4,4
	.type	Nr,@object                      # @Nr
	.local	Nr
	.comm	Nr,4,4
	.type	Nk,@object                      # @Nk
	.local	Nk
	.comm	Nk,4,4
	.type	ek,@object                      # @ek
	.local	ek
	.comm	ek,176,16
	.type	_ZL3s_h,@object                 # @_ZL3s_h
	.section	.rodata,"a",@progbits
	.p2align	4, 0x0
_ZL3s_h:
	.ascii	"c|w{\362ko\3050\001g+\376\327\253v\312\202\311}\372YG\360\255\324\242\257\234\244r\300\267\375\223&6?\367\3144\245\345\361q\3301\025\004\307#\303\030\226\005\232\007\022\200\342\353'\262u\t\203,\032\033nZ\240R;\326\263)\343/\204S\321\000\355 \374\261[j\313\2769JLX\317\320\357\252\373CM3\205E\371\002\177P<\237\250Q\243@\217\222\2358\365\274\266\332!\020\377\363\322\315\f\023\354_\227D\027\304\247~=d]\031s`\201O\334\"*\220\210F\356\270\024\336^\013\333\3402:\nI\006$\\\302\323\254b\221\225\344y\347\3107m\215\325N\251lV\364\352ez\256\b\272x%.\034\246\264\306\350\335t\037K\275\213\212p>\265fH\003\366\016a5W\271\206\301\035\236\341\370\230\021i\331\216\224\233\036\207\351\316U(\337\214\241\211\r\277\346BhA\231-\017\260T\273\026"
	.size	_ZL3s_h, 256

	.type	_Z10cudaRunnerPh,@object        # @_Z10cudaRunnerPh
	.globl	_Z10cudaRunnerPh
	.p2align	3, 0x0
_Z10cudaRunnerPh:
	.quad	_Z25__device_stub__cudaRunnerPh
	.size	_Z10cudaRunnerPh, 8

	.type	_ZL4Nk_h,@object                # @_ZL4Nk_h
	.p2align	2, 0x0
_ZL4Nk_h:
	.long	4                               # 0x4
	.size	_ZL4Nk_h, 4

	.type	_ZL4Nr_h,@object                # @_ZL4Nr_h
	.p2align	2, 0x0
_ZL4Nr_h:
	.long	10                              # 0xa
	.size	_ZL4Nr_h, 4

	.type	_ZL4Nb_h,@object                # @_ZL4Nb_h
	.p2align	2, 0x0
_ZL4Nb_h:
	.long	4                               # 0x4
	.size	_ZL4Nb_h, 4

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"cudaDevAssistant: %s %d\n"
	.size	.L.str, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10cudaRunnerPh"
	.size	.L__unnamed_1, 17

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"s"
	.size	.L__unnamed_2, 2

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"Nb"
	.size	.L__unnamed_3, 3

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"Nr"
	.size	.L__unnamed_4, 3

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"Nk"
	.size	.L__unnamed_5, 3

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"ek"
	.size	.L__unnamed_6, 3

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__cudaRunnerPh
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym s
	.addrsig_sym Nb
	.addrsig_sym Nr
	.addrsig_sym Nk
	.addrsig_sym ek
	.addrsig_sym _ZL3s_h
	.addrsig_sym _Z10cudaRunnerPh
	.addrsig_sym _ZL4Nk_h
	.addrsig_sym _ZL4Nr_h
	.addrsig_sym _ZL4Nb_h
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10cudaRunnerPh        ; -- Begin function _Z10cudaRunnerPh
	.globl	_Z10cudaRunnerPh
	.p2align	8
	.type	_Z10cudaRunnerPh,@function
_Z10cudaRunnerPh:                       ; @_Z10cudaRunnerPh
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x14
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b64 s[16:17], 0
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr17
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s2
	v_add_lshl_u32 v0, s15, v0, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v0, s16
	v_add_co_ci_u32_e32 v19, vcc_lo, s17, v1, vcc_lo
	s_cmp_eq_u32 s16, 13
	v_and_b32_e32 v6, 0xff, v6
	s_cselect_b32 vcc_lo, -1, 0
	global_load_u8 v18, v[18:19], off
	s_cmp_eq_u32 s16, 5
	v_lshlrev_b16 v9, 8, v9
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s16, 11
	v_and_b32_e32 v12, 0xff, v12
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s16, 3
	v_lshlrev_b16 v15, 8, v15
	v_lshlrev_b16 v10, 8, v10
	v_and_b32_e32 v7, 0xff, v7
	v_and_b32_e32 v2, 0xff, v2
	v_lshlrev_b16 v3, 8, v3
	v_and_b32_e32 v4, 0xff, v4
	v_lshlrev_b16 v17, 8, v17
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s16, 12
	v_and_b32_e32 v11, 0xff, v11
	v_lshlrev_b16 v14, 8, v14
	v_and_b32_e32 v13, 0xff, v13
	v_lshlrev_b16 v16, 8, v16
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s16, 8
	v_lshlrev_b16 v8, 8, v8
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s16, 4
	v_and_b32_e32 v5, 0xff, v5
	v_or_b32_e32 v6, v6, v9
	v_or_b32_e32 v12, v12, v15
	v_and_b32_e32 v9, 0xffff, v10
	v_or_b32_e32 v7, v7, v10
	v_or_b32_e32 v10, v2, v3
	v_or_b32_e32 v15, v4, v17
	v_or_b32_e32 v11, v11, v14
	v_or_b32_e32 v13, v13, v16
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s16, 0
	v_and_b32_e32 v14, 0xffff, v8
	s_cselect_b32 s6, -1, 0
	s_cmp_eq_u32 s16, 14
	v_or_b32_e32 v8, v5, v8
	v_and_b32_e32 v3, 0xffff, v6
	v_lshlrev_b32_e32 v16, 16, v12
	v_and_b32_e32 v5, 0xffff, v10
	v_lshlrev_b32_e32 v17, 16, v15
	s_cselect_b32 s7, -1, 0
	s_cmp_eq_u32 s16, 10
	v_lshlrev_b32_e32 v2, 16, v11
	v_lshlrev_b32_e32 v4, 16, v13
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s16, 6
	v_or_b32_e32 v3, v3, v16
	s_cselect_b32 s9, -1, 0
	s_cmp_eq_u32 s16, 2
	v_or_b32_e32 v5, v5, v17
	v_or_b32_e32 v14, v14, v2
	v_or_b32_e32 v9, v9, v4
	s_cselect_b32 s10, -1, 0
	s_cmp_eq_u32 s16, 15
	v_lshrrev_b32_e32 v19, 24, v16
	s_cselect_b32 s11, -1, 0
	s_cmp_eq_u32 s16, 7
	v_lshrrev_b32_e32 v16, 8, v3
	v_lshrrev_b32_e32 v20, 8, v5
	v_lshrrev_b64 v[4:5], 24, v[4:5]
	v_lshrrev_b64 v[2:3], 24, v[2:3]
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s16, 9
	v_lshrrev_b32_e32 v17, 24, v17
	v_lshrrev_b32_e32 v21, 8, v9
	v_lshrrev_b32_e32 v22, 8, v14
	s_cselect_b32 s13, -1, 0
	s_cmp_eq_u32 s16, 1
	s_cselect_b32 s14, -1, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_eq_u32 s16, 16
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v3, v20, v18, vcc_lo
	v_cndmask_b32_e64 v9, v16, v18, s0
	v_cndmask_b32_e64 v16, v4, v18, s1
	v_cndmask_b32_e64 v14, v2, v18, s2
	v_cndmask_b32_e64 v2, v10, v18, s3
	v_cndmask_b32_e64 v7, v7, v18, s4
	v_cndmask_b32_e64 v6, v6, v18, s5
	v_cndmask_b32_e64 v5, v8, v18, s6
	v_cndmask_b32_e64 v4, v15, v18, s7
	v_cndmask_b32_e64 v13, v13, v18, s8
	v_cndmask_b32_e64 v12, v12, v18, s9
	v_cndmask_b32_e64 v11, v11, v18, s10
	v_cndmask_b32_e64 v17, v17, v18, s11
	v_cndmask_b32_e64 v15, v19, v18, s12
	v_cndmask_b32_e64 v10, v21, v18, s13
	v_cndmask_b32_e64 v8, v22, v18, s14
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ek@rel32@lo+4
	s_addc_u32 s1, s1, ek@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, Nr@rel32@lo+4
	s_addc_u32 s5, s5, Nr@rel32@hi+12
	s_load_b128 s[0:3], s[0:1], 0x0
	s_load_b32 s15, s[4:5], 0x0
	s_mov_b32 s18, 1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s0, 8
	s_lshr_b32 s5, s0, 16
	s_lshr_b32 s6, s0, 24
	s_lshr_b32 s7, s1, 8
	s_lshr_b32 s8, s1, 16
	s_lshr_b32 s9, s1, 24
	s_lshr_b32 s10, s2, 8
	s_lshr_b32 s11, s2, 16
	s_lshr_b32 s12, s2, 24
	s_lshr_b32 s13, s3, 8
	s_lshr_b32 s14, s3, 16
	s_lshr_b32 s16, s3, 24
	v_xor_b32_e32 v2, s0, v2
	v_xor_b32_e32 v3, s1, v3
	v_xor_b32_e32 v4, s2, v4
	v_xor_b32_e32 v5, s6, v5
	v_xor_b32_e32 v6, s5, v6
	v_xor_b32_e32 v7, s4, v7
	v_xor_b32_e32 v8, s9, v8
	v_xor_b32_e32 v9, s8, v9
	v_xor_b32_e32 v10, s7, v10
	v_xor_b32_e32 v11, s12, v11
	v_xor_b32_e32 v12, s11, v12
	v_xor_b32_e32 v13, s10, v13
	v_xor_b32_e32 v14, s16, v14
	v_xor_b32_e32 v15, s14, v15
	v_xor_b32_e32 v16, s13, v16
	v_xor_b32_e32 v17, s3, v17
	s_cmp_gt_i32 s15, 1
	s_cbranch_scc0 .LBB0_13
; %bb.3:                                ; %.preheader63.lr.ph
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Nb@rel32@lo+4
	s_addc_u32 s1, s1, Nb@rel32@hi+12
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, s@rel32@lo+4
	s_addc_u32 s21, s21, s@rel32@hi+12
	s_load_b32 s19, s[0:1], 0x0
.LBB0_4:                                ; %.preheader63
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_7 Depth 2
                                        ;     Child Loop BB0_9 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
	s_mov_b64 s[16:17], 0
.LBB0_5:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s16, 2
	v_cndmask_b32_e32 v18, v5, v8, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s16, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v11, s0
	s_cmp_eq_u32 s16, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s16, 5
	v_cndmask_b32_e64 v18, v18, v14, s1
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s16, 6
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v6, s2
	s_cmp_eq_u32 s16, 7
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s16, 8
	v_cndmask_b32_e64 v18, v18, v9, s3
	s_cselect_b32 s6, -1, 0
	s_cmp_eq_u32 s16, 9
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v12, s4
	s_cmp_eq_u32 s16, 10
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s16, 11
	v_cndmask_b32_e64 v18, v18, v15, s5
	s_cselect_b32 s9, -1, 0
	s_cmp_eq_u32 s16, 12
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v7, s6
	s_cmp_eq_u32 s16, 13
	s_cselect_b32 s11, -1, 0
	s_cmp_eq_u32 s16, 14
	v_cndmask_b32_e64 v18, v18, v10, s7
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s16, 15
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v13, s8
	s_cmp_eq_u32 s16, 0
	v_cndmask_b32_e64 v18, v18, v16, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v2, s10
	v_cndmask_b32_e64 v18, v18, v3, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v4, s12
	v_cndmask_b32_e64 v18, v18, v17, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v18, 0xff, v18
	v_add_co_u32 v18, s14, v18, s20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, null, 0, s21, s14
	s_cselect_b32 s14, -1, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	global_load_u8 v18, v[18:19], off
	s_cmp_lg_u32 s16, 16
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v17, v17, v18, s13
	v_cndmask_b32_e64 v4, v4, v18, s12
	v_cndmask_b32_e64 v3, v3, v18, s11
	v_cndmask_b32_e64 v2, v2, v18, s10
	v_cndmask_b32_e64 v16, v16, v18, s9
	v_cndmask_b32_e64 v13, v13, v18, s8
	v_cndmask_b32_e64 v10, v10, v18, s7
	v_cndmask_b32_e64 v7, v7, v18, s6
	v_cndmask_b32_e64 v15, v15, v18, s5
	v_cndmask_b32_e64 v12, v12, v18, s4
	v_cndmask_b32_e64 v9, v9, v18, s3
	v_cndmask_b32_e64 v6, v6, v18, s2
	v_cndmask_b32_e64 v14, v14, v18, s1
	v_cndmask_b32_e64 v11, v11, v18, s0
	v_cndmask_b32_e32 v8, v8, v18, vcc_lo
	v_cndmask_b32_e64 v5, v5, v18, s14
	s_cbranch_scc1 .LBB0_5
; %bb.6:                                ; %_Z2sbPh.exit32
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v25, v5 :: v_dual_mov_b32 v24, v8
	v_dual_mov_b32 v23, v11 :: v_dual_mov_b32 v22, v14
	v_dual_mov_b32 v21, v6 :: v_dual_mov_b32 v20, v9
	v_dual_mov_b32 v19, v12 :: v_dual_mov_b32 v18, v15
	v_dual_mov_b32 v26, v7 :: v_dual_mov_b32 v27, v10
	v_dual_mov_b32 v28, v13 :: v_dual_mov_b32 v29, v16
	v_dual_mov_b32 v30, v2 :: v_dual_mov_b32 v33, v4
	v_dual_mov_b32 v32, v3 :: v_dual_mov_b32 v31, v17
	s_mov_b64 s[16:17], 0
.LBB0_7:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s16, 2
	v_cndmask_b32_e32 v34, v5, v8, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s16, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v11, s0
	s_cmp_eq_u32 s16, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s16, 5
	v_cndmask_b32_e64 v34, v34, v14, s1
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s16, 6
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v9, s2
	s_cmp_eq_u32 s16, 7
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s16, 8
	v_cndmask_b32_e64 v34, v34, v12, s3
	s_cselect_b32 s6, -1, 0
	s_cmp_eq_u32 s16, 9
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v15, s4
	s_cmp_eq_u32 s16, 10
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s16, 11
	v_cndmask_b32_e64 v34, v34, v6, s5
	s_cselect_b32 s9, -1, 0
	s_cmp_eq_u32 s16, 12
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v13, s6
	s_cmp_eq_u32 s16, 13
	s_cselect_b32 s11, -1, 0
	s_cmp_eq_u32 s16, 14
	v_cndmask_b32_e64 v34, v34, v16, s7
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s16, 15
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v7, s8
	s_cmp_eq_u32 s16, 0
	s_cselect_b32 s14, -1, 0
	s_add_u32 s16, s16, 1
	v_cndmask_b32_e64 v34, v34, v10, s9
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s16, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v17, s10
	v_cndmask_b32_e64 v34, v34, v2, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v3, s12
	v_cndmask_b32_e64 v34, v34, v4, s13
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v31, v31, v34, s13
	v_cndmask_b32_e64 v33, v33, v34, s12
	v_cndmask_b32_e64 v32, v32, v34, s11
	v_cndmask_b32_e64 v30, v30, v34, s10
	v_cndmask_b32_e64 v29, v29, v34, s9
	v_cndmask_b32_e64 v28, v28, v34, s8
	v_cndmask_b32_e64 v27, v27, v34, s7
	v_cndmask_b32_e64 v26, v26, v34, s6
	v_cndmask_b32_e64 v18, v18, v34, s5
	v_cndmask_b32_e64 v19, v19, v34, s4
	v_cndmask_b32_e64 v20, v20, v34, s3
	v_cndmask_b32_e64 v21, v21, v34, s2
	v_cndmask_b32_e64 v22, v22, v34, s1
	v_cndmask_b32_e64 v23, v23, v34, s0
	v_cndmask_b32_e32 v24, v24, v34, vcc_lo
	v_cndmask_b32_e64 v25, v25, v34, s14
	s_cbranch_scc1 .LBB0_7
; %bb.8:                                ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
.LBB0_9:                                ; %.preheader.i
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[0:1], s[2:3]
	s_mov_b64 s[4:5], 0
.LBB0_10:                               ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_9 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_cmp_eq_u32 s0, 1
	v_lshlrev_b16 v9, 8, v9
	s_cselect_b32 vcc_lo, -1, 0
	v_dual_cndmask_b32 v10, v25, v24 :: v_dual_and_b32 v7, 0xff, v7
	v_and_b32_e32 v2, 0xff, v2
	v_lshlrev_b16 v5, 8, v5
	v_and_b32_e32 v4, 0xff, v4
	v_lshlrev_b16 v3, 8, v3
	s_cmp_eq_u32 s0, 2
	v_or_b32_e32 v7, v7, v9
	s_cselect_b32 vcc_lo, -1, 0
	v_or_b32_e32 v2, v2, v5
	v_or_b32_e32 v3, v4, v3
	v_cndmask_b32_e32 v4, v10, v23, vcc_lo
	s_cmp_eq_u32 s0, 3
	v_lshlrev_b16 v6, 8, v6
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v4, v22 :: v_dual_and_b32 v5, 0xffff, v7
	v_and_b32_e32 v2, 0xffff, v2
	v_lshlrev_b32_e32 v3, 16, v3
	s_cmp_eq_u32 s0, 4
	s_cselect_b32 vcc_lo, -1, 0
	v_and_b32_e32 v8, 0xff, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v2, v3
	v_cndmask_b32_e32 v3, v4, v21, vcc_lo
	s_cmp_eq_u32 s0, 5
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 6
	v_cndmask_b32_e32 v3, v3, v20, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 7
	v_or_b32_e32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v19, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 8
	v_cndmask_b32_e32 v3, v3, v18, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v26, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_lshlrev_b32_e32 v6, 16, v6
	s_cmp_eq_u32 s0, 10
	v_cndmask_b32_e32 v3, v3, v27, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 11
	v_or_b32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v28, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 12
	v_cndmask_b32_e32 v3, v3, v29, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v30, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 14
	v_cndmask_b32_e32 v3, v3, v32, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e32 v3, v3, v33, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_lshl_b32 s6, s4, 3
	s_lshl_b32 s6, 0xff, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v31, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	v_bfe_i32 v4, v3, 0, 8
	v_lshlrev_b16 v6, 8, v3
	v_and_b32_e32 v7, 0xff, v3
	v_lshlrev_b16 v3, 1, v3
	s_cmp_lg_u32 s4, 4
	v_lshrrev_b16 v4, 7, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v6, v7, v6
	v_and_b32_e32 v4, 27, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v7, 0xffff, v6
	v_lshlrev_b32_e32 v6, 16, v6
	v_xor_b32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v4, v7, v6
	v_lshlrev_b16 v6, 8, v3
	v_and_b32_e32 v3, 0xff, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v7, s6, v4, v5
	v_or_b32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v8, 16, v7
	v_lshrrev_b32_e32 v9, 8, v7
	v_and_b32_e32 v6, 0xffff, v3
	v_lshlrev_b32_e32 v3, 16, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v3, v6, v3
	v_lshrrev_b32_e32 v6, 24, v7
	v_bfi_b32 v2, s6, v3, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v3, 24, v2
	v_lshrrev_b32_e32 v4, 16, v2
	v_lshrrev_b32_e32 v5, 8, v2
	s_cbranch_scc1 .LBB0_10
; %bb.11:                               ;   in Loop: Header=BB0_9 Depth=2
	v_xor_b32_e32 v10, v6, v8
	s_cmp_eq_u32 s2, 15
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 14
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v11, v10, v9
	v_xor_b32_e32 v10, v10, v7
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 13
	s_cselect_b32 s1, -1, 0
	v_xor_b32_e32 v11, v11, v2
	v_xor_b32_e32 v10, v10, v5
	s_cmp_eq_u32 s2, 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v11, v11, v5
	v_xor_b32_e32 v10, v10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v31, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 11
	v_cndmask_b32_e64 v13, v33, v11, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 10
	v_cndmask_b32_e32 v15, v30, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 9
	v_cndmask_b32_e64 v16, v29, v11, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 8
	v_cndmask_b32_e32 v17, v28, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 0
	v_cndmask_b32_e64 v27, v27, v11, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 1
	v_cndmask_b32_e32 v26, v26, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_cndmask_b32_e64 v25, v25, v11, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 3
	v_cndmask_b32_e32 v24, v24, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e64 v23, v23, v11, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 5
	v_cndmask_b32_e32 v22, v22, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 6
	v_cndmask_b32_e64 v21, v21, v11, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 7
	v_cndmask_b32_e32 v20, v20, v11, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e64 v14, v32, v11, s1
	s_or_b32 s1, s2, 4
	v_cndmask_b32_e32 v18, v18, v11, vcc_lo
	s_cmp_eq_u32 s1, 7
	v_cndmask_b32_e64 v11, v19, v11, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 6
	v_cndmask_b32_e32 v18, v18, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 5
	v_cndmask_b32_e32 v11, v11, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 4
	v_cndmask_b32_e32 v19, v20, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 3
	v_cndmask_b32_e32 v20, v21, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 2
	v_cndmask_b32_e32 v21, v22, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 1
	v_cndmask_b32_e32 v22, v23, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 0
	v_cndmask_b32_e32 v23, v24, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 8
	v_cndmask_b32_e32 v24, v25, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 9
	v_cndmask_b32_e32 v25, v26, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 10
	v_cndmask_b32_e32 v26, v27, v10, vcc_lo
	v_xor_b32_e32 v27, v9, v7
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 11
	v_cndmask_b32_e32 v17, v17, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_xor_b32_e32 v28, v27, v6
	s_cmp_eq_u32 s1, 12
	v_cndmask_b32_e32 v16, v16, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 13
	v_xor_b32_e32 v28, v28, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v28, v28, v3
	v_cndmask_b32_e32 v15, v15, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 14
	v_cndmask_b32_e32 v14, v14, v10, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 15
	s_cselect_b32 s0, -1, 0
	s_or_b32 s1, s2, 8
	v_cndmask_b32_e64 v12, v12, v10, s0
	s_cmp_eq_u32 s1, 15
	v_cndmask_b32_e32 v10, v13, v10, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 14
	v_cndmask_b32_e64 v12, v12, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 13
	v_cndmask_b32_e32 v10, v10, v28, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 12
	v_cndmask_b32_e64 v13, v14, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 11
	v_cndmask_b32_e32 v14, v15, v28, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 10
	v_cndmask_b32_e64 v15, v16, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 9
	v_cndmask_b32_e32 v16, v17, v28, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 8
	v_cndmask_b32_e64 v17, v26, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 0
	v_cndmask_b32_e32 v26, v25, v28, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 1
	v_cndmask_b32_e64 v25, v24, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 2
	v_cndmask_b32_e32 v24, v23, v28, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 3
	v_cndmask_b32_e64 v23, v22, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 4
	v_cndmask_b32_e32 v22, v21, v28, vcc_lo
	v_xor_b32_e32 v21, v27, v8
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 5
	v_cndmask_b32_e64 v27, v20, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 6
	v_xor_b32_e32 v20, v21, v3
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s1, 7
	v_cndmask_b32_e32 v21, v19, v28, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_or_b32 s1, s2, 12
	v_cndmask_b32_e32 v18, v18, v28, vcc_lo
	v_xor_b32_e32 v31, v20, v2
	s_cmp_eq_u32 s1, 7
	v_cndmask_b32_e64 v11, v11, v28, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 6
	v_cndmask_b32_e32 v18, v18, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 5
	v_cndmask_b32_e32 v19, v11, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 4
	v_cndmask_b32_e32 v20, v21, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 3
	v_cndmask_b32_e32 v21, v27, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 2
	v_cndmask_b32_e32 v22, v22, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 1
	v_cndmask_b32_e32 v23, v23, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 0
	v_cndmask_b32_e32 v24, v24, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 8
	v_cndmask_b32_e32 v25, v25, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 9
	v_cndmask_b32_e32 v26, v26, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 10
	v_cndmask_b32_e32 v27, v17, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 11
	v_cndmask_b32_e32 v28, v16, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 12
	v_cndmask_b32_e32 v29, v15, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 13
	v_cndmask_b32_e32 v30, v14, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 14
	v_cndmask_b32_e32 v32, v13, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 15
	v_cndmask_b32_e32 v33, v10, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	v_cndmask_b32_e32 v31, v12, v31, vcc_lo
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 4
	s_cbranch_scc1 .LBB0_9
; %bb.12:                               ; %_Z2mcPh.exit
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s19, s18
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ek@rel32@lo+4
	s_addc_u32 s3, s3, ek@rel32@hi+12
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_add_i32 s18, s18, 1
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s0, 8
	s_lshr_b32 s5, s0, 16
	s_lshr_b32 s6, s0, 24
	s_lshr_b32 s7, s1, 8
	s_lshr_b32 s8, s1, 16
	s_lshr_b32 s9, s1, 24
	s_lshr_b32 s10, s2, 8
	s_lshr_b32 s11, s2, 16
	s_lshr_b32 s12, s2, 24
	s_lshr_b32 s13, s3, 8
	s_lshr_b32 s14, s3, 16
	s_lshr_b32 s16, s3, 24
	v_xor_b32_e32 v2, s0, v30
	v_xor_b32_e32 v3, s1, v32
	v_xor_b32_e32 v4, s2, v33
	v_xor_b32_e32 v5, s6, v25
	v_xor_b32_e32 v6, s5, v21
	v_xor_b32_e32 v7, s4, v26
	v_xor_b32_e32 v8, s9, v24
	v_xor_b32_e32 v9, s8, v20
	v_xor_b32_e32 v10, s7, v27
	v_xor_b32_e32 v11, s12, v23
	v_xor_b32_e32 v12, s11, v19
	v_xor_b32_e32 v13, s10, v28
	v_xor_b32_e32 v14, s16, v22
	v_xor_b32_e32 v15, s14, v18
	v_xor_b32_e32 v16, s13, v29
	v_xor_b32_e32 v17, s3, v31
	s_cmp_eq_u32 s18, s15
	s_cbranch_scc0 .LBB0_4
.LBB0_13:                               ; %Flow154
	s_mov_b64 s[16:17], 0
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, s@rel32@lo+4
	s_addc_u32 s19, s19, s@rel32@hi+12
.LBB0_14:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s16, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s16, 2
	v_cndmask_b32_e32 v18, v5, v8, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s16, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v11, s0
	s_cmp_eq_u32 s16, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s16, 5
	v_cndmask_b32_e64 v18, v18, v14, s1
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s16, 6
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v6, s2
	s_cmp_eq_u32 s16, 7
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s16, 8
	v_cndmask_b32_e64 v18, v18, v9, s3
	s_cselect_b32 s6, -1, 0
	s_cmp_eq_u32 s16, 9
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v12, s4
	s_cmp_eq_u32 s16, 10
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s16, 11
	v_cndmask_b32_e64 v18, v18, v15, s5
	s_cselect_b32 s9, -1, 0
	s_cmp_eq_u32 s16, 12
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v7, s6
	s_cmp_eq_u32 s16, 13
	s_cselect_b32 s11, -1, 0
	s_cmp_eq_u32 s16, 14
	v_cndmask_b32_e64 v18, v18, v10, s7
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s16, 15
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v13, s8
	s_cmp_eq_u32 s16, 0
	v_cndmask_b32_e64 v18, v18, v16, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v2, s10
	v_cndmask_b32_e64 v18, v18, v3, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, v18, v4, s12
	v_cndmask_b32_e64 v18, v18, v17, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v18, 0xff, v18
	v_add_co_u32 v18, s14, v18, s18
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, null, 0, s19, s14
	s_cselect_b32 s14, -1, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	global_load_u8 v18, v[18:19], off
	s_cmp_lg_u32 s16, 16
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v17, v17, v18, s13
	v_cndmask_b32_e64 v4, v4, v18, s12
	v_cndmask_b32_e64 v3, v3, v18, s11
	v_cndmask_b32_e64 v2, v2, v18, s10
	v_cndmask_b32_e64 v16, v16, v18, s9
	v_cndmask_b32_e64 v13, v13, v18, s8
	v_cndmask_b32_e64 v10, v10, v18, s7
	v_cndmask_b32_e64 v7, v7, v18, s6
	v_cndmask_b32_e64 v15, v15, v18, s5
	v_cndmask_b32_e64 v12, v12, v18, s4
	v_cndmask_b32_e64 v9, v9, v18, s3
	v_cndmask_b32_e64 v6, v6, v18, s2
	v_cndmask_b32_e64 v14, v14, v18, s1
	v_cndmask_b32_e64 v11, v11, v18, s0
	v_cndmask_b32_e32 v8, v8, v18, vcc_lo
	v_cndmask_b32_e64 v5, v5, v18, s14
	s_cbranch_scc1 .LBB0_14
; %bb.15:                               ; %_Z2sbPh.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v18, v14
	v_dual_mov_b32 v21, v8 :: v_dual_mov_b32 v20, v15
	v_dual_mov_b32 v19, v11 :: v_dual_mov_b32 v22, v12
	v_dual_mov_b32 v27, v6 :: v_dual_mov_b32 v30, v7
	v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v16
	v_dual_mov_b32 v29, v10 :: v_dual_mov_b32 v26, v13
	v_dual_mov_b32 v33, v2 :: v_dual_mov_b32 v32, v3
	v_dual_mov_b32 v31, v4 :: v_dual_mov_b32 v28, v17
	s_mov_b64 s[16:17], 0
.LBB0_16:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s16, 2
	v_cndmask_b32_e32 v34, v5, v8, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s16, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v11, s0
	s_cmp_eq_u32 s16, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s16, 5
	v_cndmask_b32_e64 v34, v34, v14, s1
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s16, 6
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v9, s2
	s_cmp_eq_u32 s16, 7
	s_cselect_b32 s5, -1, 0
	s_cmp_eq_u32 s16, 8
	v_cndmask_b32_e64 v34, v34, v12, s3
	s_cselect_b32 s6, -1, 0
	s_cmp_eq_u32 s16, 9
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v15, s4
	s_cmp_eq_u32 s16, 10
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s16, 11
	v_cndmask_b32_e64 v34, v34, v6, s5
	s_cselect_b32 s9, -1, 0
	s_cmp_eq_u32 s16, 12
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v13, s6
	s_cmp_eq_u32 s16, 13
	s_cselect_b32 s11, -1, 0
	s_cmp_eq_u32 s16, 14
	v_cndmask_b32_e64 v34, v34, v16, s7
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s16, 15
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v7, s8
	s_cmp_eq_u32 s16, 0
	s_cselect_b32 s14, -1, 0
	s_add_u32 s16, s16, 1
	v_cndmask_b32_e64 v34, v34, v10, s9
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s16, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v17, s10
	v_cndmask_b32_e64 v34, v34, v2, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v34, v34, v3, s12
	v_cndmask_b32_e64 v34, v34, v4, s13
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v34, s13
	v_cndmask_b32_e64 v31, v31, v34, s12
	v_cndmask_b32_e64 v32, v32, v34, s11
	v_cndmask_b32_e64 v33, v33, v34, s10
	v_cndmask_b32_e64 v24, v24, v34, s9
	v_cndmask_b32_e64 v26, v26, v34, s8
	v_cndmask_b32_e64 v29, v29, v34, s7
	v_cndmask_b32_e64 v30, v30, v34, s6
	v_cndmask_b32_e64 v20, v20, v34, s5
	v_cndmask_b32_e64 v22, v22, v34, s4
	v_cndmask_b32_e64 v25, v25, v34, s3
	v_cndmask_b32_e64 v27, v27, v34, s2
	v_cndmask_b32_e64 v18, v18, v34, s1
	v_cndmask_b32_e64 v19, v19, v34, s0
	v_cndmask_b32_e32 v21, v21, v34, vcc_lo
	v_cndmask_b32_e64 v23, v23, v34, s14
	s_cbranch_scc1 .LBB0_16
; %bb.17:                               ; %_Z2srPh.exit
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Nb@rel32@lo+4
	s_addc_u32 s1, s1, Nb@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ek@rel32@lo+4
	s_addc_u32 s3, s3, ek@rel32@hi+12
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s0, 8
	s_lshr_b32 s5, s0, 16
	s_lshr_b32 s6, s0, 24
	s_lshr_b32 s7, s1, 8
	s_lshr_b32 s8, s1, 16
	s_lshr_b32 s9, s1, 24
	s_lshr_b32 s10, s2, 8
	s_lshr_b32 s11, s2, 16
	s_lshr_b32 s12, s2, 24
	s_lshr_b32 s13, s3, 8
	s_lshr_b32 s14, s3, 16
	s_lshr_b32 s15, s3, 24
	v_xor_b32_e32 v2, s0, v33
	v_xor_b32_e32 v3, s1, v32
	v_xor_b32_e32 v4, s2, v31
	v_xor_b32_e32 v5, s6, v23
	v_xor_b32_e32 v6, s5, v27
	v_xor_b32_e32 v7, s4, v30
	v_xor_b32_e32 v8, s9, v21
	v_xor_b32_e32 v9, s8, v25
	v_xor_b32_e32 v10, s7, v29
	v_xor_b32_e32 v11, s12, v19
	v_xor_b32_e32 v12, s11, v22
	v_xor_b32_e32 v13, s10, v26
	v_xor_b32_e32 v14, s15, v18
	v_xor_b32_e32 v15, s14, v20
	v_xor_b32_e32 v16, s13, v24
	v_xor_b32_e32 v17, s3, v28
	s_mov_b64 s[2:3], 0
.LBB0_18:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 1
	v_add_co_u32 v18, vcc_lo, v0, s2
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 2
	v_cndmask_b32_e64 v19, v5, v8, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v11, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e64 v19, v19, v14, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v6, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 6
	v_cndmask_b32_e64 v19, v19, v9, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v12, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 8
	v_cndmask_b32_e64 v19, v19, v15, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v7, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 10
	v_cndmask_b32_e64 v19, v19, v10, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v13, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 12
	v_cndmask_b32_e64 v19, v19, v16, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v2, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 14
	v_cndmask_b32_e64 v19, v19, v3, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v20, v19, v4, s0
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	v_cndmask_b32_e32 v20, v20, v17, vcc_lo
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 16
	global_store_b8 v[18:19], v20, off
	s_cbranch_scc0 .LBB0_18
; %bb.19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10cudaRunnerPh
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10cudaRunnerPh, .Lfunc_end0-_Z10cudaRunnerPh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4984
; NumSgprs: 24
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	s                       ; @s
	.type	s,@object
	.section	.bss,"aw",@nobits
	.globl	s
	.p2align	4, 0x0
s:
	.zero	256
	.size	s, 256

	.protected	Nb                      ; @Nb
	.type	Nb,@object
	.globl	Nb
	.p2align	2, 0x0
Nb:
	.long	0                               ; 0x0
	.size	Nb, 4

	.protected	Nr                      ; @Nr
	.type	Nr,@object
	.globl	Nr
	.p2align	2, 0x0
Nr:
	.long	0                               ; 0x0
	.size	Nr, 4

	.protected	Nk                      ; @Nk
	.type	Nk,@object
	.globl	Nk
	.p2align	2, 0x0
Nk:
	.long	0                               ; 0x0
	.size	Nk, 4

	.protected	ek                      ; @ek
	.type	ek,@object
	.globl	ek
	.p2align	4, 0x0
ek:
	.zero	176
	.size	ek, 176

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym s
	.addrsig_sym Nb
	.addrsig_sym Nr
	.addrsig_sym Nk
	.addrsig_sym ek
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10cudaRunnerPh
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z10cudaRunnerPh.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     35
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
