/*
 * MSU CUDA Course Examples and Exercises.
 *
 * Copyright (c) 2011 Dmitry Mikushin
 *
 * This software is provided 'as-is', without any express or implied warranty.
 * In no event will the authors be held liable for any damages arising 
 * from the use of this software.
 * Permission is granted to anyone to use this software for any purpose, 
 * including commercial applications, and to alter it and redistribute it freely,
 * without any restrictons.
 */

#include <cuda_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>

// Maximum allowed results difference.
#define EPS 1e-04

// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16

#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]

// GPU device kernel.
__global__ void pattern2d_gpu(
	int bx, int nx, int ex, int by, int ny, int ey,
	float* in, float* out)
{
	// Compute absolute (i,j) indexes for
	// the current GPU thread using grid mapping params.
	int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
	int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
	
	// Compute one data point - a piece of
	// work for the current GPU thread.
	OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
		2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}

// CPU control implementation.
void pattern2d_cpu(
	int bx, int nx, int ex, int by, int ny, int ey,
	float* in, float* out)
{
	for (int j = by; j < ny - ey; j++)
		for (int i = bx; i < nx - ex; i++)
			OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
				2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}

// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
	if ((nx <= 0) || (ny <= 0)) return -1;

	long np = nx * ny;

	size_t size = sizeof(float) * np;

	// Create GPU data array and copy input data to it.
	float* in_gpu;
	cudaError_t status = cudaMalloc((void**)&in_gpu, size);
	if (status != cudaSuccess)
	{
		fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
			"Cannot malloc input memory on GPU by process", pid, status);
		return status;
	}
	status = cudaMemcpy(in_gpu, in, size, cudaMemcpyHostToDevice);
	if (status != cudaSuccess)
	{
		fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
			pid, status);
		return status;
	}
	
	// Create CPU data output array and get
	// control result using CPU function.
	float* control = (float*)malloc(size);
	memset(control, 0, size);
	pattern2d_cpu(
		1, nx, 1, 1, ny, 1, in, control);
	
	// Configure GPU computational grid:
	// nx = nblocks_x * block_length
	// ny = nblocks_y * block_height
	//
	// NOTE: we have degree of freedom in
	// selecting how real problem grid maps onto
	// computational grid. Usually these params
	// are tuned to get optimal performance.
	//
	// NOTE: chose of grid/block config is
	// also limited by device properties:
	// - Maximum number of threads per block (512)
	// - Maximum sizes of each dimension of a block (512 x 512 x 64)
	// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
	int nblocks_x = (nx - 2) / BLOCK_LENGTH;
	int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
	
	// Perform the same processing on GPU,
	// returning result to GPU array.
	float* out_gpu;
	status = cudaMalloc((void**)&out_gpu, size);
	if (status != cudaSuccess)
	{
		fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
			"Cannot malloc output memory on GPU by process", pid, status);
		return status;
	}
	status = cudaMemset(out_gpu, 0, size);
	if (status != cudaSuccess)
	{
		fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
			pid, status);
		return status; 
	}
	pattern2d_gpu<<<
		dim3(nblocks_x, nblocks_y, 1),
		dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
			1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
	status = cudaGetLastError();
	if (status != cudaSuccess)
	{
		fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
			pid, status);
		return status;
	}
	status = cudaThreadSynchronize();
	if (status != cudaSuccess)
	{
		fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
			pid, status);
		return status;
	}
		
	// Copy GPU result from GPU memory to CPU buffer.
	status = cudaMemcpy(out, out_gpu, size, cudaMemcpyDeviceToHost);
	if (status != cudaSuccess)
	{
		fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
			pid, status);
		return status;
	}

	// Don't bother with processing the remainder
	// on GPU. Do it on CPU instead.
	pattern2d_cpu(
		1, nx, 1,
		ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
		in, out);
	pattern2d_cpu(
		nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
		1, ny, 1,
		in, out);
	
	// Compare results and find the maximum abs difference.
	int maxi = 0, maxj = 0;
	float maxdiff = fabs(out[0] - control[0]);
	float* diffs = (float*)malloc(size);
	memset(diffs, 0, size);
	for (int j = 0; j < ny; j++)
		for (int i = 0; i < nx; i++)
		{
			float diff = fabs(
				out[i + j * nx] -
				control[i + j * nx]);
			if (diff > maxdiff)
			{
				maxdiff = diff;
				maxi = i; maxj = j;
			}
			diffs[i + j * nx] = diff;
		}

	// Release data arrays.
	status = cudaFree(in_gpu);
	if (status != cudaSuccess)
	{
		fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
			pid, status);
		return status;
	}
	free(control);
	status = cudaFree(out_gpu);
	if (status != cudaSuccess)
	{
		fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
			pid, status);
		return status;
	}
	free(diffs);

	printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
		step, pid, maxdiff, maxi, maxj);
	
	return 0;
}


	.file	"tmpxft_002a2ec8_00000000-6_pattern2d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13pattern2d_cpuiiiiiiPfS_
	.type	_Z13pattern2d_cpuiiiiiiPfS_, @function
_Z13pattern2d_cpuiiiiiiPfS_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	leal	-1(%rbp), %r14d
	leal	1(%rbp), %r13d
	movl	%ebx, %ecx
	imull	%ebx, %r14d
	imull	%ebp, %ecx
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	imull	%ebx, %r13d
	movl	%edi, 4(%rsp)
	movq	112(%rsp), %rsi
	movl	%r8d, 32(%rsp)
.L3:
	movl	32(%rsp), %eax
	subl	%r9d, %eax
	cmpl	%ebp, %eax
	jle	.L2
	movslq	4(%rsp), %r12
	movslq	%ecx, %rdi
	movslq	%r14d, %r8
	movq	120(%rsp), %r15
	leaq	(%rsi,%r8,4), %r10
	movslq	%r13d, %r8
	leaq	(%r12,%rdi), %rax
	leaq	(%rsi,%r8,4), %r8
	leaq	(%rsi,%rax,4), %rax
	leaq	(%r15,%rdi,4), %r15
.L6:
	movl	%ebx, %r11d
	addq	$4, %rax
	subl	%edx, %r11d
	cmpl	%r12d, %r11d
	jle	.L9
	movss	(%r10,%r12,4), %xmm1
	movss	-4(%rax), %xmm0
	movq	%rsi, 112(%rsp)
	addss	-8(%rax), %xmm0
	addss	(%rax), %xmm0
	movl	%r9d, 44(%rsp)
	addss	%xmm1, %xmm1
	movl	%edx, 40(%rsp)
	movl	%ecx, 36(%rsp)
	movq	%rax, 24(%rsp)
	subss	%xmm1, %xmm0
	movss	.LC0(%rip), %xmm1
	mulss	(%r8,%r12,4), %xmm1
	movq	%r10, 16(%rsp)
	movq	%r8, 8(%rsp)
	addss	%xmm1, %xmm0
	andps	.LC1(%rip), %xmm0
	call	sqrtf@PLT
	movq	112(%rsp), %rsi
	movl	44(%rsp), %r9d
	movss	%xmm0, (%r15,%r12,4)
	movl	40(%rsp), %edx
	movl	36(%rsp), %ecx
	incq	%r12
	movq	24(%rsp), %rax
	movq	16(%rsp), %r10
	movq	8(%rsp), %r8
	jmp	.L6
.L9:
	incl	%ebp
	addl	%ebx, %ecx
	addl	%ebx, %r14d
	addl	%ebx, %r13d
	jmp	.L3
.L2:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z13pattern2d_cpuiiiiiiPfS_, .-_Z13pattern2d_cpuiiiiiiPfS_
	.globl	_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
	.type	_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_, @function
_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	216(%rsp), %rax
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 28(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z13pattern2d_gpuiiiiiiPfS_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L10:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_, .-_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
	.globl	_Z13pattern2d_gpuiiiiiiPfS_
	.type	_Z13pattern2d_gpuiiiiiiPfS_, @function
_Z13pattern2d_gpuiiiiiiPfS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
	.cfi_endproc
.LFE2054:
	.size	_Z13pattern2d_gpuiiiiiiPfS_, .-_Z13pattern2d_gpuiiiiiiPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"Cannot malloc input memory on GPU by process"
.LC3:
	.string	"%s %d, status = %d\nInsufficient GPU memory?\n"
.LC4:
	.string	"Cannot copy data from host to gpu by process %d, status = %d\n"
.LC5:
	.string	"Cannot malloc output memory on GPU by process"
.LC6:
	.string	"Cannot erase output memory on GPU by process %d, status = %d\n"
.LC7:
	.string	"Cannot execute CUDA kernel by process %d, status = %d\n"
.LC8:
	.string	"Cannot synchronize thread by process %d, status = %d\n"
.LC9:
	.string	"Cannot copy data from gpu to host by process %d, status = %d\n"
.LC10:
	.string	"Cannot free device input memory by process %d, status = %d\n"
.LC11:
	.string	"Cannot free device output memory by process %d, status = %d\n"
.LC12:
	.string	"Step %d result abs max diff by process %d = %f @ (%d,%d)\n"
	.text
	.globl	_Z9pattern2diiPfS_ii
	.type	_Z9pattern2diiPfS_ii, @function
_Z9pattern2diiPfS_ii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	%r8d, 20(%rsp)
	movl	%r9d, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	testl	%edi, %edi
	jle	.L32
	movl	%esi, %ebp
	testl	%esi, %esi
	jle	.L32
	movl	%edi, %eax
	movl	%edi, %ebx
	leaq	32(%rsp), %rdi
	movq	%rdx, %r13
	imull	%esi, %eax
	movq	%rcx, %r12
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L17
	movl	20(%rsp), %r8d
	movl	%eax, %ebx
	movl	%eax, %r9d
	leaq	.LC2(%rip), %rcx
	jmp	.L36
.L17:
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L18
	movl	20(%rsp), %ecx
	movl	%eax, %ebx
	movl	%eax, %r8d
	leaq	.LC4(%rip), %rdx
	jmp	.L37
.L18:
	movq	8(%rsp), %rdi
	call	malloc@PLT
	movq	8(%rsp), %rcx
	xorl	%esi, %esi
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	pushq	%r14
	.cfi_def_cfa_offset 152
	movl	%ebx, %esi
	movl	$1, %edi
	pushq	%r13
	.cfi_def_cfa_offset 160
	movl	$1, %r9d
	movl	%ebp, %r8d
	movl	$1, %ecx
	movl	$1, %edx
	call	_Z13pattern2d_cpuiiiiiiPfS_
	popq	%rsi
	.cfi_def_cfa_offset 152
	popq	%rdi
	.cfi_def_cfa_offset 144
	movq	8(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L19
	movl	20(%rsp), %r8d
	movl	%eax, %ebx
	movl	%eax, %r9d
	leaq	.LC5(%rip), %rcx
.L36:
	movq	stderr(%rip), %rdi
	leaq	.LC3(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L15
.L19:
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaMemset@PLT
	testl	%eax, %eax
	je	.L20
	movl	20(%rsp), %ecx
	movl	%eax, %ebx
	movl	%eax, %r8d
	leaq	.LC6(%rip), %rdx
	jmp	.L37
.L20:
	leal	-2(%rbp), %eax
	leal	-2(%rbx), %r15d
	movl	$32, %ecx
	xorl	%r9d, %r9d
	movl	%eax, 24(%rsp)
	movl	%r15d, %eax
	xorl	%r8d, %r8d
	movl	$1, %esi
	cltd
	idivl	%ecx
	movl	$16, %ecx
	movl	%eax, 48(%rsp)
	movl	24(%rsp), %eax
	cltd
	idivl	%ecx
	movl	$2147483649, %edx
	movl	$1, %ecx
	salq	$5, %rdx
	movl	%eax, 52(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	movl	$1, %ecx
	movl	$1, %edx
	movl	%ebx, %esi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movl	$1, %r9d
	movl	%ebp, %r8d
	movl	$1, %edi
	call	_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L21:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L22
	movl	20(%rsp), %ecx
	movl	%eax, %ebx
	movl	%eax, %r8d
	leaq	.LC7(%rip), %rdx
	jmp	.L37
.L22:
	call	cudaThreadSynchronize@PLT
	testl	%eax, %eax
	je	.L23
	movl	20(%rsp), %ecx
	movl	%eax, %ebx
	movl	%eax, %r8d
	leaq	.LC8(%rip), %rdx
	jmp	.L37
.L23:
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L24
	movl	20(%rsp), %ecx
	movl	%eax, %ebx
	movl	%eax, %r8d
	leaq	.LC9(%rip), %rdx
	jmp	.L37
.L24:
	movl	24(%rsp), %eax
	movl	$16, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 152
	movl	%ebp, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 160
	movl	$1, %r9d
	movl	%ebx, %esi
	movl	$1, %edi
	cltd
	idivl	%ecx
	movl	%ebp, %ecx
	subl	%edx, %ecx
	movl	$1, %edx
	subl	$2, %ecx
	call	_Z13pattern2d_cpuiiiiiiPfS_
	movl	%r15d, %eax
	movl	$32, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 168
	cltd
	pushq	%r13
	.cfi_def_cfa_offset 176
	movl	%ebx, %edi
	movl	$1, %r9d
	idivl	%ecx
	movl	%ebp, %r8d
	movl	$1, %ecx
	movl	%ebx, %esi
	xorl	%r15d, %r15d
	subl	%edx, %edi
	movl	$1, %edx
	subl	$2, %edi
	call	_Z13pattern2d_cpuiiiiiiPfS_
	movss	(%r12), %xmm0
	subss	(%r14), %xmm0
	movss	.LC1(%rip), %xmm1
	andps	%xmm1, %xmm0
	movss	%xmm0, 56(%rsp)
	movq	40(%rsp), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 144
	call	malloc@PLT
	movq	8(%rsp), %rcx
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, %r13
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	xorl	%eax, %eax
	movslq	%ebx, %rdi
	xorl	%esi, %esi
	movl	%eax, 8(%rsp)
	salq	$2, %rdi
	xorl	%ecx, %ecx
	movss	.LC1(%rip), %xmm1
.L25:
	movq	%rsi, %rax
	xorl	%edx, %edx
.L27:
	movss	(%r12,%rax), %xmm0
	subss	(%r14,%rax), %xmm0
	andps	%xmm1, %xmm0
	comiss	24(%rsp), %xmm0
	jbe	.L26
	movl	%edx, 8(%rsp)
	movl	%ecx, %r15d
	movss	%xmm0, 24(%rsp)
.L26:
	incl	%edx
	movss	%xmm0, 0(%r13,%rax)
	addq	$4, %rax
	cmpl	%edx, %ebx
	jg	.L27
	incl	%ecx
	addq	%rdi, %rsi
	cmpl	%ecx, %ebp
	jg	.L25
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L29
	movl	20(%rsp), %ecx
	movl	%eax, %r8d
	leaq	.LC10(%rip), %rdx
	jmp	.L37
.L29:
	movq	%r14, %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L30
	movl	20(%rsp), %ecx
	movl	%eax, %r8d
	leaq	.LC11(%rip), %rdx
.L37:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L15
.L30:
	movq	%r13, %rdi
	xorl	%ebx, %ebx
	call	free@PLT
	movl	8(%rsp), %r8d
	movl	20(%rsp), %ecx
	movb	$1, %al
	movl	28(%rsp), %edx
	movl	%r15d, %r9d
	movl	$2, %edi
	leaq	.LC12(%rip), %rsi
	cvtss2sd	24(%rsp), %xmm0
	call	__printf_chk@PLT
	jmp	.L15
.L32:
	orl	$-1, %ebx
.L15:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	movl	%ebx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z9pattern2diiPfS_ii, .-_Z9pattern2diiPfS_ii
	.section	.rodata.str1.1
.LC13:
	.string	"_Z13pattern2d_gpuiiiiiiPfS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z13pattern2d_gpuiiiiiiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1077936128
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * MSU CUDA Course Examples and Exercises.
 *
 * Copyright (c) 2011 Dmitry Mikushin
 *
 * This software is provided 'as-is', without any express or implied warranty.
 * In no event will the authors be held liable for any damages arising 
 * from the use of this software.
 * Permission is granted to anyone to use this software for any purpose, 
 * including commercial applications, and to alter it and redistribute it freely,
 * without any restrictons.
 */

#include <hip/hip_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>

// Maximum allowed results difference.
#define EPS 1e-04

// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16

#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]

// GPU device kernel.
__global__ void pattern2d_gpu(
	int bx, int nx, int ex, int by, int ny, int ey,
	float* in, float* out)
{
	// Compute absolute (i,j) indexes for
	// the current GPU thread using grid mapping params.
	int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
	int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
	
	// Compute one data point - a piece of
	// work for the current GPU thread.
	OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
		2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}

// CPU control implementation.
void pattern2d_cpu(
	int bx, int nx, int ex, int by, int ny, int ey,
	float* in, float* out)
{
	for (int j = by; j < ny - ey; j++)
		for (int i = bx; i < nx - ex; i++)
			OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
				2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}

// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
	if ((nx <= 0) || (ny <= 0)) return -1;

	long np = nx * ny;

	size_t size = sizeof(float) * np;

	// Create GPU data array and copy input data to it.
	float* in_gpu;
	hipError_t status = hipMalloc((void**)&in_gpu, size);
	if (status != hipSuccess)
	{
		fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
			"Cannot malloc input memory on GPU by process", pid, status);
		return status;
	}
	status = hipMemcpy(in_gpu, in, size, hipMemcpyHostToDevice);
	if (status != hipSuccess)
	{
		fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
			pid, status);
		return status;
	}
	
	// Create CPU data output array and get
	// control result using CPU function.
	float* control = (float*)malloc(size);
	memset(control, 0, size);
	pattern2d_cpu(
		1, nx, 1, 1, ny, 1, in, control);
	
	// Configure GPU computational grid:
	// nx = nblocks_x * block_length
	// ny = nblocks_y * block_height
	//
	// NOTE: we have degree of freedom in
	// selecting how real problem grid maps onto
	// computational grid. Usually these params
	// are tuned to get optimal performance.
	//
	// NOTE: chose of grid/block config is
	// also limited by device properties:
	// - Maximum number of threads per block (512)
	// - Maximum sizes of each dimension of a block (512 x 512 x 64)
	// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
	int nblocks_x = (nx - 2) / BLOCK_LENGTH;
	int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
	
	// Perform the same processing on GPU,
	// returning result to GPU array.
	float* out_gpu;
	status = hipMalloc((void**)&out_gpu, size);
	if (status != hipSuccess)
	{
		fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
			"Cannot malloc output memory on GPU by process", pid, status);
		return status;
	}
	status = hipMemset(out_gpu, 0, size);
	if (status != hipSuccess)
	{
		fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
			pid, status);
		return status; 
	}
	pattern2d_gpu<<<
		dim3(nblocks_x, nblocks_y, 1),
		dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
			1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
	status = hipGetLastError();
	if (status != hipSuccess)
	{
		fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
			pid, status);
		return status;
	}
	status = hipDeviceSynchronize();
	if (status != hipSuccess)
	{
		fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
			pid, status);
		return status;
	}
		
	// Copy GPU result from GPU memory to CPU buffer.
	status = hipMemcpy(out, out_gpu, size, hipMemcpyDeviceToHost);
	if (status != hipSuccess)
	{
		fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
			pid, status);
		return status;
	}

	// Don't bother with processing the remainder
	// on GPU. Do it on CPU instead.
	pattern2d_cpu(
		1, nx, 1,
		ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
		in, out);
	pattern2d_cpu(
		nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
		1, ny, 1,
		in, out);
	
	// Compare results and find the maximum abs difference.
	int maxi = 0, maxj = 0;
	float maxdiff = fabs(out[0] - control[0]);
	float* diffs = (float*)malloc(size);
	memset(diffs, 0, size);
	for (int j = 0; j < ny; j++)
		for (int i = 0; i < nx; i++)
		{
			float diff = fabs(
				out[i + j * nx] -
				control[i + j * nx]);
			if (diff > maxdiff)
			{
				maxdiff = diff;
				maxi = i; maxj = j;
			}
			diffs[i + j * nx] = diff;
		}

	// Release data arrays.
	status = hipFree(in_gpu);
	if (status != hipSuccess)
	{
		fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
			pid, status);
		return status;
	}
	free(control);
	status = hipFree(out_gpu);
	if (status != hipSuccess)
	{
		fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
			pid, status);
		return status;
	}
	free(diffs);

	printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
		step, pid, maxdiff, maxi, maxj);
	
	return 0;
}


	.text
	.file	"pattern2d.hip"
	.globl	_Z28__device_stub__pattern2d_gpuiiiiiiPfS_ # -- Begin function _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
	.type	_Z28__device_stub__pattern2d_gpuiiiiiiPfS_,@function
_Z28__device_stub__pattern2d_gpuiiiiiiPfS_: # @_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13pattern2d_gpuiiiiiiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__pattern2d_gpuiiiiiiPfS_, .Lfunc_end0-_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z13pattern2d_cpuiiiiiiPfS_
.LCPI1_0:
	.long	0x40400000                      # float 3
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI1_1:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	_Z13pattern2d_cpuiiiiiiPfS_
	.type	_Z13pattern2d_cpuiiiiiiPfS_,@function
_Z13pattern2d_cpuiiiiiiPfS_:            # @_Z13pattern2d_cpuiiiiiiPfS_
	.cfi_startproc
# %bb.0:
	subl	%r9d, %r8d
	cmpl	%ecx, %r8d
	jle	.LBB1_6
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	56(%rsp), %r9
	movl	$4294967295, %r10d              # imm = 0xFFFFFFFF
	movslq	%esi, %r11
	subl	%edx, %esi
	movslq	%edi, %rax
	movslq	%esi, %rbx
	movslq	%ecx, %r12
	movslq	%r8d, %rcx
	movq	%rax, -8(%rsp)                  # 8-byte Spill
	addq	%r10, %rax
	movq	%rax, -16(%rsp)                 # 8-byte Spill
	leaq	(,%r11,4), %rax
	movq	%rax, -24(%rsp)                 # 8-byte Spill
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	.LCPI1_1(%rip), %xmm1           # xmm1 = [NaN,NaN,NaN,NaN]
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_8 Depth 2
	cmpl	%edi, %esi
	jle	.LBB1_3
# %bb.7:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movq	%r12, %r14
	imulq	%r11, %r14
	leaq	-1(%r12), %rax
	imulq	%r11, %rax
	leaq	1(%r12), %r15
	movq	%r15, %rdx
	imulq	%r11, %rdx
	leaq	(%r9,%r14,4), %rbp
	leaq	(%r9,%rax,4), %rax
	leaq	(%r9,%rdx,4), %r8
	addl	-16(%rsp), %r14d                # 4-byte Folded Reload
	shlq	$32, %r14
	imulq	-24(%rsp), %r12                 # 8-byte Folded Reload
	addq	64(%rsp), %r12
	movq	-8(%rsp), %rdx                  # 8-byte Reload
.LBB1_8:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rbp,%rdx,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	movq	%r14, %r13
	sarq	$30, %r13
	addss	(%r9,%r13), %xmm2
	addss	4(%rbp,%rdx,4), %xmm2
	movss	(%rax,%rdx,4), %xmm3            # xmm3 = mem[0],zero,zero,zero
	addss	%xmm3, %xmm3
	subss	%xmm3, %xmm2
	movss	(%r8,%rdx,4), %xmm3             # xmm3 = mem[0],zero,zero,zero
	mulss	%xmm0, %xmm3
	addss	%xmm2, %xmm3
	andps	%xmm1, %xmm3
	xorps	%xmm2, %xmm2
	sqrtss	%xmm3, %xmm2
	movss	%xmm2, (%r12,%rdx,4)
	leaq	1(%rdx), %r13
	addq	%r10, %r14
	incq	%r14
	movq	%r13, %rdx
	cmpq	%rbx, %r13
	jl	.LBB1_8
# %bb.9:                                #   in Loop: Header=BB1_2 Depth=1
	movq	%r15, %r12
	jmp	.LBB1_4
.LBB1_3:                                # %.preheader.._crit_edge_crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r12
	movq	%r12, %r15
.LBB1_4:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	cmpq	%rcx, %r15
	jl	.LBB1_2
# %bb.5:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB1_6:                                # %._crit_edge36
	retq
.Lfunc_end1:
	.size	_Z13pattern2d_cpuiiiiiiPfS_, .Lfunc_end1-_Z13pattern2d_cpuiiiiiiPfS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z9pattern2diiPfS_ii
.LCPI2_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	_Z9pattern2diiPfS_ii
	.type	_Z9pattern2diiPfS_ii,@function
_Z9pattern2diiPfS_ii:                   # @_Z9pattern2diiPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $esi killed $esi def $rsi
	movl	$-1, %ebp
	testl	%edi, %edi
	jle	.LBB2_30
# %bb.1:
	testl	%esi, %esi
	jle	.LBB2_30
# %bb.2:
	movl	%r9d, %r13d
	movl	%r8d, %r12d
	movq	%rcx, %r14
	movl	%edi, %r15d
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movl	%esi, %eax
	imull	%edi, %eax
	movslq	%eax, %rbx
	shlq	$2, %rbx
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_3
# %bb.5:
	movq	24(%rsp), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.7:
	movl	%r13d, 36(%rsp)                 # 4-byte Spill
	movl	%r12d, 4(%rsp)                  # 4-byte Spill
	movl	$1, %edi
	movq	%rbx, %rsi
	callq	calloc@PLT
	movq	%rax, %r12
	movl	$1, %edi
	movl	%r15d, %esi
	movl	$1, %edx
	movl	$1, %ecx
	movq	16(%rsp), %r13                  # 8-byte Reload
	movl	%r13d, %r8d
	movl	$1, %r9d
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z13pattern2d_cpuiiiiiiPfS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	leal	-2(%r15), %eax
	leal	29(%r15), %ecx
	testl	%eax, %eax
	movl	%eax, 44(%rsp)                  # 4-byte Spill
	cmovnsl	%eax, %ecx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	leal	-2(%r13), %eax
	addl	$13, %r13d
	testl	%eax, %eax
	movl	%eax, 40(%rsp)                  # 4-byte Spill
	cmovnsl	%eax, %r13d
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.9:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	callq	hipMemset
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.13:
	movq	64(%rsp), %rax                  # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax
	sarl	$5, %eax
	movl	%r13d, %ecx
	sarl	$4, %ecx
	shlq	$32, %rcx
	movl	%eax, %edi
	orq	%rcx, %rdi
	movabsq	$68719476768, %rdx              # imm = 0x1000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:
	movl	$1, %edi
	movl	%r15d, %esi
	movl	$1, %edx
	movl	$1, %ecx
	movq	16(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	movl	$1, %r9d
	pushq	8(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB2_15:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_16
# %bb.17:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB2_18
# %bb.19:
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_20
# %bb.21:                               # %.preheader.lr.ph
	movq	64(%rsp), %rax                  # 8-byte Reload
	andl	$-32, %eax
	andl	$-16, %r13d
	negl	%eax
	negl	%r13d
	leal	(%r15,%rax), %ebx
	addl	$-2, %ebx
	movq	16(%rsp), %rbp                  # 8-byte Reload
	leal	-2(%rbp,%r13), %eax
	movl	40(%rsp), %ecx                  # 4-byte Reload
	subl	%eax, %ecx
	movl	$1, %edi
	movl	%r15d, %esi
	movl	$1, %edx
	movl	%ebp, %r8d
	movl	$1, %r9d
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	movq	56(%rsp), %r13                  # 8-byte Reload
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z13pattern2d_cpuiiiiiiPfS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	44(%rsp), %edi                  # 4-byte Reload
	subl	%ebx, %edi
	movl	%r15d, %esi
	movl	$1, %edx
	movl	$1, %ecx
	movl	%ebp, %r8d
	movl	$1, %r9d
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z13pattern2d_cpuiiiiiiPfS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movss	(%r14), %xmm2                   # xmm2 = mem[0],zero,zero,zero
	subss	(%r12), %xmm2
	andps	.LCPI2_0(%rip), %xmm2
	movl	%ebp, %eax
	movl	%r15d, %ecx
	xorl	%edx, %edx
	movaps	.LCPI2_0(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
.LBB2_22:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_23 Depth 2
	movl	%edx, %r8d
	leaq	(%r12,%r8,4), %rdi
	leaq	(%r14,%r8,4), %r8
	xorl	%r9d, %r9d
.LBB2_23:                               #   Parent Loop BB2_22 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movaps	%xmm2, %xmm1
	movss	(%r8,%r9,4), %xmm2              # xmm2 = mem[0],zero,zero,zero
	subss	(%rdi,%r9,4), %xmm2
	andps	%xmm0, %xmm2
	ucomiss	%xmm1, %xmm2
	cmoval	%r9d, %r13d
	cmoval	%esi, %ebx
	maxss	%xmm1, %xmm2
	incq	%r9
	cmpq	%r9, %rcx
	jne	.LBB2_23
# %bb.24:                               # %._crit_edge
                                        #   in Loop: Header=BB2_22 Depth=1
	incq	%rsi
	addl	%r15d, %edx
	cmpq	%rax, %rsi
	jne	.LBB2_22
# %bb.25:                               # %._crit_edge158
	movaps	%xmm2, 48(%rsp)                 # 16-byte Spill
	movq	24(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB2_26
# %bb.27:
	movq	%r12, %rdi
	callq	free
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB2_28
# %bb.29:
	xorps	%xmm0, %xmm0
	cvtss2sd	48(%rsp), %xmm0                 # 16-byte Folded Reload
	movl	$.L.str.10, %edi
	movl	36(%rsp), %esi                  # 4-byte Reload
	movl	4(%rsp), %edx                   # 4-byte Reload
	movl	%r13d, %ecx
	movl	%ebx, %r8d
	movb	$1, %al
	callq	printf
	xorl	%ebp, %ebp
	jmp	.LBB2_30
.LBB2_3:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movl	%r12d, %ecx
	jmp	.LBB2_4
.LBB2_6:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.2, %esi
	movl	%r12d, %edx
	jmp	.LBB2_12
.LBB2_8:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str, %esi
	movl	$.L.str.3, %edx
	movl	4(%rsp), %ecx                   # 4-byte Reload
.LBB2_4:
	movl	%ebp, %r8d
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB2_30
.LBB2_10:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.4, %esi
	jmp	.LBB2_11
.LBB2_16:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.5, %esi
	jmp	.LBB2_11
.LBB2_18:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.6, %esi
	jmp	.LBB2_11
.LBB2_20:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.7, %esi
	jmp	.LBB2_11
.LBB2_26:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.8, %esi
	jmp	.LBB2_11
.LBB2_28:
	movl	%eax, %ebp
	movq	stderr(%rip), %rdi
	movl	$.L.str.9, %esi
.LBB2_11:
	movl	4(%rsp), %edx                   # 4-byte Reload
.LBB2_12:
	movl	%ebp, %ecx
	xorl	%eax, %eax
	callq	fprintf
.LBB2_30:
	movl	%ebp, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9pattern2diiPfS_ii, .Lfunc_end2-_Z9pattern2diiPfS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13pattern2d_gpuiiiiiiPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13pattern2d_gpuiiiiiiPfS_,@object # @_Z13pattern2d_gpuiiiiiiPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z13pattern2d_gpuiiiiiiPfS_
	.p2align	3, 0x0
_Z13pattern2d_gpuiiiiiiPfS_:
	.quad	_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
	.size	_Z13pattern2d_gpuiiiiiiPfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%s %d, status = %d\nInsufficient GPU memory?\n"
	.size	.L.str, 45

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Cannot malloc input memory on GPU by process"
	.size	.L.str.1, 45

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Cannot copy data from host to gpu by process %d, status = %d\n"
	.size	.L.str.2, 62

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Cannot malloc output memory on GPU by process"
	.size	.L.str.3, 46

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Cannot erase output memory on GPU by process %d, status = %d\n"
	.size	.L.str.4, 62

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Cannot execute CUDA kernel by process %d, status = %d\n"
	.size	.L.str.5, 55

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Cannot synchronize thread by process %d, status = %d\n"
	.size	.L.str.6, 54

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Cannot copy data from gpu to host by process %d, status = %d\n"
	.size	.L.str.7, 62

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Cannot free device input memory by process %d, status = %d\n"
	.size	.L.str.8, 60

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Cannot free device output memory by process %d, status = %d\n"
	.size	.L.str.9, 61

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Step %d result abs max diff by process %d = %f @ (%d,%d)\n"
	.size	.L.str.10, 58

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13pattern2d_gpuiiiiiiPfS_"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13pattern2d_gpuiiiiiiPfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13pattern2d_gpuiiiiiiPfS_ ; -- Begin function _Z13pattern2d_gpuiiiiiiPfS_
	.globl	_Z13pattern2d_gpuiiiiiiPfS_
	.p2align	8
	.type	_Z13pattern2d_gpuiiiiiiPfS_,@function
_Z13pattern2d_gpuiiiiiiPfS_:            ; @_Z13pattern2d_gpuiiiiiiPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0xc
	s_load_b64 s[4:5], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	s_lshl_b32 s3, s15, 4
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v1, s2, s3, v1
	s_lshl_b32 s2, s14, 5
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v3, s4, s2, v0
	s_load_b128 s[0:3], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s5
	v_add_nc_u32_e32 v0, v1, v3
	v_subrev_nc_u32_e32 v4, s5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, -1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v6, s5, 1, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_clause 0x1
	global_load_b64 v[8:9], v[8:9], off
	global_load_b32 v10, v[2:3], off
	v_lshlrev_b64 v[2:3], 2, v[6:7]
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v3, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v9
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v3, -2.0, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v2, v2, 0x40400000, v3
	v_mul_f32_e64 v3, 0x4f800000, |v2|
	v_cmp_gt_f32_e64 vcc_lo, 0xf800000, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, |v2|, v3, vcc_lo
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v5, 1, v3
	v_add_nc_u32_e32 v4, -1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v3, v2
	v_fma_f32 v6, -v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v6
	v_cndmask_b32_e64 v3, v3, v4, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v7
	v_cndmask_b32_e64 v3, v3, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x37800000, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13pattern2d_gpuiiiiiiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13pattern2d_gpuiiiiiiPfS_, .Lfunc_end0-_Z13pattern2d_gpuiiiiiiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13pattern2d_gpuiiiiiiPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13pattern2d_gpuiiiiiiPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
