#include <stdio.h>
#include <stdlib.h>



__global__
void gpu_conv1d(float *d_out, float *d_in, float *d_filter, int size_in, int size_filter){
	int i = blockDim.x * blockIdx.x + threadIdx.x;
	float sum = 0.0;
	int offset = size_filter / 2;
	if (i < size_in){
		for (int j=0; j < size_filter; j++){
			if ((i-offset+j) >= 0 && (i - offset + j) <= size_in)
				sum += d_in[i-offset+j]*d_filter[j];
		}
		d_out[i] = sum;
	}

}

void init(float *arr, int N, float val){
	for (int r=0; r < N; r++){
			arr[r] = val;
	}
}

void host_conv1d(float *h_out, float *h_in, float *h_filter, int size_in, int size_filter){
	
	int offset = size_filter / 2;
	for (int i =0; i < size_in; i++){
		float sum = 0.0;
		for (int j = 0; j < size_filter; j++){
			if ((i-offset+j) >= 0 && (i - offset + j) <= size_in)
				sum += h_in[i-offset+j]*h_filter[j];
		}
		h_out[i] = sum;
	}

}

int main(){
	float *d_in, *d_filter, *d_out;
	float *h_in, *h_filter, *h_out; // Only for checking. Not needed for functionality


	int din_size = 24;
	int filter_size = 5;

	size_t size_in = din_size*sizeof(float);
	size_t size_filter = filter_size*sizeof(float);
	size_t size_out = din_size*sizeof(float);

	h_in = (float*) malloc (size_in);
	h_filter = (float*) malloc (size_filter);
	h_out = (float*) malloc (size_out);

	cudaMallocManaged(&d_in, size_in);
	cudaMallocManaged(&d_filter, size_filter);
	cudaMallocManaged(&d_out, size_out);

	init(d_in, size_in, 1.0);
	init(d_filter, size_filter, 1.0);
	init(d_out, size_out, 0.0);

	size_t num_threads = 256;
	size_t num_blocks = (size_out-1)/num_threads + 1;

	gpu_conv1d<<<num_blocks, num_threads>>>(d_out, d_in, d_filter, size_in, size_filter);
	cudaDeviceSynchronize();

	init(h_in, size_in, 1.0);
	init(h_filter, size_filter, 1.0);
	init(h_out, size_out, 0.0);

	host_conv1d(h_out, h_in, h_filter, size_in, size_filter);
    for (int i =0; i<size_out; i++)
            if (d_out[i] != h_out[i]){
                    printf("Program failed!! Check the idx: %d", i);
                    return 0;
            }
    printf("Success!!\n");
}

	.file	"tmpxft_00254d28_00000000-6_conv1d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4initPfif
	.type	_Z4initPfif, @function
_Z4initPfif:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	cmpl	%eax, %esi
	jle	.L6
	movss	%xmm0, (%rdi,%rax,4)
	incq	%rax
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z4initPfif, .-_Z4initPfif
	.globl	_Z11host_conv1dPfS_S_ii
	.type	_Z11host_conv1dPfS_S_ii, @function
_Z11host_conv1dPfS_S_ii:
.LFB2028:
	.cfi_startproc
	endbr64
	movl	%r8d, %eax
	movq	%rdi, %r10
	movq	%rdx, %r11
	movl	%ecx, %edi
	cltd
	movl	$2, %ecx
	idivl	%ecx
	xorl	%ecx, %ecx
	movslq	%eax, %rdx
	negl	%eax
	imulq	$-4, %rdx, %rdx
	addq	%rsi, %rdx
	cmpl	%ecx, %edi
	jg	.L18
	ret
.L18:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
.L12:
	movl	%eax, %r9d
	movq	%rdx, %rbx
	xorps	%xmm0, %xmm0
	xorl	%esi, %esi
.L11:
	cmpl	%esi, %r8d
	jle	.L19
	testl	%r9d, %r9d
	js	.L9
	cmpl	%r9d, %edi
	jl	.L9
	movss	(%rbx), %xmm1
	mulss	(%r11,%rsi,4), %xmm1
	addss	%xmm1, %xmm0
.L9:
	incq	%rsi
	addq	$4, %rbx
	incl	%r9d
	jmp	.L11
.L19:
	movss	%xmm0, (%r10,%rcx,4)
	incq	%rcx
	addq	$4, %rdx
	incl	%eax
	cmpl	%ecx, %edi
	jg	.L12
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z11host_conv1dPfS_S_ii, .-_Z11host_conv1dPfS_S_ii
	.globl	_Z36__device_stub__Z10gpu_conv1dPfS_S_iiPfS_S_ii
	.type	_Z36__device_stub__Z10gpu_conv1dPfS_S_iiPfS_S_ii, @function
_Z36__device_stub__Z10gpu_conv1dPfS_S_iiPfS_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10gpu_conv1dPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L20:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z36__device_stub__Z10gpu_conv1dPfS_S_iiPfS_S_ii, .-_Z36__device_stub__Z10gpu_conv1dPfS_S_iiPfS_S_ii
	.globl	_Z10gpu_conv1dPfS_S_ii
	.type	_Z10gpu_conv1dPfS_S_ii, @function
_Z10gpu_conv1dPfS_S_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10gpu_conv1dPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2055:
	.size	_Z10gpu_conv1dPfS_S_ii, .-_Z10gpu_conv1dPfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"Program failed!! Check the idx: %d"
.LC3:
	.string	"Success!!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$96, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$20, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$96, %edi
	movq	%rax, %r12
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$96, %esi
	movq	%rax, %rbx
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$20, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$96, %esi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$96, %esi
	movl	$16777217, %edx
	movl	$1, %ecx
	movss	.LC1(%rip), %xmm0
	salq	$8, %rdx
	call	_Z4initPfif
	movq	16(%rsp), %rdi
	movl	$20, %esi
	movss	.LC1(%rip), %xmm0
	call	_Z4initPfif
	movq	24(%rsp), %rdi
	movl	$96, %esi
	xorps	%xmm0, %xmm0
	call	_Z4initPfif
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$96, %ecx
	movl	$20, %r8d
	movq	24(%rsp), %rdi
	call	_Z36__device_stub__Z10gpu_conv1dPfS_S_iiPfS_S_ii
.L26:
	call	cudaDeviceSynchronize@PLT
	movl	$96, %esi
	movq	%rbp, %rdi
	movq	%r12, %rdx
	movss	.LC1(%rip), %xmm0
	movl	$20, %r8d
	movl	$96, %ecx
	call	_Z4initPfif
	movss	.LC1(%rip), %xmm0
	movl	$20, %esi
	movq	%r12, %rdi
	call	_Z4initPfif
	xorps	%xmm0, %xmm0
	movl	$96, %esi
	movq	%rbx, %rdi
	call	_Z4initPfif
	movq	%rbp, %rsi
	call	_Z11host_conv1dPfS_S_ii
	movq	24(%rsp), %rax
	xorl	%edx, %edx
.L30:
	movss	(%rax,%rdx,4), %xmm0
	ucomiss	(%rbx,%rdx,4), %xmm0
	jp	.L32
	je	.L27
.L32:
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L29
.L27:
	incq	%rdx
	cmpq	$96, %rdx
	jne	.L30
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L29:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z10gpu_conv1dPfS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10gpu_conv1dPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>



__global__
void gpu_conv1d(float *d_out, float *d_in, float *d_filter, int size_in, int size_filter){
	int i = blockDim.x * blockIdx.x + threadIdx.x;
	float sum = 0.0;
	int offset = size_filter / 2;
	if (i < size_in){
		for (int j=0; j < size_filter; j++){
			if ((i-offset+j) >= 0 && (i - offset + j) <= size_in)
				sum += d_in[i-offset+j]*d_filter[j];
		}
		d_out[i] = sum;
	}

}

void init(float *arr, int N, float val){
	for (int r=0; r < N; r++){
			arr[r] = val;
	}
}

void host_conv1d(float *h_out, float *h_in, float *h_filter, int size_in, int size_filter){
	
	int offset = size_filter / 2;
	for (int i =0; i < size_in; i++){
		float sum = 0.0;
		for (int j = 0; j < size_filter; j++){
			if ((i-offset+j) >= 0 && (i - offset + j) <= size_in)
				sum += h_in[i-offset+j]*h_filter[j];
		}
		h_out[i] = sum;
	}

}

int main(){
	float *d_in, *d_filter, *d_out;
	float *h_in, *h_filter, *h_out; // Only for checking. Not needed for functionality


	int din_size = 24;
	int filter_size = 5;

	size_t size_in = din_size*sizeof(float);
	size_t size_filter = filter_size*sizeof(float);
	size_t size_out = din_size*sizeof(float);

	h_in = (float*) malloc (size_in);
	h_filter = (float*) malloc (size_filter);
	h_out = (float*) malloc (size_out);

	hipMallocManaged(&d_in, size_in);
	hipMallocManaged(&d_filter, size_filter);
	hipMallocManaged(&d_out, size_out);

	init(d_in, size_in, 1.0);
	init(d_filter, size_filter, 1.0);
	init(d_out, size_out, 0.0);

	size_t num_threads = 256;
	size_t num_blocks = (size_out-1)/num_threads + 1;

	gpu_conv1d<<<num_blocks, num_threads>>>(d_out, d_in, d_filter, size_in, size_filter);
	hipDeviceSynchronize();

	init(h_in, size_in, 1.0);
	init(h_filter, size_filter, 1.0);
	init(h_out, size_out, 0.0);

	host_conv1d(h_out, h_in, h_filter, size_in, size_filter);
    for (int i =0; i<size_out; i++)
            if (d_out[i] != h_out[i]){
                    printf("Program failed!! Check the idx: %d", i);
                    return 0;
            }
    printf("Success!!\n");
}

	.text
	.file	"conv1d.hip"
	.globl	_Z25__device_stub__gpu_conv1dPfS_S_ii # -- Begin function _Z25__device_stub__gpu_conv1dPfS_S_ii
	.type	_Z25__device_stub__gpu_conv1dPfS_S_ii,@function
_Z25__device_stub__gpu_conv1dPfS_S_ii:  # @_Z25__device_stub__gpu_conv1dPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_conv1dPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__gpu_conv1dPfS_S_ii, .Lfunc_end0-_Z25__device_stub__gpu_conv1dPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z4initPfif                     # -- Begin function _Z4initPfif
	.type	_Z4initPfif,@function
_Z4initPfif:                            # @_Z4initPfif
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%esi, %eax
	xorl	%ecx, %ecx
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	%xmm0, (%rdi,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	retq
.Lfunc_end1:
	.size	_Z4initPfif, .Lfunc_end1-_Z4initPfif
	.cfi_endproc
                                        # -- End function
	.globl	_Z11host_conv1dPfS_S_ii         # -- Begin function _Z11host_conv1dPfS_S_ii
	.type	_Z11host_conv1dPfS_S_ii,@function
_Z11host_conv1dPfS_S_ii:                # @_Z11host_conv1dPfS_S_ii
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB2_6
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r10d
	shrl	$31, %r10d
	addl	%r8d, %r10d
	sarl	%r10d
	negl	%r10d
	movl	%ecx, %eax
	movl	%r8d, %r9d
	movl	%r10d, %r10d
	xorl	%r11d, %r11d
.LBB2_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_8 Depth 2
	testl	%r8d, %r8d
	jle	.LBB2_3
# %bb.7:                                # %.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	movslq	%r10d, %rbx
	leaq	(%rsi,%rbx,4), %rbx
	xorps	%xmm0, %xmm0
	xorl	%r14d, %r14d
.LBB2_8:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%r10,%r14), %ebp
	cmpl	%ecx, %ebp
	ja	.LBB2_10
# %bb.9:                                #   in Loop: Header=BB2_8 Depth=2
	movss	(%rbx,%r14,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%rdx,%r14,4), %xmm1
	addss	%xmm1, %xmm0
.LBB2_10:                               #   in Loop: Header=BB2_8 Depth=2
	incq	%r14
	cmpq	%r14, %r9
	jne	.LBB2_8
	jmp	.LBB2_4
.LBB2_3:                                #   in Loop: Header=BB2_2 Depth=1
	xorps	%xmm0, %xmm0
.LBB2_4:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	movss	%xmm0, (%rdi,%r11,4)
	incq	%r11
	incq	%r10
	cmpq	%rax, %r11
	jne	.LBB2_2
# %bb.5:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %rbp
.LBB2_6:                                # %._crit_edge30
	retq
.Lfunc_end2:
	.size	_Z11host_conv1dPfS_S_ii, .Lfunc_end2-_Z11host_conv1dPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$96, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$20, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$96, %edi
	callq	malloc
	movq	%rax, %rbx
	leaq	16(%rsp), %r12
	movl	$96, %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$20, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movl	$96, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%eax, %eax
	movq	(%r12), %rcx
.LBB3_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rcx,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$96, %rax
	jne	.LBB3_1
# %bb.2:                                # %_Z4initPfif.exit
	movq	8(%rsp), %rax
	xorl	%ecx, %ecx
.LBB3_3:                                # %.lr.ph.i42
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rax,%rcx,4)      # imm = 0x3F800000
	incq	%rcx
	cmpq	$20, %rcx
	jne	.LBB3_3
# %bb.4:                                # %_Z4initPfif.exit46
	movq	(%rsp), %rdi
	movl	$384, %edx                      # imm = 0x180
	xorl	%esi, %esi
	callq	memset@PLT
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	255(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$96, %ecx
	movl	$20, %r8d
	callq	_Z25__device_stub__gpu_conv1dPfS_S_ii
.LBB3_6:
	callq	hipDeviceSynchronize
	xorl	%eax, %eax
.LBB3_7:                                # %.lr.ph.i52
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r14,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$96, %rax
	jne	.LBB3_7
# %bb.8:                                # %.lr.ph.i57.preheader
	xorl	%eax, %eax
.LBB3_9:                                # %.lr.ph.i57
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r15,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$20, %rax
	jne	.LBB3_9
# %bb.10:                               # %.preheader.i.preheader
	xorl	%eax, %eax
.LBB3_11:                               # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_12 Depth 2
	xorps	%xmm0, %xmm0
	movq	$-10, %rcx
.LBB3_12:                               #   Parent Loop BB3_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rax,%rcx), %edx
	cmpl	$96, %edx
	ja	.LBB3_14
# %bb.13:                               #   in Loop: Header=BB3_12 Depth=2
	movss	(%r14,%rcx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	40(%r15,%rcx,4), %xmm1
	addss	%xmm1, %xmm0
.LBB3_14:                               #   in Loop: Header=BB3_12 Depth=2
	incq	%rcx
	cmpq	$10, %rcx
	jne	.LBB3_12
# %bb.15:                               # %._crit_edge.i
                                        #   in Loop: Header=BB3_11 Depth=1
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	addq	$4, %r14
	cmpq	$96, %rax
	jne	.LBB3_11
# %bb.16:                               # %_Z11host_conv1dPfS_S_ii.exit.preheader
	movq	(%rsp), %rax
	xorl	%esi, %esi
.LBB3_17:                               # =>This Inner Loop Header: Depth=1
	movss	(%rax,%rsi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%rbx,%rsi,4), %xmm0
	jne	.LBB3_18
	jp	.LBB3_18
# %bb.19:                               # %_Z11host_conv1dPfS_S_ii.exit
                                        #   in Loop: Header=BB3_17 Depth=1
	incq	%rsi
	cmpq	$96, %rsi
	jne	.LBB3_17
# %bb.20:                               # %.critedge
	movl	$.Lstr, %edi
	callq	puts@PLT
	jmp	.LBB3_21
.LBB3_18:
	movl	$.L.str, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
.LBB3_21:
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_conv1dPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10gpu_conv1dPfS_S_ii,@object  # @_Z10gpu_conv1dPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z10gpu_conv1dPfS_S_ii
	.p2align	3, 0x0
_Z10gpu_conv1dPfS_S_ii:
	.quad	_Z25__device_stub__gpu_conv1dPfS_S_ii
	.size	_Z10gpu_conv1dPfS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Program failed!! Check the idx: %d"
	.size	.L.str, 35

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10gpu_conv1dPfS_S_ii"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Success!!"
	.size	.Lstr, 10

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__gpu_conv1dPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10gpu_conv1dPfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10gpu_conv1dPfS_S_ii  ; -- Begin function _Z10gpu_conv1dPfS_S_ii
	.globl	_Z10gpu_conv1dPfS_S_ii
	.p2align	8
	.type	_Z10gpu_conv1dPfS_S_ii,@function
_Z10gpu_conv1dPfS_S_ii:                 ; @_Z10gpu_conv1dPfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_8
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB0_6
; %bb.2:                                ; %.lr.ph
	s_lshr_b32 s0, s3, 31
	v_mov_b32_e32 v3, 0
	s_add_i32 s0, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s0, s0, 1
	v_mov_b32_e32 v0, v3
	v_subrev_nc_u32_e32 v2, s0, v1
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_cmp_ge_i32_e64 s0, s2, v2
	s_and_b32 s1, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_load_b32 s1, s[8:9], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s1, v4
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s3, s3, -1
	v_add_nc_u32_e32 v2, 1, v2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_7
.LBB0_6:
	v_mov_b32_e32 v0, 0
.LBB0_7:                                ; %Flow48
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_conv1dPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10gpu_conv1dPfS_S_ii, .Lfunc_end0-_Z10gpu_conv1dPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10gpu_conv1dPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10gpu_conv1dPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
