__device__
int rectanglesSum(int** integralImage, int x, int y, int w, int h)
{
	int A = x > 0 && y > 0 ? integralImage[x - 1][y - 1] : 0;
	int B = x + w > 0 && y > 0 ? integralImage[x + w - 1][y - 1] : 0;
	int C = x > 0 && y + h > 0 ? integralImage[x - 1][y + h - 1] : 0;
	int D = x + w > 0 && y + h > 0 ? integralImage[x + w - 1][y + h - 1] : 0;

	return A + D - B - C;
}

extern "C"
	__global__
void computeWindowFeatures(int** integralImage, int* features, int totalNumFeatures, float* window, int* haarFeatures)
{
	// Get an "unique id" of the thread
	const unsigned int blockId = ((blockIdx.y * 65535) + blockIdx.x);
	const unsigned int tidX = blockId * blockDim.x + threadIdx.x;

	if (tidX < totalNumFeatures)
	{
		int type = features[threadIdx.x * 5];
        int x = (int) ((float)features[threadIdx.x * 5 + 1] * window[blockId * 3 + 2] + window[blockId * 3]);
        int y = (int) ((float)features[threadIdx.x * 5 + 2] * window[blockId * 3 + 2] + window[blockId * 3 + 1]);
		int w = (int) (((float) (features[threadIdx.x * 5 + 3])) * window[blockId * 3 + 2]);
		int h = (int) (((float) (features[threadIdx.x * 5 + 4])) * window[blockId * 3 + 2]);

		if (type == 1)
		{
			int mid = w / 2;
			int r1 = rectanglesSum(integralImage, x, y, mid, h);
			int r2 = rectanglesSum(integralImage, x + mid, y, mid, h);
			haarFeatures[tidX] = r1 - r2;
		}
		else if (type == 2)
		{
			int mid = w / 3;

			int r1 = rectanglesSum(integralImage, x, y, mid, h);
			int r2 = rectanglesSum(integralImage, x + mid, y, mid, h);
			int r3 = rectanglesSum(integralImage, x + 2 * mid, y, mid, h);

			haarFeatures[tidX] = r1 - r2 + r3;
		}
		else if (type == 3)
		{
			int mid = h / 2;
			int r1 = rectanglesSum(integralImage, x, y, w, mid);
			int r2 = rectanglesSum(integralImage, x, y + mid, w, mid);
			haarFeatures[tidX] = r2 - r1;
		}
		else if (type == 4)
		{
			int mid = h / 3;

			int r1 = rectanglesSum(integralImage, x, y, w, mid);
			int r2 = rectanglesSum(integralImage, x, y + mid, w, mid);
			int r3 = rectanglesSum(integralImage, x, y + 2 * mid, w, mid);

			haarFeatures[tidX] = r1 - r2 + r3;
		}
		else if (type == 5)
		{
			int mid_w = w / 2;
			int mid_h = h / 2;

			int r1 = rectanglesSum(integralImage, x, y, mid_w, mid_h);
			int r2 = rectanglesSum(integralImage, x + mid_w, y, mid_w, mid_h);
			int r3 = rectanglesSum(integralImage, x, y + mid_h, mid_w, mid_h);
			int r4 = rectanglesSum(integralImage, x + mid_w, y + mid_h, mid_w, mid_h);

			haarFeatures[tidX] = r1 - r2 - r3 + r4;
		}
	}

	__syncthreads();
}

	.file	"tmpxft_0021c483_00000000-6_ComputeWindowFeatures.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13rectanglesSumPPiiiii
	.type	_Z13rectanglesSumPPiiiii, @function
_Z13rectanglesSumPPiiiii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z13rectanglesSumPPiiiii, .-_Z13rectanglesSumPPiiiii
	.globl	_Z49__device_stub__Z21computeWindowFeaturesPPiS_iPfS_PPiS_iPfS_
	.type	_Z49__device_stub__Z21computeWindowFeaturesPPiS_iPfS_PPiS_iPfS_, @function
_Z49__device_stub__Z21computeWindowFeaturesPPiS_iPfS_PPiS_iPfS_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	computeWindowFeatures(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L4:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z49__device_stub__Z21computeWindowFeaturesPPiS_iPfS_PPiS_iPfS_, .-_Z49__device_stub__Z21computeWindowFeaturesPPiS_iPfS_PPiS_iPfS_
	.globl	computeWindowFeatures
	.type	computeWindowFeatures, @function
computeWindowFeatures:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z21computeWindowFeaturesPPiS_iPfS_PPiS_iPfS_
	.cfi_endproc
.LFE2034:
	.size	computeWindowFeatures, .-computeWindowFeatures
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"computeWindowFeatures"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	computeWindowFeatures(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__device__
int rectanglesSum(int** integralImage, int x, int y, int w, int h)
{
	int A = x > 0 && y > 0 ? integralImage[x - 1][y - 1] : 0;
	int B = x + w > 0 && y > 0 ? integralImage[x + w - 1][y - 1] : 0;
	int C = x > 0 && y + h > 0 ? integralImage[x - 1][y + h - 1] : 0;
	int D = x + w > 0 && y + h > 0 ? integralImage[x + w - 1][y + h - 1] : 0;

	return A + D - B - C;
}

extern "C"
	__global__
void computeWindowFeatures(int** integralImage, int* features, int totalNumFeatures, float* window, int* haarFeatures)
{
	// Get an "unique id" of the thread
	const unsigned int blockId = ((blockIdx.y * 65535) + blockIdx.x);
	const unsigned int tidX = blockId * blockDim.x + threadIdx.x;

	if (tidX < totalNumFeatures)
	{
		int type = features[threadIdx.x * 5];
        int x = (int) ((float)features[threadIdx.x * 5 + 1] * window[blockId * 3 + 2] + window[blockId * 3]);
        int y = (int) ((float)features[threadIdx.x * 5 + 2] * window[blockId * 3 + 2] + window[blockId * 3 + 1]);
		int w = (int) (((float) (features[threadIdx.x * 5 + 3])) * window[blockId * 3 + 2]);
		int h = (int) (((float) (features[threadIdx.x * 5 + 4])) * window[blockId * 3 + 2]);

		if (type == 1)
		{
			int mid = w / 2;
			int r1 = rectanglesSum(integralImage, x, y, mid, h);
			int r2 = rectanglesSum(integralImage, x + mid, y, mid, h);
			haarFeatures[tidX] = r1 - r2;
		}
		else if (type == 2)
		{
			int mid = w / 3;

			int r1 = rectanglesSum(integralImage, x, y, mid, h);
			int r2 = rectanglesSum(integralImage, x + mid, y, mid, h);
			int r3 = rectanglesSum(integralImage, x + 2 * mid, y, mid, h);

			haarFeatures[tidX] = r1 - r2 + r3;
		}
		else if (type == 3)
		{
			int mid = h / 2;
			int r1 = rectanglesSum(integralImage, x, y, w, mid);
			int r2 = rectanglesSum(integralImage, x, y + mid, w, mid);
			haarFeatures[tidX] = r2 - r1;
		}
		else if (type == 4)
		{
			int mid = h / 3;

			int r1 = rectanglesSum(integralImage, x, y, w, mid);
			int r2 = rectanglesSum(integralImage, x, y + mid, w, mid);
			int r3 = rectanglesSum(integralImage, x, y + 2 * mid, w, mid);

			haarFeatures[tidX] = r1 - r2 + r3;
		}
		else if (type == 5)
		{
			int mid_w = w / 2;
			int mid_h = h / 2;

			int r1 = rectanglesSum(integralImage, x, y, mid_w, mid_h);
			int r2 = rectanglesSum(integralImage, x + mid_w, y, mid_w, mid_h);
			int r3 = rectanglesSum(integralImage, x, y + mid_h, mid_w, mid_h);
			int r4 = rectanglesSum(integralImage, x + mid_w, y + mid_h, mid_w, mid_h);

			haarFeatures[tidX] = r1 - r2 - r3 + r4;
		}
	}

	__syncthreads();
}

	.text
	.file	"ComputeWindowFeatures.hip"
	.globl	__device_stub__computeWindowFeatures # -- Begin function __device_stub__computeWindowFeatures
	.type	__device_stub__computeWindowFeatures,@function
__device_stub__computeWindowFeatures:   # @__device_stub__computeWindowFeatures
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$computeWindowFeatures, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__computeWindowFeatures, .Lfunc_end0-__device_stub__computeWindowFeatures
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$computeWindowFeatures, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	computeWindowFeatures,@object   # @computeWindowFeatures
	.section	.rodata,"a",@progbits
	.globl	computeWindowFeatures
	.p2align	3, 0x0
computeWindowFeatures:
	.quad	__device_stub__computeWindowFeatures
	.size	computeWindowFeatures, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"computeWindowFeatures"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__computeWindowFeatures
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym computeWindowFeatures
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	computeWindowFeatures   ; -- Begin function computeWindowFeatures
	.globl	computeWindowFeatures
	.p2align	8
	.type	computeWindowFeatures,@function
computeWindowFeatures:                  ; @computeWindowFeatures
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s4, s[0:1], 0x10
	s_mul_i32 s2, s15, 0xffff
	s_mov_b32 s12, exec_lo
	s_add_i32 s2, s2, s14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s2, s3, v[0:1]
	v_cmpx_gt_u32_e64 s4, v4
	s_cbranch_execz .LBB0_185
; %bb.1:                                ; %NodeBlock276
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x18
	v_mul_u32_u24_e32 v0, 5, v0
	s_mul_i32 s0, s2, 3
	s_mov_b32 s3, 0
	s_add_i32 s2, s0, 2
	s_mov_b32 s1, s3
	v_lshlrev_b32_e32 v5, 2, v0
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b128 v[0:3], v5, s[10:11]
	global_load_b32 v5, v5, s[10:11] offset:16
	s_lshl_b64 s[10:11], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s10, s4, s10
	s_addc_u32 s11, s5, s11
	s_lshl_b64 s[14:15], s[0:1], 2
	s_add_u32 s14, s4, s14
	s_addc_u32 s15, s5, s15
	s_add_i32 s2, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_clause 0x2
	s_load_b32 s2, s[10:11], 0x0
	s_load_b32 s4, s[14:15], 0x0
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt vmcnt(1)
	v_cvt_f32_i32_e32 v1, v1
	v_cvt_f32_i32_e32 v2, v2
	v_cvt_f32_i32_e32 v3, v3
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v5, v5
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v1, s2, v1, s4
	v_fma_f32 v2, s2, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v3, s2, v3 :: v_dual_mul_f32 v6, s2, v5
	s_mov_b32 s0, exec_lo
	v_cvt_i32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v5, v2
	v_cvt_i32_f32_e32 v7, v3
	v_cvt_i32_f32_e32 v9, v6
                                        ; implicit-def: $vgpr6
	v_cmpx_lt_i32_e32 2, v0
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_115
; %bb.2:                                ; %NodeBlock274
                                        ; implicit-def: $vgpr6
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 3, v0
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB0_90
; %bb.3:                                ; %NodeBlock272
                                        ; implicit-def: $vgpr6
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 4, v0
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_53
; %bb.4:                                ; %LeafBlock270
	s_mov_b32 s0, 0
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr6
	v_cmpx_eq_u32_e32 5, v0
	s_cbranch_execz .LBB0_52
; %bb.5:
	v_cmp_lt_i32_e64 s0, 0, v1
	v_cmp_lt_i32_e64 s2, 0, v5
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s0, s2
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[12:13], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v10, v12
	v_add_co_ci_u32_e32 v2, vcc_lo, v11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, -1, v2, vcc_lo
	flat_load_b32 v13, v[10:11]
.LBB0_7:
	s_or_b32 exec_lo, exec_lo, s1
	v_lshrrev_b32_e32 v0, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v7, v0
	v_ashrrev_i32_e32 v11, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v11, v1
	v_cmp_lt_i32_e32 vcc_lo, 0, v7
	s_and_b32 s3, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s13, s3
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[14:15], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s8, v2
	v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
	global_load_b64 v[2:3], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s1, v2, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s1, v3, v15, s1
	v_add_co_u32 v2, s1, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s1, -1, v3, s1
	flat_load_b32 v3, v[2:3]
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s13
	v_lshrrev_b32_e32 v0, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v15, 0 :: v_dual_add_nc_u32 v0, v9, v0
	v_ashrrev_i32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v14, 0 :: v_dual_add_nc_u32 v9, v0, v5
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_13
; %bb.10:
	v_mov_b32_e32 v15, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i32_e32 0, v9
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 3, v[1:2]
	v_mov_b32_e32 v10, v2
	v_lshlrev_b64 v[17:18], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s1, s8, v15
	v_add_co_ci_u32_e64 v16, s1, s9, v16, s1
	global_load_b64 v[15:16], v[15:16], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v16, v18, s1
	v_add_co_u32 v15, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s1, -1, v6, s1
	flat_load_b32 v15, v[15:16]
.LBB0_12:                               ; %Flow283
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_13:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB0_17
; %bb.14:
	v_mov_b32_e32 v14, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i32_e32 0, v9
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[7:8]
	v_mov_b32_e32 v10, v8
	v_lshlrev_b64 v[18:19], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v16, s1, s8, v16
	v_add_co_ci_u32_e64 v17, s1, s9, v17, s1
	global_load_b64 v[16:17], v[16:17], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v17, v19, s1
	v_add_co_u32 v16, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v17, s1, -1, v6, s1
	flat_load_b32 v14, v[16:17]
.LBB0_16:                               ; %Flow282
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_17:                               ; %_Z13rectanglesSumPPiiiii.exit168
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v17, 0
	s_and_saveexec_b32 s13, s3
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[19:20], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s1, s8, v17
	v_add_co_ci_u32_e64 v18, s1, s9, v18, s1
	global_load_b64 v[17:18], v[17:18], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v18, v20, s1
	v_add_co_u32 v17, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v18, s1, -1, v6, s1
	flat_load_b32 v17, v[17:18]
.LBB0_19:
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v11, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, 0, v11
	s_and_b32 s2, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_21
; %bb.20:
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 3, v[11:12]
	v_mov_b32_e32 v6, v12
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s2, s8, v18
	v_add_co_ci_u32_e64 v19, s2, s9, v19, s2
	global_load_b64 v[18:19], v[18:19], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s2, v18, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s2, v19, v6, s2
	v_add_co_u32 v5, s2, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s2, -1, v6, s2
	flat_load_b32 v16, v[5:6]
.LBB0_21:
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_25
; %bb.22:
	v_mov_b32_e32 v6, 0
	s_mov_b32 s13, exec_lo
	v_cmpx_lt_i32_e32 0, v9
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 3, v[7:8]
	v_mov_b32_e32 v10, v8
	v_lshlrev_b64 v[20:21], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s2, s8, v18
	v_add_co_ci_u32_e64 v19, s2, s9, v19, s2
	global_load_b64 v[18:19], v[18:19], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s2, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s2, v19, v21, s2
	v_add_co_u32 v18, s2, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s2, -1, v6, s2
	flat_load_b32 v6, v[18:19]
.LBB0_24:                               ; %Flow281
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_25:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_lt_i32_e64 s2, 0, v9
	s_and_b32 s13, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s14, s13
	s_cbranch_execz .LBB0_27
; %bb.26:
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 3, v[11:12]
	v_mov_b32_e32 v10, v12
	v_lshlrev_b64 v[20:21], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s3, s8, v18
	v_add_co_ci_u32_e64 v19, s3, s9, v19, s3
	global_load_b64 v[18:19], v[18:19], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s3, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v5, s3, v19, v21, s3
	v_add_co_u32 v18, s3, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s3, -1, v5, s3
	flat_load_b32 v5, v[18:19]
.LBB0_27:                               ; %_Z13rectanglesSumPPiiiii.exit171
	s_or_b32 exec_lo, exec_lo, s14
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v19, 0
	s_and_b32 s3, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s14, s3
	s_cbranch_execz .LBB0_29
; %bb.28:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 3, v[1:2]
	v_mov_b32_e32 v10, v2
	v_lshlrev_b64 v[21:22], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v19, s3, s8, v19
	v_add_co_ci_u32_e64 v20, s3, s9, v20, s3
	global_load_b64 v[19:20], v[19:20], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s3, v19, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v8, s3, v20, v22, s3
	v_add_co_u32 v19, s3, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v20, s3, -1, v8, s3
	flat_load_b32 v19, v[19:20]
.LBB0_29:
	s_or_b32 exec_lo, exec_lo, s14
	s_and_b32 s3, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s14, s3
	s_cbranch_execz .LBB0_31
; %bb.30:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 3, v[7:8]
	v_mov_b32_e32 v10, v8
	v_lshlrev_b64 v[22:23], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v20, s2, s8, v20
	v_add_co_ci_u32_e64 v21, s2, s9, v21, s2
	global_load_b64 v[20:21], v[20:21], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s2, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v8, s2, v21, v23, s2
	v_add_co_u32 v20, s2, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v21, s2, -1, v8, s2
	flat_load_b32 v18, v[20:21]
.LBB0_31:
	s_or_b32 exec_lo, exec_lo, s14
	v_mov_b32_e32 v20, 0
	v_add_nc_u32_e32 v0, v9, v0
	v_mov_b32_e32 v2, 0
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_35
; %bb.32:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_34
; %bb.33:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[21:22], 3, v[1:2]
	v_mov_b32_e32 v1, v2
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v21, s0, s8, v21
	v_add_co_ci_u32_e64 v22, s0, s9, v22, s0
	global_load_b64 v[21:22], v[21:22], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v21, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s0, v22, v2, s0
	v_add_co_u32 v1, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, -1, v2, s0
	flat_load_b32 v2, v[1:2]
.LBB0_34:                               ; %Flow280
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_35:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_39
; %bb.36:
	v_mov_b32_e32 v20, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_38
; %bb.37:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 3, v[7:8]
	v_mov_b32_e32 v1, v8
	v_lshlrev_b64 v[22:23], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v20, s0, s8, v20
	v_add_co_ci_u32_e64 v21, s0, s9, v21, s0
	global_load_b64 v[20:21], v[20:21], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v8, s0, v21, v23, s0
	v_add_co_u32 v20, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v21, s0, -1, v8, s0
	flat_load_b32 v20, v[20:21]
.LBB0_38:                               ; %Flow279
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_39:                               ; %_Z13rectanglesSumPPiiiii.exit174
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, 0
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_41
; %bb.40:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], 3, v[7:8]
	v_mov_b32_e32 v10, v8
	v_lshlrev_b64 v[24:25], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v22, s0, s8, v22
	v_add_co_ci_u32_e64 v23, s0, s9, v23, s0
	global_load_b64 v[22:23], v[22:23], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v22, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v8, s0, v23, v25, s0
	v_add_co_u32 v22, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v23, s0, -1, v8, s0
	flat_load_b32 v22, v[22:23]
.LBB0_41:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s13
	s_cbranch_execz .LBB0_43
; %bb.42:
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 3, v[11:12]
	v_mov_b32_e32 v10, v12
	v_lshlrev_b64 v[8:9], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v23, s0, s8, v23
	v_add_co_ci_u32_e64 v24, s0, s9, v24, s0
	global_load_b64 v[23:24], v[23:24], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v23, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v9, s0, v24, v9, s0
	v_add_co_u32 v8, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, -1, v9, s0
	flat_load_b32 v21, v[8:9]
.LBB0_43:
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, 0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_47
; %bb.44:
	v_mov_b32_e32 v8, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_46
; %bb.45:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 3, v[7:8]
	v_mov_b32_e32 v1, v8
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v23, vcc_lo, s8, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo
	global_load_b64 v[23:24], v[23:24], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v23, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v24, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, -4, v1
	v_add_co_ci_u32_e32 v8, vcc_lo, -1, v8, vcc_lo
	flat_load_b32 v8, v[7:8]
.LBB0_46:                               ; %Flow278
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_47:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_51
; %bb.48:
	v_mov_b32_e32 v9, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_50
; %bb.49:
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 3, v[11:12]
	v_mov_b32_e32 v1, v12
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	global_load_b64 v[9:10], v[9:10], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v9, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	flat_load_b32 v9, v[0:1]
.LBB0_50:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_51:                               ; %_Z13rectanglesSumPPiiiii.exit177
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v13, v14
	v_add3_u32 v1, v3, v15, v17
	s_mov_b32 s0, exec_lo
	v_sub_nc_u32_e32 v0, v0, v1
	v_add_nc_u32_e32 v1, v5, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v16, v6
	v_sub_nc_u32_e32 v0, v0, v1
	v_add3_u32 v1, v20, v21, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v18
	v_add3_u32 v0, v0, v2, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v1
	v_add_nc_u32_e32 v6, v0, v9
.LBB0_52:                               ; %Flow305
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s0, exec_lo
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr7
.LBB0_53:                               ; %Flow304
	s_and_not1_saveexec_b32 s10, s10
	s_cbranch_execz .LBB0_89
; %bb.54:
	v_cmp_lt_i32_e64 s0, 0, v1
	v_cmp_lt_i32_e64 s1, 0, v5
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v10, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, s0, s1
	s_and_saveexec_b32 s2, s11
	s_cbranch_execz .LBB0_56
; %bb.55:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[12:13], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v10, v12
	v_add_co_ci_u32_e32 v2, vcc_lo, v11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, -1, v2, vcc_lo
	flat_load_b32 v10, v[10:11]
.LBB0_56:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v7, v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0, v7
	s_and_b32 s1, s1, vcc_lo
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_58
; %bb.57:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[11:12], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s8, v2
	v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
	global_load_b64 v[2:3], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s1, v2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s1, v3, v12, s1
	v_add_co_u32 v2, s1, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s1, -1, v3, s1
	flat_load_b32 v3, v[2:3]
.LBB0_58:
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_hi_i32 v0, 0x55555556, v9
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 31, v0
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v0, v5
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_62
; %bb.59:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s11, exec_lo
	v_cmpx_lt_i32_e32 0, v5
	s_cbranch_execz .LBB0_61
; %bb.60:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[13:14], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s1, s8, v11
	v_add_co_ci_u32_e64 v12, s1, s9, v12, s1
	global_load_b64 v[11:12], v[11:12], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v12, v14, s1
	v_add_co_u32 v11, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s1, -1, v6, s1
	flat_load_b32 v11, v[11:12]
.LBB0_61:                               ; %Flow288
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_62:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_lt_i32_e64 s1, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, vcc_lo, s1
	s_and_saveexec_b32 s13, s11
	s_cbranch_execz .LBB0_64
; %bb.63:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s2, s8, v12
	v_add_co_ci_u32_e64 v13, s2, s9, v13, s2
	global_load_b64 v[12:13], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s2, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s2, v13, v9, s2
	v_add_co_u32 v8, s2, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s2, -1, v6, s2
	flat_load_b32 v9, v[8:9]
.LBB0_64:                               ; %_Z13rectanglesSumPPiiiii.exit159
	s_or_b32 exec_lo, exec_lo, s13
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 0
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_66
; %bb.65:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[15:16], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s1, s8, v13
	v_add_co_ci_u32_e64 v14, s1, s9, v14, s1
	global_load_b64 v[13:14], v[13:14], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v14, v16, s1
	v_add_co_u32 v13, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v14, s1, -1, v6, s1
	flat_load_b32 v13, v[13:14]
.LBB0_66:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s11
	s_cbranch_execz .LBB0_68
; %bb.67:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[16:17], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s1, s8, v14
	v_add_co_ci_u32_e64 v15, s1, s9, v15, s1
	global_load_b64 v[14:15], v[14:15], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v15, v17, s1
	v_add_co_u32 v14, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v15, s1, -1, v6, s1
	flat_load_b32 v12, v[14:15]
.LBB0_68:
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v14, 0 :: v_dual_add_nc_u32 v5, v5, v0
	v_mov_b32_e32 v15, 0
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_72
; %bb.69:
	v_mov_b32_e32 v15, 0
	s_mov_b32 s11, exec_lo
	v_cmpx_lt_i32_e32 0, v5
	s_cbranch_execz .LBB0_71
; %bb.70:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[17:18], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s1, s8, v15
	v_add_co_ci_u32_e64 v16, s1, s9, v16, s1
	global_load_b64 v[15:16], v[15:16], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v16, v18, s1
	v_add_co_u32 v15, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s1, -1, v6, s1
	flat_load_b32 v15, v[15:16]
.LBB0_71:                               ; %Flow287
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_72:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_76
; %bb.73:
	v_mov_b32_e32 v14, 0
	s_mov_b32 s11, exec_lo
	v_cmpx_lt_i32_e32 0, v5
	s_cbranch_execz .LBB0_75
; %bb.74:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[18:19], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v16, s1, s8, v16
	v_add_co_ci_u32_e64 v17, s1, s9, v17, s1
	global_load_b64 v[16:17], v[16:17], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v17, v19, s1
	v_add_co_u32 v16, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v17, s1, -1, v6, s1
	flat_load_b32 v14, v[16:17]
.LBB0_75:                               ; %Flow286
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_76:                               ; %_Z13rectanglesSumPPiiiii.exit162
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_lt_i32_e64 s1, 0, v5
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v16, 0
	s_and_b32 s2, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s11, s2
	s_cbranch_execz .LBB0_78
; %bb.77:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[20:21], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s2, s8, v18
	v_add_co_ci_u32_e64 v19, s2, s9, v19, s2
	global_load_b64 v[18:19], v[18:19], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s2, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s2, v19, v21, s2
	v_add_co_u32 v18, s2, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s2, -1, v6, s2
	flat_load_b32 v16, v[18:19]
.LBB0_78:
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v6, 0
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_80
; %bb.79:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[20:21], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s1, s8, v18
	v_add_co_ci_u32_e64 v19, s1, s9, v19, s1
	global_load_b64 v[18:19], v[18:19], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v19, v21, s1
	v_add_co_u32 v18, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s1, -1, v6, s1
	flat_load_b32 v6, v[18:19]
.LBB0_80:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v0, v5, v0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_84
; %bb.81:
	v_mov_b32_e32 v17, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_83
; %bb.82:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 3, v[1:2]
	v_mov_b32_e32 v1, v2
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s0, s8, v17
	v_add_co_ci_u32_e64 v18, s0, s9, v18, s0
	global_load_b64 v[17:18], v[17:18], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s0, v18, v2, s0
	v_add_co_u32 v1, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, -1, v2, s0
	flat_load_b32 v17, v[1:2]
.LBB0_83:                               ; %Flow285
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_84:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_88
; %bb.85:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_87
; %bb.86:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[7:8]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b64 v[18:19], v[1:2], off offset:-8
	v_mov_b32_e32 v1, v8
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v18, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v19, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	flat_load_b32 v1, v[0:1]
.LBB0_87:                               ; %Flow284
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_88:                               ; %_Z13rectanglesSumPPiiiii.exit165
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v10, v9
	v_add3_u32 v2, v3, v11, v13
	s_or_b32 s3, s3, exec_lo
	v_sub_nc_u32_e32 v0, v0, v2
	v_add3_u32 v2, v14, v6, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v12
	v_add3_u32 v0, v0, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v2
	v_add_nc_u32_e32 v6, v0, v1
.LBB0_89:                               ; %Flow306
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr7
.LBB0_90:                               ; %Flow303
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_114
; %bb.91:
	v_cmp_lt_i32_e64 s0, 0, v1
	v_cmp_lt_i32_e64 s1, 0, v5
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v10, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, s0, s1
	s_and_saveexec_b32 s2, s10
	s_cbranch_execz .LBB0_93
; %bb.92:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[12:13], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v10, v12
	v_add_co_ci_u32_e32 v2, vcc_lo, v11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, -1, v2, vcc_lo
	flat_load_b32 v10, v[10:11]
.LBB0_93:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v7, v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0, v7
	s_and_b32 s1, s1, vcc_lo
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_95
; %bb.94:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[11:12], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s8, v2
	v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
	global_load_b64 v[2:3], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s1, v2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s1, v3, v12, s1
	v_add_co_u32 v2, s1, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s1, -1, v3, s1
	flat_load_b32 v3, v[2:3]
.LBB0_95:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshrrev_b32_e32 v0, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v0, v9, v0
	v_mov_b32_e32 v9, 0
	v_ashrrev_i32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v0, v5
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_99
; %bb.96:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e32 0, v5
	s_cbranch_execz .LBB0_98
; %bb.97:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[13:14], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s1, s8, v11
	v_add_co_ci_u32_e64 v12, s1, s9, v12, s1
	global_load_b64 v[11:12], v[11:12], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v12, v14, s1
	v_add_co_u32 v11, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s1, -1, v6, s1
	flat_load_b32 v11, v[11:12]
.LBB0_98:                               ; %Flow291
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_99:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_lt_i32_e64 s1, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, vcc_lo, s1
	s_and_saveexec_b32 s11, s10
	s_cbranch_execz .LBB0_101
; %bb.100:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s2, s8, v12
	v_add_co_ci_u32_e64 v13, s2, s9, v13, s2
	global_load_b64 v[12:13], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s2, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s2, v13, v9, s2
	v_add_co_u32 v8, s2, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s2, -1, v6, s2
	flat_load_b32 v9, v[8:9]
.LBB0_101:                              ; %_Z13rectanglesSumPPiiiii.exit153
	s_or_b32 exec_lo, exec_lo, s11
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 0
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_103
; %bb.102:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[15:16], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s1, s8, v13
	v_add_co_ci_u32_e64 v14, s1, s9, v14, s1
	global_load_b64 v[13:14], v[13:14], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v14, v16, s1
	v_add_co_u32 v13, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v14, s1, -1, v6, s1
	flat_load_b32 v13, v[13:14]
.LBB0_103:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s10
	s_cbranch_execz .LBB0_105
; %bb.104:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[16:17], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s1, s8, v14
	v_add_co_ci_u32_e64 v15, s1, s9, v15, s1
	global_load_b64 v[14:15], v[14:15], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s1, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, v15, v17, s1
	v_add_co_u32 v14, s1, -4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v15, s1, -1, v6, s1
	flat_load_b32 v12, v[14:15]
.LBB0_105:
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v6, 0
	v_add_nc_u32_e32 v0, v5, v0
	v_mov_b32_e32 v2, 0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_109
; %bb.106:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_108
; %bb.107:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[1:2]
	v_mov_b32_e32 v1, v2
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s0, s8, v14
	v_add_co_ci_u32_e64 v15, s0, s9, v15, s0
	global_load_b64 v[14:15], v[14:15], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s0, v15, v2, s0
	v_add_co_u32 v1, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, -1, v2, s0
	flat_load_b32 v2, v[1:2]
.LBB0_108:                              ; %Flow290
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_109:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_113
; %bb.110:
	v_mov_b32_e32 v6, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_112
; %bb.111:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[7:8]
	v_mov_b32_e32 v1, v8
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v5, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	flat_load_b32 v6, v[0:1]
.LBB0_112:                              ; %Flow289
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_113:                              ; %_Z13rectanglesSumPPiiiii.exit156
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v10, v9
	v_add3_u32 v1, v3, v11, v13
	s_or_b32 s3, s3, exec_lo
	v_add3_u32 v0, v0, v12, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v1, v0
	v_add_nc_u32_e32 v6, v0, v6
.LBB0_114:                              ; %Flow307
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr1
.LBB0_115:                              ; %Flow302
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_183
; %bb.116:                              ; %NodeBlock
	s_mov_b32 s10, s3
                                        ; implicit-def: $vgpr6
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 1, v0
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB0_154
; %bb.117:
	v_cmp_lt_i32_e64 s1, 0, v1
	v_cmp_lt_i32_e32 vcc_lo, 0, v5
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s1, vcc_lo
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_119
; %bb.118:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s0, s8, v11
	v_add_co_ci_u32_e64 v12, s0, s9, v12, s0
	global_load_b64 v[11:12], v[11:12], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s0, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s0, v12, v3, s0
	v_add_co_u32 v2, s0, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, -1, v3, s0
	flat_load_b32 v11, v[2:3]
.LBB0_119:
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_hi_i32 v0, 0x55555556, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 31, v0
	v_add_nc_u32_e32 v14, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v14, v1
	v_cmp_lt_i32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, vcc_lo, s0
	s_and_saveexec_b32 s11, s10
	s_cbranch_execz .LBB0_121
; %bb.120:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[12:13], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s2, s8, v2
	v_add_co_ci_u32_e64 v3, s2, s9, v3, s2
	global_load_b64 v[2:3], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s2, v2, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s2, v3, v13, s2
	v_add_co_u32 v2, s2, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s2, -1, v3, s2
	flat_load_b32 v10, v[2:3]
.LBB0_121:
	s_or_b32 exec_lo, exec_lo, s11
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_125
; %bb.122:
	v_add_nc_u32_e32 v0, v9, v5
	v_mov_b32_e32 v12, 0
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_124
; %bb.123:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 3, v[1:2]
	v_mov_b32_e32 v1, v2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s1, s8, v15
	v_add_co_ci_u32_e64 v16, s1, s9, v16, s1
	global_load_b64 v[15:16], v[15:16], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s1, v15, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v1, s1, v16, v1, s1
	v_add_co_u32 v0, s1, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s1, -1, v1, s1
	flat_load_b32 v12, v[0:1]
.LBB0_124:                              ; %Flow297
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_125:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_129
; %bb.126:
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v0, v9, v5
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_128
; %bb.127:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[7:8]
	v_add_co_u32 v1, s1, s8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s1, s9, v2, s1
	global_load_b64 v[2:3], v[1:2], off offset:-8
	v_mov_b32_e32 v1, v8
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s1, v2, v0
	v_add_co_ci_u32_e64 v1, s1, v3, v1, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s1, -4, v0
	v_add_co_ci_u32_e64 v1, s1, -1, v1, s1
	flat_load_b32 v13, v[0:1]
.LBB0_128:                              ; %Flow296
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_129:                              ; %_Z13rectanglesSumPPiiiii.exit144
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v16, 0
	s_and_saveexec_b32 s2, s10
	s_cbranch_execz .LBB0_131
; %bb.130:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s1, s8, v0
	v_add_co_ci_u32_e64 v1, s1, s9, v1, s1
	global_load_b64 v[0:1], v[0:1], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s1, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v1, s1, v1, v3, s1
	v_add_co_u32 v0, s1, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s1, -1, v1, s1
	flat_load_b32 v16, v[0:1]
.LBB0_131:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v0, v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, 0, v0
	s_and_b32 s10, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s11, s10
	s_cbranch_execz .LBB0_133
; %bb.132:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	v_mov_b32_e32 v6, v1
	v_lshlrev_b64 v[17:18], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s2, s8, v2
	v_add_co_ci_u32_e64 v3, s2, s9, v3, s2
	global_load_b64 v[2:3], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s2, v2, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s2, v3, v18, s2
	v_add_co_u32 v1, s2, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s2, -1, v2, s2
	flat_load_b32 v15, v[1:2]
.LBB0_133:
	s_or_b32 exec_lo, exec_lo, s11
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v8, 0
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_137
; %bb.134:
	v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v1, v9, v5
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v1
	s_cbranch_execz .LBB0_136
; %bb.135:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_add_co_u32 v2, s0, s8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	global_load_b64 v[6:7], v[2:3], off offset:-8
	v_mov_b32_e32 v2, v8
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s0, v6, v1
	v_add_co_ci_u32_e64 v2, s0, v7, v2, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s0, -4, v1
	v_add_co_ci_u32_e64 v2, s0, -1, v2, s0
	flat_load_b32 v8, v[1:2]
.LBB0_136:                              ; %Flow295
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_137:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_141
; %bb.138:
	v_dual_mov_b32 v17, 0 :: v_dual_add_nc_u32 v2, v9, v5
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v2
	s_cbranch_execz .LBB0_140
; %bb.139:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[0:1]
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s8, v6
	v_add_co_ci_u32_e64 v7, s0, s9, v7, s0
	global_load_b64 v[6:7], v[6:7], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s0, v7, v2, s0
	v_add_co_u32 v1, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, -1, v2, s0
	flat_load_b32 v17, v[1:2]
.LBB0_140:                              ; %Flow294
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_141:                              ; %_Z13rectanglesSumPPiiiii.exit147
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v19, 0
	s_and_saveexec_b32 s2, s10
	s_cbranch_execz .LBB0_143
; %bb.142:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	v_mov_b32_e32 v6, v1
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s8, v2
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	global_load_b64 v[2:3], v[2:3], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s0, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s0, v3, v7, s0
	v_add_co_u32 v1, s0, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, -1, v2, s0
	flat_load_b32 v19, v[1:2]
.LBB0_143:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v2, v0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s0, 0, v2
	s_and_b32 s10, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s10
	s_cbranch_execz .LBB0_145
; %bb.144:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	v_add_co_u32 v6, vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b64 v[20:21], v[6:7], off offset:-8
	v_mov_b32_e32 v6, v3
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v20, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, v21, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, -4, v1
	v_add_co_ci_u32_e32 v7, vcc_lo, -1, v3, vcc_lo
	flat_load_b32 v18, v[6:7]
.LBB0_145:
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v7, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_149
; %bb.146:
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, v9, v5
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v6
	s_cbranch_execz .LBB0_148
; %bb.147:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 3, v[0:1]
	v_mov_b32_e32 v7, v1
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, s8, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s9, v21, vcc_lo
	global_load_b64 v[20:21], v[20:21], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v21, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	flat_load_b32 v7, v[0:1]
.LBB0_148:                              ; %Flow293
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_149:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_153
; %bb.150:
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v0, v9, v5
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_152
; %bb.151:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b64 v[5:6], v[1:2], off offset:-8
	v_mov_b32_e32 v1, v3
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	flat_load_b32 v3, v[0:1]
.LBB0_152:                              ; %Flow292
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_153:                              ; %_Z13rectanglesSumPPiiiii.exit150
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v11, v13
	v_add3_u32 v1, v10, v12, v16
	s_or_b32 s10, s3, exec_lo
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr9
	v_sub_nc_u32_e32 v0, v0, v1
	v_add3_u32 v1, v17, v18, v7
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v15
	v_add3_u32 v0, v0, v8, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v1
	v_add_nc_u32_e32 v6, v0, v3
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
                                        ; implicit-def: $vgpr1
.LBB0_154:                              ; %Flow309
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_182
; %bb.155:                              ; %LeafBlock
	s_mov_b32 s0, s10
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr6
	v_cmpx_eq_u32_e32 1, v0
	s_cbranch_execz .LBB0_181
; %bb.156:
	v_cmp_lt_i32_e64 s1, 0, v1
	v_cmp_lt_i32_e32 vcc_lo, 0, v5
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s1, vcc_lo
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_158
; %bb.157:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[1:2]
	v_mov_b32_e32 v6, v2
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s0, s8, v11
	v_add_co_ci_u32_e64 v12, s0, s9, v12, s0
	global_load_b64 v[11:12], v[11:12], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s0, v11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s0, v12, v3, s0
	v_add_co_u32 v2, s0, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, -1, v3, s0
	flat_load_b32 v11, v[2:3]
.LBB0_158:
	s_or_b32 exec_lo, exec_lo, s2
	v_lshrrev_b32_e32 v0, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v7, v0
	v_ashrrev_i32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v3, v1
	v_cmp_lt_i32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s13, vcc_lo, s0
	s_and_saveexec_b32 s14, s13
	s_cbranch_execz .LBB0_160
; %bb.159:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[14:15], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s2, s8, v12
	v_add_co_ci_u32_e64 v13, s2, s9, v13, s2
	global_load_b64 v[12:13], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, s2, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s2, v13, v15, s2
	v_add_co_u32 v12, s2, -4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s2, -1, v2, s2
	flat_load_b32 v10, v[12:13]
.LBB0_160:
	s_or_b32 exec_lo, exec_lo, s14
	v_mov_b32_e32 v12, 0
	v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v0, v9, v5
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_164
; %bb.161:
	v_mov_b32_e32 v9, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_163
; %bb.162:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[1:2]
	v_mov_b32_e32 v1, v2
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, s8, v8
	v_add_co_ci_u32_e64 v9, s1, s9, v9, s1
	global_load_b64 v[8:9], v[8:9], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s1, v8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s1, v9, v2, s1
	v_add_co_u32 v1, s1, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s1, -1, v2, s1
	flat_load_b32 v9, v[1:2]
.LBB0_163:                              ; %Flow301
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_164:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_168
; %bb.165:
	v_mov_b32_e32 v12, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_167
; %bb.166:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[7:8]
	v_add_co_u32 v1, s1, s8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s1, s9, v2, s1
	global_load_b64 v[12:13], v[1:2], off offset:-8
	v_mov_b32_e32 v1, v8
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s1, v12, v1
	v_add_co_ci_u32_e64 v2, s1, v13, v2, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s1, -4, v1
	v_add_co_ci_u32_e64 v2, s1, -1, v2, s1
	flat_load_b32 v12, v[1:2]
.LBB0_167:                              ; %Flow300
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_168:                              ; %_Z13rectanglesSumPPiiiii.exit
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, 0
	s_and_saveexec_b32 s2, s13
	s_cbranch_execz .LBB0_170
; %bb.169:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[7:8]
	v_mov_b32_e32 v6, v8
	v_lshlrev_b64 v[14:15], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s1, s8, v1
	v_add_co_ci_u32_e64 v2, s1, s9, v2, s1
	global_load_b64 v[1:2], v[1:2], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, s1, v1, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s1, v2, v15, s1
	v_add_co_u32 v1, s1, -4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s1, -1, v2, s1
	flat_load_b32 v14, v[1:2]
.LBB0_170:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v2, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, 0, v2
	s_and_b32 s13, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s13
	s_cbranch_execz .LBB0_172
; %bb.171:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 3, v[2:3]
	v_mov_b32_e32 v6, v3
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s8, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
	global_load_b64 v[15:16], v[15:16], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v15, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, v16, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, -4, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, -1, v3, vcc_lo
	flat_load_b32 v13, v[5:6]
.LBB0_172:
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v5, 0
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_176
; %bb.173:
	v_mov_b32_e32 v5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_175
; %bb.174:
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[7:8]
	v_mov_b32_e32 v1, v8
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, -4, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, -1, v6, vcc_lo
	flat_load_b32 v5, v[5:6]
.LBB0_175:                              ; %Flow299
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_176:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_180
; %bb.177:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_179
; %bb.178:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off offset:-8
	v_mov_b32_e32 v1, v3
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, -4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	flat_load_b32 v3, v[0:1]
.LBB0_179:                              ; %Flow298
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_180:                              ; %_Z13rectanglesSumPPiiiii.exit141
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v11, v12
	v_add3_u32 v1, v10, v9, v14
	s_or_b32 s0, s10, exec_lo
	v_sub_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v13, v5
	v_sub_nc_u32_e32 v6, v0, v3
.LBB0_181:                              ; %Flow311
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s10, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s10, s1, s0
.LBB0_182:                              ; %Flow310
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s3, exec_lo
	s_and_b32 s1, s10, exec_lo
	s_or_b32 s3, s0, s1
.LBB0_183:                              ; %Flow308
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_185
; %bb.184:                              ; %.sink.split
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_185:                              ; %Flow313
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel computeWindowFeatures
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	computeWindowFeatures, .Lfunc_end0-computeWindowFeatures
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8828
; NumSgprs: 18
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           computeWindowFeatures
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         computeWindowFeatures.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
