
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>


__global__ void sim_cell_onelife(int* d_cell, int m, int n) {

	 __shared__ int s_arr[100];
	 int neighbor = 0;  
	 
	 int r = threadIdx.x % m;
	 int c = threadIdx.x / m;
	 int cell = d_cell[r + c * m];
	 int row = r - 1; 
	 int col = c - 1; 


	 s_arr[r + c * m] = d_cell[r + c * m];
	 __syncthreads(); 

	 for (int i = row; i < row + 3; i++) {

	 	for (int j = col; j < col + 3; j++) {

	 		if (i >= 0 && j >= 0) {

	 			if (i < m && j < n) {

	 				if (i != r || j != c) {

	 					if (s_arr[i + j * m] == 1) {

	 						neighbor += 1; 

	 					}
	 				}
	 			}
	 		}
	 	}
	 }

	 if (cell == 1 && neighbor <= 1) {
	 	cell = 0; 
	 } else if (cell == 0 && neighbor == 2) {
	 	cell = 1;
	 } else if (cell == 0 && neighbor == 3){ 
	 	cell = 1; 
	 } else if (cell == 1 && neighbor >= 4) {
	 	cell = 0; 
	 }

	__syncthreads(); 

	d_cell[r + c * m] = cell;

}


int main(void) {
	
	int *cell; 
	int *d_cell; 
	int t_num; 
	int size; 
	int m, n, k; 

	struct timeval gpu_start, gpu_end;

	// m x n
	printf("Enter M: \n");
	scanf("%d", &m);

	printf("Enter N: \n");
	scanf("%d", &n);

	printf("Enter K: \n");
	scanf("%d", &k);

	t_num = n * m; 
	size = t_num * sizeof(int);

	cell = (int *)malloc(size);

	printf("-------BEFORE LIFE CYCLE--------\n");

	for (int i = 0; i < m; ++i) {
		for (int j = 0; j < n; ++j) {
			cell[i + j * m] = rand() % (1 - 0 + 1) + 0; 
		}
	}

	for (int i = 0; i < m; ++i) {
		for (int j = 0; j < n; ++j) {
			printf("%d ", cell[i + j * m]);
		}
		printf("\n");
	}		

	printf("-------AFTER %d LIFE CYCLES-------\n", k);
	cudaMalloc((void **)&d_cell, size);
	
	cudaMemcpy(d_cell, cell, size, cudaMemcpyHostToDevice);

	gettimeofday(&gpu_start, NULL);
	for (int i = 0; i < k; i++) {
		sim_cell_onelife<<<1,t_num>>>(d_cell, m, n);
	}
	gettimeofday(&gpu_end, NULL);

	memset(cell, 0, size);

	cudaMemcpy(cell, d_cell, size, cudaMemcpyDeviceToHost);

	for (int i = 0; i < m; ++i) {
		for (int j = 0; j < n; ++j) {
			printf("%d ", cell[i + j * m]);
		}
		printf("\n");
	}	

	free(cell);
	cudaFree(d_cell);
	printf("GPU run time: %ld\n",(gpu_end.tv_usec - gpu_start.tv_usec));

}
	.file	"tmpxft_0020c506_00000000-6_cell_sim.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z16sim_cell_onelifePiiiPiii
	.type	_Z38__device_stub__Z16sim_cell_onelifePiiiPiii, @function
_Z38__device_stub__Z16sim_cell_onelifePiiiPiii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z16sim_cell_onelifePiii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z38__device_stub__Z16sim_cell_onelifePiiiPiii, .-_Z38__device_stub__Z16sim_cell_onelifePiiiPiii
	.globl	_Z16sim_cell_onelifePiii
	.type	_Z16sim_cell_onelifePiii, @function
_Z16sim_cell_onelifePiii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z16sim_cell_onelifePiiiPiii
	.cfi_endproc
.LFE2053:
	.size	_Z16sim_cell_onelifePiii, .-_Z16sim_cell_onelifePiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter M: \n"
.LC1:
	.string	"%d"
.LC2:
	.string	"Enter N: \n"
.LC3:
	.string	"Enter K: \n"
.LC4:
	.string	"-------BEFORE LIFE CYCLE--------\n"
.LC5:
	.string	"%d "
.LC6:
	.string	"\n"
.LC7:
	.string	"-------AFTER %d LIFE CYCLES-------\n"
.LC8:
	.string	"GPU run time: %ld\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$2, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	.LC1(%rip), %rbx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	leaq	4(%rsp), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	leaq	8(%rsp), %rsi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	12(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	8(%rsp), %r12d
	imull	4(%rsp), %r12d
	leal	0(,%r12,4), %ebp
	movslq	%ebp, %rbp
	movq	%rbp, %rdi
	call	malloc@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L9:
	cmpl	%r14d, 4(%rsp)
	jle	.L26
	xorl	%r15d, %r15d
.L11:
	cmpl	%r15d, 8(%rsp)
	jle	.L27
	call	rand@PLT
	movl	4(%rsp), %ecx
	cltd
	idivl	%r13d
	imull	%r15d, %ecx
	incl	%r15d
	addl	%r14d, %ecx
	movslq	%ecx, %rcx
	movl	%edx, (%rbx,%rcx,4)
	jmp	.L11
.L27:
	incl	%r14d
	jmp	.L9
.L26:
	xorl	%r14d, %r14d
	leaq	.LC5(%rip), %r13
.L12:
	cmpl	%r14d, 4(%rsp)
	jle	.L28
	xorl	%r15d, %r15d
.L14:
	cmpl	%r15d, 8(%rsp)
	jle	.L29
	movl	4(%rsp), %eax
	movq	%r13, %rsi
	movl	$2, %edi
	imull	%r15d, %eax
	incl	%r15d
	addl	%r14d, %eax
	cltq
	movl	(%rbx,%rax,4), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L14
.L29:
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%r14d
	call	__printf_chk@PLT
	jmp	.L12
.L28:
	movl	12(%rsp), %edx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	xorl	%r13d, %r13d
	movabsq	$4294967297, %r14
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
.L15:
	cmpl	%r13d, 12(%rsp)
	jle	.L30
	movq	%r14, 60(%rsp)
	movl	64(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%r12d, 56(%rsp)
	movq	56(%rsp), %rdx
	movq	%r14, %rdi
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	movq	16(%rsp), %rdi
	call	_Z38__device_stub__Z16sim_cell_onelifePiiiPiii
.L16:
	incl	%r13d
	jmp	.L15
.L30:
	leaq	56(%rsp), %rdi
	xorl	%esi, %esi
	leaq	.LC5(%rip), %r12
	call	gettimeofday@PLT
	movq	%rbp, %rcx
	movq	%rbp, %rdx
	xorl	%esi, %esi
	movq	%rbx, %rdi
	call	__memset_chk@PLT
	movq	16(%rsp), %rsi
	movq	%rbp, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	xorl	%ebp, %ebp
	call	cudaMemcpy@PLT
.L18:
	cmpl	%ebp, 4(%rsp)
	jle	.L31
	xorl	%r13d, %r13d
.L20:
	cmpl	%r13d, 8(%rsp)
	jle	.L32
	movl	4(%rsp), %eax
	movq	%r12, %rsi
	movl	$2, %edi
	imull	%r13d, %eax
	incl	%r13d
	addl	%ebp, %eax
	cltq
	movl	(%rbx,%rax,4), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L20
.L32:
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%ebp
	call	__printf_chk@PLT
	jmp	.L18
.L31:
	movq	%rbx, %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdx
	xorl	%eax, %eax
	subq	48(%rsp), %rdx
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z16sim_cell_onelifePiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16sim_cell_onelifePiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:



#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>


__global__ void sim_cell_onelife(int* d_cell, int m, int n) {

	 __shared__ int s_arr[100];
	 int neighbor = 0;  
	 
	 int r = threadIdx.x % m;
	 int c = threadIdx.x / m;
	 int cell = d_cell[r + c * m];
	 int row = r - 1; 
	 int col = c - 1; 


	 s_arr[r + c * m] = d_cell[r + c * m];
	 __syncthreads(); 

	 for (int i = row; i < row + 3; i++) {

	 	for (int j = col; j < col + 3; j++) {

	 		if (i >= 0 && j >= 0) {

	 			if (i < m && j < n) {

	 				if (i != r || j != c) {

	 					if (s_arr[i + j * m] == 1) {

	 						neighbor += 1; 

	 					}
	 				}
	 			}
	 		}
	 	}
	 }

	 if (cell == 1 && neighbor <= 1) {
	 	cell = 0; 
	 } else if (cell == 0 && neighbor == 2) {
	 	cell = 1;
	 } else if (cell == 0 && neighbor == 3){ 
	 	cell = 1; 
	 } else if (cell == 1 && neighbor >= 4) {
	 	cell = 0; 
	 }

	__syncthreads(); 

	d_cell[r + c * m] = cell;

}


int main(void) {
	
	int *cell; 
	int *d_cell; 
	int t_num; 
	int size; 
	int m, n, k; 

	struct timeval gpu_start, gpu_end;

	// m x n
	printf("Enter M: \n");
	scanf("%d", &m);

	printf("Enter N: \n");
	scanf("%d", &n);

	printf("Enter K: \n");
	scanf("%d", &k);

	t_num = n * m; 
	size = t_num * sizeof(int);

	cell = (int *)malloc(size);

	printf("-------BEFORE LIFE CYCLE--------\n");

	for (int i = 0; i < m; ++i) {
		for (int j = 0; j < n; ++j) {
			cell[i + j * m] = rand() % (1 - 0 + 1) + 0; 
		}
	}

	for (int i = 0; i < m; ++i) {
		for (int j = 0; j < n; ++j) {
			printf("%d ", cell[i + j * m]);
		}
		printf("\n");
	}		

	printf("-------AFTER %d LIFE CYCLES-------\n", k);
	hipMalloc((void **)&d_cell, size);
	
	hipMemcpy(d_cell, cell, size, hipMemcpyHostToDevice);

	gettimeofday(&gpu_start, NULL);
	for (int i = 0; i < k; i++) {
		sim_cell_onelife<<<1,t_num>>>(d_cell, m, n);
	}
	gettimeofday(&gpu_end, NULL);

	memset(cell, 0, size);

	hipMemcpy(cell, d_cell, size, hipMemcpyDeviceToHost);

	for (int i = 0; i < m; ++i) {
		for (int j = 0; j < n; ++j) {
			printf("%d ", cell[i + j * m]);
		}
		printf("\n");
	}	

	free(cell);
	hipFree(d_cell);
	printf("GPU run time: %ld\n",(gpu_end.tv_usec - gpu_start.tv_usec));

}
	.text
	.file	"cell_sim.hip"
	.globl	_Z31__device_stub__sim_cell_onelifePiii # -- Begin function _Z31__device_stub__sim_cell_onelifePiii
	.type	_Z31__device_stub__sim_cell_onelifePiii,@function
_Z31__device_stub__sim_cell_onelifePiii: # @_Z31__device_stub__sim_cell_onelifePiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16sim_cell_onelifePiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__sim_cell_onelifePiii, .Lfunc_end0-_Z31__device_stub__sim_cell_onelifePiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%ebp, %ebp
	leaq	8(%rsp), %r15
	movl	$.L.str.1, %edi
	movq	%r15, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	leaq	4(%rsp), %rbx
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	leaq	12(%rsp), %rsi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%r15), %r12d
	imull	(%rbx), %r12d
	leal	(,%r12,4), %eax
	movslq	%eax, %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %rbx
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	(%r15), %ecx
	testl	%ecx, %ecx
	jle	.LBB1_12
# %bb.1:                                # %.preheader51.preheader
	movl	4(%rsp), %eax
.LBB1_2:                                # %.preheader51
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%eax, %eax
	jle	.LBB1_5
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_2 Depth=1
	xorl	%r15d, %r15d
.LBB1_4:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	andl	$-2, %ecx
	subl	%ecx, %eax
	movl	8(%rsp), %ecx
	movl	%ecx, %edx
	imull	%r15d, %edx
	addl	%ebp, %edx
	movslq	%edx, %rdx
	movl	%eax, (%rbx,%rdx,4)
	incl	%r15d
	movl	4(%rsp), %eax
	cmpl	%eax, %r15d
	jl	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incl	%ebp
	cmpl	%ecx, %ebp
	jl	.LBB1_2
# %bb.6:                                # %.preheader50
	testl	%ecx, %ecx
	jle	.LBB1_12
# %bb.7:                                # %.preheader49.preheader
	xorl	%ebp, %ebp
.LBB1_8:                                # %.preheader49
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_10 Depth 2
	cmpl	$0, 4(%rsp)
	jle	.LBB1_11
# %bb.9:                                # %.lr.ph55.preheader
                                        #   in Loop: Header=BB1_8 Depth=1
	xorl	%r15d, %r15d
.LBB1_10:                               # %.lr.ph55
                                        #   Parent Loop BB1_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	8(%rsp), %eax
	imull	%r15d, %eax
	addl	%ebp, %eax
	cltq
	movl	(%rbx,%rax,4), %esi
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	incl	%r15d
	cmpl	4(%rsp), %r15d
	jl	.LBB1_10
.LBB1_11:                               # %._crit_edge56
                                        #   in Loop: Header=BB1_8 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incl	%ebp
	cmpl	8(%rsp), %ebp
	jl	.LBB1_8
.LBB1_12:                               # %._crit_edge58
	movl	12(%rsp), %esi
	xorl	%r13d, %r13d
	movl	$.L.str.7, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cmpl	$0, 12(%rsp)
	jle	.LBB1_17
# %bb.13:                               # %.lr.ph61
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	%r12d, %r12d
	btsq	$32, %r12
	incq	%r15
.LBB1_14:                               # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_16
# %bb.15:                               #   in Loop: Header=BB1_14 Depth=1
	movq	16(%rsp), %rdi
	movl	8(%rsp), %esi
	movl	4(%rsp), %edx
	callq	_Z31__device_stub__sim_cell_onelifePiii
.LBB1_16:                               #   in Loop: Header=BB1_14 Depth=1
	incl	%r13d
	cmpl	12(%rsp), %r13d
	jl	.LBB1_14
.LBB1_17:                               # %._crit_edge62
	leaq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	memset@PLT
	movq	16(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, 8(%rsp)
	jle	.LBB1_23
# %bb.18:                               # %.preheader.preheader
	xorl	%ebp, %ebp
.LBB1_19:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_21 Depth 2
	cmpl	$0, 4(%rsp)
	jle	.LBB1_22
# %bb.20:                               # %.lr.ph64.preheader
                                        #   in Loop: Header=BB1_19 Depth=1
	xorl	%r14d, %r14d
.LBB1_21:                               # %.lr.ph64
                                        #   Parent Loop BB1_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	8(%rsp), %eax
	imull	%r14d, %eax
	addl	%ebp, %eax
	cltq
	movl	(%rbx,%rax,4), %esi
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	incl	%r14d
	cmpl	4(%rsp), %r14d
	jl	.LBB1_21
.LBB1_22:                               # %._crit_edge65
                                        #   in Loop: Header=BB1_19 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incl	%ebp
	cmpl	8(%rsp), %ebp
	jl	.LBB1_19
.LBB1_23:                               # %._crit_edge67
	movq	%rbx, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rsi
	subq	48(%rsp), %rsi
	movl	$.L.str.8, %edi
	xorl	%eax, %eax
	callq	printf
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16sim_cell_onelifePiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16sim_cell_onelifePiii,@object # @_Z16sim_cell_onelifePiii
	.section	.rodata,"a",@progbits
	.globl	_Z16sim_cell_onelifePiii
	.p2align	3, 0x0
_Z16sim_cell_onelifePiii:
	.quad	_Z31__device_stub__sim_cell_onelifePiii
	.size	_Z16sim_cell_onelifePiii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d "
	.size	.L.str.5, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"-------AFTER %d LIFE CYCLES-------\n"
	.size	.L.str.7, 36

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"GPU run time: %ld\n"
	.size	.L.str.8, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16sim_cell_onelifePiii"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Enter M: "
	.size	.Lstr, 10

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Enter N: "
	.size	.Lstr.1, 10

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Enter K: "
	.size	.Lstr.2, 10

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"-------BEFORE LIFE CYCLE--------"
	.size	.Lstr.3, 33

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__sim_cell_onelifePiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16sim_cell_onelifePiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16sim_cell_onelifePiii ; -- Begin function _Z16sim_cell_onelifePiii
	.globl	_Z16sim_cell_onelifePiii
	.p2align	8
	.type	_Z16sim_cell_onelifePiii,@function
_Z16sim_cell_onelifePiii:               ; @_Z16sim_cell_onelifePiii
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s4, 0, s2
	s_lshl_b32 s5, s2, 2
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_lshlrev_b32 v8, 2, v0
	global_load_b32 v2, v8, s[0:1]
	v_subrev_nc_u32_e32 v6, s5, v8
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, -4, v6
	v_mul_lo_u32 v3, s4, v1
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v1, v3
	v_add_nc_u32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_mul_lo_u32 v3, v1, s2
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v3
	v_cmp_le_u32_e32 vcc_lo, s2, v3
	v_subrev_nc_u32_e32 v5, s2, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v4, v1, v4
	v_mul_lo_u32 v1, v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v0, v1
	v_add_co_u32 v0, s0, s0, v8
	v_add_co_ci_u32_e64 v1, null, s1, 0, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v7, -1, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e64 s0, s2, v7
	v_cmp_eq_u32_e32 vcc_lo, v7, v5
	v_mov_b32_e32 v8, v6
	s_mov_b32 s7, -1
	s_xor_b32 s6, s0, -1
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v9, s7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v10, v9, v7
	v_cmp_le_i32_e64 s1, s3, v9
	v_cmp_gt_i32_e64 s0, 0, v10
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s0, s6, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_cmp_eq_u32 s7, 0
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	ds_load_b32 v9, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e64 s0, 1, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v8, s5, v8
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, 2
	s_cbranch_scc0 .LBB0_2
; %bb.5:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v8, 1, v7
	v_cmp_gt_i32_e32 vcc_lo, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v7, v8 :: v_dual_add_nc_u32 v6, 4, v6
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_1
; %bb.6:
	s_or_b32 exec_lo, exec_lo, s4
	v_cmp_ne_u32_e64 s0, 1, v2
	v_cmp_lt_i32_e64 s1, 1, v3
	v_cmp_eq_u32_e32 vcc_lo, 1, v2
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_and_saveexec_b32 s3, s0
; %bb.7:
	v_and_b32_e32 v4, -2, v3
	v_cmp_lt_i32_e64 s0, 3, v3
	v_cmp_eq_u32_e64 s1, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e64 s2, 2, v4
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v2, 0, s0
	s_and_b32 s0, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v4, v2, 1, s0
; %bb.8:
	s_or_b32 exec_lo, exec_lo, s3
	s_barrier
	buffer_gl0_inv
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16sim_cell_onelifePiii
		.amdhsa_group_segment_fixed_size 400
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16sim_cell_onelifePiii, .Lfunc_end0-_Z16sim_cell_onelifePiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 10
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 400 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 400
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16sim_cell_onelifePiii
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z16sim_cell_onelifePiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
