#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <time.h>

#define N 100
__global__ void mul(int a[][N], int b[][N], int c[][N]){
	int row = blockIdx.x*blockDim.x+threadIdx.x;
	int col = blockIdx.y*blockDim.y+threadIdx.y;

	if(row < N && col < N) {
		for(int i = 0; i < N; i++) {
			for(int j = 0; j < N; j++) {
				c[i][j] = 0;
				for(int k = 0; k < N; k++) {
					c[i][j] += a[i][k] * b[k][j];
				}
			}
		}
	}
}

int main(){
	int (*pa)[N], (*pb)[N], (*pc)[N];
	int a[N][N], b[N][N], c[N][N];

	srand((unsigned)time(NULL));	

	cudaEvent_t start, stop;

	cudaEventCreate(&start);
        cudaEventCreate(&stop);
        cudaEventRecord(start, 0);
	
	cudaMalloc((void**)&pa, (N*N) * sizeof(int));
	cudaMalloc((void**)&pb, (N*N) * sizeof(int));
	cudaMalloc((void**)&pc, (N*N) * sizeof(int));

	for(int i = 0 ; i<N ; i++){
		for(int j = 0 ; j<N ; j++) {
			a[i][j] = rand()%10 + 1;
			b[i][j] = rand()%10 + 1;
		}
	}
	
	cudaMemcpy(pa, a, (N*N) * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(pb, b, (N*N) * sizeof(int), cudaMemcpyHostToDevice);	
	
	dim3 threadsPerThreads(N,N);
	mul<<<1,threadsPerThreads>>>(pa, pb, pc);

	cudaMemcpy(c, pc, (N*N) * sizeof(int), cudaMemcpyDeviceToHost);

	printf("matrix multiplication per thread\n");


/*	for(int i = 0 ; i<N ; i++){
		for(int j = 0 ; j<N ; j++) {
			printf("%d ",c[i][j]);
		}
		printf("\n");
	}
*/
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);

	float elapsedTime;
	cudaEventElapsedTime(&elapsedTime, start, stop);

	cudaEventDestroy(start);
	cudaEventDestroy(stop);

	printf("Time to generate : %3.1f ms\n", elapsedTime);

	cudaFree(pa);
	cudaFree(pb);
	cudaFree(pc);

	return 0;

}

	.file	"tmpxft_003815db_00000000-6_matrixRandMul_Thread.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z3mulPA100_iS0_S0_PA100_iS0_S0_
	.type	_Z33__device_stub__Z3mulPA100_iS0_S0_PA100_iS0_S0_, @function
_Z33__device_stub__Z3mulPA100_iS0_S0_PA100_iS0_S0_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z3mulPA100_iS0_S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z33__device_stub__Z3mulPA100_iS0_S0_PA100_iS0_S0_, .-_Z33__device_stub__Z3mulPA100_iS0_S0_PA100_iS0_S0_
	.globl	_Z3mulPA100_iS0_S0_
	.type	_Z3mulPA100_iS0_S0_, @function
_Z3mulPA100_iS0_S0_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z3mulPA100_iS0_S0_PA100_iS0_S0_
	.cfi_endproc
.LFE2053:
	.size	_Z3mulPA100_iS0_S0_, .-_Z3mulPA100_iS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"matrix multiplication per thread\n"
.LC1:
	.string	"Time to generate : %3.1f ms\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-118784(%rsp), %r11
	.cfi_def_cfa 11, 118840
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$1304, %rsp
	.cfi_def_cfa_offset 120144
	xorl	%edi, %edi
	xorl	%ebp, %ebp
	movl	$10, %r12d
	movq	%fs:40, %rax
	movq	%rax, 120072(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	8(%rsp), %rdi
	movl	$40000, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$40000, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$40000, %esi
	call	cudaMalloc@PLT
.L9:
	movq	%rbp, %rbx
	movl	$100, %r13d
.L10:
	call	rand@PLT
	leaq	72(%rsp), %r15
	leaq	40072(%rsp), %r14
	cltd
	idivl	%r12d
	incl	%edx
	movl	%edx, 72(%rsp,%rbx)
	call	rand@PLT
	cltd
	idivl	%r12d
	incl	%edx
	movl	%edx, 40072(%rsp,%rbx)
	addq	$4, %rbx
	decl	%r13d
	jne	.L10
	addq	$400, %rbp
	cmpq	$40000, %rbp
	jne	.L9
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$40000, %edx
	movq	%r15, %rsi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$40000, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$429496729700, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 56(%rsp)
	movq	%rdx, 48(%rsp)
	movq	%rdi, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z33__device_stub__Z3mulPA100_iS0_S0_PA100_iS0_S0_
.L12:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$40000, %edx
	leaq	80072(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	60(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	60(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	120072(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$120088, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z3mulPA100_iS0_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3mulPA100_iS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <hip/hip_runtime.h>

#include <time.h>

#define N 100
__global__ void mul(int a[][N], int b[][N], int c[][N]){
	int row = blockIdx.x*blockDim.x+threadIdx.x;
	int col = blockIdx.y*blockDim.y+threadIdx.y;

	if(row < N && col < N) {
		for(int i = 0; i < N; i++) {
			for(int j = 0; j < N; j++) {
				c[i][j] = 0;
				for(int k = 0; k < N; k++) {
					c[i][j] += a[i][k] * b[k][j];
				}
			}
		}
	}
}

int main(){
	int (*pa)[N], (*pb)[N], (*pc)[N];
	int a[N][N], b[N][N], c[N][N];

	srand((unsigned)time(NULL));	

	hipEvent_t start, stop;

	hipEventCreate(&start);
        hipEventCreate(&stop);
        hipEventRecord(start, 0);
	
	hipMalloc((void**)&pa, (N*N) * sizeof(int));
	hipMalloc((void**)&pb, (N*N) * sizeof(int));
	hipMalloc((void**)&pc, (N*N) * sizeof(int));

	for(int i = 0 ; i<N ; i++){
		for(int j = 0 ; j<N ; j++) {
			a[i][j] = rand()%10 + 1;
			b[i][j] = rand()%10 + 1;
		}
	}
	
	hipMemcpy(pa, a, (N*N) * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(pb, b, (N*N) * sizeof(int), hipMemcpyHostToDevice);	
	
	dim3 threadsPerThreads(N,N);
	mul<<<1,threadsPerThreads>>>(pa, pb, pc);

	hipMemcpy(c, pc, (N*N) * sizeof(int), hipMemcpyDeviceToHost);

	printf("matrix multiplication per thread\n");


/*	for(int i = 0 ; i<N ; i++){
		for(int j = 0 ; j<N ; j++) {
			printf("%d ",c[i][j]);
		}
		printf("\n");
	}
*/
	hipEventRecord(stop, 0);
	hipEventSynchronize(stop);

	float elapsedTime;
	hipEventElapsedTime(&elapsedTime, start, stop);

	hipEventDestroy(start);
	hipEventDestroy(stop);

	printf("Time to generate : %3.1f ms\n", elapsedTime);

	hipFree(pa);
	hipFree(pb);
	hipFree(pc);

	return 0;

}

	.text
	.file	"matrixRandMul_Thread.hip"
	.globl	_Z18__device_stub__mulPA100_iS0_S0_ # -- Begin function _Z18__device_stub__mulPA100_iS0_S0_
	.type	_Z18__device_stub__mulPA100_iS0_S0_,@function
_Z18__device_stub__mulPA100_iS0_S0_:    # @_Z18__device_stub__mulPA100_iS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3mulPA100_iS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__mulPA100_iS0_S0_, .Lfunc_end0-_Z18__device_stub__mulPA100_iS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$120048, %rsp                   # imm = 0x1D4F0
	.cfi_def_cfa_offset 120096
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%r14d, %r14d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	24(%rsp), %rdi
	movl	$40000, %esi                    # imm = 0x9C40
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$40000, %esi                    # imm = 0x9C40
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$40000, %esi                    # imm = 0x9C40
	callq	hipMalloc
	leaq	40048(%rsp), %rbx
	leaq	48(%rsp), %r15
	movl	$400, %r12d                     # imm = 0x190
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%r13d, %r13d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%rbx,%r13,4)
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%r15,%r13,4)
	incq	%r13
	cmpq	$100, %r13
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r14
	addq	%r12, %rbx
	addq	%r12, %r15
	cmpq	$100, %r14
	jne	.LBB1_1
# %bb.4:
	movq	24(%rsp), %rdi
	leaq	40048(%rsp), %rsi
	movl	$40000, %edx                    # imm = 0x9C40
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	leaq	48(%rsp), %rsi
	movl	$40000, %edx                    # imm = 0x9C40
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$429496729700, %rdx             # imm = 0x6400000064
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z18__device_stub__mulPA100_iS0_S0_
.LBB1_6:
	movq	8(%rsp), %rsi
	leaq	80048(%rsp), %rdi
	movl	$40000, %edx                    # imm = 0x9C40
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	44(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	(%rsp), %rdi
	callq	hipEventDestroy
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$120048, %rsp                   # imm = 0x1D4F0
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3mulPA100_iS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3mulPA100_iS0_S0_,@object     # @_Z3mulPA100_iS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z3mulPA100_iS0_S0_
	.p2align	3, 0x0
_Z3mulPA100_iS0_S0_:
	.quad	_Z18__device_stub__mulPA100_iS0_S0_
	.size	_Z3mulPA100_iS0_S0_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Time to generate : %3.1f ms\n"
	.size	.L.str.1, 29

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3mulPA100_iS0_S0_"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"matrix multiplication per thread"
	.size	.Lstr, 33

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__mulPA100_iS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3mulPA100_iS0_S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3mulPA100_iS0_S0_     ; -- Begin function _Z3mulPA100_iS0_S0_
	.globl	_Z3mulPA100_iS0_S0_
	.p2align	8
	.type	_Z3mulPA100_iS0_S0_,@function
_Z3mulPA100_iS0_S0_:                    ; @_Z3mulPA100_iS0_S0_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_max_i32_e32 v0, v2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x64, v0
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.preheader.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s16, s3
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_4 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_hi_u32 s17, s16, 0x190
	s_mul_i32 s18, s16, 0x190
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[8:9], s[6:7]
	s_mov_b32 s2, s3
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_4 Depth 3
	s_add_u32 s12, s0, s18
	s_addc_u32 s13, s1, s17
	s_lshl_b64 s[10:11], s[2:3], 2
	v_mov_b32_e32 v1, 0
	s_add_u32 s10, s12, s10
	s_addc_u32 s11, s13, s11
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[8:9]
	global_store_b32 v0, v0, s[10:11]
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_add_u32 s20, s4, s12
	s_addc_u32 s21, s5, s13
	s_add_u32 s12, s12, 4
	s_clause 0x1
	global_load_b32 v2, v0, s[20:21]
	global_load_b32 v3, v0, s[14:15]
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 0x190
	s_addc_u32 s15, s15, 0
	s_cmpk_eq_i32 s12, 0x190
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	global_store_b32 v0, v1, s[10:11]
	s_cbranch_scc0 .LBB0_4
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_add_i32 s2, s2, 1
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmpk_eq_i32 s2, 0x64
	s_cbranch_scc0 .LBB0_3
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s16, s16, 1
	s_add_u32 s4, s4, 0x190
	s_addc_u32 s5, s5, 0
	s_cmpk_eq_i32 s16, 0x64
	s_cbranch_scc0 .LBB0_2
.LBB0_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3mulPA100_iS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 22
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3mulPA100_iS0_S0_, .Lfunc_end0-_Z3mulPA100_iS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 22
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3mulPA100_iS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z3mulPA100_iS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
