
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <stdio.h>
#include <iostream>


#define NUM_BLOCKS 800
#define NUM_THREADS 1024

__global__ void localReductionKernel(int* cudaDeltaArray) {
	__shared__ int sharedDeltaArray[NUM_THREADS];

	unsigned int id = threadIdx.x;

	sharedDeltaArray[id] = 1;
	__syncthreads();

	for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
		if (id < s) {
			sharedDeltaArray[id] = sharedDeltaArray[id] + sharedDeltaArray[id + s];
		}

		__syncthreads();
	}

	if (id == 0) {
		cudaDeltaArray[blockIdx.x] = sharedDeltaArray[0];
	}
}

int nextPowerOf2(int a){
	int b = 1;
	while (b < a)
	{
		b = b << 1;
	}
	return b;
}

__global__ void globalReductionKernel(int* cudaDeltaArray) {

	unsigned int id = blockIdx.x * blockDim.x + threadIdx.x;
	
	int b = 1;
	while (b < gridDim.x)
	{
		b = b << 1;
	}

	//printf("b=%d", b);

	for (unsigned int s = b / 2; s > 0; s >>= 1) {
		//printf("s=%d", s);
		if ((id < s) && (id + s <gridDim.x)) {
			printf("Id=%d niz[%d]=niz[%d]+niz[%d] => %d + %d\n", id, id, id, id + s, cudaDeltaArray[id], cudaDeltaArray[id + s]);
			cudaDeltaArray[id] = cudaDeltaArray[id] + cudaDeltaArray[id + s];
		}
		__syncthreads();
	}
}

int main() {

	int* deltaArray = new int[NUM_BLOCKS];
	int* cudaDeltaArray;

	cudaMalloc(&cudaDeltaArray, NUM_BLOCKS * sizeof(int));
	cudaMemcpy(cudaDeltaArray, deltaArray, NUM_BLOCKS * sizeof(int), cudaMemcpyHostToDevice);

	dim3 dimGrid(NUM_BLOCKS);
	dim3 dimBlock(NUM_THREADS);

	localReductionKernel <<< dimGrid, dimBlock >>> (cudaDeltaArray);
	globalReductionKernel <<< dimGrid, dimBlock >>> (cudaDeltaArray);

	int delta;

	cudaMemcpy(&delta, &cudaDeltaArray[0], sizeof(int), cudaMemcpyDeviceToHost);


	std::cout << "Delta je " << delta;
	return 0;
}
	.file	"tmpxft_0031c4ec_00000000-6_kernel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12nextPowerOf2i
	.type	_Z12nextPowerOf2i, @function
_Z12nextPowerOf2i:
.LFB3635:
	.cfi_startproc
	endbr64
	movl	$1, %eax
.L3:
	cmpl	%edi, %eax
	jge	.L6
	addl	%eax, %eax
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z12nextPowerOf2i, .-_Z12nextPowerOf2i
	.globl	_Z40__device_stub__Z20localReductionKernelPiPi
	.type	_Z40__device_stub__Z20localReductionKernelPiPi, @function
_Z40__device_stub__Z20localReductionKernelPiPi:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z20localReductionKernelPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L7:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z40__device_stub__Z20localReductionKernelPiPi, .-_Z40__device_stub__Z20localReductionKernelPiPi
	.globl	_Z20localReductionKernelPi
	.type	_Z20localReductionKernelPi, @function
_Z20localReductionKernelPi:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z20localReductionKernelPiPi
	.cfi_endproc
.LFE3662:
	.size	_Z20localReductionKernelPi, .-_Z20localReductionKernelPi
	.globl	_Z41__device_stub__Z21globalReductionKernelPiPi
	.type	_Z41__device_stub__Z21globalReductionKernelPiPi, @function
_Z41__device_stub__Z21globalReductionKernelPiPi:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z21globalReductionKernelPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L12:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z41__device_stub__Z21globalReductionKernelPiPi, .-_Z41__device_stub__Z21globalReductionKernelPiPi
	.globl	_Z21globalReductionKernelPi
	.type	_Z21globalReductionKernelPi, @function
_Z21globalReductionKernelPi:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z21globalReductionKernelPiPi
	.cfi_endproc
.LFE3664:
	.size	_Z21globalReductionKernelPi, .-_Z21globalReductionKernelPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Delta je "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$3200, %edi
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	leaq	8(%rsp), %rdi
	movl	$3200, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$3200, %edx
	call	cudaMemcpy@PLT
	movl	$134217753, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4194305, %edx
	salq	$5, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	salq	$10, %rdx
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	8(%rsp), %rdi
	call	_Z40__device_stub__Z20localReductionKernelPiPi
.L18:
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	8(%rsp), %rdi
	call	_Z41__device_stub__Z21globalReductionKernelPiPi
.L19:
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	4(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z21globalReductionKernelPi"
.LC2:
	.string	"_Z20localReductionKernelPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21globalReductionKernelPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20localReductionKernelPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3666:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"


#include <stdio.h>
#include <iostream>


#define NUM_BLOCKS 800
#define NUM_THREADS 1024

__global__ void localReductionKernel(int* cudaDeltaArray) {
	__shared__ int sharedDeltaArray[NUM_THREADS];

	unsigned int id = threadIdx.x;

	sharedDeltaArray[id] = 1;
	__syncthreads();

	for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
		if (id < s) {
			sharedDeltaArray[id] = sharedDeltaArray[id] + sharedDeltaArray[id + s];
		}

		__syncthreads();
	}

	if (id == 0) {
		cudaDeltaArray[blockIdx.x] = sharedDeltaArray[0];
	}
}

int nextPowerOf2(int a){
	int b = 1;
	while (b < a)
	{
		b = b << 1;
	}
	return b;
}

__global__ void globalReductionKernel(int* cudaDeltaArray) {

	unsigned int id = blockIdx.x * blockDim.x + threadIdx.x;
	
	int b = 1;
	while (b < gridDim.x)
	{
		b = b << 1;
	}

	//printf("b=%d", b);

	for (unsigned int s = b / 2; s > 0; s >>= 1) {
		//printf("s=%d", s);
		if ((id < s) && (id + s <gridDim.x)) {
			printf("Id=%d niz[%d]=niz[%d]+niz[%d] => %d + %d\n", id, id, id, id + s, cudaDeltaArray[id], cudaDeltaArray[id + s]);
			cudaDeltaArray[id] = cudaDeltaArray[id] + cudaDeltaArray[id + s];
		}
		__syncthreads();
	}
}

int main() {

	int* deltaArray = new int[NUM_BLOCKS];
	int* cudaDeltaArray;

	hipMalloc(&cudaDeltaArray, NUM_BLOCKS * sizeof(int));
	hipMemcpy(cudaDeltaArray, deltaArray, NUM_BLOCKS * sizeof(int), hipMemcpyHostToDevice);

	dim3 dimGrid(NUM_BLOCKS);
	dim3 dimBlock(NUM_THREADS);

	localReductionKernel <<< dimGrid, dimBlock >>> (cudaDeltaArray);
	globalReductionKernel <<< dimGrid, dimBlock >>> (cudaDeltaArray);

	int delta;

	hipMemcpy(&delta, &cudaDeltaArray[0], sizeof(int), hipMemcpyDeviceToHost);


	std::cout << "Delta je " << delta;
	return 0;
}
	.text
	.file	"kernel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z35__device_stub__localReductionKernelPi # -- Begin function _Z35__device_stub__localReductionKernelPi
	.type	_Z35__device_stub__localReductionKernelPi,@function
_Z35__device_stub__localReductionKernelPi: # @_Z35__device_stub__localReductionKernelPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20localReductionKernelPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__localReductionKernelPi, .Lfunc_end0-_Z35__device_stub__localReductionKernelPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z12nextPowerOf2i               # -- Begin function _Z12nextPowerOf2i
	.type	_Z12nextPowerOf2i,@function
_Z12nextPowerOf2i:                      # @_Z12nextPowerOf2i
	.cfi_startproc
# %bb.0:
	movl	$1, %ecx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	%ecx, %eax
	leal	(%rax,%rax), %ecx
	cmpl	%edi, %eax
	jl	.LBB1_1
# %bb.2:
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end1:
	.size	_Z12nextPowerOf2i, .Lfunc_end1-_Z12nextPowerOf2i
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__globalReductionKernelPi # -- Begin function _Z36__device_stub__globalReductionKernelPi
	.type	_Z36__device_stub__globalReductionKernelPi,@function
_Z36__device_stub__globalReductionKernelPi: # @_Z36__device_stub__globalReductionKernelPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21globalReductionKernelPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z36__device_stub__globalReductionKernelPi, .Lfunc_end2-_Z36__device_stub__globalReductionKernelPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294968096, %rbx               # imm = 0x100000320
	movl	$3200, %edi                     # imm = 0xC80
	callq	_Znam
	movq	%rax, %r14
	movq	%rsp, %r15
	movl	$3200, %esi                     # imm = 0xC80
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$3200, %edx                     # imm = 0xC80
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	224(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	(%rsp), %rdi
	callq	_Z35__device_stub__localReductionKernelPi
.LBB3_2:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	(%rsp), %rdi
	callq	_Z36__device_stub__globalReductionKernelPi
.LBB3_4:
	movq	(%rsp), %rsi
	leaq	12(%rsp), %rbx
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%rbx), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20localReductionKernelPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21globalReductionKernelPi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20localReductionKernelPi,@object # @_Z20localReductionKernelPi
	.section	.rodata,"a",@progbits
	.globl	_Z20localReductionKernelPi
	.p2align	3, 0x0
_Z20localReductionKernelPi:
	.quad	_Z35__device_stub__localReductionKernelPi
	.size	_Z20localReductionKernelPi, 8

	.type	_Z21globalReductionKernelPi,@object # @_Z21globalReductionKernelPi
	.globl	_Z21globalReductionKernelPi
	.p2align	3, 0x0
_Z21globalReductionKernelPi:
	.quad	_Z36__device_stub__globalReductionKernelPi
	.size	_Z21globalReductionKernelPi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Delta je "
	.size	.L.str, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z20localReductionKernelPi"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z21globalReductionKernelPi"
	.size	.L__unnamed_2, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__localReductionKernelPi
	.addrsig_sym _Z36__device_stub__globalReductionKernelPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20localReductionKernelPi
	.addrsig_sym _Z21globalReductionKernelPi
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20localReductionKernelPi ; -- Begin function _Z20localReductionKernelPi
	.globl	_Z20localReductionKernelPi
	.p2align	8
	.type	_Z20localReductionKernelPi,@function
_Z20localReductionKernelPi:             ; @_Z20localReductionKernelPi
; %bb.0:
	v_dual_mov_b32 v2, 1 :: v_dual_lshlrev_b32 v1, 2, v0
	s_mov_b32 s2, s15
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b32 s3, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s3, 2
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_lshr_b32 s3, s3, 1
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s3, v0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshl_add_u32 v2, s3, 2, v1
	ds_load_b32 v3, v1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_lshr_b32 s4, s3, 1
	s_cmp_lt_u32 s3, 2
	s_mov_b32 s3, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_mov_b32 s3, 0
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_lshl_b64 s[2:3], s[2:3], 2
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_store_b32 v0, v1, s[0:1]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20localReductionKernelPi
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20localReductionKernelPi, .Lfunc_end0-_Z20localReductionKernelPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 16
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21globalReductionKernelPi ; -- Begin function _Z21globalReductionKernelPi
	.globl	_Z21globalReductionKernelPi
	.p2align	8
	.type	_Z21globalReductionKernelPi,@function
_Z21globalReductionKernelPi:            ; @_Z21globalReductionKernelPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s20, s[0:1], 0x8
	s_load_b32 s5, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_mov_b32 s6, 1
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s4, s6
	s_lshl_b32 s6, s6, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s4, s20
	s_cbranch_scc1 .LBB1_1
; %bb.2:
	s_add_i32 s6, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s6, 3
	s_cbranch_scc1 .LBB1_314
; %bb.3:                                ; %.lr.ph
	s_load_b64 s[8:9], s[0:1], 0x0
	s_and_b32 s0, 0xffff, s5
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v9, 2
	v_mad_u64_u32 v[5:6], null, s15, s0, v[0:1]
	s_lshr_b32 s0, s4, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v6, v2
	v_mbcnt_lo_u32_b32 v47, -1, 0
	v_mov_b32_e32 v10, 1
	s_add_i32 s0, s4, s0
	s_mov_b32 s4, 0
	v_lshlrev_b64 v[0:1], 2, v[5:6]
	s_ashr_i32 s21, s0, 1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v44, vcc_lo, s9, v1, vcc_lo
	v_mov_b32_e32 v0, 33
.LBB1_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_9 Depth 2
                                        ;     Child Loop BB1_17 Depth 2
                                        ;     Child Loop BB1_23 Depth 2
                                        ;     Child Loop BB1_32 Depth 2
                                        ;     Child Loop BB1_35 Depth 2
                                        ;       Child Loop BB1_38 Depth 3
                                        ;       Child Loop BB1_46 Depth 3
                                        ;       Child Loop BB1_54 Depth 3
                                        ;       Child Loop BB1_62 Depth 3
                                        ;       Child Loop BB1_70 Depth 3
                                        ;       Child Loop BB1_78 Depth 3
                                        ;       Child Loop BB1_86 Depth 3
                                        ;       Child Loop BB1_94 Depth 3
                                        ;       Child Loop BB1_102 Depth 3
                                        ;       Child Loop BB1_108 Depth 3
                                        ;       Child Loop BB1_117 Depth 3
                                        ;     Child Loop BB1_125 Depth 2
                                        ;     Child Loop BB1_133 Depth 2
                                        ;     Child Loop BB1_139 Depth 2
                                        ;     Child Loop BB1_148 Depth 2
                                        ;     Child Loop BB1_153 Depth 2
                                        ;     Child Loop BB1_161 Depth 2
                                        ;     Child Loop BB1_167 Depth 2
                                        ;     Child Loop BB1_176 Depth 2
                                        ;     Child Loop BB1_180 Depth 2
                                        ;     Child Loop BB1_188 Depth 2
                                        ;     Child Loop BB1_194 Depth 2
                                        ;     Child Loop BB1_203 Depth 2
                                        ;     Child Loop BB1_207 Depth 2
                                        ;     Child Loop BB1_215 Depth 2
                                        ;     Child Loop BB1_221 Depth 2
                                        ;     Child Loop BB1_230 Depth 2
                                        ;     Child Loop BB1_234 Depth 2
                                        ;     Child Loop BB1_242 Depth 2
                                        ;     Child Loop BB1_248 Depth 2
                                        ;     Child Loop BB1_257 Depth 2
                                        ;     Child Loop BB1_261 Depth 2
                                        ;     Child Loop BB1_269 Depth 2
                                        ;     Child Loop BB1_275 Depth 2
                                        ;     Child Loop BB1_284 Depth 2
                                        ;     Child Loop BB1_288 Depth 2
                                        ;     Child Loop BB1_296 Depth 2
                                        ;     Child Loop BB1_302 Depth 2
                                        ;     Child Loop BB1_311 Depth 2
	s_mov_b32 s22, exec_lo
	v_cmpx_gt_u32_e64 s21, v5
	s_cbranch_execz .LBB1_313
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=1
	v_add_nc_u32_e32 v19, s21, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s20, v19
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_313
; %bb.6:                                ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v20, v2 :: v_dual_mov_b32 v1, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[19:20]
	v_add_co_u32 v45, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v46, vcc_lo, s9, v4, vcc_lo
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_clause 0x1
	global_load_b32 v16, v[43:44], off
	global_load_b32 v13, v[45:46], off
	s_load_b64 s[10:11], s[2:3], 0x50
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_12
; %bb.7:                                ;   in Loop: Header=BB1_4 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v24
	v_and_b32_e32 v3, v3, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[21:22], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[23:24]
	s_cbranch_execz .LBB1_11
; %bb.8:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_9:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	v_dual_mov_b32 v24, v4 :: v_dual_mov_b32 v23, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v23
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[21:22], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[23:24]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_9
; %bb.10:                               ; %Flow592
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_11:                               ; %Flow594
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_12:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b128 v[21:24], v2, s[10:11]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_14
; %bb.13:                               ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[3:4], v[7:10], off offset:8
.LBB1_14:                               ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v4, vcc_lo
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v26, s7
	v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v24, s5
	v_mov_b32_e32 v25, s6
	v_mov_b32_e32 v23, s4
	s_clause 0x3
	global_store_b128 v[7:8], v[0:3], off
	global_store_b128 v[7:8], v[23:26], off offset:16
	global_store_b128 v[7:8], v[23:26], off offset:32
	global_store_b128 v[7:8], v[23:26], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_22
; %bb.15:                               ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[27:28], v2, s[10:11] offset:32 glc
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	v_mov_b32_e32 v25, s12
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v26, s13 :: v_dual_and_b32 v1, s13, v4
	v_and_b32_e32 v3, s12, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v4, v1
	v_add_co_u32 v3, vcc_lo, v21, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v22, v1, vcc_lo
	global_store_b64 v[3:4], v[27:28], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v2, v[25:28], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[27:28]
	s_cbranch_execz .LBB1_18
; %bb.16:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_17:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v24, s13
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[23:26], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_17
.LBB1_18:                               ; %Flow590
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[3:4], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_20
; %bb.19:                               ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_20:                               ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_22
; %bb.21:                               ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_22:                               ; %Flow591
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s14, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_23:                               ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_25
; %bb.24:                               ;   in Loop: Header=BB1_23 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_25:                               ;   in Loop: Header=BB1_23 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_27
; %bb.26:                               ;   in Loop: Header=BB1_23 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_28
.LBB1_27:                               ;   in Loop: Header=BB1_23 Depth=2
	s_mov_b32 s1, -1
.LBB1_28:                               ; %Flow585
                                        ;   in Loop: Header=BB1_23 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_23
; %bb.29:                               ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[21:22], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_33
; %bb.30:                               ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11] offset:24 glc
	global_load_b64 v[11:12], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v25, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v17, vcc_lo
	v_mov_b32_e32 v26, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_cndmask_b32_e32 v24, v15, v17, vcc_lo
	v_cndmask_b32_e32 v23, v14, v1, vcc_lo
	v_and_b32_e32 v1, v24, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v23, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v2, v[23:26], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[25:26], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_33
; %bb.31:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_32:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[23:26], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[25:26]
	v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v25, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_32
.LBB1_33:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB1_120
; %bb.34:                               ;   in Loop: Header=BB1_4 Depth=1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v14, 2, v21
	v_dual_mov_b32 v24, v22 :: v_dual_and_b32 v23, -3, v21
	s_mov_b64 s[12:13], 42
.LBB1_35:                               ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_38 Depth 3
                                        ;       Child Loop BB1_46 Depth 3
                                        ;       Child Loop BB1_54 Depth 3
                                        ;       Child Loop BB1_62 Depth 3
                                        ;       Child Loop BB1_70 Depth 3
                                        ;       Child Loop BB1_78 Depth 3
                                        ;       Child Loop BB1_86 Depth 3
                                        ;       Child Loop BB1_94 Depth 3
                                        ;       Child Loop BB1_102 Depth 3
                                        ;       Child Loop BB1_108 Depth 3
                                        ;       Child Loop BB1_117 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[12:13], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s14, s12, 56
	s_cselect_b32 s15, s13, 0
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB1_40
; %bb.36:                               ;   in Loop: Header=BB1_35 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_39
; %bb.37:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_lshl_b64 s[0:1], s[14:15], 3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[6:7]
.LBB1_38:                               ; %.preheader31.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[18:19]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s0, s16
	v_or_b32_e32 v25, v3, v25
	v_or_b32_e32 v26, v4, v26
	s_cbranch_scc1 .LBB1_38
.LBB1_39:                               ; %Flow561
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s5, 0
	s_branch .LBB1_41
.LBB1_40:                               ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr5
.LBB1_41:                               ; %Flow563
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[6:7]
	s_cbranch_vccnz .LBB1_43
; %bb.42:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[25:26], v2, s[6:7]
	s_add_i32 s5, s14, -8
	s_add_u32 s0, s6, 8
	s_addc_u32 s1, s7, 0
.LBB1_43:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB1_48
; %bb.44:                               ;   in Loop: Header=BB1_35 Depth=2
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB1_47
; %bb.45:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_46:                               ; %.preheader29.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s5, s18
	v_or_b32_e32 v27, v3, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v28, v4, v28
	s_cbranch_scc1 .LBB1_46
.LBB1_47:                               ; %Flow556
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s23, 0
	s_branch .LBB1_49
.LBB1_48:                               ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr27_vgpr28
                                        ; implicit-def: $sgpr23
.LBB1_49:                               ; %Flow558
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_51
; %bb.50:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[27:28], v2, s[0:1]
	s_add_i32 s23, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_51:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_cmp_gt_u32 s23, 7
	s_cbranch_scc1 .LBB1_56
; %bb.52:                               ;   in Loop: Header=BB1_35 Depth=2
	v_mov_b32_e32 v29, 0
	v_mov_b32_e32 v30, 0
	s_cmp_eq_u32 s23, 0
	s_cbranch_scc1 .LBB1_55
; %bb.53:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_54:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s23, s18
	v_or_b32_e32 v29, v3, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v30, v4, v30
	s_cbranch_scc1 .LBB1_54
.LBB1_55:                               ; %Flow551
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s5, 0
	s_branch .LBB1_57
.LBB1_56:                               ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr5
.LBB1_57:                               ; %Flow553
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_59
; %bb.58:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[29:30], v2, s[0:1]
	s_add_i32 s5, s23, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_59:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB1_64
; %bb.60:                               ;   in Loop: Header=BB1_35 Depth=2
	v_mov_b32_e32 v31, 0
	v_mov_b32_e32 v32, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB1_63
; %bb.61:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_62:                               ; %.preheader25.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s5, s18
	v_or_b32_e32 v31, v3, v31
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v32, v4, v32
	s_cbranch_scc1 .LBB1_62
.LBB1_63:                               ; %Flow546
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s23, 0
	s_branch .LBB1_65
.LBB1_64:                               ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr31_vgpr32
                                        ; implicit-def: $sgpr23
.LBB1_65:                               ; %Flow548
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_67
; %bb.66:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[31:32], v2, s[0:1]
	s_add_i32 s23, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_67:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_cmp_gt_u32 s23, 7
	s_cbranch_scc1 .LBB1_72
; %bb.68:                               ;   in Loop: Header=BB1_35 Depth=2
	v_mov_b32_e32 v33, 0
	v_mov_b32_e32 v34, 0
	s_cmp_eq_u32 s23, 0
	s_cbranch_scc1 .LBB1_71
; %bb.69:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_70:                               ; %.preheader23.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s23, s18
	v_or_b32_e32 v33, v3, v33
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v34, v4, v34
	s_cbranch_scc1 .LBB1_70
.LBB1_71:                               ; %Flow541
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s5, 0
	s_branch .LBB1_73
.LBB1_72:                               ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr5
.LBB1_73:                               ; %Flow543
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_75
; %bb.74:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[33:34], v2, s[0:1]
	s_add_i32 s5, s23, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_75:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB1_80
; %bb.76:                               ;   in Loop: Header=BB1_35 Depth=2
	v_mov_b32_e32 v35, 0
	v_mov_b32_e32 v36, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB1_79
; %bb.77:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB1_78:                               ; %.preheader21.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s5, s18
	v_or_b32_e32 v35, v3, v35
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v36, v4, v36
	s_cbranch_scc1 .LBB1_78
.LBB1_79:                               ; %Flow536
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s23, 0
	s_branch .LBB1_81
.LBB1_80:                               ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr35_vgpr36
                                        ; implicit-def: $sgpr23
.LBB1_81:                               ; %Flow538
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_83
; %bb.82:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[35:36], v2, s[0:1]
	s_add_i32 s23, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_83:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_cmp_gt_u32 s23, 7
	s_cbranch_scc1 .LBB1_88
; %bb.84:                               ;   in Loop: Header=BB1_35 Depth=2
	v_mov_b32_e32 v37, 0
	v_mov_b32_e32 v38, 0
	s_cmp_eq_u32 s23, 0
	s_cbranch_scc1 .LBB1_87
; %bb.85:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[0:1]
.LBB1_86:                               ; %.preheader.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[18:19]
	s_add_i32 s23, s23, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s16, v[1:2]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s23, 0
	v_or_b32_e32 v37, v3, v37
	v_or_b32_e32 v38, v4, v38
	s_cbranch_scc1 .LBB1_86
.LBB1_87:                               ; %Flow531
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s5, 0
	s_branch .LBB1_89
.LBB1_88:                               ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s5, -1
.LBB1_89:                               ; %Flow533
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB1_91
; %bb.90:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[37:38], v2, s[0:1]
.LBB1_91:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_97
; %bb.92:                               ;   in Loop: Header=BB1_35 Depth=2
	global_load_b64 v[41:42], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v42
	v_and_b32_e32 v3, v3, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[39:40], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[39:42], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[41:42]
	s_cbranch_execz .LBB1_96
; %bb.93:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s16, 0
.LBB1_94:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	v_dual_mov_b32 v42, v4 :: v_dual_mov_b32 v41, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v41
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[39:40], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[39:42], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[41:42]
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_94
; %bb.95:                               ; %Flow526
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
.LBB1_96:                               ; %Flow528
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_97:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b128 v[39:42], v2, s[10:11]
	v_readfirstlane_b32 s16, v3
	v_readfirstlane_b32 s17, v4
	s_mov_b32 s24, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s18, v7
	v_readfirstlane_b32 s19, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[16:17], s[18:19]
	s_mul_i32 s1, s19, 24
	s_mul_hi_u32 s5, s18, 24
	s_mul_i32 s23, s18, 24
	s_and_saveexec_b32 s25, s0
	s_cbranch_execz .LBB1_99
; %bb.98:                               ;   in Loop: Header=BB1_35 Depth=2
	v_dual_mov_b32 v7, s24 :: v_dual_mov_b32 v8, v2
	s_add_i32 s24, s5, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v39, s23
	v_add_co_ci_u32_e32 v4, vcc_lo, s24, v40, vcc_lo
	global_store_b128 v[3:4], v[7:10], off offset:8
.LBB1_99:                               ;   in Loop: Header=BB1_35 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	v_cmp_gt_u64_e64 vcc_lo, s[12:13], 56
	v_or_b32_e32 v3, 0, v24
	v_or_b32_e32 v4, v23, v14
	s_lshl_b64 s[18:19], s[18:19], 12
	s_lshl_b32 s24, s14, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s24, s24, 28
	v_dual_cndmask_b32 v24, v3, v24 :: v_dual_cndmask_b32 v7, v4, v23
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v41, s18
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v42, vcc_lo
	s_and_b32 s24, s24, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v23, 0xffffff1f, v7, s24
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[23:26], off
	global_store_b128 v[3:4], v[27:30], off offset:16
	global_store_b128 v[3:4], v[31:34], off offset:32
	global_store_b128 v[3:4], v[35:38], off offset:48
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB1_107
; %bb.100:                              ;   in Loop: Header=BB1_35 Depth=2
	s_clause 0x1
	global_load_b64 v[27:28], v2, s[10:11] offset:32 glc
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	v_dual_mov_b32 v25, s16 :: v_dual_mov_b32 v26, s17
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s24, v7
	v_readfirstlane_b32 s25, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[24:25], s[24:25], s[16:17]
	s_mul_i32 s19, s25, 24
	s_mul_hi_u32 s25, s24, 24
	s_mul_i32 s24, s24, 24
	s_add_i32 s25, s25, s19
	v_add_co_u32 v7, vcc_lo, v39, s24
	v_add_co_ci_u32_e32 v8, vcc_lo, s25, v40, vcc_lo
	s_mov_b32 s19, exec_lo
	global_store_b64 v[7:8], v[27:28], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v2, v[25:28], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[27:28]
	s_cbranch_execz .LBB1_103
; %bb.101:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s24, 0
.LBB1_102:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v23, s16 :: v_dual_mov_b32 v24, s17
	s_sleep 1
	global_store_b64 v[7:8], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[23:26], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s24, vcc_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB1_102
.LBB1_103:                              ; %Flow524
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	global_load_b64 v[7:8], v2, s[10:11] offset:16
	s_mov_b32 s24, exec_lo
	s_mov_b32 s19, exec_lo
	v_mbcnt_lo_u32_b32 v1, s24, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_105
; %bb.104:                              ;   in Loop: Header=BB1_35 Depth=2
	s_bcnt1_i32_b32 s24, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s24
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_105:                              ;   in Loop: Header=BB1_35 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_107
; %bb.106:                              ;   in Loop: Header=BB1_35 Depth=2
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s19, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s19, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_107:                              ; %Flow525
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s5, s5, s1
	v_add_co_u32 v1, vcc_lo, v39, s23
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_108:                              ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_110
; %bb.109:                              ;   in Loop: Header=BB1_108 Depth=3
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_110:                              ;   in Loop: Header=BB1_108 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_112
; %bb.111:                              ;   in Loop: Header=BB1_108 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_113
.LBB1_112:                              ;   in Loop: Header=BB1_108 Depth=3
	s_mov_b32 s1, -1
.LBB1_113:                              ; %Flow519
                                        ;   in Loop: Header=BB1_108 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_108
; %bb.114:                              ;   in Loop: Header=BB1_35 Depth=2
	global_load_b128 v[23:26], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_118
; %bb.115:                              ;   in Loop: Header=BB1_35 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11] offset:24 glc
	global_load_b64 v[11:12], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v27, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, v1, s16
	v_add_co_ci_u32_e32 v18, vcc_lo, s17, v15, vcc_lo
	v_mov_b32_e32 v28, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[17:18]
	v_dual_cndmask_b32 v26, v18, v15 :: v_dual_cndmask_b32 v25, v17, v1
	v_and_b32_e32 v1, v26, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v25, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[27:28], v2, v[25:28], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[27:28], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_118
; %bb.116:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_mov_b32 s0, 0
.LBB1_117:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB1_4 Depth=1
                                        ;     Parent Loop BB1_35 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[27:28], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[25:28], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[27:28]
	v_dual_mov_b32 v28, v8 :: v_dual_mov_b32 v27, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_117
.LBB1_118:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB1_35 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s12, s12, s14
	s_subb_u32 s13, s13, s15
	s_add_u32 s6, s6, s14
	s_addc_u32 s7, s7, s15
	s_cmp_lg_u64 s[12:13], 0
	s_cbranch_scc1 .LBB1_35
; %bb.119:                              ; %Flow564
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB1_121
.LBB1_120:                              ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr23_vgpr24
.LBB1_121:                              ; %Flow579
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_150
; %bb.122:                              ;   in Loop: Header=BB1_4 Depth=1
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_128
; %bb.123:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[25:26], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v26
	v_and_b32_e32 v3, v3, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[23:24], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[23:26], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[25:26]
	s_cbranch_execz .LBB1_127
; %bb.124:                              ; %.preheader3.i.i.i34.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_125:                              ; %.preheader3.i.i.i34
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	v_dual_mov_b32 v26, v4 :: v_dual_mov_b32 v25, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v25
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[23:24], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[23:26], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[25:26]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_125
; %bb.126:                              ; %Flow576
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_127:                              ; %Flow578
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_128:                              ; %.loopexit4.i.i.i29
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b128 v[25:28], v2, s[10:11]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_130
; %bb.129:                              ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v25, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v26, vcc_lo
	global_store_b128 v[3:4], v[7:10], off offset:8
.LBB1_130:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v27, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v28, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v21, 0xffffff1f, v21, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v23, v2 :: v_dual_mov_b32 v30, s7
	v_dual_mov_b32 v24, v2 :: v_dual_mov_b32 v29, s6
	v_dual_mov_b32 v28, s5 :: v_dual_mov_b32 v27, s4
	s_clause 0x3
	global_store_b128 v[3:4], v[21:24], off
	global_store_b128 v[3:4], v[27:30], off offset:16
	global_store_b128 v[3:4], v[27:30], off offset:32
	global_store_b128 v[3:4], v[27:30], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_138
; %bb.131:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[29:30], v2, s[10:11] offset:32 glc
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	v_dual_mov_b32 v27, s12 :: v_dual_mov_b32 v28, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v7, vcc_lo, v25, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v26, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[7:8], v[29:30], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v2, v[27:30], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[23:24], v[29:30]
	s_cbranch_execz .LBB1_134
; %bb.132:                              ; %.preheader1.i.i.i32.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_133:                              ; %.preheader1.i.i.i32
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v21, s12 :: v_dual_mov_b32 v22, s13
	s_sleep 1
	global_store_b64 v[7:8], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[21:24], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_133
.LBB1_134:                              ; %Flow574
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_136
; %bb.135:                              ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_136:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_138
; %bb.137:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_138:                              ; %Flow575
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v25, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_139:                              ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_141
; %bb.140:                              ;   in Loop: Header=BB1_139 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_141:                              ;   in Loop: Header=BB1_139 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_143
; %bb.142:                              ;   in Loop: Header=BB1_139 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_144
.LBB1_143:                              ;   in Loop: Header=BB1_139 Depth=2
	s_mov_b32 s1, -1
.LBB1_144:                              ; %Flow569
                                        ;   in Loop: Header=BB1_139 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_139
; %bb.145:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b128 v[23:26], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_149
; %bb.146:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11] offset:24 glc
	global_load_b64 v[11:12], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v27, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v17, vcc_lo
	v_mov_b32_e32 v28, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_cndmask_b32_e32 v25, v14, v1, vcc_lo
	v_dual_cndmask_b32 v26, v15, v17 :: v_dual_and_b32 v3, v25, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v26, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[27:28], v2, v[25:28], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[27:28], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_149
; %bb.147:                              ; %.preheader.i.i.i31.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_148:                              ; %.preheader.i.i.i31
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[27:28], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[25:28], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[27:28]
	v_dual_mov_b32 v28, v8 :: v_dual_mov_b32 v27, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_148
.LBB1_149:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_150:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB1_4 Depth=1
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_156
; %bb.151:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[27:28], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v28
	v_and_b32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[27:28]
	s_cbranch_execz .LBB1_155
; %bb.152:                              ; %.preheader3.i.i.i41.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_153:                              ; %.preheader3.i.i.i41
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v27, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[27:28]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_153
; %bb.154:                              ; %Flow512
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_155:                              ; %Flow514
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_156:                              ; %.loopexit4.i.i.i35
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b128 v[27:30], v2, s[10:11]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_158
; %bb.157:                              ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v27, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v28, vcc_lo
	global_store_b128 v[3:4], v[7:10], off offset:8
.LBB1_158:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v29, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v30, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v23, 0xffffff1f, v23, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v25, v5 :: v_dual_mov_b32 v26, v6
	v_dual_mov_b32 v32, s7 :: v_dual_mov_b32 v31, s6
	v_dual_mov_b32 v30, s5 :: v_dual_mov_b32 v29, s4
	s_clause 0x3
	global_store_b128 v[3:4], v[23:26], off
	global_store_b128 v[3:4], v[29:32], off offset:16
	global_store_b128 v[3:4], v[29:32], off offset:32
	global_store_b128 v[3:4], v[29:32], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_166
; %bb.159:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[10:11] offset:32 glc
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v24, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v7, vcc_lo, v27, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v28, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[7:8], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v2, v[23:26], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[23:24], v[25:26]
	s_cbranch_execz .LBB1_162
; %bb.160:                              ; %.preheader1.i.i.i39.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_161:                              ; %.preheader1.i.i.i39
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v21, s12 :: v_dual_mov_b32 v22, s13
	s_sleep 1
	global_store_b64 v[7:8], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[21:24], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_161
.LBB1_162:                              ; %Flow510
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_164
; %bb.163:                              ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_164:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_166
; %bb.165:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_166:                              ; %Flow511
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v27, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_167:                              ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_169
; %bb.168:                              ;   in Loop: Header=BB1_167 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_169:                              ;   in Loop: Header=BB1_167 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_171
; %bb.170:                              ;   in Loop: Header=BB1_167 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_172
.LBB1_171:                              ;   in Loop: Header=BB1_167 Depth=2
	s_mov_b32 s1, -1
.LBB1_172:                              ; %Flow505
                                        ;   in Loop: Header=BB1_167 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_167
; %bb.173:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[3:4], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_177
; %bb.174:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11] offset:24 glc
	global_load_b64 v[14:15], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v7, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v8, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v23, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v18, vcc_lo, s13, v21, vcc_lo
	v_mov_b32_e32 v24, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[17:18]
	v_cndmask_b32_e32 v22, v18, v21, vcc_lo
	v_cndmask_b32_e32 v21, v17, v1, vcc_lo
	v_and_b32_e32 v7, v21, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v22, v8
	v_mul_hi_u32 v8, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v1, v8, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v14, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v15, v1, vcc_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_177
; %bb.175:                              ; %.preheader.i.i.i38.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_176:                              ; %.preheader.i.i.i38
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[7:8], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_176
.LBB1_177:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_183
; %bb.178:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[23:24], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v24
	v_and_b32_e32 v7, v7, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, 24
	v_mul_hi_u32 v14, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v14, v8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	global_load_b64 v[21:22], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[23:24]
	s_cbranch_execz .LBB1_182
; %bb.179:                              ; %.preheader3.i.i.i48.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_180:                              ; %.preheader3.i.i.i48
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[10:11] offset:40
	global_load_b64 v[14:15], v2, s[10:11]
	v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v23
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[14:15]
	v_and_b32_e32 v14, v12, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v14, 24, v[8:9]
	v_mov_b32_e32 v8, v11
	global_load_b64 v[21:22], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[23:24]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_180
; %bb.181:                              ; %Flow498
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_182:                              ; %Flow500
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_183:                              ; %.loopexit4.i.i.i42
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[10:11] offset:40
	global_load_b128 v[21:24], v2, s[10:11]
	v_readfirstlane_b32 s12, v7
	v_readfirstlane_b32 s13, v8
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_185
; %bb.184:                              ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB1_185:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[7:8], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v3, 0xffffff1f, v3, 32
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v24, s5 :: v_dual_mov_b32 v23, s4
	s_clause 0x3
	global_store_b128 v[7:8], v[3:6], off
	global_store_b128 v[7:8], v[23:26], off offset:16
	global_store_b128 v[7:8], v[23:26], off offset:32
	global_store_b128 v[7:8], v[23:26], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_193
; %bb.186:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[27:28], v2, s[10:11] offset:32 glc
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	v_dual_mov_b32 v25, s12 :: v_dual_mov_b32 v26, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v3
	v_readfirstlane_b32 s7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v3, vcc_lo, v21, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v22, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[3:4], v[27:28], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v2, v[25:28], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[27:28]
	s_cbranch_execz .LBB1_189
; %bb.187:                              ; %.preheader1.i.i.i46.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_188:                              ; %.preheader1.i.i.i46
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v24, s13
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[23:26], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_188
.LBB1_189:                              ; %Flow496
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[3:4], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_191
; %bb.190:                              ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_191:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_193
; %bb.192:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_193:                              ; %Flow497
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s14, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_194:                              ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_196
; %bb.195:                              ;   in Loop: Header=BB1_194 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_196:                              ;   in Loop: Header=BB1_194 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_198
; %bb.197:                              ;   in Loop: Header=BB1_194 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_199
.LBB1_198:                              ;   in Loop: Header=BB1_194 Depth=2
	s_mov_b32 s1, -1
.LBB1_199:                              ; %Flow491
                                        ;   in Loop: Header=BB1_194 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_194
; %bb.200:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[3:4], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_204
; %bb.201:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11] offset:24 glc
	global_load_b64 v[14:15], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v7, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v8, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v23, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v18, vcc_lo, s13, v21, vcc_lo
	v_mov_b32_e32 v24, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[17:18]
	v_cndmask_b32_e32 v22, v18, v21, vcc_lo
	v_cndmask_b32_e32 v21, v17, v1, vcc_lo
	v_and_b32_e32 v7, v21, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v22, v8
	v_mul_hi_u32 v8, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v1, v8, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v14, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v15, v1, vcc_lo
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_204
; %bb.202:                              ; %.preheader.i.i.i45.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_203:                              ; %.preheader.i.i.i45
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[7:8], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_203
.LBB1_204:                              ; %__ockl_printf_append_args.exit49
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_210
; %bb.205:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[23:24], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v24
	v_and_b32_e32 v7, v7, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, 24
	v_mul_hi_u32 v14, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v14, v8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	global_load_b64 v[21:22], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[23:24]
	s_cbranch_execz .LBB1_209
; %bb.206:                              ; %.preheader3.i.i.i56.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_207:                              ; %.preheader3.i.i.i56
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[10:11] offset:40
	global_load_b64 v[14:15], v2, s[10:11]
	v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v23
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[14:15]
	v_and_b32_e32 v14, v12, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v14, 24, v[8:9]
	v_mov_b32_e32 v8, v11
	global_load_b64 v[21:22], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[23:24]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_207
; %bb.208:                              ; %Flow484
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_209:                              ; %Flow486
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_210:                              ; %.loopexit4.i.i.i50
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[10:11] offset:40
	global_load_b128 v[21:24], v2, s[10:11]
	v_readfirstlane_b32 s12, v7
	v_readfirstlane_b32 s13, v8
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_212
; %bb.211:                              ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[11:12], v[7:10], off offset:8
.LBB1_212:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[7:8], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v3, 0xffffff1f, v3, 32
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v24, s5 :: v_dual_mov_b32 v23, s4
	s_clause 0x3
	global_store_b128 v[7:8], v[3:6], off
	global_store_b128 v[7:8], v[23:26], off offset:16
	global_store_b128 v[7:8], v[23:26], off offset:32
	global_store_b128 v[7:8], v[23:26], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_220
; %bb.213:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[27:28], v2, s[10:11] offset:32 glc
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	v_dual_mov_b32 v25, s12 :: v_dual_mov_b32 v26, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v3
	v_readfirstlane_b32 s7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v3, vcc_lo, v21, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v22, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[3:4], v[27:28], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v2, v[25:28], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[27:28]
	s_cbranch_execz .LBB1_216
; %bb.214:                              ; %.preheader1.i.i.i54.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_215:                              ; %.preheader1.i.i.i54
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v24, s13
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[23:26], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_215
.LBB1_216:                              ; %Flow482
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[3:4], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_218
; %bb.217:                              ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_218:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_220
; %bb.219:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_220:                              ; %Flow483
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s14, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_221:                              ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_223
; %bb.222:                              ;   in Loop: Header=BB1_221 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_223:                              ;   in Loop: Header=BB1_221 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_225
; %bb.224:                              ;   in Loop: Header=BB1_221 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_226
.LBB1_225:                              ;   in Loop: Header=BB1_221 Depth=2
	s_mov_b32 s1, -1
.LBB1_226:                              ; %Flow477
                                        ;   in Loop: Header=BB1_221 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_221
; %bb.227:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[17:18], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_231
; %bb.228:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11] offset:24 glc
	global_load_b64 v[11:12], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v23, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v21, vcc_lo
	v_mov_b32_e32 v24, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_cndmask_b32_e32 v22, v15, v21, vcc_lo
	v_cndmask_b32_e32 v21, v14, v1, vcc_lo
	v_and_b32_e32 v3, v21, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v22, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_231
; %bb.229:                              ; %.preheader.i.i.i53.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_230:                              ; %.preheader.i.i.i53
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[23:24]
	v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_230
.LBB1_231:                              ; %__ockl_printf_append_args.exit57
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_237
; %bb.232:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[23:24], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v24
	v_and_b32_e32 v3, v3, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[21:22], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[23:24]
	s_cbranch_execz .LBB1_236
; %bb.233:                              ; %.preheader3.i.i.i64.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_234:                              ; %.preheader3.i.i.i64
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	v_dual_mov_b32 v24, v4 :: v_dual_mov_b32 v23, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v23
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[21:22], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[21:24], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[23:24]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_234
; %bb.235:                              ; %Flow470
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_236:                              ; %Flow472
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_237:                              ; %.loopexit4.i.i.i58
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b128 v[21:24], v2, s[10:11]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_239
; %bb.238:                              ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[3:4], v[7:10], off offset:8
.LBB1_239:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v17, 0xffffff1f, v17, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v24, s5 :: v_dual_mov_b32 v23, s4
	s_clause 0x3
	global_store_b128 v[3:4], v[17:20], off
	global_store_b128 v[3:4], v[23:26], off offset:16
	global_store_b128 v[3:4], v[23:26], off offset:32
	global_store_b128 v[3:4], v[23:26], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_247
; %bb.240:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[10:11] offset:32 glc
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v24, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v7, vcc_lo, v21, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v22, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[7:8], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[19:20], v2, v[23:26], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[19:20], v[25:26]
	s_cbranch_execz .LBB1_243
; %bb.241:                              ; %.preheader1.i.i.i62.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_242:                              ; %.preheader1.i.i.i62
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v17, s12 :: v_dual_mov_b32 v18, s13
	s_sleep 1
	global_store_b64 v[7:8], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[17:20], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[19:20]
	v_dual_mov_b32 v20, v12 :: v_dual_mov_b32 v19, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_242
.LBB1_243:                              ; %Flow468
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_245
; %bb.244:                              ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_245:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_247
; %bb.246:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_247:                              ; %Flow469
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v21, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_248:                              ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_250
; %bb.249:                              ;   in Loop: Header=BB1_248 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_250:                              ;   in Loop: Header=BB1_248 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_252
; %bb.251:                              ;   in Loop: Header=BB1_248 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_253
.LBB1_252:                              ;   in Loop: Header=BB1_248 Depth=2
	s_mov_b32 s1, -1
.LBB1_253:                              ; %Flow463
                                        ;   in Loop: Header=BB1_248 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_248
; %bb.254:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[14:15], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_258
; %bb.255:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11] offset:24 glc
	global_load_b64 v[11:12], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v20, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v18, vcc_lo, s13, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[17:18]
	v_dual_cndmask_b32 v18, v18, v19 :: v_dual_cndmask_b32 v17, v17, v1
	v_mov_b32_e32 v19, v7
	v_and_b32_e32 v1, v18, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v17, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[19:20], v2, v[17:20], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[19:20], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_258
; %bb.256:                              ; %.preheader.i.i.i61.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_257:                              ; %.preheader.i.i.i61
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[17:20], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[19:20]
	v_dual_mov_b32 v20, v8 :: v_dual_mov_b32 v19, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_257
.LBB1_258:                              ; %__ockl_printf_append_args.exit65
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_264
; %bb.259:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[19:20], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v20
	v_and_b32_e32 v3, v3, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[17:18], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[17:20], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[19:20]
	s_cbranch_execz .LBB1_263
; %bb.260:                              ; %.preheader3.i.i.i72.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_261:                              ; %.preheader3.i.i.i72
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[11:12], v2, s[10:11]
	v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v19
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[17:18], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[17:20], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[19:20]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_261
; %bb.262:                              ; %Flow456
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_263:                              ; %Flow458
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_264:                              ; %.loopexit4.i.i.i66
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b128 v[18:21], v2, s[10:11]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_266
; %bb.265:                              ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v18, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v19, vcc_lo
	global_store_b128 v[3:4], v[7:10], off offset:8
.LBB1_266:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v20, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v21, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v14, 0xffffff1f, v14, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_mov_b32_e32 v17, v2
	v_dual_mov_b32 v23, s7 :: v_dual_mov_b32 v20, s4
	v_dual_mov_b32 v22, s6 :: v_dual_mov_b32 v21, s5
	s_clause 0x3
	global_store_b128 v[3:4], v[14:17], off
	global_store_b128 v[3:4], v[20:23], off offset:16
	global_store_b128 v[3:4], v[20:23], off offset:32
	global_store_b128 v[3:4], v[20:23], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_274
; %bb.267:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[22:23], v2, s[10:11] offset:32 glc
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	v_dual_mov_b32 v20, s12 :: v_dual_mov_b32 v21, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v7, vcc_lo, v18, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v19, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[7:8], v[22:23], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[20:23], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[16:17], v[22:23]
	s_cbranch_execz .LBB1_270
; %bb.268:                              ; %.preheader1.i.i.i70.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_269:                              ; %.preheader1.i.i.i70
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
	s_sleep 1
	global_store_b64 v[7:8], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[14:17], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[16:17]
	v_dual_mov_b32 v17, v12 :: v_dual_mov_b32 v16, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_269
.LBB1_270:                              ; %Flow454
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_272
; %bb.271:                              ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB1_272:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB1_274
; %bb.273:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_274:                              ; %Flow455
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v18, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB1_275:                              ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_277
; %bb.276:                              ;   in Loop: Header=BB1_275 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_277:                              ;   in Loop: Header=BB1_275 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_279
; %bb.278:                              ;   in Loop: Header=BB1_275 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_280
.LBB1_279:                              ;   in Loop: Header=BB1_275 Depth=2
	s_mov_b32 s1, -1
.LBB1_280:                              ; %Flow449
                                        ;   in Loop: Header=BB1_275 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_275
; %bb.281:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[11:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_285
; %bb.282:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11] offset:24 glc
	global_load_b64 v[16:17], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v18 :: v_dual_cndmask_b32 v14, v14, v1
	v_and_b32_e32 v1, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v14, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v16, v3
	v_mov_b32_e32 v16, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v17, v1, vcc_lo
	v_mov_b32_e32 v17, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[14:17], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_285
; %bb.283:                              ; %.preheader.i.i.i69.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_284:                              ; %.preheader.i.i.i69
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[14:17], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[16:17]
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v16, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_284
.LBB1_285:                              ; %__ockl_printf_append_args.exit73
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v47
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_291
; %bb.286:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b64 v[16:17], v2, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v17
	v_and_b32_e32 v3, v3, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v14, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v14, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[16:17]
	s_cbranch_execz .LBB1_290
; %bb.287:                              ; %.preheader3.i.i.i80.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s6, 0
.LBB1_288:                              ; %.preheader3.i.i.i80
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b64 v[14:15], v2, s[10:11]
	v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v16, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v16
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[14:15]
	v_and_b32_e32 v14, v8, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v14, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[16:17]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_288
; %bb.289:                              ; %Flow442
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_290:                              ; %Flow444
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_291:                              ; %.loopexit4.i.i.i74
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[10:11] offset:40
	global_load_b128 v[15:18], v2, s[10:11]
	v_readfirstlane_b32 s12, v3
	v_readfirstlane_b32 s13, v4
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB1_293
; %bb.292:                              ;   in Loop: Header=BB1_4 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v2
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v16, vcc_lo
	global_store_b128 v[3:4], v[7:10], off offset:8
.LBB1_293:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v17, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v18, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v11, 0xffffff1d, v11, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_mov_b32_e32 v14, v2
	v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v17, s4
	v_dual_mov_b32 v19, s6 :: v_dual_mov_b32 v18, s5
	s_clause 0x3
	global_store_b128 v[3:4], v[11:14], off
	global_store_b128 v[3:4], v[17:20], off offset:16
	global_store_b128 v[3:4], v[17:20], off offset:32
	global_store_b128 v[3:4], v[17:20], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB1_301
; %bb.294:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x1
	global_load_b64 v[19:20], v2, s[10:11] offset:32 glc
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	v_dual_mov_b32 v17, s12 :: v_dual_mov_b32 v18, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v3
	v_readfirstlane_b32 s7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v3, vcc_lo, v15, s6
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v16, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[3:4], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[17:20], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB1_297
; %bb.295:                              ; %.preheader1.i.i.i78.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s7, 0
.LBB1_296:                              ; %.preheader1.i.i.i78
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_296
.LBB1_297:                              ; %Flow440
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[3:4], v2, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v1, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB1_299
; %bb.298:                              ;   in Loop: Header=BB1_4 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB1_299:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB1_301
; %bb.300:                              ;   in Loop: Header=BB1_4 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_301:                              ; %Flow441
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v1, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v4, vcc_lo, s14, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB1_302:                              ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_304
; %bb.303:                              ;   in Loop: Header=BB1_302 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB1_304:                              ;   in Loop: Header=BB1_302 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_306
; %bb.305:                              ;   in Loop: Header=BB1_302 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_307
.LBB1_306:                              ;   in Loop: Header=BB1_302 Depth=2
	s_mov_b32 s1, -1
.LBB1_307:                              ; %Flow435
                                        ;   in Loop: Header=BB1_302 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_302
; %bb.308:                              ;   in Loop: Header=BB1_4 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_312
; %bb.309:                              ;   in Loop: Header=BB1_4 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[10:11] offset:40
	global_load_b64 v[7:8], v2, s[10:11] offset:24 glc
	global_load_b64 v[13:14], v2, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s12
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v1
	v_and_b32_e32 v1, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v11, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_312
; %bb.310:                              ; %.preheader.i.i.i77.preheader
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_mov_b32 s0, 0
.LBB1_311:                              ; %.preheader.i.i.i77
                                        ;   Parent Loop BB1_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_311
.LBB1_312:                              ; %__ockl_printf_append_args.exit81
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b32 v1, v[43:44], off
	global_load_b32 v3, v[45:46], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v3, v1
	global_store_b32 v[43:44], v1, off
.LBB1_313:                              ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_lshr_b32 s0, s21, 1
	s_cmp_lt_u32 s21, 2
	s_mov_b32 s21, s0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_4
.LBB1_314:                              ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21globalReductionKernelPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 48
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z21globalReductionKernelPi, .Lfunc_end1-_Z21globalReductionKernelPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 13516
; NumSgprs: 28
; NumVgprs: 48
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 48
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"Id=%d niz[%d]=niz[%d]+niz[%d] => %d + %d\n"
	.size	.str, 42

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20localReductionKernelPi
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z20localReductionKernelPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         88
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21globalReductionKernelPi
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z21globalReductionKernelPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     48
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
