#include "cudaCode.cuh"

__device__ int x_error, y_error;
__device__ int errorFlag = 0;
__device__ int errorCode;

__device__ void nanException(int x, int y, int e) {
  errorFlag = 1;
  errorCode = e;
  x_error = x;
  y_error = y;
  asm("trap;");
}

__global__ void calcRhoGPU(float* data, float* rhos) {
  int tid = blockDim.x*blockIdx.x+threadIdx.x + yOffset[0];
  if (tid < gridIter[0]) {
    float result = 0;
    for(int i = 0; i<q; i++) {
      result += data[i*nNodes[0]+tid];
    }
    rhos[tid] = result;
  }
}

__global__ void calcVelGPU(float* data, float* vels, float* usqrs, float* rhos) {

  int tid = blockDim.x*blockIdx.x+threadIdx.x + yOffset[0];

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    float ux;
    float uy;
    float uxPlus;
    float uyPlus;
    float uxMinus;
    float uyMinus;
    uxPlus = data[1*thisnNodes+tid] + data[5*thisnNodes+tid] + data[8*thisnNodes+tid];
    uyPlus = data[2*thisnNodes+tid] + data[5*thisnNodes+tid] + data[6*thisnNodes+tid];
    uxMinus = data[3*thisnNodes+tid] + data[6*thisnNodes+tid] + data[7*thisnNodes+tid];
    uyMinus = data[4*thisnNodes+tid] + data[7*thisnNodes+tid] + data[8*thisnNodes+tid];
    ux = (uxPlus - uxMinus)/rhos[tid];
    uy = (uyPlus - uyMinus)/rhos[tid];
    vels[tid] = ux;
    vels[thisnNodes+tid] = uy;
    usqrs[tid] = ux*ux + uy*uy;
  }
}

__global__ void calcEquilibriumGPU(float* equis, float* rhos, float* vels, float* usqrs) {

  int tid = blockDim.x*blockIdx.x+threadIdx.x + yOffset[0];

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    float ux = vels[tid];
    float uy = vels[thisnNodes+tid];
    float uSqr = usqrs[tid];
    float rho = rhos[tid];
    for (int i=0; i<q; i++) {
      float velDot = velCol0[i]*ux + velCol1[i]*uy;
      float result = rho * weights[i] * (1.0 + 3.0*velDot + 4.5*velDot*velDot - 1.5*uSqr);
      equis[i*thisnNodes+tid] = result;
    }
  }
}

__global__ void BGKCollideGPU(float* data, float* equis, int* nodeMap) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x + yOffset[0];

  if (tid < gridIter[0]) {
    if (nodeMap[tid] == 0) {
      int thisnNodes = nNodes[0];
      for (int i = 0; i<q; i++) {
        data[i*thisnNodes+tid] *= (1.0 - omega[0]);
        data[i*thisnNodes+tid] += omega[0]*equis[i*thisnNodes+tid];
      }
    }
  }
}

__global__ void bounceBackGPU(float* data, int* nodeMap) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x + yOffset[0];

  if (tid<gridIter[0]) {
    int thisnNodes = nNodes[0];
    float oldVels[q];
    if (nodeMap[tid] == 1) {
      for (int i = 0; i<q; i++) {
        float tmpResult = data[i*thisnNodes+tid];
        // if (tmpResult != tmpResult) {
        //   nanException(tid%lx, tid/lx, 3);
        // }
        oldVels[i] = tmpResult;
      }
      for (int i = 0; i<q; i++) {
        data[i*thisnNodes+tid] = oldVels[bounceBackMap[i]];
      }
    }
  }
}

__global__ void streamGPU(float* outData, float* inData) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x + yOffset[0];

  //Avoid streaming the special first and last column.
  //Probably best avoided by just no-oping those threads.

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    int thisLx = lx[0];
    int x = tid % thisLx;
    if (x != 0 || x != thisLx-1) {
      for (int i = 0; i<q; i++) {
        float tmpResult = inData[i*thisnNodes + tid];
        int dst = i*thisnNodes + tid + velColInt1[i]*thisLx + velColInt0[i];
        outData[dst] = tmpResult;
      }
    }
  }
}

__global__ void streamInGPU(float* outData, float* inData, float* inFlow) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x;

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    int thisLx = lx[0];
    int thisLy = ly[0];
    int node = tid*thisLx + yOffset[0];
    int y = tid + 1;
    outData[5*thisnNodes+node] = inFlow[(thisLy+2)*5+y];
    outData[1*thisnNodes+node] = inFlow[(thisLy+2)*1+y];
    outData[8*thisnNodes+node] = inFlow[(thisLy+2)*8+y];

    outData[2*thisnNodes+node] = inData[2*thisnNodes+node-thisLx];
    outData[4*thisnNodes+node] = inData[4*thisnNodes+node+thisLx];

    outData[5*thisnNodes+node+1] = inData[5*thisnNodes+node-thisLx];
    outData[1*thisnNodes+node+1] = inData[1*thisnNodes+node];
    outData[8*thisnNodes+node+1] = inData[8*thisnNodes+node+thisLx];
  }
}

__global__ void streamOutGPU(float* outData, float* inData, float* inFlow) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x;

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    int thisLx = lx[0];
    int thisLy = ly[0];
    int node = tid*thisLx + yOffset[0] + thisLx-1;
    int y = node / thisLx;
    outData[6*thisnNodes+node] = inFlow[(thisLy+2)*6+y];
    outData[3*thisnNodes+node] = inFlow[(thisLy+2)*3+y];
    outData[7*thisnNodes+node] = inFlow[(thisLy+2)*7+y];

    outData[2*thisnNodes+node] = inData[2*thisnNodes+node-thisLx];
    outData[4*thisnNodes+node] = inData[4*thisnNodes+node+thisLx];

    outData[6*thisnNodes+node-1] = inData[6*thisnNodes+node-thisLx];
    outData[3*thisnNodes+node-1] = inData[3*thisnNodes+node];
    outData[7*thisnNodes+node-1] = inData[7*thisnNodes+node+thisLx];
  }
}
	.file	"tmpxft_0034912e_00000000-6_cudaCode.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12nanExceptioniii
	.type	_Z12nanExceptioniii, @function
_Z12nanExceptioniii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z12nanExceptioniii, .-_Z12nanExceptioniii
	.globl	_Z32__device_stub__Z10calcRhoGPUPfS_PfS_
	.type	_Z32__device_stub__Z10calcRhoGPUPfS_PfS_, @function
_Z32__device_stub__Z10calcRhoGPUPfS_PfS_:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10calcRhoGPUPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z32__device_stub__Z10calcRhoGPUPfS_PfS_, .-_Z32__device_stub__Z10calcRhoGPUPfS_PfS_
	.globl	_Z10calcRhoGPUPfS_
	.type	_Z10calcRhoGPUPfS_, @function
_Z10calcRhoGPUPfS_:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10calcRhoGPUPfS_PfS_
	.cfi_endproc
.LFE2034:
	.size	_Z10calcRhoGPUPfS_, .-_Z10calcRhoGPUPfS_
	.globl	_Z36__device_stub__Z10calcVelGPUPfS_S_S_PfS_S_S_
	.type	_Z36__device_stub__Z10calcVelGPUPfS_S_S_PfS_S_S_, @function
_Z36__device_stub__Z10calcVelGPUPfS_S_S_PfS_S_S_:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10calcVelGPUPfS_S_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z36__device_stub__Z10calcVelGPUPfS_S_S_PfS_S_S_, .-_Z36__device_stub__Z10calcVelGPUPfS_S_S_PfS_S_S_
	.globl	_Z10calcVelGPUPfS_S_S_
	.type	_Z10calcVelGPUPfS_S_S_, @function
_Z10calcVelGPUPfS_S_S_:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10calcVelGPUPfS_S_S_PfS_S_S_
	.cfi_endproc
.LFE2036:
	.size	_Z10calcVelGPUPfS_S_S_, .-_Z10calcVelGPUPfS_S_S_
	.globl	_Z44__device_stub__Z18calcEquilibriumGPUPfS_S_S_PfS_S_S_
	.type	_Z44__device_stub__Z18calcEquilibriumGPUPfS_S_S_PfS_S_S_, @function
_Z44__device_stub__Z18calcEquilibriumGPUPfS_S_S_PfS_S_S_:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18calcEquilibriumGPUPfS_S_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z44__device_stub__Z18calcEquilibriumGPUPfS_S_S_PfS_S_S_, .-_Z44__device_stub__Z18calcEquilibriumGPUPfS_S_S_PfS_S_S_
	.globl	_Z18calcEquilibriumGPUPfS_S_S_
	.type	_Z18calcEquilibriumGPUPfS_S_S_, @function
_Z18calcEquilibriumGPUPfS_S_S_:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z18calcEquilibriumGPUPfS_S_S_PfS_S_S_
	.cfi_endproc
.LFE2038:
	.size	_Z18calcEquilibriumGPUPfS_S_S_, .-_Z18calcEquilibriumGPUPfS_S_S_
	.globl	_Z37__device_stub__Z13BGKCollideGPUPfS_PiPfS_Pi
	.type	_Z37__device_stub__Z13BGKCollideGPUPfS_PiPfS_Pi, @function
_Z37__device_stub__Z13BGKCollideGPUPfS_PiPfS_Pi:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z13BGKCollideGPUPfS_Pi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L20:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z37__device_stub__Z13BGKCollideGPUPfS_PiPfS_Pi, .-_Z37__device_stub__Z13BGKCollideGPUPfS_PiPfS_Pi
	.globl	_Z13BGKCollideGPUPfS_Pi
	.type	_Z13BGKCollideGPUPfS_Pi, @function
_Z13BGKCollideGPUPfS_Pi:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13BGKCollideGPUPfS_PiPfS_Pi
	.cfi_endproc
.LFE2040:
	.size	_Z13BGKCollideGPUPfS_Pi, .-_Z13BGKCollideGPUPfS_Pi
	.globl	_Z35__device_stub__Z13bounceBackGPUPfPiPfPi
	.type	_Z35__device_stub__Z13bounceBackGPUPfPiPfPi, @function
_Z35__device_stub__Z13bounceBackGPUPfPiPfPi:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13bounceBackGPUPfPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L25:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z35__device_stub__Z13bounceBackGPUPfPiPfPi, .-_Z35__device_stub__Z13bounceBackGPUPfPiPfPi
	.globl	_Z13bounceBackGPUPfPi
	.type	_Z13bounceBackGPUPfPi, @function
_Z13bounceBackGPUPfPi:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z13bounceBackGPUPfPiPfPi
	.cfi_endproc
.LFE2042:
	.size	_Z13bounceBackGPUPfPi, .-_Z13bounceBackGPUPfPi
	.globl	_Z30__device_stub__Z9streamGPUPfS_PfS_
	.type	_Z30__device_stub__Z9streamGPUPfS_PfS_, @function
_Z30__device_stub__Z9streamGPUPfS_PfS_:
.LFB2043:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9streamGPUPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L30:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z30__device_stub__Z9streamGPUPfS_PfS_, .-_Z30__device_stub__Z9streamGPUPfS_PfS_
	.globl	_Z9streamGPUPfS_
	.type	_Z9streamGPUPfS_, @function
_Z9streamGPUPfS_:
.LFB2044:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z9streamGPUPfS_PfS_
	.cfi_endproc
.LFE2044:
	.size	_Z9streamGPUPfS_, .-_Z9streamGPUPfS_
	.globl	_Z35__device_stub__Z11streamInGPUPfS_S_PfS_S_
	.type	_Z35__device_stub__Z11streamInGPUPfS_S_PfS_S_, @function
_Z35__device_stub__Z11streamInGPUPfS_S_PfS_S_:
.LFB2045:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z11streamInGPUPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L35:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_Z35__device_stub__Z11streamInGPUPfS_S_PfS_S_, .-_Z35__device_stub__Z11streamInGPUPfS_S_PfS_S_
	.globl	_Z11streamInGPUPfS_S_
	.type	_Z11streamInGPUPfS_S_, @function
_Z11streamInGPUPfS_S_:
.LFB2046:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z11streamInGPUPfS_S_PfS_S_
	.cfi_endproc
.LFE2046:
	.size	_Z11streamInGPUPfS_S_, .-_Z11streamInGPUPfS_S_
	.globl	_Z36__device_stub__Z12streamOutGPUPfS_S_PfS_S_
	.type	_Z36__device_stub__Z12streamOutGPUPfS_S_PfS_S_, @function
_Z36__device_stub__Z12streamOutGPUPfS_S_PfS_S_:
.LFB2047:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12streamOutGPUPfS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L40:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2047:
	.size	_Z36__device_stub__Z12streamOutGPUPfS_S_PfS_S_, .-_Z36__device_stub__Z12streamOutGPUPfS_S_PfS_S_
	.globl	_Z12streamOutGPUPfS_S_
	.type	_Z12streamOutGPUPfS_S_, @function
_Z12streamOutGPUPfS_S_:
.LFB2048:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12streamOutGPUPfS_S_PfS_S_
	.cfi_endproc
.LFE2048:
	.size	_Z12streamOutGPUPfS_S_, .-_Z12streamOutGPUPfS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12streamOutGPUPfS_S_"
.LC1:
	.string	"_Z11streamInGPUPfS_S_"
.LC2:
	.string	"_Z9streamGPUPfS_"
.LC3:
	.string	"_Z13bounceBackGPUPfPi"
.LC4:
	.string	"_Z13BGKCollideGPUPfS_Pi"
.LC5:
	.string	"_Z18calcEquilibriumGPUPfS_S_S_"
.LC6:
	.string	"_Z10calcVelGPUPfS_S_S_"
.LC7:
	.string	"_Z10calcRhoGPUPfS_"
.LC8:
	.string	"velCol0"
.LC9:
	.string	"velCol1"
.LC10:
	.string	"velColInt0"
.LC11:
	.string	"velColInt1"
.LC12:
	.string	"weights"
.LC13:
	.string	"bounceBackMap"
.LC14:
	.string	"omega"
.LC15:
	.string	"lx"
.LC16:
	.string	"ly"
.LC17:
	.string	"yOffset"
.LC18:
	.string	"gridIter"
.LC19:
	.string	"nNodes"
.LC20:
	.string	"x_error"
.LC21:
	.string	"y_error"
.LC22:
	.string	"errorFlag"
.LC23:
	.string	"errorCode"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2050:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12streamOutGPUPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11streamInGPUPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9streamGPUPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13bounceBackGPUPfPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13BGKCollideGPUPfS_Pi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18calcEquilibriumGPUPfS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10calcVelGPUPfS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10calcRhoGPUPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$36, %r9d
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	_ZL7velCol0(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL7velCol1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL10velColInt0(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL10velColInt1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL7weights(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL13bounceBackMap(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL5omega(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL2lx(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL2ly(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL7yOffset(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL8gridIter(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL6nNodes(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL7x_error(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL7y_error(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9errorFlag(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9errorCode(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2050:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL9errorCode
	.comm	_ZL9errorCode,4,4
	.local	_ZL9errorFlag
	.comm	_ZL9errorFlag,4,4
	.local	_ZL7y_error
	.comm	_ZL7y_error,4,4
	.local	_ZL7x_error
	.comm	_ZL7x_error,4,4
	.local	_ZL6nNodes
	.comm	_ZL6nNodes,4,4
	.local	_ZL8gridIter
	.comm	_ZL8gridIter,4,4
	.local	_ZL7yOffset
	.comm	_ZL7yOffset,4,4
	.local	_ZL2ly
	.comm	_ZL2ly,4,4
	.local	_ZL2lx
	.comm	_ZL2lx,4,4
	.local	_ZL5omega
	.comm	_ZL5omega,4,4
	.local	_ZL13bounceBackMap
	.comm	_ZL13bounceBackMap,36,32
	.local	_ZL7weights
	.comm	_ZL7weights,36,32
	.local	_ZL10velColInt1
	.comm	_ZL10velColInt1,36,32
	.local	_ZL10velColInt0
	.comm	_ZL10velColInt0,36,32
	.local	_ZL7velCol1
	.comm	_ZL7velCol1,36,32
	.local	_ZL7velCol0
	.comm	_ZL7velCol0,36,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "cudaCode.cuh"

__device__ int x_error, y_error;
__device__ int errorFlag = 0;
__device__ int errorCode;

__device__ void nanException(int x, int y, int e) {
  errorFlag = 1;
  errorCode = e;
  x_error = x;
  y_error = y;
  asm("trap;");
}

__global__ void calcRhoGPU(float* data, float* rhos) {
  int tid = blockDim.x*blockIdx.x+threadIdx.x + yOffset[0];
  if (tid < gridIter[0]) {
    float result = 0;
    for(int i = 0; i<q; i++) {
      result += data[i*nNodes[0]+tid];
    }
    rhos[tid] = result;
  }
}

__global__ void calcVelGPU(float* data, float* vels, float* usqrs, float* rhos) {

  int tid = blockDim.x*blockIdx.x+threadIdx.x + yOffset[0];

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    float ux;
    float uy;
    float uxPlus;
    float uyPlus;
    float uxMinus;
    float uyMinus;
    uxPlus = data[1*thisnNodes+tid] + data[5*thisnNodes+tid] + data[8*thisnNodes+tid];
    uyPlus = data[2*thisnNodes+tid] + data[5*thisnNodes+tid] + data[6*thisnNodes+tid];
    uxMinus = data[3*thisnNodes+tid] + data[6*thisnNodes+tid] + data[7*thisnNodes+tid];
    uyMinus = data[4*thisnNodes+tid] + data[7*thisnNodes+tid] + data[8*thisnNodes+tid];
    ux = (uxPlus - uxMinus)/rhos[tid];
    uy = (uyPlus - uyMinus)/rhos[tid];
    vels[tid] = ux;
    vels[thisnNodes+tid] = uy;
    usqrs[tid] = ux*ux + uy*uy;
  }
}

__global__ void calcEquilibriumGPU(float* equis, float* rhos, float* vels, float* usqrs) {

  int tid = blockDim.x*blockIdx.x+threadIdx.x + yOffset[0];

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    float ux = vels[tid];
    float uy = vels[thisnNodes+tid];
    float uSqr = usqrs[tid];
    float rho = rhos[tid];
    for (int i=0; i<q; i++) {
      float velDot = velCol0[i]*ux + velCol1[i]*uy;
      float result = rho * weights[i] * (1.0 + 3.0*velDot + 4.5*velDot*velDot - 1.5*uSqr);
      equis[i*thisnNodes+tid] = result;
    }
  }
}

__global__ void BGKCollideGPU(float* data, float* equis, int* nodeMap) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x + yOffset[0];

  if (tid < gridIter[0]) {
    if (nodeMap[tid] == 0) {
      int thisnNodes = nNodes[0];
      for (int i = 0; i<q; i++) {
        data[i*thisnNodes+tid] *= (1.0 - omega[0]);
        data[i*thisnNodes+tid] += omega[0]*equis[i*thisnNodes+tid];
      }
    }
  }
}

__global__ void bounceBackGPU(float* data, int* nodeMap) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x + yOffset[0];

  if (tid<gridIter[0]) {
    int thisnNodes = nNodes[0];
    float oldVels[q];
    if (nodeMap[tid] == 1) {
      for (int i = 0; i<q; i++) {
        float tmpResult = data[i*thisnNodes+tid];
        // if (tmpResult != tmpResult) {
        //   nanException(tid%lx, tid/lx, 3);
        // }
        oldVels[i] = tmpResult;
      }
      for (int i = 0; i<q; i++) {
        data[i*thisnNodes+tid] = oldVels[bounceBackMap[i]];
      }
    }
  }
}

__global__ void streamGPU(float* outData, float* inData) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x + yOffset[0];

  //Avoid streaming the special first and last column.
  //Probably best avoided by just no-oping those threads.

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    int thisLx = lx[0];
    int x = tid % thisLx;
    if (x != 0 || x != thisLx-1) {
      for (int i = 0; i<q; i++) {
        float tmpResult = inData[i*thisnNodes + tid];
        int dst = i*thisnNodes + tid + velColInt1[i]*thisLx + velColInt0[i];
        outData[dst] = tmpResult;
      }
    }
  }
}

__global__ void streamInGPU(float* outData, float* inData, float* inFlow) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x;

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    int thisLx = lx[0];
    int thisLy = ly[0];
    int node = tid*thisLx + yOffset[0];
    int y = tid + 1;
    outData[5*thisnNodes+node] = inFlow[(thisLy+2)*5+y];
    outData[1*thisnNodes+node] = inFlow[(thisLy+2)*1+y];
    outData[8*thisnNodes+node] = inFlow[(thisLy+2)*8+y];

    outData[2*thisnNodes+node] = inData[2*thisnNodes+node-thisLx];
    outData[4*thisnNodes+node] = inData[4*thisnNodes+node+thisLx];

    outData[5*thisnNodes+node+1] = inData[5*thisnNodes+node-thisLx];
    outData[1*thisnNodes+node+1] = inData[1*thisnNodes+node];
    outData[8*thisnNodes+node+1] = inData[8*thisnNodes+node+thisLx];
  }
}

__global__ void streamOutGPU(float* outData, float* inData, float* inFlow) {

  int tid = blockIdx.x*blockDim.x + threadIdx.x;

  if (tid < gridIter[0]) {
    int thisnNodes = nNodes[0];
    int thisLx = lx[0];
    int thisLy = ly[0];
    int node = tid*thisLx + yOffset[0] + thisLx-1;
    int y = node / thisLx;
    outData[6*thisnNodes+node] = inFlow[(thisLy+2)*6+y];
    outData[3*thisnNodes+node] = inFlow[(thisLy+2)*3+y];
    outData[7*thisnNodes+node] = inFlow[(thisLy+2)*7+y];

    outData[2*thisnNodes+node] = inData[2*thisnNodes+node-thisLx];
    outData[4*thisnNodes+node] = inData[4*thisnNodes+node+thisLx];

    outData[6*thisnNodes+node-1] = inData[6*thisnNodes+node-thisLx];
    outData[3*thisnNodes+node-1] = inData[3*thisnNodes+node];
    outData[7*thisnNodes+node-1] = inData[7*thisnNodes+node+thisLx];
  }
}
	.text
	.file	"cudaCode.hip"
	.globl	_Z25__device_stub__calcRhoGPUPfS_ # -- Begin function _Z25__device_stub__calcRhoGPUPfS_
	.type	_Z25__device_stub__calcRhoGPUPfS_,@function
_Z25__device_stub__calcRhoGPUPfS_:      # @_Z25__device_stub__calcRhoGPUPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10calcRhoGPUPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__calcRhoGPUPfS_, .Lfunc_end0-_Z25__device_stub__calcRhoGPUPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__calcVelGPUPfS_S_S_ # -- Begin function _Z25__device_stub__calcVelGPUPfS_S_S_
	.type	_Z25__device_stub__calcVelGPUPfS_S_S_,@function
_Z25__device_stub__calcVelGPUPfS_S_S_:  # @_Z25__device_stub__calcVelGPUPfS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10calcVelGPUPfS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__calcVelGPUPfS_S_S_, .Lfunc_end1-_Z25__device_stub__calcVelGPUPfS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__calcEquilibriumGPUPfS_S_S_ # -- Begin function _Z33__device_stub__calcEquilibriumGPUPfS_S_S_
	.type	_Z33__device_stub__calcEquilibriumGPUPfS_S_S_,@function
_Z33__device_stub__calcEquilibriumGPUPfS_S_S_: # @_Z33__device_stub__calcEquilibriumGPUPfS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18calcEquilibriumGPUPfS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z33__device_stub__calcEquilibriumGPUPfS_S_S_, .Lfunc_end2-_Z33__device_stub__calcEquilibriumGPUPfS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__BGKCollideGPUPfS_Pi # -- Begin function _Z28__device_stub__BGKCollideGPUPfS_Pi
	.type	_Z28__device_stub__BGKCollideGPUPfS_Pi,@function
_Z28__device_stub__BGKCollideGPUPfS_Pi: # @_Z28__device_stub__BGKCollideGPUPfS_Pi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13BGKCollideGPUPfS_Pi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__BGKCollideGPUPfS_Pi, .Lfunc_end3-_Z28__device_stub__BGKCollideGPUPfS_Pi
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__bounceBackGPUPfPi # -- Begin function _Z28__device_stub__bounceBackGPUPfPi
	.type	_Z28__device_stub__bounceBackGPUPfPi,@function
_Z28__device_stub__bounceBackGPUPfPi:   # @_Z28__device_stub__bounceBackGPUPfPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13bounceBackGPUPfPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z28__device_stub__bounceBackGPUPfPi, .Lfunc_end4-_Z28__device_stub__bounceBackGPUPfPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__streamGPUPfS_ # -- Begin function _Z24__device_stub__streamGPUPfS_
	.type	_Z24__device_stub__streamGPUPfS_,@function
_Z24__device_stub__streamGPUPfS_:       # @_Z24__device_stub__streamGPUPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9streamGPUPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z24__device_stub__streamGPUPfS_, .Lfunc_end5-_Z24__device_stub__streamGPUPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__streamInGPUPfS_S_ # -- Begin function _Z26__device_stub__streamInGPUPfS_S_
	.type	_Z26__device_stub__streamInGPUPfS_S_,@function
_Z26__device_stub__streamInGPUPfS_S_:   # @_Z26__device_stub__streamInGPUPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11streamInGPUPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z26__device_stub__streamInGPUPfS_S_, .Lfunc_end6-_Z26__device_stub__streamInGPUPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__streamOutGPUPfS_S_ # -- Begin function _Z27__device_stub__streamOutGPUPfS_S_
	.type	_Z27__device_stub__streamOutGPUPfS_S_,@function
_Z27__device_stub__streamOutGPUPfS_S_:  # @_Z27__device_stub__streamOutGPUPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12streamOutGPUPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z27__device_stub__streamOutGPUPfS_S_, .Lfunc_end7-_Z27__device_stub__streamOutGPUPfS_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10calcRhoGPUPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10calcVelGPUPfS_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18calcEquilibriumGPUPfS_S_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13BGKCollideGPUPfS_Pi, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13bounceBackGPUPfPi, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9streamGPUPfS_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11streamInGPUPfS_S_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12streamOutGPUPfS_S_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$velCol0, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$velCol1, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$velColInt0, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$velColInt1, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$weights, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bounceBackMap, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$omega, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$lx, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ly, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$yOffset, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$gridIter, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$nNodes, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$x_error, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$y_error, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$errorFlag, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$errorCode, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	velCol0,@object                 # @velCol0
	.local	velCol0
	.comm	velCol0,36,16
	.type	velCol1,@object                 # @velCol1
	.local	velCol1
	.comm	velCol1,36,16
	.type	velColInt0,@object              # @velColInt0
	.local	velColInt0
	.comm	velColInt0,36,16
	.type	velColInt1,@object              # @velColInt1
	.local	velColInt1
	.comm	velColInt1,36,16
	.type	weights,@object                 # @weights
	.local	weights
	.comm	weights,36,16
	.type	bounceBackMap,@object           # @bounceBackMap
	.local	bounceBackMap
	.comm	bounceBackMap,36,16
	.type	omega,@object                   # @omega
	.local	omega
	.comm	omega,4,4
	.type	lx,@object                      # @lx
	.local	lx
	.comm	lx,4,4
	.type	ly,@object                      # @ly
	.local	ly
	.comm	ly,4,4
	.type	yOffset,@object                 # @yOffset
	.local	yOffset
	.comm	yOffset,4,4
	.type	gridIter,@object                # @gridIter
	.local	gridIter
	.comm	gridIter,4,4
	.type	nNodes,@object                  # @nNodes
	.local	nNodes
	.comm	nNodes,4,4
	.type	x_error,@object                 # @x_error
	.local	x_error
	.comm	x_error,4,4
	.type	y_error,@object                 # @y_error
	.local	y_error
	.comm	y_error,4,4
	.type	errorFlag,@object               # @errorFlag
	.local	errorFlag
	.comm	errorFlag,4,4
	.type	errorCode,@object               # @errorCode
	.local	errorCode
	.comm	errorCode,4,4
	.type	_Z10calcRhoGPUPfS_,@object      # @_Z10calcRhoGPUPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z10calcRhoGPUPfS_
	.p2align	3, 0x0
_Z10calcRhoGPUPfS_:
	.quad	_Z25__device_stub__calcRhoGPUPfS_
	.size	_Z10calcRhoGPUPfS_, 8

	.type	_Z10calcVelGPUPfS_S_S_,@object  # @_Z10calcVelGPUPfS_S_S_
	.globl	_Z10calcVelGPUPfS_S_S_
	.p2align	3, 0x0
_Z10calcVelGPUPfS_S_S_:
	.quad	_Z25__device_stub__calcVelGPUPfS_S_S_
	.size	_Z10calcVelGPUPfS_S_S_, 8

	.type	_Z18calcEquilibriumGPUPfS_S_S_,@object # @_Z18calcEquilibriumGPUPfS_S_S_
	.globl	_Z18calcEquilibriumGPUPfS_S_S_
	.p2align	3, 0x0
_Z18calcEquilibriumGPUPfS_S_S_:
	.quad	_Z33__device_stub__calcEquilibriumGPUPfS_S_S_
	.size	_Z18calcEquilibriumGPUPfS_S_S_, 8

	.type	_Z13BGKCollideGPUPfS_Pi,@object # @_Z13BGKCollideGPUPfS_Pi
	.globl	_Z13BGKCollideGPUPfS_Pi
	.p2align	3, 0x0
_Z13BGKCollideGPUPfS_Pi:
	.quad	_Z28__device_stub__BGKCollideGPUPfS_Pi
	.size	_Z13BGKCollideGPUPfS_Pi, 8

	.type	_Z13bounceBackGPUPfPi,@object   # @_Z13bounceBackGPUPfPi
	.globl	_Z13bounceBackGPUPfPi
	.p2align	3, 0x0
_Z13bounceBackGPUPfPi:
	.quad	_Z28__device_stub__bounceBackGPUPfPi
	.size	_Z13bounceBackGPUPfPi, 8

	.type	_Z9streamGPUPfS_,@object        # @_Z9streamGPUPfS_
	.globl	_Z9streamGPUPfS_
	.p2align	3, 0x0
_Z9streamGPUPfS_:
	.quad	_Z24__device_stub__streamGPUPfS_
	.size	_Z9streamGPUPfS_, 8

	.type	_Z11streamInGPUPfS_S_,@object   # @_Z11streamInGPUPfS_S_
	.globl	_Z11streamInGPUPfS_S_
	.p2align	3, 0x0
_Z11streamInGPUPfS_S_:
	.quad	_Z26__device_stub__streamInGPUPfS_S_
	.size	_Z11streamInGPUPfS_S_, 8

	.type	_Z12streamOutGPUPfS_S_,@object  # @_Z12streamOutGPUPfS_S_
	.globl	_Z12streamOutGPUPfS_S_
	.p2align	3, 0x0
_Z12streamOutGPUPfS_S_:
	.quad	_Z27__device_stub__streamOutGPUPfS_S_
	.size	_Z12streamOutGPUPfS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10calcRhoGPUPfS_"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10calcVelGPUPfS_S_S_"
	.size	.L__unnamed_2, 23

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z18calcEquilibriumGPUPfS_S_S_"
	.size	.L__unnamed_3, 31

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z13BGKCollideGPUPfS_Pi"
	.size	.L__unnamed_4, 24

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z13bounceBackGPUPfPi"
	.size	.L__unnamed_5, 22

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z9streamGPUPfS_"
	.size	.L__unnamed_6, 17

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z11streamInGPUPfS_S_"
	.size	.L__unnamed_7, 22

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z12streamOutGPUPfS_S_"
	.size	.L__unnamed_8, 23

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"velCol0"
	.size	.L__unnamed_9, 8

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"velCol1"
	.size	.L__unnamed_10, 8

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"velColInt0"
	.size	.L__unnamed_11, 11

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"velColInt1"
	.size	.L__unnamed_12, 11

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"weights"
	.size	.L__unnamed_13, 8

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"bounceBackMap"
	.size	.L__unnamed_14, 14

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"omega"
	.size	.L__unnamed_15, 6

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"lx"
	.size	.L__unnamed_16, 3

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"ly"
	.size	.L__unnamed_17, 3

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"yOffset"
	.size	.L__unnamed_18, 8

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"gridIter"
	.size	.L__unnamed_19, 9

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"nNodes"
	.size	.L__unnamed_20, 7

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"x_error"
	.size	.L__unnamed_21, 8

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"y_error"
	.size	.L__unnamed_22, 8

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"errorFlag"
	.size	.L__unnamed_23, 10

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"errorCode"
	.size	.L__unnamed_24, 10

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__calcRhoGPUPfS_
	.addrsig_sym _Z25__device_stub__calcVelGPUPfS_S_S_
	.addrsig_sym _Z33__device_stub__calcEquilibriumGPUPfS_S_S_
	.addrsig_sym _Z28__device_stub__BGKCollideGPUPfS_Pi
	.addrsig_sym _Z28__device_stub__bounceBackGPUPfPi
	.addrsig_sym _Z24__device_stub__streamGPUPfS_
	.addrsig_sym _Z26__device_stub__streamInGPUPfS_S_
	.addrsig_sym _Z27__device_stub__streamOutGPUPfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym velCol0
	.addrsig_sym velCol1
	.addrsig_sym velColInt0
	.addrsig_sym velColInt1
	.addrsig_sym weights
	.addrsig_sym bounceBackMap
	.addrsig_sym omega
	.addrsig_sym lx
	.addrsig_sym ly
	.addrsig_sym yOffset
	.addrsig_sym gridIter
	.addrsig_sym nNodes
	.addrsig_sym x_error
	.addrsig_sym y_error
	.addrsig_sym errorFlag
	.addrsig_sym errorCode
	.addrsig_sym _Z10calcRhoGPUPfS_
	.addrsig_sym _Z10calcVelGPUPfS_S_S_
	.addrsig_sym _Z18calcEquilibriumGPUPfS_S_S_
	.addrsig_sym _Z13BGKCollideGPUPfS_Pi
	.addrsig_sym _Z13bounceBackGPUPfPi
	.addrsig_sym _Z9streamGPUPfS_
	.addrsig_sym _Z11streamInGPUPfS_S_
	.addrsig_sym _Z12streamOutGPUPfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10calcRhoGPUPfS_      ; -- Begin function _Z10calcRhoGPUPfS_
	.globl	_Z10calcRhoGPUPfS_
	.p2align	8
	.type	_Z10calcRhoGPUPfS_,@function
_Z10calcRhoGPUPfS_:                     ; @_Z10calcRhoGPUPfS_
; %bb.0:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yOffset@rel32@lo+4
	s_addc_u32 s3, s3, yOffset@rel32@hi+12
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b32 s5, s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s3
	v_add3_u32 v0, s15, s5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.preheader
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, nNodes@rel32@lo+4
	s_addc_u32 s5, s5, nNodes@rel32@hi+12
	v_mov_b32_e32 v3, 0
	s_load_b128 s[0:3], s[0:1], 0x0
	s_load_b32 s4, s[4:5], 0x0
	v_mov_b32_e32 v1, v0
	s_mov_b32 s5, 9
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s5, s5, -1
	s_cmp_eq_u32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v1, s4, v1
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v3, v2
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10calcRhoGPUPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10calcRhoGPUPfS_, .Lfunc_end0-_Z10calcRhoGPUPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10calcVelGPUPfS_S_S_  ; -- Begin function _Z10calcVelGPUPfS_S_S_
	.globl	_Z10calcVelGPUPfS_S_S_
	.p2align	8
	.type	_Z10calcVelGPUPfS_S_S_,@function
_Z10calcVelGPUPfS_S_S_:                 ; @_Z10calcVelGPUPfS_S_S_
; %bb.0:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yOffset@rel32@lo+4
	s_addc_u32 s3, s3, yOffset@rel32@hi+12
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s5, s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s3
	v_add3_u32 v0, s15, s5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, nNodes@rel32@lo+4
	s_addc_u32 s3, s3, nNodes@rel32@hi+12
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b32 s8, s[2:3], 0x0
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, s8, v0
	s_lshl_b32 s9, s8, 2
	s_mul_i32 s10, s8, -3
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s9, v2
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_mad_u64_u32 v[6:7], null, s8, 3, v[4:5]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v14, v[2:3], off
	global_load_b32 v15, v[4:5], off
	v_mad_u64_u32 v[8:9], null, s8, -6, v[6:7]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_nc_u32_e32 v10, s9, v8
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_nc_u32_e32 v4, s10, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[8:9]
	v_lshlrev_b64 v[8:9], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v10, s9, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v12, s10, v10
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
	s_clause 0x5
	global_load_b32 v16, v[2:3], off
	global_load_b32 v8, v[8:9], off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[10:11], off
	global_load_b32 v9, v[12:13], off
	global_load_b32 v6, v[6:7], off
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	s_ashr_i32 s9, s8, 31
	global_load_b32 v7, v[2:3], off
	s_waitcnt vmcnt(4)
	v_dual_add_f32 v2, v14, v15 :: v_dual_add_f32 v3, v8, v4
	s_waitcnt vmcnt(2)
	v_dual_add_f32 v4, v15, v16 :: v_dual_add_f32 v9, v5, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v5
	v_dual_add_f32 v4, v4, v8 :: v_dual_add_f32 v5, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v2, v3
	v_sub_f32_e32 v2, v4, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v7, v7, v6
	v_div_scale_f32 v4, null, v7, v7, v2
	v_div_scale_f32 v11, vcc_lo, v6, v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v5, v3
	v_rcp_f32_e32 v8, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v3, v5, 1.0
	v_fma_f32 v10, -v4, v8, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v5, v9, v5
	v_div_scale_f32 v9, s0, v2, v7, v2
	v_fmac_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, v11, v5
	v_mul_f32_e32 v12, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v3, v10, v11
	v_fma_f32 v14, -v4, v12, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v13, v5
	v_fmac_f32_e32 v12, v14, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v3, v10, v11
	v_fma_f32 v4, -v4, v12, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v3, v5, v10
	s_mov_b32 vcc_lo, s0
	s_lshl_b64 s[0:1], s[8:9], 2
	v_div_fmas_f32 v3, v4, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v6, v5, v7, v6
	v_div_fixup_f32 v8, v3, v7, v2
	v_add_co_u32 v2, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, v8, v8
	v_add_co_u32 v4, vcc_lo, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_fmac_f32_e32 v7, v6, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_clause 0x1
	global_store_b32 v[2:3], v6, off
	global_store_b32 v[4:5], v8, off
	global_store_b32 v[0:1], v7, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10calcVelGPUPfS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10calcVelGPUPfS_S_S_, .Lfunc_end1-_Z10calcVelGPUPfS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 888
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18calcEquilibriumGPUPfS_S_S_ ; -- Begin function _Z18calcEquilibriumGPUPfS_S_S_
	.globl	_Z18calcEquilibriumGPUPfS_S_S_
	.p2align	8
	.type	_Z18calcEquilibriumGPUPfS_S_S_,@function
_Z18calcEquilibriumGPUPfS_S_S_:         ; @_Z18calcEquilibriumGPUPfS_S_S_
; %bb.0:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yOffset@rel32@lo+4
	s_addc_u32 s3, s3, yOffset@rel32@hi+12
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s5, s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s3
	v_add3_u32 v0, s15, s5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_3
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, nNodes@rel32@lo+4
	s_addc_u32 s7, s7, nNodes@rel32@hi+12
	s_load_b32 s6, s[6:7], 0x0
	global_load_b32 v7, v[3:4], off
	v_add_co_u32 v3, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[6:7], 2
	v_add_co_u32 v5, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[3:4], off
	global_load_b32 v5, v[5:6], off
	global_load_b32 v6, v[1:2], off
	s_mov_b64 s[2:3], 0
	s_waitcnt vmcnt(3)
	v_cvt_f64_f32_e32 v[1:2], v7
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[2:3], 0x3ff80000, v[1:2]
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, velCol0@rel32@lo+4
	s_addc_u32 s5, s5, velCol0@rel32@hi+12
	s_add_u32 s4, s2, s4
	s_addc_u32 s5, s3, s5
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, velCol1@rel32@lo+4
	s_addc_u32 s9, s9, velCol1@rel32@hi+12
	s_add_u32 s8, s2, s8
	s_addc_u32 s9, s3, s9
	s_load_b32 s7, s[8:9], 0x0
	s_load_b32 s4, s[4:5], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f32_e32 v1, s7, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v1, s4, v4
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, weights@rel32@lo+4
	s_addc_u32 s5, s5, weights@rel32@hi+12
	s_add_u32 s4, s2, s4
	s_addc_u32 s5, s3, s5
	s_add_u32 s2, s2, 4
	v_cvt_f64_f32_e32 v[7:8], v1
	s_load_b32 s4, s[4:5], 0x0
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 36
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v1, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], 0x40080000, v[7:8], 1.0
	v_mul_f64 v[11:12], 0x40120000, v[7:8]
	v_fma_f64 v[7:8], v[11:12], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[9:10], v1
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_f64 v[7:8], v[7:8], -v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[7:8], v[9:10]
	v_cvt_f32_f64_e32 v9, v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_nc_u32_e32 v0, s6, v0
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	global_store_b32 v[7:8], v9, off
	s_cbranch_scc1 .LBB2_2
.LBB2_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18calcEquilibriumGPUPfS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18calcEquilibriumGPUPfS_S_S_, .Lfunc_end2-_Z18calcEquilibriumGPUPfS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13BGKCollideGPUPfS_Pi ; -- Begin function _Z13BGKCollideGPUPfS_Pi
	.globl	_Z13BGKCollideGPUPfS_Pi
	.p2align	8
	.type	_Z13BGKCollideGPUPfS_Pi,@function
_Z13BGKCollideGPUPfS_Pi:                ; @_Z13BGKCollideGPUPfS_Pi
; %bb.0:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yOffset@rel32@lo+4
	s_addc_u32 s3, s3, yOffset@rel32@hi+12
	s_load_b32 s4, s[0:1], 0x24
	s_load_b32 s5, s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s3
	v_add3_u32 v0, s15, s5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.2:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, omega@rel32@lo+4
	s_addc_u32 s3, s3, omega@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, nNodes@rel32@lo+4
	s_addc_u32 s7, s7, nNodes@rel32@hi+12
	s_load_b32 s4, s[2:3], 0x0
	s_load_b128 s[0:3], s[0:1], 0x0
	s_load_b32 s5, s[6:7], 0x0
	s_mov_b32 s6, 9
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[1:2], s4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], -v[1:2], 1.0
.LBB3_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s6, 0
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_nc_u32_e32 v0, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[8:9], v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[2:3], v[8:9]
	v_cvt_f32_f64_e32 v1, v[8:9]
	global_store_b32 v[6:7], v1, off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v1, s4, v4
	global_store_b32 v[6:7], v1, off
	s_cbranch_scc1 .LBB3_3
.LBB3_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13BGKCollideGPUPfS_Pi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z13BGKCollideGPUPfS_Pi, .Lfunc_end3-_Z13BGKCollideGPUPfS_Pi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 400
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13bounceBackGPUPfPi   ; -- Begin function _Z13bounceBackGPUPfPi
	.globl	_Z13bounceBackGPUPfPi
	.p2align	8
	.type	_Z13bounceBackGPUPfPi,@function
_Z13bounceBackGPUPfPi:                  ; @_Z13bounceBackGPUPfPi
; %bb.0:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yOffset@rel32@lo+4
	s_addc_u32 s3, s3, yOffset@rel32@hi+12
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b32 s5, s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s3
	v_add3_u32 v9, s15, s5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v9
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB4_6
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_6
; %bb.2:                                ; %.preheader21.preheader
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, nNodes@rel32@lo+4
	s_addc_u32 s3, s3, nNodes@rel32@hi+12
	v_mov_b32_e32 v10, v9
	s_load_b32 s4, s[2:3], 0x0
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $vgpr0
.LBB4_3:                                ; %.preheader21
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 9
	v_lshlrev_b64 v[11:12], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, s4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s0, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v0, v11
	s_cbranch_scc1 .LBB4_3
; %bb.4:                                ; %.preheader.preheader
	s_mov_b64 s[2:3], 0
.LBB4_5:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, bounceBackMap@rel32@lo+4
	s_addc_u32 s7, s7, bounceBackMap@rel32@hi+12
	s_add_u32 s6, s2, s6
	s_addc_u32 s7, s3, s7
	v_ashrrev_i32_e32 v10, 31, v9
	s_load_b32 s5, s[6:7], 0x0
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 36
	v_lshlrev_b64 v[10:11], 2, v[9:10]
	v_add_nc_u32_e32 v9, s4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_mov_b32 m0, s5
	v_movrels_b32_e32 v12, v0
	global_store_b32 v[10:11], v12, off
	s_cbranch_scc1 .LBB4_5
.LBB4_6:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13bounceBackGPUPfPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z13bounceBackGPUPfPi, .Lfunc_end4-_Z13bounceBackGPUPfPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9streamGPUPfS_        ; -- Begin function _Z9streamGPUPfS_
	.globl	_Z9streamGPUPfS_
	.p2align	8
	.type	_Z9streamGPUPfS_,@function
_Z9streamGPUPfS_:                       ; @_Z9streamGPUPfS_
; %bb.0:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yOffset@rel32@lo+4
	s_addc_u32 s3, s3, yOffset@rel32@hi+12
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b32 s5, s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s3
	v_add3_u32 v0, s15, s5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB5_4
; %bb.1:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, lx@rel32@lo+4
	s_addc_u32 s3, s3, lx@rel32@hi+12
	s_load_b32 s6, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s6, 1
	s_cbranch_scc1 .LBB5_4
; %bb.2:                                ; %.preheader.preheader
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, nNodes@rel32@lo+4
	s_addc_u32 s3, s3, nNodes@rel32@hi+12
	s_mov_b64 s[4:5], 0
	s_load_b32 s7, s[2:3], 0x0
	s_load_b128 s[0:3], s[0:1], 0x0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, velColInt0@rel32@lo+4
	s_addc_u32 s11, s11, velColInt0@rel32@hi+12
.LBB5_3:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, velColInt1@rel32@lo+4
	s_addc_u32 s9, s9, velColInt1@rel32@hi+12
	s_add_u32 s8, s4, s8
	s_addc_u32 s9, s5, s9
	s_load_b32 s12, s[8:9], 0x0
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_add_u32 s8, s4, s10
	s_addc_u32 s9, s5, s11
	s_add_u32 s4, s4, 4
	s_load_b32 s8, s[8:9], 0x0
	s_addc_u32 s5, s5, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_cmp_lg_u32 s4, 36
	global_load_b32 v3, v[1:2], off
	s_mul_i32 s12, s12, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, s8, s12, v0
	v_add_nc_u32_e32 v0, s7, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v3, off
	s_cbranch_scc1 .LBB5_3
.LBB5_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9streamGPUPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z9streamGPUPfS_, .Lfunc_end5-_Z9streamGPUPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 388
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11streamInGPUPfS_S_   ; -- Begin function _Z11streamInGPUPfS_S_
	.globl	_Z11streamInGPUPfS_S_
	.p2align	8
	.type	_Z11streamInGPUPfS_S_,@function
_Z11streamInGPUPfS_S_:                  ; @_Z11streamInGPUPfS_S_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x24
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ly@rel32@lo+4
	s_addc_u32 s3, s3, ly@rel32@hi+12
	v_ashrrev_i32_e32 v9, 31, v1
	s_load_b32 s8, s[2:3], 0x0
	s_load_b64 s[4:5], s[0:1], 0x10
	v_add_nc_u32_e32 v5, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	s_add_i32 s9, s8, 2
	s_mul_i32 s2, s9, 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	v_add_co_u32 v2, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v9, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, lx@rel32@lo+4
	s_addc_u32 s3, s3, lx@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, yOffset@rel32@lo+4
	s_addc_u32 s7, s7, yOffset@rel32@hi+12
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v5
	global_load_b32 v0, v[2:3], off offset:4
	s_load_b32 s10, s[2:3], 0x0
	s_load_b32 s2, s[6:7], 0x0
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, nNodes@rel32@lo+4
	s_addc_u32 s7, s7, nNodes@rel32@hi+12
	s_load_b32 s6, s[6:7], 0x0
	s_ashr_i32 s7, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	s_lshl_b32 s7, s9, 3
	s_ashr_i32 s8, s7, 31
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, s10, v1, s[2:3]
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s6, 5, v[2:3]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_subrev_nc_u32_e32 v3, s10, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v0, off
	global_load_b32 v12, v[4:5], off offset:8
	v_add_nc_u32_e32 v4, s6, v2
	v_add_co_u32 v0, vcc_lo, s7, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_add_co_u32 v10, vcc_lo, s0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v9, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v12, off
	global_load_b32 v14, v[0:1], off offset:4
	v_mad_u64_u32 v[0:1], null, s6, 7, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_mad_u64_u32 v[4:5], null, s6, -6, v[0:1]
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_subrev_nc_u32_e32 v12, s10, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s2, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v14, off
	global_load_b32 v15, v[12:13], off
	v_lshl_add_u32 v12, s6, 1, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, s10, v12
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s2, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v15, off
	global_load_b32 v5, v[13:14], off
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[12:13], v5, off
	global_load_b32 v5, v[3:4], off
	v_add_co_u32 v3, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v9, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v5, off offset:4
	global_load_b32 v5, v[3:4], off
	v_add_nc_u32_e32 v3, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v5, off offset:4
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v0, off offset:4
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11streamInGPUPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z11streamInGPUPfS_S_, .Lfunc_end6-_Z11streamInGPUPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 900
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12streamOutGPUPfS_S_  ; -- Begin function _Z12streamOutGPUPfS_S_
	.globl	_Z12streamOutGPUPfS_S_
	.p2align	8
	.type	_Z12streamOutGPUPfS_S_,@function
_Z12streamOutGPUPfS_S_:                 ; @_Z12streamOutGPUPfS_S_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x24
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, gridIter@rel32@lo+4
	s_addc_u32 s3, s3, gridIter@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, lx@rel32@lo+4
	s_addc_u32 s3, s3, lx@rel32@hi+12
	s_load_b32 s6, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s6, 31
	v_mul_lo_u32 v1, s6, v1
	s_add_i32 s5, s6, s4
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yOffset@rel32@lo+4
	s_addc_u32 s3, s3, yOffset@rel32@hi+12
	s_xor_b32 s5, s5, s4
	s_load_b32 s2, s[2:3], 0x0
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s3, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s6, s2
	v_cvt_u32_f32_e32 v2, v0
	v_add3_u32 v0, s2, -1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, s3, v2
	v_ashrrev_i32_e32 v3, 31, v0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ly@rel32@lo+4
	s_addc_u32 s3, s3, ly@rel32@hi+12
	s_load_b32 s2, s[2:3], 0x0
	v_add_nc_u32_e32 v4, v0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v2, v1
	v_xor_b32_e32 v4, v4, v3
	v_xor_b32_e32 v3, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v2, v1
	v_mul_hi_u32 v1, v4, v1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s7, s2, 2
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, nNodes@rel32@lo+4
	s_addc_u32 s3, s3, nNodes@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v1, s5
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v1
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_load_b64 s[4:5], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v4, vcc_lo
	v_xor_b32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v3
	v_mad_u64_u32 v[2:3], null, s7, 6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v6, v[3:4], off
	s_load_b32 s8, s[2:3], 0x0
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, s8, 6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s7, -3, v[2:3]
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v6, off
	global_load_b32 v12, v[1:2], off
	v_mad_u64_u32 v[1:2], null, s8, -3, v[3:4]
	v_lshl_add_u32 v6, s7, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshl_add_u32 v0, s8, 2, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_lshlrev_b64 v[8:9], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v10, vcc_lo, s0, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v12, off
	global_load_b32 v14, v[6:7], off
	v_mad_u64_u32 v[6:7], null, s8, -5, v[0:1]
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_subrev_nc_u32_e32 v12, s6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s2, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v14, off
	global_load_b32 v15, v[12:13], off
	v_lshl_add_u32 v12, s8, 1, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, s6, v12
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s2, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v15, off
	global_load_b32 v14, v[13:14], off
	v_subrev_nc_u32_e32 v6, s6, v3
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v12, vcc_lo, s0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[12:13], v14, off
	global_load_b32 v3, v[6:7], off
	v_add_co_u32 v6, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v9, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v3, off offset:-4
	global_load_b32 v5, v[6:7], off
	v_add_nc_u32_e32 v3, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v5, off offset:-4
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v0, off offset:-4
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12streamOutGPUPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z12streamOutGPUPfS_S_, .Lfunc_end7-_Z12streamOutGPUPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1064
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	velCol0                 ; @velCol0
	.type	velCol0,@object
	.section	.bss,"aw",@nobits
	.globl	velCol0
	.p2align	4, 0x0
velCol0:
	.zero	36
	.size	velCol0, 36

	.protected	velCol1                 ; @velCol1
	.type	velCol1,@object
	.globl	velCol1
	.p2align	4, 0x0
velCol1:
	.zero	36
	.size	velCol1, 36

	.protected	velColInt0              ; @velColInt0
	.type	velColInt0,@object
	.globl	velColInt0
	.p2align	4, 0x0
velColInt0:
	.zero	36
	.size	velColInt0, 36

	.protected	velColInt1              ; @velColInt1
	.type	velColInt1,@object
	.globl	velColInt1
	.p2align	4, 0x0
velColInt1:
	.zero	36
	.size	velColInt1, 36

	.protected	weights                 ; @weights
	.type	weights,@object
	.globl	weights
	.p2align	4, 0x0
weights:
	.zero	36
	.size	weights, 36

	.protected	bounceBackMap           ; @bounceBackMap
	.type	bounceBackMap,@object
	.globl	bounceBackMap
	.p2align	4, 0x0
bounceBackMap:
	.zero	36
	.size	bounceBackMap, 36

	.protected	omega                   ; @omega
	.type	omega,@object
	.globl	omega
	.p2align	2, 0x0
omega:
	.zero	4
	.size	omega, 4

	.protected	lx                      ; @lx
	.type	lx,@object
	.globl	lx
	.p2align	2, 0x0
lx:
	.zero	4
	.size	lx, 4

	.protected	ly                      ; @ly
	.type	ly,@object
	.globl	ly
	.p2align	2, 0x0
ly:
	.zero	4
	.size	ly, 4

	.protected	yOffset                 ; @yOffset
	.type	yOffset,@object
	.globl	yOffset
	.p2align	2, 0x0
yOffset:
	.zero	4
	.size	yOffset, 4

	.protected	gridIter                ; @gridIter
	.type	gridIter,@object
	.globl	gridIter
	.p2align	2, 0x0
gridIter:
	.zero	4
	.size	gridIter, 4

	.protected	nNodes                  ; @nNodes
	.type	nNodes,@object
	.globl	nNodes
	.p2align	2, 0x0
nNodes:
	.zero	4
	.size	nNodes, 4

	.protected	x_error                 ; @x_error
	.type	x_error,@object
	.globl	x_error
	.p2align	2, 0x0
x_error:
	.long	0                               ; 0x0
	.size	x_error, 4

	.protected	y_error                 ; @y_error
	.type	y_error,@object
	.globl	y_error
	.p2align	2, 0x0
y_error:
	.long	0                               ; 0x0
	.size	y_error, 4

	.protected	errorFlag               ; @errorFlag
	.type	errorFlag,@object
	.globl	errorFlag
	.p2align	2, 0x0
errorFlag:
	.long	0                               ; 0x0
	.size	errorFlag, 4

	.protected	errorCode               ; @errorCode
	.type	errorCode,@object
	.globl	errorCode
	.p2align	2, 0x0
errorCode:
	.long	0                               ; 0x0
	.size	errorCode, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym velCol0
	.addrsig_sym velCol1
	.addrsig_sym velColInt0
	.addrsig_sym velColInt1
	.addrsig_sym weights
	.addrsig_sym bounceBackMap
	.addrsig_sym omega
	.addrsig_sym lx
	.addrsig_sym ly
	.addrsig_sym yOffset
	.addrsig_sym gridIter
	.addrsig_sym nNodes
	.addrsig_sym x_error
	.addrsig_sym y_error
	.addrsig_sym errorFlag
	.addrsig_sym errorCode
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10calcRhoGPUPfS_
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    .sgpr_spill_count: 0
    .symbol:         _Z10calcRhoGPUPfS_.kd
    .uniform_work_group_size: 1
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    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
