
/* Fold each FFT chunk separately.
 * pol0, pol1 are input baseband data
 * Only works for 4 pol output.
 * Call with grid dims (nffts, nbins/BINS_PER_BLOCK)
 * All shared blocks need to fit into shared mem (16kB)
 */
#define BINS_PER_BLOCK 64
#define NTHREAD_FOLD BINS_PER_BLOCK
__global__ void fold_fft_blocks(const float2 *pol0, const float2 *pol1, 
        const double *phase, const double *step, 
        int fftlen, int overlap, int nbin,
        float4 *foldtmp, unsigned *foldtmp_c) {

    // Size params
    const int ifft = blockIdx.x;
    const int ibin = blockIdx.y;
    const int tid = threadIdx.x; // Thread index within the block
    const int nvalid = fftlen - overlap;

    // Pointers to start of valid data in global mem
    const float2 *ptr0 = pol0 + ifft*fftlen + overlap/2;
    const float2 *ptr1 = pol1 + ifft*fftlen + overlap/2;

    // Fold info
    const double bin0 = phase[ifft];
    const double bin_samp = step[ifft];   // bins/sample
    const double samp_bin = 1.0/bin_samp; // samples/bin
    const int bin_lo = ibin*BINS_PER_BLOCK + tid; // assumes 1 thread/bin
    const int nturn = ((double)nvalid*bin_samp)/(double)nbin + 2; // GD : Change +1 into +2

    // Fold results for this thread
    float4 folddata = make_float4(0,0,0,0);
    unsigned foldcount = 0;

    // Loop over number of pulse periods in data block
    for (int iturn=0; iturn<nturn; iturn++) {

        // Determine range of samples needed for this bin, turn
        int samp0 = samp_bin*((double)bin_lo-bin0+(double)iturn*nbin)+0.5;
        int samp1 = samp_bin*((double)bin_lo-bin0+(double)iturn*nbin+1)+0.5;

        // Range checks
        if (samp0<0) { samp0=0; }
        if (samp1<0) { samp1=0; }
        if (samp0>nvalid) { samp0=nvalid; }
        if (samp1>nvalid) { samp1=nvalid; }

        // Read in and add samples
        for (int isamp=samp0; isamp<samp1; isamp++) {
            float2 p0 = ptr0[isamp];
            float2 p1 = ptr1[isamp];
            folddata.x += p0.x*p0.x + p0.y*p0.y;
            folddata.y += p1.x*p1.x + p1.y*p1.y;
            folddata.z += p0.x*p1.x + p0.y*p1.y;
            folddata.w += p0.x*p1.y - p0.y*p1.x;
            foldcount++;
        }
    }

    // Copy results into global mem
    const unsigned prof_offset = ifft * nbin;
    foldtmp[prof_offset + bin_lo].x = folddata.x;
    foldtmp[prof_offset + bin_lo].y = folddata.y;
    foldtmp[prof_offset + bin_lo].z = folddata.z;
    foldtmp[prof_offset + bin_lo].w = folddata.w;
    foldtmp_c[prof_offset + bin_lo] = foldcount;
}

	.file	"tmpxft_002049f6_00000000-6_fold_gpu_Extract_fold_fft_block.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z64__device_stub__Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4PjPK6float2S1_PKdS3_iiiP6float4Pj
	.type	_Z64__device_stub__Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4PjPK6float2S1_PKdS3_iiiP6float4Pj, @function
_Z64__device_stub__Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4PjPK6float2S1_PKdS3_iiiP6float4Pj:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	232(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	240(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movl	%r8d, 28(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z64__device_stub__Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4PjPK6float2S1_PKdS3_iiiP6float4Pj, .-_Z64__device_stub__Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4PjPK6float2S1_PKdS3_iiiP6float4Pj
	.globl	_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj
	.type	_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj, @function
_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4PjPK6float2S1_PKdS3_iiiP6float4Pj
	.cfi_endproc
.LFE2033:
	.size	_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj, .-_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15fold_fft_blocksPK6float2S1_PKdS3_iiiP6float4Pj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

/* Fold each FFT chunk separately.
 * pol0, pol1 are input baseband data
 * Only works for 4 pol output.
 * Call with grid dims (nffts, nbins/BINS_PER_BLOCK)
 * All shared blocks need to fit into shared mem (16kB)
 */
#define BINS_PER_BLOCK 64
#define NTHREAD_FOLD BINS_PER_BLOCK
__global__ void fold_fft_blocks(const float2 *pol0, const float2 *pol1, 
        const double *phase, const double *step, 
        int fftlen, int overlap, int nbin,
        float4 *foldtmp, unsigned *foldtmp_c) {

    // Size params
    const int ifft = blockIdx.x;
    const int ibin = blockIdx.y;
    const int tid = threadIdx.x; // Thread index within the block
    const int nvalid = fftlen - overlap;

    // Pointers to start of valid data in global mem
    const float2 *ptr0 = pol0 + ifft*fftlen + overlap/2;
    const float2 *ptr1 = pol1 + ifft*fftlen + overlap/2;

    // Fold info
    const double bin0 = phase[ifft];
    const double bin_samp = step[ifft];   // bins/sample
    const double samp_bin = 1.0/bin_samp; // samples/bin
    const int bin_lo = ibin*BINS_PER_BLOCK + tid; // assumes 1 thread/bin
    const int nturn = ((double)nvalid*bin_samp)/(double)nbin + 2; // GD : Change +1 into +2

    // Fold results for this thread
    float4 folddata = make_float4(0,0,0,0);
    unsigned foldcount = 0;

    // Loop over number of pulse periods in data block
    for (int iturn=0; iturn<nturn; iturn++) {

        // Determine range of samples needed for this bin, turn
        int samp0 = samp_bin*((double)bin_lo-bin0+(double)iturn*nbin)+0.5;
        int samp1 = samp_bin*((double)bin_lo-bin0+(double)iturn*nbin+1)+0.5;

        // Range checks
        if (samp0<0) { samp0=0; }
        if (samp1<0) { samp1=0; }
        if (samp0>nvalid) { samp0=nvalid; }
        if (samp1>nvalid) { samp1=nvalid; }

        // Read in and add samples
        for (int isamp=samp0; isamp<samp1; isamp++) {
            float2 p0 = ptr0[isamp];
            float2 p1 = ptr1[isamp];
            folddata.x += p0.x*p0.x + p0.y*p0.y;
            folddata.y += p1.x*p1.x + p1.y*p1.y;
            folddata.z += p0.x*p1.x + p0.y*p1.y;
            folddata.w += p0.x*p1.y - p0.y*p1.x;
            foldcount++;
        }
    }

    // Copy results into global mem
    const unsigned prof_offset = ifft * nbin;
    foldtmp[prof_offset + bin_lo].x = folddata.x;
    foldtmp[prof_offset + bin_lo].y = folddata.y;
    foldtmp[prof_offset + bin_lo].z = folddata.z;
    foldtmp[prof_offset + bin_lo].w = folddata.w;
    foldtmp_c[prof_offset + bin_lo] = foldcount;
}

	.text
	.file	"fold_gpu_Extract_fold_fft_block.hip"
	.globl	_Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj # -- Begin function _Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.type	_Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj,@function
_Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj: # @_Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj, .Lfunc_end0-_Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj,@object # @_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.section	.rodata,"a",@progbits
	.globl	_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.p2align	3, 0x0
_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj:
	.quad	_Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.size	_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj"
	.size	.L__unnamed_1, 70

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj ; -- Begin function _Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.globl	_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
	.p2align	8
	.type	_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj,@function
_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj: ; @_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[14:15], 3
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s12, s16, s17
	s_add_u32 s10, s10, s20
	v_cvt_f64_i32_e32 v[1:2], s12
	s_addc_u32 s11, s11, s21
	v_cvt_f64_i32_e32 v[5:6], s18
	s_load_b64 s[10:11], s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[1:2], s[10:11], v[1:2]
	v_div_scale_f64 v[3:4], null, v[5:6], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_div_scale_f64 v[9:10], vcc_lo, v[1:2], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[9:10], v[7:8]
	v_fma_f64 v[3:4], -v[3:4], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[3:4], v[3:4], v[7:8], v[11:12]
	v_div_fixup_f64 v[1:2], v[3:4], v[5:6], v[1:2]
	v_lshl_add_u32 v4, s2, 6, v0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], 2.0
	v_cvt_i32_f64_e32 v19, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, 1, v19
	s_cbranch_vccnz .LBB0_7
; %bb.1:                                ; %.lr.ph115
	v_div_scale_f64 v[0:1], null, s[10:11], s[10:11], 1.0
	v_div_scale_f64 v[9:10], vcc_lo, 1.0, s[10:11], 1.0
	s_lshr_b32 s3, s17, 31
	s_mul_i32 s16, s14, s16
	s_add_i32 s3, s17, s3
	s_ashr_i32 s17, s16, 31
	s_ashr_i32 s22, s3, 1
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v20, 0
	s_ashr_i32 s23, s22, 31
	s_add_u32 s8, s8, s20
	s_addc_u32 s9, s9, s21
	v_mov_b32_e32 v12, 0
	s_load_b64 s[8:9], s[8:9], 0x0
	v_mov_b32_e32 v14, 0
	v_rcp_f64_e32 v[2:3], v[0:1]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[7:8], -v[0:1], v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], v[7:8], v[2:3]
	v_fma_f64 v[7:8], -v[0:1], v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], v[7:8], v[2:3]
	v_mul_f64 v[7:8], v[9:10], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], -v[0:1], v[7:8], v[9:10]
	v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[7:8]
	v_cvt_f64_i32_e32 v[2:3], v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[7:8], v[0:1], s[10:11], 1.0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[9:10], v[2:3], -s[8:9]
	v_mov_b32_e32 v3, 0
	s_lshl_b64 s[8:9], s[22:23], 3
	s_lshl_b64 s[10:11], s[16:17], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s3, s8, s10
	s_addc_u32 s8, s9, s11
	s_or_b32 s9, s3, 4
	v_mov_b32_e32 v1, 0
	s_add_u32 s3, s6, s9
	v_mov_b32_e32 v2, 0
	s_addc_u32 s6, s7, s8
	s_ashr_i32 s13, s12, 31
	s_add_u32 s4, s4, s9
	s_addc_u32 s5, s5, s8
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[5:6], v[11:12], v[9:10]
	s_mov_b32 s7, exec_lo
	v_add_f64 v[17:18], v[15:16], 1.0
	v_fma_f64 v[15:16], v[7:8], v[15:16], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[7:8], v[17:18], 0.5
	v_cvt_i32_f64_e32 v13, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v15, v[17:18]
	v_max_i32_e32 v13, 0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_maxmin_i32 v21, v15, 0, s12
	v_cmpx_lt_i32_e64 v13, v21
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_lt_i64_e32 vcc_lo, s[12:13], v[13:14]
	s_mov_b32 s8, 0
	v_cndmask_b32_e64 v16, 0, s13, vcc_lo
	v_cndmask_b32_e64 v15, v13, s12, vcc_lo
	v_min_i32_e32 v13, s12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 3, v[15:16]
	v_add_co_u32 v15, vcc_lo, s3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, s6, v18, vcc_lo
	v_add_co_u32 v17, vcc_lo, s4, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[22:23], v[17:18], off offset:-4
	global_load_b64 v[24:25], v[15:16], off offset:-4
	v_add_nc_u32_e32 v20, 1, v20
	v_add_nc_u32_e32 v13, 1, v13
	v_add_co_u32 v15, vcc_lo, v15, 8
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v17, vcc_lo, v17, 8
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v26, v23, v23 :: v_dual_mul_f32 v27, v25, v25
	v_mul_f32_e32 v28, v23, v25
	v_mul_f32_e32 v23, v23, v24
	v_cmp_ge_i32_e32 vcc_lo, v13, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v26, v22, v22 :: v_dual_fmac_f32 v27, v24, v24
	v_fmac_f32_e32 v28, v22, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v22, v22, v25, -v23
	s_or_b32 s8, vcc_lo, s8
	v_dual_add_f32 v0, v0, v26 :: v_dual_add_f32 v1, v1, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_add_f32 v2, v2, v28 :: v_dual_add_f32 v3, v3, v22
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_6:                                ; %Flow191
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	v_add_f64 v[11:12], v[11:12], 1.0
	s_add_i32 s2, s2, 1
	v_cmp_eq_u32_e32 vcc_lo, s2, v19
	s_cbranch_vccz .LBB0_2
	s_branch .LBB0_8
.LBB0_7:
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v1, 0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v0, 0
.LBB0_8:                                ; %Flow193
	s_load_b128 s[0:3], s[0:1], 0x30
	v_mad_u64_u32 v[5:6], null, s14, s18, v[4:5]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 4, v[5:6]
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_store_b128 v[6:7], v[0:3], off
	global_store_b32 v[4:5], v20, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 64
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj, .Lfunc_end0-_Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 26
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 64
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z15fold_fft_blocksPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiPS_IfLj4EEPj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
