
#include "grid_cell_kernel.cuh"

__device__ bool IsGridIdxValid(int idx, int maxGridNum) 
{
	return !(idx == GRID_UNDEF || idx < 0 || idx > maxGridNum - 1);
}

__device__ int GetGridCell(
	const float3 & gridVolMin,
	const int3 & gridRes,
	const float3 & pos,
	float cellSize,
	int3 & gridCell)
{
	float gx = gridVolMin.x;
	float gy = gridVolMin.y;
	float gz = gridVolMin.z;

	int rx = gridRes.x;
	int ry = gridRes.y;
	int rz = gridRes.z;

	float px = pos.x - gx;
	float py = pos.y - gy;
	float pz = pos.z - gz;

	if (px < 0.0) px = 0.0;
	if (py < 0.0) py = 0.0;
	if (pz < 0.0) pz = 0.0;

	gridCell.x = (int)(px / cellSize);
	gridCell.y = (int)(py / cellSize);
	gridCell.z = (int)(pz / cellSize);

	if (gridCell.x > rx - 1) gridCell.x = rx - 1;
	if (gridCell.y > ry - 1) gridCell.y = ry - 1;
	if (gridCell.z > rz - 1) gridCell.z = rz - 1;

	return gridCell.y * rx * rz + gridCell.z * rx + gridCell.x;
}

__global__ void UniformAdd(
	int * data,
	int * uniforms,
	int n,
	int block_offset,
	int base_idx)
{
	__shared__ int uniform;

	if (threadIdx.x == 0)
		uniform = uniforms[blockIdx.x + block_offset];

	int address = threadIdx.x + __mul24(blockIdx.x, (blockDim.x << 1)) + base_idx;

	__syncthreads();

	data[address] += uniform;
	data[address + blockDim.x] += (threadIdx.x + blockDim.x < n) * uniform;
}

__device__ int BuildSum(int * input)
{
	int idx = threadIdx.x;
	int stride = 1;

	// Build The Sum In Place Up The Tree
	for (int d = blockDim.x; d > 0; d >>= 1)
	{
		__syncthreads();

		if (idx < d)
		{
			int i = __mul24(__mul24(2, stride), idx);
			int ai = i + stride - 1;
			int bi = ai + stride;

			ai += CONFLICT_FREE_OFFSET(ai);
			bi += CONFLICT_FREE_OFFSET(bi);

			input[bi] += input[ai];
		}

		stride *= 2;
	}

	return stride;
}



__device__ void ScanRootToLeaves(int * input, int stride)
{
	int idx = threadIdx.x;

	// Traverse Down The Tree Building The Scan In Place
	for (int d = 1; d <= blockDim.x; d *= 2)
	{
		stride >>= 1;

		__syncthreads();

		if (idx < d)
		{
			int i = __mul24(__mul24(2, stride), idx);
			int ai = i + stride - 1;
			int bi = ai + stride;

			ai += CONFLICT_FREE_OFFSET(ai);
			bi += CONFLICT_FREE_OFFSET(bi);

			int temp_data = input[ai];
			input[ai] = input[bi];
			input[bi] += temp_data;
		}

	}

}


	.file	"tmpxft_0028fae2_00000000-6_grid_cell_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2020:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2020:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14IsGridIdxValidii
	.type	_Z14IsGridIdxValidii, @function
_Z14IsGridIdxValidii:
.LFB2014:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2014:
	.size	_Z14IsGridIdxValidii, .-_Z14IsGridIdxValidii
	.globl	_Z11GetGridCellRK6float3RK4int3S1_fRS2_
	.type	_Z11GetGridCellRK6float3RK4int3S1_fRS2_, @function
_Z11GetGridCellRK6float3RK4int3S1_fRS2_:
.LFB2015:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2015:
	.size	_Z11GetGridCellRK6float3RK4int3S1_fRS2_, .-_Z11GetGridCellRK6float3RK4int3S1_fRS2_
	.globl	_Z8BuildSumPi
	.type	_Z8BuildSumPi, @function
_Z8BuildSumPi:
.LFB2016:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2016:
	.size	_Z8BuildSumPi, .-_Z8BuildSumPi
	.globl	_Z16ScanRootToLeavesPii
	.type	_Z16ScanRootToLeavesPii, @function
_Z16ScanRootToLeavesPii:
.LFB2017:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2017:
	.size	_Z16ScanRootToLeavesPii, .-_Z16ScanRootToLeavesPii
	.globl	_Z35__device_stub__Z10UniformAddPiS_iiiPiS_iii
	.type	_Z35__device_stub__Z10UniformAddPiS_iiiPiS_iii, @function
_Z35__device_stub__Z10UniformAddPiS_iiiPiS_iii:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10UniformAddPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z35__device_stub__Z10UniformAddPiS_iiiPiS_iii, .-_Z35__device_stub__Z10UniformAddPiS_iiiPiS_iii
	.globl	_Z10UniformAddPiS_iii
	.type	_Z10UniformAddPiS_iii, @function
_Z10UniformAddPiS_iii:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z10UniformAddPiS_iiiPiS_iii
	.cfi_endproc
.LFE2043:
	.size	_Z10UniformAddPiS_iii, .-_Z10UniformAddPiS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10UniformAddPiS_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2045:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10UniformAddPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2045:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#ifndef GRID_CELL_KERNEL_CUH
#define GRID_CELL_KERNEL_CUH

#include <math.h>
#include <hip/hip_runtime.h>

#include <hip/device_functions.h>

#define GRID_UCHAR   0xFF
#define GRID_UNDEF   0xFFFFFFFF
#define MAX_GRID_NBR 27

#define LOG_BANK_NUM 4
#define CONFLICT_FREE_OFFSET(index) ((index)>>LOG_BANK_NUM)

#define BLOCK_SIZE 256

// жϵԪǷڷΧ
__device__ bool IsGridIdxValid(int idx, int maxGridNum);

// ӵλü㵥Ԫ
__device__ int  GetGridCell(
	const float3 & gridVolMin,
	const int3 & gridRes,
	const float3 & pos,
	float cellSize,
	int3 & gridCell);

__global__ void UniformAdd(
	int * data, 
	int * uniforms, 
	int n, 
	int block_offset,
	int base_idx);


__device__ int BuildSum(int * input);


__device__ void ScanRootToLeaves(int * input, int stride);

template<bool is_np2>
__device__ void LoadSharedChunk(
	int * output, int * input,
	int n, int base_idx,
	int & ai, int & bi,
	int & mem_ai, int & mem_bi,
	int & bank_offset_a, int & bank_offset_b) 
{
	int i = threadIdx.x;

	mem_ai = base_idx + i;
	mem_bi = mem_ai + blockDim.x;

	ai = i;
	bi = i + blockDim.x;

	// Compute Spacing To Avoid Bank Conflicts
	bank_offset_a = CONFLICT_FREE_OFFSET(ai);
	bank_offset_b = CONFLICT_FREE_OFFSET(bi);

	// Cache The Computational Window In Shared Memory Pad Values Beyond N With Zeros
	output[ai + bank_offset_a] = input[mem_ai];

	if (is_np2) 
	{
		output[bi + bank_offset_b] = (bi < n) ? input[mem_bi] : 0;
	}
	else 
	{
		output[bi + bank_offset_b] = input[mem_bi];
	}

}

template<bool store_sum>
__device__ void ClearLastElement(int * input, int * block_sum, int block_idx)
{
	if (threadIdx.x == 0)
	{
		int i = (blockDim.x << 1) - 1;
		i += CONFLICT_FREE_OFFSET(i);

		if (store_sum)
		{
			// Write This Block's Total Sum To The Corresponding Index In The Block Sum Array
			block_sum[block_idx] = input[i];
		}
		// Zero The Last Element In The Scan So It Will propagate Back To The Front
		input[i] = 0;
	}

}

template<bool store_sum>
__device__ void PrescanBlock(int * data, int block_idx, int * block_sum)
{
	// Build The Sum In Place Up The Tree
	int stride = BuildSum(data);

	int b_idx = (block_idx == 0) ? blockIdx.x : block_idx;
	ClearLastElement<store_sum>(data, block_sum, b_idx);

	// Traverse Down Tree To Build The Scan
	ScanRootToLeaves(data, stride);
}

template<bool is_np2>
__device__ void StoreSharedChunk(
	int * output, int * input, 
	int n, int ai, int bi,
	int mem_ai, int mem_bi, 
	int bank_offset_a, int bank_offset_b)
{
	__syncthreads();

	// Write Results To Global Memoery
	output[mem_ai] = input[ai + bank_offset_a];

	if (is_np2)
	{
		if (bi < n)
		{
			output[mem_bi] = input[bi + bank_offset_b];
		}
	}
	else
	{
		output[mem_bi] = input[bi + bank_offset_b];
	}

}

template<bool store_sum, bool is_np2>
__global__ void PrescanCUDA(
	int * output, int * input,
	int * block_sum, 
	int n, int block_idx, int base_idx) 
{

	int ai, bi, mem_ai, mem_bi, bank_offset_a, bank_offset_b;

	extern __shared__ int shared_data[];

	int b_idx = (base_idx == 0) ? __mul24(blockIdx.x, (blockDim.x << 1)) : base_idx;

	LoadSharedChunk<is_np2>(shared_data, input, n, b_idx, ai, bi, mem_ai, mem_bi, bank_offset_a, bank_offset_b);

	PrescanBlock<store_sum>(shared_data, block_idx, block_sum);

	StoreSharedChunk<is_np2>(output, shared_data, n, ai, bi, mem_ai, mem_bi, bank_offset_a, bank_offset_b);
}




#endif
	.text
	.file	"grid_cell_kernel.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.amdgpu_metadata
---
amdhsa.kernels:  []
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
