#include <stdio.h>
#include <stdlib.h>
#include <time.h>

__device__ double logsumexp(double a, double b)
{

	if(a <= -1e20)
	{
		return b;
	}
	else
	if(b <= -1e20)
	{
		return a;
	}

	/*double diff = a-b;
	if (diff < -20.0f)
	{
		return b;
	}
	else
	if (diff > 20.0f)
	{
		return a;
	}*/
	

	if(a > b)
	{
		return a + log(1.0+exp(b-a));
	}
	else
	{
		return b + log(1.0+exp(a-b));
	}
}

__device__ double safeadd(double a, double b)
{
	if(a <= -1e20)
	{
		return b;
	}
	else
	if(b <= -1e20)
	{
		return a;
	}
	return a+b;
}

/*
push!(rules, Rule('S', "LS",0.868534, 3))
    push!(rules, Rule('S', "s",0.117609877998, 1))
    push!(rules, Rule('S', "dFd",0.013856122002, 2))
    push!(rules, Rule('F', "dFd",0.787640, 2))
    push!(rules, Rule('F', "LS",0.21236, 3))
    push!(rules, Rule('L', "s",0.894603, 1))
    push!(rules, Rule('L', "dFd",0.105397, 2))
    type1rules = Rule[rules[2],rules[6]]
    type2rules = Rule[rules[3],rules[4],rules[7]]
    type3rules = Rule[rules[1],rules[5]]
    ruleindex = Dict('S' => 1, 'F' => 2, 'L' => 3)
*/

__constant__ int S = 0;
__constant__ int F = 1;
__constant__ int L = 2;
	
__constant__ double r1logprob = -0.14094854611;
__constant__ double r2logprob = -2.14038225046;
__constant__ double r3logprob = -4.27902812221;
__constant__ double r4logprob = -0.2387141463;
__constant__ double r5logprob = -1.549472331;
__constant__ double r6logprob = -0.11137523453;
__constant__ double r7logprob = -2.25002110628;

__global__ void insidealgorithm(double* inside, const double* pairedlogprobs, const double* unpairedlogprobs, const int b, const int len, const double BT)
{	
	int j = blockIdx.x*blockDim.x + threadIdx.x;
	if (j < len-b)
	{		
		int index = 0;
		// type 3 rules

		// rule 1
		double tmp = -1e20;
		for(int h=j ; h < j+b ; h++)
		{
			tmp = logsumexp(tmp, inside[L*len*len + j*len + h] + inside[S*len*len + (h+1)*len + (j+b)]);
		}
		index = S*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r1logprob*BT + tmp);

		// rule 5
		/*tmp = -1e20f;
		for(int h=j ; h < j+b ; h++)
		{			
			double prob1 = inside[L*len*len + j*len + h];
			double prob2 = inside[S*len*len + (h+1)*len + j+b];
			tmp = logsumexp(tmp, prob1 + prob2);
		}*/
		index = F*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r5logprob*BT + tmp);

		// type 2 rules

		double v = pairedlogprobs[j*len+j+b]*BT + inside[F*len*len+(j+1)*len+ (j+b-1)];

		// rule 3
		index = S*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r3logprob*BT + v);

		// rule 4
		index = F*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r4logprob*BT + v);

		// rule 7
		index = L*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r7logprob*BT + v);  
 	}
	
}


/*
push!(rules, Rule('S', "LS",0.868534, 3))
    push!(rules, Rule('S', "s",0.117609877998, 1))
    push!(rules, Rule('S', "dFd",0.013856122002, 2))
    push!(rules, Rule('F', "dFd",0.787640, 2))
    push!(rules, Rule('F', "LS",0.21236, 3))
    push!(rules, Rule('L', "s",0.894603, 1))
    push!(rules, Rule('L', "dFd",0.105397, 2))
    type1rules = Rule[rules[2],rules[6]]
    type2rules = Rule[rules[3],rules[4],rules[7]]
    type3rules = Rule[rules[1],rules[5]]
    ruleindex = Dict('S' => 1, 'F' => 2, 'L' => 3)
*/
__global__ void outsidealgorithm(double* outside, const double* inside, const double* pairedlogprobs, const double* unpairedlogprobs, const int b, const int len, const double BT)
{	
	int j = blockIdx.x*blockDim.x + threadIdx.x;
	if (j < len - b)
	{
		int index = 0;
		// type 3 rules

		// rule 1 Rule('S', "LS",0.868534, 3))
		double tmp = -1e20;
		for (int k = j + b + 1; k < len; k++)
		{
			tmp = logsumexp(tmp, outside[S*len*len + j*len + k] + inside[S*len*len + (j+b+1)*len + k]);
		}
		index = L*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r1logprob*BT + tmp);

		tmp = -1e20;
		for (int k = 0 ; k < j ; k++)
		{
			tmp = logsumexp(tmp, outside[S*len*len + k*len + j+b] + inside[L*len*len + k*len + j-1]);
		}
		index = S*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r1logprob*BT + tmp);

		// rule 5 Rule('F', "LS",0.21236, 3)
		tmp = -1e20;
		for (int k = j + b + 1; k < len; k++)
		{
			tmp = logsumexp(tmp, outside[F*len*len + j*len + k] + inside[S*len*len + (j+b+1)*len + k]);
		}
		index = L*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r5logprob*BT + tmp);

		tmp = -1e20;
		for (int k = 0 ; k < j ; k++)
		{
			tmp = logsumexp(tmp, outside[F*len*len + k*len + j+b] + inside[L*len*len + k*len + j-1]);
		}
		index = S*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r5logprob*BT + tmp);
			
		// type 2 rules
		if ((j>=1) && (j+b+1<len))
		{
			double v = pairedlogprobs[(j-1)*len+(j+b+1)]*BT;
			index = F*len*len + j*len + j+b;
			// rule 3 Rule('S', "dFd",0.013856122002, 2)
			outside[index] = logsumexp(outside[index], r3logprob*BT + outside[S*len*len + (j-1)*len + j+b+1] + v);

			// rule 4 Rule('F', "dFd",0.787640, 2)
			outside[index] = logsumexp(outside[index], r4logprob*BT + outside[F*len*len + (j-1)*len + j+b+1] + v);

			// rule 7 Rule('L', "dFd",0.105397, 2)
			outside[index] = logsumexp(outside[index], r7logprob*BT + outside[L*len*len + (j-1)*len + j+b+1] + v);
		}
 	}
	
}

	.file	"tmpxft_002c0f62_00000000-6_insidedouble.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9logsumexpdd
	.type	_Z9logsumexpdd, @function
_Z9logsumexpdd:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z9logsumexpdd, .-_Z9logsumexpdd
	.globl	_Z7safeadddd
	.type	_Z7safeadddd, @function
_Z7safeadddd:
.LFB2175:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z9logsumexpdd
	.cfi_endproc
.LFE2175:
	.size	_Z7safeadddd, .-_Z7safeadddd
	.globl	_Z44__device_stub__Z15insidealgorithmPdPKdS1_iidPdPKdS1_iid
	.type	_Z44__device_stub__Z15insidealgorithmPdPKdS1_iidPdPKdS1_iid, @function
_Z44__device_stub__Z15insidealgorithmPdPKdS1_iidPdPKdS1_iid:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15insidealgorithmPdPKdS1_iid(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L6:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z44__device_stub__Z15insidealgorithmPdPKdS1_iidPdPKdS1_iid, .-_Z44__device_stub__Z15insidealgorithmPdPKdS1_iidPdPKdS1_iid
	.globl	_Z15insidealgorithmPdPKdS1_iid
	.type	_Z15insidealgorithmPdPKdS1_iid, @function
_Z15insidealgorithmPdPKdS1_iid:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z15insidealgorithmPdPKdS1_iidPdPKdS1_iid
	.cfi_endproc
.LFE2054:
	.size	_Z15insidealgorithmPdPKdS1_iid, .-_Z15insidealgorithmPdPKdS1_iid
	.globl	_Z48__device_stub__Z16outsidealgorithmPdPKdS1_S1_iidPdPKdS1_S1_iid
	.type	_Z48__device_stub__Z16outsidealgorithmPdPKdS1_S1_iidPdPKdS1_S1_iid, @function
_Z48__device_stub__Z16outsidealgorithmPdPKdS1_S1_iidPdPKdS1_S1_iid:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movsd	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z16outsidealgorithmPdPKdS1_S1_iid(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L12:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z48__device_stub__Z16outsidealgorithmPdPKdS1_S1_iidPdPKdS1_S1_iid, .-_Z48__device_stub__Z16outsidealgorithmPdPKdS1_S1_iidPdPKdS1_S1_iid
	.globl	_Z16outsidealgorithmPdPKdS1_S1_iid
	.type	_Z16outsidealgorithmPdPKdS1_S1_iid, @function
_Z16outsidealgorithmPdPKdS1_S1_iid:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z16outsidealgorithmPdPKdS1_S1_iidPdPKdS1_S1_iid
	.cfi_endproc
.LFE2056:
	.size	_Z16outsidealgorithmPdPKdS1_S1_iid, .-_Z16outsidealgorithmPdPKdS1_S1_iid
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16outsidealgorithmPdPKdS1_S1_iid"
.LC1:
	.string	"_Z15insidealgorithmPdPKdS1_iid"
.LC2:
	.string	"S"
.LC3:
	.string	"F"
.LC4:
	.string	"L"
.LC5:
	.string	"r1logprob"
.LC6:
	.string	"r2logprob"
.LC7:
	.string	"r3logprob"
.LC8:
	.string	"r4logprob"
.LC9:
	.string	"r5logprob"
.LC10:
	.string	"r6logprob"
.LC11:
	.string	"r7logprob"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16outsidealgorithmPdPKdS1_S1_iid(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15insidealgorithmPdPKdS1_iid(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movl	$4, %r9d
	leaq	_ZL1S(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL1F(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL1L(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL9r1logprob(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL9r2logprob(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL9r3logprob(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL9r4logprob(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL9r5logprob(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL9r6logprob(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$8, %r9d
	movq	%rdx, %rcx
	leaq	_ZL9r7logprob(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL9r7logprob
	.comm	_ZL9r7logprob,8,8
	.local	_ZL9r6logprob
	.comm	_ZL9r6logprob,8,8
	.local	_ZL9r5logprob
	.comm	_ZL9r5logprob,8,8
	.local	_ZL9r4logprob
	.comm	_ZL9r4logprob,8,8
	.local	_ZL9r3logprob
	.comm	_ZL9r3logprob,8,8
	.local	_ZL9r2logprob
	.comm	_ZL9r2logprob,8,8
	.local	_ZL9r1logprob
	.comm	_ZL9r1logprob,8,8
	.local	_ZL1L
	.comm	_ZL1L,4,4
	.local	_ZL1F
	.comm	_ZL1F,4,4
	.local	_ZL1S
	.comm	_ZL1S,4,4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

__device__ double logsumexp(double a, double b)
{

	if(a <= -1e20)
	{
		return b;
	}
	else
	if(b <= -1e20)
	{
		return a;
	}

	/*double diff = a-b;
	if (diff < -20.0f)
	{
		return b;
	}
	else
	if (diff > 20.0f)
	{
		return a;
	}*/
	

	if(a > b)
	{
		return a + log(1.0+exp(b-a));
	}
	else
	{
		return b + log(1.0+exp(a-b));
	}
}

__device__ double safeadd(double a, double b)
{
	if(a <= -1e20)
	{
		return b;
	}
	else
	if(b <= -1e20)
	{
		return a;
	}
	return a+b;
}

/*
push!(rules, Rule('S', "LS",0.868534, 3))
    push!(rules, Rule('S', "s",0.117609877998, 1))
    push!(rules, Rule('S', "dFd",0.013856122002, 2))
    push!(rules, Rule('F', "dFd",0.787640, 2))
    push!(rules, Rule('F', "LS",0.21236, 3))
    push!(rules, Rule('L', "s",0.894603, 1))
    push!(rules, Rule('L', "dFd",0.105397, 2))
    type1rules = Rule[rules[2],rules[6]]
    type2rules = Rule[rules[3],rules[4],rules[7]]
    type3rules = Rule[rules[1],rules[5]]
    ruleindex = Dict('S' => 1, 'F' => 2, 'L' => 3)
*/

__constant__ int S = 0;
__constant__ int F = 1;
__constant__ int L = 2;
	
__constant__ double r1logprob = -0.14094854611;
__constant__ double r2logprob = -2.14038225046;
__constant__ double r3logprob = -4.27902812221;
__constant__ double r4logprob = -0.2387141463;
__constant__ double r5logprob = -1.549472331;
__constant__ double r6logprob = -0.11137523453;
__constant__ double r7logprob = -2.25002110628;

__global__ void insidealgorithm(double* inside, const double* pairedlogprobs, const double* unpairedlogprobs, const int b, const int len, const double BT)
{	
	int j = blockIdx.x*blockDim.x + threadIdx.x;
	if (j < len-b)
	{		
		int index = 0;
		// type 3 rules

		// rule 1
		double tmp = -1e20;
		for(int h=j ; h < j+b ; h++)
		{
			tmp = logsumexp(tmp, inside[L*len*len + j*len + h] + inside[S*len*len + (h+1)*len + (j+b)]);
		}
		index = S*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r1logprob*BT + tmp);

		// rule 5
		/*tmp = -1e20f;
		for(int h=j ; h < j+b ; h++)
		{			
			double prob1 = inside[L*len*len + j*len + h];
			double prob2 = inside[S*len*len + (h+1)*len + j+b];
			tmp = logsumexp(tmp, prob1 + prob2);
		}*/
		index = F*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r5logprob*BT + tmp);

		// type 2 rules

		double v = pairedlogprobs[j*len+j+b]*BT + inside[F*len*len+(j+1)*len+ (j+b-1)];

		// rule 3
		index = S*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r3logprob*BT + v);

		// rule 4
		index = F*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r4logprob*BT + v);

		// rule 7
		index = L*len*len + j*len + j+b;
		inside[index] = logsumexp(inside[index], r7logprob*BT + v);  
 	}
	
}


/*
push!(rules, Rule('S', "LS",0.868534, 3))
    push!(rules, Rule('S', "s",0.117609877998, 1))
    push!(rules, Rule('S', "dFd",0.013856122002, 2))
    push!(rules, Rule('F', "dFd",0.787640, 2))
    push!(rules, Rule('F', "LS",0.21236, 3))
    push!(rules, Rule('L', "s",0.894603, 1))
    push!(rules, Rule('L', "dFd",0.105397, 2))
    type1rules = Rule[rules[2],rules[6]]
    type2rules = Rule[rules[3],rules[4],rules[7]]
    type3rules = Rule[rules[1],rules[5]]
    ruleindex = Dict('S' => 1, 'F' => 2, 'L' => 3)
*/
__global__ void outsidealgorithm(double* outside, const double* inside, const double* pairedlogprobs, const double* unpairedlogprobs, const int b, const int len, const double BT)
{	
	int j = blockIdx.x*blockDim.x + threadIdx.x;
	if (j < len - b)
	{
		int index = 0;
		// type 3 rules

		// rule 1 Rule('S', "LS",0.868534, 3))
		double tmp = -1e20;
		for (int k = j + b + 1; k < len; k++)
		{
			tmp = logsumexp(tmp, outside[S*len*len + j*len + k] + inside[S*len*len + (j+b+1)*len + k]);
		}
		index = L*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r1logprob*BT + tmp);

		tmp = -1e20;
		for (int k = 0 ; k < j ; k++)
		{
			tmp = logsumexp(tmp, outside[S*len*len + k*len + j+b] + inside[L*len*len + k*len + j-1]);
		}
		index = S*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r1logprob*BT + tmp);

		// rule 5 Rule('F', "LS",0.21236, 3)
		tmp = -1e20;
		for (int k = j + b + 1; k < len; k++)
		{
			tmp = logsumexp(tmp, outside[F*len*len + j*len + k] + inside[S*len*len + (j+b+1)*len + k]);
		}
		index = L*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r5logprob*BT + tmp);

		tmp = -1e20;
		for (int k = 0 ; k < j ; k++)
		{
			tmp = logsumexp(tmp, outside[F*len*len + k*len + j+b] + inside[L*len*len + k*len + j-1]);
		}
		index = S*len*len + j*len + j+b;
		outside[index] = logsumexp(outside[index], r5logprob*BT + tmp);
			
		// type 2 rules
		if ((j>=1) && (j+b+1<len))
		{
			double v = pairedlogprobs[(j-1)*len+(j+b+1)]*BT;
			index = F*len*len + j*len + j+b;
			// rule 3 Rule('S', "dFd",0.013856122002, 2)
			outside[index] = logsumexp(outside[index], r3logprob*BT + outside[S*len*len + (j-1)*len + j+b+1] + v);

			// rule 4 Rule('F', "dFd",0.787640, 2)
			outside[index] = logsumexp(outside[index], r4logprob*BT + outside[F*len*len + (j-1)*len + j+b+1] + v);

			// rule 7 Rule('L', "dFd",0.105397, 2)
			outside[index] = logsumexp(outside[index], r7logprob*BT + outside[L*len*len + (j-1)*len + j+b+1] + v);
		}
 	}
	
}

	.text
	.file	"insidedouble.hip"
	.globl	_Z30__device_stub__insidealgorithmPdPKdS1_iid # -- Begin function _Z30__device_stub__insidealgorithmPdPKdS1_iid
	.type	_Z30__device_stub__insidealgorithmPdPKdS1_iid,@function
_Z30__device_stub__insidealgorithmPdPKdS1_iid: # @_Z30__device_stub__insidealgorithmPdPKdS1_iid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15insidealgorithmPdPKdS1_iid, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__insidealgorithmPdPKdS1_iid, .Lfunc_end0-_Z30__device_stub__insidealgorithmPdPKdS1_iid
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid # -- Begin function _Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid
	.type	_Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid,@function
_Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid: # @_Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	24(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16outsidealgorithmPdPKdS1_S1_iid, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid, .Lfunc_end1-_Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15insidealgorithmPdPKdS1_iid, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16outsidealgorithmPdPKdS1_S1_iid, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$S, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$F, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$L, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$r1logprob, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$r2logprob, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$r3logprob, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$r4logprob, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$r5logprob, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$r6logprob, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$r7logprob, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	S,@object                       # @S
	.local	S
	.comm	S,4,4
	.type	F,@object                       # @F
	.local	F
	.comm	F,4,4
	.type	L,@object                       # @L
	.local	L
	.comm	L,4,4
	.type	r1logprob,@object               # @r1logprob
	.local	r1logprob
	.comm	r1logprob,8,8
	.type	r2logprob,@object               # @r2logprob
	.local	r2logprob
	.comm	r2logprob,8,8
	.type	r3logprob,@object               # @r3logprob
	.local	r3logprob
	.comm	r3logprob,8,8
	.type	r4logprob,@object               # @r4logprob
	.local	r4logprob
	.comm	r4logprob,8,8
	.type	r5logprob,@object               # @r5logprob
	.local	r5logprob
	.comm	r5logprob,8,8
	.type	r6logprob,@object               # @r6logprob
	.local	r6logprob
	.comm	r6logprob,8,8
	.type	r7logprob,@object               # @r7logprob
	.local	r7logprob
	.comm	r7logprob,8,8
	.type	_Z15insidealgorithmPdPKdS1_iid,@object # @_Z15insidealgorithmPdPKdS1_iid
	.section	.rodata,"a",@progbits
	.globl	_Z15insidealgorithmPdPKdS1_iid
	.p2align	3, 0x0
_Z15insidealgorithmPdPKdS1_iid:
	.quad	_Z30__device_stub__insidealgorithmPdPKdS1_iid
	.size	_Z15insidealgorithmPdPKdS1_iid, 8

	.type	_Z16outsidealgorithmPdPKdS1_S1_iid,@object # @_Z16outsidealgorithmPdPKdS1_S1_iid
	.globl	_Z16outsidealgorithmPdPKdS1_S1_iid
	.p2align	3, 0x0
_Z16outsidealgorithmPdPKdS1_S1_iid:
	.quad	_Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid
	.size	_Z16outsidealgorithmPdPKdS1_S1_iid, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15insidealgorithmPdPKdS1_iid"
	.size	.L__unnamed_1, 31

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16outsidealgorithmPdPKdS1_S1_iid"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"S"
	.size	.L__unnamed_3, 2

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"F"
	.size	.L__unnamed_4, 2

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"L"
	.size	.L__unnamed_5, 2

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"r1logprob"
	.size	.L__unnamed_6, 10

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"r2logprob"
	.size	.L__unnamed_7, 10

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"r3logprob"
	.size	.L__unnamed_8, 10

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"r4logprob"
	.size	.L__unnamed_9, 10

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"r5logprob"
	.size	.L__unnamed_10, 10

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"r6logprob"
	.size	.L__unnamed_11, 10

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"r7logprob"
	.size	.L__unnamed_12, 10

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__insidealgorithmPdPKdS1_iid
	.addrsig_sym _Z31__device_stub__outsidealgorithmPdPKdS1_S1_iid
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym S
	.addrsig_sym F
	.addrsig_sym L
	.addrsig_sym r1logprob
	.addrsig_sym r2logprob
	.addrsig_sym r3logprob
	.addrsig_sym r4logprob
	.addrsig_sym r5logprob
	.addrsig_sym r6logprob
	.addrsig_sym r7logprob
	.addrsig_sym _Z15insidealgorithmPdPKdS1_iid
	.addrsig_sym _Z16outsidealgorithmPdPKdS1_S1_iid
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z9logsumexpdd
	.type	_Z9logsumexpdd,@function
_Z9logsumexpdd:                         ; @_Z9logsumexpdd
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_mov_b32 s0, 0x78b58c40
	s_mov_b32 s1, 0xc415af1d
	s_mov_b32 s6, exec_lo
	v_cmpx_nge_f64_e32 s[0:1], v[0:1]
	s_cbranch_execz .LBB0_8
; %bb.1:
	v_cmp_nge_f64_e32 vcc_lo, s[0:1], v[2:3]
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.2:
	s_mov_b32 s0, exec_lo
	v_cmpx_ngt_f64_e32 v[0:1], v[2:3]
	s_xor_b32 s7, exec_lo, s0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	s_mov_b32 s2, 0x652b82fe
	s_mov_b32 s3, 0x3ff71547
	s_mov_b32 s5, 0xbfe62e42
	s_mov_b32 s4, 0xfefa39ef
	s_mov_b32 s8, 0xfca7ab0c
	s_mov_b32 s10, 0x6a5dcb37
	s_mov_b32 s9, 0x3e928af3
	s_mov_b32 s11, 0x3e5ade15
	s_mov_b32 s12, 0xbf559e2b
	s_mov_b32 s13, 0x3fc3ab76
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], v[0:1], s[2:3]
	s_mov_b32 s3, 0xbc7abc9e
	s_mov_b32 s2, 0x3b39803f
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[0:1]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[0:1]
	v_rndne_f64_e32 v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[4:5], s[4:5], v[0:1]
	v_cvt_i32_f64_e32 v10, v[4:5]
	s_mov_b32 s5, 0x3fe62e42
	v_fma_f64 v[6:7], v[4:5], s[2:3], v[6:7]
	s_mov_b32 s3, 0x3c7abc9e
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], s[10:11], s[8:9]
	s_mov_b32 s8, 0x623fde64
	s_mov_b32 s9, 0x3ec71dee
	s_mov_b32 s10, 0x6b47b09a
	s_mov_b32 s11, 0x3fc38538
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x7c89e6b0
	s_mov_b32 s9, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x14761f6e
	s_mov_b32 s9, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x1852b7b0
	s_mov_b32 s9, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x11122322
	s_mov_b32 s9, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x555502a1
	s_mov_b32 s9, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x55555511
	s_mov_b32 s9, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 11
	s_mov_b32 s9, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s9, 0x3fe55555
	s_mov_b32 s8, 0x55555555
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
	v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[4:5], v[4:5], v10
	v_add_f64 v[4:5], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e64 v1, 0x3ff00000, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, 0, v4, vcc_lo
	v_frexp_mant_f64_e32 v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[4:5]
	s_mov_b32 s8, 0x55555780
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_ldexp_f64 v[4:5], v[4:5], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[4:5], 1.0
	v_add_f64 v[12:13], v[4:5], -1.0
	v_rcp_f64_e32 v[8:9], v[6:7]
	v_add_f64 v[14:15], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	v_mul_f64 v[16:17], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
	v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[16:17], v[4:5]
	v_add_f64 v[14:15], v[12:13], -v[6:7]
	v_add_f64 v[16:17], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_add_f64 v[4:5], v[16:17], -v[4:5]
	v_frexp_exp_i32_f64_e32 v16, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	v_add_f64 v[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[14:15], v[4:5]
	v_mul_f64 v[4:5], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[10:11], v[4:5]
	v_mul_f64 v[8:9], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[8:9], s[12:13], s[10:11]
	s_mov_b32 s10, 0xd7f4df2e
	s_mov_b32 s11, 0x3fc7474d
	v_mul_f64 v[14:15], v[6:7], v[8:9]
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_mov_b32 s10, 0x16291751
	s_mov_b32 s11, 0x3fcc71c0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_mov_b32 s10, 0x9b27acf1
	s_mov_b32 s11, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_mov_b32 s10, 0x998ef7b6
	s_mov_b32 s11, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[12:13], s[8:9]
	v_ldexp_f64 v[12:13], v[6:7], 1
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_mul_f64 v[8:9], v[14:15], v[8:9]
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
	v_cvt_f64_i32_e32 v[14:15], v14
	v_add_f64 v[10:11], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[4:5], v[4:5], 1
	v_mul_f64 v[16:17], v[14:15], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[10:11], -v[12:13]
	v_fma_f64 v[12:13], v[14:15], s[4:5], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	v_fma_f64 v[8:9], v[14:15], s[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[10:11], v[4:5]
	v_add_f64 v[16:17], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[6:7], v[12:13]
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[14:15], -v[6:7]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[14:15], -v[18:19]
	v_add_f64 v[10:11], v[12:13], -v[18:19]
	v_add_f64 v[12:13], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[12:13], -v[8:9]
	v_add_f64 v[6:7], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[10:11]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	v_add_f64 v[16:17], v[14:15], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	v_add_f64 v[10:11], v[16:17], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[4:5], v[16:17], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v5, v1 :: v_dual_cndmask_b32 v4, v4, v0
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_cndmask_b32_e32 v5, 0x7ff80000, v5, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[0:1]
	v_cndmask_b32_e32 v5, 0xfff00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[4:5], v[2:3]
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_4:                                ; %Flow
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], -v[0:1]
	s_mov_b32 s2, 0x652b82fe
	s_mov_b32 s3, 0x3ff71547
	s_mov_b32 s5, 0xbfe62e42
	s_mov_b32 s4, 0xfefa39ef
	s_mov_b32 s8, 0xfca7ab0c
	s_mov_b32 s10, 0x6a5dcb37
	s_mov_b32 s9, 0x3e928af3
	s_mov_b32 s11, 0x3e5ade15
	s_mov_b32 s12, 0xbf559e2b
	s_mov_b32 s13, 0x3fc3ab76
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], v[2:3], s[2:3]
	s_mov_b32 s3, 0xbc7abc9e
	s_mov_b32 s2, 0x3b39803f
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
	v_rndne_f64_e32 v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[6:7], v[4:5], s[4:5], v[2:3]
	v_cvt_i32_f64_e32 v10, v[4:5]
	s_mov_b32 s5, 0x3fe62e42
	v_fma_f64 v[6:7], v[4:5], s[2:3], v[6:7]
	s_mov_b32 s3, 0x3c7abc9e
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], s[10:11], s[8:9]
	s_mov_b32 s8, 0x623fde64
	s_mov_b32 s9, 0x3ec71dee
	s_mov_b32 s10, 0x6b47b09a
	s_mov_b32 s11, 0x3fc38538
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x7c89e6b0
	s_mov_b32 s9, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x14761f6e
	s_mov_b32 s9, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x1852b7b0
	s_mov_b32 s9, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x11122322
	s_mov_b32 s9, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x555502a1
	s_mov_b32 s9, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 0x55555511
	s_mov_b32 s9, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s8, 11
	s_mov_b32 s9, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[8:9]
	s_mov_b32 s9, 0x3fe55555
	s_mov_b32 s8, 0x55555555
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
	v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[4:5], v[4:5], v10
	v_add_f64 v[4:5], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	v_cndmask_b32_e64 v3, 0x3ff00000, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v4, vcc_lo
	v_frexp_mant_f64_e32 v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[4:5]
	s_mov_b32 s8, 0x55555780
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_ldexp_f64 v[4:5], v[4:5], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[4:5], 1.0
	v_add_f64 v[12:13], v[4:5], -1.0
	v_rcp_f64_e32 v[8:9], v[6:7]
	v_add_f64 v[14:15], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	v_mul_f64 v[16:17], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
	v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[16:17], v[4:5]
	v_add_f64 v[14:15], v[12:13], -v[6:7]
	v_add_f64 v[16:17], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_add_f64 v[4:5], v[16:17], -v[4:5]
	v_frexp_exp_i32_f64_e32 v16, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	v_add_f64 v[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[14:15], v[4:5]
	v_mul_f64 v[4:5], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[10:11], v[4:5]
	v_mul_f64 v[8:9], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[8:9], s[12:13], s[10:11]
	s_mov_b32 s10, 0xd7f4df2e
	s_mov_b32 s11, 0x3fc7474d
	v_mul_f64 v[14:15], v[6:7], v[8:9]
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_mov_b32 s10, 0x16291751
	s_mov_b32 s11, 0x3fcc71c0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_mov_b32 s10, 0x9b27acf1
	s_mov_b32 s11, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_mov_b32 s10, 0x998ef7b6
	s_mov_b32 s11, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[12:13], s[8:9]
	v_ldexp_f64 v[12:13], v[6:7], 1
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_mul_f64 v[8:9], v[14:15], v[8:9]
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x204
	v_cvt_f64_i32_e32 v[14:15], v14
	v_add_f64 v[10:11], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[4:5], v[4:5], 1
	v_mul_f64 v[16:17], v[14:15], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[10:11], -v[12:13]
	v_fma_f64 v[12:13], v[14:15], s[4:5], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	v_fma_f64 v[8:9], v[14:15], s[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[10:11], v[4:5]
	v_add_f64 v[16:17], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[6:7], v[12:13]
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[14:15], -v[6:7]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[14:15], -v[18:19]
	v_add_f64 v[10:11], v[12:13], -v[18:19]
	v_add_f64 v[12:13], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[12:13], -v[8:9]
	v_add_f64 v[6:7], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[10:11]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	v_add_f64 v[16:17], v[14:15], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	v_add_f64 v[10:11], v[16:17], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[4:5], v[16:17], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v5, v3 :: v_dual_cndmask_b32 v4, v4, v2
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[2:3]
	v_cndmask_b32_e32 v5, 0x7ff80000, v5, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[2:3]
	v_cndmask_b32_e32 v5, 0xfff00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[4:5], v[0:1]
.LBB0_6:                                ; %Flow15
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z9logsumexpdd, .Lfunc_end0-_Z9logsumexpdd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2824
; NumSgprs: 34
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z15insidealgorithmPdPKdS1_iid ; -- Begin function _Z15insidealgorithmPdPKdS1_iid
	.globl	_Z15insidealgorithmPdPKdS1_iid
	.p2align	8
	.type	_Z15insidealgorithmPdPKdS1_iid,@function
_Z15insidealgorithmPdPKdS1_iid:         ; @_Z15insidealgorithmPdPKdS1_iid
; %bb.0:
	s_mov_b64 s[16:17], s[0:1]
	s_load_b32 s0, s[0:1], 0x34
	s_load_b64 s[18:19], s[16:17], 0x18
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s0
	s_sub_i32 s0, s19, s18
	v_add_nc_u32_e32 v25, s15, v0
	v_cmp_gt_i32_e32 vcc_lo, s0, v25
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_9
; %bb.1:                                ; %.preheader
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, S@rel32@lo+4
	s_addc_u32 s1, s1, S@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, L@rel32@lo+4
	s_addc_u32 s3, s3, L@rel32@hi+12
	s_mov_b32 s4, 0
	s_load_b32 s0, s[0:1], 0x0
	s_load_b128 s[20:23], s[16:17], 0x0
	s_load_b32 s2, s[2:3], 0x0
	s_cmp_gt_i32 s18, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s0, s19
	s_cbranch_scc1 .LBB1_3
; %bb.2:                                ; %.preheader.._crit_edge_crit_edge
	v_mad_u64_u32 v[1:2], null, s2, s19, v[25:26]
	s_mul_i32 s3, s0, s19
	s_mov_b32 s1, 0xc415af1d
	s_mov_b32 s0, 0x78b58c40
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v30, v1, s19
	s_branch .LBB1_4
.LBB1_3:
	s_mov_b32 s4, -1
                                        ; implicit-def: $sgpr0_sgpr1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr30
.LBB1_4:                                ; %Flow126
	v_dual_mov_b32 v23, s1 :: v_dual_add_nc_u32 v24, s18, v25
	v_mov_b32_e32 v22, s0
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_8
; %bb.5:                                ; %.lr.ph
	v_mad_u64_u32 v[1:2], null, s2, s19, v[25:26]
	v_add3_u32 v5, s15, s14, v0
	s_mov_b32 s0, s19
	v_mov_b32_e32 v31, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[3:4], null, s19, v5, s[0:1]
	v_mul_lo_u32 v30, v1, s19
	s_mov_b32 s0, 0x78b58c40
	s_mov_b32 s1, 0xc415af1d
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v23, s1 :: v_dual_add_nc_u32 v4, s18, v0
	v_mov_b32_e32 v22, s0
	v_add3_u32 v26, v4, v3, s15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v0, v30, s15
	s_mov_b32 s15, 0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v28, vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v29, vcc_lo, s21, v1, vcc_lo
.LBB1_6:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v27, 31, v26
	v_add_nc_u32_e32 v31, 1, v31
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	v_lshlrev_b64 v[0:1], 3, v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	global_load_b64 v[2:3], v[28:29], off
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[0:1]
	v_dual_mov_b32 v0, v22 :: v_dual_mov_b32 v1, v23
	s_swappc_b64 s[30:31], s[0:1]
	v_cmp_ge_i32_e32 vcc_lo, v31, v24
	v_add_co_u32 v28, s0, v28, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v22, v0 :: v_dual_mov_b32 v23, v1
	v_add_nc_u32_e32 v26, s19, v26
	v_add_co_ci_u32_e64 v29, s0, 0, v29, s0
	s_or_b32 s15, vcc_lo, s15
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB1_6
; %bb.7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s15
	s_mov_b32 s3, s14
.LBB1_8:                                ; %Flow127
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s3, v25
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r1logprob@rel32@lo+4
	s_addc_u32 s1, s1, r1logprob@rel32@hi+12
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s15, s15, _Z9logsumexpdd@rel32@hi+12
	v_mad_u64_u32 v[0:1], null, v2, s19, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v26, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v27, vcc_lo, s21, v1, vcc_lo
	global_load_b64 v[0:1], v[26:27], off
	s_load_b64 s[16:17], s[16:17], 0x20
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[2:3], s[0:1], s[16:17], v[22:23]
	s_swappc_b64 s[30:31], s[14:15]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, F@rel32@lo+4
	s_addc_u32 s1, s1, F@rel32@hi+12
	global_store_b64 v[26:27], v[0:1], off
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, s0, s19, v[25:26]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r5logprob@rel32@lo+4
	s_addc_u32 s1, s1, r5logprob@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v31, v2, s19
	v_add_nc_u32_e32 v2, v24, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v29, vcc_lo, s21, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[2:3], s[0:1], s[16:17], v[22:23]
	global_load_b64 v[0:1], v[28:29], off
	s_swappc_b64 s[30:31], s[14:15]
	v_mul_lo_u32 v2, v25, s19
	v_add_nc_u32_e32 v3, s19, v31
	v_ashrrev_i32_e32 v5, 31, v24
	global_store_b64 v[28:29], v[0:1], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r3logprob@rel32@lo+4
	s_addc_u32 s1, s1, r3logprob@rel32@hi+12
	v_ashrrev_i32_e32 v6, 31, v3
	v_add_co_u32 v4, vcc_lo, v24, v3
	v_add3_u32 v2, v2, v25, s18
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v6, vcc_lo
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
	global_load_b64 v[4:5], v[4:5], off offset:-8
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[0:1], v[26:27], off
	s_waitcnt vmcnt(1)
	v_fma_f64 v[22:23], v[2:3], s[16:17], v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], s[0:1], s[16:17], v[22:23]
	s_swappc_b64 s[30:31], s[14:15]
	global_store_b64 v[26:27], v[0:1], off
	global_load_b64 v[0:1], v[28:29], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r4logprob@rel32@lo+4
	s_addc_u32 s1, s1, r4logprob@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[2:3], s[0:1], s[16:17], v[22:23]
	s_swappc_b64 s[30:31], s[14:15]
	v_add_nc_u32_e32 v2, v24, v30
	global_store_b64 v[28:29], v[0:1], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r7logprob@rel32@lo+4
	s_addc_u32 s1, s1, r7logprob@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v24, vcc_lo, s20, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v25, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[0:1], v[24:25], off
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[2:3], s[0:1], s[16:17], v[22:23]
	s_swappc_b64 s[30:31], s[14:15]
	global_store_b64 v[24:25], v[0:1], off
.LBB1_9:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15insidealgorithmPdPKdS1_iid
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15insidealgorithmPdPKdS1_iid, .Lfunc_end1-_Z15insidealgorithmPdPKdS1_iid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1132
; NumSgprs: 35
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16outsidealgorithmPdPKdS1_S1_iid ; -- Begin function _Z16outsidealgorithmPdPKdS1_S1_iid
	.globl	_Z16outsidealgorithmPdPKdS1_S1_iid
	.p2align	8
	.type	_Z16outsidealgorithmPdPKdS1_S1_iid,@function
_Z16outsidealgorithmPdPKdS1_S1_iid:     ; @_Z16outsidealgorithmPdPKdS1_S1_iid
; %bb.0:
	s_mov_b64 s[18:19], s[0:1]
	s_load_b32 s0, s[0:1], 0x3c
	s_load_b64 s[24:25], s[18:19], 0x20
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s34, s15, s0
	s_sub_i32 s0, s25, s24
	v_add_nc_u32_e32 v23, s34, v0
	v_cmp_gt_i32_e32 vcc_lo, s0, v23
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB2_19
; %bb.1:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, S@rel32@lo+4
	s_addc_u32 s1, s1, S@rel32@hi+12
	v_add_nc_u32_e32 v24, s24, v0
	s_load_b32 s36, s[0:1], 0x0
	s_clause 0x1
	s_load_b128 s[20:23], s[18:19], 0x0
	s_load_b64 s[26:27], s[18:19], 0x10
	s_mov_b32 s0, 0x78b58c40
	s_mov_b32 s1, 0xc415af1d
	v_add_nc_u32_e32 v22, s24, v23
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s15, s36, s25
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v33, 1, v22
	v_add_nc_u32_e32 v30, s15, v23
	v_add_nc_u32_e32 v29, s15, v33
	v_cmp_gt_i32_e64 s16, s25, v33
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s14, s16
	s_cbranch_execz .LBB2_5
; %bb.2:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[0:1], null, v29, s25, v[24:25]
	v_mad_u64_u32 v[1:2], null, v30, s25, v[24:25]
	v_mov_b32_e32 v31, v33
	s_mov_b32 s17, 0
	v_add3_u32 v0, v0, s34, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v2, v1, s34, 1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v25, vcc_lo, s22, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v26, vcc_lo, s23, v5, vcc_lo
	v_add_co_u32 v27, vcc_lo, s20, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v28, vcc_lo, s21, v3, vcc_lo
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[2:3], v[27:28], off
	global_load_b64 v[4:5], v[25:26], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	s_swappc_b64 s[30:31], s[0:1]
	v_add_nc_u32_e32 v31, 1, v31
	v_add_co_u32 v25, vcc_lo, v25, 8
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s25, v31
	v_add_co_u32 v27, s0, v27, 8
	v_add_co_ci_u32_e64 v28, s0, 0, v28, s0
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB2_3
; %bb.4:                                ; %Flow271
	s_or_b32 exec_lo, exec_lo, s17
.LBB2_5:                                ; %Flow272
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s14
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, L@rel32@lo+4
	s_addc_u32 s1, s1, L@rel32@hi+12
	s_load_b32 s33, s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r1logprob@rel32@lo+4
	s_addc_u32 s1, s1, r1logprob@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s17, s33, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, s17, v23
	v_mad_u64_u32 v[2:3], null, v4, s25, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v26, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[4:5], v[25:26], off
	s_load_b64 s[18:19], s[18:19], 0x28
	s_load_b64 s[28:29], s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[2:3], s[28:29], s[18:19], v[0:1]
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
	s_swappc_b64 s[30:31], s[0:1]
	s_mov_b32 s0, 0x78b58c40
	s_mov_b32 s1, 0xc415af1d
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
	v_cmp_lt_i32_e64 s14, 0, v23
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	s_mul_i32 s35, s25, s25
	s_mov_b32 s38, 0
	s_mul_i32 s33, s33, s35
	global_store_b64 v[25:26], v[2:3], off
	s_and_saveexec_b32 s37, s14
	s_cbranch_execz .LBB2_9
; %bb.6:                                ; %.lr.ph194.preheader
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	v_mov_b32_e32 v27, v23
	v_mov_b32_e32 v28, v23
	s_mul_i32 s0, s36, s35
	s_add_u32 s39, s22, -8
	s_addc_u32 s36, s23, -1
	s_add_i32 s40, s24, s0
.LBB2_7:                                ; %.lr.ph194
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s40, v27
	v_add_nc_u32_e32 v4, s33, v27
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s39, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s36, v5, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	s_swappc_b64 s[30:31], s[0:1]
	v_add_nc_u32_e32 v28, -1, v28
	v_add_nc_u32_e32 v27, s25, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	s_or_b32 s38, vcc_lo, s38
	s_and_not1_b32 exec_lo, exec_lo, s38
	s_cbranch_execnz .LBB2_7
; %bb.8:                                ; %Flow269
	s_or_b32 exec_lo, exec_lo, s38
.LBB2_9:                                ; %Flow270
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s37
	v_mad_u64_u32 v[4:5], null, v30, s25, v[22:23]
	v_mul_f64 v[2:3], s[28:29], s[18:19]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v28, vcc_lo, s21, v5, vcc_lo
	global_load_b64 v[4:5], v[27:28], off
	v_add_f64 v[2:3], v[2:3], v[0:1]
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	s_swappc_b64 s[30:31], s[0:1]
	s_mov_b32 s0, 0x78b58c40
	s_mov_b32 s1, 0xc415af1d
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	global_store_b64 v[27:28], v[2:3], off
	s_and_saveexec_b32 s28, s16
	s_cbranch_execz .LBB2_13
; %bb.10:                               ; %.lr.ph200
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, F@rel32@lo+4
	s_addc_u32 s3, s3, F@rel32@hi+12
	s_mov_b32 s29, 0
	s_load_b32 s2, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[0:1], null, s2, s25, v[23:24]
	v_mad_u64_u32 v[1:2], null, v29, s25, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v0, s25, v[24:25]
	v_add3_u32 v0, v1, s34, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add3_u32 v2, v2, s34, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, s22, v0
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v30, vcc_lo, s23, v1, vcc_lo
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	v_add_co_u32 v31, vcc_lo, s20, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v32, vcc_lo, s21, v3, vcc_lo
.LBB2_11:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[2:3], v[31:32], off
	global_load_b64 v[4:5], v[29:30], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	s_swappc_b64 s[30:31], s[0:1]
	v_add_nc_u32_e32 v33, 1, v33
	v_add_co_u32 v29, vcc_lo, v29, 8
	v_add_co_ci_u32_e32 v30, vcc_lo, 0, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s25, v33
	v_add_co_u32 v31, s0, v31, 8
	v_add_co_ci_u32_e64 v32, s0, 0, v32, s0
	s_or_b32 s29, vcc_lo, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s29
	s_cbranch_execnz .LBB2_11
; %bb.12:                               ; %Flow267
	s_or_b32 exec_lo, exec_lo, s29
.LBB2_13:                               ; %Flow268
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s28
	global_load_b64 v[4:5], v[25:26], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r5logprob@rel32@lo+4
	s_addc_u32 s1, s1, r5logprob@rel32@hi+12
	s_load_b64 s[28:29], s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[2:3], s[28:29], s[18:19], v[0:1]
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	s_swappc_b64 s[30:31], s[0:1]
	s_mov_b32 s0, 0x78b58c40
	s_mov_b32 s1, 0xc415af1d
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	global_store_b64 v[25:26], v[2:3], off
	s_and_saveexec_b32 s34, s14
	s_cbranch_execz .LBB2_17
; %bb.14:                               ; %.lr.ph208
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, F@rel32@lo+4
	s_addc_u32 s3, s3, F@rel32@hi+12
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	s_load_b32 s2, s[2:3], 0x0
	v_mov_b32_e32 v24, v23
	v_mov_b32_e32 v25, v23
	s_add_u32 s22, s22, -8
	s_addc_u32 s23, s23, -1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s35
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s35, s24, s2
	s_mov_b32 s24, 0
.LBB2_15:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s35, v24
	v_add_nc_u32_e32 v4, s33, v24
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s1, s1, _Z9logsumexpdd@rel32@hi+12
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s22, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v5, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	s_swappc_b64 s[30:31], s[0:1]
	v_add_nc_u32_e32 v25, -1, v25
	v_add_nc_u32_e32 v24, s25, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_or_b32 s24, vcc_lo, s24
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB2_15
; %bb.16:                               ; %Flow265
	s_or_b32 exec_lo, exec_lo, s24
.LBB2_17:                               ; %Flow266
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s34
	global_load_b64 v[4:5], v[27:28], off
	v_mul_f64 v[2:3], s[28:29], s[18:19]
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, _Z9logsumexpdd@rel32@lo+4
	s_addc_u32 s23, s23, _Z9logsumexpdd@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[0:1]
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	s_swappc_b64 s[30:31], s[22:23]
	s_and_b32 s0, s14, s16
	global_store_b64 v[27:28], v[0:1], off
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_19
; %bb.18:
	v_add_nc_u32_e32 v28, -1, v23
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, F@rel32@lo+4
	s_addc_u32 s1, s1, F@rel32@hi+12
	s_load_b32 s0, s[0:1], 0x0
	v_add_nc_u32_e32 v2, s15, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s25, v[22:23]
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s0, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r3logprob@rel32@lo+4
	s_addc_u32 s1, s1, r3logprob@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	global_load_b64 v[2:3], v[0:1], off offset:8
	v_mul_lo_u32 v0, v28, s25
	v_ashrrev_i32_e32 v1, 31, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v0
	v_add_co_u32 v0, vcc_lo, v0, v22
	v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
	v_add_nc_u32_e32 v4, s14, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s26, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s27, v1, vcc_lo
	global_load_b64 v[24:25], v[0:1], off offset:8
	v_mad_u64_u32 v[0:1], null, v4, s25, v[22:23]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v26, vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v27, vcc_lo, s21, v1, vcc_lo
	global_load_b64 v[0:1], v[26:27], off
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_fma_f64 v[2:3], s[0:1], s[18:19], v[2:3]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[2:3], v[24:25], s[18:19], v[2:3]
	s_swappc_b64 s[30:31], s[22:23]
	v_add_nc_u32_e32 v4, s14, v28
	global_store_b64 v[26:27], v[0:1], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r4logprob@rel32@lo+4
	s_addc_u32 s1, s1, r4logprob@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v4, s25, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off offset:8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[2:3], s[0:1], s[18:19], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[24:25], s[18:19], v[2:3]
	s_swappc_b64 s[30:31], s[22:23]
	v_add_nc_u32_e32 v4, s17, v28
	global_store_b64 v[26:27], v[0:1], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, r7logprob@rel32@lo+4
	s_addc_u32 s1, s1, r7logprob@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v4, s25, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off offset:8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[2:3], s[0:1], s[18:19], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[24:25], s[18:19], v[2:3]
	s_swappc_b64 s[30:31], s[22:23]
	global_store_b64 v[26:27], v[0:1], off
.LBB2_19:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16outsidealgorithmPdPKdS1_S1_iid
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 34
		.amdhsa_next_free_sgpr 41
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z16outsidealgorithmPdPKdS1_S1_iid, .Lfunc_end2-_Z16outsidealgorithmPdPKdS1_S1_iid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2264
; NumSgprs: 43
; NumVgprs: 34
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 43
; NumVGPRsForWavesPerEU: 34
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	S                       ; @S
	.type	S,@object
	.section	.bss,"aw",@nobits
	.globl	S
	.p2align	2, 0x0
S:
	.long	0                               ; 0x0
	.size	S, 4

	.protected	F                       ; @F
	.type	F,@object
	.data
	.globl	F
	.p2align	2, 0x0
F:
	.long	1                               ; 0x1
	.size	F, 4

	.protected	L                       ; @L
	.type	L,@object
	.globl	L
	.p2align	2, 0x0
L:
	.long	2                               ; 0x2
	.size	L, 4

	.protected	r1logprob               ; @r1logprob
	.type	r1logprob,@object
	.globl	r1logprob
	.p2align	3, 0x0
r1logprob:
	.quad	0xbfc20a9a19fb0889              ; double -0.14094854610999999
	.size	r1logprob, 8

	.protected	r2logprob               ; @r2logprob
	.type	r2logprob,@object
	.globl	r2logprob
	.p2align	3, 0x0
r2logprob:
	.quad	0xc0011f80bab55110              ; double -2.1403822504600001
	.size	r2logprob, 8

	.protected	r3logprob               ; @r3logprob
	.type	r3logprob,@object
	.globl	r3logprob
	.p2align	3, 0x0
r3logprob:
	.quad	0xc0111db98c4e3997              ; double -4.2790281222099997
	.size	r3logprob, 8

	.protected	r4logprob               ; @r4logprob
	.type	r4logprob,@object
	.globl	r4logprob
	.p2align	3, 0x0
r4logprob:
	.quad	0xbfce8e2f65b9bc51              ; double -0.23871414630000001
	.size	r4logprob, 8

	.protected	r5logprob               ; @r5logprob
	.type	r5logprob,@object
	.globl	r5logprob
	.p2align	3, 0x0
r5logprob:
	.quad	0xbff8caa37fbb3aee              ; double -1.549472331
	.size	r5logprob, 8

	.protected	r6logprob               ; @r6logprob
	.type	r6logprob,@object
	.globl	r6logprob
	.p2align	3, 0x0
r6logprob:
	.quad	0xbfbc83165de4039a              ; double -0.11137523453000001
	.size	r6logprob, 8

	.protected	r7logprob               ; @r7logprob
	.type	r7logprob,@object
	.globl	r7logprob
	.p2align	3, 0x0
r7logprob:
	.quad	0xc002000b10d6423c              ; double -2.2500211062800002
	.size	r7logprob, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym S
	.addrsig_sym F
	.addrsig_sym L
	.addrsig_sym r1logprob
	.addrsig_sym r3logprob
	.addrsig_sym r4logprob
	.addrsig_sym r5logprob
	.addrsig_sym r7logprob
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15insidealgorithmPdPKdS1_iid
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z15insidealgorithmPdPKdS1_iid.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16outsidealgorithmPdPKdS1_S1_iid
    .private_segment_fixed_size: 0
    .sgpr_count:     43
    .sgpr_spill_count: 0
    .symbol:         _Z16outsidealgorithmPdPKdS1_S1_iid.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     34
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
