/*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
#include <vector>



static inline void check(cudaError_t err, const char* context) {
  if (err != cudaSuccess) {
      std::cerr << "CUDA error: " << context << ": "
          << cudaGetErrorString(err) << std::endl;
      std::exit(EXIT_FAILURE);
  }
}

#define CHECK(x) check(x, #x)

template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, cudaMemcpyKind direction) {
  CHECK(cudaMemcpy(target, source, num * sizeof(T), direction));
}

  // params: 
  //         data : transposed padding data
  

__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
  const int nd=8;//         nd:    nd==blockDim.x==blockDim.y
                  //                compute nd*nd results each thread.

  // int step=nd*nd;// each block will compute step*step results.
  int ia=threadIdx.x;
  int ja=threadIdx.y;
  int ic=blockIdx.x;
  int jc=blockIdx.y;
  // int i=ic*step+ib*nd+ia;
  // int j=jc*step+jb*nd+ja;
  // 0<=ia<=nd, 0<=ja<=nd
  // if ic>jc , then i>j
  if(ic>jc){ 
    for(int ib=0; ib<nd; ib++){
      for(int jb=0; jb<nd; jb++){
        int i=(ic*nd+ib)*nd+ia;
        int j=(jc*nd+jb)*nd+ja;
        if(i<ny&&j<ny){
          result[ny*i+j]=0;
        }
      }
    }
  }else{
    float v[nd][nd];
    // double temp=0;
    for(int ib=0; ib<nd; ib++){
      for(int jb=0; jb<nd; jb++){
        v[ib][jb]=0;
      }
    }

    for (int k=0; k<nx; ++k){
      float x[nd];
      float y[nd];
      for(int ii=0; ii<nd; ii++){
        int i=(ic*nd+ii)*nd+ia;
        int j=(jc*nd+ii)*nd+ja;
        x[ii]=data[k*new_ny +i];
        y[ii]=data[k*new_ny +j];
      }



      for(int ib=0; ib<nd; ib++){
        for(int jb=0; jb<nd; jb++){
            v[ib][jb]+=x[ib]*y[jb];
        }
      }
    }
    for(int ib=0; ib<nd; ib++){
      for(int jb=0; jb<nd; jb++){
        int i=(ic*nd+ib)*nd+ia;
        int j=(jc*nd+jb)*nd+ja;
        if(i<ny&&j<ny){
          result[ny*i+j]=v[ib][jb];
        }
      }
    }
  }
  

  // result[i*ny+j]=temp;
}

__global__ void normalize(int ny, int nx, float*data, int step){
  int i = blockIdx.x;
  int j = threadIdx.x;
  int row=i*step+j;
  
  if (row<ny){
    // printf("row is %d \n", row);
    //for each row
    float temp=0, avg=0, sqrtSqureSum=0;
    for (int x=0; x<nx; ++x){
      temp+=data[row*nx+x];
    }
    avg=temp/nx;
    for (int x=0; x<nx; ++x){
      data[row*nx+x]=data[row*nx+x]-avg;
    }

    for (int x=0; x<nx; ++x){
      sqrtSqureSum+=powf(data[row*nx+x],2);
    }
    sqrtSqureSum=sqrtf(sqrtSqureSum);

    for (int x=0; x<nx; ++x){
      data[row*nx+x]/=sqrtSqureSum;
    }
  }
}


__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
  //result is padding and transpose data
  int ja=threadIdx.x;
  int i=blockIdx.y;
  
  for (int jb=0; jb<nx; jb+=blockDim.x){
    int j=jb+ja;
    if (j>=nx) break;
    float v=i<ny?data[i*nx+j]:0.0; //padding
    result[new_ny*j+i]=v; //transpose
  }
}


static inline int divup(int a, int b) {
  return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
  return divup(a, b) * b;
}


void correlate(int ny, int nx, const float *data, float *result) {


  // const int nd=16;//compute nd*nd results each thread. could not less than 
  const int block_size=8; //16*16 threads
  const int step=block_size*block_size; // each block will compute step*step results.

  int new_ny=roundup(ny,step);
  
  //allocate memory & copy data to GPU
  float *dGPU=NULL;
  CHECK(cudaMalloc((void**)&dGPU,ny*nx*sizeof(float)));

  float *padding=NULL;
  CHECK(cudaMalloc((void**)&padding,new_ny*nx*sizeof(float)));

  float *rGPU=NULL;
  CHECK(cudaMalloc((void**)&rGPU,ny*ny*sizeof(float)));

  cuda_memcpy(dGPU,data,ny*nx,cudaMemcpyHostToDevice);


  {
    normalize<<<divup(ny,step),step>>>(ny,nx,dGPU,step);
  }

  // Run kernel to padding and transpose
  {
    dim3 dimBlock(64,1);
    dim3 dimGrid(1,new_ny);
    padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
    CHECK(cudaGetLastError());
  }


  // Run kernel to calculate cp
  {
    dim3 dimBlock(block_size,block_size);
    dim3 dimGrid(new_ny/step,new_ny/step);
    correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
    CHECK(cudaGetLastError());
  }
    
  
  cuda_memcpy(result, rGPU, ny * ny, cudaMemcpyDeviceToHost);
  // CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
  CHECK(cudaFree(dGPU));
  CHECK(cudaFree(padding));
  CHECK(cudaFree(rGPU));
  // delete[] normalized;
}


	.file	"tmpxft_002f8472_00000000-6_cp.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4005:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4005:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
.LC1:
	.string	": "
	.text
	.type	_ZL5check9cudaErrorPKc, @function
_ZL5check9cudaErrorPKc:
.LFB3998:
	.cfi_startproc
	testl	%edi, %edi
	je	.L2
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	leaq	.LC0(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3998:
	.size	_ZL5check9cudaErrorPKc, .-_ZL5check9cudaErrorPKc
	.globl	_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
	.type	_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, @function
_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi:
.LFB4027:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13correlate_gpuiiPKfPfi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4027:
	.size	_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, .-_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
	.globl	_Z13correlate_gpuiiPKfPfi
	.type	_Z13correlate_gpuiiPKfPfi, @function
_Z13correlate_gpuiiPKfPfi:
.LFB4028:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
	.cfi_endproc
.LFE4028:
	.size	_Z13correlate_gpuiiPKfPfi, .-_Z13correlate_gpuiiPKfPfi
	.globl	_Z31__device_stub__Z9normalizeiiPfiiiPfi
	.type	_Z31__device_stub__Z9normalizeiiPfiiiPfi, @function
_Z31__device_stub__Z9normalizeiiPfiiiPfi:
.LFB4029:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9normalizeiiPfi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4029:
	.size	_Z31__device_stub__Z9normalizeiiPfiiiPfi, .-_Z31__device_stub__Z9normalizeiiPfiiiPfi
	.globl	_Z9normalizeiiPfi
	.type	_Z9normalizeiiPfi, @function
_Z9normalizeiiPfi:
.LFB4030:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9normalizeiiPfiiiPfi
	.cfi_endproc
.LFE4030:
	.size	_Z9normalizeiiPfi, .-_Z9normalizeiiPfi
	.globl	_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
	.type	_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, @function
_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi:
.LFB4031:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z17padding_transposeiiPKfPfi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4031:
	.size	_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, .-_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
	.globl	_Z17padding_transposeiiPKfPfi
	.type	_Z17padding_transposeiiPKfPfi, @function
_Z17padding_transposeiiPKfPfi:
.LFB4032:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
	.cfi_endproc
.LFE4032:
	.size	_Z17padding_transposeiiPKfPfi, .-_Z17padding_transposeiiPKfPfi
	.section	.rodata.str1.1
.LC2:
	.string	"cudaMalloc((void**)&dGPU,ny*nx*sizeof(float))"
.LC3:
	.string	"cudaMalloc((void**)&padding,new_ny*nx*sizeof(float))"
.LC4:
	.string	"cudaMalloc((void**)&rGPU,ny*ny*sizeof(float))"
.LC5:
	.string	"cudaMemcpy(target, source, num * sizeof(T), direction)"
.LC6:
	.string	"cudaGetLastError()"
.LC7:
	.string	"cudaFree(dGPU)"
.LC8:
	.string	"cudaFree(padding)"
.LC9:
	.string	"cudaFree(rGPU)"
	.text
	.globl	_Z9correlateiiPKfPf
	.type	_Z9correlateiiPKfPf, @function
_Z9correlateiiPKfPf:
.LFB4002:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	movl	$64, %ecx
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leal	63(%rdi), %eax
	cltd
	idivl	%ecx
	movl	%edi, %edx
	leaq	24(%rsp), %rdi
	imull	%esi, %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	movq	%rdx, %rsi
	movq	%rdx, 8(%rsp)
	movl	%eax, %r12d
	movl	%eax, %r13d
	xorl	%eax, %eax
	movq	%rax, 24(%rsp)
	sall	$6, %r13d
	call	cudaMalloc@PLT
	leaq	.LC2(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movl	%ebp, %esi
	xorl	%edx, %edx
	leaq	32(%rsp), %rdi
	imull	%r13d, %esi
	movq	%rdx, 32(%rsp)
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movl	%ebx, %eax
	xorl	%ecx, %ecx
	leaq	40(%rsp), %rdi
	imull	%ebx, %eax
	movq	%rcx, 40(%rsp)
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movl	%r12d, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$67108865, %edx
	movl	$1, %ecx
	movl	$1, 68(%rsp)
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	salq	$6, %rdx
	movl	56(%rsp), %esi
	movq	%rdx, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	24(%rsp), %rdx
	movl	$64, %ecx
	movl	%ebp, %esi
	movl	%ebx, %edi
	call	_Z31__device_stub__Z9normalizeiiPfiiiPfi
.L24:
	movl	%r13d, 64(%rsp)
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, 60(%rsp)
	movq	60(%rsp), %rdi
	movl	$1, %esi
	movq	%rdx, 48(%rsp)
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movl	%r13d, %r8d
	movl	%ebp, %esi
	movl	%ebx, %edi
	call	_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.L25:
	call	cudaGetLastError@PLT
	leaq	.LC6(%rip), %r15
	movl	%eax, %edi
	movq	%r15, %rsi
	call	_ZL5check9cudaErrorPKc
	movl	%r12d, 60(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%r12d, 64(%rsp)
	movq	60(%rsp), %rdi
	movl	$1, %ecx
	movabsq	$34359738376, %rdx
	movl	$1, %esi
	movq	%rdx, 48(%rsp)
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	%r13d, %r8d
	movl	%ebp, %esi
	movl	%ebx, %edi
	call	_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.L26:
	call	cudaGetLastError@PLT
	movq	%r15, %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	%r14, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC7(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC8(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC9(%rip), %rsi
	movl	%eax, %edi
	call	_ZL5check9cudaErrorPKc
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4002:
	.size	_Z9correlateiiPKfPf, .-_Z9correlateiiPKfPf
	.section	.rodata.str1.1
.LC10:
	.string	"_Z17padding_transposeiiPKfPfi"
.LC11:
	.string	"_Z9normalizeiiPfi"
.LC12:
	.string	"_Z13correlate_gpuiiPKfPfi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4034:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17padding_transposeiiPKfPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9normalizeiiPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13correlate_gpuiiPKfPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4034:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <hip/hip_runtime.h>

#include <iostream>
#include <math.h>
#include <vector>



static inline void check(hipError_t err, const char* context) {
  if (err != hipSuccess) {
      std::cerr << "CUDA error: " << context << ": "
          << hipGetErrorString(err) << std::endl;
      std::exit(EXIT_FAILURE);
  }
}

#define CHECK(x) check(x, #x)

template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, hipMemcpyKind direction) {
  CHECK(hipMemcpy(target, source, num * sizeof(T), direction));
}

  // params: 
  //         data : transposed padding data
  

__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
  const int nd=8;//         nd:    nd==blockDim.x==blockDim.y
                  //                compute nd*nd results each thread.

  // int step=nd*nd;// each block will compute step*step results.
  int ia=threadIdx.x;
  int ja=threadIdx.y;
  int ic=blockIdx.x;
  int jc=blockIdx.y;
  // int i=ic*step+ib*nd+ia;
  // int j=jc*step+jb*nd+ja;
  // 0<=ia<=nd, 0<=ja<=nd
  // if ic>jc , then i>j
  if(ic>jc){ 
    for(int ib=0; ib<nd; ib++){
      for(int jb=0; jb<nd; jb++){
        int i=(ic*nd+ib)*nd+ia;
        int j=(jc*nd+jb)*nd+ja;
        if(i<ny&&j<ny){
          result[ny*i+j]=0;
        }
      }
    }
  }else{
    float v[nd][nd];
    // double temp=0;
    for(int ib=0; ib<nd; ib++){
      for(int jb=0; jb<nd; jb++){
        v[ib][jb]=0;
      }
    }

    for (int k=0; k<nx; ++k){
      float x[nd];
      float y[nd];
      for(int ii=0; ii<nd; ii++){
        int i=(ic*nd+ii)*nd+ia;
        int j=(jc*nd+ii)*nd+ja;
        x[ii]=data[k*new_ny +i];
        y[ii]=data[k*new_ny +j];
      }



      for(int ib=0; ib<nd; ib++){
        for(int jb=0; jb<nd; jb++){
            v[ib][jb]+=x[ib]*y[jb];
        }
      }
    }
    for(int ib=0; ib<nd; ib++){
      for(int jb=0; jb<nd; jb++){
        int i=(ic*nd+ib)*nd+ia;
        int j=(jc*nd+jb)*nd+ja;
        if(i<ny&&j<ny){
          result[ny*i+j]=v[ib][jb];
        }
      }
    }
  }
  

  // result[i*ny+j]=temp;
}

__global__ void normalize(int ny, int nx, float*data, int step){
  int i = blockIdx.x;
  int j = threadIdx.x;
  int row=i*step+j;
  
  if (row<ny){
    // printf("row is %d \n", row);
    //for each row
    float temp=0, avg=0, sqrtSqureSum=0;
    for (int x=0; x<nx; ++x){
      temp+=data[row*nx+x];
    }
    avg=temp/nx;
    for (int x=0; x<nx; ++x){
      data[row*nx+x]=data[row*nx+x]-avg;
    }

    for (int x=0; x<nx; ++x){
      sqrtSqureSum+=powf(data[row*nx+x],2);
    }
    sqrtSqureSum=sqrtf(sqrtSqureSum);

    for (int x=0; x<nx; ++x){
      data[row*nx+x]/=sqrtSqureSum;
    }
  }
}


__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
  //result is padding and transpose data
  int ja=threadIdx.x;
  int i=blockIdx.y;
  
  for (int jb=0; jb<nx; jb+=blockDim.x){
    int j=jb+ja;
    if (j>=nx) break;
    float v=i<ny?data[i*nx+j]:0.0; //padding
    result[new_ny*j+i]=v; //transpose
  }
}


static inline int divup(int a, int b) {
  return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
  return divup(a, b) * b;
}


void correlate(int ny, int nx, const float *data, float *result) {


  // const int nd=16;//compute nd*nd results each thread. could not less than 
  const int block_size=8; //16*16 threads
  const int step=block_size*block_size; // each block will compute step*step results.

  int new_ny=roundup(ny,step);
  
  //allocate memory & copy data to GPU
  float *dGPU=NULL;
  CHECK(hipMalloc((void**)&dGPU,ny*nx*sizeof(float)));

  float *padding=NULL;
  CHECK(hipMalloc((void**)&padding,new_ny*nx*sizeof(float)));

  float *rGPU=NULL;
  CHECK(hipMalloc((void**)&rGPU,ny*ny*sizeof(float)));

  cuda_memcpy(dGPU,data,ny*nx,hipMemcpyHostToDevice);


  {
    normalize<<<divup(ny,step),step>>>(ny,nx,dGPU,step);
  }

  // Run kernel to padding and transpose
  {
    dim3 dimBlock(64,1);
    dim3 dimGrid(1,new_ny);
    padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
    CHECK(hipGetLastError());
  }


  // Run kernel to calculate cp
  {
    dim3 dimBlock(block_size,block_size);
    dim3 dimGrid(new_ny/step,new_ny/step);
    correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
    CHECK(hipGetLastError());
  }
    
  
  cuda_memcpy(result, rGPU, ny * ny, hipMemcpyDeviceToHost);
  // CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
  CHECK(hipFree(dGPU));
  CHECK(hipFree(padding));
  CHECK(hipFree(rGPU));
  // delete[] normalized;
}


	.text
	.file	"cp.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z28__device_stub__correlate_gpuiiPKfPfi # -- Begin function _Z28__device_stub__correlate_gpuiiPKfPfi
	.type	_Z28__device_stub__correlate_gpuiiPKfPfi,@function
_Z28__device_stub__correlate_gpuiiPKfPfi: # @_Z28__device_stub__correlate_gpuiiPKfPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13correlate_gpuiiPKfPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__correlate_gpuiiPKfPfi, .Lfunc_end0-_Z28__device_stub__correlate_gpuiiPKfPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__normalizeiiPfi # -- Begin function _Z24__device_stub__normalizeiiPfi
	.type	_Z24__device_stub__normalizeiiPfi,@function
_Z24__device_stub__normalizeiiPfi:      # @_Z24__device_stub__normalizeiiPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9normalizeiiPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__normalizeiiPfi, .Lfunc_end1-_Z24__device_stub__normalizeiiPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__padding_transposeiiPKfPfi # -- Begin function _Z32__device_stub__padding_transposeiiPKfPfi
	.type	_Z32__device_stub__padding_transposeiiPKfPfi,@function
_Z32__device_stub__padding_transposeiiPKfPfi: # @_Z32__device_stub__padding_transposeiiPKfPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17padding_transposeiiPKfPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__padding_transposeiiPKfPfi, .Lfunc_end2-_Z32__device_stub__padding_transposeiiPKfPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z9correlateiiPKfPf             # -- Begin function _Z9correlateiiPKfPf
	.type	_Z9correlateiiPKfPf,@function
_Z9correlateiiPKfPf:                    # @_Z9correlateiiPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %r12
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movl	%esi, %r13d
	movl	%edi, %r14d
	leal	63(%r14), %eax
	leal	126(%r14), %ebx
	testl	%eax, %eax
	cmovnsl	%eax, %ebx
	leaq	16(%rsp), %rdi
	movq	$0, (%rdi)
	movl	%esi, %eax
	imull	%r14d, %eax
	movslq	%eax, %rbp
	leaq	(,%rbp,4), %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.4:                                # %_ZL5check10hipError_tPKc.exit
	movq	%r12, 40(%rsp)                  # 8-byte Spill
	movl	%ebx, %r15d
	andl	$-64, %r15d
	leaq	32(%rsp), %rdi
	movq	$0, (%rdi)
	movl	%r15d, %eax
	movl	%r13d, 12(%rsp)                 # 4-byte Spill
	imull	%r13d, %eax
	movslq	%eax, %rsi
	shlq	$2, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_5
# %bb.6:                                # %_ZL5check10hipError_tPKc.exit45
	leaq	24(%rsp), %rdi
	movq	$0, (%rdi)
	movl	%r14d, %r12d
	imull	%r12d, %r12d
	leaq	(,%r12,4), %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_7
# %bb.8:                                # %_ZL5check10hipError_tPKc.exit47
	sarl	$6, %ebx
	movabsq	$4294967360, %r13               # imm = 0x100000040
	movq	16(%rsp), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
	movl	%ebx, %ebx
	leaq	(%rbx,%r13), %rdi
	addq	$-64, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	movq	16(%rsp), %rdx
	movl	%r14d, %edi
	movl	12(%rsp), %esi                  # 4-byte Reload
	movl	$64, %ecx
	callq	_Z24__device_stub__normalizeiiPfi
.LBB3_10:
	movq	%r15, %rdi
	shlq	$32, %rdi
	orq	$1, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_12
# %bb.11:
	movq	16(%rsp), %rdx
	movq	32(%rsp), %rcx
	movl	%r14d, %edi
	movl	12(%rsp), %esi                  # 4-byte Reload
	movl	%r15d, %r8d
	callq	_Z32__device_stub__padding_transposeiiPKfPfi
.LBB3_12:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB3_13
# %bb.14:                               # %_ZL5check10hipError_tPKc.exit49
	addq	$-63, %r13
	imulq	%r13, %rbx
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_16
# %bb.15:
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	%r14d, %edi
	movl	12(%rsp), %esi                  # 4-byte Reload
	movl	%r15d, %r8d
	callq	_Z28__device_stub__correlate_gpuiiPKfPfi
.LBB3_16:
	callq	hipGetLastError
	testl	%eax, %eax
	movq	40(%rsp), %rdi                  # 8-byte Reload
	jne	.LBB3_17
# %bb.19:                               # %_ZL5check10hipError_tPKc.exit51
	movq	24(%rsp), %rsi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB3_20
# %bb.21:                               # %_ZL5check10hipError_tPKc.exit53
	movq	32(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB3_22
# %bb.23:                               # %_ZL5check10hipError_tPKc.exit55
	movq	24(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB3_24
# %bb.25:                               # %_ZL5check10hipError_tPKc.exit57
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_1:
	.cfi_def_cfa_offset 112
	movl	%eax, %r15d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.8, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%r15d, %edi
	jmp	.LBB3_2
.LBB3_5:
	movl	%eax, %r12d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.8, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%r12d, %edi
	jmp	.LBB3_2
.LBB3_7:
	movl	%eax, %r13d
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.8, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%r13d, %edi
	jmp	.LBB3_2
.LBB3_13:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.8, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rbx
	movl	%ebp, %edi
.LBB3_2:
	callq	hipGetErrorString
	movq	%rbx, %rdi
	jmp	.LBB3_3
.LBB3_17:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.3, %esi
	jmp	.LBB3_18
.LBB3_20:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.4, %esi
	jmp	.LBB3_18
.LBB3_22:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.5, %esi
	jmp	.LBB3_18
.LBB3_24:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.6, %esi
.LBB3_18:
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.8, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
.LBB3_3:
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end3:
	.size	_Z9correlateiiPKfPf, .Lfunc_end3-_Z9correlateiiPKfPf
	.cfi_endproc
                                        # -- End function
	.section	.text._Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,"axG",@progbits,_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,comdat
	.weak	_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind # -- Begin function _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
	.type	_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,@function
_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind: # @_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	shlq	$2, %rdx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:                                # %_ZL5check10hipError_tPKc.exit
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 32
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.9, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.8, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end4:
	.size	_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind, .Lfunc_end4-_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13correlate_gpuiiPKfPfi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9normalizeiiPfi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17padding_transposeiiPKfPfi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13correlate_gpuiiPKfPfi,@object # @_Z13correlate_gpuiiPKfPfi
	.section	.rodata,"a",@progbits
	.globl	_Z13correlate_gpuiiPKfPfi
	.p2align	3, 0x0
_Z13correlate_gpuiiPKfPfi:
	.quad	_Z28__device_stub__correlate_gpuiiPKfPfi
	.size	_Z13correlate_gpuiiPKfPfi, 8

	.type	_Z9normalizeiiPfi,@object       # @_Z9normalizeiiPfi
	.globl	_Z9normalizeiiPfi
	.p2align	3, 0x0
_Z9normalizeiiPfi:
	.quad	_Z24__device_stub__normalizeiiPfi
	.size	_Z9normalizeiiPfi, 8

	.type	_Z17padding_transposeiiPKfPfi,@object # @_Z17padding_transposeiiPKfPfi
	.globl	_Z17padding_transposeiiPKfPfi
	.p2align	3, 0x0
_Z17padding_transposeiiPKfPfi:
	.quad	_Z32__device_stub__padding_transposeiiPKfPfi
	.size	_Z17padding_transposeiiPKfPfi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"hipMalloc((void**)&dGPU,ny*nx*sizeof(float))"
	.size	.L.str, 45

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"hipMalloc((void**)&padding,new_ny*nx*sizeof(float))"
	.size	.L.str.1, 52

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"hipMalloc((void**)&rGPU,ny*ny*sizeof(float))"
	.size	.L.str.2, 45

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipGetLastError()"
	.size	.L.str.3, 18

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"hipFree(dGPU)"
	.size	.L.str.4, 14

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipFree(padding)"
	.size	.L.str.5, 17

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"hipFree(rGPU)"
	.size	.L.str.6, 14

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"CUDA error: "
	.size	.L.str.7, 13

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	": "
	.size	.L.str.8, 3

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"hipMemcpy(target, source, num * sizeof(T), direction)"
	.size	.L.str.9, 54

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13correlate_gpuiiPKfPfi"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9normalizeiiPfi"
	.size	.L__unnamed_2, 18

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z17padding_transposeiiPKfPfi"
	.size	.L__unnamed_3, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__correlate_gpuiiPKfPfi
	.addrsig_sym _Z24__device_stub__normalizeiiPfi
	.addrsig_sym _Z32__device_stub__padding_transposeiiPKfPfi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13correlate_gpuiiPKfPfi
	.addrsig_sym _Z9normalizeiiPfi
	.addrsig_sym _Z17padding_transposeiiPKfPfi
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13correlate_gpuiiPKfPfi ; -- Begin function _Z13correlate_gpuiiPKfPfi
	.globl	_Z13correlate_gpuiiPKfPfi
	.p2align	8
	.type	_Z13correlate_gpuiiPKfPfi,@function
_Z13correlate_gpuiiPKfPfi:              ; @_Z13correlate_gpuiiPKfPfi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v21, 0x3ff, v0
	v_bfe_u32 v20, v0, 10, 10
	s_cmp_le_i32 s14, s15
	s_mov_b32 s8, -1
	s_cbranch_scc0 .LBB0_25
; %bb.1:
	v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
	s_mov_b32 s8, 0
.LBB0_2:                                ; %.preheader104
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_mov_b32 s9, 0
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s9, v0
	s_add_i32 s9, s9, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s9, 32
	scratch_store_b32 v2, v1, off
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v0, 32, v0
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, 8
	s_cbranch_scc0 .LBB0_2
; %bb.5:                                ; %.preheader103
	s_lshl_b32 s9, s14, 6
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s3, 0
	v_add_nc_u32_e32 v23, s9, v21
	s_mov_b32 s8, 0
	s_cbranch_scc1 .LBB0_7
; %bb.6:                                ; %.preheader103..preheader99_crit_edge
	v_add_nc_u32_e32 v0, s9, v21
	v_lshl_add_u32 v22, s15, 6, v20
	s_branch .LBB0_8
.LBB0_7:
	s_mov_b32 s8, -1
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr22
.LBB0_8:                                ; %Flow187
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_18
; %bb.9:                                ; %.preheader102.lr.ph
	s_load_b32 s8, s[0:1], 0x18
	v_lshl_add_u32 v22, s15, 6, v20
	v_mov_b32_e32 v24, v23
	s_mov_b32 s9, 0
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
                                        ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v25, v22
.LBB0_10:                               ; %.preheader102
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;       Child Loop BB0_14 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v16, v24
	v_mov_b32_e32 v18, v25
	s_mov_b64 s[0:1], 0
.LBB0_11:                               ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v17, 31, v16
	v_ashrrev_i32_e32 v19, 31, v18
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	v_lshlrev_b64 v[26:27], 2, v[16:17]
	v_add_nc_u32_e32 v16, 8, v16
	s_cmp_lg_u32 s0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, s4, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v27, vcc_lo
	global_load_b32 v17, v[26:27], off
	v_lshlrev_b64 v[26:27], 2, v[18:19]
	v_add_nc_u32_e32 v18, 8, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, s4, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v27, vcc_lo
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v0, v17
	global_load_b32 v17, v[26:27], off
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v8, v17
	s_cbranch_scc1 .LBB0_11
; %bb.12:                               ; %.preheader100.preheader
                                        ;   in Loop: Header=BB0_10 Depth=1
	v_mov_b32_e32 v16, 16
	s_mov_b32 s10, 0
.LBB0_13:                               ; %.preheader100
                                        ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_14 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s10
	v_mov_b32_e32 v18, v16
	v_movrels_b32_e32 v17, v0
	s_mov_b64 s[0:1], 0
.LBB0_14:                               ;   Parent Loop BB0_10 Depth=1
                                        ;     Parent Loop BB0_13 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	scratch_load_b32 v19, v18, off
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	v_movrels_b32_e32 v26, v8
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v19, v17, v26
	scratch_store_b32 v18, v19, off
	v_add_nc_u32_e32 v18, 4, v18
	s_cbranch_scc0 .LBB0_14
; %bb.15:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_nc_u32_e32 v16, 32, v16
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, 8
	s_cbranch_scc0 .LBB0_13
; %bb.16:                               ;   in Loop: Header=BB0_10 Depth=1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v25, s8, v25
	v_add_nc_u32_e32 v24, s8, v24
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s9, s3
	s_cbranch_scc0 .LBB0_10
; %bb.17:
	v_mov_b32_e32 v0, v23
.LBB0_18:                               ; %.preheader99
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v1, v0, s2
	v_mov_b32_e32 v2, 16
	s_lshl_b32 s1, s2, 3
	s_mov_b32 s3, 0
.LBB0_19:                               ; %.preheader98
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_20 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, s3, 3, v0
	s_mov_b32 s4, 0
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	v_mov_b32_e32 v3, v22
.LBB0_20:                               ;   Parent Loop BB0_19 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s2, v3
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=2
	v_add_nc_u32_e32 v4, s4, v2
	scratch_load_b32 v6, v4, off
	v_add_nc_u32_e32 v4, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s0, s6, v4
	v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v6, off
.LBB0_22:                               ;   in Loop: Header=BB0_20 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v3, 8, v3
	s_add_i32 s4, s4, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 32
	s_cbranch_scc0 .LBB0_20
; %bb.23:                               ;   in Loop: Header=BB0_19 Depth=1
	v_add_nc_u32_e32 v1, s1, v1
	v_add_nc_u32_e32 v2, 32, v2
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 8
	s_cbranch_scc0 .LBB0_19
; %bb.24:
	s_mov_b32 s8, 0
.LBB0_25:                               ; %Flow190
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccz .LBB0_32
; %bb.26:                               ; %.preheader97
	v_lshl_add_u32 v0, s14, 6, v21
	v_lshl_add_u32 v2, s15, 6, v20
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s2, 3
	s_mov_b32 s3, 0
	v_mul_lo_u32 v1, s2, v0
.LBB0_27:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_28 Depth 2
	v_lshl_add_u32 v4, s3, 3, v0
	s_mov_b32 s4, 8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v4
	v_mov_b32_e32 v4, v2
.LBB0_28:                               ;   Parent Loop BB0_27 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s2, v4
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_30
; %bb.29:                               ;   in Loop: Header=BB0_28 Depth=2
	v_add_nc_u32_e32 v5, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s6, v5
	v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
	global_store_b32 v[5:6], v3, off
.LBB0_30:                               ;   in Loop: Header=BB0_28 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v4, 8, v4
	s_add_i32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 0
	s_cbranch_scc0 .LBB0_28
; %bb.31:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v1, s1, v1
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 8
	s_cbranch_scc0 .LBB0_27
.LBB0_32:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13correlate_gpuiiPKfPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 272
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13correlate_gpuiiPKfPfi, .Lfunc_end0-_Z13correlate_gpuiiPKfPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 868
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 272
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9normalizeiiPfi       ; -- Begin function _Z9normalizeiiPfi
	.globl	_Z9normalizeiiPfi
	.p2align	8
	.type	_Z9normalizeiiPfi,@function
_Z9normalizeiiPfi:                      ; @_Z9normalizeiiPfi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_14
; %bb.1:                                ; %.preheader51
	s_load_b64 s[4:5], s[0:1], 0x8
	v_mul_lo_u32 v0, v1, s3
	s_cmp_gt_i32 s3, 0
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s3, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_mov_b32_e32 v4, 0
	s_mov_b32 s1, s3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v5
	s_cbranch_scc0 .LBB1_3
	s_branch .LBB1_5
.LBB1_4:
	v_mov_b32_e32 v4, 0
.LBB1_5:                                ; %._crit_edge
	v_cndmask_b32_e64 v6, 0, 1, s0
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_10
; %bb.6:                                ; %.lr.ph56
	v_cvt_f32_i32_e32 v5, s3
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v5, v5, v4
	v_div_scale_f32 v8, vcc_lo, v4, v5, v4
	v_rcp_f32_e32 v7, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v2, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v3, v7
	v_mul_f32_e32 v9, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v2, v9, v8
	v_fmac_f32_e32 v9, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v2, v9, v8
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_div_fmas_f32 v7, v8, v7, v9
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v7, v7, v5, v4
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
.LBB1_7:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[4:5], off
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v8, v8, v7
	global_store_b32 v[4:5], v8, off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_cbranch_scc0 .LBB1_7
; %bb.8:                                ; %.preheader
	v_mov_b32_e32 v4, 0
	s_mov_b32 s2, 0x3e76c4e1
	s_mov_b32 s6, s3
.LBB1_9:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[2:3], off
	s_add_i32 s6, s6, -1
	s_waitcnt vmcnt(0)
	v_frexp_mant_f32_e64 v7, |v5|
	v_frexp_exp_i32_f32_e32 v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v7
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f32 v7, v7, v9
	v_cvt_f32_i32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, 1.0, v7
	v_dual_add_f32 v10, -1.0, v7 :: v_dual_mul_f32 v13, 0x3f317218, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, -1.0, v9
	v_sub_f32_e32 v7, v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, 0x3f317218, v8, -v13
	v_fmac_f32_e32 v12, 0xb102e308, v8
	v_rcp_f32_e32 v11, v9
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v14, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v9, v14
	v_fma_f32 v9, v14, v9, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v14, v7
	v_add_f32_e32 v7, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v10, v7
	v_sub_f32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v7, v8 :: v_dual_sub_f32 v7, v10, v7
	v_sub_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v8, v7
	v_add_f32_e32 v7, v15, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v11, v7
	v_add_f32_e32 v8, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v8, v14
	v_dual_mul_f32 v10, v8, v8 :: v_dual_sub_f32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v9, v8, v8, -v10
	v_ldexp_f32 v11, v8, 1
	v_add_f32_e32 v14, v7, v7
	v_ldexp_f32 v15, v7, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v8, v14
	v_add_f32_e32 v14, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v16, s2, v14, 0x3e91f4c4
	v_fmaak_f32 v16, v14, v16, 0x3ecccdef
	v_sub_f32_e32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v17, v8, v14 :: v_dual_mul_f32 v18, v14, v16
	v_sub_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v14, v8, -v17
	v_fmac_f32_e32 v10, v14, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, v14, v16, -v18
	v_fmac_f32_e32 v10, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v9, v16
	v_add_f32_e32 v9, v18, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v9, v18
	v_dual_add_f32 v8, v17, v10 :: v_dual_sub_f32 v7, v7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v8, v17
	v_add_f32_e32 v17, 0x3f2aaaaa, v9
	v_dual_add_f32 v7, 0x31739010, v7 :: v_dual_sub_f32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, 0xbf2aaaaa, v17
	v_sub_f32_e32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v9
	v_add_f32_e32 v9, v17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v17, v9
	v_dual_mul_f32 v16, v8, v9 :: v_dual_add_f32 v7, v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, v8, v9, -v16
	v_fmac_f32_e32 v14, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v10, v9
	v_add_f32_e32 v7, v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v7, v16
	v_dual_add_f32 v8, v11, v7 :: v_dual_sub_f32 v9, v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v8, v11 :: v_dual_add_f32 v9, v15, v9
	v_dual_sub_f32 v7, v7, v10 :: v_dual_add_f32 v10, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v9, v7
	v_add_f32_e32 v11, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v10, v13 :: v_dual_sub_f32 v8, v11, v8
	v_dual_sub_f32 v9, v12, v9 :: v_dual_add_f32 v12, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v12, v10
	v_dual_sub_f32 v7, v7, v8 :: v_dual_sub_f32 v8, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v10, v8 :: v_dual_sub_f32 v11, v11, v13
	v_dual_add_f32 v13, v9, v7 :: v_dual_add_f32 v8, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v13, v9
	v_add_f32_e32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v13, v10
	v_dual_sub_f32 v7, v7, v10 :: v_dual_add_f32 v10, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v9, v11
	v_sub_f32_e32 v11, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v8, v11 :: v_dual_add_f32 v7, v7, v9
	v_add_f32_e32 v7, v7, v8
	v_cndmask_b32_e64 v8, 2.0, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v10, v7
	v_dual_sub_f32 v10, v9, v10 :: v_dual_mul_f32 v11, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v10
	v_fma_f32 v9, v8, v9, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v8, v7
	v_add_f32_e32 v7, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v7, v11, vcc_lo
	v_sub_f32_e32 v7, v7, v11
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v9, v7
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_sub_f32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, 0x3fb8aa3b, v13
	v_fma_f32 v15, 0x3fb8aa3b, v13, -v14
	v_rndne_f32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v15, 0x32a5705f, v13 :: v_dual_sub_f32 v14, v14, v16
	v_cvt_i32_f32_e32 v11, v16
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	v_trunc_f32_e32 v10, v8
	v_add_f32_e32 v14, v14, v15
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v14, v14
	v_add_f32_e32 v7, v12, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v9, v14, v11
	v_mul_f32_e32 v11, 0.5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	v_trunc_f32_e32 v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v10, v8
	v_cmp_neq_f32_e64 s0, v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v7, v9, v7, v9
	v_cmp_eq_f32_e64 s1, 0x7f800000, v9
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 1.0, v5, s0
	v_cndmask_b32_e64 v7, v7, v9, s1
	v_cmp_eq_f32_e64 s1, 0, v5
	v_cndmask_b32_e64 v9, 0, v5, s0
	v_cmp_class_f32_e64 s0, v5, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v7, 0x7fffffff, v7, v8
	v_cndmask_b32_e64 v8, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, 0x7fc00000, v7, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v5
	v_bfi_b32 v8, 0x7fffffff, v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v7, v10, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	s_cmp_eq_u32 s6, 0
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, 0x7fc00000, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_f32_e32 v4, v4, v5
	s_cbranch_scc0 .LBB1_9
	s_branch .LBB1_11
.LBB1_10:
	v_mov_b32_e32 v4, 0
.LBB1_11:                               ; %._crit_edge60
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 1, v6
	s_cbranch_vccnz .LBB1_14
; %bb.12:                               ; %.lr.ph64
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v2, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_cndmask_b32_e32 v2, v4, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v3
	v_add_nc_u32_e32 v5, 1, v3
	v_fma_f32 v6, -v4, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v3, v2
	v_cmp_ge_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v4, s0
	v_cmp_lt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v5, s0
	v_mul_f32_e32 v4, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
.LBB1_13:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v[0:1], off
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s3, 0
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v4, null, v2, v2, v3
	v_div_scale_f32 v7, vcc_lo, v3, v2, v3
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v6, v7
	v_div_fmas_f32 v4, v4, v5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v3, v4, v2, v3
	global_store_b32 v[0:1], v3, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_cbranch_scc1 .LBB1_13
.LBB1_14:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9normalizeiiPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9normalizeiiPfi, .Lfunc_end1-_Z9normalizeiiPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1824
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17padding_transposeiiPKfPfi ; -- Begin function _Z17padding_transposeiiPKfPfi
	.globl	_Z17padding_transposeiiPKfPfi
	.p2align	8
	.type	_Z17padding_transposeiiPKfPfi,@function
_Z17padding_transposeiiPKfPfi:          ; @_Z17padding_transposeiiPKfPfi
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB2_7
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s3, s[0:1], 0x18
	s_cmp_lt_i32 s15, s8
	s_mov_b32 s2, s15
	s_cselect_b32 s10, -1, 0
	s_add_u32 s0, s0, 32
	s_mul_i32 s8, s15, s9
	s_addc_u32 s1, s1, 0
	s_mov_b32 s11, 0
	s_mov_b32 s12, 0
                                        ; implicit-def: $sgpr13
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s12, v0
	s_or_b32 s13, s13, exec_lo
	s_mov_b32 s14, exec_lo
	v_cmpx_gt_i32_e64 s9, v1
	s_cbranch_execz .LBB2_6
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v2, 0
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v2, s8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
.LBB2_5:                                ;   in Loop: Header=BB2_2 Depth=1
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, v1, s3, s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v2, off
	s_load_b32 s15, s[0:1], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s15, s15, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s12, s15
	s_cmp_ge_i32 s12, s9
	s_cselect_b32 s15, -1, 0
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s15, s15, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s13, s13, s15
.LBB2_6:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s14, exec_lo, s13
	s_or_b32 s11, s14, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB2_2
.LBB2_7:                                ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17padding_transposeiiPKfPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z17padding_transposeiiPKfPfi, .Lfunc_end2-_Z17padding_transposeiiPKfPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13correlate_gpuiiPKfPfi
    .private_segment_fixed_size: 272
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13correlate_gpuiiPKfPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9normalizeiiPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9normalizeiiPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17padding_transposeiiPKfPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17padding_transposeiiPKfPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
