#include <iostream>
#include <cstdlib>
#include <math.h>

using namespace std; 

__global__
void p_vec_dist(int dim, float3 p, float3 *vec, float *res){
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int i = index; i < dim; i += stride){
        res[i] = (p.x - vec[i].x) * (p.x - vec[i].x);   
        res[i] += (p.y - vec[i].y) * (p.y - vec[i].y);
        res[i] += (p.z - vec[i].z) * (p.z - vec[i].z);
    }
}

__global__
void vec_vec_dist(int dim, float3 *vec0, float3 *vec1, float *res){
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int i = index; i < dim; i += stride){
        //p_vec_dist<<<1, dim>>>(dim, vec0[i], vec1, res[i]);
        for (int j = 0; j < dim; j++){
            res[i] = (vec0[i].x - vec1[j].x) * (vec0[i].x - vec1[j].x);
            res[i] += (vec0[i].y - vec1[j].y) * (vec0[i].y - vec1[j].y);
            res[i] += (vec0[i].z - vec1[j].z) * (vec0[i].z - vec1[j].z);   
        }
    }
}

__global__
void fill_float3(int dim, float3 val, float3 *dst)
{
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < dim; i += stride){
    dst[i].x = val.x;
    dst[i].y = val.y;
    dst[i].z = val.z;
  }
}

int main(void){
    int dim = 1 << 10;
    float3 *x, *y; 
    float *res; 

    cudaMallocManaged(&x, dim * sizeof(float3));
    cudaMallocManaged(&y, dim * sizeof(float3));
    cudaMallocManaged(&res, dim * sizeof(float));

    fill_float3<<<32, 32>>>(dim, make_float3(1.0, 2.0, 3.0), x);
    fill_float3<<<32, 32>>>(dim, make_float3(4.0, 5.0, 6.0), y);

    vec_vec_dist<<<32, 32>>>(dim, x, y, res);

    float maxError = 0.0;
    for (int i = 0; i < dim; i++)
        for (int j = 0; j < dim; j++)
            maxError = fmax(maxError, fabs(res[i] - 0.0f));
    cout << "Max error: " << maxError << endl;

    cudaFree(x);
    cudaFree(y);
    cudaFree(res);
    return 0;
}
	.file	"tmpxft_0032f57a_00000000-6_kernel_2-2.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z10p_vec_disti6float3PS_PfiR6float3PS_Pf
	.type	_Z41__device_stub__Z10p_vec_disti6float3PS_PfiR6float3PS_Pf, @function
_Z41__device_stub__Z10p_vec_disti6float3PS_PfiR6float3PS_Pf:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%rsi, 112(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10p_vec_disti6float3PS_Pf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z41__device_stub__Z10p_vec_disti6float3PS_PfiR6float3PS_Pf, .-_Z41__device_stub__Z10p_vec_disti6float3PS_PfiR6float3PS_Pf
	.globl	_Z10p_vec_disti6float3PS_Pf
	.type	_Z10p_vec_disti6float3PS_Pf, @function
_Z10p_vec_disti6float3PS_Pf:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	movq	%rsi, %rdx
	movq	%rsp, %rax
	movq	%xmm0, (%rsp)
	movq	%rax, %rsi
	movss	%xmm1, 8(%rsp)
	call	_Z41__device_stub__Z10p_vec_disti6float3PS_PfiR6float3PS_Pf
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z10p_vec_disti6float3PS_Pf, .-_Z10p_vec_disti6float3PS_Pf
	.globl	_Z44__device_stub__Z12vec_vec_distiP6float3S0_PfiP6float3S0_Pf
	.type	_Z44__device_stub__Z12vec_vec_distiP6float3S0_PfiP6float3S0_Pf, @function
_Z44__device_stub__Z12vec_vec_distiP6float3S0_PfiP6float3S0_Pf:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12vec_vec_distiP6float3S0_Pf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L9:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z44__device_stub__Z12vec_vec_distiP6float3S0_PfiP6float3S0_Pf, .-_Z44__device_stub__Z12vec_vec_distiP6float3S0_PfiP6float3S0_Pf
	.globl	_Z12vec_vec_distiP6float3S0_Pf
	.type	_Z12vec_vec_distiP6float3S0_Pf, @function
_Z12vec_vec_distiP6float3S0_Pf:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z12vec_vec_distiP6float3S0_PfiP6float3S0_Pf
	.cfi_endproc
.LFE3663:
	.size	_Z12vec_vec_distiP6float3S0_Pf, .-_Z12vec_vec_distiP6float3S0_Pf
	.globl	_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_
	.type	_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_, @function
_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movq	%rdx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 88(%rsp)
	leaq	44(%rsp), %rsi
	movq	%rax, 80(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11fill_float3i6float3PS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L14:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_, .-_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_
	.globl	_Z11fill_float3i6float3PS_
	.type	_Z11fill_float3i6float3PS_, @function
_Z11fill_float3i6float3PS_:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, %rdx
	movq	%rsp, %rsi
	movq	%xmm0, (%rsp)
	movss	%xmm1, 8(%rsp)
	call	_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z11fill_float3i6float3PS_, .-_Z11fill_float3i6float3PS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"Max error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$1, %edx
	movl	$12288, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$104, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	cudaMallocManaged@PLT
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	movl	$12288, %esi
	call	cudaMallocManaged@PLT
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	movl	$4096, %esi
	call	cudaMallocManaged@PLT
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 72(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 64(%rsp)
	movq	%rdi, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	24(%rsp), %rdx
	leaq	76(%rsp), %rsi
	movabsq	$4611686019492741120, %rax
	movl	$1024, %edi
	movq	%rax, 76(%rsp)
	movl	$0x40400000, 84(%rsp)
	call	_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_
.L21:
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdi
	movl	$1, %esi
	movl	$1, 72(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 64(%rsp)
	movq	%rdi, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	32(%rsp), %rdx
	leaq	76(%rsp), %rsi
	movabsq	$4656722015783223296, %rax
	movl	$1024, %edi
	movq	%rax, 76(%rsp)
	movl	$0x40c00000, 84(%rsp)
	call	_Z40__device_stub__Z11fill_float3i6float3PS_iR6float3PS_
.L22:
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdi
	movl	$1, %esi
	movl	$1, 84(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 76(%rsp)
	movq	%rdi, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	$1024, %edi
	movq	24(%rsp), %rsi
	call	_Z44__device_stub__Z12vec_vec_distiP6float3S0_PfiP6float3S0_Pf
.L23:
	movq	40(%rsp), %r12
	xorl	%ebx, %ebx
	xorps	%xmm1, %xmm1
.L24:
	movss	(%r12,%rbx,4), %xmm0
	andps	.LC3(%rip), %xmm0
	movl	$1024, %ebp
	movd	%xmm0, %r14d
.L25:
	movd	%r14d, %xmm0
	call	fmaxf@PLT
	movaps	%xmm0, %xmm1
	decl	%ebp
	jne	.L25
	incq	%rbx
	cmpq	$1024, %rbx
	jne	.L24
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movss	%xmm0, 12(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	12(%rsp), %xmm1
	movq	%rax, %rdi
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$104, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z11fill_float3i6float3PS_"
.LC6:
	.string	"_Z12vec_vec_distiP6float3S0_Pf"
.LC7:
	.string	"_Z10p_vec_disti6float3PS_Pf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3667:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11fill_float3i6float3PS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12vec_vec_distiP6float3S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10p_vec_disti6float3PS_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3667:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC3:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <math.h>

using namespace std; 

__global__
void p_vec_dist(int dim, float3 p, float3 *vec, float *res){
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int i = index; i < dim; i += stride){
        res[i] = (p.x - vec[i].x) * (p.x - vec[i].x);   
        res[i] += (p.y - vec[i].y) * (p.y - vec[i].y);
        res[i] += (p.z - vec[i].z) * (p.z - vec[i].z);
    }
}

__global__
void vec_vec_dist(int dim, float3 *vec0, float3 *vec1, float *res){
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int i = index; i < dim; i += stride){
        //p_vec_dist<<<1, dim>>>(dim, vec0[i], vec1, res[i]);
        for (int j = 0; j < dim; j++){
            res[i] = (vec0[i].x - vec1[j].x) * (vec0[i].x - vec1[j].x);
            res[i] += (vec0[i].y - vec1[j].y) * (vec0[i].y - vec1[j].y);
            res[i] += (vec0[i].z - vec1[j].z) * (vec0[i].z - vec1[j].z);   
        }
    }
}

__global__
void fill_float3(int dim, float3 val, float3 *dst)
{
  int index = blockIdx.x * blockDim.x + threadIdx.x;
  int stride = blockDim.x * gridDim.x;
  for (int i = index; i < dim; i += stride){
    dst[i].x = val.x;
    dst[i].y = val.y;
    dst[i].z = val.z;
  }
}

int main(void){
    int dim = 1 << 10;
    float3 *x, *y; 
    float *res; 

    hipMallocManaged(&x, dim * sizeof(float3));
    hipMallocManaged(&y, dim * sizeof(float3));
    hipMallocManaged(&res, dim * sizeof(float));

    fill_float3<<<32, 32>>>(dim, make_float3(1.0, 2.0, 3.0), x);
    fill_float3<<<32, 32>>>(dim, make_float3(4.0, 5.0, 6.0), y);

    vec_vec_dist<<<32, 32>>>(dim, x, y, res);

    float maxError = 0.0;
    for (int i = 0; i < dim; i++)
        for (int j = 0; j < dim; j++)
            maxError = fmax(maxError, fabs(res[i] - 0.0f));
    cout << "Max error: " << maxError << endl;

    hipFree(x);
    hipFree(y);
    hipFree(res);
    return 0;
}
	.text
	.file	"kernel_2-2.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf # -- Begin function _Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.type	_Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf,@function
_Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf: # @_Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	12(%rsp), %rcx
	movl	%edi, (%rcx)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	96(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rsi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf, .Lfunc_end0-_Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf # -- Begin function _Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.type	_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf,@function
_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf: # @_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf, .Lfunc_end1-_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_ # -- Begin function _Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.type	_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_,@function
_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_: # @_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	64(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	4(%rsp), %rcx
	movl	%edi, (%rcx)
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_, .Lfunc_end2-_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x3f800000                      # float 1
	.long	0x40000000                      # float 2
	.zero	4
	.zero	4
.LCPI3_2:
	.long	0x40800000                      # float 4
	.long	0x40a00000                      # float 5
	.zero	4
	.zero	4
.LCPI3_4:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI3_1:
	.long	0x40400000                      # float 3
.LCPI3_3:
	.long	0x40c00000                      # float 6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -16
	movabsq	$4294967328, %rbx               # imm = 0x100000020
	leaq	24(%rsp), %rdi
	movl	$12288, %esi                    # imm = 0x3000
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %rdi
	movl	$12288, %esi                    # imm = 0x3000
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	24(%rsp), %rsi
	movaps	.LCPI3_0(%rip), %xmm0           # xmm0 = <1.0E+0,2.0E+0,u,u>
	movss	.LCPI3_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movl	$1024, %edi                     # imm = 0x400
	callq	_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_
.LBB3_2:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	16(%rsp), %rsi
	movaps	.LCPI3_2(%rip), %xmm0           # xmm0 = <4.0E+0,5.0E+0,u,u>
	movss	.LCPI3_3(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movl	$1024, %edi                     # imm = 0x400
	callq	_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_
.LBB3_4:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	$1024, %edi                     # imm = 0x400
	callq	_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
.LBB3_6:
	xorps	%xmm4, %xmm4
	movq	8(%rsp), %rax
	xorl	%ecx, %ecx
	movaps	.LCPI3_4(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
.LBB3_7:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_8 Depth 2
	movss	(%rax,%rcx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	andps	%xmm0, %xmm1
	movl	$1024, %edx                     # imm = 0x400
.LBB3_8:                                #   Parent Loop BB3_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movaps	%xmm1, %xmm2
	maxss	%xmm4, %xmm2
	cmpunordss	%xmm4, %xmm4
	movaps	%xmm4, %xmm3
	andps	%xmm1, %xmm3
	andnps	%xmm2, %xmm4
	orps	%xmm3, %xmm4
	decl	%edx
	jne	.LBB3_8
# %bb.9:                                #   in Loop: Header=BB3_7 Depth=1
	incq	%rcx
	cmpq	$1024, %rcx                     # imm = 0x400
	jne	.LBB3_7
# %bb.10:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$11, %edx
	movaps	%xmm4, 32(%rsp)                 # 16-byte Spill
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp), %xmm0                 # 16-byte Folded Reload
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf,@object # @_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.p2align	3, 0x0
_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf:
	.quad	_Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.size	_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf, 8

	.type	_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf,@object # @_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.globl	_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.p2align	3, 0x0
_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf:
	.quad	_Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.size	_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf, 8

	.type	_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_,@object # @_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.globl	_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.p2align	3, 0x0
_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_:
	.quad	_Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.size	_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Max error: "
	.size	.L.str, 12

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf"
	.size	.L__unnamed_1, 46

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf"
	.size	.L__unnamed_2, 48

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_"
	.size	.L__unnamed_3, 45

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.addrsig_sym _Z27__device_stub__vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.addrsig_sym _Z26__device_stub__fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.addrsig_sym _Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.addrsig_sym _Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf ; -- Begin function _Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.globl	_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
	.p2align	8
	.type	_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf,@function
_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf: ; @_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[12:15], s[0:1], 0x10
	s_load_b32 s0, s[2:3], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[3:4], null, v1, 12, s[12:13]
	s_mul_i32 s2, s0, s8
	s_ashr_i32 s3, s2, 31
	s_mul_hi_i32 s1, s2, 12
	s_mul_i32 s10, s2, 12
	s_lshl_b64 s[8:9], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v6, vcc_lo
	s_mov_b32 s3, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v0, v[2:3], off offset:-4
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, s5, v0
	v_mul_f32_e32 v0, v0, v0
	global_store_b32 v[4:5], v0, off
	global_load_b32 v6, v[2:3], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v6, s6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v6, v6
	global_store_b32 v[4:5], v0, off
	global_load_b32 v6, v[2:3], off offset:4
	v_add_co_u32 v2, s0, v2, s10
	v_add_co_ci_u32_e64 v3, s0, s1, v3, s0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v6, s7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v6, v6
	global_store_b32 v[4:5], v0, off
	v_add_co_u32 v4, s0, v4, s8
	v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow45
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf, .Lfunc_end0-_Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf ; -- Begin function _Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.globl	_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
	.p2align	8
	.type	_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf,@function
_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf: ; @_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s8, s[0:1], 0x0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB1_6
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x18
	s_cmp_gt_i32 s8, 0
	v_mov_b32_e32 v0, 0
	s_cselect_b32 s10, -1, 0
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s2, s11
	s_add_u32 s2, s6, 4
	s_addc_u32 s3, s7, 0
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB1_5
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b64 s[6:7], s[2:3]
	s_mov_b32 s12, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v6, v[2:3], off
	global_load_b32 v7, v0, s[6:7] offset:-4
	s_add_i32 s12, s12, -1
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v6, v6, v6
	global_store_b32 v[4:5], v6, off
	global_load_b32 v7, v[2:3], off offset:4
	global_load_b32 v8, v0, s[6:7]
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v7
	global_store_b32 v[4:5], v6, off
	global_load_b32 v7, v[2:3], off offset:8
	global_load_b32 v8, v0, s[6:7] offset:4
	s_add_u32 s6, s6, 12
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s12, 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v7
	global_store_b32 v[4:5], v6, off
	s_cbranch_scc0 .LBB1_4
.LBB1_5:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v1, s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	s_or_b32 s9, vcc_lo, s9
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_2
.LBB1_6:                                ; %._crit_edge44
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf, .Lfunc_end1-_Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_ ; -- Begin function _Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.globl	_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
	.p2align	8
	.type	_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_,@function
_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_: ; @_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s8, v[0:1]
	v_cmpx_gt_i32_e64 s4, v3
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x10
	s_load_b32 s2, s[2:3], 0x0
	v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, s6
	v_mov_b32_e32 v2, s7
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[4:5], null, v3, 12, s[0:1]
	s_mul_i32 s1, s2, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_mul_hi_i32 s2, s1, 12
	s_mul_i32 s3, s1, 12
	v_add_co_u32 v4, vcc_lo, v4, 4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s1, v3
	global_store_b96 v[4:5], v[0:2], off offset:-4
	v_add_co_u32 v4, s0, v4, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v5, s0, s2, v5, s0
	v_cmp_le_i32_e32 vcc_lo, s4, v3
	s_or_b32 s5, vcc_lo, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_2
.LBB2_3:                                ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_, .Lfunc_end2-_Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           12
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10p_vec_disti15HIP_vector_typeIfLj3EEPS0_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12vec_vec_distiP15HIP_vector_typeIfLj3EES1_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           12
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11fill_float3i15HIP_vector_typeIfLj3EEPS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
