#include "includes.h"
#define max(a, b) ((a > b)?a:b)

#define THREADSPERDIM   16

#define FALSE 0
#define TRUE !FALSE

// mX has order rows x cols
// vectY has length rows

// mX has order rows x cols
// vectY has length rows

__global__ void ftest(int diagFlag, int p, int rows, int colsx, int colsy, int rCols, int unrCols, float * obs, int obsDim, float * rCoeffs, int rCoeffsDim, float * unrCoeffs, int unrCoeffsDim, float * rdata, int rdataDim, float * unrdata, int unrdataDim, float * dfStats) // float * dpValues)
{
int
j = blockIdx.x * THREADSPERDIM + threadIdx.x,
i = blockIdx.y * THREADSPERDIM + threadIdx.y,
idx = i*colsx + j, k, m;
float
kobs, fp = (float) p, frows = (float) rows,
rSsq, unrSsq,
rEst, unrEst,
score = 0.f,
* tObs, * tRCoeffs, * tUnrCoeffs,
* tRdata, * tUnrdata;

if((i >= colsy) || (j >= colsx)) return;
if((!diagFlag) && (i == j)) {
dfStats[idx] = 0.f;
// dpValues[idx] = 0.f;
return;
}

tObs = obs + (i*colsx+j)*obsDim;

tRCoeffs = rCoeffs + i*rCoeffsDim;
tRdata = rdata + i*rdataDim;

tUnrCoeffs = unrCoeffs + (i*colsx+j)*unrCoeffsDim;
tUnrdata = unrdata + (i*colsx+j)*unrdataDim;

rSsq = unrSsq = 0.f;
for(k = 0; k < rows; k++) {
unrEst = rEst = 0.f;
kobs = tObs[k];
for(m = 0; m < rCols; m++)
rEst += tRCoeffs[m] * tRdata[k+m*rows];
for(m = 0; m < unrCols; m++)
unrEst += tUnrCoeffs[m] * tUnrdata[k+m*rows];
rSsq   += (kobs - rEst) * (kobs - rEst);
unrSsq += (kobs - unrEst) * (kobs - unrEst);

}
score = ((rSsq - unrSsq)*(frows-2.f*fp-1.f)) / (fp*unrSsq);

if(!isfinite(score))
score = 0.f;

dfStats[idx] = score;
}
	.file	"tmpxft_002cd5b5_00000000-6_ftest.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_iiiiiiiPfiS_iS_iS_iS_iS_
	.type	_Z46__device_stub__Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_iiiiiiiPfiS_iS_iS_iS_iS_, @function
_Z46__device_stub__Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_iiiiiiiPfiS_iS_iS_iS_iS_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movq	328(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	344(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	360(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	376(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 24(%rsp)
	movq	392(%rsp), %rax
	movl	%r9d, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	408(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 328
	leaq	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 336
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L2:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z46__device_stub__Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_iiiiiiiPfiS_iS_iS_iS_iS_, .-_Z46__device_stub__Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_iiiiiiiPfiS_iS_iS_iS_iS_
	.globl	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.type	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_, @function
_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_iiiiiiiPfiS_iS_iS_iS_iS_
	.cfi_endproc
.LFE2033:
	.size	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_, .-_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
#define max(a, b) ((a > b)?a:b)

#define THREADSPERDIM   16

#define FALSE 0
#define TRUE !FALSE

// mX has order rows x cols
// vectY has length rows

// mX has order rows x cols
// vectY has length rows

__global__ void ftest(int diagFlag, int p, int rows, int colsx, int colsy, int rCols, int unrCols, float * obs, int obsDim, float * rCoeffs, int rCoeffsDim, float * unrCoeffs, int unrCoeffsDim, float * rdata, int rdataDim, float * unrdata, int unrdataDim, float * dfStats) // float * dpValues)
{
int
j = blockIdx.x * THREADSPERDIM + threadIdx.x,
i = blockIdx.y * THREADSPERDIM + threadIdx.y,
idx = i*colsx + j, k, m;
float
kobs, fp = (float) p, frows = (float) rows,
rSsq, unrSsq,
rEst, unrEst,
score = 0.f,
* tObs, * tRCoeffs, * tUnrCoeffs,
* tRdata, * tUnrdata;

if((i >= colsy) || (j >= colsx)) return;
if((!diagFlag) && (i == j)) {
dfStats[idx] = 0.f;
// dpValues[idx] = 0.f;
return;
}

tObs = obs + (i*colsx+j)*obsDim;

tRCoeffs = rCoeffs + i*rCoeffsDim;
tRdata = rdata + i*rdataDim;

tUnrCoeffs = unrCoeffs + (i*colsx+j)*unrCoeffsDim;
tUnrdata = unrdata + (i*colsx+j)*unrdataDim;

rSsq = unrSsq = 0.f;
for(k = 0; k < rows; k++) {
unrEst = rEst = 0.f;
kobs = tObs[k];
for(m = 0; m < rCols; m++)
rEst += tRCoeffs[m] * tRdata[k+m*rows];
for(m = 0; m < unrCols; m++)
unrEst += tUnrCoeffs[m] * tUnrdata[k+m*rows];
rSsq   += (kobs - rEst) * (kobs - rEst);
unrSsq += (kobs - unrEst) * (kobs - unrEst);

}
score = ((rSsq - unrSsq)*(frows-2.f*fp-1.f)) / (fp*unrSsq);

if(!isfinite(score))
score = 0.f;

dfStats[idx] = score;
}
	.text
	.file	"ftest.hip"
	.globl	_Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_ # -- Begin function _Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.type	_Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_,@function
_Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_: # @_Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_, .Lfunc_end0-_Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_,@object # @_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.section	.rodata,"a",@progbits
	.globl	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.p2align	3, 0x0
_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_:
	.quad	_Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.size	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_ ; -- Begin function _Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.globl	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
	.p2align	8
	.type	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_,@function
_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_:       ; @_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v3, s15, 4, v1
	v_lshl_add_u32 v2, s14, 4, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s8, v3
	v_cmp_gt_i32_e64 s2, s7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_13
; %bb.1:
	v_mad_u64_u32 v[0:1], null, v3, s7, v[2:3]
	v_cmp_ne_u32_e32 vcc_lo, v3, v2
	s_cmp_lg_u32 s4, 0
	v_mov_b32_e32 v2, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_12
; %bb.2:
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v10, 0
	s_cmp_lt_i32 s6, 1
	s_mov_b32 s3, 0
	s_cbranch_scc1 .LBB0_11
; %bb.3:                                ; %.lr.ph107
	s_clause 0x7
	s_load_b32 s2, s[0:1], 0x28
	s_load_b32 s7, s[0:1], 0x38
	s_load_b32 s8, s[0:1], 0x58
	s_load_b32 s11, s[0:1], 0x48
	s_load_b32 s18, s[0:1], 0x68
	s_load_b64 s[12:13], s[0:1], 0x20
	s_load_b64 s[14:15], s[0:1], 0x30
	s_load_b64 s[16:17], s[0:1], 0x50
	s_cmp_gt_i32 s9, 0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, v0, s2
	v_mul_lo_u32 v4, v3, s7
	v_mul_lo_u32 v6, v3, s8
	v_mul_lo_u32 v8, v0, s11
	v_mul_lo_u32 v10, v0, s18
	s_clause 0x1
	s_load_b64 s[18:19], s[0:1], 0x40
	s_load_b64 s[20:21], s[0:1], 0x60
	s_cselect_b32 s7, -1, 0
	s_cmp_gt_i32 s10, 0
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	v_lshlrev_b64 v[13:14], 2, v[8:9]
	v_lshlrev_b64 v[15:16], 2, v[10:11]
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v10, 0
	v_add_co_u32 v8, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s15, v4, vcc_lo
	v_add_co_u32 v11, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s18, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v14, vcc_lo
	v_add_co_u32 v13, vcc_lo, s20, v15
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v16, vcc_lo
	s_cselect_b32 s8, -1, 0
	s_mov_b32 s12, s3
.LBB0_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;     Child Loop BB0_9 Depth 2
	s_mov_b32 s13, s3
	v_mov_b32_e32 v16, 0
	s_lshl_b64 s[14:15], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v5, vcc_lo, v8, s14
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v9, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s7
	global_load_b32 v15, v[5:6], off
	s_cbranch_vccnz .LBB0_7
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	s_mov_b32 s2, s12
	s_mov_b32 s11, s9
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b64 s[14:15], s[2:3], 2
	s_add_i32 s11, s11, -1
	v_add_co_u32 v17, vcc_lo, v11, s14
	v_add_co_ci_u32_e32 v18, vcc_lo, s15, v12, vcc_lo
	s_add_i32 s2, s2, s6
	s_cmp_eq_u32 s11, 0
	global_load_b32 v19, v[5:6], off
	global_load_b32 v17, v[17:18], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v16, v19, v17
	s_cbranch_scc0 .LBB0_6
.LBB0_7:                                ; %.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v17, 0
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB0_10
; %bb.8:                                ; %.lr.ph101.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_mov_b32 s2, s12
	s_mov_b32 s11, s10
.LBB0_9:                                ; %.lr.ph101
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b64 s[14:15], s[2:3], 2
	s_add_i32 s11, s11, -1
	v_add_co_u32 v18, vcc_lo, v13, s14
	v_add_co_ci_u32_e32 v19, vcc_lo, s15, v14, vcc_lo
	s_add_i32 s2, s2, s6
	s_cmp_lg_u32 s11, 0
	global_load_b32 v20, v[5:6], off
	global_load_b32 v18, v[18:19], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v17, v20, v18
	s_cbranch_scc1 .LBB0_9
.LBB0_10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_sub_f32_e32 v6, v15, v17
	v_sub_f32_e32 v5, v15, v16
	s_add_i32 s12, s12, 1
	s_cmp_lg_u32 s12, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmac_f32 v10, v6, v6 :: v_dual_fmac_f32 v7, v5, v5
	s_cbranch_scc1 .LBB0_4
.LBB0_11:                               ; %._crit_edge108
	v_cvt_f32_i32_e32 v1, s5
	v_cvt_f32_i32_e32 v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v3, v7, v10 :: v_dual_fmac_f32 v2, -2.0, v1
	v_dual_mul_f32 v1, v10, v1 :: v_dual_add_f32 v2, -1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v2, v3
	v_div_scale_f32 v3, null, v1, v1, v2
	v_div_scale_f32 v6, vcc_lo, v2, v1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v4
	v_fma_f32 v7, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v4
	v_fma_f32 v3, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v5
	v_div_fixup_f32 v1, v3, v1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_class_f32_e64 vcc_lo, v1, 0x1f8
	v_cndmask_b32_e32 v2, 0, v1, vcc_lo
.LBB0_12:                               ; %Flow188
	s_or_b32 exec_lo, exec_lo, s4
	s_load_b64 s[0:1], s[0:1], 0x70
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 120
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_, .Lfunc_end0-_Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 24
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 120
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z5ftestiiiiiiiPfiS_iS_iS_iS_iS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
