#include "cuda.h"

/**
 * ref_dev        B,N,D
 * query_dev      B,M,D
 * ind_dev        B,N,K
 * out_feat_dev   B,N,K,D
 */
__global__ void gather_nn_kernel(
    float* out_feat_dev, float* ref_dev, float* query_dev, long* ind_dev,
    int64_t B, int64_t N, int64_t k, int64_t Dim, int64_t M
) {
  unsigned int index = threadIdx.x + blockIdx.x * blockDim.x;
  if (index >= B*N)
    return;
  unsigned int iB = index / N;
  unsigned int iN = index % N;

  long *ind_ptr = ind_dev + iB * N * k + iN * k;
  float *ref_ptr = ref_dev + iB * N * Dim;
  float *query_ptr = query_dev + iB * M * Dim;
  float *out_feat_ptr = out_feat_dev + iB * N * k * Dim + iN * k * Dim;
  for (int64_t i = 0; i < k; i++) {
    auto ind = *(ind_ptr + i);
    auto ref = ref_ptr + iN * Dim;
    auto query = query_ptr + ind * Dim;
    auto out_feat = out_feat_ptr + i * Dim;
    for (int64_t j = 0;  j < Dim; j++)
      out_feat[j] = query[j] - ref[j];
  }
  __syncthreads();
}

void gather_nn_dev(
  float* ref_dev, float* query_dev, long* ind_dev,
  int64_t B, int64_t N, int64_t k, int64_t Dim, int64_t M,
  float* out_feat_dev
) {
  int64_t all = B * N;
  dim3 blockSize;
  if (all <= 32)
    blockSize.x = 32;
  else if (all <= 64)
    blockSize.x = 64;
  else if (all <= 512)
    blockSize.x = 128;
  else if (all <= 1024)
    blockSize.x = 256;
  else
    blockSize.x = 512;
  dim3 gridSize((all + blockSize.x - 1) / blockSize.x);

  gather_nn_kernel<<<gridSize, blockSize>>>(
    out_feat_dev, ref_dev, query_dev, ind_dev,
    B, N, k, Dim, M
  );
  cudaDeviceSynchronize();
}

	.file	"tmpxft_002d8ffb_00000000-6_gather_nn_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z16gather_nn_kernelPfS_S_PllllllPfS_S_Pllllll
	.type	_Z47__device_stub__Z16gather_nn_kernelPfS_S_PllllllPfS_S_Pllllll, @function
_Z47__device_stub__Z16gather_nn_kernelPfS_S_PllllllPfS_S_Pllllll:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z16gather_nn_kernelPfS_S_Pllllll(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z47__device_stub__Z16gather_nn_kernelPfS_S_PllllllPfS_S_Pllllll, .-_Z47__device_stub__Z16gather_nn_kernelPfS_S_PllllllPfS_S_Pllllll
	.globl	_Z16gather_nn_kernelPfS_S_Pllllll
	.type	_Z16gather_nn_kernelPfS_S_Pllllll, @function
_Z16gather_nn_kernelPfS_S_Pllllll:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z16gather_nn_kernelPfS_S_PllllllPfS_S_Pllllll
	.cfi_endproc
.LFE2034:
	.size	_Z16gather_nn_kernelPfS_S_Pllllll, .-_Z16gather_nn_kernelPfS_S_Pllllll
	.globl	_Z13gather_nn_devPfS_PllllllS_
	.type	_Z13gather_nn_devPfS_PllllllS_, @function
_Z13gather_nn_devPfS_PllllllS_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r8, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rcx, %rbx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	144(%rsp), %rax
	movq	%rdi, 8(%rsp)
	movabsq	$4294967297, %rdi
	movq	%rsi, 16(%rsp)
	movq	128(%rsp), %r12
	movq	%rax, 24(%rsp)
	movq	%rcx, %rax
	movq	136(%rsp), %r13
	movl	$32, %ecx
	imulq	%r8, %rax
	movq	%rdi, 44(%rsp)
	cmpq	$32, %rax
	jle	.L9
	movl	$64, %ecx
	cmpq	$64, %rax
	jle	.L9
	movl	$128, %ecx
	cmpq	$512, %rax
	jle	.L9
	cmpq	$1024, %rax
	movl	$512, %ecx
	movl	$256, %edx
	cmovle	%edx, %ecx
.L9:
	movl	%ecx, %esi
	movl	%ecx, 40(%rsp)
	movl	48(%rsp), %ecx
	xorl	%r9d, %r9d
	leaq	-1(%rsi,%rax), %rax
	xorl	%r8d, %r8d
	cqto
	idivq	%rsi
	movq	40(%rsp), %rdx
	movl	%eax, 52(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	%rax
	.cfi_def_cfa_offset 136
	movq	%rbp, %r9
	movq	%rbx, %r8
	movq	%r14, %rcx
	pushq	%r13
	.cfi_def_cfa_offset 144
	pushq	%r12
	.cfi_def_cfa_offset 152
	pushq	%r15
	.cfi_def_cfa_offset 160
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z47__device_stub__Z16gather_nn_kernelPfS_S_PllllllPfS_S_Pllllll
	addq	$32, %rsp
	.cfi_def_cfa_offset 128
.L10:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaDeviceSynchronize@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z13gather_nn_devPfS_PllllllS_, .-_Z13gather_nn_devPfS_PllllllS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16gather_nn_kernelPfS_S_Pllllll"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16gather_nn_kernelPfS_S_Pllllll(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

/**
 * ref_dev        B,N,D
 * query_dev      B,M,D
 * ind_dev        B,N,K
 * out_feat_dev   B,N,K,D
 */
__global__ void gather_nn_kernel(
    float* out_feat_dev, float* ref_dev, float* query_dev, long* ind_dev,
    int64_t B, int64_t N, int64_t k, int64_t Dim, int64_t M
) {
  unsigned int index = threadIdx.x + blockIdx.x * blockDim.x;
  if (index >= B*N)
    return;
  unsigned int iB = index / N;
  unsigned int iN = index % N;

  long *ind_ptr = ind_dev + iB * N * k + iN * k;
  float *ref_ptr = ref_dev + iB * N * Dim;
  float *query_ptr = query_dev + iB * M * Dim;
  float *out_feat_ptr = out_feat_dev + iB * N * k * Dim + iN * k * Dim;
  for (int64_t i = 0; i < k; i++) {
    auto ind = *(ind_ptr + i);
    auto ref = ref_ptr + iN * Dim;
    auto query = query_ptr + ind * Dim;
    auto out_feat = out_feat_ptr + i * Dim;
    for (int64_t j = 0;  j < Dim; j++)
      out_feat[j] = query[j] - ref[j];
  }
  __syncthreads();
}

void gather_nn_dev(
  float* ref_dev, float* query_dev, long* ind_dev,
  int64_t B, int64_t N, int64_t k, int64_t Dim, int64_t M,
  float* out_feat_dev
) {
  int64_t all = B * N;
  dim3 blockSize;
  if (all <= 32)
    blockSize.x = 32;
  else if (all <= 64)
    blockSize.x = 64;
  else if (all <= 512)
    blockSize.x = 128;
  else if (all <= 1024)
    blockSize.x = 256;
  else
    blockSize.x = 512;
  dim3 gridSize((all + blockSize.x - 1) / blockSize.x);

  gather_nn_kernel<<<gridSize, blockSize>>>(
    out_feat_dev, ref_dev, query_dev, ind_dev,
    B, N, k, Dim, M
  );
  hipDeviceSynchronize();
}

	.text
	.file	"gather_nn_kernel.hip"
	.globl	_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll # -- Begin function _Z31__device_stub__gather_nn_kernelPfS_S_Pllllll
	.type	_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll,@function
_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll: # @_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16gather_nn_kernelPfS_S_Pllllll, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll, .Lfunc_end0-_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll
	.cfi_endproc
                                        # -- End function
	.globl	_Z13gather_nn_devPfS_PllllllS_  # -- Begin function _Z13gather_nn_devPfS_PllllllS_
	.type	_Z13gather_nn_devPfS_PllllllS_,@function
_Z13gather_nn_devPfS_PllllllS_:         # @_Z13gather_nn_devPfS_PllllllS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, 8(%rsp)                   # 8-byte Spill
	movq	%rsi, (%rsp)                    # 8-byte Spill
	movq	%rdi, %rbp
	movabsq	$4294967296, %rsi               # imm = 0x100000000
	movq	%r8, %rax
	imulq	%rcx, %rax
	cmpq	$33, %rax
	jge	.LBB1_2
# %bb.1:
	leaq	32(%rsi), %rcx
	jmp	.LBB1_7
.LBB1_2:
	cmpq	$65, %rax
	jae	.LBB1_4
# %bb.3:
	leaq	64(%rsi), %rcx
	jmp	.LBB1_7
.LBB1_4:
	cmpq	$513, %rax                      # imm = 0x201
	jae	.LBB1_6
# %bb.5:
	leaq	128(%rsi), %rcx
	jmp	.LBB1_7
.LBB1_6:
	xorl	%ecx, %ecx
	cmpq	$1025, %rax                     # imm = 0x401
	setae	%cl
	shll	$8, %ecx
	addq	%rsi, %rcx
	addq	$256, %rcx                      # imm = 0x100
.LBB1_7:
	movq	96(%rsp), %rbx
	movq	88(%rsp), %r13
	movq	80(%rsp), %r12
	movl	%ecx, %edi
	andl	$992, %edi                      # imm = 0x3E0
	addq	%rdi, %rax
	decq	%rax
	cqto
	idivq	%rdi
	movl	%eax, %edi
	orq	%rsi, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.8:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movq	%r15, %r8
	movq	%r14, %r9
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_9:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end1:
	.size	_Z13gather_nn_devPfS_PllllllS_, .Lfunc_end1-_Z13gather_nn_devPfS_PllllllS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16gather_nn_kernelPfS_S_Pllllll, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16gather_nn_kernelPfS_S_Pllllll,@object # @_Z16gather_nn_kernelPfS_S_Pllllll
	.section	.rodata,"a",@progbits
	.globl	_Z16gather_nn_kernelPfS_S_Pllllll
	.p2align	3, 0x0
_Z16gather_nn_kernelPfS_S_Pllllll:
	.quad	_Z31__device_stub__gather_nn_kernelPfS_S_Pllllll
	.size	_Z16gather_nn_kernelPfS_S_Pllllll, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16gather_nn_kernelPfS_S_Pllllll"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__gather_nn_kernelPfS_S_Pllllll
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16gather_nn_kernelPfS_S_Pllllll
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16gather_nn_kernelPfS_S_Pllllll ; -- Begin function _Z16gather_nn_kernelPfS_S_Pllllll
	.globl	_Z16gather_nn_kernelPfS_S_Pllllll
	.p2align	8
	.type	_Z16gather_nn_kernelPfS_S_Pllllll,@function
_Z16gather_nn_kernelPfS_S_Pllllll:      ; @_Z16gather_nn_kernelPfS_S_Pllllll
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b512 s[16:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s3, s26, s25
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_hi_u32 s2, s26, s24
	v_mov_b32_e32 v2, 0
	s_add_i32 s2, s2, s3
	s_mul_i32 s3, s27, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s3, s2, s3
	s_mul_i32 s2, s26, s24
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.1:
	v_cmp_lt_i64_e64 s2, s[28:29], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_7
; %bb.2:                                ; %.lr.ph60
	s_ashr_i32 s4, s27, 31
	s_load_b64 s[0:1], s[0:1], 0x40
	s_add_u32 s2, s26, s4
	s_mov_b32 s5, s4
	s_addc_u32 s3, s27, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b64 s[6:7], s[2:3], s[4:5]
	v_cvt_f32_u32_e32 v0, s6
	v_cvt_f32_u32_e32 v2, s7
	s_sub_u32 s2, 0, s6
	s_subb_u32 s3, 0, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v2, 0x4f800000, v0
	v_rcp_f32_e32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s1, s30
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v0
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v2, 0xcf800000, v0
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, s2, v2
	v_mul_hi_u32 v4, s2, v0
	v_mul_lo_u32 v5, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_mul_lo_u32 v4, s2, v0
	v_add_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, v4
	v_mul_lo_u32 v6, v0, v3
	v_mul_hi_u32 v7, v0, v3
	v_mul_hi_u32 v8, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_mul_hi_u32 v9, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_ashrrev_i32_e64 v8, 31, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s2, v0
	v_mul_lo_u32 v5, s3, v0
	v_mul_lo_u32 v4, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s2, v0
	v_add_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, v4
	v_mul_lo_u32 v6, v0, v3
	v_mul_hi_u32 v7, v0, v3
	v_mul_hi_u32 v9, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_mul_hi_u32 v10, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v9, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v6, vcc_lo, v1, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v6, v8
	v_add_co_u32 v0, vcc_lo, v0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, v2, v4, vcc_lo
	v_xor_b32_e32 v11, v7, v8
	v_mul_hi_u32 v12, v9, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, v9, v10, 0
	v_mad_u64_u32 v[4:5], null, v11, v0, 0
	v_mad_u64_u32 v[6:7], null, v11, v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v12, v2
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v0, vcc_lo, v2, v5, vcc_lo
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v5, s7, v0
	v_mad_u64_u32 v[2:3], null, s6, v0, 0
	v_mul_lo_u32 v6, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v2, vcc_lo, v9, v2
	v_add3_u32 v3, v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v11, v3
	v_subrev_co_ci_u32_e64 v5, s2, s7, v5, vcc_lo
	v_add_co_u32 v6, s2, v0, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s2, 0, v4, s2
	v_sub_co_u32 v9, s2, v2, s6
	v_sub_co_ci_u32_e32 v3, vcc_lo, v11, v3, vcc_lo
	v_subrev_co_ci_u32_e64 v5, s2, 0, v5, s2
	v_cmp_le_u32_e32 vcc_lo, s6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e64 s2, s7, v3
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s7, v5
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s6, v2
	v_cmp_gt_i64_e64 s6, s[30:31], 0
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s7, v3
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v11, v2, s2
	v_cndmask_b32_e32 v5, v10, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	s_mul_i32 s2, s0, s30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v9, v6, vcc_lo
	v_cndmask_b32_e32 v3, v10, v7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_xor_b32_e32 v2, s4, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_cndmask_b32_e32 v3, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v2
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v11, vcc_lo, v0, v2
	v_sub_co_ci_u32_e32 v14, vcc_lo, v3, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, v11, s26, 0
	v_mad_u64_u32 v[4:5], null, s2, v11, 0
	s_mul_i32 s2, s0, s31
	s_mul_hi_u32 s0, s0, s30
	s_add_i32 s0, s0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, v3
	s_add_i32 s0, s0, s1
	v_mov_b32_e32 v3, v5
	v_mul_lo_u32 v15, v2, s31
	v_mad_u64_u32 v[12:13], null, v2, s30, 0
	v_mad_u64_u32 v[8:9], null, v11, s27, v[0:1]
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[9:10], null, s0, v11, v[3:4]
	v_mad_u64_u32 v[6:7], null, v2, s28, 0
	v_mul_lo_u32 v0, v2, s29
	v_sub_co_u32 v17, vcc_lo, v1, v2
	v_mul_lo_u32 v16, v8, s30
	v_mad_u64_u32 v[10:11], null, v14, s26, v[8:9]
	v_mov_b32_e32 v5, v9
	v_mul_lo_u32 v11, v8, s28
	v_mul_lo_u32 v14, v6, s31
	v_mad_u64_u32 v[8:9], null, v6, s30, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_mov_b32_e32 v5, v10
	v_add3_u32 v13, v13, v15, v16
	v_mul_lo_u32 v16, v17, s29
	v_add3_u32 v7, v7, v0, v11
	s_lshl_b64 s[2:3], s[30:31], 2
	v_sub_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v10, s0, s20, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s0, s21, v4, s0
	v_mad_u64_u32 v[2:3], null, v17, s28, 0
	v_lshlrev_b64 v[4:5], 2, v[12:13]
	v_mul_lo_u32 v13, v15, s28
	v_lshlrev_b64 v[0:1], 3, v[6:7]
	v_mul_lo_u32 v18, v7, s30
	v_mul_lo_u32 v12, v17, s31
	v_mad_u64_u32 v[6:7], null, v17, s30, 0
	v_mul_lo_u32 v15, v15, s30
	v_add_co_u32 v17, vcc_lo, s22, v0
	v_add3_u32 v3, v3, v16, v13
	v_add_co_ci_u32_e32 v19, vcc_lo, s23, v1, vcc_lo
	v_add3_u32 v9, v9, v14, v18
	v_mul_lo_u32 v13, v2, s31
	v_mad_u64_u32 v[0:1], null, v2, s30, 0
	v_mul_lo_u32 v14, v3, s30
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add3_u32 v7, v7, v12, v15
	v_add_co_u32 v15, vcc_lo, s18, v4
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_ci_u32_e32 v16, vcc_lo, s19, v5, vcc_lo
	v_add3_u32 v1, v1, v13, v14
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v12, vcc_lo, v17, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, v19, v3, vcc_lo
	s_mov_b64 s[0:1], 0
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v15, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, v16, v5, vcc_lo
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_6
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_lshl_b64 s[4:5], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v12, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v13, vcc_lo
	s_mov_b64 s[4:5], s[30:31]
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v7, v5, s30
	v_mul_lo_u32 v8, v4, s31
	v_mad_u64_u32 v[5:6], null, v4, s30, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v6, v6, v8, v7
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v10, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo
.LBB0_5:                                ; %.lr.ph
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v14, v[6:7], off
	global_load_b32 v15, v[4:5], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_add_u32 s4, s4, -1
	s_addc_u32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[4:5], 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v14, v14, v15
	global_store_b32 v[8:9], v14, off
	v_add_co_u32 v8, vcc_lo, v8, 4
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_cbranch_scc0 .LBB0_5
.LBB0_6:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_co_u32 v0, vcc_lo, v0, s2
	s_add_u32 s0, s0, 1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[0:1], s[28:29]
	s_cbranch_scc0 .LBB0_3
.LBB0_7:                                ; %._crit_edge61
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_8:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16gather_nn_kernelPfS_S_Pllllll
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16gather_nn_kernelPfS_S_Pllllll, .Lfunc_end0-_Z16gather_nn_kernelPfS_S_Pllllll
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1684
; NumSgprs: 34
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16gather_nn_kernelPfS_S_Pllllll
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z16gather_nn_kernelPfS_S_Pllllll.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
