#include <functional>

#include "auxiliares.cu"

using namespace std;

// Punteros a memoria global
double *g_datos;
double *g_resp;

double *g_verosimilitud;
double *g_verosimilitudParcial;
double *g_sumaProbabilidades;
double *g_medias;
double *g_pesos;
double *g_covarianzas;

double *g_L;
double *g_logDets;

__global__ void paso_e_cholesky(double *g_covarianzas, double *g_L, const size_t numDimensiones)
{
    const size_t k = blockIdx.z;

    for (size_t j = 0; j < numDimensiones; j++) {
        for (size_t h = 0; h < numDimensiones; h++) {
            g_L[k * numDimensiones * numDimensiones + j * numDimensiones + h] = 0.0;
        }
    }

    for (size_t i = 0; i < numDimensiones; i++) {
        for (size_t j = 0; j < i + 1; j++) {
            double suma = 0.0;

            for (size_t h = 0; h < j; h++) {
                suma += g_L[k * numDimensiones * numDimensiones + i * numDimensiones + h] * g_L[k * numDimensiones * numDimensiones + j * numDimensiones + h];
            }

            g_L[k * numDimensiones * numDimensiones + i * numDimensiones + j] = (i == j) ?
                sqrt(g_covarianzas[k * numDimensiones * numDimensiones + i * numDimensiones + i] - suma) :
                (1.0 / g_L[k * numDimensiones * numDimensiones + j * numDimensiones + j] * (g_covarianzas[k * numDimensiones * numDimensiones + i * numDimensiones + j] - suma));
        }
    }
}

__global__ void paso_e(double *g_L, double *g_logDets, double *g_datos, double *g_pesos, double *g_medias, double *g_resp, const size_t n, size_t const numDimensiones)
{
    const size_t i = blockIdx.x * BLOCK_SIZE + threadIdx.x;
    const size_t k = blockIdx.z;
    const size_t knd = k * numDimensiones;
    const size_t kndnd = knd * numDimensiones;

    if (i == 0 && threadIdx.x == 0) {
       g_logDets[k] = logaritmoDeterminante(g_L, k, numDimensiones);
    }

    __syncthreads();

    if (i < n) {
        extern __shared__ double sharedData[];
        double *v = (double*) &sharedData[threadIdx.x * numDimensiones];
        double suma = 0.0;
        double tmp;

        for (size_t j = 0; j < numDimensiones; j++) {
            tmp = g_datos[j * n + i] - g_medias[knd + j];

            for (size_t h = 0; h < j; h++) {
                tmp -= g_L[kndnd + j * numDimensiones + h] * v[h];
            }

            v[j] = tmp / g_L[kndnd + j * numDimensiones + j];

            suma += v[j] * v[j];
        }

        g_resp[k * n + i] = -0.5 * (suma + g_logDets[k]) + log(g_pesos[k]);
    }
}

__global__ void paso_e2(double *g_resp, double *g_verosimilitudParcial, const size_t n, const size_t numGaussianas)
{
    const size_t i = blockIdx.x * BLOCK_SIZE + threadIdx.x;

    if (i < n) {
        double suma = 0.0;
        double verosimilitudParcial;
        double maxContribucion = MENOS_INFINITO;

        for (size_t k = 0; k < numGaussianas; k++) {
            if (g_resp[k * n + i] > maxContribucion) {
                maxContribucion = g_resp[k * n + i];
            }
        }

        for (size_t k = 0; k < numGaussianas; k++) {
            suma += exp(g_resp[k * n + i] - maxContribucion);
        }

        verosimilitudParcial = maxContribucion + log(suma);

        for (size_t k = 0; k < numGaussianas; k++) {
            g_resp[k * n + i] = exp(g_resp[k * n + i] - verosimilitudParcial);
        }

        g_verosimilitudParcial[i] = verosimilitudParcial;
    }
}

__global__ void paso_e_verosimilitud(double *g_verosimilitudParcial, double *g_verosimilitud, const size_t n)
{
    extern __shared__ double sharedData[];

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_verosimilitudParcial[i]; },
            [&] () -> double* { return &g_verosimilitud[blockIdx.x]; },
            [&] () -> void { reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_verosimilitud[tid]; }, [&] () -> double* { return &g_verosimilitud[0]; }, sharedData, gridDim.x); },
            n, sharedData, gridDim.x * gridDim.y * gridDim.z);
}

__global__ void paso_m(double *g_resp, double *g_sumaProbabilidades, double *g_pesos, const size_t n)
{
    extern __shared__ double sharedData[];

    const size_t k = blockIdx.z;

    const size_t numGaussianas = gridDim.z;

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_resp[k * n + i]; },
            [&] () -> double* { return &g_sumaProbabilidades[k * gridDim.x + blockIdx.x]; },
            [&] () -> void {
                for (size_t a = 0; a < numGaussianas; a++) {
                    reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_sumaProbabilidades[a * gridDim.x + tid]; }, [&] () -> double* { return &g_sumaProbabilidades[a]; }, sharedData, gridDim.x);
                    if (threadIdx.x == 0) g_pesos[a] = g_sumaProbabilidades[a] / n;
                }
            }, n, sharedData, gridDim.x * gridDim.z);
}

__global__ void paso_m2(double *g_resp, double *g_datos, double *g_sumaProbabilidades, double *g_medias, const size_t n)
{
    extern __shared__ double sharedData[];

    const size_t j = blockIdx.y;
    const size_t k = blockIdx.z;

    const size_t numGaussianas = gridDim.z;
    const size_t numDimensiones = gridDim.y;

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_resp[k * n + i] * g_datos[j * n + i]; },
            [&] () -> double* { return &g_medias[k * numDimensiones * gridDim.x + j * gridDim.x + blockIdx.x]; },
            [&] () -> void {
                for (size_t a = 0; a < numGaussianas; a++) {
                    for (size_t b = 0; b < numDimensiones; b++) {
                        reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_medias[a * numDimensiones * gridDim.x + b * gridDim.x + tid]; }, [&] () -> double* { return &g_medias[a * numDimensiones + b]; }, sharedData, gridDim.x);
                        if (threadIdx.x == 0) g_medias[a * numDimensiones + b] /= g_sumaProbabilidades[a];
                    }
                }
            }, n, sharedData, gridDim.x * gridDim.y * gridDim.z);
}

__global__ void paso_m_covarianzas(double *g_resp, double *g_datos, double *g_medias, double *g_covarianzas, const size_t n, const size_t numDimensiones)
{
    __shared__ double sharedData[BLOCK_SIZE];
    __shared__ size_t numBloques;
    __shared__ size_t j;
    __shared__ size_t h;
    __shared__ size_t k;
    __shared__ size_t kn;
    __shared__ size_t jn;
    __shared__ size_t hn;
    __shared__ size_t knd;
    __shared__ double medias_j;
    __shared__ double medias_h;

    if (threadIdx.x == 0) {
        numBloques = gridDim.x * gridDim.y * gridDim.z;
        j = blockIdx.y / numDimensiones;
        h = blockIdx.y % numDimensiones;
        k = blockIdx.z;
        kn = k * n;
        jn = j * n;
        hn = h * n;
        knd = k * numDimensiones;
        medias_j = g_medias[knd + j];
        medias_h = g_medias[knd + h];
    }

    __syncthreads();

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_resp[kn + i] * (g_datos[jn + i] - medias_j) * (g_datos[hn + i] - medias_h); },
            [&] () -> double* { return &g_covarianzas[knd * numDimensiones * gridDim.x + j * numDimensiones * gridDim.x + h * gridDim.x + blockIdx.x]; },
            [&] () -> void {
            }, n, sharedData, numBloques);
}

__global__ void paso_m_covarianzas_final(double *g_sumaProbabilidades, double *g_covarianzas, const size_t numTrozos)
{
    extern __shared__ double sharedData[];

    const size_t j = blockIdx.x;
    const size_t h = blockIdx.y;
    const size_t k = blockIdx.z;

    const size_t numDimensiones = gridDim.y;

    reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_covarianzas[k * numDimensiones * numDimensiones * numTrozos + j * numDimensiones * numTrozos + h * numTrozos + tid]; }, [&] () -> double* { return &g_covarianzas[k * numDimensiones * numDimensiones + j * numDimensiones + h]; }, sharedData, numTrozos);
    if (threadIdx.x == 0) g_covarianzas[k * numDimensiones * numDimensiones + j * numDimensiones + h] /= g_sumaProbabilidades[k];
}

	.file	"tmpxft_002371bb_00000000-6_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3775:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z21logaritmoDeterminantePdmm
	.type	_Z21logaritmoDeterminantePdmm, @function
_Z21logaritmoDeterminantePdmm:
.LFB3769:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3769:
	.size	_Z21logaritmoDeterminantePdmm, .-_Z21logaritmoDeterminantePdmm
	.globl	_Z38__device_stub__Z15paso_e_choleskyPdS_mPdS_m
	.type	_Z38__device_stub__Z15paso_e_choleskyPdS_mPdS_m, @function
_Z38__device_stub__Z15paso_e_choleskyPdS_mPdS_m:
.LFB3797:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15paso_e_choleskyPdS_m(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L4:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3797:
	.size	_Z38__device_stub__Z15paso_e_choleskyPdS_mPdS_m, .-_Z38__device_stub__Z15paso_e_choleskyPdS_mPdS_m
	.globl	_Z15paso_e_choleskyPdS_m
	.type	_Z15paso_e_choleskyPdS_m, @function
_Z15paso_e_choleskyPdS_m:
.LFB3798:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z15paso_e_choleskyPdS_mPdS_m
	.cfi_endproc
.LFE3798:
	.size	_Z15paso_e_choleskyPdS_m, .-_Z15paso_e_choleskyPdS_m
	.globl	_Z37__device_stub__Z6paso_ePdS_S_S_S_S_mmPdS_S_S_S_S_mm
	.type	_Z37__device_stub__Z6paso_ePdS_S_S_S_S_mmPdS_S_S_S_S_mm, @function
_Z37__device_stub__Z6paso_ePdS_S_S_S_S_mmPdS_S_S_S_S_mm:
.LFB3799:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z6paso_ePdS_S_S_S_S_mm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L10:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3799:
	.size	_Z37__device_stub__Z6paso_ePdS_S_S_S_S_mmPdS_S_S_S_S_mm, .-_Z37__device_stub__Z6paso_ePdS_S_S_S_S_mmPdS_S_S_S_S_mm
	.globl	_Z6paso_ePdS_S_S_S_S_mm
	.type	_Z6paso_ePdS_S_S_S_S_mm, @function
_Z6paso_ePdS_S_S_S_S_mm:
.LFB3800:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z6paso_ePdS_S_S_S_S_mmPdS_S_S_S_S_mm
	.cfi_endproc
.LFE3800:
	.size	_Z6paso_ePdS_S_S_S_S_mm, .-_Z6paso_ePdS_S_S_S_S_mm
	.globl	_Z30__device_stub__Z7paso_e2PdS_mmPdS_mm
	.type	_Z30__device_stub__Z7paso_e2PdS_mmPdS_mm, @function
_Z30__device_stub__Z7paso_e2PdS_mmPdS_mm:
.LFB3801:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7paso_e2PdS_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3801:
	.size	_Z30__device_stub__Z7paso_e2PdS_mmPdS_mm, .-_Z30__device_stub__Z7paso_e2PdS_mmPdS_mm
	.globl	_Z7paso_e2PdS_mm
	.type	_Z7paso_e2PdS_mm, @function
_Z7paso_e2PdS_mm:
.LFB3802:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z7paso_e2PdS_mmPdS_mm
	.cfi_endproc
.LFE3802:
	.size	_Z7paso_e2PdS_mm, .-_Z7paso_e2PdS_mm
	.globl	_Z43__device_stub__Z20paso_e_verosimilitudPdS_mPdS_m
	.type	_Z43__device_stub__Z20paso_e_verosimilitudPdS_mPdS_m, @function
_Z43__device_stub__Z20paso_e_verosimilitudPdS_mPdS_m:
.LFB3803:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z20paso_e_verosimilitudPdS_m(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L20:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3803:
	.size	_Z43__device_stub__Z20paso_e_verosimilitudPdS_mPdS_m, .-_Z43__device_stub__Z20paso_e_verosimilitudPdS_mPdS_m
	.globl	_Z20paso_e_verosimilitudPdS_m
	.type	_Z20paso_e_verosimilitudPdS_m, @function
_Z20paso_e_verosimilitudPdS_m:
.LFB3804:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z20paso_e_verosimilitudPdS_mPdS_m
	.cfi_endproc
.LFE3804:
	.size	_Z20paso_e_verosimilitudPdS_m, .-_Z20paso_e_verosimilitudPdS_m
	.globl	_Z30__device_stub__Z6paso_mPdS_S_mPdS_S_m
	.type	_Z30__device_stub__Z6paso_mPdS_S_mPdS_S_m, @function
_Z30__device_stub__Z6paso_mPdS_S_mPdS_S_m:
.LFB3805:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6paso_mPdS_S_m(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L25:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3805:
	.size	_Z30__device_stub__Z6paso_mPdS_S_mPdS_S_m, .-_Z30__device_stub__Z6paso_mPdS_S_mPdS_S_m
	.globl	_Z6paso_mPdS_S_m
	.type	_Z6paso_mPdS_S_m, @function
_Z6paso_mPdS_S_m:
.LFB3806:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z6paso_mPdS_S_mPdS_S_m
	.cfi_endproc
.LFE3806:
	.size	_Z6paso_mPdS_S_m, .-_Z6paso_mPdS_S_m
	.globl	_Z33__device_stub__Z7paso_m2PdS_S_S_mPdS_S_S_m
	.type	_Z33__device_stub__Z7paso_m2PdS_S_S_mPdS_S_S_m, @function
_Z33__device_stub__Z7paso_m2PdS_S_S_mPdS_S_S_m:
.LFB3807:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7paso_m2PdS_S_S_m(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L30:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3807:
	.size	_Z33__device_stub__Z7paso_m2PdS_S_S_mPdS_S_S_m, .-_Z33__device_stub__Z7paso_m2PdS_S_S_mPdS_S_S_m
	.globl	_Z7paso_m2PdS_S_S_m
	.type	_Z7paso_m2PdS_S_S_m, @function
_Z7paso_m2PdS_S_S_m:
.LFB3808:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z7paso_m2PdS_S_S_mPdS_S_S_m
	.cfi_endproc
.LFE3808:
	.size	_Z7paso_m2PdS_S_S_m, .-_Z7paso_m2PdS_S_S_m
	.globl	_Z46__device_stub__Z18paso_m_covarianzasPdS_S_S_mmPdS_S_S_mm
	.type	_Z46__device_stub__Z18paso_m_covarianzasPdS_S_S_mmPdS_S_S_mm, @function
_Z46__device_stub__Z18paso_m_covarianzasPdS_S_S_mmPdS_S_S_mm:
.LFB3809:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18paso_m_covarianzasPdS_S_S_mm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L35:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3809:
	.size	_Z46__device_stub__Z18paso_m_covarianzasPdS_S_S_mmPdS_S_S_mm, .-_Z46__device_stub__Z18paso_m_covarianzasPdS_S_S_mmPdS_S_S_mm
	.globl	_Z18paso_m_covarianzasPdS_S_S_mm
	.type	_Z18paso_m_covarianzasPdS_S_S_mm, @function
_Z18paso_m_covarianzasPdS_S_S_mm:
.LFB3810:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z18paso_m_covarianzasPdS_S_S_mmPdS_S_S_mm
	.cfi_endproc
.LFE3810:
	.size	_Z18paso_m_covarianzasPdS_S_S_mm, .-_Z18paso_m_covarianzasPdS_S_S_mm
	.globl	_Z47__device_stub__Z24paso_m_covarianzas_finalPdS_mPdS_m
	.type	_Z47__device_stub__Z24paso_m_covarianzas_finalPdS_mPdS_m, @function
_Z47__device_stub__Z24paso_m_covarianzas_finalPdS_mPdS_m:
.LFB3811:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z24paso_m_covarianzas_finalPdS_m(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L40:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3811:
	.size	_Z47__device_stub__Z24paso_m_covarianzas_finalPdS_mPdS_m, .-_Z47__device_stub__Z24paso_m_covarianzas_finalPdS_mPdS_m
	.globl	_Z24paso_m_covarianzas_finalPdS_m
	.type	_Z24paso_m_covarianzas_finalPdS_m, @function
_Z24paso_m_covarianzas_finalPdS_m:
.LFB3812:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z24paso_m_covarianzas_finalPdS_mPdS_m
	.cfi_endproc
.LFE3812:
	.size	_Z24paso_m_covarianzas_finalPdS_m, .-_Z24paso_m_covarianzas_finalPdS_m
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24paso_m_covarianzas_finalPdS_m"
.LC1:
	.string	"_Z18paso_m_covarianzasPdS_S_S_mm"
.LC2:
	.string	"_Z7paso_m2PdS_S_S_m"
.LC3:
	.string	"_Z6paso_mPdS_S_m"
.LC4:
	.string	"_Z20paso_e_verosimilitudPdS_m"
.LC5:
	.string	"_Z7paso_e2PdS_mm"
.LC6:
	.string	"_Z6paso_ePdS_S_S_S_S_mm"
.LC7:
	.string	"_Z15paso_e_choleskyPdS_m"
.LC8:
	.string	"contadorBloques"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3814:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z24paso_m_covarianzas_finalPdS_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18paso_m_covarianzasPdS_S_S_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7paso_m2PdS_S_S_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6paso_mPdS_S_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20paso_e_verosimilitudPdS_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7paso_e2PdS_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6paso_ePdS_S_S_S_S_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15paso_e_choleskyPdS_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	movl	$4, %r9d
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_ZL15contadorBloques(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3814:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	g_logDets
	.bss
	.align 8
	.type	g_logDets, @object
	.size	g_logDets, 8
g_logDets:
	.zero	8
	.globl	g_L
	.align 8
	.type	g_L, @object
	.size	g_L, 8
g_L:
	.zero	8
	.globl	g_covarianzas
	.align 8
	.type	g_covarianzas, @object
	.size	g_covarianzas, 8
g_covarianzas:
	.zero	8
	.globl	g_pesos
	.align 8
	.type	g_pesos, @object
	.size	g_pesos, 8
g_pesos:
	.zero	8
	.globl	g_medias
	.align 8
	.type	g_medias, @object
	.size	g_medias, 8
g_medias:
	.zero	8
	.globl	g_sumaProbabilidades
	.align 8
	.type	g_sumaProbabilidades, @object
	.size	g_sumaProbabilidades, 8
g_sumaProbabilidades:
	.zero	8
	.globl	g_verosimilitudParcial
	.align 8
	.type	g_verosimilitudParcial, @object
	.size	g_verosimilitudParcial, 8
g_verosimilitudParcial:
	.zero	8
	.globl	g_verosimilitud
	.align 8
	.type	g_verosimilitud, @object
	.size	g_verosimilitud, 8
g_verosimilitud:
	.zero	8
	.globl	g_resp
	.align 8
	.type	g_resp, @object
	.size	g_resp, 8
g_resp:
	.zero	8
	.globl	g_datos
	.align 8
	.type	g_datos, @object
	.size	g_datos, 8
g_datos:
	.zero	8
	.local	_ZL15contadorBloques
	.comm	_ZL15contadorBloques,4,4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <functional>

#include "auxiliares.cu"

using namespace std;

// Punteros a memoria global
double *g_datos;
double *g_resp;

double *g_verosimilitud;
double *g_verosimilitudParcial;
double *g_sumaProbabilidades;
double *g_medias;
double *g_pesos;
double *g_covarianzas;

double *g_L;
double *g_logDets;

__global__ void paso_e_cholesky(double *g_covarianzas, double *g_L, const size_t numDimensiones)
{
    const size_t k = blockIdx.z;

    for (size_t j = 0; j < numDimensiones; j++) {
        for (size_t h = 0; h < numDimensiones; h++) {
            g_L[k * numDimensiones * numDimensiones + j * numDimensiones + h] = 0.0;
        }
    }

    for (size_t i = 0; i < numDimensiones; i++) {
        for (size_t j = 0; j < i + 1; j++) {
            double suma = 0.0;

            for (size_t h = 0; h < j; h++) {
                suma += g_L[k * numDimensiones * numDimensiones + i * numDimensiones + h] * g_L[k * numDimensiones * numDimensiones + j * numDimensiones + h];
            }

            g_L[k * numDimensiones * numDimensiones + i * numDimensiones + j] = (i == j) ?
                sqrt(g_covarianzas[k * numDimensiones * numDimensiones + i * numDimensiones + i] - suma) :
                (1.0 / g_L[k * numDimensiones * numDimensiones + j * numDimensiones + j] * (g_covarianzas[k * numDimensiones * numDimensiones + i * numDimensiones + j] - suma));
        }
    }
}

__global__ void paso_e(double *g_L, double *g_logDets, double *g_datos, double *g_pesos, double *g_medias, double *g_resp, const size_t n, size_t const numDimensiones)
{
    const size_t i = blockIdx.x * BLOCK_SIZE + threadIdx.x;
    const size_t k = blockIdx.z;
    const size_t knd = k * numDimensiones;
    const size_t kndnd = knd * numDimensiones;

    if (i == 0 && threadIdx.x == 0) {
       g_logDets[k] = logaritmoDeterminante(g_L, k, numDimensiones);
    }

    __syncthreads();

    if (i < n) {
        extern __shared__ double sharedData[];
        double *v = (double*) &sharedData[threadIdx.x * numDimensiones];
        double suma = 0.0;
        double tmp;

        for (size_t j = 0; j < numDimensiones; j++) {
            tmp = g_datos[j * n + i] - g_medias[knd + j];

            for (size_t h = 0; h < j; h++) {
                tmp -= g_L[kndnd + j * numDimensiones + h] * v[h];
            }

            v[j] = tmp / g_L[kndnd + j * numDimensiones + j];

            suma += v[j] * v[j];
        }

        g_resp[k * n + i] = -0.5 * (suma + g_logDets[k]) + log(g_pesos[k]);
    }
}

__global__ void paso_e2(double *g_resp, double *g_verosimilitudParcial, const size_t n, const size_t numGaussianas)
{
    const size_t i = blockIdx.x * BLOCK_SIZE + threadIdx.x;

    if (i < n) {
        double suma = 0.0;
        double verosimilitudParcial;
        double maxContribucion = MENOS_INFINITO;

        for (size_t k = 0; k < numGaussianas; k++) {
            if (g_resp[k * n + i] > maxContribucion) {
                maxContribucion = g_resp[k * n + i];
            }
        }

        for (size_t k = 0; k < numGaussianas; k++) {
            suma += exp(g_resp[k * n + i] - maxContribucion);
        }

        verosimilitudParcial = maxContribucion + log(suma);

        for (size_t k = 0; k < numGaussianas; k++) {
            g_resp[k * n + i] = exp(g_resp[k * n + i] - verosimilitudParcial);
        }

        g_verosimilitudParcial[i] = verosimilitudParcial;
    }
}

__global__ void paso_e_verosimilitud(double *g_verosimilitudParcial, double *g_verosimilitud, const size_t n)
{
    extern __shared__ double sharedData[];

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_verosimilitudParcial[i]; },
            [&] () -> double* { return &g_verosimilitud[blockIdx.x]; },
            [&] () -> void { reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_verosimilitud[tid]; }, [&] () -> double* { return &g_verosimilitud[0]; }, sharedData, gridDim.x); },
            n, sharedData, gridDim.x * gridDim.y * gridDim.z);
}

__global__ void paso_m(double *g_resp, double *g_sumaProbabilidades, double *g_pesos, const size_t n)
{
    extern __shared__ double sharedData[];

    const size_t k = blockIdx.z;

    const size_t numGaussianas = gridDim.z;

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_resp[k * n + i]; },
            [&] () -> double* { return &g_sumaProbabilidades[k * gridDim.x + blockIdx.x]; },
            [&] () -> void {
                for (size_t a = 0; a < numGaussianas; a++) {
                    reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_sumaProbabilidades[a * gridDim.x + tid]; }, [&] () -> double* { return &g_sumaProbabilidades[a]; }, sharedData, gridDim.x);
                    if (threadIdx.x == 0) g_pesos[a] = g_sumaProbabilidades[a] / n;
                }
            }, n, sharedData, gridDim.x * gridDim.z);
}

__global__ void paso_m2(double *g_resp, double *g_datos, double *g_sumaProbabilidades, double *g_medias, const size_t n)
{
    extern __shared__ double sharedData[];

    const size_t j = blockIdx.y;
    const size_t k = blockIdx.z;

    const size_t numGaussianas = gridDim.z;
    const size_t numDimensiones = gridDim.y;

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_resp[k * n + i] * g_datos[j * n + i]; },
            [&] () -> double* { return &g_medias[k * numDimensiones * gridDim.x + j * gridDim.x + blockIdx.x]; },
            [&] () -> void {
                for (size_t a = 0; a < numGaussianas; a++) {
                    for (size_t b = 0; b < numDimensiones; b++) {
                        reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_medias[a * numDimensiones * gridDim.x + b * gridDim.x + tid]; }, [&] () -> double* { return &g_medias[a * numDimensiones + b]; }, sharedData, gridDim.x);
                        if (threadIdx.x == 0) g_medias[a * numDimensiones + b] /= g_sumaProbabilidades[a];
                    }
                }
            }, n, sharedData, gridDim.x * gridDim.y * gridDim.z);
}

__global__ void paso_m_covarianzas(double *g_resp, double *g_datos, double *g_medias, double *g_covarianzas, const size_t n, const size_t numDimensiones)
{
    __shared__ double sharedData[BLOCK_SIZE];
    __shared__ size_t numBloques;
    __shared__ size_t j;
    __shared__ size_t h;
    __shared__ size_t k;
    __shared__ size_t kn;
    __shared__ size_t jn;
    __shared__ size_t hn;
    __shared__ size_t knd;
    __shared__ double medias_j;
    __shared__ double medias_h;

    if (threadIdx.x == 0) {
        numBloques = gridDim.x * gridDim.y * gridDim.z;
        j = blockIdx.y / numDimensiones;
        h = blockIdx.y % numDimensiones;
        k = blockIdx.z;
        kn = k * n;
        jn = j * n;
        hn = h * n;
        knd = k * numDimensiones;
        medias_j = g_medias[knd + j];
        medias_h = g_medias[knd + h];
    }

    __syncthreads();

    reducir<BLOCK_SIZE>([&] (size_t i) -> double { return g_resp[kn + i] * (g_datos[jn + i] - medias_j) * (g_datos[hn + i] - medias_h); },
            [&] () -> double* { return &g_covarianzas[knd * numDimensiones * gridDim.x + j * numDimensiones * gridDim.x + h * gridDim.x + blockIdx.x]; },
            [&] () -> void {
            }, n, sharedData, numBloques);
}

__global__ void paso_m_covarianzas_final(double *g_sumaProbabilidades, double *g_covarianzas, const size_t numTrozos)
{
    extern __shared__ double sharedData[];

    const size_t j = blockIdx.x;
    const size_t h = blockIdx.y;
    const size_t k = blockIdx.z;

    const size_t numDimensiones = gridDim.y;

    reducirFinal<BLOCK_SIZE>([&] (size_t tid) -> double* { return &g_covarianzas[k * numDimensiones * numDimensiones * numTrozos + j * numDimensiones * numTrozos + h * numTrozos + tid]; }, [&] () -> double* { return &g_covarianzas[k * numDimensiones * numDimensiones + j * numDimensiones + h]; }, sharedData, numTrozos);
    if (threadIdx.x == 0) g_covarianzas[k * numDimensiones * numDimensiones + j * numDimensiones + h] /= g_sumaProbabilidades[k];
}

	.text
	.file	"kernels.hip"
	.globl	_Z30__device_stub__paso_e_choleskyPdS_m # -- Begin function _Z30__device_stub__paso_e_choleskyPdS_m
	.type	_Z30__device_stub__paso_e_choleskyPdS_m,@function
_Z30__device_stub__paso_e_choleskyPdS_m: # @_Z30__device_stub__paso_e_choleskyPdS_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15paso_e_choleskyPdS_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__paso_e_choleskyPdS_m, .Lfunc_end0-_Z30__device_stub__paso_e_choleskyPdS_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__paso_ePdS_S_S_S_S_mm # -- Begin function _Z21__device_stub__paso_ePdS_S_S_S_S_mm
	.type	_Z21__device_stub__paso_ePdS_S_S_S_S_mm,@function
_Z21__device_stub__paso_ePdS_S_S_S_S_mm: # @_Z21__device_stub__paso_ePdS_S_S_S_S_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6paso_ePdS_S_S_S_S_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__paso_ePdS_S_S_S_S_mm, .Lfunc_end1-_Z21__device_stub__paso_ePdS_S_S_S_S_mm
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__paso_e2PdS_mm # -- Begin function _Z22__device_stub__paso_e2PdS_mm
	.type	_Z22__device_stub__paso_e2PdS_mm,@function
_Z22__device_stub__paso_e2PdS_mm:       # @_Z22__device_stub__paso_e2PdS_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7paso_e2PdS_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__paso_e2PdS_mm, .Lfunc_end2-_Z22__device_stub__paso_e2PdS_mm
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__paso_e_verosimilitudPdS_m # -- Begin function _Z35__device_stub__paso_e_verosimilitudPdS_m
	.type	_Z35__device_stub__paso_e_verosimilitudPdS_m,@function
_Z35__device_stub__paso_e_verosimilitudPdS_m: # @_Z35__device_stub__paso_e_verosimilitudPdS_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20paso_e_verosimilitudPdS_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z35__device_stub__paso_e_verosimilitudPdS_m, .Lfunc_end3-_Z35__device_stub__paso_e_verosimilitudPdS_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__paso_mPdS_S_m # -- Begin function _Z21__device_stub__paso_mPdS_S_m
	.type	_Z21__device_stub__paso_mPdS_S_m,@function
_Z21__device_stub__paso_mPdS_S_m:       # @_Z21__device_stub__paso_mPdS_S_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6paso_mPdS_S_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z21__device_stub__paso_mPdS_S_m, .Lfunc_end4-_Z21__device_stub__paso_mPdS_S_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__paso_m2PdS_S_S_m # -- Begin function _Z22__device_stub__paso_m2PdS_S_S_m
	.type	_Z22__device_stub__paso_m2PdS_S_S_m,@function
_Z22__device_stub__paso_m2PdS_S_S_m:    # @_Z22__device_stub__paso_m2PdS_S_S_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7paso_m2PdS_S_S_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22__device_stub__paso_m2PdS_S_S_m, .Lfunc_end5-_Z22__device_stub__paso_m2PdS_S_S_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__paso_m_covarianzasPdS_S_S_mm # -- Begin function _Z33__device_stub__paso_m_covarianzasPdS_S_S_mm
	.type	_Z33__device_stub__paso_m_covarianzasPdS_S_S_mm,@function
_Z33__device_stub__paso_m_covarianzasPdS_S_S_mm: # @_Z33__device_stub__paso_m_covarianzasPdS_S_S_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18paso_m_covarianzasPdS_S_S_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z33__device_stub__paso_m_covarianzasPdS_S_S_mm, .Lfunc_end6-_Z33__device_stub__paso_m_covarianzasPdS_S_S_mm
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__paso_m_covarianzas_finalPdS_m # -- Begin function _Z39__device_stub__paso_m_covarianzas_finalPdS_m
	.type	_Z39__device_stub__paso_m_covarianzas_finalPdS_m,@function
_Z39__device_stub__paso_m_covarianzas_finalPdS_m: # @_Z39__device_stub__paso_m_covarianzas_finalPdS_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24paso_m_covarianzas_finalPdS_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z39__device_stub__paso_m_covarianzas_finalPdS_m, .Lfunc_end7-_Z39__device_stub__paso_m_covarianzas_finalPdS_m
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15paso_e_choleskyPdS_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6paso_ePdS_S_S_S_S_mm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7paso_e2PdS_mm, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20paso_e_verosimilitudPdS_m, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6paso_mPdS_S_m, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7paso_m2PdS_S_S_m, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18paso_m_covarianzasPdS_S_S_mm, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24paso_m_covarianzas_finalPdS_m, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$contadorBloques, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	contadorBloques,@object         # @contadorBloques
	.local	contadorBloques
	.comm	contadorBloques,4,4
	.type	g_datos,@object                 # @g_datos
	.bss
	.globl	g_datos
	.p2align	3, 0x0
g_datos:
	.quad	0
	.size	g_datos, 8

	.type	g_resp,@object                  # @g_resp
	.globl	g_resp
	.p2align	3, 0x0
g_resp:
	.quad	0
	.size	g_resp, 8

	.type	g_verosimilitud,@object         # @g_verosimilitud
	.globl	g_verosimilitud
	.p2align	3, 0x0
g_verosimilitud:
	.quad	0
	.size	g_verosimilitud, 8

	.type	g_verosimilitudParcial,@object  # @g_verosimilitudParcial
	.globl	g_verosimilitudParcial
	.p2align	3, 0x0
g_verosimilitudParcial:
	.quad	0
	.size	g_verosimilitudParcial, 8

	.type	g_sumaProbabilidades,@object    # @g_sumaProbabilidades
	.globl	g_sumaProbabilidades
	.p2align	3, 0x0
g_sumaProbabilidades:
	.quad	0
	.size	g_sumaProbabilidades, 8

	.type	g_medias,@object                # @g_medias
	.globl	g_medias
	.p2align	3, 0x0
g_medias:
	.quad	0
	.size	g_medias, 8

	.type	g_pesos,@object                 # @g_pesos
	.globl	g_pesos
	.p2align	3, 0x0
g_pesos:
	.quad	0
	.size	g_pesos, 8

	.type	g_covarianzas,@object           # @g_covarianzas
	.globl	g_covarianzas
	.p2align	3, 0x0
g_covarianzas:
	.quad	0
	.size	g_covarianzas, 8

	.type	g_L,@object                     # @g_L
	.globl	g_L
	.p2align	3, 0x0
g_L:
	.quad	0
	.size	g_L, 8

	.type	g_logDets,@object               # @g_logDets
	.globl	g_logDets
	.p2align	3, 0x0
g_logDets:
	.quad	0
	.size	g_logDets, 8

	.type	_Z15paso_e_choleskyPdS_m,@object # @_Z15paso_e_choleskyPdS_m
	.section	.rodata,"a",@progbits
	.globl	_Z15paso_e_choleskyPdS_m
	.p2align	3, 0x0
_Z15paso_e_choleskyPdS_m:
	.quad	_Z30__device_stub__paso_e_choleskyPdS_m
	.size	_Z15paso_e_choleskyPdS_m, 8

	.type	_Z6paso_ePdS_S_S_S_S_mm,@object # @_Z6paso_ePdS_S_S_S_S_mm
	.globl	_Z6paso_ePdS_S_S_S_S_mm
	.p2align	3, 0x0
_Z6paso_ePdS_S_S_S_S_mm:
	.quad	_Z21__device_stub__paso_ePdS_S_S_S_S_mm
	.size	_Z6paso_ePdS_S_S_S_S_mm, 8

	.type	_Z7paso_e2PdS_mm,@object        # @_Z7paso_e2PdS_mm
	.globl	_Z7paso_e2PdS_mm
	.p2align	3, 0x0
_Z7paso_e2PdS_mm:
	.quad	_Z22__device_stub__paso_e2PdS_mm
	.size	_Z7paso_e2PdS_mm, 8

	.type	_Z20paso_e_verosimilitudPdS_m,@object # @_Z20paso_e_verosimilitudPdS_m
	.globl	_Z20paso_e_verosimilitudPdS_m
	.p2align	3, 0x0
_Z20paso_e_verosimilitudPdS_m:
	.quad	_Z35__device_stub__paso_e_verosimilitudPdS_m
	.size	_Z20paso_e_verosimilitudPdS_m, 8

	.type	_Z6paso_mPdS_S_m,@object        # @_Z6paso_mPdS_S_m
	.globl	_Z6paso_mPdS_S_m
	.p2align	3, 0x0
_Z6paso_mPdS_S_m:
	.quad	_Z21__device_stub__paso_mPdS_S_m
	.size	_Z6paso_mPdS_S_m, 8

	.type	_Z7paso_m2PdS_S_S_m,@object     # @_Z7paso_m2PdS_S_S_m
	.globl	_Z7paso_m2PdS_S_S_m
	.p2align	3, 0x0
_Z7paso_m2PdS_S_S_m:
	.quad	_Z22__device_stub__paso_m2PdS_S_S_m
	.size	_Z7paso_m2PdS_S_S_m, 8

	.type	_Z18paso_m_covarianzasPdS_S_S_mm,@object # @_Z18paso_m_covarianzasPdS_S_S_mm
	.globl	_Z18paso_m_covarianzasPdS_S_S_mm
	.p2align	3, 0x0
_Z18paso_m_covarianzasPdS_S_S_mm:
	.quad	_Z33__device_stub__paso_m_covarianzasPdS_S_S_mm
	.size	_Z18paso_m_covarianzasPdS_S_S_mm, 8

	.type	_Z24paso_m_covarianzas_finalPdS_m,@object # @_Z24paso_m_covarianzas_finalPdS_m
	.globl	_Z24paso_m_covarianzas_finalPdS_m
	.p2align	3, 0x0
_Z24paso_m_covarianzas_finalPdS_m:
	.quad	_Z39__device_stub__paso_m_covarianzas_finalPdS_m
	.size	_Z24paso_m_covarianzas_finalPdS_m, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15paso_e_choleskyPdS_m"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6paso_ePdS_S_S_S_S_mm"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7paso_e2PdS_mm"
	.size	.L__unnamed_3, 17

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z20paso_e_verosimilitudPdS_m"
	.size	.L__unnamed_4, 30

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z6paso_mPdS_S_m"
	.size	.L__unnamed_5, 17

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z7paso_m2PdS_S_S_m"
	.size	.L__unnamed_6, 20

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z18paso_m_covarianzasPdS_S_S_mm"
	.size	.L__unnamed_7, 33

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z24paso_m_covarianzas_finalPdS_m"
	.size	.L__unnamed_8, 34

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"contadorBloques"
	.size	.L__unnamed_9, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__paso_e_choleskyPdS_m
	.addrsig_sym _Z21__device_stub__paso_ePdS_S_S_S_S_mm
	.addrsig_sym _Z22__device_stub__paso_e2PdS_mm
	.addrsig_sym _Z35__device_stub__paso_e_verosimilitudPdS_m
	.addrsig_sym _Z21__device_stub__paso_mPdS_S_m
	.addrsig_sym _Z22__device_stub__paso_m2PdS_S_S_m
	.addrsig_sym _Z33__device_stub__paso_m_covarianzasPdS_S_S_mm
	.addrsig_sym _Z39__device_stub__paso_m_covarianzas_finalPdS_m
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym contadorBloques
	.addrsig_sym _Z15paso_e_choleskyPdS_m
	.addrsig_sym _Z6paso_ePdS_S_S_S_S_mm
	.addrsig_sym _Z7paso_e2PdS_mm
	.addrsig_sym _Z20paso_e_verosimilitudPdS_m
	.addrsig_sym _Z6paso_mPdS_S_m
	.addrsig_sym _Z7paso_m2PdS_S_S_m
	.addrsig_sym _Z18paso_m_covarianzasPdS_S_S_mm
	.addrsig_sym _Z24paso_m_covarianzas_finalPdS_m
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15paso_e_choleskyPdS_m ; -- Begin function _Z15paso_e_choleskyPdS_m
	.globl	_Z15paso_e_choleskyPdS_m
	.p2align	8
	.type	_Z15paso_e_choleskyPdS_m,@function
_Z15paso_e_choleskyPdS_m:               ; @_Z15paso_e_choleskyPdS_m
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x10
	s_mov_b64 s[10:11], 0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u64 s[4:5], 0
	s_cbranch_scc1 .LBB0_17
; %bb.1:                                ; %.preheader79.lr.ph
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mul_i32 s6, s4, s5
	s_mul_hi_u32 s7, s4, s4
	s_mul_i32 s8, s4, s4
	s_add_i32 s7, s7, s6
	v_mov_b32_e32 v0, 0
	s_add_i32 s6, s7, s6
	s_mul_hi_u32 s7, s8, s15
	s_mul_i32 s9, s6, s15
	s_mul_i32 s6, s8, s15
	s_add_i32 s7, s7, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[6:7], 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s2, s6
	s_addc_u32 s7, s3, s7
	s_lshl_b64 s[8:9], s[4:5], 3
	s_mov_b64 s[12:13], s[6:7]
.LBB0_2:                                ; %.preheader79
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[16:17], s[12:13]
	s_mov_b64 s[18:19], s[4:5]
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, v0
	s_add_u32 s18, s18, -1
	s_addc_u32 s19, s19, -1
	global_store_b64 v0, v[0:1], s[16:17]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_eq_u64 s[18:19], 0
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, s8
	s_addc_u32 s13, s13, s9
	s_cmp_eq_u64 s[10:11], s[4:5]
	s_cbranch_scc0 .LBB0_2
; %bb.5:                                ; %.preheader78
	s_mul_i32 s10, s15, s5
	s_mul_hi_u32 s11, s15, s4
	s_mul_i32 s29, s15, s4
	s_add_i32 s28, s11, s10
	v_mov_b32_e32 v4, 0
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 1
	s_mov_b64 s[14:15], s[6:7]
.LBB0_6:                                ; %.preheader77
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
                                        ;       Child Loop BB0_9 Depth 3
	s_lshl_b64 s[18:19], s[10:11], 3
	s_add_u32 s16, s10, s29
	s_addc_u32 s21, s11, s28
	s_mul_i32 s17, s16, s5
	s_mul_hi_u32 s20, s16, s4
	s_mul_i32 s21, s21, s4
	s_add_i32 s17, s20, s17
	s_mul_i32 s16, s16, s4
	s_add_i32 s17, s17, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[16:17], 3
	s_mov_b64 s[16:17], s[6:7]
	s_add_u32 s30, s2, s20
	s_addc_u32 s31, s3, s21
	s_add_u32 s33, s0, s20
	s_addc_u32 s34, s1, s21
	s_add_u32 s18, s33, s18
	s_addc_u32 s19, s34, s19
	s_mov_b64 s[20:21], 0
.LBB0_7:                                ; %.preheader
                                        ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_9 Depth 3
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_cmp_eq_u64 s[20:21], 0
	s_cbranch_scc1 .LBB0_10
; %bb.8:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], s[14:15]
	s_mov_b64 s[26:27], s[16:17]
.LBB0_9:                                ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_7 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_clause 0x1
	global_load_b64 v[2:3], v4, s[24:25]
	global_load_b64 v[5:6], v4, s[26:27]
	s_add_u32 s22, s22, 1
	s_addc_u32 s23, s23, 0
	s_add_u32 s26, s26, 8
	v_cmp_ge_u64_e64 s35, s[22:23], s[20:21]
	s_addc_u32 s27, s27, 0
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s35
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[2:3], v[5:6], v[0:1]
	s_cbranch_vccz .LBB0_9
.LBB0_10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_cmp_lg_u64 s[10:11], s[20:21]
	s_cbranch_scc0 .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_7 Depth=2
	s_add_u32 s22, s20, s29
	s_addc_u32 s25, s21, s28
	s_mul_i32 s23, s22, s5
	s_mul_hi_u32 s24, s22, s4
	s_mul_i32 s25, s25, s4
	s_add_i32 s23, s24, s23
	s_mul_i32 s22, s22, s4
	s_add_i32 s23, s23, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[22:23], s[22:23], 3
	s_add_u32 s24, s2, s22
	s_addc_u32 s25, s3, s23
	s_lshl_b64 s[22:23], s[20:21], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s24, s22
	s_addc_u32 s25, s25, s23
	s_add_u32 s22, s33, s22
	global_load_b64 v[2:3], v4, s[24:25]
	s_addc_u32 s23, s34, s23
	global_load_b64 v[5:6], v4, s[22:23]
	s_mov_b32 s22, 0
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[7:8], null, v[2:3], v[2:3], 1.0
	v_div_scale_f64 v[13:14], vcc_lo, 1.0, v[2:3], 1.0
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[5:6], -v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
	v_div_fixup_f64 v[2:3], v[7:8], v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[5:6]
	s_branch .LBB0_13
.LBB0_12:                               ;   in Loop: Header=BB0_7 Depth=2
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_13:                               ; %Flow
                                        ;   in Loop: Header=BB0_7 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_7 Depth=2
	global_load_b64 v[2:3], v4, s[18:19]
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], -v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_and_b32 s22, vcc_lo, exec_lo
	s_cselect_b32 s22, 0xffffff80, 0
	v_lshlrev_b32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[0:1], v[0:1], v2
	v_rsq_f64_e32 v[2:3], v[0:1]
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[5:6], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[2:3], v[5:6], 0.5
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_fma_f64 v[2:3], v[2:3], v[7:8], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[5:6], v[5:6], v[0:1]
	v_fma_f64 v[5:6], v[7:8], v[2:3], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[5:6], v[5:6], v[0:1]
	v_fma_f64 v[2:3], v[7:8], v[2:3], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], s22
	v_dual_cndmask_b32 v3, v3, v1 :: v_dual_cndmask_b32 v2, v2, v0
.LBB0_15:                               ;   in Loop: Header=BB0_7 Depth=2
	s_lshl_b64 s[22:23], s[20:21], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s30, s22
	s_addc_u32 s23, s31, s23
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_add_u32 s16, s16, s8
	s_addc_u32 s17, s17, s9
	s_cmp_eq_u64 s[20:21], s[12:13]
	global_store_b64 v4, v[2:3], s[22:23]
	s_cbranch_scc0 .LBB0_7
; %bb.16:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, s8
	s_addc_u32 s15, s15, s9
	s_cmp_eq_u64 s[10:11], s[4:5]
	s_cbranch_scc0 .LBB0_6
.LBB0_17:                               ; %._crit_edge87
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15paso_e_choleskyPdS_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15paso_e_choleskyPdS_m, .Lfunc_end0-_Z15paso_e_choleskyPdS_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 920
; NumSgprs: 38
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6paso_ePdS_S_S_S_S_mm ; -- Begin function _Z6paso_ePdS_S_S_S_S_mm
	.globl	_Z6paso_ePdS_S_S_S_S_mm
	.p2align	8
	.type	_Z6paso_ePdS_S_S_S_S_mm,@function
_Z6paso_ePdS_S_S_S_S_mm:                ; @_Z6paso_ePdS_S_S_S_S_mm
; %bb.0:
	s_load_b512 s[16:31], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_mov_b32 s15, 0
	s_mov_b32 s33, exec_lo
	s_lshl_b64 s[0:1], s[14:15], 7
	s_mov_b32 s3, s15
	v_add_co_u32 v1, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, null, s1, 0, s0
	v_cmpx_eq_u64_e32 0, v[1:2]
	s_cbranch_execz .LBB1_7
; %bb.1:
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u64 s[30:31], 0
	s_cbranch_scc1 .LBB1_5
; %bb.2:                                ; %.lr.ph.i.preheader
	s_mul_i32 s0, s30, s31
	s_mul_hi_u32 s1, s30, s30
	s_mul_i32 s4, s30, s30
	s_add_i32 s1, s1, s0
	v_mov_b32_e32 v3, 0
	s_add_i32 s0, s1, s0
	s_mul_hi_u32 s1, s4, s2
	s_mul_i32 s5, s0, s2
	s_mul_i32 s0, s4, s2
	s_add_i32 s1, s1, s5
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_mov_b32 s4, 0x55555555
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_lshl_b64 s[40:41], s[30:31], 3
	s_mov_b32 s6, 0x6b47b09a
	s_mov_b32 s8, 0xbf559e2b
	s_mov_b32 s10, 0xd7f4df2e
	s_mov_b32 s12, 0x16291751
	s_mov_b32 s14, 0x9b27acf1
	s_mov_b32 s34, 0x998ef7b6
	s_mov_b32 s36, 0xfefa39ef
	s_mov_b32 s38, 0x3b39803f
	s_add_u32 s46, s40, 8
	s_mov_b32 s5, 0x3fe55555
	s_mov_b32 s7, 0x3fc38538
	s_mov_b32 s9, 0x3fc3ab76
	s_mov_b32 s11, 0x3fc7474d
	s_mov_b32 s13, 0x3fcc71c0
	s_mov_b32 s15, 0x3fd24924
	s_mov_b32 s35, 0x3fd99999
	s_mov_b32 s37, 0x3fe62e42
	s_mov_b32 s39, 0x3c7abc9e
	s_addc_u32 s47, s41, 0
	s_mov_b32 s40, 0x55555780
	s_mov_b64 s[42:43], s[30:31]
.LBB1_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b64 s[44:45], s[0:1], 0x0
	s_mov_b32 s41, s5
	s_add_u32 s0, s0, s46
	s_addc_u32 s1, s1, s47
	s_add_u32 s42, s42, -1
	s_addc_u32 s43, s43, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u64 s[42:43], 0
	s_waitcnt lgkmcnt(0)
	v_frexp_mant_f64_e32 v[5:6], s[44:45]
	v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[5:6]
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[5:6], v[5:6], v7
	v_add_f64 v[7:8], v[5:6], 1.0
	v_add_f64 v[13:14], v[5:6], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	v_add_f64 v[15:16], v[7:8], -1.0
	v_add_f64 v[5:6], v[5:6], -v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[7:8], v[11:12]
	v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[11:12], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[17:18], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[13:14], -v[7:8]
	v_add_f64 v[17:18], v[7:8], -v[17:18]
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[17:18], -v[5:6]
	v_frexp_exp_i32_f64_e32 v17, s[44:45]
	v_add_f64 v[7:8], v[13:14], -v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[5:6], v[15:16], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[5:6], v[9:10], v[5:6]
	v_add_f64 v[7:8], v[11:12], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[7:8], v[7:8]
	v_fma_f64 v[13:14], v[9:10], s[8:9], s[6:7]
	v_mul_f64 v[15:16], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[10:11]
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[14:15]
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[9:10], v[9:10], v[13:14], s[40:41]
	v_ldexp_f64 v[13:14], v[7:8], 1
	v_add_f64 v[7:8], v[7:8], -v[11:12]
	v_cmp_class_f64_e64 s41, s[44:45], 0x204
	v_mul_f64 v[9:10], v[15:16], v[9:10]
	v_subrev_co_ci_u32_e32 v15, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_cmp_nlt_f64_e64 vcc_lo, s[44:45], 0
	v_cvt_f64_i32_e32 v[15:16], v15
	v_add_f64 v[11:12], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[5:6], v[5:6], 1
	v_mul_f64 v[17:18], v[15:16], s[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[11:12], -v[13:14]
	v_fma_f64 v[13:14], v[15:16], s[36:37], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[9:10], -v[7:8]
	v_fma_f64 v[9:10], v[15:16], s[38:39], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[11:12], v[5:6]
	v_add_f64 v[17:18], v[7:8], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[7:8], v[13:14]
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[15:16], -v[7:8]
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], -v[19:20]
	v_add_f64 v[11:12], v[13:14], -v[19:20]
	v_add_f64 v[13:14], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[21:22]
	v_add_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[13:14], -v[9:10]
	v_add_f64 v[7:8], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], -v[11:12]
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	v_add_f64 v[17:18], v[15:16], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	v_add_f64 v[11:12], v[17:18], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[9:10]
	v_add_f64 v[7:8], v[7:8], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[5:6], v[17:18], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v6, s45, s41
	v_cndmask_b32_e64 v5, v5, s44, s41
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, 0x7ff80000, v6, vcc_lo
	v_cmp_nle_f64_e64 vcc_lo, s[44:45], 0
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_neq_f64_e64 vcc_lo, s[44:45], 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0xfff00000, v6, vcc_lo
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_cbranch_scc0 .LBB1_3
; %bb.4:                                ; %._crit_edge.loopexit.i
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], v[3:4]
	s_branch .LBB1_6
.LBB1_5:
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
.LBB1_6:                                ; %_Z21logaritmoDeterminantePdmm.exit
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v5, 0
	s_add_u32 s0, s18, s0
	s_addc_u32 s1, s19, s1
	global_store_b64 v5, v[3:4], s[0:1]
.LBB1_7:                                ; %Flow129
	s_or_b32 exec_lo, exec_lo, s33
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u64_e64 s[28:29], v[1:2]
	s_cbranch_execz .LBB1_17
; %bb.8:
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_cmp_eq_u64 s[30:31], 0
	s_mov_b64 s[0:1], 0
	s_cbranch_scc1 .LBB1_15
; %bb.9:                                ; %.lr.ph72
	s_mul_i32 s5, s2, s31
	s_mul_hi_u32 s6, s2, s30
	s_mul_i32 s4, s2, s30
	s_add_i32 s5, s6, s5
	s_mul_i32 s8, s30, s31
	s_lshl_b64 s[6:7], s[4:5], 3
	s_mul_hi_u32 s9, s30, s30
	s_add_u32 s33, s24, s6
	v_mul_lo_u32 v0, v0, s30
	s_addc_u32 s34, s25, s7
	s_mul_i32 s7, s4, s31
	s_mul_hi_u32 s10, s4, s30
	s_add_i32 s9, s9, s8
	s_add_i32 s7, s10, s7
	s_add_i32 s8, s9, s8
	s_mul_i32 s10, s30, s30
	s_mul_i32 s8, s8, s2
	s_mul_hi_u32 s9, s10, s2
	v_add_co_u32 v7, vcc_lo, s20, v1
	s_add_i32 s9, s9, s8
	s_mul_i32 s8, s10, s2
	s_mul_i32 s6, s5, s30
	v_mov_b32_e32 v3, 0
	v_lshl_add_u32 v0, v0, 3, 0
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v2, vcc_lo
	s_lshl_b64 s[8:9], s[8:9], 3
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v9, 0
	s_add_i32 s7, s7, s6
	s_add_u32 s8, s16, s8
	s_mul_i32 s6, s4, s30
	s_addc_u32 s9, s17, s9
	s_lshl_b64 s[10:11], s[30:31], 3
.LBB1_10:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_12 Depth 2
	s_mul_i32 s12, s0, s29
	s_mul_hi_u32 s13, s0, s28
	s_mul_i32 s14, s1, s28
	s_add_i32 s13, s13, s12
	s_mul_i32 s12, s0, s28
	s_add_i32 s13, s13, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[12:13], 3
	v_add_co_u32 v5, vcc_lo, v7, s12
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v8, vcc_lo
	s_lshl_b64 s[12:13], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s14, s33, s12
	s_addc_u32 s15, s34, s13
	global_load_b64 v[5:6], v[5:6], off
	global_load_b64 v[10:11], v9, s[14:15]
	s_cmp_eq_u64 s[0:1], 0
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[5:6], -v[10:11]
	s_cbranch_scc1 .LBB1_13
; %bb.11:                               ; %.lr.ph
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_add_u32 s14, s0, s4
	s_addc_u32 s15, s1, s5
	s_mul_i32 s20, s14, s31
	s_mul_hi_u32 s21, s14, s30
	v_mov_b32_e32 v10, v0
	s_mul_i32 s15, s15, s30
	s_add_i32 s20, s21, s20
	s_mul_i32 s14, s14, s30
	s_add_i32 s15, s20, s15
	s_mov_b64 s[20:21], 0
	s_mov_b64 s[24:25], s[8:9]
.LBB1_12:                               ;   Parent Loop BB1_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[11:12], v9, s[24:25]
	ds_load_b64 v[13:14], v10
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	v_add_nc_u32_e32 v10, 8, v10
	v_cmp_ge_u64_e64 s35, s[20:21], s[0:1]
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s35
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[5:6], -v[11:12], v[13:14], v[5:6]
	s_cbranch_vccz .LBB1_12
	s_branch .LBB1_14
.LBB1_13:                               ;   in Loop: Header=BB1_10 Depth=1
	s_mov_b64 s[14:15], s[6:7]
.LBB1_14:                               ; %._crit_edge
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[14:15], s[14:15], 3
	s_add_u32 s14, s16, s14
	s_addc_u32 s15, s17, s15
	s_add_u32 s12, s14, s12
	s_addc_u32 s13, s15, s13
	global_load_b64 v[10:11], v9, s[12:13]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, v[5:6], v[10:11], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	v_fma_f64 v[12:13], -v[12:13], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[18:19]
	v_div_fixup_f64 v[5:6], v[12:13], v[10:11], v[5:6]
	v_lshl_add_u32 v10, s0, 3, v0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_add_u32 s8, s8, s10
	s_addc_u32 s9, s9, s11
	s_cmp_eq_u64 s[0:1], s[30:31]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[3:4], v[5:6], v[5:6], v[3:4]
	ds_store_b64 v10, v[5:6]
	s_cbranch_scc0 .LBB1_10
	s_branch .LBB1_16
.LBB1_15:
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
.LBB1_16:                               ; %Flow126
	s_lshl_b64 s[4:5], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s18, s4
	s_addc_u32 s1, s19, s5
	s_add_u32 s4, s22, s4
	s_addc_u32 s5, s23, s5
	s_mov_b32 s6, 0x6b47b09a
	s_clause 0x1
	global_load_b64 v[5:6], v0, s[4:5]
	global_load_b64 v[23:24], v0, s[0:1]
	s_mov_b32 s5, 0x3fe55555
	s_mov_b32 s4, 0x55555555
	s_mov_b32 s8, 0xbf559e2b
	s_mov_b32 s7, 0x3fc38538
	s_mov_b32 s9, 0x3fc3ab76
	s_mul_i32 s0, s2, s29
	s_mul_hi_u32 s1, s2, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, s0
	s_mul_i32 s0, s2, s28
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s26, s0
	s_addc_u32 s1, s27, s1
	s_waitcnt vmcnt(1)
	v_frexp_mant_f64_e32 v[7:8], v[5:6]
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[7:8]
	s_mov_b32 s4, 0x55555780
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_ldexp_f64 v[7:8], v[7:8], v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[7:8], 1.0
	v_add_f64 v[15:16], v[7:8], -1.0
	v_rcp_f64_e32 v[11:12], v[9:10]
	v_add_f64 v[17:18], v[9:10], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	v_mul_f64 v[19:20], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[13:14], v[9:10], -v[19:20]
	v_fma_f64 v[7:8], v[13:14], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[19:20], v[7:8]
	v_add_f64 v[17:18], v[15:16], -v[9:10]
	v_add_f64 v[19:20], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[17:18]
	v_add_f64 v[7:8], v[19:20], -v[7:8]
	v_frexp_exp_i32_f64_e32 v19, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	v_add_f64 v[7:8], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[17:18], v[7:8]
	v_mul_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[13:14], v[7:8]
	v_mul_f64 v[11:12], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[11:12], s[8:9], s[6:7]
	s_mov_b32 s6, 0xd7f4df2e
	s_mov_b32 s7, 0x3fc7474d
	v_mul_f64 v[17:18], v[9:10], v[11:12]
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[6:7]
	s_mov_b32 s6, 0x16291751
	s_mov_b32 s7, 0x3fcc71c0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[6:7]
	s_mov_b32 s6, 0x9b27acf1
	s_mov_b32 s7, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[6:7]
	s_mov_b32 s6, 0x998ef7b6
	s_mov_b32 s7, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[11:12], v[15:16], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[11:12], v[15:16], s[4:5]
	v_ldexp_f64 v[15:16], v[9:10], 1
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	s_mov_b32 s4, 0xfefa39ef
	s_mov_b32 s5, 0x3fe62e42
	v_mul_f64 v[11:12], v[17:18], v[11:12]
	v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_cmp_class_f64_e64 vcc_lo, v[5:6], 0x204
	v_cvt_f64_i32_e32 v[17:18], v17
	v_add_f64 v[13:14], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[7:8], v[7:8], 1
	v_mul_f64 v[19:20], v[17:18], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[13:14], -v[15:16]
	v_fma_f64 v[15:16], v[17:18], s[4:5], -v[19:20]
	s_mov_b32 s4, 0x3b39803f
	s_mov_b32 s5, 0x3c7abc9e
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[11:12], -v[9:10]
	v_fma_f64 v[11:12], v[17:18], s[4:5], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[9:10], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[13:14], v[7:8]
	v_add_f64 v[19:20], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[9:10], v[15:16]
	v_add_f64 v[13:14], v[15:16], -v[13:14]
	v_add_f64 v[11:12], v[11:12], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[17:18], -v[9:10]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[17:18], -v[21:22]
	v_add_f64 v[13:14], v[15:16], -v[21:22]
	v_add_f64 v[15:16], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -v[25:26]
	v_add_f64 v[9:10], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[15:16], -v[11:12]
	v_add_f64 v[9:10], v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[13:14]
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	v_add_f64 v[19:20], v[17:18], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	v_add_f64 v[13:14], v[19:20], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[11:12]
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_add_f64 v[7:8], v[19:20], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v0, v7, v5 :: v_dual_cndmask_b32 v7, v8, v6
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[5:6]
	v_cndmask_b32_e32 v8, 0x7ff80000, v7, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, 0, v0, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[5:6]
	v_cndmask_b32_e32 v8, 0xfff00000, v8, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[3:4], v[3:4], -0.5, v[7:8]
	global_store_b64 v[0:1], v[3:4], off
.LBB1_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6paso_ePdS_S_S_S_S_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 64
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 48
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6paso_ePdS_S_S_S_S_mm, .Lfunc_end1-_Z6paso_ePdS_S_S_S_S_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2836
; NumSgprs: 50
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 50
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7paso_e2PdS_mm        ; -- Begin function _Z7paso_e2PdS_mm
	.globl	_Z7paso_e2PdS_mm
	.p2align	8
	.type	_Z7paso_e2PdS_mm,@function
_Z7paso_e2PdS_mm:                       ; @_Z7paso_e2PdS_mm
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	s_mov_b32 s8, s15
	s_mov_b32 s9, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 7
	v_add_co_u32 v0, s8, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s9, 0, s8
	s_mov_b32 s8, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u64_e64 s[4:5], v[0:1]
	s_cbranch_execz .LBB2_11
; %bb.1:                                ; %.preheader49
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_mov_b32 s8, -1
	s_mov_b32 s9, 0xffefffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
	s_cmp_lg_u64 s[6:7], 0
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u64 s[6:7], 0
	s_cbranch_scc1 .LBB2_4
; %bb.2:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	s_lshl_b64 s[8:9], s[4:5], 3
	s_mov_b64 s[10:11], s[6:7]
.LBB2_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[8:9], v[6:7], off
	v_add_co_u32 v6, s0, v6, s8
	s_add_u32 s10, s10, -1
	v_add_co_ci_u32_e64 v7, s0, s9, v7, s0
	s_addc_u32 s11, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[10:11], 0
	s_waitcnt vmcnt(0)
	v_cmp_gt_f64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
	s_cbranch_scc0 .LBB2_3
.LBB2_4:                                ; %.preheader
	v_mov_b32_e32 v6, 0
	v_cndmask_b32_e64 v10, 0, 1, s1
	v_mov_b32_e32 v7, 0
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_7
; %bb.5:                                ; %.lr.ph56.preheader
	v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
	s_mov_b32 s8, 0x652b82fe
	s_mov_b32 s10, 0xfefa39ef
	s_mov_b32 s12, 0x3b39803f
	s_mov_b32 s14, 0xfca7ab0c
	s_mov_b32 s16, 0x6a5dcb37
	s_mov_b32 s18, 0x623fde64
	s_mov_b32 s20, 0x7c89e6b0
	s_mov_b32 s22, 0x14761f6e
	s_mov_b32 s24, 0x1852b7b0
	s_mov_b32 s26, 0x11122322
	s_mov_b32 s28, 0x555502a1
	s_mov_b32 s30, 0x55555511
	s_mov_b32 s34, 11
	s_mov_b32 s9, 0x3ff71547
	s_mov_b32 s11, 0xbfe62e42
	s_mov_b32 s13, 0xbc7abc9e
	s_mov_b32 s15, 0x3e928af3
	s_mov_b32 s17, 0x3e5ade15
	s_mov_b32 s19, 0x3ec71dee
	s_mov_b32 s21, 0x3efa0199
	s_mov_b32 s23, 0x3f2a01a0
	s_mov_b32 s25, 0x3f56c16c
	s_mov_b32 s27, 0x3f811111
	s_mov_b32 s29, 0x3fa55555
	s_mov_b32 s31, 0x3fc55555
	s_mov_b32 s35, 0x3fe00000
	s_lshl_b64 s[36:37], s[4:5], 3
	s_mov_b64 s[38:39], s[6:7]
.LBB2_6:                                ; %.lr.ph56
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[11:12], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[11:12], v[11:12], -v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[13:14], v[11:12], s[8:9]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[11:12]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[11:12]
	v_rndne_f64_e32 v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[13:14], s[10:11], v[11:12]
	v_cvt_i32_f64_e32 v19, v[13:14]
	v_fma_f64 v[15:16], v[13:14], s[12:13], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], s[16:17], s[14:15]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[20:21]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[24:25]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[28:29]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[34:35]
	v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
	v_ldexp_f64 v[13:14], v[13:14], v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, 0x7ff00000, v14, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_add_u32 s38, s38, -1
	v_cndmask_b32_e32 v11, 0, v13, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, s36
	v_cndmask_b32_e64 v12, 0, v14, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s37, v9, vcc_lo
	s_addc_u32 s39, s39, -1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[11:12]
	s_cmp_eq_u64 s[38:39], 0
	s_cbranch_scc0 .LBB2_6
.LBB2_7:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_frexp_mant_f64_e32 v[8:9], v[6:7]
	s_mov_b32 s1, 0x3fe55555
	s_mov_b32 s0, 0x55555555
	s_mov_b32 s8, 0x6b47b09a
	s_mov_b32 s10, 0xbf559e2b
	s_mov_b32 s9, 0x3fc38538
	s_mov_b32 s11, 0x3fc3ab76
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[8:9]
	s_mov_b32 s0, 0x55555780
	v_cndmask_b32_e64 v11, 0, 1, vcc_lo
	v_ldexp_f64 v[8:9], v[8:9], v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[8:9], 1.0
	v_add_f64 v[17:18], v[8:9], -1.0
	v_rcp_f64_e32 v[13:14], v[11:12]
	v_add_f64 v[19:20], v[11:12], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[19:20]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[15:16], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[15:16], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	v_mul_f64 v[21:22], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[15:16], v[11:12], -v[21:22]
	v_fma_f64 v[8:9], v[15:16], v[8:9], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[21:22], v[8:9]
	v_add_f64 v[19:20], v[17:18], -v[11:12]
	v_add_f64 v[21:22], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	v_add_f64 v[8:9], v[21:22], -v[8:9]
	v_frexp_exp_i32_f64_e32 v21, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[17:18], -v[11:12]
	v_add_f64 v[8:9], v[8:9], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[19:20], v[8:9]
	v_mul_f64 v[8:9], v[13:14], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[15:16], v[8:9]
	v_mul_f64 v[13:14], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[17:18], v[13:14], s[10:11], s[8:9]
	s_mov_b32 s8, 0xd7f4df2e
	s_mov_b32 s9, 0x3fc7474d
	v_mul_f64 v[19:20], v[11:12], v[13:14]
	s_mov_b32 s11, 0x3c7abc9e
	s_mov_b32 s10, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[8:9]
	s_mov_b32 s8, 0x16291751
	s_mov_b32 s9, 0x3fcc71c0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[8:9]
	s_mov_b32 s8, 0x9b27acf1
	s_mov_b32 s9, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[8:9]
	s_mov_b32 s8, 0x998ef7b6
	s_mov_b32 s9, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[8:9]
	s_mov_b32 s9, 0x3fe62e42
	s_mov_b32 s8, 0xfefa39ef
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[13:14], v[17:18], s[0:1]
	v_ldexp_f64 v[17:18], v[11:12], 1
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	v_mul_f64 v[13:14], v[19:20], v[13:14]
	v_subrev_co_ci_u32_e32 v19, vcc_lo, 0, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], -v[11:12]
	v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x204
	v_cvt_f64_i32_e32 v[19:20], v19
	v_add_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[8:9], v[8:9], 1
	v_mul_f64 v[21:22], v[19:20], s[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], -v[17:18]
	v_fma_f64 v[17:18], v[19:20], s[8:9], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	v_fma_f64 v[13:14], v[19:20], s[10:11], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[11:12]
	v_add_f64 v[11:12], v[21:22], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[15:16], v[8:9]
	v_add_f64 v[21:22], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[11:12], v[17:18]
	v_add_f64 v[15:16], v[17:18], -v[15:16]
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[19:20], -v[11:12]
	v_add_f64 v[8:9], v[8:9], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[19:20], -v[23:24]
	v_add_f64 v[15:16], v[17:18], -v[23:24]
	v_add_f64 v[17:18], v[13:14], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[25:26]
	v_add_f64 v[11:12], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[17:18], -v[13:14]
	v_add_f64 v[11:12], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], -v[15:16]
	v_add_f64 v[8:9], v[8:9], -v[15:16]
	v_add_f64 v[21:22], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[17:18]
	v_add_f64 v[15:16], v[21:22], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[13:14]
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], v[11:12]
	v_add_f64 v[8:9], v[21:22], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v8, v6 :: v_dual_cndmask_b32 v9, v9, v7
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[6:7]
	v_cndmask_b32_e32 v9, 0x7ff80000, v9, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[6:7]
	v_cndmask_b32_e32 v9, 0xfff00000, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	s_cbranch_vccnz .LBB2_10
; %bb.8:                                ; %.lr.ph62.preheader
	s_mov_b32 s12, 0x652b82fe
	s_mov_b32 s14, 0xfca7ab0c
	s_mov_b32 s16, 0x6a5dcb37
	s_mov_b32 s18, 0x623fde64
	s_mov_b32 s20, 0x7c89e6b0
	s_mov_b32 s22, 0x14761f6e
	s_mov_b32 s24, 0x1852b7b0
	s_mov_b32 s26, 0x11122322
	s_mov_b32 s28, 0x555502a1
	s_mov_b32 s30, 0x55555511
	s_mov_b32 s34, 11
	s_mov_b32 s13, 0x3ff71547
	s_mov_b32 s15, 0x3e928af3
	s_mov_b32 s17, 0x3e5ade15
	s_mov_b32 s19, 0x3ec71dee
	s_mov_b32 s21, 0x3efa0199
	s_mov_b32 s23, 0x3f2a01a0
	s_mov_b32 s25, 0x3f56c16c
	s_mov_b32 s27, 0x3f811111
	s_mov_b32 s29, 0x3fa55555
	s_mov_b32 s31, 0x3fc55555
	s_mov_b32 s35, 0x3fe00000
	s_lshl_b64 s[4:5], s[4:5], 3
	s_mov_b32 s9, 0xbfe62e42
	s_mov_b32 s11, 0xbc7abc9e
.LBB2_9:                                ; %.lr.ph62
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[6:7], -v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[8:9], v[6:7], s[12:13]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[6:7]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[6:7]
	v_rndne_f64_e32 v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[8:9], s[8:9], v[6:7]
	v_cvt_i32_f64_e32 v14, v[8:9]
	v_fma_f64 v[10:11], v[8:9], s[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], s[16:17], s[14:15]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[20:21]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[24:25]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[28:29]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[34:35]
	v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[10:11], v[12:13], 1.0
	v_ldexp_f64 v[8:9], v[8:9], v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, 0x7ff00000, v9, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_add_u32 s6, s6, -1
	v_cndmask_b32_e32 v6, 0, v8, vcc_lo
	s_addc_u32 s7, s7, -1
	v_cndmask_b32_e64 v7, 0, v9, s0
	s_cmp_eq_u64 s[6:7], 0
	global_store_b64 v[2:3], v[6:7], off
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_cbranch_scc0 .LBB2_9
.LBB2_10:                               ; %._crit_edge63
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b64 v[0:1], v[4:5], off
.LBB2_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7paso_e2PdS_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z7paso_e2PdS_mm, .Lfunc_end2-_Z7paso_e2PdS_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2144
; NumSgprs: 42
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20paso_e_verosimilitudPdS_m ; -- Begin function _Z20paso_e_verosimilitudPdS_m
	.globl	_Z20paso_e_verosimilitudPdS_m
	.p2align	8
	.type	_Z20paso_e_verosimilitudPdS_m,@function
_Z20paso_e_verosimilitudPdS_m:          ; @_Z20paso_e_verosimilitudPdS_m
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s16, s[0:1], 0x20
	s_mov_b32 s13, 0
	s_mov_b32 s14, s15
	s_mov_b32 s15, s13
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
	s_lshl_b64 s[0:1], s[14:15], 8
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v8, 3, v0
	v_add_co_u32 v2, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s12, s10
	v_cmpx_gt_u64_e64 s[8:9], v[2:3]
	s_cbranch_execz .LBB3_6
; %bb.1:                                ; %.lr.ph.i.preheader
	s_lshl_b64 s[18:19], s[14:15], 11
	s_lshl_b64 s[2:3], s[12:13], 8
	s_add_u32 s0, s4, s18
	s_addc_u32 s4, s5, s19
	v_add_co_u32 v6, s0, s0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, null, s4, 0, s0
	v_mov_b32_e32 v4, 0
	v_add_co_u32 v6, vcc_lo, 0x400, v6
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_lshl_b64 s[4:5], s[12:13], 11
	s_mov_b32 s17, s13
.LBB3_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[9:10], v[6:7], off offset:-1024
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[9:10]
	v_add_co_u32 v9, vcc_lo, 0x80, v2
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[8:9], v[9:10]
	s_cbranch_execz .LBB3_4
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	global_load_b64 v[9:10], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[9:10]
.LBB3_4:                                ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v2, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v6, s0, v6, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	v_cmp_le_u64_e32 vcc_lo, s[8:9], v[2:3]
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB3_2
; %bb.5:                                ; %Flow25
	s_or_b32 exec_lo, exec_lo, s17
.LBB3_6:                                ; %Flow26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshl_add_u32 v9, v0, 3, 8
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_gt_u32_e64 s0, 64, v0
	v_cmp_ne_u32_e32 vcc_lo, -1, v9
	v_cndmask_b32_e32 v2, 0, v9, vcc_lo
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB3_8
; %bb.7:
	v_add3_u32 v6, 8, v8, 0x200
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_8:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u32_e64 s1, 32, v0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_10
; %bb.9:
	v_add3_u32 v6, 8, v8, 0x100
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 0x80, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 64, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 32, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 16, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 8, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_10:                               ; %_Z13reducirBloqueILm128EEvPVddm.exit.i
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_eq_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_12
; %bb.11:
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v4, 8 :: v_dual_mov_b32 v5, s5
	s_mul_i32 s8, s11, s10
	s_lshl_b64 s[4:5], s[14:15], 3
	s_mul_i32 s10, s8, s16
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, s10
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	s_add_u32 s4, s6, s4
	s_addc_u32 s5, s7, s5
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, contadorBloques@rel32@lo+4
	s_addc_u32 s9, s9, contadorBloques@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	global_store_b64 v6, v[4:5], s[4:5]
	s_waitcnt_vscnt null, 0x0
	buffer_gl1_inv
	buffer_gl0_inv
	global_atomic_inc_u32 v5, v6, v7, s[8:9] glc
	s_add_u32 s4, s10, -1
	s_addc_u32 s5, 0, -1
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	ds_store_b8 v6, v4
.LBB3_12:
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v4, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB3_23
; %bb.13:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e64 s12, v0
	s_cbranch_execz .LBB3_17
; %bb.14:                               ; %.lr.ph.i.i.i.preheader
	v_mov_b32_e32 v4, 0
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 0x80, v0
	s_mov_b32 s4, 0
.LBB3_15:                               ; %.lr.ph.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u64_e32 vcc_lo, s[12:13], v[6:7]
	global_load_b64 v[0:1], v[0:1], off
	s_or_b32 s4, vcc_lo, s4
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[0:1]
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	v_add_nc_u32_e32 v6, 0x80, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB3_15
; %bb.16:                               ; %Flow22
	s_or_b32 exec_lo, exec_lo, s4
.LBB3_17:                               ; %Flow23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB3_19
; %bb.18:
	v_add3_u32 v0, 8, v8, 0x200
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cndmask_b32_e64 v1, 0, s5, vcc_lo
	flat_load_b64 v[0:1], v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[0:1]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_19:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB3_21
; %bb.20:
	v_add3_u32 v0, 8, v8, 0x100
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v0
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cndmask_b32_e64 v1, 0, s5, vcc_lo
	flat_load_b64 v[0:1], v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[0:1], v[4:5], v[0:1]
	v_add_nc_u32_e32 v4, 0x80, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[0:1] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	v_add_nc_u32_e32 v4, 64, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[0:1] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	v_add_nc_u32_e32 v4, 32, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[0:1] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	v_add_nc_u32_e32 v4, 16, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[0:1] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	v_add_nc_u32_e32 v4, 8, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[0:1] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	flat_store_b64 v[2:3], v[0:1] dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_21:                               ; %_Z13reducirBloqueILm128EEvPVddm.exit.i.i.i
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB3_23
; %bb.22:                               ; %_ZZ20paso_e_verosimilitudPdS_mENKUlvE0_clEv.exit.i
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, 8 :: v_dual_mov_b32 v1, s1
	v_mov_b32_e32 v2, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, contadorBloques@rel32@lo+4
	s_addc_u32 s1, s1, contadorBloques@rel32@hi+12
	flat_load_b64 v[0:1], v[0:1] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_clause 0x1
	global_store_b64 v2, v[0:1], s[6:7]
	global_store_b32 v2, v2, s[0:1]
.LBB3_23:                               ; %_Z7reducirILm128EZ20paso_e_verosimilitudPdS0_mEUlmE_Z20paso_e_verosimilitudS0_S0_mEUlvE_Z20paso_e_verosimilitudS0_S0_mEUlvE0_EvT0_T1_T2_mPVdm.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20paso_e_verosimilitudPdS_m
		.amdhsa_group_segment_fixed_size 8
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z20paso_e_verosimilitudPdS_m, .Lfunc_end3-_Z20paso_e_verosimilitudPdS_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1780
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6paso_mPdS_S_m        ; -- Begin function _Z6paso_mPdS_S_m
	.globl	_Z6paso_mPdS_S_m
	.p2align	8
	.type	_Z6paso_mPdS_S_m,@function
_Z6paso_mPdS_S_m:                       ; @_Z6paso_mPdS_S_m
; %bb.0:
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x20
	s_load_b32 s16, s[0:1], 0x28
	s_mov_b32 s13, 0
	s_mov_b32 s3, s15
	s_mov_b32 s15, s13
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, 0
	s_lshl_b64 s[0:1], s[14:15], 8
	v_mov_b32_e32 v5, 0
	v_add_co_u32 v2, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u64_e64 s[10:11], v[2:3]
	s_cbranch_execz .LBB4_6
; %bb.1:                                ; %.lr.ph.i
	s_mul_i32 s0, s11, s3
	s_mul_hi_u32 s2, s10, s3
	s_mul_i32 s18, s10, s3
	s_add_i32 s19, s2, s0
	s_lshl_b64 s[22:23], s[14:15], 11
	s_lshl_b64 s[20:21], s[18:19], 3
	s_lshl_b64 s[18:19], s[12:13], 8
	v_lshlrev_b32_e32 v4, 3, v0
	s_add_u32 s0, s20, s22
	s_addc_u32 s2, s21, s23
	s_add_u32 s0, s4, s0
	s_addc_u32 s2, s5, s2
	v_add_co_u32 v6, s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, null, s2, 0, s0
	v_mov_b32_e32 v4, 0
	v_add_co_u32 v6, vcc_lo, 0x400, v6
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_lshl_b64 s[4:5], s[12:13], 11
	s_mov_b32 s2, s13
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[8:9], v[6:7], off offset:-1024
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_co_u32 v8, vcc_lo, 0x80, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[10:11], v[8:9]
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	global_load_b64 v[8:9], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[8:9]
.LBB4_4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v2, vcc_lo, v2, s18
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	v_add_co_u32 v6, s0, v6, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[2:3]
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB4_2
; %bb.5:                                ; %Flow36
	s_or_b32 exec_lo, exec_lo, s2
.LBB4_6:                                ; %Flow37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshl_add_u32 v8, v0, 3, 8
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_gt_u32_e64 s0, 64, v0
	v_cmp_ne_u32_e32 vcc_lo, -1, v8
	v_cndmask_b32_e32 v2, 0, v8, vcc_lo
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB4_8
; %bb.7:
	v_lshlrev_b32_e32 v6, 3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, 8, v6, 0x200
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_8:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u32_e64 s1, 32, v0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB4_10
; %bb.9:
	v_lshlrev_b32_e32 v6, 3, v0
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, 8, v6, 0x100
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 0x80, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 64, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 32, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 16, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 8, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_10:                               ; %_Z13reducirBloqueILm128EEvPVddm.exit.i
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_eq_u32_e64 s2, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB4_12
; %bb.11:
	s_mov_b64 s[18:19], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v4, 8 :: v_dual_mov_b32 v5, s19
	s_mul_hi_u32 s19, s12, s3
	s_mul_i32 s18, s12, s3
	s_mul_i32 s3, s12, s16
	s_lshl_b64 s[18:19], s[18:19], 3
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	s_add_u32 s5, s6, s18
	s_addc_u32 s17, s7, s19
	s_lshl_b64 s[14:15], s[14:15], 3
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, s3
	s_add_u32 s14, s5, s14
	s_addc_u32 s15, s17, s15
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, contadorBloques@rel32@lo+4
	s_addc_u32 s19, s19, contadorBloques@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	global_store_b64 v6, v[4:5], s[14:15]
	s_waitcnt_vscnt null, 0x0
	buffer_gl1_inv
	buffer_gl0_inv
	global_atomic_inc_u32 v5, v6, v7, s[18:19] glc
	s_add_u32 s14, s3, -1
	s_addc_u32 s15, 0, -1
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, s[14:15], v[5:6]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	ds_store_b8 v6, v4
.LBB4_12:
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v4, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB4_28
; %bb.13:
	s_cmp_eq_u32 s16, 0
	s_mov_b32 s17, 0
	s_cbranch_scc1 .LBB4_26
; %bb.14:                               ; %.lr.ph.i.i
	v_cvt_f64_u32_e32 v[4:5], s11
	v_cvt_f64_u32_e32 v[6:7], s10
	v_add_nc_u32_e32 v14, 64, v8
	v_add_nc_u32_e32 v9, 0x200, v8
	v_add_nc_u32_e32 v12, 0x80, v8
	s_mov_b64 s[10:11], src_shared_base
	v_add_nc_u32_e32 v10, 0x100, v8
	v_add_nc_u32_e32 v16, 32, v8
	v_cmp_ne_u32_e32 vcc_lo, -1, v9
	v_add_nc_u32_e32 v18, 16, v8
	v_add_nc_u32_e32 v8, 8, v8
	v_cmp_gt_u32_e64 s3, s12, v0
	v_dual_mov_b32 v28, 0 :: v_dual_add_nc_u32 v27, 0x80, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s5, -1, v8
	v_cndmask_b32_e64 v20, 0, v8, s5
	v_cndmask_b32_e64 v21, 0, s11, s5
	v_mov_b32_e32 v8, 8
	v_ldexp_f64 v[4:5], v[4:5], 32
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_cndmask_b32_e32 v6, 0, v9, vcc_lo
	v_cndmask_b32_e64 v7, 0, s11, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v12
	v_mov_b32_e32 v9, s11
	v_cmp_ne_u32_e64 s4, -1, v10
	v_cndmask_b32_e32 v12, 0, v12, vcc_lo
	v_cndmask_b32_e64 v13, 0, s11, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v14
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v10, 0, v10, s4
	v_cndmask_b32_e64 v11, 0, s11, s4
	v_cmp_ne_u32_e64 s4, -1, v16
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_cndmask_b32_e64 v15, 0, s11, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v18
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v16, 0, v16, s4
	v_cndmask_b32_e64 v17, 0, s11, s4
	s_mov_b64 s[4:5], 0
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	v_cndmask_b32_e64 v19, 0, s11, vcc_lo
.LBB4_15:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_17 Depth 2
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_and_saveexec_b32 s10, s3
	s_cbranch_execz .LBB4_19
; %bb.16:                               ; %.lr.ph.i.i.i
                                        ;   in Loop: Header=BB4_15 Depth=1
	s_mul_i32 s11, s5, s12
	s_mul_hi_u32 s15, s4, s12
	s_mul_i32 s14, s4, s12
	s_add_i32 s15, s15, s11
	v_mov_b32_e32 v22, 0
	v_dual_mov_b32 v26, v1 :: v_dual_mov_b32 v25, v0
	s_lshl_b64 s[14:15], s[14:15], 3
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v24, v27
	s_add_u32 s11, s6, s14
	s_addc_u32 s15, s7, s15
	s_mov_b32 s14, 0
.LBB4_17:                               ;   Parent Loop BB4_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], 3, v[25:26]
	v_add_co_u32 v25, vcc_lo, s11, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v26, vcc_lo, s15, v26, vcc_lo
	global_load_b64 v[25:26], v[25:26], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[25:26]
	v_ashrrev_i32_e32 v25, 31, v24
	v_cmp_le_u64_e32 vcc_lo, s[12:13], v[24:25]
	v_mov_b32_e32 v26, v25
	v_dual_mov_b32 v25, v24 :: v_dual_add_nc_u32 v24, 0x80, v24
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB4_17
; %bb.18:                               ; %Flow31
                                        ;   in Loop: Header=BB4_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB4_19:                               ; %Flow32
                                        ;   in Loop: Header=BB4_15 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB4_21
; %bb.20:                               ;   in Loop: Header=BB4_15 Depth=1
	flat_load_b64 v[24:25], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_21:                               ;   in Loop: Header=BB4_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s10, s1
	s_cbranch_execz .LBB4_23
; %bb.22:                               ;   in Loop: Header=BB4_15 Depth=1
	flat_load_b64 v[24:25], v[10:11] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[24:25], v[12:13] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[24:25], v[14:15] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[24:25], v[16:17] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[24:25], v[18:19] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[24:25], v[20:21] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	flat_store_b64 v[2:3], v[22:23] dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_23:                               ; %_Z13reducirBloqueILm128EEvPVddm.exit.i.i.i
                                        ;   in Loop: Header=BB4_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB4_25
; %bb.24:                               ; %_Z12reducirFinalILm128EZZ6paso_mPdS0_S0_mENKUlvE0_clEvEUlmE_ZZ6paso_mS0_S0_S0_mENKS1_clEvEUlvE_EvT0_T1_PVdm.exit.i.i
                                        ;   in Loop: Header=BB4_15 Depth=1
	flat_load_b64 v[22:23], v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	s_lshl_b64 s[14:15], s[4:5], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s8, s14
	s_addc_u32 s19, s9, s15
	s_add_u32 s14, s6, s14
	s_addc_u32 s15, s7, s15
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[24:25], null, v[4:5], v[4:5], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[29:30], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[31:32], -v[24:25], v[29:30], 1.0
	v_fma_f64 v[29:30], v[29:30], v[31:32], v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], -v[24:25], v[29:30], 1.0
	v_fma_f64 v[29:30], v[29:30], v[31:32], v[29:30]
	v_div_scale_f64 v[31:32], vcc_lo, v[22:23], v[4:5], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[33:34], v[31:32], v[29:30]
	v_fma_f64 v[24:25], -v[24:25], v[33:34], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[24:25], v[24:25], v[29:30], v[33:34]
	v_div_fixup_f64 v[24:25], v[24:25], v[4:5], v[22:23]
	s_clause 0x1
	global_store_b64 v28, v[22:23], s[14:15]
	global_store_b64 v28, v[24:25], s[18:19]
.LBB4_25:                               ; %.critedge.i.i
                                        ;   in Loop: Header=BB4_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], s[16:17]
	s_cbranch_scc1 .LBB4_15
.LBB4_26:                               ; %_ZZ6paso_mPdS_S_mENKUlvE0_clEv.exit.i
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB4_28
; %bb.27:
	v_mov_b32_e32 v0, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, contadorBloques@rel32@lo+4
	s_addc_u32 s1, s1, contadorBloques@rel32@hi+12
	global_store_b32 v0, v0, s[0:1]
.LBB4_28:                               ; %_Z7reducirILm128EZ6paso_mPdS0_S0_mEUlmE_Z6paso_mS0_S0_S0_mEUlvE_Z6paso_mS0_S0_S0_mEUlvE0_EvT0_T1_T2_mPVdm.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6paso_mPdS_S_m
		.amdhsa_group_segment_fixed_size 8
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z6paso_mPdS_S_m, .Lfunc_end4-_Z6paso_mPdS_S_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2084
; NumSgprs: 26
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7paso_m2PdS_S_S_m     ; -- Begin function _Z7paso_m2PdS_S_S_m
	.globl	_Z7paso_m2PdS_S_S_m
	.p2align	8
	.type	_Z7paso_m2PdS_S_S_m,@function
_Z7paso_m2PdS_S_S_m:                    ; @_Z7paso_m2PdS_S_S_m
; %bb.0:
	s_clause 0x2
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s12, s[0:1], 0x30
	s_mov_b32 s21, 0
	s_mov_b32 s22, s13
	s_mov_b32 s23, s21
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
	s_lshl_b64 s[0:1], s[22:23], 8
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v10, 3, v0
	v_add_co_u32 v2, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s20, s18
	v_cmpx_gt_u64_e64 s[16:17], v[2:3]
	s_cbranch_execz .LBB5_6
; %bb.1:                                ; %.lr.ph.i
	s_mul_i32 s0, s15, s17
	s_mul_hi_u32 s3, s15, s16
	s_mul_i32 s2, s15, s16
	s_add_i32 s3, s3, s0
	s_mul_i32 s0, s14, s17
	s_lshl_b64 s[24:25], s[2:3], 3
	s_lshl_b64 s[2:3], s[20:21], 8
	s_add_u32 s13, s4, s24
	s_mul_hi_u32 s4, s14, s16
	s_addc_u32 s24, s5, s25
	s_add_i32 s5, s4, s0
	s_mul_i32 s4, s14, s16
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[4:5], s[4:5], 3
	v_mov_b32_e32 v5, 0
	s_add_u32 s6, s6, s4
	s_addc_u32 s7, s7, s5
	s_lshl_b64 s[4:5], s[22:23], 11
	s_mov_b32 s25, s21
	v_add_co_u32 v11, s0, s4, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, null, s5, 0, s0
	s_lshl_b64 s[4:5], s[20:21], 11
.LBB5_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s13, v11
	v_add_co_ci_u32_e32 v7, vcc_lo, s24, v12, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v12, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b64 v[13:14], v[6:7], off
	global_load_b64 v[15:16], v[8:9], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[4:5], v[13:14], v[15:16], v[4:5]
	v_add_co_u32 v13, vcc_lo, 0x80, v2
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[16:17], v[13:14]
	s_cbranch_execz .LBB5_4
; %bb.3:                                ;   in Loop: Header=BB5_2 Depth=1
	global_load_b64 v[6:7], v[6:7], off offset:1024
	global_load_b64 v[8:9], v[8:9], off offset:1024
	s_waitcnt vmcnt(0)
	v_fma_f64 v[4:5], v[6:7], v[8:9], v[4:5]
.LBB5_4:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v2, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v11, s0, v11, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v12, s0, s5, v12, s0
	v_cmp_le_u64_e32 vcc_lo, s[16:17], v[2:3]
	s_or_b32 s25, vcc_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB5_2
; %bb.5:                                ; %Flow58
	s_or_b32 exec_lo, exec_lo, s25
.LBB5_6:                                ; %Flow59
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshl_add_u32 v13, v0, 3, 8
	s_mov_b64 s[0:1], src_shared_base
	v_cmp_gt_u32_e64 s0, 64, v0
	v_cmp_ne_u32_e32 vcc_lo, -1, v13
	v_cndmask_b32_e32 v2, 0, v13, vcc_lo
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB5_8
; %bb.7:
	v_add3_u32 v6, 8, v10, 0x200
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s1, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_8:
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u32_e64 s1, 32, v0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB5_10
; %bb.9:
	v_add3_u32 v6, 8, v10, 0x100
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 0x80, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 64, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 32, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 16, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_nc_u32_e32 v6, 8, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s5, vcc_lo
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	flat_store_b64 v[2:3], v[4:5] dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_10:                               ; %_Z13reducirBloqueILm128EEvPVddm.exit.i
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_eq_u32_e64 s2, 0, v0
	s_mov_b32 s5, 0
	s_mov_b32 s4, s19
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB5_12
; %bb.11:
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v4, 8 :: v_dual_mov_b32 v5, s7
	s_mul_i32 s6, s4, s15
	s_mul_hi_u32 s15, s4, s15
	s_mul_hi_u32 s17, s6, s20
	s_mul_i32 s15, s15, s20
	flat_load_b64 v[4:5], v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	s_mul_i32 s16, s6, s20
	s_add_i32 s17, s17, s15
	s_mul_hi_u32 s7, s20, s14
	s_mul_i32 s6, s20, s14
	s_lshl_b64 s[14:15], s[16:17], 3
	s_mul_i32 s13, s19, s12
	s_add_u32 s14, s10, s14
	s_addc_u32 s15, s11, s15
	s_lshl_b64 s[6:7], s[6:7], 3
	s_mul_i32 s13, s13, s18
	s_add_u32 s14, s14, s6
	s_addc_u32 s15, s15, s7
	s_lshl_b64 s[6:7], s[22:23], 3
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, s13
	s_add_u32 s6, s14, s6
	s_addc_u32 s7, s15, s7
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, contadorBloques@rel32@lo+4
	s_addc_u32 s15, s15, contadorBloques@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	global_store_b64 v6, v[4:5], s[6:7]
	s_waitcnt_vscnt null, 0x0
	buffer_gl1_inv
	buffer_gl0_inv
	global_atomic_inc_u32 v5, v6, v7, s[14:15] glc
	s_add_u32 s6, s13, -1
	s_addc_u32 s7, 0, -1
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, s[6:7], v[5:6]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	ds_store_b8 v6, v4
.LBB5_12:
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_u8 v4, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB5_31
; %bb.13:
	s_cmp_eq_u32 s12, 0
	s_mov_b32 s13, 0
	s_cbranch_scc1 .LBB5_29
; %bb.14:                               ; %.preheader.lr.ph.i.i
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v5, s7 :: v_dual_add_nc_u32 v4, 0x200, v13
	v_add_nc_u32_e32 v10, 0x80, v13
	v_add_nc_u32_e32 v14, 32, v13
	v_add_nc_u32_e32 v18, 8, v13
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_add_nc_u32_e32 v7, 0x100, v13
	v_cmp_gt_u64_e64 s6, s[4:5], 1
	v_mov_b32_e32 v26, 0
	s_mov_b64 s[14:15], 0
	v_cndmask_b32_e32 v6, 0, v4, vcc_lo
	v_cmp_ne_u32_e64 s3, -1, v7
	v_add_nc_u32_e32 v4, 64, v13
	s_and_b32 s6, s6, exec_lo
	s_cselect_b32 s6, s4, 1
	s_mov_b64 s[22:23], s[4:5]
	v_cndmask_b32_e64 v8, 0, v7, s3
	v_cndmask_b32_e64 v7, 0, s7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v10
	v_cndmask_b32_e64 v9, 0, s7, s3
	v_cmp_ne_u32_e64 s3, -1, v14
	v_dual_cndmask_b32 v10, 0, v10 :: v_dual_add_nc_u32 v25, 0x80, v0
	v_cndmask_b32_e64 v11, 0, s7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0, v14, s3
	v_cndmask_b32_e64 v15, 0, s7, s3
	v_cmp_ne_u32_e64 s3, -1, v18
	v_cndmask_b32_e32 v12, 0, v4, vcc_lo
	v_add_nc_u32_e32 v4, 16, v13
	v_cndmask_b32_e64 v13, 0, s7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v18, 0, v18, s3
	v_cndmask_b32_e64 v19, 0, s7, s3
	v_cmp_gt_u32_e64 s3, s20, v0
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v16, 0, v4, vcc_lo
	v_cndmask_b32_e64 v17, 0, s7, vcc_lo
	v_mov_b32_e32 v4, 8
	s_cselect_b32 s7, 0, 0
.LBB5_15:                               ; %.preheader.i.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_17 Depth 2
                                        ;       Child Loop BB5_19 Depth 3
	s_cmp_eq_u64 s[22:23], 0
	s_mov_b64 s[24:25], 0
	s_cbranch_scc1 .LBB5_28
; %bb.16:                               ; %.lr.ph.i.i
                                        ;   in Loop: Header=BB5_15 Depth=1
	s_mul_i32 s16, s15, s4
	s_mul_hi_u32 s17, s14, s4
	s_mul_i32 s18, s15, s20
	s_add_i32 s17, s17, s16
	s_mul_i32 s16, s14, s4
	s_mul_hi_u32 s19, s14, s20
	s_lshl_b64 s[16:17], s[16:17], 3
	s_add_i32 s26, s19, s18
	s_add_u32 s27, s10, s16
	s_addc_u32 s28, s11, s17
	s_lshl_b64 s[16:17], s[14:15], 3
	s_mul_i32 s29, s14, s20
	s_add_u32 s16, s8, s16
	s_addc_u32 s17, s9, s17
	s_mov_b64 s[18:19], 0
.LBB5_17:                               ;   Parent Loop BB5_15 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB5_19 Depth 3
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_and_saveexec_b32 s24, s3
	s_cbranch_execz .LBB5_21
; %bb.18:                               ; %.lr.ph.i.i.i
                                        ;   in Loop: Header=BB5_17 Depth=2
	s_mul_i32 s23, s29, s23
	s_mul_hi_u32 s25, s29, s22
	s_mul_i32 s30, s26, s22
	s_add_i32 s23, s25, s23
	s_mul_i32 s22, s29, s22
	s_add_i32 s23, s23, s30
	s_mul_i32 s25, s19, s20
	s_mul_hi_u32 s30, s18, s20
	s_lshl_b64 s[22:23], s[22:23], 3
	s_add_i32 s31, s30, s25
	s_mul_i32 s30, s18, s20
	s_add_u32 s25, s10, s22
	v_mov_b32_e32 v20, 0
	v_dual_mov_b32 v24, v1 :: v_dual_mov_b32 v23, v0
	s_addc_u32 s33, s11, s23
	s_lshl_b64 s[22:23], s[30:31], 3
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, v25
	s_add_u32 s22, s25, s22
	s_addc_u32 s25, s33, s23
	s_mov_b32 s23, 0
.LBB5_19:                               ;   Parent Loop BB5_15 Depth=1
                                        ;     Parent Loop BB5_17 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 3, v[23:24]
	v_add_co_u32 v23, vcc_lo, s22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v24, vcc_lo, s25, v24, vcc_lo
	global_load_b64 v[23:24], v[23:24], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[23:24]
	v_ashrrev_i32_e32 v23, 31, v22
	v_cmp_le_u64_e32 vcc_lo, s[20:21], v[22:23]
	v_mov_b32_e32 v24, v23
	v_dual_mov_b32 v23, v22 :: v_dual_add_nc_u32 v22, 0x80, v22
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB5_19
; %bb.20:                               ; %Flow51
                                        ;   in Loop: Header=BB5_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
.LBB5_21:                               ; %Flow52
                                        ;   in Loop: Header=BB5_17 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s24
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB5_23
; %bb.22:                               ;   in Loop: Header=BB5_17 Depth=2
	flat_load_b64 v[22:23], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_23:                               ;   in Loop: Header=BB5_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s22, s1
	s_cbranch_execz .LBB5_25
; %bb.24:                               ;   in Loop: Header=BB5_17 Depth=2
	flat_load_b64 v[22:23], v[8:9] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[22:23], v[10:11] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[22:23], v[12:13] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[22:23], v[14:15] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[22:23], v[16:17] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[22:23], v[18:19] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[22:23]
	flat_store_b64 v[2:3], v[20:21] dlc
	s_waitcnt_vscnt null, 0x0
.LBB5_25:                               ; %_Z13reducirBloqueILm128EEvPVddm.exit.i.i.i
                                        ;   in Loop: Header=BB5_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_and_saveexec_b32 s22, s2
	s_cbranch_execz .LBB5_27
; %bb.26:                               ; %_Z12reducirFinalILm128EZZ7paso_m2PdS0_S0_S0_mENKUlvE0_clEvEUlmE_ZZ7paso_m2S0_S0_S0_S0_mENKS1_clEvEUlvE_EvT0_T1_PVdm.exit.i.i
                                        ;   in Loop: Header=BB5_17 Depth=2
	flat_load_b64 v[20:21], v[4:5] glc dlc
	s_waitcnt vmcnt(0)
	s_lshl_b64 s[24:25], s[18:19], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s27, s24
	s_addc_u32 s25, s28, s25
	s_waitcnt lgkmcnt(0)
	global_store_b64 v26, v[20:21], s[24:25]
	global_load_b64 v[22:23], v26, s[16:17]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[27:28], null, v[22:23], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[29:30], v[27:28]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[31:32], -v[27:28], v[29:30], 1.0
	v_fma_f64 v[29:30], v[29:30], v[31:32], v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], -v[27:28], v[29:30], 1.0
	v_fma_f64 v[29:30], v[29:30], v[31:32], v[29:30]
	v_div_scale_f64 v[31:32], vcc_lo, v[20:21], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[33:34], v[31:32], v[29:30]
	v_fma_f64 v[27:28], -v[27:28], v[33:34], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[27:28], v[27:28], v[29:30], v[33:34]
	v_div_fixup_f64 v[20:21], v[27:28], v[22:23], v[20:21]
	global_store_b64 v26, v[20:21], s[24:25]
.LBB5_27:                               ; %.critedge.i.i
                                        ;   in Loop: Header=BB5_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_mov_b64 s[24:25], s[4:5]
	s_cmp_eq_u64 s[18:19], s[6:7]
	s_mov_b64 s[22:23], s[4:5]
	s_cbranch_scc0 .LBB5_17
.LBB5_28:                               ; %Flow54
                                        ;   in Loop: Header=BB5_15 Depth=1
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_mov_b64 s[22:23], s[24:25]
	s_cmp_eq_u64 s[14:15], s[12:13]
	s_cbranch_scc0 .LBB5_15
.LBB5_29:                               ; %_ZZ7paso_m2PdS_S_S_mENKUlvE0_clEv.exit.i
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB5_31
; %bb.30:
	v_mov_b32_e32 v0, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, contadorBloques@rel32@lo+4
	s_addc_u32 s1, s1, contadorBloques@rel32@hi+12
	global_store_b32 v0, v0, s[0:1]
.LBB5_31:                               ; %_Z7reducirILm128EZ7paso_m2PdS0_S0_S0_mEUlmE_Z7paso_m2S0_S0_S0_S0_mEUlvE_Z7paso_m2S0_S0_S0_S0_mEUlvE0_EvT0_T1_T2_mPVdm.exit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7paso_m2PdS_S_S_m
		.amdhsa_group_segment_fixed_size 8
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 34
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z7paso_m2PdS_S_S_m, .Lfunc_end5-_Z7paso_m2PdS_S_S_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2300
; NumSgprs: 36
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18paso_m_covarianzasPdS_S_S_mm ; -- Begin function _Z18paso_m_covarianzasPdS_S_S_mm
	.globl	_Z18paso_m_covarianzasPdS_S_S_mm
	.p2align	8
	.type	_Z18paso_m_covarianzasPdS_S_S_mm,@function
_Z18paso_m_covarianzasPdS_S_S_mm:       ; @_Z18paso_m_covarianzasPdS_S_S_mm
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	s_add_u32 s0, s0, 48
	s_mov_b32 s2, s13
	s_mov_b32 s13, 0
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s18
	v_cvt_f32_u32_e32 v2, s19
	s_sub_u32 s21, 0, s18
	s_subb_u32 s22, 0, s19
	s_mul_hi_u32 s29, s15, s16
	s_mul_i32 s31, s15, s19
	v_fmamk_f32 v1, v2, 0x4f800000, v1
	s_mul_hi_u32 s33, s15, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	v_mul_f32_e32 v2, 0x2f800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v2, v2
	v_fmamk_f32 v1, v2, 0xcf800000, v1
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s20, v1
	s_mul_i32 s23, s21, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s25, s21, s20
	s_mul_i32 s24, s22, s20
	s_add_i32 s23, s25, s23
	s_mul_i32 s26, s21, s20
	s_add_i32 s23, s23, s24
	s_mul_hi_u32 s25, s20, s26
	s_mul_hi_u32 s27, s12, s26
	s_mul_i32 s24, s12, s26
	s_mul_hi_u32 s26, s20, s23
	s_mul_i32 s20, s20, s23
	s_mul_hi_u32 s28, s12, s23
	s_add_u32 s20, s25, s20
	s_addc_u32 s25, 0, s26
	s_add_u32 s20, s20, s24
	s_mul_i32 s23, s12, s23
	s_addc_u32 s20, s25, s27
	s_addc_u32 s24, s28, 0
	s_add_u32 s20, s20, s23
	s_addc_u32 s23, 0, s24
	v_add_co_u32 v1, s20, v1, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s20, 0
	s_mul_i32 s28, s15, s17
	s_addc_u32 s12, s12, s23
	v_readfirstlane_b32 s20, v1
	s_mul_i32 s23, s21, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s24, s21, s20
	s_mul_i32 s22, s22, s20
	s_add_i32 s23, s24, s23
	s_mul_i32 s21, s21, s20
	s_add_i32 s23, s23, s22
	s_mul_hi_u32 s24, s12, s21
	s_mul_i32 s25, s12, s21
	s_mul_hi_u32 s21, s20, s21
	s_mul_hi_u32 s26, s20, s23
	s_mul_i32 s20, s20, s23
	s_mul_hi_u32 s22, s12, s23
	s_add_u32 s20, s21, s20
	s_addc_u32 s21, 0, s26
	s_add_u32 s20, s20, s25
	s_mul_i32 s23, s12, s23
	s_addc_u32 s20, s21, s24
	s_addc_u32 s21, s22, 0
	s_add_u32 s20, s20, s23
	s_addc_u32 s21, 0, s21
	v_add_co_u32 v1, s20, v1, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s20, 0
	s_addc_u32 s12, s12, s21
	v_readfirstlane_b32 s20, v1
	s_mul_i32 s21, s14, s12
	s_mul_hi_u32 s12, s14, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s20, s14, s20
	s_add_u32 s20, s20, s21
	s_addc_u32 s12, 0, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s20, s19, s12
	s_mul_hi_u32 s21, s18, s12
	s_mul_i32 s22, s18, s12
	s_add_i32 s21, s21, s20
	v_sub_co_u32 v1, s20, s14, s22
	s_sub_i32 s22, 0, s21
	s_cmp_lg_u32 s20, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_co_u32 v2, s23, v1, s18
	s_subb_u32 s22, s22, s19
	s_cmp_lg_u32 s23, 0
	v_readfirstlane_b32 s23, v2
	s_subb_u32 s22, s22, 0
	v_mov_b32_e32 v2, 0
	s_cmp_ge_u32 s22, s19
	s_cselect_b32 s24, -1, 0
	s_cmp_ge_u32 s23, s18
	s_cselect_b32 s23, -1, 0
	s_cmp_eq_u32 s22, s19
	s_cselect_b32 s22, s23, s24
	s_add_u32 s23, s12, 1
	s_addc_u32 s24, 0, 0
	s_add_u32 s25, s12, 2
	s_addc_u32 s26, 0, 0
	s_cmp_lg_u32 s22, 0
	v_readfirstlane_b32 s22, v1
	s_cselect_b32 s23, s25, s23
	s_cselect_b32 s25, s26, s24
	s_cmp_lg_u32 s20, 0
	s_subb_u32 s24, 0, s21
	s_clause 0x1
	s_load_b64 s[20:21], s[0:1], 0x0
	s_load_b32 s30, s[0:1], 0x8
	s_cmp_ge_u32 s24, s19
	s_cselect_b32 s26, -1, 0
	s_cmp_ge_u32 s22, s18
	s_cselect_b32 s22, -1, 0
	s_cmp_eq_u32 s24, s19
	s_cselect_b32 s22, s22, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s22, 0
	s_mul_i32 s22, s15, s18
	s_cselect_b32 s24, s23, s12
	s_cselect_b32 s25, s25, 0
	s_mul_i32 s12, s24, s19
	s_mul_hi_u32 s23, s24, s18
	s_mul_i32 s26, s25, s18
	s_add_i32 s12, s23, s12
	s_mul_i32 s27, s24, s18
	s_add_i32 s12, s12, s26
	s_sub_u32 s26, s14, s27
	s_mul_i32 s34, s24, s17
	s_mul_hi_u32 s35, s24, s16
	s_subb_u32 s27, 0, s12
	s_add_i32 s12, s29, s28
	v_mov_b32_e32 v4, s27
	s_mul_i32 s28, s26, s17
	s_mul_hi_u32 s29, s26, s16
	s_add_i32 s23, s33, s31
	s_mul_i32 s36, s25, s16
	s_add_i32 s14, s35, s34
	s_mul_i32 s31, s27, s16
	s_add_i32 s33, s29, s28
	s_lshl_b64 s[28:29], s[22:23], 3
	s_add_i32 s14, s14, s36
	s_add_i32 s33, s33, s31
	s_add_u32 s31, s8, s28
	s_addc_u32 s34, s9, s29
	s_lshl_b64 s[8:9], s[24:25], 3
	s_mul_i32 s15, s15, s16
	s_add_u32 s8, s31, s8
	s_addc_u32 s9, s34, s9
	s_lshl_b64 s[28:29], s[26:27], 3
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s20, s21, s20
	s_add_u32 s28, s31, s28
	s_addc_u32 s29, s34, s29
	s_clause 0x1
	s_load_b64 s[8:9], s[8:9], 0x0
	s_load_b64 s[28:29], s[28:29], 0x0
	v_mov_b32_e32 v7, s15
	s_mul_i32 s15, s24, s16
	s_mul_i32 s20, s20, s30
	v_dual_mov_b32 v5, s15 :: v_dual_mov_b32 v16, s33
	s_mul_i32 s15, s26, s16
	v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v10, s23
	v_mov_b32_e32 v3, s26
	v_dual_mov_b32 v13, s24 :: v_dual_mov_b32 v6, s14
	v_dual_mov_b32 v14, s25 :: v_dual_mov_b32 v15, s15
	v_dual_mov_b32 v9, s22 :: v_dual_mov_b32 v8, s12
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v17, s8
	v_dual_mov_b32 v11, s28 :: v_dual_mov_b32 v12, s29
	ds_store_b128 v2, v[1:4] offset:1024
	ds_store_b128 v2, v[13:16] offset:1040
	ds_store_b64 v2, v[17:18] offset:1088
	ds_store_b128 v2, v[5:8] offset:1056
	ds_store_b128 v2, v[9:12] offset:1072
.LBB6_2:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[5:6], v1 offset:1024
	s_load_b32 s12, s[0:1], 0x0
	s_mov_b32 s3, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 8
	v_add_co_u32 v9, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, null, s1, 0, s0
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u64_e64 s[16:17], v[9:10]
	s_cbranch_execz .LBB6_8
; %bb.3:                                ; %.lr.ph.i
	ds_load_b64 v[7:8], v1 offset:1064
	ds_load_2addr_b64 v[11:14], v1 offset0:131 offset1:132
	ds_load_2addr_b64 v[1:4], v1 offset0:135 offset1:136
	s_lshl_b64 s[8:9], s[2:3], 11
	v_lshlrev_b32_e32 v17, 3, v0
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b64 v[15:16], 3, v[7:8]
	v_lshlrev_b64 v[13:14], 3, v[13:14]
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	v_add_co_u32 v15, vcc_lo, s8, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
	v_add_co_u32 v13, vcc_lo, s8, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	v_add_co_u32 v18, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v16, vcc_lo
	v_add_co_u32 v20, vcc_lo, s6, v13
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v14, vcc_lo
	v_add_co_u32 v22, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v23, vcc_lo, s7, v12, vcc_lo
	s_lshl_b64 s[4:5], s[12:13], 8
	s_lshl_b64 s[6:7], s[12:13], 11
	s_mov_b32 s8, 0
.LBB6_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v11, vcc_lo, v20, v17
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v13, vcc_lo, v18, v17
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v19, vcc_lo
	global_load_b64 v[24:25], v[11:12], off
	v_add_co_u32 v15, vcc_lo, v22, v17
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v23, vcc_lo
	global_load_b64 v[26:27], v[13:14], off
	global_load_b64 v[28:29], v[15:16], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(2)
	v_add_f64 v[24:25], v[24:25], -v[3:4]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[24:25], v[26:27], v[24:25]
	s_waitcnt vmcnt(0)
	v_add_f64 v[26:27], v[28:29], -v[1:2]
	v_fma_f64 v[7:8], v[24:25], v[26:27], v[7:8]
	v_add_co_u32 v24, vcc_lo, 0x80, v9
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[16:17], v[24:25]
	s_cbranch_execz .LBB6_6
; %bb.5:                                ;   in Loop: Header=BB6_4 Depth=1
	global_load_b64 v[11:12], v[11:12], off offset:1024
	global_load_b64 v[13:14], v[13:14], off offset:1024
	global_load_b64 v[15:16], v[15:16], off offset:1024
	s_waitcnt vmcnt(2)
	v_add_f64 v[11:12], v[11:12], -v[3:4]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[13:14], v[11:12]
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[15:16], -v[1:2]
	v_fma_f64 v[7:8], v[11:12], v[13:14], v[7:8]
.LBB6_6:                                ;   in Loop: Header=BB6_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v9, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v18, vcc_lo, v18, s6
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, v20, s6
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v21, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[16:17], v[9:10]
	v_add_co_u32 v22, s0, v22, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v23, s0, s7, v23, s0
	s_or_b32 s8, vcc_lo, s8
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB6_4
; %bb.7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s8
.LBB6_8:                                ; %Flow54
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b32_e32 v3, 3, v0
	s_mov_b64 s[0:1], src_shared_base
	s_mov_b32 s0, exec_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v1, 0, v3, vcc_lo
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB6_10
; %bb.9:
	v_lshl_add_u32 v4, v0, 3, 0x200
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e32 v9, 0, v4, vcc_lo
	v_cndmask_b32_e64 v10, 0, s1, vcc_lo
	flat_load_b64 v[9:10], v[9:10] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB6_12
; %bb.11:
	v_lshl_add_u32 v4, v0, 3, 0x100
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_dual_cndmask_b32 v9, 0, v4 :: v_dual_add_nc_u32 v4, 0x80, v3
	v_cndmask_b32_e64 v10, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	flat_load_b64 v[9:10], v[9:10] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_dual_cndmask_b32 v9, 0, v4 :: v_dual_add_nc_u32 v4, 64, v3
	v_cndmask_b32_e64 v10, 0, s5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[9:10], v[9:10] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_dual_cndmask_b32 v9, 0, v4 :: v_dual_add_nc_u32 v4, 32, v3
	v_cndmask_b32_e64 v10, 0, s5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[9:10], v[9:10] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_dual_cndmask_b32 v9, 0, v4 :: v_dual_add_nc_u32 v4, 16, v3
	v_cndmask_b32_e64 v10, 0, s5, vcc_lo
	v_add_nc_u32_e32 v3, 8, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[9:10], v[9:10] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_cndmask_b32_e32 v9, 0, v4, vcc_lo
	v_cndmask_b32_e64 v10, 0, s5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cndmask_b32_e64 v4, 0, s5, vcc_lo
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[9:10], v[9:10] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	flat_store_b64 v[1:2], v[7:8] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[3:4], v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[3:4], v[7:8], v[3:4]
	flat_store_b64 v[1:2], v[3:4] dlc
	s_waitcnt_vscnt null, 0x0
.LBB6_12:                               ; %_Z13reducirBloqueILm128EEvPVddm.exit.i
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_14
; %bb.13:
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, s5
	s_mul_i32 s0, s12, s19
	s_mul_hi_u32 s4, s12, s18
	s_mul_i32 s5, s12, s18
	s_add_i32 s4, s4, s0
	flat_load_b64 v[8:9], v[7:8] glc dlc
	s_waitcnt vmcnt(0)
	ds_load_b64 v[10:11], v7 offset:1072
	ds_load_2addr_b64 v[0:3], v7 offset0:129 offset1:130
	s_lshl_b64 s[2:3], s[2:3], 3
	s_waitcnt lgkmcnt(1)
	v_readfirstlane_b32 s0, v10
	v_mul_lo_u32 v4, v11, s5
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s6, v2
	v_mul_lo_u32 v10, v3, s5
	v_mul_lo_u32 v11, v1, s12
	s_mul_i32 s7, s0, s4
	s_mul_hi_u32 s8, s0, s5
	s_mul_i32 s0, s0, s5
	s_add_i32 s8, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, s0 :: v_dual_add_nc_u32 v2, s8, v4
	s_mul_i32 s4, s6, s4
	s_mul_hi_u32 s9, s6, s5
	v_mul_hi_u32 v12, v0, s12
	s_mul_i32 s6, s6, s5
	s_add_i32 s9, s9, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v3, s6 :: v_dual_add_nc_u32 v4, s9, v10
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_mul_lo_u32 v10, v0, s12
	v_add_nc_u32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_add_co_u32 v12, s0, s10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v2, s0, s11, v2, s0
	v_lshlrev_b64 v[0:1], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s0, v12, v3
	v_add_co_ci_u32_e64 v2, s0, v2, v4, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, v3, v0
	v_add_co_ci_u32_e64 v1, s0, v2, v1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, v0, s2
	v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, contadorBloques@rel32@lo+4
	s_addc_u32 s3, s3, contadorBloques@rel32@hi+12
	v_add_co_u32 v2, s0, v5, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, -1, v6, s0
	global_store_b64 v[0:1], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	buffer_gl1_inv
	buffer_gl0_inv
	global_atomic_inc_u32 v0, v7, v5, s[2:3] glc
	v_mov_b32_e32 v1, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e64 s0, v[2:3], v[0:1]
	v_cndmask_b32_e64 v0, 0, 1, s0
	ds_store_b8 v7, v0 offset:1096
.LBB6_14:
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_xor_b32 s1, vcc_lo, -1
	ds_load_u8 v1, v0 offset:1096
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u16_e64 s0, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s1, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB6_16
; %bb.15:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, contadorBloques@rel32@lo+4
	s_addc_u32 s1, s1, contadorBloques@rel32@hi+12
	global_store_b32 v0, v0, s[0:1]
.LBB6_16:                               ; %_Z7reducirILm128EZ18paso_m_covarianzasPdS0_S0_S0_mmEUlmE_Z18paso_m_covarianzasS0_S0_S0_S0_mmEUlvE_Z18paso_m_covarianzasS0_S0_S0_S0_mmEUlvE0_EvT0_T1_T2_mPVdm.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18paso_m_covarianzasPdS_S_S_mm
		.amdhsa_group_segment_fixed_size 1104
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 37
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z18paso_m_covarianzasPdS_S_S_mm, .Lfunc_end6-_Z18paso_m_covarianzasPdS_S_S_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2460
; NumSgprs: 39
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1104 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 39
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z24paso_m_covarianzas_finalPdS_m ; -- Begin function _Z24paso_m_covarianzas_finalPdS_m
	.globl	_Z24paso_m_covarianzas_finalPdS_m
	.p2align	8
	.type	_Z24paso_m_covarianzas_finalPdS_m,@function
_Z24paso_m_covarianzas_finalPdS_m:      ; @_Z24paso_m_covarianzas_finalPdS_m
; %bb.0:
	s_clause 0x2
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b32 s8, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, s15
	s_mov_b32 s15, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s5, s15
	s_waitcnt lgkmcnt(0)
	s_mul_hi_u32 s9, s8, s4
	s_mul_i32 s10, s8, s4
	v_cmpx_gt_u64_e64 s[6:7], v[0:1]
	s_cbranch_execz .LBB7_4
; %bb.1:                                ; %.lr.ph.i
	s_add_u32 s12, s10, s13
	s_addc_u32 s16, s9, 0
	s_mul_hi_u32 s17, s12, s8
	s_mul_i32 s16, s16, s8
	s_mul_i32 s12, s12, s8
	s_add_i32 s17, s17, s16
	s_add_u32 s12, s12, s14
	s_addc_u32 s17, s17, 0
	s_mul_i32 s16, s12, s7
	s_mul_hi_u32 s18, s12, s6
	s_mul_i32 s17, s17, s6
	s_add_i32 s18, s18, s16
	s_mul_i32 s16, s12, s6
	s_add_i32 s17, s18, s17
	v_mov_b32_e32 v2, 0
	v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
	s_lshl_b64 s[16:17], s[16:17], 3
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v4, 0x80, v0
	s_add_u32 s12, s2, s16
	s_addc_u32 s17, s3, s17
	s_mov_b32 s16, s15
.LBB7_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v5, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[5:6]
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_le_u64_e32 vcc_lo, s[6:7], v[4:5]
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v5, v4 :: v_dual_add_nc_u32 v4, 0x80, v4
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB7_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s16
.LBB7_4:                                ; %Flow25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s11
	v_lshl_add_u32 v1, v0, 3, 0
	s_mov_b64 s[6:7], src_shared_base
	v_lshlrev_b32_e32 v6, 3, v0
	s_mov_b32 s6, exec_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v4, 0, v1, vcc_lo
	v_cndmask_b32_e64 v5, 0, s7, vcc_lo
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB7_6
; %bb.5:
	v_add3_u32 v7, 0, v6, 0x200
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v7
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cndmask_b32_e64 v8, 0, s7, vcc_lo
	flat_load_b64 v[7:8], v[7:8] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[7:8]
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_6:
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB7_8
; %bb.7:
	v_add3_u32 v6, 0, v6, 0x100
	s_mov_b64 s[16:17], src_shared_base
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s17, vcc_lo
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_nc_u32_e32 v6, 0x80, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s17, vcc_lo
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_nc_u32_e32 v6, 64, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s17, vcc_lo
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_nc_u32_e32 v6, 32, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s17, vcc_lo
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_add_nc_u32_e32 v6, 16, v1
	v_add_nc_u32_e32 v1, 8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, -1, v6
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cndmask_b32_e64 v7, 0, s17, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_cndmask_b32_e32 v6, 0, v1, vcc_lo
	v_cndmask_b32_e64 v7, 0, s17, vcc_lo
	flat_store_b64 v[4:5], v[2:3] dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b64 v[6:7], v[6:7] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f64 v[1:2], v[2:3], v[6:7]
	flat_store_b64 v[4:5], v[1:2] dlc
	s_waitcnt_vscnt null, 0x0
.LBB7_8:                                ; %_Z13reducirBloqueILm128EEvPVddm.exit.i
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB7_10
; %bb.9:                                ; %_Z12reducirFinalILm128EZ24paso_m_covarianzas_finalPdS0_mEUlmE_Z24paso_m_covarianzas_finalS0_S0_mEUlvE_EvT0_T1_PVdm.exit
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s7
	s_add_u32 s6, s10, s13
	s_addc_u32 s7, s9, 0
	s_mul_hi_u32 s9, s6, s8
	s_mul_i32 s7, s7, s8
	flat_load_b64 v[1:2], v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	s_mul_i32 s6, s6, s8
	s_add_i32 s7, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[6:7], 3
	s_add_u32 s6, s2, s6
	s_addc_u32 s7, s3, s7
	s_lshl_b64 s[2:3], s[14:15], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
	s_lshl_b64 s[4:5], s[4:5], 3
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	s_waitcnt lgkmcnt(0)
	global_store_b64 v0, v[1:2], s[2:3]
	global_load_b64 v[3:4], v0, s[0:1]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_div_scale_f64 v[9:10], vcc_lo, v[1:2], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[9:10], v[7:8]
	v_fma_f64 v[5:6], -v[5:6], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12]
	v_div_fixup_f64 v[1:2], v[5:6], v[3:4], v[1:2]
	global_store_b64 v0, v[1:2], s[2:3]
.LBB7_10:                               ; %.critedge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24paso_m_covarianzas_finalPdS_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z24paso_m_covarianzas_finalPdS_m, .Lfunc_end7-_Z24paso_m_covarianzas_finalPdS_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1056
; NumSgprs: 21
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	contadorBloques         ; @contadorBloques
	.type	contadorBloques,@object
	.section	.bss,"aw",@nobits
	.globl	contadorBloques
	.p2align	2, 0x0
contadorBloques:
	.long	0                               ; 0x0
	.size	contadorBloques, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym contadorBloques
	.addrsig_sym sharedData
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15paso_e_choleskyPdS_m
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z15paso_e_choleskyPdS_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 64
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6paso_ePdS_S_S_S_S_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     50
    .sgpr_spill_count: 0
    .symbol:         _Z6paso_ePdS_S_S_S_S_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7paso_e2PdS_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     42
    .sgpr_spill_count: 0
    .symbol:         _Z7paso_e2PdS_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 8
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20paso_e_verosimilitudPdS_m
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z20paso_e_verosimilitudPdS_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
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amdhsa.version:
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...

	.end_amdgpu_metadata
