#include <stdio.h>

__global__ void kernel_A( float *g_data, int dimx, int dimy )
{
    int ix  = blockIdx.x;
    int iy  = blockIdx.y*blockDim.y + threadIdx.y;
    int idx = iy*dimx + ix;

    float value = g_data[idx];

    if( ix % 2 )
    {
        value += sqrtf( logf(value) + 1.f );
    }
    else
    {
        value += sqrtf( cosf(value) + 1.f );
    }

    g_data[idx] = value;
}

__global__ void kernel_B( float *g_data, int dimx, int dimy )
{
    int id  = blockIdx.x*blockDim.x + threadIdx.x;

    float value = g_data[id];

    if( id % 2 )
    {
        value += sqrtf( logf(value) + 1.f );
    }
    else
    {
        value += sqrtf( cosf(value) + 1.f );
    }

    g_data[id] = value;
}

__global__ void kernel_C( float * _g_data, int dimx, int dimy )
{
    float2* g_data = reinterpret_cast<float2 *>(_g_data);

    int id  = blockIdx.x*blockDim.x + threadIdx.x;

    float2 value = g_data[id];

    value.x += sqrtf( cosf(value.x) + 1.f );
    value.y += sqrtf( logf(value.y) + 1.f );

    g_data[id] = value;
}

__global__ void kernel_D( float * _g_data, int dimx, int dimy )
{
    float4* g_data = reinterpret_cast<float4 *>(_g_data);

    int id  = blockIdx.x*blockDim.x + threadIdx.x;

    float4 value = g_data[id];

    value.x += sqrtf( cosf(value.x) + 1.f );
    value.y += sqrtf( logf(value.y) + 1.f );
    value.z += sqrtf( cosf(value.z) + 1.f );
    value.w += sqrtf( logf(value.w) + 1.f );

    g_data[id] = value;
}

float timing_experiment( void (*kernel)( float*, int,int), float *d_data, int dimx, int dimy, int nreps, int blockx, int blocky )
{
    float elapsed_time_ms=0.0f;
    cudaEvent_t start, stop;
    cudaEventCreate( &start );
    cudaEventCreate( &stop  );

    dim3 block( blockx, blocky );
    dim3 grid( dimx/block.x, dimy/block.y );

    cudaEventRecord( start, 0 );
    for(int i=0; i<nreps; i++)  // do not change this loop, it's not part of the algorithm - it's just to average time over several kernel launches
        kernel<<<grid,block>>>( d_data, dimx,dimy );
    cudaEventRecord( stop, 0 );
    cudaThreadSynchronize();
    cudaEventElapsedTime( &elapsed_time_ms, start, stop );
    elapsed_time_ms /= nreps;

    cudaEventDestroy( start );
    cudaEventDestroy( stop );

    return elapsed_time_ms;
}

int main(int argc, char *argv[])
{
    //begin choosing whether testing correctness, and code version
    size_t version = 1;
    bool testCorretness = 0;
    if(argc >= 2)
        version = atoi(argv[1]);
    if(argc >= 3)
        testCorretness = atoi(argv[2]);
    //end choosing whether testing correctness, and code version

    int dimx = 2*1024;
    int dimy = 2*1024;

    int nreps = 10;

    int nbytes = dimx*dimy*sizeof(float);

    float *d_data=0, *h_data=0;
    cudaMalloc( (void**)&d_data, nbytes );
    if( 0 == d_data )
    {
        printf("couldn't allocate GPU memory\n");
        return -1;
    }
    printf("allocated %.2f MB on GPU\n", nbytes/(1024.f*1024.f) );
    h_data = (float*)malloc( nbytes );
    if( 0 == h_data )
    {
        printf("couldn't allocate CPU memory\n");
        return -2;
    }
    printf("allocated %.2f MB on CPU\n", nbytes/(1024.f*1024.f) );
    for(int i=0; i<dimx*dimy; i++)
        h_data[i] = 10.f + rand() % 256;
    cudaMemcpy( d_data, h_data, nbytes, cudaMemcpyHostToDevice );

    float elapsed_time_ms=0.0f;

    //start choosing different versions and run
    if ( version == 1 ) {
        elapsed_time_ms = timing_experiment( kernel_A, d_data, dimx,dimy, nreps, 1, 512 );
    } else if ( version == 2 ) {
        elapsed_time_ms = timing_experiment( kernel_B, d_data, dimx*dimy, 1, nreps, 256, 1 );
    } else if ( version == 3 ) {
        elapsed_time_ms = timing_experiment( kernel_C, d_data, dimx*dimy/2, 1, nreps, 256, 1 );
    } else if ( version == 4 ) {
        elapsed_time_ms = timing_experiment( kernel_D, d_data, dimx*dimy/4, 1, nreps, 256, 1 );
    } else {
        printf( "code version does not exist.\n" );
        return -3;
    }
    printf("%c:  %8.6f ms\n", (char)(version-1+'A'), elapsed_time_ms );
    printf("CUDA: %s\n", cudaGetErrorString( cudaGetLastError() ) );
    //end choosing different versions and run

    //start test correctness
    if(testCorretness) {
        printf("\ncorrectness:\n");

        //read data from gpu to array "h_gpuRes"
        float *h_gpuRes=0;
        h_gpuRes = (float*)malloc( nbytes );
        if ( 0 == h_gpuRes )
        {
            printf("couldn't allocate CPU memory\n");
            return -2;
        }
        cudaMemcpy( h_gpuRes, d_data, nbytes, cudaMemcpyDeviceToHost);

        //execute the original version to test correctness
        cudaMemcpy( d_data, h_data, nbytes, cudaMemcpyHostToDevice );
        elapsed_time_ms = timing_experiment( kernel_A, d_data, dimx,dimy, nreps, 1, 512 );

        //read kernel A's data from gpu to array "h_gpuResA"
        float *h_gpuResA=0;
        h_gpuResA = (float*)malloc( nbytes );
        if ( 0 == h_gpuResA )
        {
            printf("couldn't allocate CPU memory\n");
            return -2;
        }
        cudaMemcpy( h_gpuResA, d_data, nbytes, cudaMemcpyDeviceToHost);

        //compare result
        int i;
        for(i=0; i<dimx*dimy; i++) {
            if( abs(h_gpuRes[i] - h_gpuResA[i]) > 1e-7 )  {
                printf( "calculation error in GPU results in %d\n", i );
                printf( "data: %f\nA's gpu result: %f\nOther version's gpu result: %f\n", h_data[i], h_gpuResA[i], h_gpuRes[i]);
                break;
            }
        }
        if( i >= dimx*dimy ) {
            printf( "calculation correct in GPU results! Congrats!\n" );
        }

        //release cpu memory
        if( h_gpuRes )
            free( h_gpuRes);
        if( h_gpuResA )
            free( h_gpuResA);
    }
    //end test correctness

    if( d_data )
        cudaFree( d_data );
    if( h_data )
        free( h_data );

    cudaThreadExit();

    return 0;
}

	.file	"tmpxft_00263e27_00000000-6_cuda_prog_1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z17timing_experimentPFvPfiiES_iiiii
	.type	_Z17timing_experimentPFvPfiiES_iiiii, @function
_Z17timing_experimentPFvPfiiES_iiiii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r8d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r9d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movl	$0x00000000, 28(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%ebx, %eax
	xorl	%edx, %edx
	movq	32(%rsp), %rdi
	divl	%r12d
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	xorl	%edx, %edx
	xorl	%esi, %esi
	movl	%eax, 60(%rsp)
	movl	%ebp, %eax
	divl	144(%rsp)
	movl	%eax, 64(%rsp)
	call	cudaEventRecord@PLT
.L3:
	cmpl	%r13d, %r14d
	jge	.L9
	movl	%r12d, 48(%rsp)
	movl	56(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	144(%rsp), %eax
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	movl	%eax, 52(%rsp)
	movq	48(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	movq	8(%rsp), %rdi
	movl	%ebp, %edx
	movl	%ebx, %esi
	call	*%r15
.L4:
	incl	%r14d
	jmp	.L3
.L9:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	call	cudaThreadSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	cvtsi2ssl	%r13d, %xmm1
	movss	28(%rsp), %xmm0
	movq	32(%rsp), %rdi
	divss	%xmm1, %xmm0
	movss	%xmm0, 28(%rsp)
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movss	28(%rsp), %xmm0
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z17timing_experimentPFvPfiiES_iiiii, .-_Z17timing_experimentPFvPfiiES_iiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"couldn't allocate GPU memory\n"
.LC3:
	.string	"allocated %.2f MB on GPU\n"
.LC4:
	.string	"couldn't allocate CPU memory\n"
.LC5:
	.string	"allocated %.2f MB on CPU\n"
.LC7:
	.string	"code version does not exist.\n"
.LC8:
	.string	"%c:  %8.6f ms\n"
.LC9:
	.string	"CUDA: %s\n"
.LC10:
	.string	"\ncorrectness:\n"
.LC13:
	.string	"calculation error in GPU results in %d\n"
.LC14:
	.string	"data: %f\nA's gpu result: %f\nOther version's gpu result: %f\n"
.LC15:
	.string	"calculation correct in GPU results! Congrats!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	cmpl	$1, %edi
	jle	.L29
	movl	%edi, %r13d
	movq	8(%rsi), %rdi
	movq	%rsi, %rbp
	xorl	%r12d, %r12d
	call	atoi@PLT
	movslq	%eax, %rbx
	cmpl	$2, %r13d
	je	.L11
	movq	16(%rbp), %rdi
	call	atoi@PLT
	testl	%eax, %eax
	setne	%r12b
	jmp	.L11
.L29:
	movl	$1, %ebx
	xorl	%r12d, %r12d
.L11:
	xorl	%ebp, %ebp
	movq	%rsp, %rdi
	movl	$16777216, %esi
	movq	%rbp, (%rsp)
	call	cudaMalloc@PLT
	cmpq	$0, (%rsp)
	jne	.L12
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %eax
	jmp	.L10
.L12:
	movsd	.LC2(%rip), %xmm0
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	movl	$16777216, %edi
	call	malloc@PLT
	movq	%rax, %rbp
	testq	%rax, %rax
	jne	.L14
.L22:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$-2, %eax
	jmp	.L10
.L14:
	movsd	.LC2(%rip), %xmm0
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	xorl	%r13d, %r13d
	call	__printf_chk@PLT
.L15:
	call	rand@PLT
	movl	$256, %ecx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	addss	.LC6(%rip), %xmm0
	movss	%xmm0, 0(%rbp,%r13,4)
	incq	%r13
	cmpq	$4194304, %r13
	jne	.L15
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$16777216, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	cmpq	$1, %rbx
	jne	.L16
	movl	$1, %r9d
	pushq	%r11
	.cfi_remember_state
	.cfi_def_cfa_offset 72
	movl	$10, %r8d
	movl	$2048, %ecx
	pushq	$512
	.cfi_def_cfa_offset 80
	movl	$2048, %edx
	movq	16(%rsp), %rsi
	leaq	_Z8kernel_APfii(%rip), %rdi
	jmp	.L48
.L16:
	.cfi_restore_state
	cmpq	$2, %rbx
	jne	.L18
	movl	$256, %r9d
	pushq	%r10
	.cfi_remember_state
	.cfi_def_cfa_offset 72
	movl	$10, %r8d
	movl	$1, %ecx
	pushq	$1
	.cfi_def_cfa_offset 80
	movl	$4194304, %edx
	movq	16(%rsp), %rsi
	leaq	_Z8kernel_BPfii(%rip), %rdi
	jmp	.L48
.L18:
	.cfi_restore_state
	cmpq	$3, %rbx
	jne	.L19
	movl	$10, %r8d
	pushq	%r9
	.cfi_remember_state
	.cfi_def_cfa_offset 72
	movl	$1, %ecx
	movl	$256, %r9d
	pushq	$1
	.cfi_def_cfa_offset 80
	movl	$2097152, %edx
	movq	16(%rsp), %rsi
	leaq	_Z8kernel_CPfii(%rip), %rdi
	jmp	.L48
.L19:
	.cfi_restore_state
	cmpq	$4, %rbx
	jne	.L20
	pushq	%r8
	.cfi_def_cfa_offset 72
	movl	$256, %r9d
	movl	$10, %r8d
	movl	$1, %ecx
	pushq	$1
	.cfi_def_cfa_offset 80
	movq	16(%rsp), %rsi
	movl	$1048576, %edx
	leaq	_Z8kernel_DPfii(%rip), %rdi
.L48:
	call	_Z17timing_experimentPFvPfiiES_iiiii
	leal	64(%rbx), %edx
	popq	%rsi
	.cfi_def_cfa_offset 72
	movb	$1, %al
	popq	%rdi
	.cfi_def_cfa_offset 64
	movzbl	%dl, %edx
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	testb	%r12b, %r12b
	je	.L21
	jmp	.L49
.L20:
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$-3, %eax
	jmp	.L10
.L49:
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$16777216, %edi
	call	malloc@PLT
	movq	%rax, %r12
	testq	%rax, %rax
	je	.L22
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$16777216, %edx
	movq	%rax, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$16777216, %edx
	call	cudaMemcpy@PLT
	movl	$2048, %ecx
	movl	$2048, %edx
	movl	$1, %r9d
	pushq	%rax
	.cfi_def_cfa_offset 72
	movl	$10, %r8d
	leaq	_Z8kernel_APfii(%rip), %rdi
	pushq	$512
	.cfi_def_cfa_offset 80
	movq	16(%rsp), %rsi
	call	_Z17timing_experimentPFvPfiiES_iiiii
	movl	$16777216, %edi
	call	malloc@PLT
	popq	%rdx
	.cfi_def_cfa_offset 72
	popq	%rcx
	.cfi_def_cfa_offset 64
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L22
	movq	(%rsp), %rsi
	movl	$16777216, %edx
	movq	%rax, %rdi
	xorl	%r13d, %r13d
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movsd	.LC12(%rip), %xmm2
	xorl	%edx, %edx
	movss	.LC11(%rip), %xmm1
.L26:
	movss	(%r12,%r13), %xmm0
	subss	(%rbx,%r13), %xmm0
	andps	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	comisd	%xmm2, %xmm0
	jbe	.L46
	leaq	.LC13(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC14(%rip), %rsi
	movb	$3, %al
	movl	$2, %edi
	cvtss2sd	0(%rbp,%r13), %xmm0
	cvtss2sd	(%r12,%r13), %xmm2
	cvtss2sd	(%rbx,%r13), %xmm1
	call	__printf_chk@PLT
	jmp	.L25
.L46:
	incl	%edx
	addq	$4, %r13
	cmpl	$4194304, %edx
	jne	.L26
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L25:
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
.L21:
	movq	(%rsp), %rdi
	testq	%rdi, %rdi
	je	.L27
	call	cudaFree@PLT
.L27:
	movq	%rbp, %rdi
	call	free@PLT
	call	cudaThreadExit@PLT
	xorl	%eax, %eax
.L10:
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.text
	.globl	_Z29__device_stub__Z8kernel_APfiiPfii
	.type	_Z29__device_stub__Z8kernel_APfiiPfii, @function
_Z29__device_stub__Z8kernel_APfiiPfii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8kernel_APfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L50:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z29__device_stub__Z8kernel_APfiiPfii, .-_Z29__device_stub__Z8kernel_APfiiPfii
	.globl	_Z8kernel_APfii
	.type	_Z8kernel_APfii, @function
_Z8kernel_APfii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8kernel_APfiiPfii
	.cfi_endproc
.LFE2054:
	.size	_Z8kernel_APfii, .-_Z8kernel_APfii
	.globl	_Z29__device_stub__Z8kernel_BPfiiPfii
	.type	_Z29__device_stub__Z8kernel_BPfiiPfii, @function
_Z29__device_stub__Z8kernel_BPfiiPfii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8kernel_BPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L55:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z29__device_stub__Z8kernel_BPfiiPfii, .-_Z29__device_stub__Z8kernel_BPfiiPfii
	.globl	_Z8kernel_BPfii
	.type	_Z8kernel_BPfii, @function
_Z8kernel_BPfii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8kernel_BPfiiPfii
	.cfi_endproc
.LFE2056:
	.size	_Z8kernel_BPfii, .-_Z8kernel_BPfii
	.globl	_Z29__device_stub__Z8kernel_CPfiiPfii
	.type	_Z29__device_stub__Z8kernel_CPfiiPfii, @function
_Z29__device_stub__Z8kernel_CPfiiPfii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8kernel_CPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L60:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z29__device_stub__Z8kernel_CPfiiPfii, .-_Z29__device_stub__Z8kernel_CPfiiPfii
	.globl	_Z8kernel_CPfii
	.type	_Z8kernel_CPfii, @function
_Z8kernel_CPfii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8kernel_CPfiiPfii
	.cfi_endproc
.LFE2058:
	.size	_Z8kernel_CPfii, .-_Z8kernel_CPfii
	.globl	_Z29__device_stub__Z8kernel_DPfiiPfii
	.type	_Z29__device_stub__Z8kernel_DPfiiPfii, @function
_Z29__device_stub__Z8kernel_DPfiiPfii:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8kernel_DPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L65:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L67
	call	__stack_chk_fail@PLT
.L67:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z29__device_stub__Z8kernel_DPfiiPfii, .-_Z29__device_stub__Z8kernel_DPfiiPfii
	.globl	_Z8kernel_DPfii
	.type	_Z8kernel_DPfii, @function
_Z8kernel_DPfii:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8kernel_DPfiiPfii
	.cfi_endproc
.LFE2060:
	.size	_Z8kernel_DPfii, .-_Z8kernel_DPfii
	.section	.rodata.str1.1
.LC16:
	.string	"_Z8kernel_DPfii"
.LC17:
	.string	"_Z8kernel_CPfii"
.LC18:
	.string	"_Z8kernel_BPfii"
.LC19:
	.string	"_Z8kernel_APfii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8kernel_DPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8kernel_CPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8kernel_BPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8kernel_APfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1076887552
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC6:
	.long	1092616192
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC11:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC12:
	.long	-1698910392
	.long	1048238066
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

__global__ void kernel_A( float *g_data, int dimx, int dimy )
{
    int ix  = blockIdx.x;
    int iy  = blockIdx.y*blockDim.y + threadIdx.y;
    int idx = iy*dimx + ix;

    float value = g_data[idx];

    if( ix % 2 )
    {
        value += sqrtf( logf(value) + 1.f );
    }
    else
    {
        value += sqrtf( cosf(value) + 1.f );
    }

    g_data[idx] = value;
}

__global__ void kernel_B( float *g_data, int dimx, int dimy )
{
    int id  = blockIdx.x*blockDim.x + threadIdx.x;

    float value = g_data[id];

    if( id % 2 )
    {
        value += sqrtf( logf(value) + 1.f );
    }
    else
    {
        value += sqrtf( cosf(value) + 1.f );
    }

    g_data[id] = value;
}

__global__ void kernel_C( float * _g_data, int dimx, int dimy )
{
    float2* g_data = reinterpret_cast<float2 *>(_g_data);

    int id  = blockIdx.x*blockDim.x + threadIdx.x;

    float2 value = g_data[id];

    value.x += sqrtf( cosf(value.x) + 1.f );
    value.y += sqrtf( logf(value.y) + 1.f );

    g_data[id] = value;
}

__global__ void kernel_D( float * _g_data, int dimx, int dimy )
{
    float4* g_data = reinterpret_cast<float4 *>(_g_data);

    int id  = blockIdx.x*blockDim.x + threadIdx.x;

    float4 value = g_data[id];

    value.x += sqrtf( cosf(value.x) + 1.f );
    value.y += sqrtf( logf(value.y) + 1.f );
    value.z += sqrtf( cosf(value.z) + 1.f );
    value.w += sqrtf( logf(value.w) + 1.f );

    g_data[id] = value;
}

float timing_experiment( void (*kernel)( float*, int,int), float *d_data, int dimx, int dimy, int nreps, int blockx, int blocky )
{
    float elapsed_time_ms=0.0f;
    hipEvent_t start, stop;
    hipEventCreate( &start );
    hipEventCreate( &stop  );

    dim3 block( blockx, blocky );
    dim3 grid( dimx/block.x, dimy/block.y );

    hipEventRecord( start, 0 );
    for(int i=0; i<nreps; i++)  // do not change this loop, it's not part of the algorithm - it's just to average time over several kernel launches
        kernel<<<grid,block>>>( d_data, dimx,dimy );
    hipEventRecord( stop, 0 );
    hipDeviceSynchronize();
    hipEventElapsedTime( &elapsed_time_ms, start, stop );
    elapsed_time_ms /= nreps;

    hipEventDestroy( start );
    hipEventDestroy( stop );

    return elapsed_time_ms;
}

int main(int argc, char *argv[])
{
    //begin choosing whether testing correctness, and code version
    size_t version = 1;
    bool testCorretness = 0;
    if(argc >= 2)
        version = atoi(argv[1]);
    if(argc >= 3)
        testCorretness = atoi(argv[2]);
    //end choosing whether testing correctness, and code version

    int dimx = 2*1024;
    int dimy = 2*1024;

    int nreps = 10;

    int nbytes = dimx*dimy*sizeof(float);

    float *d_data=0, *h_data=0;
    hipMalloc( (void**)&d_data, nbytes );
    if( 0 == d_data )
    {
        printf("couldn't allocate GPU memory\n");
        return -1;
    }
    printf("allocated %.2f MB on GPU\n", nbytes/(1024.f*1024.f) );
    h_data = (float*)malloc( nbytes );
    if( 0 == h_data )
    {
        printf("couldn't allocate CPU memory\n");
        return -2;
    }
    printf("allocated %.2f MB on CPU\n", nbytes/(1024.f*1024.f) );
    for(int i=0; i<dimx*dimy; i++)
        h_data[i] = 10.f + rand() % 256;
    hipMemcpy( d_data, h_data, nbytes, hipMemcpyHostToDevice );

    float elapsed_time_ms=0.0f;

    //start choosing different versions and run
    if ( version == 1 ) {
        elapsed_time_ms = timing_experiment( kernel_A, d_data, dimx,dimy, nreps, 1, 512 );
    } else if ( version == 2 ) {
        elapsed_time_ms = timing_experiment( kernel_B, d_data, dimx*dimy, 1, nreps, 256, 1 );
    } else if ( version == 3 ) {
        elapsed_time_ms = timing_experiment( kernel_C, d_data, dimx*dimy/2, 1, nreps, 256, 1 );
    } else if ( version == 4 ) {
        elapsed_time_ms = timing_experiment( kernel_D, d_data, dimx*dimy/4, 1, nreps, 256, 1 );
    } else {
        printf( "code version does not exist.\n" );
        return -3;
    }
    printf("%c:  %8.6f ms\n", (char)(version-1+'A'), elapsed_time_ms );
    printf("CUDA: %s\n", hipGetErrorString( hipGetLastError() ) );
    //end choosing different versions and run

    //start test correctness
    if(testCorretness) {
        printf("\ncorrectness:\n");

        //read data from gpu to array "h_gpuRes"
        float *h_gpuRes=0;
        h_gpuRes = (float*)malloc( nbytes );
        if ( 0 == h_gpuRes )
        {
            printf("couldn't allocate CPU memory\n");
            return -2;
        }
        hipMemcpy( h_gpuRes, d_data, nbytes, hipMemcpyDeviceToHost);

        //execute the original version to test correctness
        hipMemcpy( d_data, h_data, nbytes, hipMemcpyHostToDevice );
        elapsed_time_ms = timing_experiment( kernel_A, d_data, dimx,dimy, nreps, 1, 512 );

        //read kernel A's data from gpu to array "h_gpuResA"
        float *h_gpuResA=0;
        h_gpuResA = (float*)malloc( nbytes );
        if ( 0 == h_gpuResA )
        {
            printf("couldn't allocate CPU memory\n");
            return -2;
        }
        hipMemcpy( h_gpuResA, d_data, nbytes, hipMemcpyDeviceToHost);

        //compare result
        int i;
        for(i=0; i<dimx*dimy; i++) {
            if( abs(h_gpuRes[i] - h_gpuResA[i]) > 1e-7 )  {
                printf( "calculation error in GPU results in %d\n", i );
                printf( "data: %f\nA's gpu result: %f\nOther version's gpu result: %f\n", h_data[i], h_gpuResA[i], h_gpuRes[i]);
                break;
            }
        }
        if( i >= dimx*dimy ) {
            printf( "calculation correct in GPU results! Congrats!\n" );
        }

        //release cpu memory
        if( h_gpuRes )
            free( h_gpuRes);
        if( h_gpuResA )
            free( h_gpuResA);
    }
    //end test correctness

    if( d_data )
        hipFree( d_data );
    if( h_data )
        free( h_data );

    hipDeviceReset();

    return 0;
}

	.text
	.file	"cuda_prog_1.hip"
	.globl	_Z23__device_stub__kernel_APfii # -- Begin function _Z23__device_stub__kernel_APfii
	.type	_Z23__device_stub__kernel_APfii,@function
_Z23__device_stub__kernel_APfii:        # @_Z23__device_stub__kernel_APfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8kernel_APfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__kernel_APfii, .Lfunc_end0-_Z23__device_stub__kernel_APfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernel_BPfii # -- Begin function _Z23__device_stub__kernel_BPfii
	.type	_Z23__device_stub__kernel_BPfii,@function
_Z23__device_stub__kernel_BPfii:        # @_Z23__device_stub__kernel_BPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8kernel_BPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__kernel_BPfii, .Lfunc_end1-_Z23__device_stub__kernel_BPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernel_CPfii # -- Begin function _Z23__device_stub__kernel_CPfii
	.type	_Z23__device_stub__kernel_CPfii,@function
_Z23__device_stub__kernel_CPfii:        # @_Z23__device_stub__kernel_CPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8kernel_CPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__kernel_CPfii, .Lfunc_end2-_Z23__device_stub__kernel_CPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__kernel_DPfii # -- Begin function _Z23__device_stub__kernel_DPfii
	.type	_Z23__device_stub__kernel_DPfii,@function
_Z23__device_stub__kernel_DPfii:        # @_Z23__device_stub__kernel_DPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8kernel_DPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__kernel_DPfii, .Lfunc_end3-_Z23__device_stub__kernel_DPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z17timing_experimentPFvPfiiES_iiiii # -- Begin function _Z17timing_experimentPFvPfiiES_iiiii
	.type	_Z17timing_experimentPFvPfiiES_iiiii,@function
_Z17timing_experimentPFvPfiiES_iiiii:   # @_Z17timing_experimentPFvPfiiES_iiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	movq	%rdi, %r12
	movl	112(%rsp), %r13d
	movl	$0, 36(%rsp)
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movl	%r14d, %eax
	xorl	%edx, %edx
	movl	%ebx, 32(%rsp)                  # 4-byte Spill
	divl	%ebx
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	%ebp, %eax
	xorl	%edx, %edx
	divl	%r13d
	movl	%eax, %ebx
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	%r15d, 12(%rsp)                 # 4-byte Spill
	testl	%r15d, %r15d
	jle	.LBB4_5
# %bb.1:
	movl	32(%rsp), %eax                  # 4-byte Reload
	shlq	$32, %r13
	orq	%rax, %r13
	shlq	$32, %rbx
	addq	40(%rsp), %rbx                  # 8-byte Folded Reload
	movl	12(%rsp), %r15d                 # 4-byte Reload
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.3:                                #   in Loop: Header=BB4_2 Depth=1
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	%r14d, %esi
	movl	%ebp, %edx
	callq	*(%r12)
.LBB4_4:                                #   in Loop: Header=BB4_2 Depth=1
	decl	%r15d
	jne	.LBB4_2
.LBB4_5:                                # %._crit_edge
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtsi2ssl	12(%rsp), %xmm0         # 4-byte Folded Reload
	movss	(%rbx), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, (%rbx)
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z17timing_experimentPFvPfiiES_iiiii, .Lfunc_end4-_Z17timing_experimentPFvPfiiES_iiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x4030000000000000              # double 16
.LCPI5_3:
	.quad	0x3e7ad7f29abcaf48              # double 9.9999999999999995E-8
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI5_1:
	.long	0x41200000                      # float 10
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI5_2:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jl	.LBB5_1
# %bb.2:
	movq	%rsi, %rbx
	movl	%edi, %ebp
	movq	8(%rsi), %rdi
	callq	atoi
	movslq	%eax, %r14
	cmpl	$2, %ebp
	je	.LBB5_3
# %bb.4:
	movq	16(%rbx), %rdi
	callq	atoi
	testl	%eax, %eax
	setne	%bpl
	jmp	.LBB5_5
.LBB5_1:
	movl	$1, %r14d
.LBB5_3:
	xorl	%ebp, %ebp
.LBB5_5:                                # %.thread
	leaq	8(%rsp), %rbx
	movq	$0, (%rbx)
	movl	$16777216, %esi                 # imm = 0x1000000
	movq	%rbx, %rdi
	callq	hipMalloc
	cmpq	$0, (%rbx)
	je	.LBB5_6
# %bb.7:
	movsd	.LCPI5_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movl	$16777216, %edi                 # imm = 0x1000000
	callq	malloc
	testq	%rax, %rax
	je	.LBB5_8
# %bb.11:
	movq	%rax, %rbx
	movsd	.LCPI5_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorl	%r15d, %r15d
.LBB5_12:                               # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	255(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-256, %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	addss	.LCPI5_1(%rip), %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$4194304, %r15                  # imm = 0x400000
	jne	.LBB5_12
# %bb.9:
	movq	8(%rsp), %rdi
	movl	$16777216, %edx                 # imm = 0x1000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-1(%r14), %rax
	cmpq	$3, %rax
	ja	.LBB5_17
# %bb.10:
	jmpq	*.LJTI5_0(,%rax,8)
.LBB5_18:
	movq	8(%rsp), %rsi
	movl	$512, (%rsp)                    # imm = 0x200
	movl	$_Z8kernel_APfii, %edi
	movl	$2048, %edx                     # imm = 0x800
	movl	$2048, %ecx                     # imm = 0x800
	movl	$10, %r8d
	movl	$1, %r9d
	jmp	.LBB5_19
.LBB5_6:
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movl	$-1, %eax
	jmp	.LBB5_30
.LBB5_15:
	movq	8(%rsp), %rsi
	movl	$1, (%rsp)
	movl	$_Z8kernel_CPfii, %edi
	movl	$2097152, %edx                  # imm = 0x200000
	jmp	.LBB5_14
.LBB5_16:
	movq	8(%rsp), %rsi
	movl	$1, (%rsp)
	movl	$_Z8kernel_DPfii, %edi
	movl	$1048576, %edx                  # imm = 0x100000
	jmp	.LBB5_14
.LBB5_13:
	movq	8(%rsp), %rsi
	movl	$1, (%rsp)
	movl	$_Z8kernel_BPfii, %edi
	movl	$4194304, %edx                  # imm = 0x400000
.LBB5_14:
	movl	$1, %ecx
	movl	$10, %r8d
	movl	$256, %r9d                      # imm = 0x100
.LBB5_19:
	callq	_Z17timing_experimentPFvPfiiES_iiiii
	addl	$64, %r14d
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.5, %edi
	movl	%r14d, %esi
	movb	$1, %al
	callq	printf
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.6, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	testb	%bpl, %bpl
	je	.LBB5_27
# %bb.20:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$16777216, %edi                 # imm = 0x1000000
	callq	malloc
	testq	%rax, %rax
	je	.LBB5_8
# %bb.21:
	movq	%rax, %r14
	movq	8(%rsp), %rsi
	movl	$16777216, %edx                 # imm = 0x1000000
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$16777216, %edx                 # imm = 0x1000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$512, (%rsp)                    # imm = 0x200
	movl	$_Z8kernel_APfii, %edi
	movl	$2048, %edx                     # imm = 0x800
	movl	$2048, %ecx                     # imm = 0x800
	movl	$10, %r8d
	movl	$1, %r9d
	callq	_Z17timing_experimentPFvPfiiES_iiiii
	movl	$16777216, %edi                 # imm = 0x1000000
	callq	malloc
	testq	%rax, %rax
	je	.LBB5_8
# %bb.22:
	movq	%rax, %r15
	movq	8(%rsp), %rsi
	movl	$16777216, %edx                 # imm = 0x1000000
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
	movaps	.LCPI5_2(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	movsd	.LCPI5_3(%rip), %xmm1           # xmm1 = mem[0],zero
.LBB5_23:                               # =>This Inner Loop Header: Depth=1
	movss	(%r14,%r12,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	(%r15,%r12,4), %xmm2
	andps	%xmm0, %xmm2
	cvtss2sd	%xmm2, %xmm2
	ucomisd	%xmm1, %xmm2
	ja	.LBB5_31
# %bb.24:                               #   in Loop: Header=BB5_23 Depth=1
	incq	%r12
	cmpq	$4194304, %r12                  # imm = 0x400000
	jne	.LBB5_23
# %bb.25:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	jmp	.LBB5_26
.LBB5_8:
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$-2, %eax
	jmp	.LBB5_30
.LBB5_17:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$-3, %eax
	jmp	.LBB5_30
.LBB5_31:
	movl	$.L.str.8, %edi
	movl	%r12d, %esi
	xorl	%eax, %eax
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r12,4), %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	(%r15,%r12,4), %xmm1
	xorps	%xmm2, %xmm2
	cvtss2sd	(%r14,%r12,4), %xmm2
	movl	$.L.str.9, %edi
	movb	$3, %al
	callq	printf
.LBB5_26:
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
.LBB5_27:
	movq	8(%rsp), %rdi
	testq	%rdi, %rdi
	je	.LBB5_29
# %bb.28:
	callq	hipFree
.LBB5_29:
	movq	%rbx, %rdi
	callq	free
	callq	hipDeviceReset
	xorl	%eax, %eax
.LBB5_30:                               # %.thread96
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI5_0:
	.quad	.LBB5_18
	.quad	.LBB5_13
	.quad	.LBB5_15
	.quad	.LBB5_16
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_APfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_BPfii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_CPfii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8kernel_DPfii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8kernel_APfii,@object         # @_Z8kernel_APfii
	.section	.rodata,"a",@progbits
	.globl	_Z8kernel_APfii
	.p2align	3, 0x0
_Z8kernel_APfii:
	.quad	_Z23__device_stub__kernel_APfii
	.size	_Z8kernel_APfii, 8

	.type	_Z8kernel_BPfii,@object         # @_Z8kernel_BPfii
	.globl	_Z8kernel_BPfii
	.p2align	3, 0x0
_Z8kernel_BPfii:
	.quad	_Z23__device_stub__kernel_BPfii
	.size	_Z8kernel_BPfii, 8

	.type	_Z8kernel_CPfii,@object         # @_Z8kernel_CPfii
	.globl	_Z8kernel_CPfii
	.p2align	3, 0x0
_Z8kernel_CPfii:
	.quad	_Z23__device_stub__kernel_CPfii
	.size	_Z8kernel_CPfii, 8

	.type	_Z8kernel_DPfii,@object         # @_Z8kernel_DPfii
	.globl	_Z8kernel_DPfii
	.p2align	3, 0x0
_Z8kernel_DPfii:
	.quad	_Z23__device_stub__kernel_DPfii
	.size	_Z8kernel_DPfii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"allocated %.2f MB on GPU\n"
	.size	.L.str.1, 26

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"allocated %.2f MB on CPU\n"
	.size	.L.str.3, 26

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%c:  %8.6f ms\n"
	.size	.L.str.5, 15

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"CUDA: %s\n"
	.size	.L.str.6, 10

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"calculation error in GPU results in %d\n"
	.size	.L.str.8, 40

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"data: %f\nA's gpu result: %f\nOther version's gpu result: %f\n"
	.size	.L.str.9, 60

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8kernel_APfii"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8kernel_BPfii"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8kernel_CPfii"
	.size	.L__unnamed_3, 16

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z8kernel_DPfii"
	.size	.L__unnamed_4, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"code version does not exist."
	.size	.Lstr, 29

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\ncorrectness:"
	.size	.Lstr.1, 14

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"calculation correct in GPU results! Congrats!"
	.size	.Lstr.2, 46

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"couldn't allocate CPU memory"
	.size	.Lstr.5, 29

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"couldn't allocate GPU memory"
	.size	.Lstr.6, 29

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__kernel_APfii
	.addrsig_sym _Z23__device_stub__kernel_BPfii
	.addrsig_sym _Z23__device_stub__kernel_CPfii
	.addrsig_sym _Z23__device_stub__kernel_DPfii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8kernel_APfii
	.addrsig_sym _Z8kernel_BPfii
	.addrsig_sym _Z8kernel_CPfii
	.addrsig_sym _Z8kernel_DPfii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8kernel_APfii         ; -- Begin function _Z8kernel_APfii
	.globl	_Z8kernel_APfii
	.p2align	8
	.type	_Z8kernel_APfii,@function
_Z8kernel_APfii:                        ; @_Z8kernel_APfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x8
	v_bfe_u32 v0, v0, 10, 10
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_bitcmp0_b32 s14, 0
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v1, s3, s[14:15]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s1, 0
	global_load_b32 v2, v[0:1], off
	s_cbranch_scc1 .LBB0_2
; %bb.1:
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
	v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v2, v3
	v_log_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x3f317217, v3
	v_cmp_gt_f32_e64 s0, 0x7f800000, |v3|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0x3f317217, v3, -v4
	v_fmamk_f32 v5, v3, 0x3377d1cf, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	v_cndmask_b32_e64 v3, v3, v4, s0
	v_cndmask_b32_e64 v4, 0, 0x41b17218, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v4
	v_add_f32_e32 v3, 1.0, v3
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr3
.LBB0_3:                                ; %Flow18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_9
; %bb.4:
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v10, 0x7fffffff, v2
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v13, v10, s0, 0x800000
	v_lshrrev_b32_e32 v10, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v13, 0
	v_add_nc_u32_e32 v11, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v13, v[4:5]
	v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v7
	v_add_nc_u32_e32 v12, v12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v13, v[4:5]
	v_cmp_lt_u32_e64 s0, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s0
	v_dual_mov_b32 v4, v8 :: v_dual_cndmask_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v12
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v13, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v14
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v13, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v6, v3, s0
	v_mov_b32_e32 v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x4e441529, v13, v[4:5]
	v_mov_b32_e32 v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0xa2f9836e, v13, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v5, v10, v8 :: v_dual_add_nc_u32 v4, v4, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v12, v10
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v11, v5, s0
	v_cndmask_b32_e64 v10, v10, v11, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, v5, v9, s0
	v_sub_nc_u32_e32 v11, 32, v4
	v_cndmask_b32_e64 v9, v9, v6, s0
	v_cndmask_b32_e64 v10, v10, v8, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v5, s1
	v_cndmask_b32_e64 v5, v5, v9, s1
	v_cndmask_b32_e64 v3, v9, v3, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v10, v8, v11
	v_alignbit_b32 v7, v8, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, v12, v10, vcc_lo
	v_alignbit_b32 v10, v5, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_bfe_u32 v7, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	v_alignbit_b32 v8, v4, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, 0, v7
	v_alignbit_b32 v6, v6, v5, 30
	v_alignbit_b32 v3, v5, v3, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v9
	v_xor_b32_e32 v5, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v9
	v_clz_i32_u32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v6, 31, v10
	v_lshlrev_b32_e32 v12, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v8, v5, v6
	v_alignbit_b32 v3, v5, v3, v6
	v_lshrrev_b32_e32 v6, 29, v4
	v_alignbit_b32 v5, v8, v3, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v6, 31, v6
	v_lshrrev_b32_e32 v8, 9, v8
	v_clz_i32_u32_e32 v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v11, 0.5, v6
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v12
	v_sub_nc_u32_e32 v13, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v5, v3, v13
	v_or_b32_e32 v5, v8, v11
	v_add_lshl_u32 v8, v9, v10, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 9, v3
	v_mul_f32_e32 v9, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v8
	v_fma_f32 v8, 0x3fc90fda, v5, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 0x33000000, v3
	v_fmamk_f32 v5, v5, 0x33a22168, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v3, v3, v6
	v_fmac_f32_e32 v5, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v9, v5
	v_lshrrev_b32_e32 v4, 30, v4
	v_add_nc_u32_e32 v4, v7, v4
.LBB0_6:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s2
; %bb.7:
	v_mul_f32_e64 v3, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v3
	v_fma_f32 v3, 0xbfc90fda, v4, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v4, 0xb3a22168, v3
	v_fmamk_f32 v3, v4, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v4, v4
; %bb.8:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v5, v3, v3 :: v_dual_and_b32 v8, 1, v4
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_lshlrev_b32_e32 v4, 30, v4
	v_fmaak_f32 v6, s0, v5, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v4, 0x80000000, v4
	v_fmaak_f32 v6, v5, v6, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v7, s1, v5, 0xbab64f3b :: v_dual_mul_f32 v6, v5, v6
	v_fmaak_f32 v7, v5, v7, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v3, v3, v6
	v_fmaak_f32 v7, v5, v7, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v5, v7, 1.0
	v_cndmask_b32_e64 v3, -v3, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v4, v3
	v_add_f32_e32 v3, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
.LBB0_9:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x4f800000, v3
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v5, -1, v4
	v_add_nc_u32_e32 v6, 1, v4
	v_fma_f32 v7, -v5, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v6, v4, v3
	v_cmp_ge_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v4, v5, s0
	v_cmp_lt_f32_e64 s0, 0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v6, s0
	v_mul_f32_e32 v5, 0x37800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x260
	v_cndmask_b32_e32 v3, v4, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_APfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8kernel_APfii, .Lfunc_end0-_Z8kernel_APfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1380
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8kernel_BPfii         ; -- Begin function _Z8kernel_BPfii
	.globl	_Z8kernel_BPfii
	.p2align	8
	.type	_Z8kernel_BPfii,@function
_Z8kernel_BPfii:                        ; @_Z8kernel_BPfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_and_b32_e32 v3, 1, v3
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v3
                                        ; implicit-def: $vgpr3
	global_load_b32 v2, v[0:1], off
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
	v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v2, v3
	v_log_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x3f317217, v3
	v_cmp_gt_f32_e64 s0, 0x7f800000, |v3|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0x3f317217, v3, -v4
	v_fmamk_f32 v5, v3, 0x3377d1cf, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	v_cndmask_b32_e64 v3, v3, v4, s0
	v_cndmask_b32_e64 v4, 0, 0x41b17218, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v4
	v_add_f32_e32 v3, 1.0, v3
.LBB1_2:                                ; %Flow13
	s_and_not1_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_8
; %bb.3:
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s3, exec_lo, s1
	s_cbranch_execz .LBB1_5
; %bb.4:
	v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v10, 0x7fffffff, v2
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v13, v10, s0, 0x800000
	v_lshrrev_b32_e32 v10, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v13, 0
	v_add_nc_u32_e32 v11, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v13, v[4:5]
	v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v7
	v_add_nc_u32_e32 v12, v12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v13, v[4:5]
	v_cmp_lt_u32_e64 s0, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s0
	v_dual_mov_b32 v4, v8 :: v_dual_cndmask_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v12
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v13, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v14
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v13, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v6, v3, s0
	v_mov_b32_e32 v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x4e441529, v13, v[4:5]
	v_mov_b32_e32 v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0xa2f9836e, v13, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v5, v10, v8 :: v_dual_add_nc_u32 v4, v4, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v12, v10
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v11, v5, s0
	v_cndmask_b32_e64 v10, v10, v11, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, v5, v9, s0
	v_sub_nc_u32_e32 v11, 32, v4
	v_cndmask_b32_e64 v9, v9, v6, s0
	v_cndmask_b32_e64 v10, v10, v8, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v5, s1
	v_cndmask_b32_e64 v5, v5, v9, s1
	v_cndmask_b32_e64 v3, v9, v3, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v10, v8, v11
	v_alignbit_b32 v7, v8, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, v12, v10, vcc_lo
	v_alignbit_b32 v10, v5, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_bfe_u32 v7, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	v_alignbit_b32 v8, v4, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, 0, v7
	v_alignbit_b32 v6, v6, v5, 30
	v_alignbit_b32 v3, v5, v3, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v9
	v_xor_b32_e32 v5, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v9
	v_clz_i32_u32_e32 v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v6, 31, v10
	v_lshlrev_b32_e32 v12, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v8, v5, v6
	v_alignbit_b32 v3, v5, v3, v6
	v_lshrrev_b32_e32 v6, 29, v4
	v_alignbit_b32 v5, v8, v3, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v6, 31, v6
	v_lshrrev_b32_e32 v8, 9, v8
	v_clz_i32_u32_e32 v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v11, 0.5, v6
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v12
	v_sub_nc_u32_e32 v13, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v5, v3, v13
	v_or_b32_e32 v5, v8, v11
	v_add_lshl_u32 v8, v9, v10, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 9, v3
	v_mul_f32_e32 v9, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v8
	v_fma_f32 v8, 0x3fc90fda, v5, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 0x33000000, v3
	v_fmamk_f32 v5, v5, 0x33a22168, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v3, v3, v6
	v_fmac_f32_e32 v5, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v9, v5
	v_lshrrev_b32_e32 v4, 30, v4
	v_add_nc_u32_e32 v4, v7, v4
.LBB1_5:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s3
; %bb.6:
	v_mul_f32_e64 v3, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v3
	v_fma_f32 v3, 0xbfc90fda, v4, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v4, 0xb3a22168, v3
	v_fmamk_f32 v3, v4, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v4, v4
; %bb.7:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v5, v3, v3 :: v_dual_and_b32 v8, 1, v4
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_lshlrev_b32_e32 v4, 30, v4
	v_fmaak_f32 v6, s0, v5, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v4, 0x80000000, v4
	v_fmaak_f32 v6, v5, v6, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v7, s1, v5, 0xbab64f3b :: v_dual_mul_f32 v6, v5, v6
	v_fmaak_f32 v7, v5, v7, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v3, v3, v6
	v_fmaak_f32 v7, v5, v7, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v5, v7, 1.0
	v_cndmask_b32_e64 v3, -v3, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v4, v3
	v_add_f32_e32 v3, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
.LBB1_8:                                ; %Flow14
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x4f800000, v3
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v5, -1, v4
	v_add_nc_u32_e32 v6, 1, v4
	v_fma_f32 v7, -v5, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v6, v4, v3
	v_cmp_ge_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v4, v5, s0
	v_cmp_lt_f32_e64 s0, 0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v6, s0
	v_mul_f32_e32 v5, 0x37800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x260
	v_cndmask_b32_e32 v3, v4, v3, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_BPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8kernel_BPfii, .Lfunc_end1-_Z8kernel_BPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1364
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8kernel_CPfii         ; -- Begin function _Z8kernel_CPfii
	.globl	_Z8kernel_CPfii
	.p2align	8
	.type	_Z8kernel_CPfii,@function
_Z8kernel_CPfii:                        ; @_Z8kernel_CPfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s1, exec_lo
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v11, 0x7fffffff, v2
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v14, v11, s0, 0x800000
	v_lshrrev_b32_e32 v11, 23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, 0xfe5163ab, v14, 0
	v_add_nc_u32_e32 v12, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v12
	v_mad_u64_u32 v[7:8], null, 0x3c439041, v14, v[5:6]
	v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v5, v8
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, 0xdb629599, v14, v[5:6]
	v_cmp_lt_u32_e64 s0, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, 0, 0xffffffe0, s0
	v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v15, v15, v13
	v_mad_u64_u32 v[9:10], null, 0xf534ddc0, v14, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v15
	v_mov_b32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v9, v7, vcc_lo
	v_mad_u64_u32 v[10:11], null, 0xfc2757d1, v14, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v7, v4, s0
	v_mov_b32_e32 v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0x4e441529, v14, v[5:6]
	v_mov_b32_e32 v5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0xa2f9836e, v14, v[5:6]
	v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
	v_cndmask_b32_e32 v10, v10, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v12, v6, s0
	v_cndmask_b32_e64 v11, v11, v12, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v6, v10, s0
	v_sub_nc_u32_e32 v12, 32, v5
	v_cndmask_b32_e64 v10, v10, v7, s0
	v_cndmask_b32_e64 v11, v11, v9, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v6, s1
	v_cndmask_b32_e64 v6, v6, v10, s1
	v_cndmask_b32_e64 v4, v10, v4, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v11, v9, v12
	v_alignbit_b32 v8, v9, v6, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v13, v11, vcc_lo
	v_alignbit_b32 v11, v6, v4, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v8, v9, vcc_lo
	v_bfe_u32 v8, v5, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v11, v6, vcc_lo
	v_alignbit_b32 v9, v5, v7, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, 0, v8
	v_alignbit_b32 v7, v7, v6, 30
	v_alignbit_b32 v4, v6, v4, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v10
	v_xor_b32_e32 v6, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v10
	v_clz_i32_u32_e32 v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v7, 31, v11
	v_lshlrev_b32_e32 v13, 23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v9, v9, v6, v7
	v_alignbit_b32 v4, v6, v4, v7
	v_lshrrev_b32_e32 v7, 29, v5
	v_alignbit_b32 v6, v9, v4, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v7, 31, v7
	v_lshrrev_b32_e32 v9, 9, v9
	v_clz_i32_u32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v12, 0.5, v7
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v12, v13
	v_sub_nc_u32_e32 v14, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v6, v4, v14
	v_or_b32_e32 v6, v9, v12
	v_add_lshl_u32 v9, v10, v11, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v4, 9, v4
	v_mul_f32_e32 v10, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v9
	v_fma_f32 v9, 0x3fc90fda, v6, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 0x33000000, v4
	v_fmamk_f32 v6, v6, 0x33a22168, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v4, v4, v7
	v_fmac_f32_e32 v6, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v10, v6
	v_lshrrev_b32_e32 v5, 30, v5
	v_add_nc_u32_e32 v5, v8, v5
.LBB2_2:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s2
; %bb.3:
	v_mul_f32_e64 v4, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v5, v4
	v_fma_f32 v4, 0xbfc90fda, v5, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v4, v5, 0xb3a22168, v4
	v_fmamk_f32 v4, v5, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v5, v5
; %bb.4:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v3
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_mul_f32_e32 v7, v4, v4
	v_and_b32_e32 v11, 1, v5
	v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v8, s0, v7, 0x3c0881c4 :: v_dual_lshlrev_b32 v5, 30, v5
	v_cmp_eq_u32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v6, v3, v6 :: v_dual_and_b32 v5, 0x80000000, v5
	v_fmaak_f32 v8, v7, v8, 0xbe2aaa9d
	v_fmaak_f32 v9, s1, v7, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_log_f32_e32 v6, v6
	v_mul_f32_e32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v9, v7, v9, 0x3d2aabf7 :: v_dual_fmac_f32 v4, v4, v8
	v_fmaak_f32 v9, v7, v9, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v7, v9, 1.0
	v_cndmask_b32_e64 v4, -v4, v7, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_xor_b32_e32 v4, v5, v4
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	v_mul_f32_e32 v10, 0x3f317217, v6
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, 1.0, v4
	v_fma_f32 v12, 0x3f317217, v6, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v8, v6, 0x3377d1cf, v12
	v_add_f32_e32 v7, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	v_sub_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v5
	v_mul_f32_e32 v7, 0x4f800000, v5
	v_cmp_gt_f32_e64 s0, 0xf800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v7, s0
	v_sqrt_f32_e32 v7, v5
	s_waitcnt_depctr 0xfff
	v_dual_cndmask_b32 v4, 0x7fc00000, v4 :: v_dual_add_nc_u32 v9, -1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v6, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	v_add_nc_u32_e32 v12, 1, v7
	v_fma_f32 v13, -v9, v7, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_sqrt_f32_e32 v6, v4
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v8, -1, v6
	v_add_nc_u32_e32 v10, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, -v8, v6, v4
	v_fma_f32 v14, -v10, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v11
	v_cndmask_b32_e64 v6, v6, v8, s1
	v_cmp_ge_f32_e64 s1, 0, v13
	v_fma_f32 v8, -v12, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v7, v9, s1
	v_cmp_lt_f32_e64 s1, 0, v14
	v_cndmask_b32_e64 v6, v6, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s1, 0, v8
	v_mul_f32_e32 v8, 0x37800000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_dual_cndmask_b32 v6, v6, v8 :: v_dual_mul_f32 v9, 0x37800000, v7
	v_cmp_class_f32_e64 vcc_lo, v4, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v7, v9, s0
	v_cndmask_b32_e32 v4, v6, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v2, v4 :: v_dual_cndmask_b32 v5, v7, v5
	v_add_f32_e32 v3, v3, v5
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_CPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8kernel_CPfii, .Lfunc_end2-_Z8kernel_CPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1452
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8kernel_DPfii         ; -- Begin function _Z8kernel_DPfii
	.globl	_Z8kernel_DPfii
	.p2align	8
	.type	_Z8kernel_DPfii,@function
_Z8kernel_DPfii:                        ; @_Z8kernel_DPfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x0
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	v_add_co_u32 v4, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s1, exec_lo
	global_load_b128 v[0:3], v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v13, 0x7fffffff, v0
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v16, v13, s0, 0x800000
	v_lshrrev_b32_e32 v13, 23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v16, 0
	v_add_nc_u32_e32 v14, 0xffffff88, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v14
	v_mad_u64_u32 v[9:10], null, 0x3c439041, v16, v[7:8]
	v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v10
	v_add_nc_u32_e32 v15, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xdb629599, v16, v[7:8]
	v_cmp_lt_u32_e64 s0, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s0
	v_dual_mov_b32 v7, v11 :: v_dual_cndmask_b32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v17, v17, v15
	v_mad_u64_u32 v[11:12], null, 0xf534ddc0, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v17
	v_mov_b32_e32 v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	v_mad_u64_u32 v[12:13], null, 0xfc2757d1, v16, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v9, v6, s0
	v_mov_b32_e32 v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0x4e441529, v16, v[7:8]
	v_mov_b32_e32 v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0xa2f9836e, v16, v[7:8]
	v_cndmask_b32_e64 v7, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v8, v13, v11 :: v_dual_add_nc_u32 v7, v7, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v13, v15, v13
	v_cndmask_b32_e32 v12, v12, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v14, v8, s0
	v_cndmask_b32_e64 v13, v13, v14, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, v12, s0
	v_sub_nc_u32_e32 v14, 32, v7
	v_cndmask_b32_e64 v12, v12, v9, s0
	v_cndmask_b32_e64 v13, v13, v11, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v8, s1
	v_cndmask_b32_e64 v8, v8, v12, s1
	v_cndmask_b32_e64 v6, v12, v6, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v13, v11, v14
	v_alignbit_b32 v10, v11, v8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, v15, v13, vcc_lo
	v_alignbit_b32 v13, v8, v6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v10, v11, vcc_lo
	v_bfe_u32 v10, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v13, v8, vcc_lo
	v_alignbit_b32 v11, v7, v9, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v12, 0, v10
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v6, v8, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v11, v11, v12
	v_xor_b32_e32 v8, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v12
	v_clz_i32_u32_e32 v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v13, 32, v13
	v_sub_nc_u32_e32 v9, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v11, v11, v8, v9
	v_alignbit_b32 v6, v8, v6, v9
	v_lshrrev_b32_e32 v9, 29, v7
	v_alignbit_b32 v8, v11, v6, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v9, 31, v9
	v_lshrrev_b32_e32 v11, 9, v11
	v_clz_i32_u32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v9
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v15
	v_sub_nc_u32_e32 v16, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v8, v6, v16
	v_or_b32_e32 v8, v11, v14
	v_add_lshl_u32 v11, v12, v13, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v6, 9, v6
	v_mul_f32_e32 v12, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v11
	v_fma_f32 v11, 0x3fc90fda, v8, -v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0x33000000, v6
	v_fmamk_f32 v8, v8, 0x33a22168, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, v6, v9
	v_fmac_f32_e32 v8, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v12, v8
	v_lshrrev_b32_e32 v7, 30, v7
	v_add_nc_u32_e32 v7, v10, v7
.LBB3_2:                                ; %Flow34
	s_and_not1_saveexec_b32 s0, s2
; %bb.3:
	v_mul_f32_e64 v6, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v6
	v_fma_f32 v6, 0xbfc90fda, v7, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
; %bb.4:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s2, exec_lo, s1
	s_cbranch_execz .LBB3_6
; %bb.5:
	v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v15, 0x7fffffff, v2
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v18, v15, s0, 0x800000
	v_lshrrev_b32_e32 v15, 23, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v18, 0
	v_add_nc_u32_e32 v16, 0xffffff88, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v16
	v_mad_u64_u32 v[11:12], null, 0x3c439041, v18, v[9:10]
	v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v12
	v_add_nc_u32_e32 v17, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[9:10]
	v_cmp_lt_u32_e64 s0, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s0
	v_dual_mov_b32 v9, v13 :: v_dual_cndmask_b32 v8, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v19, v17
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v19
	v_mov_b32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v13, v11, vcc_lo
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, v11, v8, s0
	v_mov_b32_e32 v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[9:10]
	v_mov_b32_e32 v9, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[9:10]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
	v_cndmask_b32_e32 v14, v14, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, v16, v10, s0
	v_cndmask_b32_e64 v15, v15, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s0
	v_sub_nc_u32_e32 v16, 32, v9
	v_cndmask_b32_e64 v14, v14, v11, s0
	v_cndmask_b32_e64 v15, v15, v13, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, v10, s1
	v_cndmask_b32_e64 v10, v10, v14, s1
	v_cndmask_b32_e64 v8, v14, v8, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v15, v13, v16
	v_alignbit_b32 v12, v13, v10, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v9, v17, v15, vcc_lo
	v_alignbit_b32 v15, v10, v8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v12, v13, vcc_lo
	v_bfe_u32 v12, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v15, v10, vcc_lo
	v_alignbit_b32 v13, v9, v11, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, 0, v12
	v_alignbit_b32 v11, v11, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v13, v13, v14
	v_xor_b32_e32 v10, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v14
	v_clz_i32_u32_e32 v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v15, 32, v15
	v_sub_nc_u32_e32 v11, 31, v15
	v_lshlrev_b32_e32 v17, 23, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v13, v13, v10, v11
	v_alignbit_b32 v8, v10, v8, v11
	v_lshrrev_b32_e32 v11, 29, v9
	v_alignbit_b32 v10, v13, v8, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v13, 9, v13
	v_clz_i32_u32_e32 v14, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v16, 0.5, v11
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, v16, v17
	v_sub_nc_u32_e32 v18, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v10, v8, v18
	v_or_b32_e32 v10, v13, v16
	v_add_lshl_u32 v13, v14, v15, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v8, 9, v8
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v13
	v_fma_f32 v13, 0x3fc90fda, v10, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 0x33000000, v8
	v_fmamk_f32 v10, v10, 0x33a22168, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v8, v8, v11
	v_fmac_f32_e32 v10, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v14, v10
	v_lshrrev_b32_e32 v9, 30, v9
	v_add_nc_u32_e32 v9, v12, v9
.LBB3_6:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s2
; %bb.7:
	v_mul_f32_e64 v8, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v9, v8
	v_fma_f32 v8, 0xbfc90fda, v9, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v8, v9, 0xb3a22168, v8
	v_fmamk_f32 v8, v9, 0xa7c234c4, v8
	v_cvt_i32_f32_e32 v9, v9
; %bb.8:                                ; %_ZL4cosff.exit21
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1
	v_cmp_gt_f32_e64 s0, 0x800000, v3
	s_mov_b32 s2, 0xb94c1982
	v_dual_mul_f32 v13, v8, v8 :: v_dual_and_b32 v14, 1, v9
	v_cndmask_b32_e64 v10, 1.0, 0x4f800000, vcc_lo
	v_lshlrev_b32_e32 v11, 30, v7
	v_dual_mul_f32 v12, v6, v6 :: v_dual_and_b32 v7, 1, v7
	v_cndmask_b32_e64 v15, 1.0, 0x4f800000, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v10, v1, v10 :: v_dual_lshlrev_b32 v9, 30, v9
	v_cndmask_b32_e64 v16, 0, 0x41b17218, vcc_lo
	v_fmaak_f32 v18, s2, v12, 0x3c0881c4
	s_mov_b32 s1, 0x37d75334
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_log_f32_e32 v10, v10
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_and_b32_e32 v9, 0x80000000, v9
	v_mul_f32_e32 v15, v3, v15
	v_log_f32_e32 v15, v15
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v20, 0x3f317217, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v22, 0x3f317217, v10, -v20
	v_fmac_f32_e32 v22, 0x3377d1cf, v10
	v_fmaak_f32 v19, s2, v13, 0x3c0881c4
	v_fmaak_f32 v18, v12, v18, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v18, v12, v18 :: v_dual_and_b32 v11, 0x80000000, v11
	v_dual_fmaak_f32 v17, s1, v12, 0xbab64f3b :: v_dual_fmac_f32 v6, v6, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v18, v20, v22 :: v_dual_fmaak_f32 v19, v13, v19, 0xbe2aaa9d
	v_fmaak_f32 v17, v12, v17, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v17, v12, v17, 0xbf000004
	v_fma_f32 v12, v12, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, -v6, v12, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v10|
	v_mul_f32_e32 v20, 0x3f317217, v15
	v_xor_b32_e32 v6, v11, v6
	v_dual_cndmask_b32 v7, v10, v18 :: v_dual_mul_f32 v10, v13, v19
	v_fmaak_f32 v21, s1, v13, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v6, 1.0, v6 :: v_dual_sub_f32 v7, v7, v16
	v_dual_fmac_f32 v8, v8, v10 :: v_dual_fmaak_f32 v17, v13, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v7, 1.0, v7 :: v_dual_fmaak_f32 v12, v13, v17, 0xbf000004
	v_fma_f32 v17, 0x3f317217, v15, -v20
	v_mul_f32_e32 v11, 0x4f800000, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v10, v13, v12, 1.0
	v_fmac_f32_e32 v17, 0x3377d1cf, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, -v8, v10, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	v_add_f32_e32 v10, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v9, v8
	v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v15|
	v_dual_add_f32 v8, 1.0, v8 :: v_dual_cndmask_b32 v9, v15, v10
	v_cndmask_b32_e64 v10, 0, 0x41b17218, s0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
	v_cmp_class_f32_e64 s0, v2, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v9, v10
	v_cndmask_b32_e64 v8, 0x7fc00000, v8, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, 1.0, v9
	v_cmp_gt_f32_e64 s0, 0xf800000, v6
	v_cmp_gt_f32_e64 s1, 0xf800000, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, 0x4f800000, v9
	v_cmp_gt_f32_e64 s2, 0xf800000, v9
	v_cndmask_b32_e64 v9, v9, v13, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v17, v9
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_mul_f32_e32 v11, 0x4f800000, v6
	v_sqrt_f32_e32 v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v6, v11, s0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v11, 0x4f800000, v8 :: v_dual_add_nc_u32 v22, 1, v17
	v_sqrt_f32_e32 v12, v6
	v_cndmask_b32_e64 v8, v8, v11, s1
	v_add_nc_u32_e32 v14, -1, v10
	v_add_nc_u32_e32 v11, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v15, v8
	v_fma_f32 v13, -v14, v10, v7
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v16, -1, v12
	v_fma_f32 v18, -v11, v10, v7
	v_cmp_ge_f32_e64 s3, 0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v13, -v16, v12, v6
	v_add_nc_u32_e32 v20, 1, v15
	v_cndmask_b32_e64 v10, v10, v14, s3
	v_cmp_lt_f32_e64 s3, 0, v18
	v_add_nc_u32_e32 v14, 1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v11, s3
	v_add_nc_u32_e32 v11, -1, v15
	v_cmp_ge_f32_e64 s3, 0, v13
	v_mul_f32_e32 v18, 0x37800000, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, -v11, v15, v8
	v_cndmask_b32_e64 v13, v12, v16, s3
	v_add_nc_u32_e32 v16, -1, v17
	v_fma_f32 v12, -v14, v12, v6
	v_cndmask_b32_e32 v10, v10, v18, vcc_lo
	v_cmp_ge_f32_e64 s3, 0, v19
	v_cmp_class_f32_e64 vcc_lo, v7, 0x260
	v_fma_f32 v21, -v16, v17, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v15, v11, s3
	v_fma_f32 v15, -v20, v15, v8
	v_cmp_ge_f32_e64 s3, 0, v21
	v_cndmask_b32_e32 v7, v10, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v16, v17, v16, s3
	v_cmp_lt_f32_e64 s3, 0, v12
	v_fma_f32 v17, -v22, v17, v9
	v_cndmask_b32_e64 v12, v13, v14, s3
	v_cmp_lt_f32_e64 s3, 0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x37800000, v12
	v_cndmask_b32_e64 v11, v11, v20, s3
	v_cmp_lt_f32_e64 s3, 0, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, v12, v14, s0
	v_cndmask_b32_e64 v13, v16, v22, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v15, 0x37800000, v11 :: v_dual_cndmask_b32 v6, v12, v6
	v_cmp_class_f32_e64 vcc_lo, v8, 0x260
	v_mul_f32_e32 v16, 0x37800000, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v11, v15, s1
	v_add_f32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v13, v16, s2
	v_cndmask_b32_e32 v8, v10, v8, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	v_dual_add_f32 v1, v1, v7 :: v_dual_add_f32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v9
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8kernel_DPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z8kernel_DPfii, .Lfunc_end3-_Z8kernel_DPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2752
; NumSgprs: 18
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8kernel_APfii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8kernel_APfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
