#include <iostream>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>

#define NUM_NODES 128

// Structure to represent an edge in the graph
struct Edge {
    int src, dest, weight;
};

// Function to perform edge betweenness centrality calculation
__global__ void edgeBetweennessCentrality(Edge* edges, float* betweenness, int numEdges, int numNodes) {
    extern __shared__ int s_betweenness[];
    int tid = threadIdx.x;

    // Initialize shared memory
    s_betweenness[tid] = 0;
    __syncthreads();

    // Each thread calculates the betweenness for a subset of edges
    int edgeIndex = blockIdx.x * blockDim.x + tid;
    if (edgeIndex < numEdges) {
        // Placeholder for betweenness calculation logic
        // This is a simplified version and does not fully implement the Girvan-Newman algorithm
        // For demonstration purposes, we just increment the betweenness for each edge
        atomicAdd(&betweenness[edgeIndex], 1.0f);
    }

    // Reduce betweenness values in shared memory
    for (int s = blockDim.x / 2; s > 0; s >>= 1) {
        if (tid < s) {
            atomicAdd(&s_betweenness[tid], s_betweenness[tid + s]);
        }
        __syncthreads();
    }

    // Write the reduced value back to global memory
    if (tid == 0) {
        atomicAdd(&betweenness[blockIdx.x], s_betweenness[0]);
    }
}

// Function to demonstrate the usage of the edgeBetweennessCentrality kernel
int main() {
    // Initialize graph edges
    Edge h_edges[NUM_NODES * (NUM_NODES - 1) / 2]; // Assuming a complete graph for demonstration
    for (int i = 0, k = 0; i < NUM_NODES; ++i) {
        for (int j = i + 1; j < NUM_NODES; ++j, ++k) {
            h_edges[k].src = i;
            h_edges[k].dest = j;
            h_edges[k].weight = 1; // Uniform weights for simplicity
        }
    }

    // Allocate memory for betweenness scores
    float h_betweenness[NUM_NODES * (NUM_NODES - 1) / 2] = {0.0f};

    // Allocate device memory
    Edge* d_edges;
    float* d_betweenness;
    cudaError_t err = cudaMalloc(&d_edges, sizeof(Edge) * NUM_NODES * (NUM_NODES - 1) / 2);
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate device memory for edges" << std::endl;
        return -1;
    }
    err = cudaMalloc(&d_betweenness, sizeof(float) * NUM_NODES * (NUM_NODES - 1) / 2);
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate device memory for betweenness" << std::endl;
        cudaFree(d_edges);
        return -1;
    }

    // Copy data to device
    err = cudaMemcpy(d_edges, h_edges, sizeof(Edge) * NUM_NODES * (NUM_NODES - 1) / 2, cudaMemcpyHostToDevice);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy edges to device" << std::endl;
        cudaFree(d_edges);
        cudaFree(d_betweenness);
        return -1;
    }

    // Launch kernel
    int numEdges = NUM_NODES * (NUM_NODES - 1) / 2;
    int threadsPerBlock = 256;
    int blocksPerGrid = (numEdges + threadsPerBlock - 1) / threadsPerBlock;
    size_t sharedMemSize = threadsPerBlock * sizeof(int);
    edgeBetweennessCentrality<<<blocksPerGrid, threadsPerBlock, sharedMemSize>>>(d_edges, d_betweenness, numEdges, NUM_NODES);
    err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "Kernel launch failed: " << cudaGetErrorString(err) << std::endl;
        cudaFree(d_edges);
        cudaFree(d_betweenness);
        return -1;
    }

    // Copy results back to host
    err = cudaMemcpy(h_betweenness, d_betweenness, sizeof(float) * NUM_NODES * (NUM_NODES - 1) / 2, cudaMemcpyDeviceToHost);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy betweenness scores back to host" << std::endl;
        cudaFree(d_edges);
        cudaFree(d_betweenness);
        return -1;
    }

    // Print results
    std::cout << "Betweenness scores for each edge:" << std::endl;
    for (int i = 0; i < numEdges; ++i) {
        std::cout << "Edge " << h_edges[i].src << "-" << h_edges[i].dest << ": " << h_betweenness[i] << std::endl;
    }

    // Free device memory
    cudaFree(d_edges);
    cudaFree(d_betweenness);

    return 0;
}
	.file	"tmpxft_000a3d73_00000000-6_cuda_code_070431.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4295:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4295:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z53__device_stub__Z25edgeBetweennessCentralityP4EdgePfiiP4EdgePfii
	.type	_Z53__device_stub__Z25edgeBetweennessCentralityP4EdgePfiiP4EdgePfii, @function
_Z53__device_stub__Z25edgeBetweennessCentralityP4EdgePfiiP4EdgePfii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z25edgeBetweennessCentralityP4EdgePfii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L3:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z53__device_stub__Z25edgeBetweennessCentralityP4EdgePfiiP4EdgePfii, .-_Z53__device_stub__Z25edgeBetweennessCentralityP4EdgePfiiP4EdgePfii
	.globl	_Z25edgeBetweennessCentralityP4EdgePfii
	.type	_Z25edgeBetweennessCentralityP4EdgePfii, @function
_Z25edgeBetweennessCentralityP4EdgePfii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z25edgeBetweennessCentralityP4EdgePfiiP4EdgePfii
	.cfi_endproc
.LFE3661:
	.size	_Z25edgeBetweennessCentralityP4EdgePfii, .-_Z25edgeBetweennessCentralityP4EdgePfii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Failed to allocate device memory for edges"
.LC1:
	.string	"Failed to allocate device memory for betweenness"
.LC2:
	.string	"Failed to copy edges to device"
.LC3:
	.string	"Kernel launch failed: "
.LC4:
	.string	"Failed to copy betweenness scores back to host"
.LC5:
	.string	"Betweenness scores for each edge:"
.LC6:
	.string	"Edge "
.LC7:
	.string	"-"
.LC8:
	.string	": "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leaq	-126976(%rsp), %r11
	.cfi_def_cfa 11, 127024
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$3120, %rsp
	.cfi_def_cfa_offset 130144
	xorl	%ecx, %ecx
	xorl	%edx, %edx
	movq	%fs:40, %rax
	movq	%rax, 130088(%rsp)
	xorl	%eax, %eax
	leaq	32552(%rsp), %rbx
.L12:
	movslq	%ecx, %rax
	movl	%edx, %edi
	incl	%edx
	imulq	$12, %rax, %rax
	movl	%edx, %esi
	addq	%rbx, %rax
.L10:
	cmpl	$128, %esi
	je	.L29
	movl	%esi, 4(%rax)
	incl	%esi
	addq	$12, %rax
	movl	%edi, -12(%rax)
	movl	$1, -4(%rax)
	jmp	.L10
.L29:
	addl	$127, %ecx
	subl	%edi, %ecx
	cmpl	$128, %edx
	jne	.L12
	xorl	%eax, %eax
	leaq	40(%rsp), %rdi
	movl	$8128, %ecx
	movl	$97536, %esi
	rep stosl
	movq	%rsp, %rdi
	leaq	40(%rsp), %r12
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L13
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	jmp	.L14
.L13:
	leaq	8(%rsp), %rdi
	movl	$32512, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L15
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	(%rsp), %rdi
.L26:
	call	cudaFree@PLT
.L14:
	orl	$-1, %eax
	jmp	.L9
.L15:
	movq	(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$97536, %edx
	call	cudaMemcpy@PLT
	leaq	.LC2(%rip), %rsi
	testl	%eax, %eax
	jne	.L28
	movl	$16777217, %edx
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	movl	$1024, %r8d
	salq	$8, %rdx
	salq	$5, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$128, %ecx
	movl	$8128, %edx
	call	_Z53__device_stub__Z25edgeBetweennessCentralityP4EdgePfiiP4EdgePfii
.L18:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L19
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	jmp	.L27
.L19:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$32512, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L20
	leaq	.LC4(%rip), %rsi
.L28:
	leaq	_ZSt4cerr(%rip), %rdi
.L27:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	jmp	.L26
.L20:
	leaq	_ZSt4cout(%rip), %r13
	leaq	.LC5(%rip), %rsi
	xorl	%ebp, %ebp
	movq	%r13, %rdi
	leaq	.LC6(%rip), %r14
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L21:
	movq	%r14, %rsi
	movq	%r13, %rdi
	addq	$12, %rbx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	-12(%rbx), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	-8(%rbx), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	(%r12,%rbp,4), %xmm0
	incq	%rbp
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpq	$8128, %rbp
	jne	.L21
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L9:
	movq	130088(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$130096, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z25edgeBetweennessCentralityP4EdgePfii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z25edgeBetweennessCentralityP4EdgePfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>


#define NUM_NODES 128

// Structure to represent an edge in the graph
struct Edge {
    int src, dest, weight;
};

// Function to perform edge betweenness centrality calculation
__global__ void edgeBetweennessCentrality(Edge* edges, float* betweenness, int numEdges, int numNodes) {
    extern __shared__ int s_betweenness[];
    int tid = threadIdx.x;

    // Initialize shared memory
    s_betweenness[tid] = 0;
    __syncthreads();

    // Each thread calculates the betweenness for a subset of edges
    int edgeIndex = blockIdx.x * blockDim.x + tid;
    if (edgeIndex < numEdges) {
        // Placeholder for betweenness calculation logic
        // This is a simplified version and does not fully implement the Girvan-Newman algorithm
        // For demonstration purposes, we just increment the betweenness for each edge
        atomicAdd(&betweenness[edgeIndex], 1.0f);
    }

    // Reduce betweenness values in shared memory
    for (int s = blockDim.x / 2; s > 0; s >>= 1) {
        if (tid < s) {
            atomicAdd(&s_betweenness[tid], s_betweenness[tid + s]);
        }
        __syncthreads();
    }

    // Write the reduced value back to global memory
    if (tid == 0) {
        atomicAdd(&betweenness[blockIdx.x], s_betweenness[0]);
    }
}

// Function to demonstrate the usage of the edgeBetweennessCentrality kernel
int main() {
    // Initialize graph edges
    Edge h_edges[NUM_NODES * (NUM_NODES - 1) / 2]; // Assuming a complete graph for demonstration
    for (int i = 0, k = 0; i < NUM_NODES; ++i) {
        for (int j = i + 1; j < NUM_NODES; ++j, ++k) {
            h_edges[k].src = i;
            h_edges[k].dest = j;
            h_edges[k].weight = 1; // Uniform weights for simplicity
        }
    }

    // Allocate memory for betweenness scores
    float h_betweenness[NUM_NODES * (NUM_NODES - 1) / 2] = {0.0f};

    // Allocate device memory
    Edge* d_edges;
    float* d_betweenness;
    hipError_t err = hipMalloc(&d_edges, sizeof(Edge) * NUM_NODES * (NUM_NODES - 1) / 2);
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate device memory for edges" << std::endl;
        return -1;
    }
    err = hipMalloc(&d_betweenness, sizeof(float) * NUM_NODES * (NUM_NODES - 1) / 2);
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate device memory for betweenness" << std::endl;
        hipFree(d_edges);
        return -1;
    }

    // Copy data to device
    err = hipMemcpy(d_edges, h_edges, sizeof(Edge) * NUM_NODES * (NUM_NODES - 1) / 2, hipMemcpyHostToDevice);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy edges to device" << std::endl;
        hipFree(d_edges);
        hipFree(d_betweenness);
        return -1;
    }

    // Launch kernel
    int numEdges = NUM_NODES * (NUM_NODES - 1) / 2;
    int threadsPerBlock = 256;
    int blocksPerGrid = (numEdges + threadsPerBlock - 1) / threadsPerBlock;
    size_t sharedMemSize = threadsPerBlock * sizeof(int);
    edgeBetweennessCentrality<<<blocksPerGrid, threadsPerBlock, sharedMemSize>>>(d_edges, d_betweenness, numEdges, NUM_NODES);
    err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "Kernel launch failed: " << hipGetErrorString(err) << std::endl;
        hipFree(d_edges);
        hipFree(d_betweenness);
        return -1;
    }

    // Copy results back to host
    err = hipMemcpy(h_betweenness, d_betweenness, sizeof(float) * NUM_NODES * (NUM_NODES - 1) / 2, hipMemcpyDeviceToHost);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy betweenness scores back to host" << std::endl;
        hipFree(d_edges);
        hipFree(d_betweenness);
        return -1;
    }

    // Print results
    std::cout << "Betweenness scores for each edge:" << std::endl;
    for (int i = 0; i < numEdges; ++i) {
        std::cout << "Edge " << h_edges[i].src << "-" << h_edges[i].dest << ": " << h_betweenness[i] << std::endl;
    }

    // Free device memory
    hipFree(d_edges);
    hipFree(d_betweenness);

    return 0;
}
	.text
	.file	"cuda_code_070431.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii # -- Begin function _Z40__device_stub__edgeBetweennessCentralityP4EdgePfii
	.type	_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii,@function
_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii: # @_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25edgeBetweennessCentralityP4EdgePfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii, .Lfunc_end0-_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$130064, %rsp                   # imm = 0x1FC10
	.cfi_def_cfa_offset 130096
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%ecx, %ecx
	leaq	32536(%rsp), %rax
	xorl	%edx, %edx
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
	movl	%ecx, %esi
	leal	1(%rsi), %ecx
	cmpl	$126, %esi
	ja	.LBB1_4
# %bb.2:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_1 Depth=1
	movl	$127, %r8d
	subl	%esi, %r8d
	movslq	%edx, %rdx
	leaq	(%rdx,%rdx,2), %rdi
	leaq	(%rax,%rdi,4), %rdi
	addl	%r8d, %edx
	movl	%ecx, %r8d
.LBB1_3:                                # %.lr.ph
                                        #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%esi, -8(%rdi)
	movl	%r8d, -4(%rdi)
	movl	$1, (%rdi)
	incl	%r8d
	addq	$12, %rdi
	cmpl	$128, %r8d
	jne	.LBB1_3
.LBB1_4:                                # %.loopexit
                                        #   in Loop: Header=BB1_1 Depth=1
	cmpl	$128, %ecx
	jne	.LBB1_1
# %bb.5:
	leaq	16(%rsp), %rdi
	movl	$32512, %edx                    # imm = 0x7F00
	xorl	%esi, %esi
	callq	memset@PLT
	movq	%rsp, %rdi
	movl	$97536, %esi                    # imm = 0x17D00
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_7
# %bb.6:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$42, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	jmp	.LBB1_23
.LBB1_7:
	leaq	8(%rsp), %rdi
	movl	$32512, %esi                    # imm = 0x7F00
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_9
# %bb.8:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$48, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	(%rsp), %rdi
	jmp	.LBB1_22
.LBB1_9:
	movq	(%rsp), %rdi
	leaq	32528(%rsp), %rsi
	movl	$97536, %edx                    # imm = 0x17D00
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_11
# %bb.10:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.2, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	jmp	.LBB1_20
.LBB1_11:
	movabsq	$4294967328, %rdi               # imm = 0x100000020
	leaq	224(%rdi), %rdx
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.12:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$8128, %edx                     # imm = 0x1FC0
	movl	$128, %ecx
	callq	_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii
.LBB1_13:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_16
# %bb.14:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_18
# %bb.15:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_19
.LBB1_16:
	movq	8(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$32512, %edx                    # imm = 0x7F00
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_25
# %bb.17:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.4, %esi
	movl	$46, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB1_21
.LBB1_18:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_19:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
.LBB1_20:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_21:
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
.LBB1_22:
	callq	hipFree
.LBB1_23:
	movl	$-1, %eax
.LBB1_24:
	addq	$130064, %rsp                   # imm = 0x1FC10
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB1_25:
	.cfi_def_cfa_offset 130096
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$33, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	leaq	32532(%rsp), %r14
	xorl	%r15d, %r15d
.LBB1_26:                               # =>This Inner Loop Header: Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	-4(%r14), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.7, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.8, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	16(%rsp,%r15,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r15
	addq	$12, %r14
	cmpq	$8128, %r15                     # imm = 0x1FC0
	jne	.LBB1_26
# %bb.27:
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB1_24
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25edgeBetweennessCentralityP4EdgePfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25edgeBetweennessCentralityP4EdgePfii,@object # @_Z25edgeBetweennessCentralityP4EdgePfii
	.section	.rodata,"a",@progbits
	.globl	_Z25edgeBetweennessCentralityP4EdgePfii
	.p2align	3, 0x0
_Z25edgeBetweennessCentralityP4EdgePfii:
	.quad	_Z40__device_stub__edgeBetweennessCentralityP4EdgePfii
	.size	_Z25edgeBetweennessCentralityP4EdgePfii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Failed to allocate device memory for edges"
	.size	.L.str, 43

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Failed to allocate device memory for betweenness"
	.size	.L.str.1, 49

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to copy edges to device"
	.size	.L.str.2, 31

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Kernel launch failed: "
	.size	.L.str.3, 23

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to copy betweenness scores back to host"
	.size	.L.str.4, 47

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Betweenness scores for each edge:"
	.size	.L.str.5, 34

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Edge "
	.size	.L.str.6, 6

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"-"
	.size	.L.str.7, 2

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	": "
	.size	.L.str.8, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z25edgeBetweennessCentralityP4EdgePfii"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__edgeBetweennessCentralityP4EdgePfii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25edgeBetweennessCentralityP4EdgePfii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25edgeBetweennessCentralityP4EdgePfii ; -- Begin function _Z25edgeBetweennessCentralityP4EdgePfii
	.globl	_Z25edgeBetweennessCentralityP4EdgePfii
	.p2align	8
	.type	_Z25edgeBetweennessCentralityP4EdgePfii,@function
_Z25edgeBetweennessCentralityP4EdgePfii: ; @_Z25edgeBetweennessCentralityP4EdgePfii
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s5, s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x8
	s_mov_b32 s2, s15
	v_lshl_add_u32 v5, v0, 2, 0
	s_mov_b32 s4, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_mov_b32_e32 v2, 0
	ds_store_b32 v5, v2
	v_cmp_gt_i32_e32 vcc_lo, s5, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v4, v[1:2], off
.LBB0_2:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, 1.0, v4
	global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v3, v4
	v_mov_b32_e32 v4, v3
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow33
	s_or_b32 exec_lo, exec_lo, s5
	s_cmp_lt_u32 s3, 2
	s_cbranch_scc1 .LBB0_7
.LBB0_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s4, s3, 1
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s4, v0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	v_lshl_add_u32 v1, s4, 2, v5
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	ds_add_u32 v5, v1
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_cmp_lt_u32 s3, 4
	s_mov_b32 s3, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
.LBB0_7:                                ; %._crit_edge
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_11
; %bb.8:
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s4, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s3, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s3
	s_cbranch_execz .LBB0_11
; %bb.9:
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[2:3], 2
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_bcnt1_i32_b32 s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_ubyte0_e32 v3, s2
	v_mov_b32_e32 v2, 0
	global_load_b32 v1, v2, s[0:1]
	ds_load_b32 v0, v2
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v3, v0, v3
.LBB0_10:                               ; %atomicrmw.start22
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v3
	global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_10
.LBB0_11:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25edgeBetweennessCentralityP4EdgePfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25edgeBetweennessCentralityP4EdgePfii, .Lfunc_end0-_Z25edgeBetweennessCentralityP4EdgePfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 452
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym s_betweenness
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25edgeBetweennessCentralityP4EdgePfii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z25edgeBetweennessCentralityP4EdgePfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
