#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>

#define LAYERS 5
#define NEURONS 128
#define BATCH_SIZE 256
#define LEARNING_RATE 0.01f

__device__ float sigmoid(float x) {
    return 1.0f / (1.0f + expf(-x));
}

__device__ float sigmoid_derivative(float x) {
    float s = sigmoid(x);
    return s * (1.0f - s);
}

__global__ void forward_pass(float* inputs, float* weights, float* biases, float* activations) {
    extern __shared__ float shared_data[];

    int tid = threadIdx.x;
    int bid = blockIdx.x;
    int neuron = tid % NEURONS;
    int layer = tid / NEURONS;

    if (layer < LAYERS) {
        float sum = 0.0f;
        if (layer == 0) {
            // Input layer
            for (int i = 0; i < NEURONS; i++) {
                sum += inputs[bid * NEURONS + i] * weights[layer * NEURONS * NEURONS + neuron * NEURONS + i];
            }
        } else {
            // Hidden layers
            for (int i = 0; i < NEURONS; i++) {
                sum += activations[(layer - 1) * NEURONS * BATCH_SIZE + bid * NEURONS + i] * weights[layer * NEURONS * NEURONS + neuron * NEURONS + i];
            }
        }
        sum += biases[layer * NEURONS + neuron];
        activations[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron] = sigmoid(sum);
    }
}

__global__ void backward_pass(float* inputs, float* weights, float* biases, float* activations, float* errors, float* deltas, float* gradients) {
    extern __shared__ float shared_data[];

    int tid = threadIdx.x;
    int bid = blockIdx.x;
    int neuron = tid % NEURONS;
    int layer = tid / NEURONS;

    if (layer < LAYERS) {
        float error = 0.0f;
        if (layer == LAYERS - 1) {
            // Output layer
            error = activations[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron] - inputs[bid * NEURONS + neuron];
        } else {
            // Hidden layers
            for (int i = 0; i < NEURONS; i++) {
                error += deltas[(layer + 1) * NEURONS * BATCH_SIZE + bid * NEURONS + i] * weights[(layer + 1) * NEURONS * NEURONS + i * NEURONS + neuron];
            }
        }
        float output = activations[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron];
        float delta = error * sigmoid_derivative(output);
        deltas[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron] = delta;

        if (layer == 0) {
            // Input layer
            for (int i = 0; i < NEURONS; i++) {
                gradients[layer * NEURONS * NEURONS + neuron * NEURONS + i] += inputs[bid * NEURONS + i] * delta;
            }
        } else {
            // Hidden layers
            for (int i = 0; i < NEURONS; i++) {
                gradients[layer * NEURONS * NEURONS + neuron * NEURONS + i] += activations[(layer - 1) * NEURONS * BATCH_SIZE + bid * NEURONS + i] * delta;
            }
        }
        gradients[layer * NEURONS + neuron] += delta;
    }
}

__global__ void update_weights(float* weights, float* biases, float* gradients, int num_batches) {
    int tid = threadIdx.x;
    int layer = tid / (NEURONS * NEURONS);
    int neuron = (tid % (NEURONS * NEURONS)) / NEURONS;
    int weight = tid % NEURONS;

    if (layer < LAYERS) {
        if (weight < NEURONS) {
            weights[layer * NEURONS * NEURONS + neuron * NEURONS + weight] -= LEARNING_RATE * gradients[layer * NEURONS * NEURONS + neuron * NEURONS + weight] / num_batches;
            gradients[layer * NEURONS * NEURONS + neuron * NEURONS + weight] = 0.0f;
        } else {
            biases[layer * NEURONS + neuron] -= LEARNING_RATE * gradients[layer * NEURONS + neuron] / num_batches;
            gradients[layer * NEURONS + neuron] = 0.0f;
        }
    }
}

int main() {
    int num_elements = NEURONS * NEURONS * LAYERS + NEURONS * LAYERS;
    int num_batches = BATCH_SIZE;

    float* h_inputs = new float[num_batches * NEURONS];
    float* h_weights = new float[num_elements];
    float* h_biases = new float[num_elements];
    float* h_activations = new float[num_batches * NEURONS * LAYERS];
    float* h_errors = new float[num_batches * NEURONS];
    float* h_deltas = new float[num_batches * NEURONS * LAYERS];
    float* h_gradients = new float[num_elements];

    float* d_inputs;
    float* d_weights;
    float* d_biases;
    float* d_activations;
    float* d_errors;
    float* d_deltas;
    float* d_gradients;

    cudaMalloc(&d_inputs, num_batches * NEURONS * sizeof(float));
    cudaMalloc(&d_weights, num_elements * sizeof(float));
    cudaMalloc(&d_biases, num_elements * sizeof(float));
    cudaMalloc(&d_activations, num_batches * NEURONS * LAYERS * sizeof(float));
    cudaMalloc(&d_errors, num_batches * NEURONS * sizeof(float));
    cudaMalloc(&d_deltas, num_batches * NEURONS * LAYERS * sizeof(float));
    cudaMalloc(&d_gradients, num_elements * sizeof(float));

    // Initialize inputs, weights, biases, and gradients
    curandGenerator_t gen;
    curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
    curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
    curandGenerateUniform(gen, d_inputs, num_batches * NEURONS);
    curandGenerateUniform(gen, d_weights, num_elements);
    curandGenerateUniform(gen, d_biases, num_elements);
    cudaMemset(d_gradients, 0, num_elements * sizeof(float));

    // Kernel launch configuration
    dim3 threadsPerBlock(NEURONS * LAYERS);
    dim3 numBlocks(num_batches);
    size_t sharedMemSize = NEURONS * sizeof(float);

    // Training loop
    int num_epochs = 1000;
    for (int epoch = 0; epoch < num_epochs; ++epoch) {
        forward_pass<<<numBlocks, threadsPerBlock, sharedMemSize>>>(d_inputs, d_weights, d_biases, d_activations);
        backward_pass<<<numBlocks, threadsPerBlock, sharedMemSize>>>(d_inputs, d_weights, d_biases, d_activations, d_errors, d_deltas, d_gradients);
        update_weights<<<(num_elements + 255) / 256, 256>>>(d_weights, d_biases, d_gradients, num_batches);
    }

    cudaDeviceSynchronize();

    // Free device memory
    cudaFree(d_inputs);
    cudaFree(d_weights);
    cudaFree(d_biases);
    cudaFree(d_activations);
    cudaFree(d_errors);
    cudaFree(d_deltas);
    cudaFree(d_gradients);

    // Free host memory
    delete[] h_inputs;
    delete[] h_weights;
    delete[] h_biases;
    delete[] h_activations;
    delete[] h_errors;
    delete[] h_deltas;
    delete[] h_gradients;

    return 0;
}
	.file	"tmpxft_000c6f25_00000000-6_cuda_code_036396.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3854:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3854:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7sigmoidf
	.type	_Z7sigmoidf, @function
_Z7sigmoidf:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3849:
	.size	_Z7sigmoidf, .-_Z7sigmoidf
	.globl	_Z18sigmoid_derivativef
	.type	_Z18sigmoid_derivativef, @function
_Z18sigmoid_derivativef:
.LFB4504:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z7sigmoidf
	.cfi_endproc
.LFE4504:
	.size	_Z18sigmoid_derivativef, .-_Z18sigmoid_derivativef
	.globl	_Z38__device_stub__Z12forward_passPfS_S_S_PfS_S_S_
	.type	_Z38__device_stub__Z12forward_passPfS_S_S_PfS_S_S_, @function
_Z38__device_stub__Z12forward_passPfS_S_S_PfS_S_S_:
.LFB3876:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12forward_passPfS_S_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L6:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3876:
	.size	_Z38__device_stub__Z12forward_passPfS_S_S_PfS_S_S_, .-_Z38__device_stub__Z12forward_passPfS_S_S_PfS_S_S_
	.globl	_Z12forward_passPfS_S_S_
	.type	_Z12forward_passPfS_S_S_, @function
_Z12forward_passPfS_S_S_:
.LFB3877:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z12forward_passPfS_S_S_PfS_S_S_
	.cfi_endproc
.LFE3877:
	.size	_Z12forward_passPfS_S_S_, .-_Z12forward_passPfS_S_S_
	.globl	_Z45__device_stub__Z13backward_passPfS_S_S_S_S_S_PfS_S_S_S_S_S_
	.type	_Z45__device_stub__Z13backward_passPfS_S_S_S_S_S_PfS_S_S_S_S_S_, @function
_Z45__device_stub__Z13backward_passPfS_S_S_S_S_S_PfS_S_S_S_S_S_:
.LFB3878:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z13backward_passPfS_S_S_S_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L12:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3878:
	.size	_Z45__device_stub__Z13backward_passPfS_S_S_S_S_S_PfS_S_S_S_S_S_, .-_Z45__device_stub__Z13backward_passPfS_S_S_S_S_S_PfS_S_S_S_S_S_
	.globl	_Z13backward_passPfS_S_S_S_S_S_
	.type	_Z13backward_passPfS_S_S_S_S_S_, @function
_Z13backward_passPfS_S_S_S_S_S_:
.LFB3879:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z13backward_passPfS_S_S_S_S_S_PfS_S_S_S_S_S_
	.cfi_endproc
.LFE3879:
	.size	_Z13backward_passPfS_S_S_S_S_S_, .-_Z13backward_passPfS_S_S_S_S_S_
	.globl	_Z39__device_stub__Z14update_weightsPfS_S_iPfS_S_i
	.type	_Z39__device_stub__Z14update_weightsPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14update_weightsPfS_S_iPfS_S_i:
.LFB3880:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14update_weightsPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L17:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3880:
	.size	_Z39__device_stub__Z14update_weightsPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14update_weightsPfS_S_iPfS_S_i
	.globl	_Z14update_weightsPfS_S_i
	.type	_Z14update_weightsPfS_S_i, @function
_Z14update_weightsPfS_S_i:
.LFB3881:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z14update_weightsPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3881:
	.size	_Z14update_weightsPfS_S_i, .-_Z14update_weightsPfS_S_i
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3851:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$131072, %esi
	movl	$16777217, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	salq	$8, %rbp
	movl	$1000, %ebx
	subq	$136, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$330240, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$330240, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$655360, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$655360, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$330240, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$100, %esi
	call	curandCreateGenerator@PLT
	movq	64(%rsp), %rdi
	movl	$1234, %esi
	call	curandSetPseudoRandomGeneratorSeed@PLT
	movq	8(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$32768, %edx
	call	curandGenerateUniform@PLT
	movq	16(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$82560, %edx
	call	curandGenerateUniform@PLT
	movq	24(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$82560, %edx
	call	curandGenerateUniform@PLT
	movq	56(%rsp), %rdi
	movl	$330240, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movl	$33554437, %eax
	movl	$1, 80(%rsp)
	salq	$7, %rax
	movq	%rbp, 84(%rsp)
	movq	%rax, 72(%rsp)
	movl	$1, 92(%rsp)
.L26:
	movl	80(%rsp), %ecx
	movq	72(%rsp), %rdx
	xorl	%r9d, %r9d
	movl	$512, %r8d
	movq	84(%rsp), %rdi
	movl	92(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z38__device_stub__Z12forward_passPfS_S_S_PfS_S_S_
.L23:
	movl	80(%rsp), %ecx
	movq	72(%rsp), %rdx
	xorl	%r9d, %r9d
	movl	$512, %r8d
	movq	84(%rsp), %rdi
	movl	92(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	%rax
	.cfi_def_cfa_offset 168
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	64(%rsp), %r9
	movq	56(%rsp), %r8
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z45__device_stub__Z13backward_passPfS_S_S_S_S_S_PfS_S_S_S_S_S_
	popq	%rdx
	.cfi_def_cfa_offset 168
	popq	%rcx
	.cfi_def_cfa_offset 160
.L24:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movabsq	$4294967619, %rdi
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	56(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$256, %ecx
	movq	16(%rsp), %rdi
	call	_Z39__device_stub__Z14update_weightsPfS_S_iPfS_S_i
.L25:
	decl	%ebx
	jne	.L26
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$136, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3851:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14update_weightsPfS_S_i"
.LC1:
	.string	"_Z13backward_passPfS_S_S_S_S_S_"
.LC2:
	.string	"_Z12forward_passPfS_S_S_"
.LC3:
	.string	"precalc_xorwow_matrix"
.LC4:
	.string	"precalc_xorwow_offset_matrix"
.LC5:
	.string	"mrg32k3aM1"
.LC6:
	.string	"mrg32k3aM2"
.LC7:
	.string	"mrg32k3aM1SubSeq"
.LC8:
	.string	"mrg32k3aM2SubSeq"
.LC9:
	.string	"mrg32k3aM1Seq"
.LC10:
	.string	"mrg32k3aM2Seq"
.LC11:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3883:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14update_weightsPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13backward_passPfS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12forward_passPfS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3883:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

#define LAYERS 5
#define NEURONS 128
#define BATCH_SIZE 256
#define LEARNING_RATE 0.01f

__device__ float sigmoid(float x) {
    return 1.0f / (1.0f + expf(-x));
}

__device__ float sigmoid_derivative(float x) {
    float s = sigmoid(x);
    return s * (1.0f - s);
}

__global__ void forward_pass(float* inputs, float* weights, float* biases, float* activations) {
    extern __shared__ float shared_data[];

    int tid = threadIdx.x;
    int bid = blockIdx.x;
    int neuron = tid % NEURONS;
    int layer = tid / NEURONS;

    if (layer < LAYERS) {
        float sum = 0.0f;
        if (layer == 0) {
            // Input layer
            for (int i = 0; i < NEURONS; i++) {
                sum += inputs[bid * NEURONS + i] * weights[layer * NEURONS * NEURONS + neuron * NEURONS + i];
            }
        } else {
            // Hidden layers
            for (int i = 0; i < NEURONS; i++) {
                sum += activations[(layer - 1) * NEURONS * BATCH_SIZE + bid * NEURONS + i] * weights[layer * NEURONS * NEURONS + neuron * NEURONS + i];
            }
        }
        sum += biases[layer * NEURONS + neuron];
        activations[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron] = sigmoid(sum);
    }
}

__global__ void backward_pass(float* inputs, float* weights, float* biases, float* activations, float* errors, float* deltas, float* gradients) {
    extern __shared__ float shared_data[];

    int tid = threadIdx.x;
    int bid = blockIdx.x;
    int neuron = tid % NEURONS;
    int layer = tid / NEURONS;

    if (layer < LAYERS) {
        float error = 0.0f;
        if (layer == LAYERS - 1) {
            // Output layer
            error = activations[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron] - inputs[bid * NEURONS + neuron];
        } else {
            // Hidden layers
            for (int i = 0; i < NEURONS; i++) {
                error += deltas[(layer + 1) * NEURONS * BATCH_SIZE + bid * NEURONS + i] * weights[(layer + 1) * NEURONS * NEURONS + i * NEURONS + neuron];
            }
        }
        float output = activations[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron];
        float delta = error * sigmoid_derivative(output);
        deltas[layer * NEURONS * BATCH_SIZE + bid * NEURONS + neuron] = delta;

        if (layer == 0) {
            // Input layer
            for (int i = 0; i < NEURONS; i++) {
                gradients[layer * NEURONS * NEURONS + neuron * NEURONS + i] += inputs[bid * NEURONS + i] * delta;
            }
        } else {
            // Hidden layers
            for (int i = 0; i < NEURONS; i++) {
                gradients[layer * NEURONS * NEURONS + neuron * NEURONS + i] += activations[(layer - 1) * NEURONS * BATCH_SIZE + bid * NEURONS + i] * delta;
            }
        }
        gradients[layer * NEURONS + neuron] += delta;
    }
}

__global__ void update_weights(float* weights, float* biases, float* gradients, int num_batches) {
    int tid = threadIdx.x;
    int layer = tid / (NEURONS * NEURONS);
    int neuron = (tid % (NEURONS * NEURONS)) / NEURONS;
    int weight = tid % NEURONS;

    if (layer < LAYERS) {
        if (weight < NEURONS) {
            weights[layer * NEURONS * NEURONS + neuron * NEURONS + weight] -= LEARNING_RATE * gradients[layer * NEURONS * NEURONS + neuron * NEURONS + weight] / num_batches;
            gradients[layer * NEURONS * NEURONS + neuron * NEURONS + weight] = 0.0f;
        } else {
            biases[layer * NEURONS + neuron] -= LEARNING_RATE * gradients[layer * NEURONS + neuron] / num_batches;
            gradients[layer * NEURONS + neuron] = 0.0f;
        }
    }
}

int main() {
    int num_elements = NEURONS * NEURONS * LAYERS + NEURONS * LAYERS;
    int num_batches = BATCH_SIZE;

    float* h_inputs = new float[num_batches * NEURONS];
    float* h_weights = new float[num_elements];
    float* h_biases = new float[num_elements];
    float* h_activations = new float[num_batches * NEURONS * LAYERS];
    float* h_errors = new float[num_batches * NEURONS];
    float* h_deltas = new float[num_batches * NEURONS * LAYERS];
    float* h_gradients = new float[num_elements];

    float* d_inputs;
    float* d_weights;
    float* d_biases;
    float* d_activations;
    float* d_errors;
    float* d_deltas;
    float* d_gradients;

    hipMalloc(&d_inputs, num_batches * NEURONS * sizeof(float));
    hipMalloc(&d_weights, num_elements * sizeof(float));
    hipMalloc(&d_biases, num_elements * sizeof(float));
    hipMalloc(&d_activations, num_batches * NEURONS * LAYERS * sizeof(float));
    hipMalloc(&d_errors, num_batches * NEURONS * sizeof(float));
    hipMalloc(&d_deltas, num_batches * NEURONS * LAYERS * sizeof(float));
    hipMalloc(&d_gradients, num_elements * sizeof(float));

    // Initialize inputs, weights, biases, and gradients
    hiprandGenerator_t gen;
    hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
    hiprandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
    hiprandGenerateUniform(gen, d_inputs, num_batches * NEURONS);
    hiprandGenerateUniform(gen, d_weights, num_elements);
    hiprandGenerateUniform(gen, d_biases, num_elements);
    hipMemset(d_gradients, 0, num_elements * sizeof(float));

    // Kernel launch configuration
    dim3 threadsPerBlock(NEURONS * LAYERS);
    dim3 numBlocks(num_batches);
    size_t sharedMemSize = NEURONS * sizeof(float);

    // Training loop
    int num_epochs = 1000;
    for (int epoch = 0; epoch < num_epochs; ++epoch) {
        forward_pass<<<numBlocks, threadsPerBlock, sharedMemSize>>>(d_inputs, d_weights, d_biases, d_activations);
        backward_pass<<<numBlocks, threadsPerBlock, sharedMemSize>>>(d_inputs, d_weights, d_biases, d_activations, d_errors, d_deltas, d_gradients);
        update_weights<<<(num_elements + 255) / 256, 256>>>(d_weights, d_biases, d_gradients, num_batches);
    }

    hipDeviceSynchronize();

    // Free device memory
    hipFree(d_inputs);
    hipFree(d_weights);
    hipFree(d_biases);
    hipFree(d_activations);
    hipFree(d_errors);
    hipFree(d_deltas);
    hipFree(d_gradients);

    // Free host memory
    delete[] h_inputs;
    delete[] h_weights;
    delete[] h_biases;
    delete[] h_activations;
    delete[] h_errors;
    delete[] h_deltas;
    delete[] h_gradients;

    return 0;
}
	.text
	.file	"cuda_code_036396.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__forward_passPfS_S_S_ # -- Begin function _Z27__device_stub__forward_passPfS_S_S_
	.type	_Z27__device_stub__forward_passPfS_S_S_,@function
_Z27__device_stub__forward_passPfS_S_S_: # @_Z27__device_stub__forward_passPfS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12forward_passPfS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__forward_passPfS_S_S_, .Lfunc_end0-_Z27__device_stub__forward_passPfS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__backward_passPfS_S_S_S_S_S_ # -- Begin function _Z28__device_stub__backward_passPfS_S_S_S_S_S_
	.type	_Z28__device_stub__backward_passPfS_S_S_S_S_S_,@function
_Z28__device_stub__backward_passPfS_S_S_S_S_S_: # @_Z28__device_stub__backward_passPfS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13backward_passPfS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__backward_passPfS_S_S_S_S_S_, .Lfunc_end1-_Z28__device_stub__backward_passPfS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__update_weightsPfS_S_i # -- Begin function _Z29__device_stub__update_weightsPfS_S_i
	.type	_Z29__device_stub__update_weightsPfS_S_i,@function
_Z29__device_stub__update_weightsPfS_S_i: # @_Z29__device_stub__update_weightsPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14update_weightsPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z29__device_stub__update_weightsPfS_S_i, .Lfunc_end2-_Z29__device_stub__update_weightsPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967552, %rbx               # imm = 0x100000100
	leaq	40(%rsp), %r12
	movl	$131072, %esi                   # imm = 0x20000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$330240, %esi                   # imm = 0x50A00
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r14
	movl	$330240, %esi                   # imm = 0x50A00
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$655360, %esi                   # imm = 0xA0000
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$655360, %esi                   # imm = 0xA0000
	callq	hipMalloc
	leaq	24(%rsp), %r13
	movl	$330240, %esi                   # imm = 0x50A00
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	64(%rsp), %rbp
	movq	%rbp, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hiprandCreateGenerator
	movq	(%rbp), %rdi
	movl	$1234, %esi                     # imm = 0x4D2
	callq	hiprandSetPseudoRandomGeneratorSeed
	movq	(%rbp), %rdi
	movq	(%r12), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	callq	hiprandGenerateUniform
	movq	(%rbp), %rdi
	movq	(%r15), %rsi
	movl	$82560, %edx                    # imm = 0x14280
	callq	hiprandGenerateUniform
	movq	(%rbp), %rdi
	movq	(%r14), %rsi
	movl	$82560, %edx                    # imm = 0x14280
	callq	hiprandGenerateUniform
	movq	(%r13), %rdi
	movl	$330240, %edx                   # imm = 0x50A00
	xorl	%esi, %esi
	callq	hipMemset
	movl	$1000, %ebp                     # imm = 0x3E8
	leaq	384(%rbx), %r14
	leaq	67(%rbx), %r15
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movl	$512, %r8d                      # imm = 0x200
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_3
# %bb.2:                                #   in Loop: Header=BB3_1 Depth=1
	movq	40(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rcx
	callq	_Z27__device_stub__forward_passPfS_S_S_
.LBB3_3:                                #   in Loop: Header=BB3_1 Depth=1
	movl	$512, %r8d                      # imm = 0x200
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_5
# %bb.4:                                #   in Loop: Header=BB3_1 Depth=1
	movq	40(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rcx
	movq	56(%rsp), %r8
	movq	48(%rsp), %r9
	movq	24(%rsp), %rax
	movq	%rax, (%rsp)
	callq	_Z28__device_stub__backward_passPfS_S_S_S_S_S_
.LBB3_5:                                #   in Loop: Header=BB3_1 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_7
# %bb.6:                                #   in Loop: Header=BB3_1 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	$256, %ecx                      # imm = 0x100
	callq	_Z29__device_stub__update_weightsPfS_S_i
.LBB3_7:                                #   in Loop: Header=BB3_1 Depth=1
	decl	%ebp
	jne	.LBB3_1
# %bb.8:
	callq	hipDeviceSynchronize
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12forward_passPfS_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13backward_passPfS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14update_weightsPfS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12forward_passPfS_S_S_,@object # @_Z12forward_passPfS_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z12forward_passPfS_S_S_
	.p2align	3, 0x0
_Z12forward_passPfS_S_S_:
	.quad	_Z27__device_stub__forward_passPfS_S_S_
	.size	_Z12forward_passPfS_S_S_, 8

	.type	_Z13backward_passPfS_S_S_S_S_S_,@object # @_Z13backward_passPfS_S_S_S_S_S_
	.globl	_Z13backward_passPfS_S_S_S_S_S_
	.p2align	3, 0x0
_Z13backward_passPfS_S_S_S_S_S_:
	.quad	_Z28__device_stub__backward_passPfS_S_S_S_S_S_
	.size	_Z13backward_passPfS_S_S_S_S_S_, 8

	.type	_Z14update_weightsPfS_S_i,@object # @_Z14update_weightsPfS_S_i
	.globl	_Z14update_weightsPfS_S_i
	.p2align	3, 0x0
_Z14update_weightsPfS_S_i:
	.quad	_Z29__device_stub__update_weightsPfS_S_i
	.size	_Z14update_weightsPfS_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12forward_passPfS_S_S_"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13backward_passPfS_S_S_S_S_S_"
	.size	.L__unnamed_2, 32

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14update_weightsPfS_S_i"
	.size	.L__unnamed_3, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__forward_passPfS_S_S_
	.addrsig_sym _Z28__device_stub__backward_passPfS_S_S_S_S_S_
	.addrsig_sym _Z29__device_stub__update_weightsPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12forward_passPfS_S_S_
	.addrsig_sym _Z13backward_passPfS_S_S_S_S_S_
	.addrsig_sym _Z14update_weightsPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12forward_passPfS_S_S_ ; -- Begin function _Z12forward_passPfS_S_S_
	.globl	_Z12forward_passPfS_S_S_
	.p2align	8
	.type	_Z12forward_passPfS_S_S_,@function
_Z12forward_passPfS_S_S_:               ; @_Z12forward_passPfS_S_S_
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 0x280, v0
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v4, 9, v0
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $sgpr11
	s_mov_b32 s8, exec_lo
	v_cmpx_lt_u32_e32 0x7f, v0
	s_xor_b32 s10, exec_lo, s8
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.preheader40
	v_lshlrev_b32_e32 v1, 8, v0
	s_lshl_b32 s11, s15, 7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, s8, s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0x38000, v1
	v_add3_u32 v5, 0xffff8000, s11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
	v_add_co_ci_u32_e64 v6, null, s3, 0, s8
	s_mov_b64 s[8:9], 0
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v7, vcc_lo, v3, s8
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v9, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v6, vcc_lo
	s_add_u32 s8, s8, 4
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[9:10], off
	s_addc_u32 s9, s9, 0
	s_cmpk_lg_i32 s8, 0x200
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v1, v7, v8
	s_cbranch_scc1 .LBB0_3
; %bb.4:                                ; %Flow
                                        ; implicit-def: $vgpr4
.LBB0_5:                                ; %Flow82
	s_or_saveexec_b32 s10, s10
	v_mov_b32_e32 v3, s11
	s_xor_b32 exec_lo, exec_lo, s10
	s_cbranch_execz .LBB0_9
; %bb.6:                                ; %.preheader
	s_lshl_b32 s8, s15, 7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, s2, s2, v4
	s_ashr_i32 s9, s8, 31
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[12:13], s[8:9], 2
	v_add_co_ci_u32_e64 v3, null, s3, 0, s2
	s_add_u32 s2, s0, s12
	s_addc_u32 s3, s1, s13
	s_mov_b64 s[0:1], 0
.LBB0_7:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	s_add_u32 s12, s2, s0
	s_addc_u32 s13, s3, s1
	s_add_u32 s0, s0, 4
	global_load_b32 v4, v[4:5], off
	s_load_b32 s9, s[12:13], 0x0
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x200
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v1, s9, v4
	s_cbranch_scc0 .LBB0_7
; %bb.8:                                ; %Flow81
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s8
.LBB0_9:                                ; %Flow83
	s_or_b32 exec_lo, exec_lo, s10
	v_lshlrev_b32_e32 v4, 2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	s_waitcnt lgkmcnt(0)
	global_load_b32 v4, v4, s[4:5]
	v_and_or_b32 v0, 0x7f, v0, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0xbfb8aa3b, v1
	v_fma_f32 v5, 0xbfb8aa3b, v1, -v4
	v_rndne_f32_e32 v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v4, v4, v6 :: v_dual_fmamk_f32 v5, v1, 0xb2a5705f, v5
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v1
	v_add_f32_e32 v4, v4, v5
	v_cvt_i32_f32_e32 v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v4, v5
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7f800000, v4, vcc_lo
	v_add_f32_e32 v4, 1.0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v1, null, v4, v4, 1.0
	v_div_scale_f32 v7, vcc_lo, 1.0, v4, 1.0
	v_rcp_f32_e32 v5, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v1, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v1, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v1, v6, v7
	v_ashrrev_i32_e32 v1, 31, v0
	v_div_fmas_f32 v2, v2, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_div_fixup_f32 v2, v2, v4, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12forward_passPfS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12forward_passPfS_S_S_, .Lfunc_end0-_Z12forward_passPfS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 648
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13backward_passPfS_S_S_S_S_S_ ; -- Begin function _Z13backward_passPfS_S_S_S_S_S_
	.globl	_Z13backward_passPfS_S_S_S_S_S_
	.p2align	8
	.type	_Z13backward_passPfS_S_S_S_S_S_,@function
_Z13backward_passPfS_S_S_S_S_S_:        ; @_Z13backward_passPfS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 0x280, v0
	s_cbranch_execz .LBB1_13
; %bb.1:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x18
	s_load_b128 s[0:3], s[0:1], 0x28
	v_and_b32_e32 v1, 0x380, v0
	v_and_b32_e32 v3, 0x7f, v0
	s_mov_b32 s11, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $sgpr10
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ne_u32_e32 0x200, v1
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB1_4
; %bb.2:                                ; %.preheader71
	v_lshlrev_b32_e32 v1, 8, v1
	v_lshlrev_b32_e32 v4, 7, v0
	s_lshl_b32 s10, s15, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_and_or_b32 v5, 0x1c000, v4, v3
	v_mov_b32_e32 v4, 0
	v_add3_u32 v1, v1, s10, 0x8000
	v_lshl_add_u32 v7, v5, 2, 0x10000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s0, v1
	v_add_co_u32 v1, s6, s6, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
	v_add_co_ci_u32_e64 v2, null, s7, 0, s6
	s_mov_b64 s[6:7], 0
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	global_load_b32 v9, v[1:2], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v1, vcc_lo, 0x200, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_cmpk_lg_i32 s6, 0x200
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v7, v9
	s_cbranch_scc1 .LBB1_3
.LBB1_4:                                ; %Flow118
	s_waitcnt lgkmcnt(0)
	s_or_saveexec_b32 s6, s11
	v_mov_b32_e32 v1, s10
	s_xor_b32 exec_lo, exec_lo, s6
	s_cbranch_execz .LBB1_6
; %bb.5:
	s_lshl_b32 s7, s15, 7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v1, s7, v3
	s_add_i32 s10, s7, 0x20000
	v_or_b32_e32 v4, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v1, v[1:2], off
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v4, v2, v1 :: v_dual_mov_b32 v1, s7
.LBB1_6:                                ; %.loopexit72
	s_or_b32 exec_lo, exec_lo, s6
	v_lshlrev_b32_e32 v2, 8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0x38000, v2
	v_add_nc_u32_e32 v2, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v2, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v7, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v3, v[7:8], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, 0xbfb8aa3b, v3
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v3
	v_fma_f32 v8, 0xbfb8aa3b, v3, -v7
	v_rndne_f32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v8, v3, 0xb2a5705f, v8
	v_sub_f32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v7, v8
	v_cvt_i32_f32_e32 v8, v9
	v_exp_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v3
	v_cndmask_b32_e32 v3, 0x7f800000, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, 1.0, v3
	v_div_scale_f32 v7, null, v3, v3, 1.0
	v_div_scale_f32 v10, vcc_lo, 1.0, v3, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v8
	v_fma_f32 v7, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v7, v7, v8, v9
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	v_div_fixup_f32 v3, v7, v3, 1.0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, 1.0, v3
	v_mul_f32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v3, v4, v3 :: v_dual_lshlrev_b32 v4, 9, v0
	global_store_b32 v[5:6], v3, off
	v_cmpx_lt_u32_e32 0x7f, v0
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB1_9
; %bb.7:                                ; %.preheader69
	v_add_nc_u32_e32 v1, 0xffff8000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v6, vcc_lo
	v_add_co_u32 v6, s0, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, null, s3, 0, s0
	s_mov_b64 s[0:1], 0
                                        ; implicit-def: $vgpr4
.LBB1_8:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v8, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v7, vcc_lo
	s_add_u32 s0, s0, 4
	global_load_b32 v1, v[8:9], off
	global_load_b32 v8, v[10:11], off
	s_addc_u32 s1, s1, 0
	s_cmpk_lg_i32 s0, 0x200
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v3, v1
                                        ; implicit-def: $vgpr1
	global_store_b32 v[10:11], v8, off
	s_cbranch_scc1 .LBB1_8
.LBB1_9:                                ; %Flow115
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB1_12
; %bb.10:                               ; %.preheader
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v4, s0, s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v5, null, s3, 0, s0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB1_11:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v1, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v8, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
	s_add_u32 s0, s0, 4
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[8:9], off
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x200
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v7, v3, v6
	global_store_b32 v[8:9], v7, off
	s_cbranch_scc0 .LBB1_11
.LBB1_12:                               ; %Flow116
	s_or_b32 exec_lo, exec_lo, s6
	v_lshlrev_b32_e32 v0, 2, v0
	global_load_b32 v1, v0, s[2:3]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, v3, v1
	global_store_b32 v0, v1, s[2:3]
.LBB1_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13backward_passPfS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13backward_passPfS_S_S_S_S_S_, .Lfunc_end1-_Z13backward_passPfS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1064
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14update_weightsPfS_S_i ; -- Begin function _Z14update_weightsPfS_S_i
	.globl	_Z14update_weightsPfS_S_i
	.p2align	8
	.type	_Z14update_weightsPfS_S_i,@function
_Z14update_weightsPfS_S_i:              ; @_Z14update_weightsPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s4, s[0:1], 0x18
	v_lshlrev_b32_e32 v0, 2, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v1, v0, s[2:3]
	v_cvt_f32_i32_e32 v3, s4
	global_load_b32 v2, v0, s[0:1]
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v1, 0xbc23d70a, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, v3, v3, v1
	v_div_scale_f32 v7, vcc_lo, v1, v3, v1
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v6, v7
	v_div_fmas_f32 v4, v4, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v4, v3, v1
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v1, v2, v1 :: v_dual_mov_b32 v2, 0
	s_clause 0x1
	global_store_b32 v0, v1, s[0:1]
	global_store_b32 v0, v2, s[2:3]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14update_weightsPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 5
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z14update_weightsPfS_S_i, .Lfunc_end2-_Z14update_weightsPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 208
; NumSgprs: 7
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 7
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12forward_passPfS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12forward_passPfS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13backward_passPfS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13backward_passPfS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14update_weightsPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     7
    .sgpr_spill_count: 0
    .symbol:         _Z14update_weightsPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
