#include <iostream>
#include <cuda_runtime.h>
#include <cooperative_groups.h>

using namespace cooperative_groups;

// Define a simple structure for 3D vector
struct Vec3 {
    float x, y, z;
};

// Constants for the simulation
const int N = 32;
const float G = 6.67430e-11f; // Gravitational constant
const float dt = 0.01f;       // Time step

// CUDA kernel for N-body simulation
__global__ void nbody_kernel(Vec3* pos, Vec3* vel, Vec3* acc, float* mass) {
    extern __shared__ float shared_mem[];
    Vec3* shared_pos = (Vec3*)shared_mem;
    Vec3* shared_vel = (Vec3*)(shared_pos + blockDim.x);
    Vec3* shared_acc = (Vec3*)(shared_vel + blockDim.x);
    float* shared_mass = (float*)(shared_acc + blockDim.x);

    // Load data into shared memory
    int idx = threadIdx.x;
    shared_pos[idx] = pos[blockIdx.x * blockDim.x + idx];
    shared_vel[idx] = vel[blockIdx.x * blockDim.x + idx];
    shared_mass[idx] = mass[blockIdx.x * blockDim.x + idx];
    __syncthreads();

    // Initialize acceleration
    shared_acc[idx] = {0.0f, 0.0f, 0.0f};
    __syncthreads();

    // Calculate acceleration using brute force
    grid_group grid = this_grid();
    for (int j = 0; j < N; ++j) {
        int jdx = j % blockDim.x;
        if (blockIdx.x * blockDim.x + idx != j) {
            Vec3 r = {shared_pos[jdx].x - shared_pos[idx].x,
                      shared_pos[jdx].y - shared_pos[idx].y,
                      shared_pos[jdx].z - shared_pos[idx].z};
            float r_squared = r.x * r.x + r.y * r.y + r.z * r.z + 1e-12f;
            float f = G * shared_mass[jdx] / powf(r_squared, 1.5f);
            shared_acc[idx].x += f * r.x;
            shared_acc[idx].y += f * r.y;
            shared_acc[idx].z += f * r.z;
        }
        __syncthreads();
    }

    // Update velocity and position
    shared_vel[idx].x += shared_acc[idx].x * dt;
    shared_vel[idx].y += shared_acc[idx].y * dt;
    shared_vel[idx].z += shared_acc[idx].z * dt;

    shared_pos[idx].x += shared_vel[idx].x * dt;
    shared_pos[idx].y += shared_vel[idx].y * dt;
    shared_pos[idx].z += shared_vel[idx].z * dt;
    __syncthreads();

    // Write back to global memory
    pos[blockIdx.x * blockDim.x + idx] = shared_pos[idx];
    vel[blockIdx.x * blockDim.x + idx] = shared_vel[idx];
}

// Main function to demonstrate the kernel's usage
int main() {
    // Allocate memory for position, velocity, acceleration, and mass
    Vec3* h_pos = new Vec3[N];
    Vec3* h_vel = new Vec3[N];
    Vec3* h_acc = new Vec3[N];
    float* h_mass = new float[N];

    // Initialize particles
    for (int i = 0; i < N; ++i) {
        h_pos[i] = {static_cast<float>(i), static_cast<float>(i), static_cast<float>(i)};
        h_vel[i] = {0.0f, 0.0f, 0.0f};
        h_mass[i] = 1.0f;
    }

    // Allocate device memory
    Vec3* d_pos, *d_vel, *d_acc;
    float* d_mass;
    cudaMalloc((void**)&d_pos, N * sizeof(Vec3));
    cudaMalloc((void**)&d_vel, N * sizeof(Vec3));
    cudaMalloc((void**)&d_acc, N * sizeof(Vec3));
    cudaMalloc((void**)&d_mass, N * sizeof(float));

    // Copy data to device
    cudaMemcpy(d_pos, h_pos, N * sizeof(Vec3), cudaMemcpyHostToDevice);
    cudaMemcpy(d_vel, h_vel, N * sizeof(Vec3), cudaMemcpyHostToDevice);
    cudaMemcpy(d_mass, h_mass, N * sizeof(float), cudaMemcpyHostToDevice);

    // Define block and grid sizes
    int blockSize = 32;
    int gridSize = (N + blockSize - 1) / blockSize;

    // Launch kernel
    nbody_kernel<<<gridSize, blockSize, 3 * blockSize * sizeof(Vec3) + blockSize * sizeof(float)>>>(d_pos, d_vel, d_acc, d_mass);

    // Check for errors
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    cudaMemcpy(h_pos, d_pos, N * sizeof(Vec3), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_vel, d_vel, N * sizeof(Vec3), cudaMemcpyDeviceToHost);

    // Print results
    std::cout << "Final positions and velocities:" << std::endl;
    for (int i = 0; i < N; ++i) {
        std::cout << "Particle " << i << ": "
                  << "Pos(" << h_pos[i].x << ", " << h_pos[i].y << ", " << h_pos[i].z << "), "
                  << "Vel(" << h_vel[i].x << ", " << h_vel[i].y << ", " << h_vel[i].z << ")" << std::endl;
    }

    // Free device memory
    cudaFree(d_pos);
    cudaFree(d_vel);
    cudaFree(d_acc);
    cudaFree(d_mass);

    // Free host memory
    delete[] h_pos;
    delete[] h_vel;
    delete[] h_acc;
    delete[] h_mass;

    return 0;
}
	.file	"tmpxft_00158218_00000000-6_cuda_code_046100.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6835:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE6835:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z44__device_stub__Z12nbody_kernelP4Vec3S0_S0_PfP4Vec3S0_S0_Pf
	.type	_Z44__device_stub__Z12nbody_kernelP4Vec3S0_S0_PfP4Vec3S0_S0_Pf, @function
_Z44__device_stub__Z12nbody_kernelP4Vec3S0_S0_PfP4Vec3S0_S0_Pf:
.LFB6857:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12nbody_kernelP4Vec3S0_S0_Pf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6857:
	.size	_Z44__device_stub__Z12nbody_kernelP4Vec3S0_S0_PfP4Vec3S0_S0_Pf, .-_Z44__device_stub__Z12nbody_kernelP4Vec3S0_S0_PfP4Vec3S0_S0_Pf
	.globl	_Z12nbody_kernelP4Vec3S0_S0_Pf
	.type	_Z12nbody_kernelP4Vec3S0_S0_Pf, @function
_Z12nbody_kernelP4Vec3S0_S0_Pf:
.LFB6858:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z12nbody_kernelP4Vec3S0_S0_PfP4Vec3S0_S0_Pf
	.cfi_endproc
.LFE6858:
	.size	_Z12nbody_kernelP4Vec3S0_S0_Pf, .-_Z12nbody_kernelP4Vec3S0_S0_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"CUDA error: "
.LC3:
	.string	"Final positions and velocities:"
.LC4:
	.string	"Particle "
.LC5:
	.string	": "
.LC6:
	.string	"Pos("
.LC7:
	.string	", "
.LC8:
	.string	"), "
.LC9:
	.string	"Vel("
.LC10:
	.string	")"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB6832:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$384, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$384, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$128, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movss	.LC1(%rip), %xmm1
	xorl	%edx, %edx
	movq	%rax, %r12
	movq	%rax, %rcx
	xorl	%eax, %eax
.L9:
	cvtsi2ssl	%edx, %xmm0
	incl	%edx
	movl	$0x00000000, (%rbx,%rax)
	addq	$4, %rcx
	movl	$0x00000000, 4(%rbx,%rax)
	movl	$0x00000000, 8(%rbx,%rax)
	movss	%xmm1, -4(%rcx)
	movss	%xmm0, 0(%rbp,%rax)
	movss	%xmm0, 4(%rbp,%rax)
	movss	%xmm0, 8(%rbp,%rax)
	addq	$12, %rax
	cmpl	$32, %edx
	jne	.L9
	movq	%rsp, %rdi
	movl	$384, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$384, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$384, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$128, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$128, %edx
	call	cudaMemcpy@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	movl	$1280, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z44__device_stub__Z12nbody_kernelP4Vec3S0_S0_PfP4Vec3S0_S0_Pf
.L10:
	call	cudaGetLastError@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	je	.L11
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L11:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movq	%rbp, %r14
	movl	$384, %edx
	movq	%rbx, %r13
	xorl	%r15d, %r15d
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L13:
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	addq	$12, %r14
	addq	$12, %r13
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r15d, %esi
	incl	%r15d
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	-12(%r14), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	-8(%r14), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	-4(%r14), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	-12(%r13), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	-8(%r13), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	-4(%r13), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpl	$32, %r15d
	jne	.L13
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L8:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6832:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z12nbody_kernelP4Vec3S0_S0_Pf"
.LC12:
	.string	"_ZN50_INTERNAL_72c57b2a_19_cuda_code_046100_cu_eb17c9284cuda3std3__419piecewise_constructE"
.LC13:
	.string	"_ZN50_INTERNAL_72c57b2a_19_cuda_code_046100_cu_eb17c9284cuda3std6ranges3__45__cpo4swapE"
.LC14:
	.string	"_ZN50_INTERNAL_72c57b2a_19_cuda_code_046100_cu_eb17c9284cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6860:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12nbody_kernelP4Vec3S0_S0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE6860:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>

using namespace cooperative_groups;

// Define a simple structure for 3D vector
struct Vec3 {
    float x, y, z;
};

// Constants for the simulation
const int N = 32;
const float G = 6.67430e-11f; // Gravitational constant
const float dt = 0.01f;       // Time step

// CUDA kernel for N-body simulation
__global__ void nbody_kernel(Vec3* pos, Vec3* vel, Vec3* acc, float* mass) {
    extern __shared__ float shared_mem[];
    Vec3* shared_pos = (Vec3*)shared_mem;
    Vec3* shared_vel = (Vec3*)(shared_pos + blockDim.x);
    Vec3* shared_acc = (Vec3*)(shared_vel + blockDim.x);
    float* shared_mass = (float*)(shared_acc + blockDim.x);

    // Load data into shared memory
    int idx = threadIdx.x;
    shared_pos[idx] = pos[blockIdx.x * blockDim.x + idx];
    shared_vel[idx] = vel[blockIdx.x * blockDim.x + idx];
    shared_mass[idx] = mass[blockIdx.x * blockDim.x + idx];
    __syncthreads();

    // Initialize acceleration
    shared_acc[idx] = {0.0f, 0.0f, 0.0f};
    __syncthreads();

    // Calculate acceleration using brute force
    grid_group grid = this_grid();
    for (int j = 0; j < N; ++j) {
        int jdx = j % blockDim.x;
        if (blockIdx.x * blockDim.x + idx != j) {
            Vec3 r = {shared_pos[jdx].x - shared_pos[idx].x,
                      shared_pos[jdx].y - shared_pos[idx].y,
                      shared_pos[jdx].z - shared_pos[idx].z};
            float r_squared = r.x * r.x + r.y * r.y + r.z * r.z + 1e-12f;
            float f = G * shared_mass[jdx] / powf(r_squared, 1.5f);
            shared_acc[idx].x += f * r.x;
            shared_acc[idx].y += f * r.y;
            shared_acc[idx].z += f * r.z;
        }
        __syncthreads();
    }

    // Update velocity and position
    shared_vel[idx].x += shared_acc[idx].x * dt;
    shared_vel[idx].y += shared_acc[idx].y * dt;
    shared_vel[idx].z += shared_acc[idx].z * dt;

    shared_pos[idx].x += shared_vel[idx].x * dt;
    shared_pos[idx].y += shared_vel[idx].y * dt;
    shared_pos[idx].z += shared_vel[idx].z * dt;
    __syncthreads();

    // Write back to global memory
    pos[blockIdx.x * blockDim.x + idx] = shared_pos[idx];
    vel[blockIdx.x * blockDim.x + idx] = shared_vel[idx];
}

// Main function to demonstrate the kernel's usage
int main() {
    // Allocate memory for position, velocity, acceleration, and mass
    Vec3* h_pos = new Vec3[N];
    Vec3* h_vel = new Vec3[N];
    Vec3* h_acc = new Vec3[N];
    float* h_mass = new float[N];

    // Initialize particles
    for (int i = 0; i < N; ++i) {
        h_pos[i] = {static_cast<float>(i), static_cast<float>(i), static_cast<float>(i)};
        h_vel[i] = {0.0f, 0.0f, 0.0f};
        h_mass[i] = 1.0f;
    }

    // Allocate device memory
    Vec3* d_pos, *d_vel, *d_acc;
    float* d_mass;
    hipMalloc((void**)&d_pos, N * sizeof(Vec3));
    hipMalloc((void**)&d_vel, N * sizeof(Vec3));
    hipMalloc((void**)&d_acc, N * sizeof(Vec3));
    hipMalloc((void**)&d_mass, N * sizeof(float));

    // Copy data to device
    hipMemcpy(d_pos, h_pos, N * sizeof(Vec3), hipMemcpyHostToDevice);
    hipMemcpy(d_vel, h_vel, N * sizeof(Vec3), hipMemcpyHostToDevice);
    hipMemcpy(d_mass, h_mass, N * sizeof(float), hipMemcpyHostToDevice);

    // Define block and grid sizes
    int blockSize = 32;
    int gridSize = (N + blockSize - 1) / blockSize;

    // Launch kernel
    nbody_kernel<<<gridSize, blockSize, 3 * blockSize * sizeof(Vec3) + blockSize * sizeof(float)>>>(d_pos, d_vel, d_acc, d_mass);

    // Check for errors
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    hipMemcpy(h_pos, d_pos, N * sizeof(Vec3), hipMemcpyDeviceToHost);
    hipMemcpy(h_vel, d_vel, N * sizeof(Vec3), hipMemcpyDeviceToHost);

    // Print results
    std::cout << "Final positions and velocities:" << std::endl;
    for (int i = 0; i < N; ++i) {
        std::cout << "Particle " << i << ": "
                  << "Pos(" << h_pos[i].x << ", " << h_pos[i].y << ", " << h_pos[i].z << "), "
                  << "Vel(" << h_vel[i].x << ", " << h_vel[i].y << ", " << h_vel[i].z << ")" << std::endl;
    }

    // Free device memory
    hipFree(d_pos);
    hipFree(d_vel);
    hipFree(d_acc);
    hipFree(d_mass);

    // Free host memory
    delete[] h_pos;
    delete[] h_vel;
    delete[] h_acc;
    delete[] h_mass;

    return 0;
}
	.text
	.file	"cuda_code_046100.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf # -- Begin function _Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf
	.type	_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf,@function
_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf: # @_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12nbody_kernelP4Vec3S0_S0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf, .Lfunc_end0-_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$384, %edi                      # imm = 0x180
	callq	_Znam
	movq	%rax, %rbx
	movl	$384, %edi                      # imm = 0x180
	callq	_Znam
	movq	%rax, %r14
	movl	$128, %edi
	callq	_Znam
	movq	%rax, %r15
	xorl	%r12d, %r12d
	movl	$384, %edx                      # imm = 0x180
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movq	%rbx, %rax
	addq	$8, %rax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r12d, %xmm0
	movss	%xmm0, -8(%rax)
	movss	%xmm0, -4(%rax)
	movss	%xmm0, (%rax)
	movl	$1065353216, (%r15,%r12,4)      # imm = 0x3F800000
	incq	%r12
	addq	$12, %rax
	cmpq	$32, %r12
	jne	.LBB1_1
# %bb.2:
	leaq	16(%rsp), %r13
	movl	$384, %esi                      # imm = 0x180
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$384, %esi                      # imm = 0x180
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$384, %esi                      # imm = 0x180
	callq	hipMalloc
	leaq	24(%rsp), %rbp
	movl	$128, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$384, %edx                      # imm = 0x180
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$384, %edx                      # imm = 0x180
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$128, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	31(%rdi), %rdx
	movl	$1280, %r8d                     # imm = 0x500
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	callq	_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf
.LBB1_4:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_9
# %bb.5:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_6
# %bb.7:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_8
.LBB1_9:
	movq	16(%rsp), %rsi
	movl	$384, %edx                      # imm = 0x180
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$384, %edx                      # imm = 0x180
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %r12d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$8, %ebp
	xorl	%r12d, %r12d
.LBB1_10:                               # =>This Inner Loop Header: Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r13
	movl	$.L.str.3, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$.L.str.4, %esi
	movl	$4, %edx
	movq	%r13, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	-8(%rbx,%rbp), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	-4(%rbx,%rbp), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%rbp), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.6, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$.L.str.7, %esi
	movl	$4, %edx
	movq	%r13, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	-8(%r14,%rbp), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	-4(%r14,%rbp), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%rbp), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r13), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r13, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r12
	addq	$12, %rbp
	cmpq	$32, %r12
	jne	.LBB1_10
# %bb.11:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_12
.LBB1_6:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_12:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12nbody_kernelP4Vec3S0_S0_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12nbody_kernelP4Vec3S0_S0_Pf,@object # @_Z12nbody_kernelP4Vec3S0_S0_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z12nbody_kernelP4Vec3S0_S0_Pf
	.p2align	3, 0x0
_Z12nbody_kernelP4Vec3S0_S0_Pf:
	.quad	_Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf
	.size	_Z12nbody_kernelP4Vec3S0_S0_Pf, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Final positions and velocities:"
	.size	.L.str.1, 32

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Particle "
	.size	.L.str.2, 10

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	": "
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Pos("
	.size	.L.str.4, 5

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	", "
	.size	.L.str.5, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"), "
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Vel("
	.size	.L.str.7, 5

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	")"
	.size	.L.str.8, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12nbody_kernelP4Vec3S0_S0_Pf"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__nbody_kernelP4Vec3S0_S0_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12nbody_kernelP4Vec3S0_S0_Pf
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12nbody_kernelP4Vec3S0_S0_Pf ; -- Begin function _Z12nbody_kernelP4Vec3S0_S0_Pf
	.globl	_Z12nbody_kernelP4Vec3S0_S0_Pf
	.p2align	8
	.type	_Z12nbody_kernelP4Vec3S0_S0_Pf,@function
_Z12nbody_kernelP4Vec3S0_S0_Pf:         ; @_Z12nbody_kernelP4Vec3S0_S0_Pf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_mov_b32 s5, 0
	s_mov_b32 s6, 0x3e76c4e1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_mov_b64 s[2:3], 0
	v_mad_u64_u32 v[5:6], null, s15, s4, v[0:1]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[5:6]
	v_mad_u64_u32 v[3:4], null, v5, 12, s[8:9]
	v_mad_u64_u32 v[1:2], null, v5, 12, s[10:11]
	s_sub_i32 s9, 0, s4
	v_add_co_u32 v7, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	s_mul_i32 s0, s4, 12
	global_load_b96 v[11:13], v[3:4], off
	global_load_b96 v[14:16], v[1:2], off
	global_load_b32 v17, v[7:8], off
	v_cvt_f32_u32_e32 v7, s4
	s_add_i32 s1, s0, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s10, s1, s0
	v_rcp_iflag_f32_e32 v7, v7
	v_mad_u32_u24 v10, v0, 12, s10
	s_add_i32 s7, s10, s0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, 0x4f7ffffe, v7
	v_mad_u32_u24 v7, v0, 12, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v8, v8
	v_add_nc_u32_e32 v9, 8, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_readfirstlane_b32 s8, v8
	v_mad_u32_u24 v8, v0, 12, s1
	v_lshl_add_u32 v0, v0, 2, s7
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v7, v11, v12 offset1:1
	ds_store_b32 v7, v13 offset:8
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v8, v14, v15 offset1:1
	ds_store_b32 v8, v16 offset:8
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v17
	s_mul_i32 s9, s9, s8
	s_waitcnt lgkmcnt(0)
	s_mul_hi_u32 s0, s8, s9
	s_barrier
	s_add_i32 s8, s8, s0
	buffer_gl0_inv
	ds_store_2addr_b32 v10, v6, v6 offset1:1
	ds_store_b32 v10, v6 offset:8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s9, exec_lo
	v_cmpx_ne_u32_e64 s5, v5
	s_cbranch_execz .LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	s_not_b32 s0, s3
	s_mul_i32 s1, s4, s3
	s_mul_i32 s0, s4, s0
	s_sub_i32 s1, s5, s1
	s_add_i32 s0, s5, s0
	s_cmp_ge_u32 s1, s4
	s_cselect_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s1, s0, s4
	s_cmp_ge_u32 s0, s4
	s_cselect_b32 s0, s1, s0
	s_mul_i32 s1, s0, 12
	s_lshl_b32 s0, s0, 2
	s_add_i32 s1, s1, 0
	s_add_i32 s0, s7, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v17, s0
	ds_load_2addr_b32 v[11:12], v7 offset1:1
	ds_load_2addr_b32 v[13:14], v0 offset1:1
	ds_load_b32 v6, v9
	ds_load_b32 v0, v0 offset:8
	ds_load_2addr_b32 v[15:16], v10 offset1:1
	ds_load_b32 v18, v10 offset:8
	ds_load_b32 v17, v17
	s_waitcnt lgkmcnt(5)
	v_dual_sub_f32 v12, v14, v12 :: v_dual_sub_f32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v12, v12
	s_waitcnt lgkmcnt(3)
	v_dual_sub_f32 v0, v0, v6 :: v_dual_fmac_f32 v13, v11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v0, v0
	v_add_f32_e32 v6, 0x2b8cbccc, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v13, |v6|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v13
	v_cndmask_b32_e64 v14, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v13, v13, v14
	v_add_f32_e32 v14, 1.0, v13
	v_add_f32_e32 v20, -1.0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, -1.0, v14
	v_sub_f32_e32 v13, v13, v22
	v_rcp_f32_e32 v19, v14
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v21, v20, v19
	v_cmp_eq_f32_e64 s1, 0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v14, v21
	v_fma_f32 v14, v21, v14, -v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v21, v13
	v_add_f32_e32 v13, v23, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v20, v13
	v_dual_sub_f32 v20, v20, v22 :: v_dual_sub_f32 v23, v13, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v20, v13 :: v_dual_sub_f32 v14, v23, v14
	v_add_f32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v22, v13
	v_mul_f32_e32 v13, v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v21, v13
	v_sub_f32_e32 v19, v14, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v20, v14, v14 :: v_dual_sub_f32 v13, v13, v19
	v_fma_f32 v19, v14, v14, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v13, v13
	v_fmac_f32_e32 v19, v14, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v20, v19
	v_fmaak_f32 v22, s6, v21, 0x3e91f4c4
	v_sub_f32_e32 v20, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v22, v21, v22, 0x3ecccdef :: v_dual_sub_f32 v19, v19, v20
	v_mul_f32_e32 v25, v14, v21
	v_mul_f32_e32 v23, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, v21, v14, -v25
	v_fma_f32 v20, v21, v22, -v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v21, v13
	v_ldexp_f32 v13, v13, 1
	v_fmac_f32_e32 v20, v19, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v19, v14
	v_ldexp_f32 v14, v14, 1
	v_add_f32_e32 v22, v23, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v23, v22, v23 :: v_dual_add_f32 v24, 0x3f2aaaaa, v22
	v_dual_sub_f32 v20, v20, v23 :: v_dual_add_f32 v23, 0xbf2aaaaa, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v20, 0x31739010, v20
	v_sub_f32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v20, v22
	v_add_f32_e32 v19, v24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v21, v25, v26 :: v_dual_sub_f32 v22, v24, v19
	v_mul_f32_e32 v23, v21, v19
	v_sub_f32_e32 v24, v21, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, v20, v22
	v_fma_f32 v22, v21, v19, -v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v26, v24
	v_fmac_f32_e32 v22, v21, v20
	v_frexp_exp_i32_f32_e32 v20, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, v24, v19
	v_subrev_co_ci_u32_e32 v19, vcc_lo, 0, v20, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, v23, v22
	v_cvt_f32_i32_e32 v19, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v14, v20
	v_dual_sub_f32 v23, v20, v23 :: v_dual_sub_f32 v14, v21, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v22, v22, v23
	v_mul_f32_e32 v24, 0x3f317218, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v20, v14
	v_add_f32_e32 v13, v13, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, 0x3f317218, v19, -v24
	v_add_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, 0xb102e308, v19
	v_dual_add_f32 v19, v21, v13 :: v_dual_add_f32 v14, v24, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v21, v19, v21
	v_dual_sub_f32 v13, v13, v21 :: v_dual_add_f32 v20, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v20, v14
	v_dual_sub_f32 v19, v19, v22 :: v_dual_sub_f32 v24, v14, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v23, v23, v24
	v_add_f32_e32 v21, v23, v13
	v_sub_f32_e32 v25, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v25
	v_dual_add_f32 v14, v19, v14 :: v_dual_sub_f32 v19, v21, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v19
	v_add_f32_e32 v14, v21, v14
	v_sub_f32_e32 v21, v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v19, v23, v21 :: v_dual_add_f32 v22, v20, v14
	v_dual_add_f32 v13, v13, v19 :: v_dual_sub_f32 v20, v22, v20
	v_cndmask_b32_e64 v19, 0x3fc00000, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v20
	v_add_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v22, v13
	v_sub_f32_e32 v20, v14, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v20
	v_mul_f32_e32 v21, v19, v14
	v_fma_f32 v14, v19, v14, -v21
	v_cmp_class_f32_e64 vcc_lo, v21, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v19, v13
	v_add_f32_e32 v13, v21, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v20, v13, v21, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v20
	v_cndmask_b32_e64 v22, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v20|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v23, v20, v22
	v_mul_f32_e32 v24, 0x3fb8aa3b, v23
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v25, 0x3fb8aa3b, v23, -v24
	v_rndne_f32_e32 v26, v24
	v_dual_fmac_f32 v25, 0x32a5705f, v23 :: v_dual_sub_f32 v24, v24, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v24, v24, v25
	v_sub_f32_e32 v13, v13, v21
	v_cvt_i32_f32_e32 v21, v26
	v_exp_f32_e32 v24, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_f32_e32 v13, v14, v13
	v_trunc_f32_e32 v14, v19
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v21, v24, v21
	v_dual_mul_f32 v24, 0.5, v19 :: v_dual_cndmask_b32 v13, 0, v13
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v20, 0, v21, vcc_lo
	v_trunc_f32_e32 v21, v24
	v_cmp_eq_f32_e32 vcc_lo, v14, v19
	v_cndmask_b32_e64 v19, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0x7f800000, v20, s0
	v_cmp_neq_f32_e64 s0, v21, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_and_b32 vcc_lo, vcc_lo, s0
	v_cmp_class_f32_e64 s0, v6, 0x204
	v_dual_cndmask_b32 v20, 1.0, v6 :: v_dual_add_f32 v13, v22, v13
	v_cndmask_b32_e32 v21, 0, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v14
	v_fma_f32 v13, v14, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v13, v13, v14, vcc_lo
	v_bfi_b32 v14, 0x7fffffff, v19, v21
	s_or_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_bfi_b32 v13, 0x7fffffff, v13, v20
	s_waitcnt lgkmcnt(0)
	v_dual_cndmask_b32 v13, v13, v14 :: v_dual_mul_f32 v14, 0x2e92c4f8, v17
	v_cmp_o_f32_e32 vcc_lo, v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0x7fc00000, v13, vcc_lo
	v_div_scale_f32 v13, null, v6, v6, v14
	v_div_scale_f32 v20, vcc_lo, v14, v6, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v13, v17, 1.0
	v_fmac_f32_e32 v17, v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v20, v17
	v_fma_f32 v21, -v13, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, v21, v17
	v_fma_f32 v13, -v13, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v13, v13, v17, v19
	v_div_fixup_f32 v6, v13, v6, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v18, v0, v6
	v_fma_f32 v11, v11, v6, v15
	v_fmac_f32_e32 v16, v12, v6
	ds_store_2addr_b32 v10, v11, v16 offset1:1
	ds_store_b32 v10, v18 offset:8
.LBB0_3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s5, s5, 1
	s_add_u32 s2, s2, s8
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s5, 32
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	ds_load_2addr_b32 v[5:6], v10 offset1:1
	ds_load_2addr_b32 v[11:12], v8 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmamk_f32 v0, v5, 0x3c23d70a, v11
	ds_load_b32 v10, v10 offset:8
	ds_load_b32 v11, v8 offset:8
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, 0x3c23d70a, v10
	v_fmac_f32_e32 v12, 0x3c23d70a, v6
	ds_store_b32 v8, v11 offset:8
	ds_store_2addr_b32 v8, v0, v12 offset1:1
	ds_load_2addr_b32 v[5:6], v7 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmamk_f32 v0, v0, 0x3c23d70a, v5
	ds_load_b32 v5, v9
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v5, 0x3c23d70a, v11 :: v_dual_fmac_f32 v6, 0x3c23d70a, v12
	ds_store_2addr_b32 v7, v0, v6 offset1:1
	ds_store_b32 v9, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[9:10], v8 offset1:1
	ds_load_b32 v11, v8 offset:8
	ds_load_b32 v8, v7 offset:8
	ds_load_2addr_b32 v[6:7], v7 offset1:1
	s_waitcnt lgkmcnt(0)
	global_store_b96 v[3:4], v[6:8], off
	global_store_b96 v[1:2], v[9:11], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12nbody_kernelP4Vec3S0_S0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12nbody_kernelP4Vec3S0_S0_Pf, .Lfunc_end0-_Z12nbody_kernelP4Vec3S0_S0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1956
; NumSgprs: 18
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12nbody_kernelP4Vec3S0_S0_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12nbody_kernelP4Vec3S0_S0_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
