#include <iostream>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

#define NUM_LAYERS 4
#define NUM_NEURONS 64
#define BATCH_SIZE 256
#define INPUT_SIZE NUM_NEURONS
#define OUTPUT_SIZE NUM_NEURONS

__global__ void forward_pass_kernel(half* input, half* weights, half* biases, half* output) {
    extern __shared__ half shared_mem[];

    // Index of the neuron in the batch
    int neuron_idx = blockIdx.x * blockDim.x + threadIdx.x;

    // Load input data into shared memory
    if (threadIdx.x < INPUT_SIZE) {
        shared_mem[threadIdx.x] = input[blockIdx.y * INPUT_SIZE + threadIdx.x];
    }
    __syncthreads();

    half sum = __float2half(0.0f);
    for (int i = 0; i < INPUT_SIZE; i++) {
        sum += shared_mem[i] * weights[(blockIdx.y * NUM_NEURONS + threadIdx.x) * INPUT_SIZE + i];
    }
    sum += biases[blockIdx.y * NUM_NEURONS + threadIdx.x];

    // Apply ReLU activation
    if (__half2float(sum) < 0.0f) {
        sum = __float2half(0.0f);
    }

    // Store the result in the output array
    output[blockIdx.y * NUM_NEURONS + threadIdx.x] = sum;
}

int main() {
    // Allocate and initialize host memory
    half* h_input = new half[BATCH_SIZE * INPUT_SIZE];
    half* h_weights = new half[NUM_LAYERS * NUM_NEURONS * INPUT_SIZE];
    half* h_biases = new half[NUM_LAYERS * NUM_NEURONS];
    half* h_output = new half[BATCH_SIZE * OUTPUT_SIZE];

    // Initialize input, weights, and biases with some values
    for (int i = 0; i < BATCH_SIZE * INPUT_SIZE; i++) {
        h_input[i] = __float2half(1.0f);
    }
    for (int i = 0; i < NUM_LAYERS * NUM_NEURONS * INPUT_SIZE; i++) {
        h_weights[i] = __float2half(0.5f);
    }
    for (int i = 0; i < NUM_LAYERS * NUM_NEURONS; i++) {
        h_biases[i] = __float2half(0.1f);
    }

    // Allocate device memory
    half* d_input;
    half* d_weights;
    half* d_biases;
    half* d_output;
    cudaMalloc(&d_input, BATCH_SIZE * INPUT_SIZE * sizeof(half));
    cudaMalloc(&d_weights, NUM_LAYERS * NUM_NEURONS * INPUT_SIZE * sizeof(half));
    cudaMalloc(&d_biases, NUM_LAYERS * NUM_NEURONS * sizeof(half));
    cudaMalloc(&d_output, BATCH_SIZE * OUTPUT_SIZE * sizeof(half));

    // Copy data from host to device
    cudaMemcpy(d_input, h_input, BATCH_SIZE * INPUT_SIZE * sizeof(half), cudaMemcpyHostToDevice);
    cudaMemcpy(d_weights, h_weights, NUM_LAYERS * NUM_NEURONS * INPUT_SIZE * sizeof(half), cudaMemcpyHostToDevice);
    cudaMemcpy(d_biases, h_biases, NUM_LAYERS * NUM_NEURONS * sizeof(half), cudaMemcpyHostToDevice);

    // Define grid and block dimensions
    dim3 threadsPerBlock(NUM_NEURONS);
    dim3 blocksPerGrid(BATCH_SIZE, NUM_LAYERS);

    // Launch the kernel
    forward_pass_kernel<<<blocksPerGrid, threadsPerBlock, INPUT_SIZE * sizeof(half)>>>(d_input, d_weights, d_biases, d_output);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    cudaMemcpy(h_output, d_output, BATCH_SIZE * OUTPUT_SIZE * sizeof(half), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_weights);
    cudaFree(d_biases);
    cudaFree(d_output);

    // Free host memory
    delete[] h_input;
    delete[] h_weights;
    delete[] h_biases;
    delete[] h_output;

    return 0;
}
	.file	"tmpxft_0000b5a9_00000000-6_cuda_code_026977.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL12__float2halff, @function
_ZL12__float2halff:
.LFB3763:
	.cfi_startproc
	movd	%xmm0, %ecx
	movl	%ecx, %edx
	movl	%ecx, %eax
	shrl	$16, %eax
	andl	$2147483647, %edx
	andl	$32768, %eax
	cmpl	$2139095039, %edx
	jbe	.L3
	orb	$124, %ah
	cmpl	$2139095040, %edx
	movl	$32767, %edx
	cmovne	%edx, %eax
	ret
.L3:
	cmpl	$1199566847, %edx
	jbe	.L5
	orw	$31743, %ax
	jmp	.L6
.L5:
	cmpl	$947912703, %edx
	jbe	.L7
	movl	%edx, %edi
	subl	$939524096, %edx
	shrl	$13, %edx
	sall	$19, %edi
	orl	%edx, %eax
	jmp	.L8
.L7:
	cmpl	$855638016, %edx
	jbe	.L4
	andl	$8388607, %ecx
	shrl	$23, %edx
	movl	%ecx, %esi
	leal	-94(%rdx), %ecx
	orl	$8388608, %esi
	movl	%esi, %edi
	sall	%cl, %edi
	movl	$126, %ecx
	subl	%edx, %ecx
	shrl	%cl, %esi
	orl	%esi, %eax
.L8:
	cmpl	$-2147483648, %edi
	ja	.L6
	jne	.L4
	testb	$1, %al
	je	.L4
.L6:
	incl	%eax
.L4:
	ret
	.cfi_endproc
.LFE3763:
	.size	_ZL12__float2halff, .-_ZL12__float2halff
	.globl	_Z54__device_stub__Z19forward_pass_kernelP6__halfS0_S0_S0_P6__halfS0_S0_S0_
	.type	_Z54__device_stub__Z19forward_pass_kernelP6__halfS0_S0_S0_P6__halfS0_S0_S0_, @function
_Z54__device_stub__Z19forward_pass_kernelP6__halfS0_S0_S0_P6__halfS0_S0_S0_:
.LFB4034:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19forward_pass_kernelP6__halfS0_S0_S0_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L15:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4034:
	.size	_Z54__device_stub__Z19forward_pass_kernelP6__halfS0_S0_S0_P6__halfS0_S0_S0_, .-_Z54__device_stub__Z19forward_pass_kernelP6__halfS0_S0_S0_P6__halfS0_S0_S0_
	.globl	_Z19forward_pass_kernelP6__halfS0_S0_S0_
	.type	_Z19forward_pass_kernelP6__halfS0_S0_S0_, @function
_Z19forward_pass_kernelP6__halfS0_S0_S0_:
.LFB4035:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z19forward_pass_kernelP6__halfS0_S0_S0_P6__halfS0_S0_S0_
	.cfi_endproc
.LFE4035:
	.size	_Z19forward_pass_kernelP6__halfS0_S0_S0_, .-_Z19forward_pass_kernelP6__halfS0_S0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4009:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$32768, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$32768, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$512, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$32768, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movq	%r12, %r8
	leaq	32768(%r12), %r9
	movq	%rax, %r13
.L21:
	movss	.LC0(%rip), %xmm0
	addq	$2, %r8
	call	_ZL12__float2halff
	movw	%ax, -2(%r8)
	cmpq	%r9, %r8
	jne	.L21
	movq	%rbp, %r8
	leaq	32768(%rbp), %r9
.L22:
	movss	.LC1(%rip), %xmm0
	addq	$2, %r8
	call	_ZL12__float2halff
	movw	%ax, -2(%r8)
	cmpq	%r9, %r8
	jne	.L22
	movq	%rbx, %r8
	leaq	512(%rbx), %r9
.L23:
	movss	.LC2(%rip), %xmm0
	addq	$2, %r8
	call	_ZL12__float2halff
	movw	%ax, -2(%r8)
	cmpq	%r9, %r8
	jne	.L23
	movq	%rsp, %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$512, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$32768, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$32768, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$512, %edx
	call	cudaMemcpy@PLT
	movl	$67108865, %edx
	movl	$67108865, %edi
	xorl	%r9d, %r9d
	salq	$6, %rdx
	salq	$8, %rdi
	movl	$128, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z54__device_stub__Z19forward_pass_kernelP6__halfS0_S0_S0_P6__halfS0_S0_S0_
.L24:
	call	cudaGetLastError@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	je	.L25
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L20
.L25:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$32768, %edx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L20:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4009:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z19forward_pass_kernelP6__halfS0_S0_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19forward_pass_kernelP6__halfS0_S0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	1056964608
	.align 4
.LC2:
	.long	1036831949
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>

#define NUM_LAYERS 4
#define NUM_NEURONS 64
#define BATCH_SIZE 256
#define INPUT_SIZE NUM_NEURONS
#define OUTPUT_SIZE NUM_NEURONS

__global__ void forward_pass_kernel(half* input, half* weights, half* biases, half* output) {
    extern __shared__ half shared_mem[];

    // Index of the neuron in the batch
    int neuron_idx = blockIdx.x * blockDim.x + threadIdx.x;

    // Load input data into shared memory
    if (threadIdx.x < INPUT_SIZE) {
        shared_mem[threadIdx.x] = input[blockIdx.y * INPUT_SIZE + threadIdx.x];
    }
    __syncthreads();

    half sum = __float2half(0.0f);
    for (int i = 0; i < INPUT_SIZE; i++) {
        sum += shared_mem[i] * weights[(blockIdx.y * NUM_NEURONS + threadIdx.x) * INPUT_SIZE + i];
    }
    sum += biases[blockIdx.y * NUM_NEURONS + threadIdx.x];

    // Apply ReLU activation
    if (__half2float(sum) < 0.0f) {
        sum = __float2half(0.0f);
    }

    // Store the result in the output array
    output[blockIdx.y * NUM_NEURONS + threadIdx.x] = sum;
}

int main() {
    // Allocate and initialize host memory
    half* h_input = new half[BATCH_SIZE * INPUT_SIZE];
    half* h_weights = new half[NUM_LAYERS * NUM_NEURONS * INPUT_SIZE];
    half* h_biases = new half[NUM_LAYERS * NUM_NEURONS];
    half* h_output = new half[BATCH_SIZE * OUTPUT_SIZE];

    // Initialize input, weights, and biases with some values
    for (int i = 0; i < BATCH_SIZE * INPUT_SIZE; i++) {
        h_input[i] = __float2half(1.0f);
    }
    for (int i = 0; i < NUM_LAYERS * NUM_NEURONS * INPUT_SIZE; i++) {
        h_weights[i] = __float2half(0.5f);
    }
    for (int i = 0; i < NUM_LAYERS * NUM_NEURONS; i++) {
        h_biases[i] = __float2half(0.1f);
    }

    // Allocate device memory
    half* d_input;
    half* d_weights;
    half* d_biases;
    half* d_output;
    hipMalloc(&d_input, BATCH_SIZE * INPUT_SIZE * sizeof(half));
    hipMalloc(&d_weights, NUM_LAYERS * NUM_NEURONS * INPUT_SIZE * sizeof(half));
    hipMalloc(&d_biases, NUM_LAYERS * NUM_NEURONS * sizeof(half));
    hipMalloc(&d_output, BATCH_SIZE * OUTPUT_SIZE * sizeof(half));

    // Copy data from host to device
    hipMemcpy(d_input, h_input, BATCH_SIZE * INPUT_SIZE * sizeof(half), hipMemcpyHostToDevice);
    hipMemcpy(d_weights, h_weights, NUM_LAYERS * NUM_NEURONS * INPUT_SIZE * sizeof(half), hipMemcpyHostToDevice);
    hipMemcpy(d_biases, h_biases, NUM_LAYERS * NUM_NEURONS * sizeof(half), hipMemcpyHostToDevice);

    // Define grid and block dimensions
    dim3 threadsPerBlock(NUM_NEURONS);
    dim3 blocksPerGrid(BATCH_SIZE, NUM_LAYERS);

    // Launch the kernel
    forward_pass_kernel<<<blocksPerGrid, threadsPerBlock, INPUT_SIZE * sizeof(half)>>>(d_input, d_weights, d_biases, d_output);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    hipMemcpy(h_output, d_output, BATCH_SIZE * OUTPUT_SIZE * sizeof(half), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_input);
    hipFree(d_weights);
    hipFree(d_biases);
    hipFree(d_output);

    // Free host memory
    delete[] h_input;
    delete[] h_weights;
    delete[] h_biases;
    delete[] h_output;

    return 0;
}
	.text
	.file	"cuda_code_026977.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_ # -- Begin function _Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_
	.type	_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_,@function
_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_: # @_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19forward_pass_kernelP6__halfS0_S0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_, .Lfunc_end0-_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$32768, %edi                    # imm = 0x8000
	callq	_Znam
	movq	%rax, %rbx
	movl	$32768, %edi                    # imm = 0x8000
	callq	_Znam
	movq	%rax, %r14
	movl	$512, %edi                      # imm = 0x200
	callq	_Znam
	movq	%rax, %r15
	movl	$32768, %edi                    # imm = 0x8000
	callq	_Znam
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movw	$15360, (%rbx,%rax,2)           # imm = 0x3C00
	incq	%rax
	cmpq	$16384, %rax                    # imm = 0x4000
	jne	.LBB1_1
# %bb.2:                                # %.preheader38.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader38
                                        # =>This Inner Loop Header: Depth=1
	movw	$14336, (%r14,%rax,2)           # imm = 0x3800
	incq	%rax
	cmpq	$16384, %rax                    # imm = 0x4000
	jne	.LBB1_3
# %bb.4:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movw	$11878, (%r15,%rax,2)           # imm = 0x2E66
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB1_5
# %bb.6:
	leaq	24(%rsp), %r12
	movl	$32768, %esi                    # imm = 0x8000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rbp
	movl	$32768, %esi                    # imm = 0x8000
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$512, %esi                      # imm = 0x200
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$32768, %esi                    # imm = 0x8000
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$32768, %edx                    # imm = 0x8000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$32768, %edx                    # imm = 0x8000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$512, %edx                      # imm = 0x200
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$17179869440, %rdi              # imm = 0x400000100
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$128, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	callq	_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_
.LBB1_8:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_13
# %bb.9:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_10
# %bb.11:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_12
.LBB1_13:
	movq	(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movq	32(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_14
.LBB1_10:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_14:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19forward_pass_kernelP6__halfS0_S0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19forward_pass_kernelP6__halfS0_S0_S0_,@object # @_Z19forward_pass_kernelP6__halfS0_S0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z19forward_pass_kernelP6__halfS0_S0_S0_
	.p2align	3, 0x0
_Z19forward_pass_kernelP6__halfS0_S0_S0_:
	.quad	_Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_
	.size	_Z19forward_pass_kernelP6__halfS0_S0_S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19forward_pass_kernelP6__halfS0_S0_S0_"
	.size	.L__unnamed_1, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__forward_pass_kernelP6__halfS0_S0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19forward_pass_kernelP6__halfS0_S0_S0_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19forward_pass_kernelP6__halfS0_S0_S0_ ; -- Begin function _Z19forward_pass_kernelP6__halfS0_S0_S0_
	.globl	_Z19forward_pass_kernelP6__halfS0_S0_S0_
	.p2align	8
	.type	_Z19forward_pass_kernelP6__halfS0_S0_S0_,@function
_Z19forward_pass_kernelP6__halfS0_S0_S0_: ; @_Z19forward_pass_kernelP6__halfS0_S0_S0_
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_u32_e32 63, v0
	s_xor_b32 s2, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_saveexec_b32 s8, s2
	s_load_b256 s[0:7], s[0:1], 0x0
	v_mov_b32_e32 v5, s15
	s_xor_b32 exec_lo, exec_lo, s8
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshl_or_b32 v1, s15, 6, v0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 1, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_u16 v1, v[1:2], off
	v_lshl_add_u32 v2, v0, 1, 0
	s_waitcnt vmcnt(0)
	ds_store_b16 v2, v1
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 6, v0
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s0, 0
	s_barrier
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v5, 12, v1
	buffer_gl0_inv
	v_lshlrev_b64 v[3:4], 1, v[1:2]
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_u16 v1, v[3:4], off
	s_add_i32 s1, s0, 0
	v_add_co_u32 v3, vcc_lo, v3, 2
	v_mov_b32_e32 v6, s1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_i32 s0, s0, 2
	ds_load_u16 v6, v6
	s_cmpk_eq_i32 s0, 0x80
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f16_e32 v2, v6, v1
	s_cbranch_scc0 .LBB0_3
; %bb.4:
	v_lshl_add_u32 v0, v5, 6, v0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 1, v[0:1]
	v_add_co_u32 v3, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	global_load_u16 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f16_e32 v2, v2, v3
	v_cmp_ngt_f16_e32 vcc_lo, 0, v2
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b16 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19forward_pass_kernelP6__halfS0_S0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19forward_pass_kernelP6__halfS0_S0_S0_, .Lfunc_end0-_Z19forward_pass_kernelP6__halfS0_S0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19forward_pass_kernelP6__halfS0_S0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19forward_pass_kernelP6__halfS0_S0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
