#include <iostream>
#include <cuda_runtime.h>

// Define the maximum number of nodes
#define MAX_NODES 64

// Kernel to perform a simple topological sort using a naive approach
// This kernel assumes the graph is a Directed Acyclic Graph (DAG)
// and uses a simple algorithm that repeatedly removes nodes with no incoming edges.
__global__ void topologicalSortKernel(int *indegree, int *adjMatrix, int *result, int *resultIndex) {
    extern __shared__ int sharedIndegree[];
    int idx = threadIdx.x;

    // Load indegree into shared memory
    sharedIndegree[idx] = indegree[idx];
    __syncthreads();

    // Find a node with no incoming edges
    int node = -1;
    for (int i = idx; i < MAX_NODES; i += blockDim.x) {
        if (sharedIndegree[i] == 0) {
            node = i;
            break;
        }
    }

    // Ensure only one thread sets the node
    if (node >= 0) {
        int oldNode = atomicCAS(&resultIndex[0], 0, 1);
        if (oldNode == 0) {
            result[resultIndex[0] - 1] = node;
            sharedIndegree[node] = -1; // Mark as visited
        }
    }
    __syncthreads();

    // Update indegree of adjacent nodes
    if (node >= 0) {
        for (int i = idx; i < MAX_NODES; i += blockDim.x) {
            if (adjMatrix[node * MAX_NODES + i] == 1) {
                atomicSub(&sharedIndegree[i], 1);
            }
        }
    }
    __syncthreads();

    // Write back updated indegree from shared memory to global memory
    indegree[idx] = sharedIndegree[idx];
}

int main() {
    // Initialize graph data on host
    int h_indegree[MAX_NODES] = {0};
    int h_adjMatrix[MAX_NODES * MAX_NODES] = {0};
    int h_result[MAX_NODES] = {0};
    int h_resultIndex[1] = {0};

    // Example graph: simple DAG
    // Node 0 -> Node 1, Node 2
    // Node 1 -> Node 3
    // Node 2 -> Node 3
    h_adjMatrix[0 * MAX_NODES + 1] = 1;
    h_adjMatrix[0 * MAX_NODES + 2] = 1;
    h_adjMatrix[1 * MAX_NODES + 3] = 1;
    h_adjMatrix[2 * MAX_NODES + 3] = 1;

    // Calculate initial indegree
    for (int i = 0; i < MAX_NODES; i++) {
        for (int j = 0; j < MAX_NODES; j++) {
            h_indegree[j] += h_adjMatrix[i * MAX_NODES + j];
        }
    }

    // Allocate device memory
    int *d_indegree, *d_adjMatrix, *d_result, *d_resultIndex;
    cudaMalloc(&d_indegree, MAX_NODES * sizeof(int));
    cudaMalloc(&d_adjMatrix, MAX_NODES * MAX_NODES * sizeof(int));
    cudaMalloc(&d_result, MAX_NODES * sizeof(int));
    cudaMalloc(&d_resultIndex, sizeof(int));

    // Copy data from host to device
    cudaMemcpy(d_indegree, h_indegree, MAX_NODES * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_adjMatrix, h_adjMatrix, MAX_NODES * MAX_NODES * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_result, h_result, MAX_NODES * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_resultIndex, h_resultIndex, sizeof(int), cudaMemcpyHostToDevice);

    // Launch kernel
    int blockSize = 64; // Block size of 64 for Turing architecture
    int sharedMemSize = blockSize * sizeof(int); // Shared memory for indegree
    topologicalSortKernel<<<1, blockSize, sharedMemSize>>>(d_indegree, d_adjMatrix, d_result, d_resultIndex);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    cudaMemcpy(h_result, d_result, MAX_NODES * sizeof(int), cudaMemcpyDeviceToHost);

    // Print the topological sort result
    std::cout << "Topological Sort Result: ";
    for (int i = 0; i < MAX_NODES; i++) {
        if (h_result[i] != 0) {
            std::cout << h_result[i] << " ";
        }
    }
    std::cout << std::endl;

    // Free device memory
    cudaFree(d_indegree);
    cudaFree(d_adjMatrix);
    cudaFree(d_result);
    cudaFree(d_resultIndex);

    return 0;
}
	.file	"tmpxft_001cd6fa_00000000-6_cuda_code_017441.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z21topologicalSortKernelPiS_S_S_PiS_S_S_
	.type	_Z47__device_stub__Z21topologicalSortKernelPiS_S_S_PiS_S_S_, @function
_Z47__device_stub__Z21topologicalSortKernelPiS_S_S_PiS_S_S_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21topologicalSortKernelPiS_S_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z47__device_stub__Z21topologicalSortKernelPiS_S_S_PiS_S_S_, .-_Z47__device_stub__Z21topologicalSortKernelPiS_S_S_PiS_S_S_
	.globl	_Z21topologicalSortKernelPiS_S_S_
	.type	_Z21topologicalSortKernelPiS_S_S_, @function
_Z21topologicalSortKernelPiS_S_S_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21topologicalSortKernelPiS_S_S_PiS_S_S_
	.cfi_endproc
.LFE3661:
	.size	_Z21topologicalSortKernelPiS_S_S_, .-_Z21topologicalSortKernelPiS_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
.LC1:
	.string	"Topological Sort Result: "
.LC2:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	-16384(%rsp), %r11
	.cfi_def_cfa 11, 16424
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$600, %rsp
	.cfi_def_cfa_offset 17024
	movl	$64, %ecx
	xorl	%edx, %edx
	movq	%fs:40, %rax
	movq	%rax, 16968(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rdi
	movl	%edx, 68(%rsp)
	leaq	584(%rsp), %rdx
	leaq	72(%rsp), %rbx
	leaq	328(%rsp), %rbp
	movq	%rdx, %r12
	rep stosl
	leaq	328(%rsp), %rdi
	movl	$64, %ecx
	rep stosl
	leaq	584(%rsp), %rdi
	movl	$4096, %ecx
	rep stosl
	movabsq	$4294967297, %rax
	movl	$1, 852(%rsp)
	movq	%rax, 588(%rsp)
	movl	$1, 1108(%rsp)
.L9:
	xorl	%eax, %eax
.L10:
	movl	(%rdx,%rax), %esi
	addl	%esi, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$256, %rax
	jne	.L10
	addl	$64, %ecx
	addq	$256, %rdx
	cmpl	$4096, %ecx
	jne	.L9
	leaq	8(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	leaq	68(%rsp), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rdi
	salq	$6, %rdx
	movl	$256, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z47__device_stub__Z21topologicalSortKernelPiS_S_S_PiS_S_S_
.L12:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L13
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L13:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%ebx, %ebx
	movl	$256, %edx
	leaq	_ZSt4cout(%rip), %r12
	leaq	.LC2(%rip), %r13
	call	cudaMemcpy@PLT
	leaq	.LC1(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L16:
	movl	0(%rbp,%rbx,4), %esi
	testl	%esi, %esi
	je	.L15
	movq	%r12, %rdi
	call	_ZNSolsEi@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L15:
	incq	%rbx
	cmpq	$64, %rbx
	jne	.L16
	movq	%r12, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L8:
	movq	16968(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$16984, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z21topologicalSortKernelPiS_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21topologicalSortKernelPiS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

// Define the maximum number of nodes
#define MAX_NODES 64

// Kernel to perform a simple topological sort using a naive approach
// This kernel assumes the graph is a Directed Acyclic Graph (DAG)
// and uses a simple algorithm that repeatedly removes nodes with no incoming edges.
__global__ void topologicalSortKernel(int *indegree, int *adjMatrix, int *result, int *resultIndex) {
    extern __shared__ int sharedIndegree[];
    int idx = threadIdx.x;

    // Load indegree into shared memory
    sharedIndegree[idx] = indegree[idx];
    __syncthreads();

    // Find a node with no incoming edges
    int node = -1;
    for (int i = idx; i < MAX_NODES; i += blockDim.x) {
        if (sharedIndegree[i] == 0) {
            node = i;
            break;
        }
    }

    // Ensure only one thread sets the node
    if (node >= 0) {
        int oldNode = atomicCAS(&resultIndex[0], 0, 1);
        if (oldNode == 0) {
            result[resultIndex[0] - 1] = node;
            sharedIndegree[node] = -1; // Mark as visited
        }
    }
    __syncthreads();

    // Update indegree of adjacent nodes
    if (node >= 0) {
        for (int i = idx; i < MAX_NODES; i += blockDim.x) {
            if (adjMatrix[node * MAX_NODES + i] == 1) {
                atomicSub(&sharedIndegree[i], 1);
            }
        }
    }
    __syncthreads();

    // Write back updated indegree from shared memory to global memory
    indegree[idx] = sharedIndegree[idx];
}

int main() {
    // Initialize graph data on host
    int h_indegree[MAX_NODES] = {0};
    int h_adjMatrix[MAX_NODES * MAX_NODES] = {0};
    int h_result[MAX_NODES] = {0};
    int h_resultIndex[1] = {0};

    // Example graph: simple DAG
    // Node 0 -> Node 1, Node 2
    // Node 1 -> Node 3
    // Node 2 -> Node 3
    h_adjMatrix[0 * MAX_NODES + 1] = 1;
    h_adjMatrix[0 * MAX_NODES + 2] = 1;
    h_adjMatrix[1 * MAX_NODES + 3] = 1;
    h_adjMatrix[2 * MAX_NODES + 3] = 1;

    // Calculate initial indegree
    for (int i = 0; i < MAX_NODES; i++) {
        for (int j = 0; j < MAX_NODES; j++) {
            h_indegree[j] += h_adjMatrix[i * MAX_NODES + j];
        }
    }

    // Allocate device memory
    int *d_indegree, *d_adjMatrix, *d_result, *d_resultIndex;
    hipMalloc(&d_indegree, MAX_NODES * sizeof(int));
    hipMalloc(&d_adjMatrix, MAX_NODES * MAX_NODES * sizeof(int));
    hipMalloc(&d_result, MAX_NODES * sizeof(int));
    hipMalloc(&d_resultIndex, sizeof(int));

    // Copy data from host to device
    hipMemcpy(d_indegree, h_indegree, MAX_NODES * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_adjMatrix, h_adjMatrix, MAX_NODES * MAX_NODES * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_result, h_result, MAX_NODES * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_resultIndex, h_resultIndex, sizeof(int), hipMemcpyHostToDevice);

    // Launch kernel
    int blockSize = 64; // Block size of 64 for Turing architecture
    int sharedMemSize = blockSize * sizeof(int); // Shared memory for indegree
    topologicalSortKernel<<<1, blockSize, sharedMemSize>>>(d_indegree, d_adjMatrix, d_result, d_resultIndex);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    hipMemcpy(h_result, d_result, MAX_NODES * sizeof(int), hipMemcpyDeviceToHost);

    // Print the topological sort result
    std::cout << "Topological Sort Result: ";
    for (int i = 0; i < MAX_NODES; i++) {
        if (h_result[i] != 0) {
            std::cout << h_result[i] << " ";
        }
    }
    std::cout << std::endl;

    // Free device memory
    hipFree(d_indegree);
    hipFree(d_adjMatrix);
    hipFree(d_result);
    hipFree(d_resultIndex);

    return 0;
}
	.text
	.file	"cuda_code_017441.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z36__device_stub__topologicalSortKernelPiS_S_S_ # -- Begin function _Z36__device_stub__topologicalSortKernelPiS_S_S_
	.type	_Z36__device_stub__topologicalSortKernelPiS_S_S_,@function
_Z36__device_stub__topologicalSortKernelPiS_S_S_: # @_Z36__device_stub__topologicalSortKernelPiS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21topologicalSortKernelPiS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__topologicalSortKernelPiS_S_S_, .Lfunc_end0-_Z36__device_stub__topologicalSortKernelPiS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16944, %rsp                    # imm = 0x4230
	.cfi_def_cfa_offset 16992
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	304(%rsp), %rdi
	xorl	%r15d, %r15d
	movl	$256, %edx                      # imm = 0x100
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	560(%rsp), %r14
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	48(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$0, 20(%rsp)
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	movq	%rbx, 4(%r14)
	movl	$1, %eax
	movl	%eax, 268(%r14)
	movl	%eax, 524(%r14)
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%eax, %eax
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r14,%rax,4), %ecx
	addl	%ecx, 304(%rsp,%rax,4)
	incq	%rax
	cmpq	$64, %rax
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r15
	addq	$256, %r14                      # imm = 0x100
	cmpq	$64, %r15
	jne	.LBB1_1
# %bb.4:
	leaq	40(%rsp), %r13
	movl	$256, %esi                      # imm = 0x100
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r12
	movl	$16384, %esi                    # imm = 0x4000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r15
	movl	$256, %esi                      # imm = 0x100
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %r14
	movl	$4, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	leaq	304(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	560(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	leaq	48(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	leaq	20(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	63(%rbx), %rdx
	movl	$256, %r8d                      # imm = 0x100
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rcx
	callq	_Z36__device_stub__topologicalSortKernelPiS_S_S_
.LBB1_6:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_11
# %bb.7:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_8
# %bb.9:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_10
.LBB1_11:
	movq	8(%rsp), %rsi
	leaq	48(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$25, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%ebx, %ebx
.LBB1_12:                               # =>This Inner Loop Header: Depth=1
	movl	48(%rsp,%rbx,4), %esi
	testl	%esi, %esi
	je	.LBB1_14
# %bb.13:                               #   in Loop: Header=BB1_12 Depth=1
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.2, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_14:                               #   in Loop: Header=BB1_12 Depth=1
	incq	%rbx
	cmpq	$64, %rbx
	jne	.LBB1_12
# %bb.15:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB1_16
.LBB1_8:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_10:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_16:
	addq	$16944, %rsp                    # imm = 0x4230
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21topologicalSortKernelPiS_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21topologicalSortKernelPiS_S_S_,@object # @_Z21topologicalSortKernelPiS_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z21topologicalSortKernelPiS_S_S_
	.p2align	3, 0x0
_Z21topologicalSortKernelPiS_S_S_:
	.quad	_Z36__device_stub__topologicalSortKernelPiS_S_S_
	.size	_Z21topologicalSortKernelPiS_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Topological Sort Result: "
	.size	.L.str.1, 26

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" "
	.size	.L.str.2, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21topologicalSortKernelPiS_S_S_"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__topologicalSortKernelPiS_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21topologicalSortKernelPiS_S_S_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21topologicalSortKernelPiS_S_S_ ; -- Begin function _Z21topologicalSortKernelPiS_S_S_
	.globl	_Z21topologicalSortKernelPiS_S_S_
	.p2align	8
	.type	_Z21topologicalSortKernelPiS_S_S_,@function
_Z21topologicalSortKernelPiS_S_S_:      ; @_Z21topologicalSortKernelPiS_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_dual_mov_b32 v6, -1 :: v_dual_lshlrev_b32 v1, 2, v0
	v_cmp_gt_u32_e32 vcc_lo, 64, v0
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, 0, v1
	s_waitcnt lgkmcnt(0)
	global_load_b32 v3, v1, s[4:5]
	v_add_co_u32 v1, s2, s4, v1
	v_add_co_ci_u32_e64 v2, null, s5, 0, s2
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s12, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.lr.ph
	v_mov_b32_e32 v3, v0
	s_add_u32 s4, s0, 32
	s_addc_u32 s5, s1, 0
                                        ; implicit-def: $sgpr13
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v4, v3, 2, 0
	s_or_b32 s13, s13, exec_lo
	ds_load_b32 v4, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e64 s2, 0, v4
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_load_b32 s2, s[4:5], 0xc
	s_and_not1_b32 s13, s13, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, -1 :: v_dual_add_nc_u32 v4, s2, v3
	v_cmp_lt_u32_e64 s2, 63, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s13, s13, s2
.LBB0_4:                                ; %Flow54
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v3, v4
	s_and_b32 s2, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s2, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
; %bb.5:                                ; %Flow55
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_6:                                ; %Flow56
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_cmp_lt_i32_e64 s2, -1, v6
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_9
; %bb.7:
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 1
	global_atomic_cmpswap_b32 v3, v4, v[3:4], s[10:11] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s3, 0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_9
; %bb.8:
	global_load_b32 v3, v4, s[10:11]
	v_lshl_add_u32 v7, v6, 2, 0
	v_mov_b32_e32 v8, -1
	ds_store_b32 v7, v8
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, s3, s8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s3, s9, v4, s3
	global_store_b32 v[3:4], v6, off offset:-4
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s4
	s_and_b32 s3, s2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_14
; %bb.10:                               ; %.lr.ph35
	s_load_b32 s0, s[0:1], 0x2c
	v_lshl_add_u32 v3, v6, 6, v0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, -1
	v_lshl_add_u32 v6, v0, 2, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s0, 0xffff
	s_lshl_b32 s4, s1, 2
.LBB0_11:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[3:4], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 1, v8
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	ds_add_u32 v6, v7
.LBB0_13:                               ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v0, s1, v0
	v_add_co_u32 v3, s0, v3, s4
	v_add_nc_u32_e32 v6, s4, v6
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v0
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_11
.LBB0_14:                               ; %Flow51
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v0, v5
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21topologicalSortKernelPiS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 15
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21topologicalSortKernelPiS_S_S_, .Lfunc_end0-_Z21topologicalSortKernelPiS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 632
; NumSgprs: 17
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 17
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym sharedIndegree
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21topologicalSortKernelPiS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     17
    .sgpr_spill_count: 0
    .symbol:         _Z21topologicalSortKernelPiS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
