#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>

#define BLOCK_SIZE 16
#define GRID_SIZE 32
#define DIM 32

__global__ void initializeVelocity(float* velocity, int N) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int idz = blockIdx.z * blockDim.z + threadIdx.z;

    if (idx < N && idy < N && idz < N) {
        int index = idx + idy * N + idz * N * N;
        velocity[index] = 0.0f; // Initialize to zero for simplicity
    }
}

__global__ void applyNavierStokes(float* velocity, float* pressure, float* density, int N, float dt, float dx, float viscosity) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int idz = blockIdx.z * blockDim.z + threadIdx.z;

    if (idx > 0 && idx < N-1 && idy > 0 && idy < N-1 && idz > 0 && idz < N-1) {
        int index = idx + idy * N + idz * N * N;

        // Simple discretization of Navier-Stokes equations
        float u = velocity[index];
        float v = velocity[index + N];
        float w = velocity[index + N * N];

        float du_dx = (velocity[index + 1] - velocity[index - 1]) / (2 * dx);
        float dv_dy = (velocity[index + N + 1] - velocity[index + N - 1]) / (2 * dx);
        float dw_dz = (velocity[index + N * N + 1] - velocity[index + N * N - 1]) / (2 * dx);

        float du_dy = (velocity[index + N] - velocity[index - N]) / (2 * dx);
        float dv_dx = (velocity[index + 1] - velocity[index - 1]) / (2 * dx);

        float du_dz = (velocity[index + N * N] - velocity[index - N * N]) / (2 * dx);
        float dw_dx = (velocity[index + 1] - velocity[index - 1]) / (2 * dx);

        float dv_dz = (velocity[index + N * N + 1] - velocity[index + N * N - 1]) / (2 * dx);
        float dw_dy = (velocity[index + N + 1] - velocity[index + N - 1]) / (2 * dx);

        float laplacian_u = (velocity[index + 1] + velocity[index - 1] + velocity[index + N] + velocity[index - N] + velocity[index + N * N] + velocity[index - N * N] - 6 * u) / (dx * dx);
        float laplacian_v = (velocity[index + N + 1] + velocity[index + N - 1] + velocity[index + 2 * N] + velocity[index] + velocity[index + N * N + 1] + velocity[index + N * N - 1] - 6 * v) / (dx * dx);
        float laplacian_w = (velocity[index + N * N + 1] + velocity[index + N * N - 1] + velocity[index + 2 * N * N] + velocity[index] + velocity[index + 1] + velocity[index - 1] - 6 * w) / (dx * dx);

        float dp_dx = (pressure[index + 1] - pressure[index - 1]) / (2 * dx);
        float dp_dy = (pressure[index + N] - pressure[index - N]) / (2 * dx);
        float dp_dz = (pressure[index + N * N] - pressure[index - N * N]) / (2 * dx);

        velocity[index] = u - dt * (u * du_dx + v * du_dy + w * du_dz) + dt * viscosity * laplacian_u - dt * dp_dx / density[index];
        velocity[index + N] = v - dt * (u * dv_dx + v * dv_dy + w * dv_dz) + dt * viscosity * laplacian_v - dt * dp_dy / density[index];
        velocity[index + N * N] = w - dt * (u * dw_dx + v * dw_dy + w * dw_dz) + dt * viscosity * laplacian_w - dt * dp_dz / density[index];
    }
}

int main() {
    int N = DIM;
    size_t size = N * N * N * sizeof(float);

    float *h_velocity, *h_pressure, *h_density;
    float *d_velocity, *d_pressure, *d_density;

    h_velocity = (float*)malloc(size);
    h_pressure = (float*)malloc(size);
    h_density = (float*)malloc(size);

    cudaError_t err = cudaMalloc((void**)&d_velocity, size);
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    err = cudaMalloc((void**)&d_pressure, size);
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    err = cudaMalloc((void**)&d_density, size);
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE, BLOCK_SIZE);
    dim3 blocksPerGrid(GRID_SIZE, GRID_SIZE, GRID_SIZE);

    initializeVelocity<<<blocksPerGrid, threadsPerBlock>>>(d_velocity, N);
    err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Initialize pressure and density (simplified)
    cudaMemset(d_pressure, 0, size);
    cudaMemset(d_density, 1, size);

    float dt = 0.01f;
    float dx = 1.0f / (N - 1);
    float viscosity = 0.01f;

    for (int step = 0; step < 100; ++step) {
        applyNavierStokes<<<blocksPerGrid, threadsPerBlock>>>(d_velocity, d_pressure, d_density, N, dt, dx, viscosity);
        err = cudaGetLastError();
        if (err != cudaSuccess) {
            std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
            return -1;
        }
    }

    err = cudaMemcpy(h_velocity, d_velocity, size, cudaMemcpyDeviceToHost);
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    cudaFree(d_velocity);
    cudaFree(d_pressure);
    cudaFree(d_density);

    free(h_velocity);
    free(h_pressure);
    free(h_density);

    return 0;
}
	.file	"tmpxft_000c8d6f_00000000-6_cuda_code_084478.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3852:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3852:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4508:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4508:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z39__device_stub__Z18initializeVelocityPfiPfi
	.type	_Z39__device_stub__Z18initializeVelocityPfiPfi, @function
_Z39__device_stub__Z18initializeVelocityPfiPfi:
.LFB3874:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z18initializeVelocityPfi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3874:
	.size	_Z39__device_stub__Z18initializeVelocityPfiPfi, .-_Z39__device_stub__Z18initializeVelocityPfiPfi
	.globl	_Z18initializeVelocityPfi
	.type	_Z18initializeVelocityPfi, @function
_Z18initializeVelocityPfi:
.LFB3875:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z18initializeVelocityPfiPfi
	.cfi_endproc
.LFE3875:
	.size	_Z18initializeVelocityPfi, .-_Z18initializeVelocityPfi
	.globl	_Z45__device_stub__Z17applyNavierStokesPfS_S_ifffPfS_S_ifff
	.type	_Z45__device_stub__Z17applyNavierStokesPfS_S_ifffPfS_S_ifff, @function
_Z45__device_stub__Z17applyNavierStokesPfS_S_ifffPfS_S_ifff:
.LFB3876:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movss	%xmm0, 16(%rsp)
	movss	%xmm1, 12(%rsp)
	movss	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z17applyNavierStokesPfS_S_ifff(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L9:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3876:
	.size	_Z45__device_stub__Z17applyNavierStokesPfS_S_ifffPfS_S_ifff, .-_Z45__device_stub__Z17applyNavierStokesPfS_S_ifffPfS_S_ifff
	.globl	_Z17applyNavierStokesPfS_S_ifff
	.type	_Z17applyNavierStokesPfS_S_ifff, @function
_Z17applyNavierStokesPfS_S_ifff:
.LFB3877:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z17applyNavierStokesPfS_S_ifffPfS_S_ifff
	.cfi_endproc
.LFE3877:
	.size	_Z17applyNavierStokesPfS_S_ifff, .-_Z17applyNavierStokesPfS_S_ifff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$131072, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$131072, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	jne	.L29
	leaq	16(%rsp), %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L17
.L29:
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	orl	$-1, %eax
	jmp	.L14
.L17:
	leaq	24(%rsp), %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	jne	.L29
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16, %ecx
	movl	$32, %esi
	movabsq	$68719476752, %rdx
	movl	$16, 40(%rsp)
	movabsq	$137438953504, %rdi
	movq	%rdx, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$32, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	8(%rsp), %rdi
	movl	$32, %esi
	call	_Z39__device_stub__Z18initializeVelocityPfiPfi
.L20:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	jne	.L29
	movq	16(%rsp), %rdi
	movl	$131072, %edx
	xorl	%esi, %esi
	movl	$100, %r12d
	call	cudaMemset@PLT
	movq	24(%rsp), %rdi
	movl	$131072, %edx
	movl	$1, %esi
	call	cudaMemset@PLT
.L24:
	movl	40(%rsp), %ecx
	movq	32(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$32, %ecx
	movss	.LC1(%rip), %xmm2
	movss	.LC2(%rip), %xmm1
	movq	8(%rsp), %rdi
	movaps	%xmm2, %xmm0
	call	_Z45__device_stub__Z17applyNavierStokesPfS_S_ifffPfS_S_ifff
.L22:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	jne	.L29
	decl	%r12d
	jne	.L24
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$131072, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	jne	.L29
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	xorl	%eax, %eax
.L14:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z17applyNavierStokesPfS_S_ifff"
.LC4:
	.string	"_Z18initializeVelocityPfi"
.LC5:
	.string	"precalc_xorwow_matrix"
.LC6:
	.string	"precalc_xorwow_offset_matrix"
.LC7:
	.string	"mrg32k3aM1"
.LC8:
	.string	"mrg32k3aM2"
.LC9:
	.string	"mrg32k3aM1SubSeq"
.LC10:
	.string	"mrg32k3aM2SubSeq"
.LC11:
	.string	"mrg32k3aM1Seq"
.LC12:
	.string	"mrg32k3aM2Seq"
.LC13:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3879:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17applyNavierStokesPfS_S_ifff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18initializeVelocityPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3879:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1008981770
	.align 4
.LC2:
	.long	1023680776
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

#define BLOCK_SIZE 16
#define GRID_SIZE 32
#define DIM 32

__global__ void initializeVelocity(float* velocity, int N) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int idz = blockIdx.z * blockDim.z + threadIdx.z;

    if (idx < N && idy < N && idz < N) {
        int index = idx + idy * N + idz * N * N;
        velocity[index] = 0.0f; // Initialize to zero for simplicity
    }
}

__global__ void applyNavierStokes(float* velocity, float* pressure, float* density, int N, float dt, float dx, float viscosity) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int idz = blockIdx.z * blockDim.z + threadIdx.z;

    if (idx > 0 && idx < N-1 && idy > 0 && idy < N-1 && idz > 0 && idz < N-1) {
        int index = idx + idy * N + idz * N * N;

        // Simple discretization of Navier-Stokes equations
        float u = velocity[index];
        float v = velocity[index + N];
        float w = velocity[index + N * N];

        float du_dx = (velocity[index + 1] - velocity[index - 1]) / (2 * dx);
        float dv_dy = (velocity[index + N + 1] - velocity[index + N - 1]) / (2 * dx);
        float dw_dz = (velocity[index + N * N + 1] - velocity[index + N * N - 1]) / (2 * dx);

        float du_dy = (velocity[index + N] - velocity[index - N]) / (2 * dx);
        float dv_dx = (velocity[index + 1] - velocity[index - 1]) / (2 * dx);

        float du_dz = (velocity[index + N * N] - velocity[index - N * N]) / (2 * dx);
        float dw_dx = (velocity[index + 1] - velocity[index - 1]) / (2 * dx);

        float dv_dz = (velocity[index + N * N + 1] - velocity[index + N * N - 1]) / (2 * dx);
        float dw_dy = (velocity[index + N + 1] - velocity[index + N - 1]) / (2 * dx);

        float laplacian_u = (velocity[index + 1] + velocity[index - 1] + velocity[index + N] + velocity[index - N] + velocity[index + N * N] + velocity[index - N * N] - 6 * u) / (dx * dx);
        float laplacian_v = (velocity[index + N + 1] + velocity[index + N - 1] + velocity[index + 2 * N] + velocity[index] + velocity[index + N * N + 1] + velocity[index + N * N - 1] - 6 * v) / (dx * dx);
        float laplacian_w = (velocity[index + N * N + 1] + velocity[index + N * N - 1] + velocity[index + 2 * N * N] + velocity[index] + velocity[index + 1] + velocity[index - 1] - 6 * w) / (dx * dx);

        float dp_dx = (pressure[index + 1] - pressure[index - 1]) / (2 * dx);
        float dp_dy = (pressure[index + N] - pressure[index - N]) / (2 * dx);
        float dp_dz = (pressure[index + N * N] - pressure[index - N * N]) / (2 * dx);

        velocity[index] = u - dt * (u * du_dx + v * du_dy + w * du_dz) + dt * viscosity * laplacian_u - dt * dp_dx / density[index];
        velocity[index + N] = v - dt * (u * dv_dx + v * dv_dy + w * dv_dz) + dt * viscosity * laplacian_v - dt * dp_dy / density[index];
        velocity[index + N * N] = w - dt * (u * dw_dx + v * dw_dy + w * dw_dz) + dt * viscosity * laplacian_w - dt * dp_dz / density[index];
    }
}

int main() {
    int N = DIM;
    size_t size = N * N * N * sizeof(float);

    float *h_velocity, *h_pressure, *h_density;
    float *d_velocity, *d_pressure, *d_density;

    h_velocity = (float*)malloc(size);
    h_pressure = (float*)malloc(size);
    h_density = (float*)malloc(size);

    hipError_t err = hipMalloc((void**)&d_velocity, size);
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    err = hipMalloc((void**)&d_pressure, size);
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    err = hipMalloc((void**)&d_density, size);
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE, BLOCK_SIZE);
    dim3 blocksPerGrid(GRID_SIZE, GRID_SIZE, GRID_SIZE);

    initializeVelocity<<<blocksPerGrid, threadsPerBlock>>>(d_velocity, N);
    err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Initialize pressure and density (simplified)
    hipMemset(d_pressure, 0, size);
    hipMemset(d_density, 1, size);

    float dt = 0.01f;
    float dx = 1.0f / (N - 1);
    float viscosity = 0.01f;

    for (int step = 0; step < 100; ++step) {
        applyNavierStokes<<<blocksPerGrid, threadsPerBlock>>>(d_velocity, d_pressure, d_density, N, dt, dx, viscosity);
        err = hipGetLastError();
        if (err != hipSuccess) {
            std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
            return -1;
        }
    }

    err = hipMemcpy(h_velocity, d_velocity, size, hipMemcpyDeviceToHost);
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    hipFree(d_velocity);
    hipFree(d_pressure);
    hipFree(d_density);

    free(h_velocity);
    free(h_pressure);
    free(h_density);

    return 0;
}
	.text
	.file	"cuda_code_084478.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__initializeVelocityPfi # -- Begin function _Z33__device_stub__initializeVelocityPfi
	.type	_Z33__device_stub__initializeVelocityPfi,@function
_Z33__device_stub__initializeVelocityPfi: # @_Z33__device_stub__initializeVelocityPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18initializeVelocityPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__initializeVelocityPfi, .Lfunc_end0-_Z33__device_stub__initializeVelocityPfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__applyNavierStokesPfS_S_ifff # -- Begin function _Z32__device_stub__applyNavierStokesPfS_S_ifff
	.type	_Z32__device_stub__applyNavierStokesPfS_S_ifff,@function
_Z32__device_stub__applyNavierStokesPfS_S_ifff: # @_Z32__device_stub__applyNavierStokesPfS_S_ifff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	12(%rsp), %r8
	movss	%xmm1, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm2, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17applyNavierStokesPfS_S_ifff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z32__device_stub__applyNavierStokesPfS_S_ifff, .Lfunc_end1-_Z32__device_stub__applyNavierStokesPfS_S_ifff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x3d042108                      # float 0.0322580636
.LCPI2_1:
	.long	0x3c23d70a                      # float 0.00999999977
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$131072, %edi                   # imm = 0x20000
	callq	malloc
	movq	%rax, %rbx
	leaq	8(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.1:
	leaq	24(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.2:
	leaq	16(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.3:
	movabsq	$137438953504, %r14             # imm = 0x2000000020
	movabsq	$68719476752, %r15              # imm = 0x1000000010
	movq	%r14, %rdi
	movl	$32, %esi
	movq	%r15, %rdx
	movl	$16, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:
	movq	8(%rsp), %rdi
	movl	$32, %esi
	callq	_Z33__device_stub__initializeVelocityPfi
.LBB2_5:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB2_12
.LBB2_6:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB2_8
# %bb.7:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB2_9
.LBB2_8:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_9:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB2_10:
	movl	$-1, %eax
.LBB2_11:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_12:
	.cfi_def_cfa_offset 80
	movq	24(%rsp), %rdi
	movl	$131072, %edx                   # imm = 0x20000
	xorl	%esi, %esi
	callq	hipMemset
	movq	16(%rsp), %rdi
	movl	$131072, %edx                   # imm = 0x20000
	movl	$1, %esi
	callq	hipMemset
	movl	$100, %r12d
.LBB2_13:                               # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$32, %esi
	movq	%r15, %rdx
	movl	$16, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:                               #   in Loop: Header=BB2_13 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$32, %ecx
	movss	.LCPI2_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm2
	callq	_Z32__device_stub__applyNavierStokesPfS_S_ifff
.LBB2_15:                               #   in Loop: Header=BB2_13 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_18
# %bb.16:                               #   in Loop: Header=BB2_13 Depth=1
	decl	%r12d
	jne	.LBB2_13
# %bb.17:
	movq	8(%rsp), %rsi
	movl	$131072, %edx                   # imm = 0x20000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB2_19
.LBB2_18:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cerr, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB2_10
.LBB2_19:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	jmp	.LBB2_11
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18initializeVelocityPfi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17applyNavierStokesPfS_S_ifff, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18initializeVelocityPfi,@object # @_Z18initializeVelocityPfi
	.section	.rodata,"a",@progbits
	.globl	_Z18initializeVelocityPfi
	.p2align	3, 0x0
_Z18initializeVelocityPfi:
	.quad	_Z33__device_stub__initializeVelocityPfi
	.size	_Z18initializeVelocityPfi, 8

	.type	_Z17applyNavierStokesPfS_S_ifff,@object # @_Z17applyNavierStokesPfS_S_ifff
	.globl	_Z17applyNavierStokesPfS_S_ifff
	.p2align	3, 0x0
_Z17applyNavierStokesPfS_S_ifff:
	.quad	_Z32__device_stub__applyNavierStokesPfS_S_ifff
	.size	_Z17applyNavierStokesPfS_S_ifff, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18initializeVelocityPfi"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17applyNavierStokesPfS_S_ifff"
	.size	.L__unnamed_2, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__initializeVelocityPfi
	.addrsig_sym _Z32__device_stub__applyNavierStokesPfS_S_ifff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18initializeVelocityPfi
	.addrsig_sym _Z17applyNavierStokesPfS_S_ifff
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18initializeVelocityPfi ; -- Begin function _Z18initializeVelocityPfi
	.globl	_Z18initializeVelocityPfi
	.p2align	8
	.type	_Z18initializeVelocityPfi,@function
_Z18initializeVelocityPfi:              ; @_Z18initializeVelocityPfi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x1c
	s_load_b32 s2, s[0:1], 0x8
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_bfe_u32 v4, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s5, 0xffff
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s13, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	s_mov_b32 s3, exec_lo
	v_max3_i32 v3, v0, v1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v3
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18initializeVelocityPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18initializeVelocityPfi, .Lfunc_end0-_Z18initializeVelocityPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z17applyNavierStokesPfS_S_ifff ; -- Begin function _Z17applyNavierStokesPfS_S_ifff
	.globl	_Z17applyNavierStokesPfS_S_ifff
	.p2align	8
	.type	_Z17applyNavierStokesPfS_S_ifff,@function
_Z17applyNavierStokesPfS_S_ifff:        ; @_Z17applyNavierStokesPfS_S_ifff
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x34
	s_load_b128 s[8:11], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_bfe_u32 v4, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s5, s8, -1
	v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
	s_and_b32 s2, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_min_i32_e32 v3, v1, v0
	v_cmp_gt_u32_e64 s2, s5, v1
	v_cmp_lt_i32_e64 s3, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e64 s4, 0, v3
	v_cmp_gt_i32_e64 s5, s5, v2
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s3, s4, vcc_lo
	s_and_b32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v2, s8, v[1:2]
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mul_i32 s2, s8, s8
	s_ashr_i32 s13, s8, 31
	s_mov_b32 s12, s8
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[14:15], s[12:13], 2
	v_mad_u64_u32 v[15:16], null, v3, s8, v[0:1]
	s_lshl_b64 s[12:13], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_subrev_nc_u32_e32 v0, s8, v15
	v_subrev_nc_u32_e32 v2, s2, v15
	s_lshl_b32 s2, s2, 1
	s_ashr_i32 s3, s2, 31
	v_lshlrev_b64 v[16:17], 2, v[15:16]
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[18:19], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v17, vcc_lo
	v_lshlrev_b64 v[20:21], 2, v[2:3]
	v_add_co_u32 v8, vcc_lo, v10, s14
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v11, vcc_lo
	v_add_co_u32 v6, vcc_lo, v10, s12
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v11, vcc_lo
	v_add_co_u32 v22, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v24, vcc_lo, s4, v20
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v21, vcc_lo
	s_clause 0x4
	global_load_b96 v[12:14], v[10:11], off offset:-4
	global_load_b96 v[3:5], v[8:9], off offset:-4
	global_load_b96 v[0:2], v[6:7], off offset:-4
	global_load_b32 v30, v[22:23], off
	global_load_b32 v31, v[24:25], off
	v_add_co_u32 v22, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v23, vcc_lo, s7, v17, vcc_lo
	v_add3_u32 v24, s8, s8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v22, s14
	v_add_co_ci_u32_e32 v27, vcc_lo, s15, v23, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
	v_add_co_u32 v28, vcc_lo, v22, s12
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v23, vcc_lo
	v_ashrrev_i32_e32 v25, 31, v24
	v_add_co_u32 v20, vcc_lo, s6, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v21, vcc_lo
	s_clause 0x5
	global_load_b32 v26, v[26:27], off
	global_load_b32 v27, v[18:19], off
	global_load_b32 v28, v[28:29], off
	global_load_b32 v29, v[20:21], off
	global_load_b32 v32, v[22:23], off offset:4
	global_load_b32 v22, v[22:23], off offset:-4
	v_lshlrev_b64 v[18:19], 2, v[24:25]
	v_mul_f32_e64 v23, s10, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v21, vcc_lo, s3, v11, vcc_lo
	s_clause 0x1
	global_load_b32 v18, v[18:19], off
	global_load_b32 v19, v[20:21], off
	v_add_co_u32 v15, vcc_lo, s0, v16
	v_add_co_ci_u32_e32 v16, vcc_lo, s1, v17, vcc_lo
	v_add_f32_e64 v20, s10, s10
	global_load_b32 v17, v[15:16], off
	s_waitcnt vmcnt(13)
	v_add_f32_e32 v24, v14, v12
	s_waitcnt vmcnt(12)
	v_dual_sub_f32 v21, v14, v12 :: v_dual_sub_f32 v34, v5, v3
	s_waitcnt vmcnt(10)
	v_dual_sub_f32 v35, v2, v0 :: v_dual_sub_f32 v36, v4, v30
	s_waitcnt vmcnt(9)
	v_dual_sub_f32 v37, v1, v31 :: v_dual_add_f32 v24, v4, v24
	v_add_f32_e32 v3, v5, v3
	v_add_f32_e32 v5, v2, v0
	v_div_scale_f32 v40, null, v20, v20, v36
	v_div_scale_f32 v25, null, v20, v20, v21
	v_div_scale_f32 v38, null, v20, v20, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v45, v40
	v_div_scale_f32 v41, s2, v36, v20, v36
	v_rcp_f32_e32 v44, v38
	v_div_scale_f32 v33, vcc_lo, v21, v20, v21
	v_div_scale_f32 v39, s1, v35, v20, v35
	s_waitcnt vmcnt(7)
	v_sub_f32_e32 v26, v26, v27
	v_div_scale_f32 v42, null, v20, v20, v37
	s_waitcnt vmcnt(5)
	v_sub_f32_e32 v27, v28, v29
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v22, v32, v22
	v_add_f32_e32 v24, v24, v30
	v_rcp_f32_e32 v28, v25
	v_div_scale_f32 v29, null, v20, v20, v34
	v_div_scale_f32 v32, s0, v34, v20, v34
	v_rcp_f32_e32 v46, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v30, v29
	v_div_scale_f32 v43, s3, v37, v20, v37
	v_fma_f32 v47, -v25, v28, 1.0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v5, v5, v19
	v_dual_add_f32 v3, v3, v18 :: v_dual_add_f32 v24, v1, v24
	v_div_scale_f32 v18, null, v20, v20, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v28, v47, v28 :: v_dual_add_f32 v3, v13, v3
	v_dual_add_f32 v24, v31, v24 :: v_dual_add_f32 v5, v13, v5
	v_fma_f32 v31, -v40, v45, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v48, v18
	v_add_f32_e32 v2, v2, v3
	v_div_scale_f32 v19, s4, v22, v20, v22
	v_add_f32_e32 v3, v14, v5
	v_fma_f32 v14, -v38, v44, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v0, v0, v2 :: v_dual_fmac_f32 v45, v31, v45
	v_fma_f32 v5, -v29, v30, 1.0
	v_fma_f32 v47, -v42, v46, 1.0
	v_dual_fmac_f32 v44, v14, v44 :: v_dual_mul_f32 v49, v41, v45
	v_add_f32_e32 v2, v12, v3
	v_fma_f32 v3, -v18, v48, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v46, v47, v46
	v_mul_f32_e32 v47, v39, v44
	v_fma_f32 v58, -v40, v49, v41
	v_fmac_f32_e32 v30, v5, v30
	v_fmac_f32_e32 v48, v3, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v57, -v38, v47, v39
	v_fmac_f32_e32 v49, v58, v45
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v24, 0xc0c00000, v13 :: v_dual_mul_f32 v31, v32, v30
	v_mul_f32_e32 v12, v33, v28
	v_mul_f32_e32 v56, v19, v48
	v_fmac_f32_e32 v47, v57, v44
	v_div_scale_f32 v5, null, v23, v23, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v3, -v25, v12, v33
	v_fma_f32 v62, -v18, v56, v19
	v_div_scale_f32 v14, s5, v24, v23, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v51, v5
	v_fmac_f32_e32 v12, v3, v28
	v_fma_f32 v3, -v29, v31, v32
	v_fmac_f32_e32 v56, v62, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v25, -v25, v12, v33
	v_fmac_f32_e32 v31, v3, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_fma_f32 v18, -v18, v56, v19
	v_fma_f32 v3, -v5, v51, 1.0
	v_fmac_f32_e32 v0, 0xc0c00000, v4
	v_div_fmas_f32 v12, v25, v28, v12
	v_fma_f32 v25, -v29, v31, v32
	s_mov_b32 vcc_lo, s0
	v_dual_fmac_f32 v51, v3, v51 :: v_dual_fmac_f32 v2, 0xc0c00000, v1
	v_div_scale_f32 v52, null, v23, v23, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v19, v25, v30, v31
	v_mul_f32_e32 v25, v14, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v54, null, v23, v23, v2
	v_rcp_f32_e32 v60, v52
	v_div_scale_f32 v55, s7, v2, v23, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f32_e32 v61, v54
	v_div_scale_f32 v53, s6, v0, v23, v0
	v_fma_f32 v30, -v5, v25, v14
	v_fma_f32 v28, -v38, v47, v39
	v_fma_f32 v29, -v40, v49, v41
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
	v_fma_f32 v32, -v52, v60, 1.0
	v_fmac_f32_e32 v25, v30, v51
	v_div_fmas_f32 v28, v28, v44, v47
	v_fma_f32 v3, -v54, v61, 1.0
	s_mov_b32 vcc_lo, s2
	v_div_fixup_f32 v12, v12, v20, v21
	v_fma_f32 v5, -v5, v25, v14
	v_div_fmas_f32 v29, v29, v45, v49
	v_dual_fmac_f32 v61, v3, v61 :: v_dual_fmac_f32 v60, v32, v60
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v19, v19, v20, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v29, v29, v20, v36
	v_mul_f32_e32 v31, v55, v61
	v_dual_mul_f32 v50, v43, v46 :: v_dual_mul_f32 v3, v53, v60
	v_mul_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v54, v31, v55
	v_fma_f32 v59, -v42, v50, v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v32, -v52, v3, v53
	v_fma_f32 v29, v4, v29, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v12, v4, v19 :: v_dual_fmac_f32 v31, v30, v61
	v_dual_fmac_f32 v50, v59, v46 :: v_dual_fmac_f32 v3, v32, v60
	v_div_scale_f32 v30, null, v20, v20, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v33, -v42, v50, v43
	v_fma_f32 v14, -v52, v3, v53
	v_div_scale_f32 v42, s0, v27, v20, v27
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f32 v32, v33, v46, v50
	s_mov_b32 vcc_lo, s5
	v_div_fmas_f32 v5, v5, v51, v25
	v_fma_f32 v25, -v54, v31, v55
	s_mov_b32 vcc_lo, s6
	v_div_fixup_f32 v32, v32, v20, v37
	v_div_fmas_f32 v3, v14, v60, v3
	s_mov_b32 vcc_lo, s7
	v_div_fixup_f32 v5, v5, v23, v24
	v_div_fmas_f32 v14, v25, v61, v31
	s_mov_b32 vcc_lo, s4
	v_div_scale_f32 v25, null, v20, v20, v26
	v_div_fmas_f32 v18, v18, v48, v56
	v_rcp_f32_e32 v31, v30
	v_div_scale_f32 v38, vcc_lo, v26, v20, v26
	v_fmac_f32_e32 v29, v1, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(TRANS32_DEP_2)
	v_div_fixup_f32 v18, v18, v20, v22
	v_rcp_f32_e32 v22, v25
	v_div_fixup_f32 v0, v3, v23, v0
	v_div_fixup_f32 v2, v14, v23, v2
	v_fma_f32 v13, -v29, s9, v13
	v_fma_f32 v40, -v30, v31, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v39, -v25, v22, 1.0
	v_dual_fmac_f32 v31, v40, v31 :: v_dual_mul_f32 v18, s9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v22, v39, v22 :: v_dual_mul_f32 v39, v42, v31
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v33, null, v17, v17, v18
	v_div_scale_f32 v36, s1, v18, v17, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v43, -v30, v39, v42
	v_rcp_f32_e32 v41, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, v43, v31
	v_fma_f32 v30, -v30, v39, v42
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v33, v41, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v41, v40, v41
	v_mul_f32_e32 v21, v38, v22
	v_mul_f32_e32 v37, v36, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v40, -v25, v21, v38
	v_fma_f32 v32, -v33, v37, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, v40, v22
	v_mul_f32_e64 v40, s9, s11
	v_fmac_f32_e32 v37, v32, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v25, -v25, v21, v38
	v_fmac_f32_e32 v13, v40, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v21, v25, v22, v21
	v_fma_f32 v22, -v33, v37, v36
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v24, v30, v31, v39
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v22, v22, v41, v37
	v_div_fixup_f32 v5, v22, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v13, v5
	global_store_b32 v[10:11], v5, off
	global_load_b32 v5, v[15:16], off
	v_div_fixup_f32 v10, v21, v20, v26
	v_div_fixup_f32 v21, v28, v20, v35
	v_mul_f32_e32 v10, s9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v1, v21
	v_fma_f32 v4, -v12, s9, v4
	v_fma_f32 v1, -v12, s9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v4, v40, v0
	v_fmac_f32_e32 v1, v40, v2
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v11, null, v5, v5, v10
	v_div_scale_f32 v18, vcc_lo, v10, v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v13, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v11, v13, 1.0
	v_fmac_f32_e32 v13, v17, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v18, v13
	v_fma_f32 v22, -v11, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v22, v13
	v_fma_f32 v11, -v11, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v11, v13, v17
	v_div_fixup_f32 v0, v3, v5, v10
	v_div_fixup_f32 v3, v24, v20, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v0, v4, v0 :: v_dual_mul_f32 v3, s9, v3
	global_store_b32 v[8:9], v0, off
	global_load_b32 v0, v[15:16], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v4, null, v0, v0, v3
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v5
	v_div_scale_f32 v8, vcc_lo, v3, v0, v3
	v_mul_f32_e32 v9, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v4, v9, v8
	v_fmac_f32_e32 v9, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v9, v8
	v_div_fmas_f32 v4, v4, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v4, v0, v3
	v_sub_f32_e32 v0, v1, v0
	global_store_b32 v[6:7], v0, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17applyNavierStokesPfS_S_ifff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 63
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17applyNavierStokesPfS_S_ifff, .Lfunc_end1-_Z17applyNavierStokesPfS_S_ifff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2180
; NumSgprs: 18
; NumVgprs: 63
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 63
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18initializeVelocityPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18initializeVelocityPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17applyNavierStokesPfS_S_ifff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17applyNavierStokesPfS_S_ifff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     63
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
