#include <iostream>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <curand_kernel.h>

#define LAYERS 12
#define NEURONS 256
#define BATCH_SIZE 256
#define LEARNING_RATE 0.01f

__global__ void forwardPass(float* inputs, float* weights, float* biases, float* outputs, int layer) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NEURONS) {
        float sum = biases[layer * NEURONS + idx];
        for (int j = 0; j < NEURONS; ++j) {
            sum += inputs[j] * weights[layer * NEURONS * NEURONS + idx * NEURONS + j];
        }
        outputs[idx] = 1.0f / (1.0f + expf(-sum)); // Sigmoid activation
    }
}

__global__ void backwardPass(float* outputs, float* deltas, float* weights, float* biases, float* nextDeltas, int layer) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NEURONS) {
        float error = 0.0f;
        for (int j = 0; j < NEURONS; ++j) {
            error += nextDeltas[j] * weights[(layer + 1) * NEURONS * NEURONS + j * NEURONS + idx];
        }
        deltas[idx] = error * outputs[idx] * (1.0f - outputs[idx]);
    }
}

__global__ void updateWeights(float* weights, float* biases, float* inputs, float* deltas, int layer) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NEURONS) {
        for (int j = 0; j < NEURONS; ++j) {
            weights[layer * NEURONS * NEURONS + idx * NEURONS + j] -= LEARNING_RATE * inputs[j] * deltas[idx];
        }
        biases[layer * NEURONS + idx] -= LEARNING_RATE * deltas[idx];
    }
}

void trainNN(float* d_inputs, float* d_weights, float* d_biases, float* d_outputs, float* d_deltas, int epochs, int deviceCount) {
    dim3 blockSize(256);
    dim3 gridSize((NEURONS + blockSize.x - 1) / blockSize.x);

    for (int epoch = 0; epoch < epochs; ++epoch) {
        for (int layer = 0; layer < LAYERS; ++layer) {
            int device = layer % deviceCount;
            cudaSetDevice(device);

            if (layer == 0) {
                forwardPass<<<gridSize, blockSize>>>(d_inputs, d_weights, d_biases, d_outputs, layer);
            } else {
                forwardPass<<<gridSize, blockSize>>>(d_outputs + (layer - 1) * NEURONS, d_weights, d_biases, d_outputs + layer * NEURONS, layer);
            }
            cudaDeviceSynchronize();
        }

        for (int layer = LAYERS - 1; layer >= 0; --layer) {
            int device = layer % deviceCount;
            cudaSetDevice(device);

            if (layer == LAYERS - 1) {
                // Assuming last layer's deltas are computed from loss function
                // Here we use a dummy computation for demonstration
                backwardPass<<<gridSize, blockSize>>>(d_outputs + layer * NEURONS, d_deltas + layer * NEURONS, d_weights, d_biases, d_deltas + (layer + 1) * NEURONS, layer);
            } else {
                backwardPass<<<gridSize, blockSize>>>(d_outputs + layer * NEURONS, d_deltas + layer * NEURONS, d_weights, d_biases, d_deltas + (layer + 1) * NEURONS, layer);
            }
            cudaDeviceSynchronize();
        }

        for (int layer = 0; layer < LAYERS; ++layer) {
            int device = layer % deviceCount;
            cudaSetDevice(device);

            if (layer == 0) {
                updateWeights<<<gridSize, blockSize>>>(d_weights, d_biases, d_inputs, d_deltas, layer);
            } else {
                updateWeights<<<gridSize, blockSize>>>(d_weights, d_biases, d_outputs + (layer - 1) * NEURONS, d_deltas, layer);
            }
            cudaDeviceSynchronize();
        }
    }
}

int main() {
    int deviceCount;
    cudaGetDeviceCount(&deviceCount);
    if (deviceCount < 2) {
        std::cerr << "This program requires at least 2 GPUs to run." << std::endl;
        return 1;
    }

    size_t sizeWeights = sizeof(float) * LAYERS * NEURONS * NEURONS;
    size_t sizeBiases = sizeof(float) * LAYERS * NEURONS;
    size_t sizeInputs = sizeof(float) * NEURONS * BATCH_SIZE;
    size_t sizeOutputs = sizeof(float) * NEURONS * LAYERS;
    size_t sizeDeltas = sizeof(float) * NEURONS * LAYERS;

    float* h_weights = (float*)malloc(sizeWeights);
    float* h_biases = (float*)malloc(sizeBiases);
    float* h_inputs = (float*)malloc(sizeInputs);
    float* h_outputs = (float*)malloc(sizeOutputs);
    float* h_deltas = (float*)malloc(sizeDeltas);

    // Initialize weights, biases, and inputs with random values
    curandGenerator_t gen;
    curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
    curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
    curandGenerateUniform(gen, h_weights, sizeWeights / sizeof(float));
    curandGenerateUniform(gen, h_biases, sizeBiases / sizeof(float));
    curandGenerateUniform(gen, h_inputs, sizeInputs / sizeof(float));
    curandDestroyGenerator(gen);

    float* d_weights;
    float* d_biases;
    float* d_inputs;
    float* d_outputs;
    float* d_deltas;

    cudaMalloc(&d_weights, sizeWeights);
    cudaMalloc(&d_biases, sizeBiases);
    cudaMalloc(&d_inputs, sizeInputs);
    cudaMalloc(&d_outputs, sizeOutputs);
    cudaMalloc(&d_deltas, sizeDeltas);

    cudaMemcpy(d_weights, h_weights, sizeWeights, cudaMemcpyHostToDevice);
    cudaMemcpy(d_biases, h_biases, sizeBiases, cudaMemcpyHostToDevice);
    cudaMemcpy(d_inputs, h_inputs, sizeInputs, cudaMemcpyHostToDevice);

    int epochs = 1000;
    trainNN(d_inputs, d_weights, d_biases, d_outputs, d_deltas, epochs, deviceCount);

    cudaMemcpy(h_outputs, d_outputs, sizeOutputs, cudaMemcpyDeviceToHost);

    cudaFree(d_weights);
    cudaFree(d_biases);
    cudaFree(d_inputs);
    cudaFree(d_outputs);
    cudaFree(d_deltas);

    free(h_weights);
    free(h_biases);
    free(h_inputs);
    free(h_outputs);
    free(h_deltas);

    return 0;
}
	.file	"tmpxft_00076469_00000000-6_cuda_code_051012.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3853:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3853:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z11forwardPassPfS_S_S_iPfS_S_S_i
	.type	_Z38__device_stub__Z11forwardPassPfS_S_S_iPfS_S_S_i, @function
_Z38__device_stub__Z11forwardPassPfS_S_S_iPfS_S_S_i:
.LFB3875:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z11forwardPassPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3875:
	.size	_Z38__device_stub__Z11forwardPassPfS_S_S_iPfS_S_S_i, .-_Z38__device_stub__Z11forwardPassPfS_S_S_iPfS_S_S_i
	.globl	_Z11forwardPassPfS_S_S_i
	.type	_Z11forwardPassPfS_S_S_i, @function
_Z11forwardPassPfS_S_S_i:
.LFB3876:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z11forwardPassPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE3876:
	.size	_Z11forwardPassPfS_S_S_i, .-_Z11forwardPassPfS_S_S_i
	.globl	_Z41__device_stub__Z12backwardPassPfS_S_S_S_iPfS_S_S_S_i
	.type	_Z41__device_stub__Z12backwardPassPfS_S_S_S_iPfS_S_S_S_i, @function
_Z41__device_stub__Z12backwardPassPfS_S_S_S_iPfS_S_S_S_i:
.LFB3877:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12backwardPassPfS_S_S_S_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3877:
	.size	_Z41__device_stub__Z12backwardPassPfS_S_S_S_iPfS_S_S_S_i, .-_Z41__device_stub__Z12backwardPassPfS_S_S_S_iPfS_S_S_S_i
	.globl	_Z12backwardPassPfS_S_S_S_i
	.type	_Z12backwardPassPfS_S_S_S_i, @function
_Z12backwardPassPfS_S_S_S_i:
.LFB3878:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z12backwardPassPfS_S_S_S_iPfS_S_S_S_i
	.cfi_endproc
.LFE3878:
	.size	_Z12backwardPassPfS_S_S_S_i, .-_Z12backwardPassPfS_S_S_S_i
	.globl	_Z40__device_stub__Z13updateWeightsPfS_S_S_iPfS_S_S_i
	.type	_Z40__device_stub__Z13updateWeightsPfS_S_S_iPfS_S_S_i, @function
_Z40__device_stub__Z13updateWeightsPfS_S_S_iPfS_S_S_i:
.LFB3879:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z13updateWeightsPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L13:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3879:
	.size	_Z40__device_stub__Z13updateWeightsPfS_S_S_iPfS_S_S_i, .-_Z40__device_stub__Z13updateWeightsPfS_S_S_iPfS_S_S_i
	.globl	_Z13updateWeightsPfS_S_S_i
	.type	_Z13updateWeightsPfS_S_S_i, @function
_Z13updateWeightsPfS_S_S_i:
.LFB3880:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z13updateWeightsPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE3880:
	.size	_Z13updateWeightsPfS_S_S_i, .-_Z13updateWeightsPfS_S_S_i
	.globl	_Z7trainNNPfS_S_S_S_ii
	.type	_Z7trainNNPfS_S_S_S_ii, @function
_Z7trainNNPfS_S_S_S_ii:
.LFB3849:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rcx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r8, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%rax, 76(%rsp)
	movq	%rax, 84(%rsp)
	leaq	11264(%rcx), %rax
	movq	%rdi, 32(%rsp)
	movq	%rsi, 8(%rsp)
	movq	%rdx, 16(%rsp)
	movl	%r9d, 60(%rsp)
	movl	$1, 92(%rsp)
	movq	%rax, 40(%rsp)
.L19:
	movl	60(%rsp), %eax
	cmpl	%eax, %r14d
	jge	.L43
	leaq	-1024(%r12), %r15
	xorl	%ebx, %ebx
	movq	%r15, %r13
.L24:
	movl	%ebx, %eax
	cltd
	idivl	160(%rsp)
	movl	%edx, %edi
	call	cudaSetDevice@PLT
	testl	%ebx, %ebx
	movl	80(%rsp), %ecx
	movq	84(%rsp), %rdi
	movl	92(%rsp), %esi
	movl	$256, 72(%rsp)
	movl	$0, %r9d
	movl	$0, %r8d
	movq	72(%rsp), %rdx
	jne	.L20
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	xorl	%r8d, %r8d
	movq	%r12, %rcx
	movq	32(%rsp), %rdi
	jmp	.L40
.L20:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	%ebx, %r8d
	movq	%r13, %rdi
	leaq	1024(%r13), %rcx
.L40:
	call	_Z38__device_stub__Z11forwardPassPfS_S_S_iPfS_S_S_i
.L22:
	call	cudaDeviceSynchronize@PLT
	incl	%ebx
	addq	$1024, %r13
	cmpl	$12, %ebx
	jne	.L24
	movq	40(%rsp), %rax
	movl	$11, %ebx
	movq	%rax, 24(%rsp)
	leaq	12288(%rbp), %rax
	movq	%rax, 48(%rsp)
	movq	%rax, %r13
.L29:
	movl	%ebx, %eax
	cltd
	idivl	160(%rsp)
	movl	%edx, %edi
	call	cudaSetDevice@PLT
	cmpl	$11, %ebx
	movl	80(%rsp), %ecx
	movl	92(%rsp), %esi
	movl	$256, 72(%rsp)
	movq	84(%rsp), %rdi
	movl	$0, %r9d
	movl	$0, %r8d
	movq	72(%rsp), %rdx
	jne	.L25
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	48(%rsp), %r8
	movq	16(%rsp), %rcx
	leaq	11264(%rbp), %rsi
	movl	$11, %r9d
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rdi
	jmp	.L41
.L25:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	movl	%ebx, %r9d
	movq	%r13, %r8
	movq	24(%rsp), %rdi
	leaq	-1024(%r13), %rsi
.L41:
	call	_Z41__device_stub__Z12backwardPassPfS_S_S_S_iPfS_S_S_S_i
.L27:
	call	cudaDeviceSynchronize@PLT
	decl	%ebx
	subq	$1024, %r13
	subq	$1024, 24(%rsp)
	cmpl	$-1, %ebx
	jne	.L29
	xorl	%ebx, %ebx
.L34:
	movl	%ebx, %eax
	cltd
	idivl	160(%rsp)
	movl	%edx, %edi
	call	cudaSetDevice@PLT
	testl	%ebx, %ebx
	movl	80(%rsp), %ecx
	movq	84(%rsp), %rdi
	movl	92(%rsp), %esi
	movl	$256, 72(%rsp)
	movl	$0, %r9d
	movl	$0, %r8d
	movq	72(%rsp), %rdx
	jne	.L30
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	32(%rsp), %rdx
	xorl	%r8d, %r8d
	movq	%rbp, %rcx
	jmp	.L42
.L30:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movl	%ebx, %r8d
	movq	%rbp, %rcx
	movq	%r15, %rdx
.L42:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z40__device_stub__Z13updateWeightsPfS_S_S_iPfS_S_S_i
.L32:
	call	cudaDeviceSynchronize@PLT
	incl	%ebx
	addq	$1024, %r15
	cmpl	$12, %ebx
	jne	.L34
	incl	%r14d
	jmp	.L19
.L43:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	_Z7trainNNPfS_S_S_S_ii, .-_Z7trainNNPfS_S_S_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"This program requires at least 2 GPUs to run."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3850:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
	cmpl	$1, 4(%rsp)
	jg	.L45
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %eax
	jmp	.L44
.L45:
	movl	$3145728, %edi
	call	malloc@PLT
	movl	$12288, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$262144, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$12288, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$100, %esi
	movq	%rax, %r13
	call	curandCreateGenerator@PLT
	movq	8(%rsp), %rdi
	movl	$1234, %esi
	call	curandSetPseudoRandomGeneratorSeed@PLT
	movq	8(%rsp), %rdi
	movl	$786432, %edx
	movq	%r12, %rsi
	call	curandGenerateUniform@PLT
	movq	8(%rsp), %rdi
	movl	$3072, %edx
	movq	%rbp, %rsi
	call	curandGenerateUniform@PLT
	movq	8(%rsp), %rdi
	movl	$65536, %edx
	movq	%rbx, %rsi
	call	curandGenerateUniform@PLT
	movq	8(%rsp), %rdi
	call	curandDestroyGenerator@PLT
	leaq	16(%rsp), %rdi
	movl	$3145728, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$12288, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$12288, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$12288, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$3145728, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$12288, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	movl	$1000, %r9d
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	12(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 128
	movq	64(%rsp), %r8
	movq	32(%rsp), %rsi
	movq	48(%rsp), %rdi
	movq	56(%rsp), %rcx
	movq	40(%rsp), %rdx
	call	_Z7trainNNPfS_S_S_S_ii
	popq	%rdx
	.cfi_def_cfa_offset 120
	popq	%rcx
	.cfi_def_cfa_offset 112
	movl	$12288, %edx
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	xorl	%eax, %eax
.L44:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3850:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z13updateWeightsPfS_S_S_i"
.LC2:
	.string	"_Z12backwardPassPfS_S_S_S_i"
.LC3:
	.string	"_Z11forwardPassPfS_S_S_i"
.LC4:
	.string	"precalc_xorwow_matrix"
.LC5:
	.string	"precalc_xorwow_offset_matrix"
.LC6:
	.string	"mrg32k3aM1"
.LC7:
	.string	"mrg32k3aM2"
.LC8:
	.string	"mrg32k3aM1SubSeq"
.LC9:
	.string	"mrg32k3aM2SubSeq"
.LC10:
	.string	"mrg32k3aM1Seq"
.LC11:
	.string	"mrg32k3aM2Seq"
.LC12:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3882:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13updateWeightsPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12backwardPassPfS_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11forwardPassPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3882:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

#include <hiprand/hiprand_kernel.h>

#define LAYERS 12
#define NEURONS 256
#define BATCH_SIZE 256
#define LEARNING_RATE 0.01f

__global__ void forwardPass(float* inputs, float* weights, float* biases, float* outputs, int layer) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NEURONS) {
        float sum = biases[layer * NEURONS + idx];
        for (int j = 0; j < NEURONS; ++j) {
            sum += inputs[j] * weights[layer * NEURONS * NEURONS + idx * NEURONS + j];
        }
        outputs[idx] = 1.0f / (1.0f + expf(-sum)); // Sigmoid activation
    }
}

__global__ void backwardPass(float* outputs, float* deltas, float* weights, float* biases, float* nextDeltas, int layer) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NEURONS) {
        float error = 0.0f;
        for (int j = 0; j < NEURONS; ++j) {
            error += nextDeltas[j] * weights[(layer + 1) * NEURONS * NEURONS + j * NEURONS + idx];
        }
        deltas[idx] = error * outputs[idx] * (1.0f - outputs[idx]);
    }
}

__global__ void updateWeights(float* weights, float* biases, float* inputs, float* deltas, int layer) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NEURONS) {
        for (int j = 0; j < NEURONS; ++j) {
            weights[layer * NEURONS * NEURONS + idx * NEURONS + j] -= LEARNING_RATE * inputs[j] * deltas[idx];
        }
        biases[layer * NEURONS + idx] -= LEARNING_RATE * deltas[idx];
    }
}

void trainNN(float* d_inputs, float* d_weights, float* d_biases, float* d_outputs, float* d_deltas, int epochs, int deviceCount) {
    dim3 blockSize(256);
    dim3 gridSize((NEURONS + blockSize.x - 1) / blockSize.x);

    for (int epoch = 0; epoch < epochs; ++epoch) {
        for (int layer = 0; layer < LAYERS; ++layer) {
            int device = layer % deviceCount;
            hipSetDevice(device);

            if (layer == 0) {
                forwardPass<<<gridSize, blockSize>>>(d_inputs, d_weights, d_biases, d_outputs, layer);
            } else {
                forwardPass<<<gridSize, blockSize>>>(d_outputs + (layer - 1) * NEURONS, d_weights, d_biases, d_outputs + layer * NEURONS, layer);
            }
            hipDeviceSynchronize();
        }

        for (int layer = LAYERS - 1; layer >= 0; --layer) {
            int device = layer % deviceCount;
            hipSetDevice(device);

            if (layer == LAYERS - 1) {
                // Assuming last layer's deltas are computed from loss function
                // Here we use a dummy computation for demonstration
                backwardPass<<<gridSize, blockSize>>>(d_outputs + layer * NEURONS, d_deltas + layer * NEURONS, d_weights, d_biases, d_deltas + (layer + 1) * NEURONS, layer);
            } else {
                backwardPass<<<gridSize, blockSize>>>(d_outputs + layer * NEURONS, d_deltas + layer * NEURONS, d_weights, d_biases, d_deltas + (layer + 1) * NEURONS, layer);
            }
            hipDeviceSynchronize();
        }

        for (int layer = 0; layer < LAYERS; ++layer) {
            int device = layer % deviceCount;
            hipSetDevice(device);

            if (layer == 0) {
                updateWeights<<<gridSize, blockSize>>>(d_weights, d_biases, d_inputs, d_deltas, layer);
            } else {
                updateWeights<<<gridSize, blockSize>>>(d_weights, d_biases, d_outputs + (layer - 1) * NEURONS, d_deltas, layer);
            }
            hipDeviceSynchronize();
        }
    }
}

int main() {
    int deviceCount;
    hipGetDeviceCount(&deviceCount);
    if (deviceCount < 2) {
        std::cerr << "This program requires at least 2 GPUs to run." << std::endl;
        return 1;
    }

    size_t sizeWeights = sizeof(float) * LAYERS * NEURONS * NEURONS;
    size_t sizeBiases = sizeof(float) * LAYERS * NEURONS;
    size_t sizeInputs = sizeof(float) * NEURONS * BATCH_SIZE;
    size_t sizeOutputs = sizeof(float) * NEURONS * LAYERS;
    size_t sizeDeltas = sizeof(float) * NEURONS * LAYERS;

    float* h_weights = (float*)malloc(sizeWeights);
    float* h_biases = (float*)malloc(sizeBiases);
    float* h_inputs = (float*)malloc(sizeInputs);
    float* h_outputs = (float*)malloc(sizeOutputs);
    float* h_deltas = (float*)malloc(sizeDeltas);

    // Initialize weights, biases, and inputs with random values
    hiprandGenerator_t gen;
    hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
    hiprandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
    hiprandGenerateUniform(gen, h_weights, sizeWeights / sizeof(float));
    hiprandGenerateUniform(gen, h_biases, sizeBiases / sizeof(float));
    hiprandGenerateUniform(gen, h_inputs, sizeInputs / sizeof(float));
    hiprandDestroyGenerator(gen);

    float* d_weights;
    float* d_biases;
    float* d_inputs;
    float* d_outputs;
    float* d_deltas;

    hipMalloc(&d_weights, sizeWeights);
    hipMalloc(&d_biases, sizeBiases);
    hipMalloc(&d_inputs, sizeInputs);
    hipMalloc(&d_outputs, sizeOutputs);
    hipMalloc(&d_deltas, sizeDeltas);

    hipMemcpy(d_weights, h_weights, sizeWeights, hipMemcpyHostToDevice);
    hipMemcpy(d_biases, h_biases, sizeBiases, hipMemcpyHostToDevice);
    hipMemcpy(d_inputs, h_inputs, sizeInputs, hipMemcpyHostToDevice);

    int epochs = 1000;
    trainNN(d_inputs, d_weights, d_biases, d_outputs, d_deltas, epochs, deviceCount);

    hipMemcpy(h_outputs, d_outputs, sizeOutputs, hipMemcpyDeviceToHost);

    hipFree(d_weights);
    hipFree(d_biases);
    hipFree(d_inputs);
    hipFree(d_outputs);
    hipFree(d_deltas);

    free(h_weights);
    free(h_biases);
    free(h_inputs);
    free(h_outputs);
    free(h_deltas);

    return 0;
}
	.text
	.file	"cuda_code_051012.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z26__device_stub__forwardPassPfS_S_S_i # -- Begin function _Z26__device_stub__forwardPassPfS_S_S_i
	.type	_Z26__device_stub__forwardPassPfS_S_S_i,@function
_Z26__device_stub__forwardPassPfS_S_S_i: # @_Z26__device_stub__forwardPassPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11forwardPassPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__forwardPassPfS_S_S_i, .Lfunc_end0-_Z26__device_stub__forwardPassPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__backwardPassPfS_S_S_S_i # -- Begin function _Z27__device_stub__backwardPassPfS_S_S_S_i
	.type	_Z27__device_stub__backwardPassPfS_S_S_S_i,@function
_Z27__device_stub__backwardPassPfS_S_S_S_i: # @_Z27__device_stub__backwardPassPfS_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12backwardPassPfS_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__backwardPassPfS_S_S_S_i, .Lfunc_end1-_Z27__device_stub__backwardPassPfS_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__updateWeightsPfS_S_S_i # -- Begin function _Z28__device_stub__updateWeightsPfS_S_S_i
	.type	_Z28__device_stub__updateWeightsPfS_S_S_i,@function
_Z28__device_stub__updateWeightsPfS_S_S_i: # @_Z28__device_stub__updateWeightsPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13updateWeightsPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__updateWeightsPfS_S_S_i, .Lfunc_end2-_Z28__device_stub__updateWeightsPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z7trainNNPfS_S_S_S_ii          # -- Begin function _Z7trainNNPfS_S_S_S_ii
	.type	_Z7trainNNPfS_S_S_S_ii,@function
_Z7trainNNPfS_S_S_S_ii:                 # @_Z7trainNNPfS_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, 16(%rsp)                   # 8-byte Spill
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movq	%rdx, 8(%rsp)                   # 8-byte Spill
	movq	%rdi, 40(%rsp)                  # 8-byte Spill
	movl	%r9d, 36(%rsp)                  # 4-byte Spill
	testl	%r9d, %r9d
	jle	.LBB3_23
# %bb.1:                                # %.preheader138.lr.ph
	movq	%rsi, %r13
	movl	144(%rsp), %r12d
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	movl	$11264, %edx                    # imm = 0x2C00
	movq	24(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rdx), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	16(%rsp), %rax                  # 8-byte Reload
	addq	%rax, %rdx
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	addq	$12288, %rax                    # imm = 0x3000
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	leaq	-1024(%rcx), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	leaq	255(%rbx), %rbp
.LBB3_2:                                # %.preheader138
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_3 Depth 2
                                        #     Child Loop BB3_11 Depth 2
                                        #     Child Loop BB3_19 Depth 2
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	24(%rsp), %r15                  # 8-byte Reload
	xorl	%r14d, %r14d
.LBB3_3:                                #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r14d, %eax
	cltd
	idivl	%r12d
	movl	%edx, %edi
	callq	hipSetDevice
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testq	%r14, %r14
	je	.LBB3_4
# %bb.6:                                #   in Loop: Header=BB3_3 Depth=2
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.7:                                #   in Loop: Header=BB3_3 Depth=2
	leaq	-1024(%r15), %rdi
	movq	%r13, %rsi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movq	%r15, %rcx
	movl	%r14d, %r8d
	jmp	.LBB3_8
.LBB3_4:                                #   in Loop: Header=BB3_3 Depth=2
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.5:                                #   in Loop: Header=BB3_3 Depth=2
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movq	%r13, %rsi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movq	24(%rsp), %rcx                  # 8-byte Reload
	xorl	%r8d, %r8d
.LBB3_8:                                #   in Loop: Header=BB3_3 Depth=2
	callq	_Z26__device_stub__forwardPassPfS_S_S_i
.LBB3_9:                                #   in Loop: Header=BB3_3 Depth=2
	callq	hipDeviceSynchronize
	incq	%r14
	addq	$1024, %r15                     # imm = 0x400
	cmpq	$12, %r14
	jne	.LBB3_3
# %bb.10:                               # %.preheader137.preheader
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	$11, %r15d
	xorl	%r14d, %r14d
.LBB3_11:                               # %.preheader137
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r15d, %eax
	cltd
	idivl	%r12d
	movl	%edx, %edi
	callq	hipSetDevice
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testq	%r14, %r14
	je	.LBB3_12
# %bb.14:                               #   in Loop: Header=BB3_11 Depth=2
	testl	%eax, %eax
	jne	.LBB3_17
# %bb.15:                               #   in Loop: Header=BB3_11 Depth=2
	movq	48(%rsp), %rax                  # 8-byte Reload
	leaq	(%rax,%r14), %rdi
	movq	16(%rsp), %rax                  # 8-byte Reload
	leaq	(%rax,%r14), %rsi
	addq	$11264, %rsi                    # imm = 0x2C00
	leaq	12288(%rax,%r14), %r8
	movq	%r13, %rdx
	movq	8(%rsp), %rcx                   # 8-byte Reload
	movl	%r15d, %r9d
	jmp	.LBB3_16
.LBB3_12:                               #   in Loop: Header=BB3_11 Depth=2
	testl	%eax, %eax
	jne	.LBB3_17
# %bb.13:                               #   in Loop: Header=BB3_11 Depth=2
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movq	8(%rsp), %rcx                   # 8-byte Reload
	movq	72(%rsp), %r8                   # 8-byte Reload
	movl	$11, %r9d
.LBB3_16:                               #   in Loop: Header=BB3_11 Depth=2
	callq	_Z27__device_stub__backwardPassPfS_S_S_S_i
.LBB3_17:                               #   in Loop: Header=BB3_11 Depth=2
	callq	hipDeviceSynchronize
	addq	$-1024, %r14                    # imm = 0xFC00
	decl	%r15d
	cmpq	$-12288, %r14                   # imm = 0xD000
	jne	.LBB3_11
# %bb.18:                               # %.preheader.preheader
                                        #   in Loop: Header=BB3_2 Depth=1
	movq	56(%rsp), %r14                  # 8-byte Reload
	xorl	%r15d, %r15d
.LBB3_19:                               # %.preheader
                                        #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r15d, %eax
	cltd
	idivl	%r12d
	movl	%edx, %edi
	callq	hipSetDevice
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testq	%r15, %r15
	je	.LBB3_20
# %bb.24:                               #   in Loop: Header=BB3_19 Depth=2
	testl	%eax, %eax
	jne	.LBB3_27
# %bb.25:                               #   in Loop: Header=BB3_19 Depth=2
	movq	%r13, %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	%r14, %rdx
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movl	%r15d, %r8d
	jmp	.LBB3_26
.LBB3_20:                               #   in Loop: Header=BB3_19 Depth=2
	testl	%eax, %eax
	jne	.LBB3_27
# %bb.21:                               #   in Loop: Header=BB3_19 Depth=2
	movq	%r13, %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movq	16(%rsp), %rcx                  # 8-byte Reload
	xorl	%r8d, %r8d
.LBB3_26:                               #   in Loop: Header=BB3_19 Depth=2
	callq	_Z28__device_stub__updateWeightsPfS_S_S_i
.LBB3_27:                               #   in Loop: Header=BB3_19 Depth=2
	callq	hipDeviceSynchronize
	incq	%r15
	addq	$1024, %r14                     # imm = 0x400
	cmpq	$12, %r15
	jne	.LBB3_19
# %bb.22:                               #   in Loop: Header=BB3_2 Depth=1
	movq	64(%rsp), %rax                  # 8-byte Reload
	incl	%eax
	cmpl	36(%rsp), %eax                  # 4-byte Folded Reload
	jne	.LBB3_2
.LBB3_23:                               # %._crit_edge
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z7trainNNPfS_S_S_S_ii, .Lfunc_end3-_Z7trainNNPfS_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	20(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$1, (%rbx)
	jg	.LBB4_2
# %bb.1:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$45, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$1, %eax
	jmp	.LBB4_3
.LBB4_2:
	movl	$3145728, %edi                  # imm = 0x300000
	callq	malloc
	movq	%rax, %r12
	movl	$12288, %edi                    # imm = 0x3000
	callq	malloc
	movq	%rax, %r14
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %r15
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	$12288, %edi                    # imm = 0x3000
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	leaq	96(%rsp), %rbx
	movq	%rbx, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hiprandCreateGenerator
	movq	(%rbx), %rdi
	movl	$1234, %esi                     # imm = 0x4D2
	callq	hiprandSetPseudoRandomGeneratorSeed
	movq	(%rbx), %rdi
	movl	$786432, %edx                   # imm = 0xC0000
	movq	%r12, %rsi
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	callq	hiprandGenerateUniform
	movq	(%rbx), %rdi
	movl	$3072, %edx                     # imm = 0xC00
	movq	%r14, %rsi
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	callq	hiprandGenerateUniform
	movq	(%rbx), %rdi
	movl	$65536, %edx                    # imm = 0x10000
	movq	%r15, %rsi
	callq	hiprandGenerateUniform
	movq	(%rbx), %rdi
	callq	hiprandDestroyGenerator
	leaq	88(%rsp), %rbp
	movl	$3145728, %esi                  # imm = 0x300000
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	80(%rsp), %r15
	movl	$12288, %esi                    # imm = 0x3000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	72(%rsp), %rbx
	movl	$262144, %esi                   # imm = 0x40000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	64(%rsp), %r13
	movl	$12288, %esi                    # imm = 0x3000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$12288, %esi                    # imm = 0x3000
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$3145728, %edx                  # imm = 0x300000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movl	$12288, %edx                    # imm = 0x3000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	movq	32(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movq	(%rbp), %rsi
	movq	(%r15), %rdx
	movq	(%r13), %rcx
	leaq	24(%rsp), %rax
	movq	(%rax), %r8
	movl	20(%rsp), %eax
	movl	%eax, (%rsp)
	movl	$1000, %r9d                     # imm = 0x3E8
	callq	_Z7trainNNPfS_S_S_S_ii
	movq	(%r13), %rsi
	movl	$12288, %edx                    # imm = 0x3000
	movq	56(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	callq	hipFree
	movq	(%r15), %rdi
	callq	hipFree
	movq	(%rbx), %rdi
	callq	hipFree
	movq	(%r13), %rdi
	callq	hipFree
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	40(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
.LBB4_3:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11forwardPassPfS_S_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12backwardPassPfS_S_S_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13updateWeightsPfS_S_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11forwardPassPfS_S_S_i,@object # @_Z11forwardPassPfS_S_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z11forwardPassPfS_S_S_i
	.p2align	3, 0x0
_Z11forwardPassPfS_S_S_i:
	.quad	_Z26__device_stub__forwardPassPfS_S_S_i
	.size	_Z11forwardPassPfS_S_S_i, 8

	.type	_Z12backwardPassPfS_S_S_S_i,@object # @_Z12backwardPassPfS_S_S_S_i
	.globl	_Z12backwardPassPfS_S_S_S_i
	.p2align	3, 0x0
_Z12backwardPassPfS_S_S_S_i:
	.quad	_Z27__device_stub__backwardPassPfS_S_S_S_i
	.size	_Z12backwardPassPfS_S_S_S_i, 8

	.type	_Z13updateWeightsPfS_S_S_i,@object # @_Z13updateWeightsPfS_S_S_i
	.globl	_Z13updateWeightsPfS_S_S_i
	.p2align	3, 0x0
_Z13updateWeightsPfS_S_S_i:
	.quad	_Z28__device_stub__updateWeightsPfS_S_S_i
	.size	_Z13updateWeightsPfS_S_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"This program requires at least 2 GPUs to run."
	.size	.L.str, 46

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11forwardPassPfS_S_S_i"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12backwardPassPfS_S_S_S_i"
	.size	.L__unnamed_2, 28

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13updateWeightsPfS_S_S_i"
	.size	.L__unnamed_3, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__forwardPassPfS_S_S_i
	.addrsig_sym _Z27__device_stub__backwardPassPfS_S_S_S_i
	.addrsig_sym _Z28__device_stub__updateWeightsPfS_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11forwardPassPfS_S_S_i
	.addrsig_sym _Z12backwardPassPfS_S_S_S_i
	.addrsig_sym _Z13updateWeightsPfS_S_S_i
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11forwardPassPfS_S_S_i ; -- Begin function _Z11forwardPassPfS_S_S_i
	.globl	_Z11forwardPassPfS_S_S_i
	.p2align	8
	.type	_Z11forwardPassPfS_S_S_i,@function
_Z11forwardPassPfS_S_S_i:               ; @_Z11forwardPassPfS_S_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x100, v1
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_lshl_add_u32 v2, s8, 8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_lshl_b32 s4, s8, 16
	global_load_b32 v0, v[2:3], off
	v_lshl_add_u32 v2, v1, 8, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_mov_b64 s[2:3], 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v2, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_add_u32 s4, s0, s2
	s_addc_u32 s5, s1, s3
	s_add_u32 s2, s2, 4
	global_load_b32 v4, v[4:5], off
	s_load_b32 s4, s[4:5], 0x0
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0x400
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s4, v4
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0xbfb8aa3b, v0
	v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v0
	v_rndne_f32_e32 v3, v2
	v_fma_f32 v4, 0xbfb8aa3b, v0, -v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v2, v3
	v_fmamk_f32 v4, v0, 0xb2a5705f, v4
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v4
	v_exp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v0
	v_cndmask_b32_e32 v0, 0x7f800000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, 1.0, v0
	v_div_scale_f32 v0, null, v3, v3, 1.0
	v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v0, v4, 1.0
	v_fmac_f32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v4
	v_fma_f32 v2, -v0, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v2, v4
	v_ashrrev_i32_e32 v2, 31, v1
	v_fma_f32 v0, -v0, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v4, v0, v4, v6
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v2, v4, v3, 1.0
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11forwardPassPfS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11forwardPassPfS_S_S_i, .Lfunc_end0-_Z11forwardPassPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 492
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12backwardPassPfS_S_S_S_i ; -- Begin function _Z12backwardPassPfS_S_S_S_i
	.globl	_Z12backwardPassPfS_S_S_S_i
	.p2align	8
	.type	_Z12backwardPassPfS_S_S_S_i,@function
_Z12backwardPassPfS_S_S_S_i:            ; @_Z12backwardPassPfS_S_S_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x100, v1
	s_cbranch_execz .LBB1_4
; %bb.1:                                ; %.preheader
	s_clause 0x3
	s_load_b32 s8, s[0:1], 0x28
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s8, s8, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add3_u32 v2, v1, s8, 0x10000
	s_mov_b64 s[8:9], 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_u32 s10, s2, s8
	s_addc_u32 s11, s3, s9
	s_add_u32 s8, s8, 4
	s_load_b32 s10, s[10:11], 0x0
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_nc_u32_e32 v2, 0x100, v2
	s_addc_u32 s9, s9, 0
	s_cmpk_eq_i32 s8, 0x400
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s10, v3
	s_cbranch_scc0 .LBB1_2
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v3
	v_sub_f32_e32 v3, 1.0, v3
	v_mul_f32_e32 v3, v0, v3
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB1_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12backwardPassPfS_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12backwardPassPfS_S_S_S_i, .Lfunc_end1-_Z12backwardPassPfS_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13updateWeightsPfS_S_S_i ; -- Begin function _Z13updateWeightsPfS_S_S_i
	.globl	_Z13updateWeightsPfS_S_S_i
	.p2align	8
	.type	_Z13updateWeightsPfS_S_S_i,@function
_Z13updateWeightsPfS_S_S_i:             ; @_Z13updateWeightsPfS_S_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x100, v1
	s_cbranch_execz .LBB2_4
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s8, 16
	v_add_co_u32 v2, vcc_lo, s6, v5
	v_lshl_add_u32 v3, v1, 8, s9
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v8, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v6, vcc_lo, v0, s0
	s_add_u32 s6, s4, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v4, vcc_lo
	s_addc_u32 s7, s5, s1
	global_load_b32 v8, v5, s[6:7]
	global_load_b32 v9, v[2:3], off
	global_load_b32 v10, v[6:7], off
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x400
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v8, 0xbc23d70a, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v10, v8, v9
	global_store_b32 v[6:7], v10, off
	s_cbranch_scc0 .LBB2_2
; %bb.3:
	v_lshl_add_u32 v0, s8, 8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmamk_f32 v2, v2, 0xbc23d70a, v3
	global_store_b32 v[0:1], v2, off
.LBB2_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13updateWeightsPfS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13updateWeightsPfS_S_S_i, .Lfunc_end2-_Z13updateWeightsPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11forwardPassPfS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11forwardPassPfS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12backwardPassPfS_S_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12backwardPassPfS_S_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13updateWeightsPfS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13updateWeightsPfS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
