#include <iostream>
#include <cuda_runtime.h>
#include <cooperative_groups.h>

using namespace cooperative_groups;

// Constants for the grid size and block size
#define GRID_SIZE 64
#define BLOCK_SIZE 16

// Kernel to simulate cloth physics using atomics and cooperative groups
__global__ void clothSimulationKernel(float* positions, float* velocities, float* forces, float dt, float damping) {
    // Create a cooperative group for the entire block
    grid_group grid = this_grid();

    // Calculate the global index for the thread
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int index = idy * GRID_SIZE + idx;

    // Check if the thread is within the bounds of the grid
    if (idx < GRID_SIZE && idy < GRID_SIZE) {
        // Apply forces and update velocities and positions
        atomicAdd(&velocities[index], forces[index] * dt);
        velocities[index] *= damping; // Apply damping
        positions[index] += velocities[index] * dt;

        // Synchronize within the grid group
        grid.sync();

        // Simple boundary condition (reflective)
        if (positions[index] < 0.0f || positions[index] > 1.0f) {
            velocities[index] = -velocities[index];
        }
    }
}

int main() {
    // Allocate memory for positions, velocities, and forces
    float* d_positions, *d_velocities, *d_forces;
    cudaMalloc((void**)&d_positions, GRID_SIZE * GRID_SIZE * sizeof(float));
    cudaMalloc((void**)&d_velocities, GRID_SIZE * GRID_SIZE * sizeof(float));
    cudaMalloc((void**)&d_forces, GRID_SIZE * GRID_SIZE * sizeof(float));

    // Initialize positions, velocities, and forces on the host
    float* h_positions = new float[GRID_SIZE * GRID_SIZE];
    float* h_velocities = new float[GRID_SIZE * GRID_SIZE];
    float* h_forces = new float[GRID_SIZE * GRID_SIZE];
    for (int i = 0; i < GRID_SIZE * GRID_SIZE; ++i) {
        h_positions[i] = 0.5f; // Initial position in the middle
        h_velocities[i] = 0.0f; // No initial velocity
        h_forces[i] = 0.0f; // No initial force
    }

    // Copy data from host to device
    cudaMemcpy(d_positions, h_positions, GRID_SIZE * GRID_SIZE * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_velocities, h_velocities, GRID_SIZE * GRID_SIZE * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_forces, h_forces, GRID_SIZE * GRID_SIZE * sizeof(float), cudaMemcpyHostToDevice);

    // Simulation parameters
    float dt = 0.01f; // Time step
    float damping = 0.99f; // Damping factor

    // Launch the kernel
    dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
    dim3 gridSize(GRID_SIZE / BLOCK_SIZE, GRID_SIZE / BLOCK_SIZE);
    clothSimulationKernel<<<gridSize, blockSize>>>(d_positions, d_velocities, d_forces, dt, damping);

    // Check for errors in the kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    cudaMemcpy(h_positions, d_positions, GRID_SIZE * GRID_SIZE * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_velocities, d_velocities, GRID_SIZE * GRID_SIZE * sizeof(float), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_positions);
    cudaFree(d_velocities);
    cudaFree(d_forces);

    // Free host memory
    delete[] h_positions;
    delete[] h_velocities;
    delete[] h_forces;

    return 0;
}
	.file	"tmpxft_0004dfd0_00000000-6_cuda_code_037500.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6835:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE6835:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
	.type	_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff, @function
_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff:
.LFB6857:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movss	%xmm0, 4(%rsp)
	movss	%xmm1, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21clothSimulationKernelPfS_S_ff(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6857:
	.size	_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff, .-_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
	.globl	_Z21clothSimulationKernelPfS_S_ff
	.type	_Z21clothSimulationKernelPfS_S_ff, @function
_Z21clothSimulationKernelPfS_S_ff:
.LFB6858:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
	.cfi_endproc
.LFE6858:
	.size	_Z21clothSimulationKernelPfS_S_ff, .-_Z21clothSimulationKernelPfS_S_ff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB6832:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$16384, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	movl	$16384, %esi
	leaq	24(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$16384, %edi
	call	_Znam@PLT
	movl	$16384, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$16384, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movss	.LC0(%rip), %xmm0
	xorl	%edx, %edx
	movq	%rax, %rbp
.L9:
	movss	%xmm0, (%r12,%rdx,4)
	incq	%rdx
	cmpq	$4096, %rdx
	jne	.L9
	xorl	%eax, %eax
	movq	%rdx, %rcx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	rep stosl
	movq	%rdx, %rcx
	movq	%rbp, %rdi
	movl	$16384, %edx
	rep stosl
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movabsq	$17179869188, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movss	.LC1(%rip), %xmm1
	movss	.LC2(%rip), %xmm0
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
.L10:
	call	cudaGetLastError@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	je	.L11
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L11:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$16384, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L8:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6832:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z21clothSimulationKernelPfS_S_ff"
.LC5:
	.string	"_ZN50_INTERNAL_45e63b91_19_cuda_code_037500_cu_3d48ed904cuda3std3__419piecewise_constructE"
.LC6:
	.string	"_ZN50_INTERNAL_45e63b91_19_cuda_code_037500_cu_3d48ed904cuda3std6ranges3__45__cpo4swapE"
.LC7:
	.string	"_ZN50_INTERNAL_45e63b91_19_cuda_code_037500_cu_3d48ed904cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6860:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21clothSimulationKernelPfS_S_ff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE6860:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1056964608
	.align 4
.LC1:
	.long	1065185444
	.align 4
.LC2:
	.long	1008981770
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>

using namespace cooperative_groups;

// Constants for the grid size and block size
#define GRID_SIZE 64
#define BLOCK_SIZE 16

// Kernel to simulate cloth physics using atomics and cooperative groups
__global__ void clothSimulationKernel(float* positions, float* velocities, float* forces, float dt, float damping) {
    // Create a cooperative group for the entire block
    grid_group grid = this_grid();

    // Calculate the global index for the thread
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int index = idy * GRID_SIZE + idx;

    // Check if the thread is within the bounds of the grid
    if (idx < GRID_SIZE && idy < GRID_SIZE) {
        // Apply forces and update velocities and positions
        atomicAdd(&velocities[index], forces[index] * dt);
        velocities[index] *= damping; // Apply damping
        positions[index] += velocities[index] * dt;

        // Synchronize within the grid group
        grid.sync();

        // Simple boundary condition (reflective)
        if (positions[index] < 0.0f || positions[index] > 1.0f) {
            velocities[index] = -velocities[index];
        }
    }
}

int main() {
    // Allocate memory for positions, velocities, and forces
    float* d_positions, *d_velocities, *d_forces;
    hipMalloc((void**)&d_positions, GRID_SIZE * GRID_SIZE * sizeof(float));
    hipMalloc((void**)&d_velocities, GRID_SIZE * GRID_SIZE * sizeof(float));
    hipMalloc((void**)&d_forces, GRID_SIZE * GRID_SIZE * sizeof(float));

    // Initialize positions, velocities, and forces on the host
    float* h_positions = new float[GRID_SIZE * GRID_SIZE];
    float* h_velocities = new float[GRID_SIZE * GRID_SIZE];
    float* h_forces = new float[GRID_SIZE * GRID_SIZE];
    for (int i = 0; i < GRID_SIZE * GRID_SIZE; ++i) {
        h_positions[i] = 0.5f; // Initial position in the middle
        h_velocities[i] = 0.0f; // No initial velocity
        h_forces[i] = 0.0f; // No initial force
    }

    // Copy data from host to device
    hipMemcpy(d_positions, h_positions, GRID_SIZE * GRID_SIZE * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_velocities, h_velocities, GRID_SIZE * GRID_SIZE * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_forces, h_forces, GRID_SIZE * GRID_SIZE * sizeof(float), hipMemcpyHostToDevice);

    // Simulation parameters
    float dt = 0.01f; // Time step
    float damping = 0.99f; // Damping factor

    // Launch the kernel
    dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
    dim3 gridSize(GRID_SIZE / BLOCK_SIZE, GRID_SIZE / BLOCK_SIZE);
    clothSimulationKernel<<<gridSize, blockSize>>>(d_positions, d_velocities, d_forces, dt, damping);

    // Check for errors in the kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    hipMemcpy(h_positions, d_positions, GRID_SIZE * GRID_SIZE * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_velocities, d_velocities, GRID_SIZE * GRID_SIZE * sizeof(float), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_positions);
    hipFree(d_velocities);
    hipFree(d_forces);

    // Free host memory
    delete[] h_positions;
    delete[] h_velocities;
    delete[] h_forces;

    return 0;
}
	.text
	.file	"cuda_code_037500.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z36__device_stub__clothSimulationKernelPfS_S_ff # -- Begin function _Z36__device_stub__clothSimulationKernelPfS_S_ff
	.type	_Z36__device_stub__clothSimulationKernelPfS_S_ff,@function
_Z36__device_stub__clothSimulationKernelPfS_S_ff: # @_Z36__device_stub__clothSimulationKernelPfS_S_ff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movss	%xmm0, (%rdx)
	movq	%rsp, %rdi
	movss	%xmm1, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rdi, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21clothSimulationKernelPfS_S_ff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__clothSimulationKernelPfS_S_ff, .Lfunc_end0-_Z36__device_stub__clothSimulationKernelPfS_S_ff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3c23d70a                      # float 0.00999999977
.LCPI1_1:
	.long	0x3f7d70a4                      # float 0.990000009
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	16(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znam
	movq	%rax, %rbx
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znam
	movq	%rax, %r14
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znam
	movq	%rax, %r15
	xorl	%r12d, %r12d
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1056964608, (%rbx,%r12,4)      # imm = 0x3F000000
	incq	%r12
	cmpq	$4096, %r12                     # imm = 0x1000
	jne	.LBB1_1
# %bb.2:
	movq	16(%rsp), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$17179869188, %rdi              # imm = 0x400000004
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdx
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	callq	_Z36__device_stub__clothSimulationKernelPfS_S_ff
.LBB1_4:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_9
# %bb.5:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_6
# %bb.7:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_8
.LBB1_9:
	movq	16(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_10
.LBB1_6:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_10:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21clothSimulationKernelPfS_S_ff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21clothSimulationKernelPfS_S_ff,@object # @_Z21clothSimulationKernelPfS_S_ff
	.section	.rodata,"a",@progbits
	.globl	_Z21clothSimulationKernelPfS_S_ff
	.p2align	3, 0x0
_Z21clothSimulationKernelPfS_S_ff:
	.quad	_Z36__device_stub__clothSimulationKernelPfS_S_ff
	.size	_Z21clothSimulationKernelPfS_S_ff, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21clothSimulationKernelPfS_S_ff"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__clothSimulationKernelPfS_S_ff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21clothSimulationKernelPfS_S_ff
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21clothSimulationKernelPfS_S_ff ; -- Begin function _Z21clothSimulationKernelPfS_S_ff
	.globl	_Z21clothSimulationKernelPfS_S_ff
	.p2align	8
	.type	_Z21clothSimulationKernelPfS_S_ff,@function
_Z21clothSimulationKernelPfS_S_ff:      ; @_Z21clothSimulationKernelPfS_S_ff
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_add_u32 s8, s0, 32
	s_addc_u32 s9, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s14, s2, v[5:6]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[6:7]
	s_mov_b32 s2, exec_lo
	v_max_i32_e32 v3, v2, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 64, v3
	s_cbranch_execz .LBB0_15
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_lshl_add_u32 v1, v2, 6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v4, vcc_lo
	s_mov_b32 s2, 0
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[1:2], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v9, s6, v7
.LBB0_2:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v7, v8, v9
	global_atomic_cmpswap_b32 v7, v[1:2], v[7:8], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v7, v8
	v_mov_b32_e32 v8, v7
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %atomicrmw.end
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v7, v[1:2], off
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_bfe_u32 v0, v0, 20, 10
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v0, v6, v0, v5
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, s7, v7
	global_store_b32 v[1:2], v7, off
	global_load_b32 v8, v[3:4], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, s6, v7
	global_store_b32 v[3:4], v8, off
	s_waitcnt_vscnt null, 0x0
	buffer_gl1_inv
	buffer_gl0_inv
	s_barrier
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_13
; %bb.4:
	s_load_b64 s[0:1], s[8:9], 0x58
	v_mov_b32_e32 v6, 0
	s_mov_b32 s3, exec_lo
	s_mov_b32 s4, exec_lo
	v_mbcnt_lo_u32_b32 v5, s3, 0
                                        ; implicit-def: $vgpr7
	s_waitcnt lgkmcnt(0)
	global_load_b32 v0, v6, s[0:1] offset:40
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_bcnt1_i32_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v7, s3
	global_atomic_add_u32 v7, v6, v7, s[0:1] offset:32 glc
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s3, v7
	v_add_nc_u32_e32 v7, -1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s3, v5
	s_mov_b32 s3, exec_lo
	v_and_b32_e32 v6, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e64 v6, v7
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_10
; %bb.7:                                ; %.preheader.i.i.i.preheader
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, 0
.LBB0_8:                                ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_load_b32 v6, v0, s[0:1] offset:32 glc
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_u32_e32 vcc_lo, 0xffff, v6
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_8
; %bb.9:                                ; %Flow52
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr0
.LBB0_10:                               ; %Flow54
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_13
; %bb.11:
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v5, s3, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_and_b32 s4, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s4
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_sub_nc_u32_e32 v0, 0x10000, v0
	s_bcnt1_i32_b32 s3, s3
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s3
	global_atomic_add_u32 v5, v0, s[0:1] offset:32
.LBB0_13:                               ; %Flow56
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	v_cmp_lt_f32_e64 s0, 1.0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_15
; %bb.14:
	global_load_b32 v0, v[1:2], off
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v0, 0x80000000, v0
	global_store_b32 v[1:2], v0, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21clothSimulationKernelPfS_S_ff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21clothSimulationKernelPfS_S_ff, .Lfunc_end0-_Z21clothSimulationKernelPfS_S_ff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 700
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         120
        .size:           8
        .value_kind:     hidden_multigrid_sync_arg
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21clothSimulationKernelPfS_S_ff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21clothSimulationKernelPfS_S_ff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
