#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>

#define POPULATION_SIZE 256
#define GENES_PER_INDIVIDUAL 32
#define NUM_GENERATIONS 100

__global__ void geneticAlgorithmKernel(curandState *states, float *population, float *fitness, float *newPopulation) {
    int idx = threadIdx.x + blockIdx.x * blockDim.x;

    // Initialize random number generator for each thread
    if (idx < POPULATION_SIZE) {
        curand_init((unsigned long long) clock() + idx, 0, 0, &states[idx]);
    }

    __shared__ float sharedPopulation[POPULATION_SIZE * GENES_PER_INDIVIDUAL];
    __shared__ float sharedFitness[POPULATION_SIZE];

    // Load population into shared memory
    for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
        if (idx < POPULATION_SIZE) {
            sharedPopulation[idx * GENES_PER_INDIVIDUAL + i] = population[idx * GENES_PER_INDIVIDUAL + i];
        }
    }
    __syncthreads();

    // Evaluate fitness
    if (idx < POPULATION_SIZE) {
        float sum = 0.0f;
        for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
            sum += sharedPopulation[idx * GENES_PER_INDIVIDUAL + i];
        }
        sharedFitness[idx] = sum; // Simple fitness function
    }
    __syncthreads();

    // Selection and crossover
    if (idx < POPULATION_SIZE) {
        int parent1 = curand(&states[idx]) % POPULATION_SIZE;
        int parent2 = curand(&states[idx]) % POPULATION_SIZE;
        int crossoverPoint = curand(&states[idx]) % GENES_PER_INDIVIDUAL;

        for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
            if (i < crossoverPoint) {
                newPopulation[idx * GENES_PER_INDIVIDUAL + i] = sharedPopulation[parent1 * GENES_PER_INDIVIDUAL + i];
            } else {
                newPopulation[idx * GENES_PER_INDIVIDUAL + i] = sharedPopulation[parent2 * GENES_PER_INDIVIDUAL + i];
            }
        }
    }
    __syncthreads();

    // Mutation
    if (idx < POPULATION_SIZE) {
        for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
            if (curand(&states[idx]) < 0.01f) { // Mutation rate
                newPopulation[idx * GENES_PER_INDIVIDUAL + i] = curand_uniform(&states[idx]);
            }
        }
    }
}

int main() {
    curandState *devStates;
    float *devPopulation, *devFitness, *devNewPopulation;

    // Allocate memory for population, fitness, and new population
    cudaMalloc((void**)&devStates, POPULATION_SIZE * sizeof(curandState));
    cudaMalloc((void**)&devPopulation, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float));
    cudaMalloc((void**)&devFitness, POPULATION_SIZE * sizeof(float));
    cudaMalloc((void**)&devNewPopulation, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float));

    // Initialize population with random values
    curandState *devStatesHost = new curandState[POPULATION_SIZE];
    float *devPopulationHost = new float[POPULATION_SIZE * GENES_PER_INDIVIDUAL];
    for (int i = 0; i < POPULATION_SIZE; ++i) {
        for (int j = 0; j < GENES_PER_INDIVIDUAL; ++j) {
            devPopulationHost[i * GENES_PER_INDIVIDUAL + j] = static_cast<float>(rand()) / RAND_MAX;
        }
    }
    cudaMemcpy(devPopulation, devPopulationHost, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float), cudaMemcpyHostToDevice);

    // Kernel launch configuration
    dim3 threadsPerBlock(POPULATION_SIZE);
    dim3 numBlocks(1);

    // Run genetic algorithm for a number of generations
    for (int generation = 0; generation < NUM_GENERATIONS; ++generation) {
        geneticAlgorithmKernel<<<numBlocks, threadsPerBlock>>>(devStates, devPopulation, devFitness, devNewPopulation);
        cudaDeviceSynchronize();

        // Swap population pointers for the next generation
        float *temp = devPopulation;
        devPopulation = devNewPopulation;
        devNewPopulation = temp;

        // Check for errors
        cudaError_t err = cudaGetLastError();
        if (err != cudaSuccess) {
            std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
            return -1;
        }
    }

    // Copy final population back to host
    cudaMemcpy(devPopulationHost, devPopulation, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float), cudaMemcpyDeviceToHost);

    // Output the best individual (simplest fitness: highest sum of genes)
    float bestFitness = -1.0f;
    int bestIndex = -1;
    for (int i = 0; i < POPULATION_SIZE; ++i) {
        float sum = 0.0f;
        for (int j = 0; j < GENES_PER_INDIVIDUAL; ++j) {
            sum += devPopulationHost[i * GENES_PER_INDIVIDUAL + j];
        }
        if (sum > bestFitness) {
            bestFitness = sum;
            bestIndex = i;
        }
    }
    std::cout << "Best individual: ";
    for (int j = 0; j < GENES_PER_INDIVIDUAL; ++j) {
        std::cout << devPopulationHost[bestIndex * GENES_PER_INDIVIDUAL + j] << " ";
    }
    std::cout << "with fitness: " << bestFitness << std::endl;

    // Free allocated memory
    delete[] devStatesHost;
    delete[] devPopulationHost;
    cudaFree(devStates);
    cudaFree(devPopulation);
    cudaFree(devFitness);
    cudaFree(devNewPopulation);

    return 0;
}
	.file	"tmpxft_001242a7_00000000-6_cuda_code_009076.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3852:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3852:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z68__device_stub__Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_P17curandStateXORWOWPfS1_S1_
	.type	_Z68__device_stub__Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_P17curandStateXORWOWPfS1_S1_, @function
_Z68__device_stub__Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_P17curandStateXORWOWPfS1_S1_:
.LFB3874:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3874:
	.size	_Z68__device_stub__Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_P17curandStateXORWOWPfS1_S1_, .-_Z68__device_stub__Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_P17curandStateXORWOWPfS1_S1_
	.globl	_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_
	.type	_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_, @function
_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_:
.LFB3875:
	.cfi_startproc
	endbr64
	jmp	_Z68__device_stub__Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_P17curandStateXORWOWPfS1_S1_
	.cfi_endproc
.LFE3875:
	.size	_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_, .-_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"CUDA error: "
.LC4:
	.string	"Best individual: "
.LC5:
	.string	" "
.LC6:
	.string	"with fitness: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$12288, %esi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	movl	$32768, %edi
	call	_Znam@PLT
	movq	%rax, %rbp
.L9:
	movq	%r13, %r14
	movq	%rbp, %r12
	xorl	%ebx, %ebx
	salq	$7, %r14
	addq	%rbp, %r14
.L10:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC2(%rip), %xmm0
	movss	%xmm0, (%r14,%rbx,4)
	incq	%rbx
	cmpq	$32, %rbx
	jne	.L10
	incq	%r13
	cmpq	$256, %r13
	jne	.L9
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$32768, %edx
	movq	%rbp, %rsi
	movl	$100, %r13d
	call	cudaMemcpy@PLT
	movl	$16777217, %eax
	movl	$1, 56(%rsp)
	salq	$8, %rax
	movl	$1, 68(%rsp)
	movq	%rax, 48(%rsp)
	subq	$255, %rax
	movq	%rax, 60(%rsp)
.L15:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z68__device_stub__Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_P17curandStateXORWOWPfS1_S1_
.L12:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rax
	movq	40(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	%rdx, 24(%rsp)
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L13
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L13:
	decl	%r13d
	jne	.L15
	movq	24(%rsp), %rsi
	movl	$32768, %edx
	movq	%rbp, %rdi
	orl	$-1, %ebx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movss	.LC1(%rip), %xmm1
	xorl	%edx, %edx
	movss	%xmm1, 12(%rsp)
.L16:
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L17:
	addss	(%r12,%rax,4), %xmm0
	incq	%rax
	cmpq	$32, %rax
	jne	.L17
	comiss	12(%rsp), %xmm0
	maxss	12(%rsp), %xmm0
	cmova	%edx, %ebx
	incl	%edx
	movss	%xmm0, 12(%rsp)
	subq	$-128, %r12
	cmpl	$256, %edx
	jne	.L16
	leaq	_ZSt4cout(%rip), %r12
	movslq	%ebx, %rbx
	leaq	.LC4(%rip), %rsi
	xorl	%r13d, %r13d
	movq	%r12, %rdi
	salq	$7, %rbx
	leaq	.LC5(%rip), %r14
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	addq	%rbp, %rbx
.L20:
	movq	%r12, %rdi
	cvtss2sd	(%rbx,%r13,4), %xmm0
	incq	%r13
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r14, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	$32, %r13
	jne	.L20
	leaq	.LC6(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	12(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L8:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_"
.LC8:
	.string	"precalc_xorwow_matrix"
.LC9:
	.string	"precalc_xorwow_offset_matrix"
.LC10:
	.string	"mrg32k3aM1"
.LC11:
	.string	"mrg32k3aM2"
.LC12:
	.string	"mrg32k3aM1SubSeq"
.LC13:
	.string	"mrg32k3aM2SubSeq"
.LC14:
	.string	"mrg32k3aM1Seq"
.LC15:
	.string	"mrg32k3aM2Seq"
.LC16:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3877:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22geneticAlgorithmKernelP17curandStateXORWOWPfS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3877:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	-1082130432
	.align 4
.LC2:
	.long	805306368
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

#define POPULATION_SIZE 256
#define GENES_PER_INDIVIDUAL 32
#define NUM_GENERATIONS 100

__global__ void geneticAlgorithmKernel(hiprandState *states, float *population, float *fitness, float *newPopulation) {
    int idx = threadIdx.x + blockIdx.x * blockDim.x;

    // Initialize random number generator for each thread
    if (idx < POPULATION_SIZE) {
        hiprand_init((unsigned long long) clock() + idx, 0, 0, &states[idx]);
    }

    __shared__ float sharedPopulation[POPULATION_SIZE * GENES_PER_INDIVIDUAL];
    __shared__ float sharedFitness[POPULATION_SIZE];

    // Load population into shared memory
    for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
        if (idx < POPULATION_SIZE) {
            sharedPopulation[idx * GENES_PER_INDIVIDUAL + i] = population[idx * GENES_PER_INDIVIDUAL + i];
        }
    }
    __syncthreads();

    // Evaluate fitness
    if (idx < POPULATION_SIZE) {
        float sum = 0.0f;
        for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
            sum += sharedPopulation[idx * GENES_PER_INDIVIDUAL + i];
        }
        sharedFitness[idx] = sum; // Simple fitness function
    }
    __syncthreads();

    // Selection and crossover
    if (idx < POPULATION_SIZE) {
        int parent1 = hiprand(&states[idx]) % POPULATION_SIZE;
        int parent2 = hiprand(&states[idx]) % POPULATION_SIZE;
        int crossoverPoint = hiprand(&states[idx]) % GENES_PER_INDIVIDUAL;

        for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
            if (i < crossoverPoint) {
                newPopulation[idx * GENES_PER_INDIVIDUAL + i] = sharedPopulation[parent1 * GENES_PER_INDIVIDUAL + i];
            } else {
                newPopulation[idx * GENES_PER_INDIVIDUAL + i] = sharedPopulation[parent2 * GENES_PER_INDIVIDUAL + i];
            }
        }
    }
    __syncthreads();

    // Mutation
    if (idx < POPULATION_SIZE) {
        for (int i = 0; i < GENES_PER_INDIVIDUAL; ++i) {
            if (hiprand(&states[idx]) < 0.01f) { // Mutation rate
                newPopulation[idx * GENES_PER_INDIVIDUAL + i] = hiprand_uniform(&states[idx]);
            }
        }
    }
}

int main() {
    hiprandState *devStates;
    float *devPopulation, *devFitness, *devNewPopulation;

    // Allocate memory for population, fitness, and new population
    hipMalloc((void**)&devStates, POPULATION_SIZE * sizeof(hiprandState));
    hipMalloc((void**)&devPopulation, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float));
    hipMalloc((void**)&devFitness, POPULATION_SIZE * sizeof(float));
    hipMalloc((void**)&devNewPopulation, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float));

    // Initialize population with random values
    hiprandState *devStatesHost = new hiprandState[POPULATION_SIZE];
    float *devPopulationHost = new float[POPULATION_SIZE * GENES_PER_INDIVIDUAL];
    for (int i = 0; i < POPULATION_SIZE; ++i) {
        for (int j = 0; j < GENES_PER_INDIVIDUAL; ++j) {
            devPopulationHost[i * GENES_PER_INDIVIDUAL + j] = static_cast<float>(rand()) / RAND_MAX;
        }
    }
    hipMemcpy(devPopulation, devPopulationHost, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float), hipMemcpyHostToDevice);

    // Kernel launch configuration
    dim3 threadsPerBlock(POPULATION_SIZE);
    dim3 numBlocks(1);

    // Run genetic algorithm for a number of generations
    for (int generation = 0; generation < NUM_GENERATIONS; ++generation) {
        geneticAlgorithmKernel<<<numBlocks, threadsPerBlock>>>(devStates, devPopulation, devFitness, devNewPopulation);
        hipDeviceSynchronize();

        // Swap population pointers for the next generation
        float *temp = devPopulation;
        devPopulation = devNewPopulation;
        devNewPopulation = temp;

        // Check for errors
        hipError_t err = hipGetLastError();
        if (err != hipSuccess) {
            std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
            return -1;
        }
    }

    // Copy final population back to host
    hipMemcpy(devPopulationHost, devPopulation, POPULATION_SIZE * GENES_PER_INDIVIDUAL * sizeof(float), hipMemcpyDeviceToHost);

    // Output the best individual (simplest fitness: highest sum of genes)
    float bestFitness = -1.0f;
    int bestIndex = -1;
    for (int i = 0; i < POPULATION_SIZE; ++i) {
        float sum = 0.0f;
        for (int j = 0; j < GENES_PER_INDIVIDUAL; ++j) {
            sum += devPopulationHost[i * GENES_PER_INDIVIDUAL + j];
        }
        if (sum > bestFitness) {
            bestFitness = sum;
            bestIndex = i;
        }
    }
    std::cout << "Best individual: ";
    for (int j = 0; j < GENES_PER_INDIVIDUAL; ++j) {
        std::cout << devPopulationHost[bestIndex * GENES_PER_INDIVIDUAL + j] << " ";
    }
    std::cout << "with fitness: " << bestFitness << std::endl;

    // Free allocated memory
    delete[] devStatesHost;
    delete[] devPopulationHost;
    hipFree(devStates);
    hipFree(devPopulation);
    hipFree(devFitness);
    hipFree(devNewPopulation);

    return 0;
}
	.text
	.file	"cuda_code_009076.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_ # -- Begin function _Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.type	_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_,@function
_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_: # @_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_, .Lfunc_end0-_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI1_1:
	.long	0xbf800000                      # float -1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	40(%rsp), %rdi
	movl	$12288, %esi                    # imm = 0x3000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$1024, %esi                     # imm = 0x400
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	callq	hipMalloc
	movl	$32768, %edi                    # imm = 0x8000
	callq	_Znam
	movq	%rax, %rbx
	xorl	%r14d, %r14d
	movq	%rax, %r15
.LBB1_1:                                # %.preheader68
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%r12d, %r12d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movss	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	%xmm1, %xmm0
	movss	%xmm0, (%r15,%r12,4)
	incq	%r12
	cmpq	$32, %r12
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r14
	subq	$-128, %r15
	cmpq	$256, %r14                      # imm = 0x100
	jne	.LBB1_1
# %bb.4:
	movabsq	$4294967297, %r14               # imm = 0x100000001
	movq	8(%rsp), %rdi
	movl	$32768, %edx                    # imm = 0x8000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$100, %r12d
	leaq	255(%r14), %r15
.LBB1_6:                                # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:                                #   in Loop: Header=BB1_6 Depth=1
	movq	40(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	16(%rsp), %rcx
	callq	_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_
.LBB1_8:                                #   in Loop: Header=BB1_6 Depth=1
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rax
	movq	16(%rsp), %rcx
	movq	%rcx, 8(%rsp)
	movq	%rax, 16(%rsp)
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.5:                                #   in Loop: Header=BB1_6 Depth=1
	decl	%r12d
	jne	.LBB1_6
# %bb.13:
	movq	8(%rsp), %rsi
	movl	$32768, %edx                    # imm = 0x8000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	.LCPI1_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$-1, %ebp
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB1_14:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_15 Depth 2
	xorps	%xmm1, %xmm1
	xorl	%edx, %edx
.LBB1_15:                               #   Parent Loop BB1_14 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	addss	(%rcx,%rdx,4), %xmm1
	incq	%rdx
	cmpq	$32, %rdx
	jne	.LBB1_15
# %bb.16:                               #   in Loop: Header=BB1_14 Depth=1
	ucomiss	%xmm0, %xmm1
	maxss	%xmm0, %xmm1
	cmoval	%eax, %ebp
	incq	%rax
	subq	$-128, %rcx
	movaps	%xmm1, %xmm0
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB1_14
# %bb.17:
	movss	%xmm1, 28(%rsp)                 # 4-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$17, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	shll	$5, %ebp
	movslq	%ebp, %rax
	leaq	(%rbx,%rax,4), %r14
	xorl	%r15d, %r15d
.LBB1_18:                               # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r15,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.2, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	$32, %r15
	jne	.LBB1_18
# %bb.19:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	28(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB1_20
.LBB1_9:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_10
# %bb.11:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_12
.LBB1_10:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12:
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_20:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_,@object # @_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.p2align	3, 0x0
_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_:
	.quad	_Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.size	_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Best individual: "
	.size	.L.str.1, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" "
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"with fitness: "
	.size	.L.str.3, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_"
	.size	.L__unnamed_1, 50

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_ ; -- Begin function _Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.globl	_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
	.p2align	8
	.type	_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_,@function
_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_: ; @_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, 0x100, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_ashrrev_i32_e32 v0, 31, v1
	s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	v_mad_i64_i32 v[9:10], null, v1, 48, s[4:5]
	v_add_co_u32 v2, s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v0, s2, 0, v0, s2
	v_xor_b32_e32 v2, 0x2c7f967f, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, 0xa03697cb, v0
	v_mul_lo_u32 v11, 0x493c4aa1, v2
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, 0x7b99840d, v0
	v_add_nc_u32_e32 v2, 0x75bcd15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v8, v7
	v_add3_u32 v6, v11, v0, 0x64f0c9
	v_xor_b32_e32 v3, 0x159a55e5, v11
	v_add_nc_u32_e32 v4, 0x1f123bb5, v0
	v_xor_b32_e32 v5, 0x5491333, v0
	v_add_nc_u32_e32 v0, 0x583f19, v11
	s_clause 0x2
	global_store_b96 v[9:10], v[6:8], off
	global_store_b128 v[9:10], v[2:5], off offset:24
	global_store_b32 v[9:10], v0, off offset:40
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b32_e32 v2, 5, v1
	v_lshlrev_b32_e32 v0, 7, v1
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s2, s6, v4
	v_add_co_ci_u32_e64 v3, s2, s7, v5, s2
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v6, v[2:3], off
	v_add_nc_u32_e32 v7, s3, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v6
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v2, s2, v2, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v3, s2, 0, v3, s2
	s_add_i32 s3, s3, 4
	s_cmpk_eq_i32 s3, 0x80
	s_cbranch_scc0 .LBB0_3
; %bb.6:                                ; %.loopexit61
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.7:
	v_mad_i64_i32 v[13:14], null, v1, 48, s[4:5]
	s_mov_b32 s6, 0
	s_mov_b32 s7, 0
	s_clause 0x2
	global_load_b128 v[6:9], v[13:14], off offset:24
	global_load_b32 v10, v[13:14], off offset:40
	global_load_b32 v2, v[13:14], off
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v0, 2, v6
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v3, 4, v10
	v_lshrrev_b32_e32 v11, 2, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v6
	v_lshlrev_b32_e32 v6, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v6, v3
	v_xor_b32_e32 v6, v11, v7
	v_lshrrev_b32_e32 v7, 2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v11, v3, v0, v10
	v_lshlrev_b32_e32 v0, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 4, v11
	v_xor_b32_e32 v0, v0, v3
	v_xor_b32_e32 v3, v7, v8
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, 0x10974f, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v12, v0, v6, v11
	v_lshlrev_b32_e32 v0, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, 4, v12
	v_xor_b32_e32 v0, v0, v6
	v_add3_u32 v6, v2, v12, 0x8a
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor3_b32 v3, v0, v3, v12
	v_add3_u32 v0, v2, v11, 0xc5
	v_add_co_u32 v2, s0, s2, v4
	v_add_nc_u32_e32 v7, v3, v8
	global_store_b32 v[13:14], v3, off offset:40
	v_add_co_ci_u32_e64 v3, s0, s3, v5, s0
	s_clause 0x1
	global_store_b128 v[13:14], v[9:12], off offset:24
	global_store_b32 v[13:14], v8, off
	v_and_b32_e32 v7, 31, v7
.LBB0_8:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, s7, v7
	s_add_i32 s7, s7, 1
	v_cndmask_b32_e64 v8, v6, v0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, 0xff, v8
	v_lshl_add_u32 v8, v8, 7, s6
	s_add_i32 s6, s6, 4
	s_cmp_lg_u32 s7, 32
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[2:3], v8, off
	v_add_co_u32 v2, s0, v2, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_cbranch_scc1 .LBB0_8
.LBB0_9:                                ; %Flow140
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_16
; %bb.10:                               ; %.preheader
	v_mad_i64_i32 v[7:8], null, v1, 48, s[4:5]
	v_add_co_u32 v9, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v5, vcc_lo
	s_mov_b64 s[0:1], 0
	s_clause 0x2
	global_load_b32 v11, v[7:8], off offset:40
	global_load_b128 v[0:3], v[7:8], off offset:24
	global_load_b32 v14, v[7:8], off
.LBB0_11:                               ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v4, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v6, v11
	v_xor_b32_e32 v0, v4, v0
	v_lshlrev_b32_e32 v4, 4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v5, 1, v0
	v_xor_b32_e32 v4, v5, v4
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor3_b32 v0, v4, v0, v11
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v13, v0 :: v_dual_add_nc_u32 v12, 0x587c5, v14
	v_sub_nc_u32_e32 v4, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, v12, v4
	v_mov_b32_e32 v4, v2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	v_lshrrev_b32_e32 v4, 2, v1
	v_add_nc_u32_e32 v12, 0xb0f8a, v14
	v_add_co_u32 v14, vcc_lo, v9, s0
	v_add_co_ci_u32_e32 v15, vcc_lo, s1, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v4, v1
	v_lshlrev_b32_e32 v4, 4, v0
	v_dual_mov_b32 v6, v0 :: v_dual_lshlrev_b32 v5, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v5, v4
	v_mov_b32_e32 v5, v11
	v_xor3_b32 v13, v4, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v3 :: v_dual_add_nc_u32 v1, v13, v12
	v_cvt_f32_u32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmaak_f32 v0, 0x2f800000, v1, 0x2f800000 :: v_dual_mov_b32 v1, v2
	global_store_b32 v[14:15], v0, off
.LBB0_13:                               ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmpk_lg_i32 s0, 0x80
	s_cbranch_scc0 .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_11 Depth=1
	v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v4
	v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v3, v6
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v14, v12
	s_branch .LBB0_11
.LBB0_15:                               ; %.loopexit
	v_mov_b32_e32 v3, v1
	s_clause 0x2
	global_store_b32 v[7:8], v13, off offset:40
	global_store_b128 v[7:8], v[3:6], off offset:24
	global_store_b32 v[7:8], v12, off
.LBB0_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
		.amdhsa_group_segment_fixed_size 32768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_, .Lfunc_end0-_Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1120
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 32768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22geneticAlgorithmKernelP12hiprandStatePfS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
