#include <iostream>
#include <cuda_runtime.h>
#include <cooperative_groups.h>
#include <cmath>

namespace cg = cooperative_groups;

#define BLOCK_SIZE 32
#define GRID_SIZE 16

__constant__ float d_alpha;

__global__ void implicitHeatKernel(float* d_u_new, float* d_u_old, int N) {
    extern __shared__ float shared_u[];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;

    if (idx >= N || idy >= N) return;

    int idx_s = threadIdx.x + 1;
    int idy_s = threadIdx.y + 1;

    // Load data into shared memory
    if (idx < N && idy < N) {
        shared_u[idy_s * (BLOCK_SIZE + 2) + idx_s] = d_u_old[idy * N + idx];
        if (threadIdx.x == 0) shared_u[idy_s * (BLOCK_SIZE + 2) + 0] = d_u_old[idy * N + (idx - 1 + N) % N];
        if (threadIdx.x == BLOCK_SIZE - 1) shared_u[idy_s * (BLOCK_SIZE + 2) + BLOCK_SIZE + 1] = d_u_old[idy * N + (idx + 1) % N];
        if (threadIdx.y == 0) shared_u[0 * (BLOCK_SIZE + 2) + idx_s] = d_u_old[((idy - 1 + N) % N) * N + idx];
        if (threadIdx.y == BLOCK_SIZE - 1) shared_u[(BLOCK_SIZE + 1) * (BLOCK_SIZE + 2) + idx_s] = d_u_old[((idy + 1) % N) * N + idx];
    }
    __syncthreads();

    // Solve tridiagonal system for each row using Thomas algorithm
    float a = -d_alpha;
    float b = 1 + 4 * d_alpha;
    float c = -d_alpha;

    float r[BLOCK_SIZE];
    float c_new[BLOCK_SIZE];
    float d_new[BLOCK_SIZE];

    // Forward sweep
    if (threadIdx.y < BLOCK_SIZE) {
        r[threadIdx.y] = shared_u[idy_s * (BLOCK_SIZE + 2) + idx_s];
        c_new[threadIdx.y] = c / b;
        d_new[threadIdx.y] = r[threadIdx.y] / b;

        for (int k = 1; k < BLOCK_SIZE; ++k) {
            float m = 1.0f / (b - a * c_new[k - 1]);
            c_new[k] = c * m;
            d_new[k] = (r[k] - a * d_new[k - 1]) * m;
        }

        // Backward sweep
        d_u_new[idy * N + idx] = d_new[BLOCK_SIZE - 1];
        for (int k = BLOCK_SIZE - 2; k >= 0; --k) {
            d_u_new[idy * N + idx] = d_new[k] - c_new[k] * d_u_new[idy * N + idx];
        }
    }
}

int main() {
    int N = 512;
    float alpha = 0.0001f;
    size_t size = N * N * sizeof(float);

    float* h_u_old = new float[size];
    float* h_u_new = new float[size];

    // Initialize data
    for (int i = 0; i < N * N; ++i) {
        h_u_old[i] = sinf(2 * M_PI * i / (N * N));
    }

    float* d_u_old;
    float* d_u_new;
    cudaMalloc((void**)&d_u_old, size);
    cudaMalloc((void**)&d_u_new, size);

    cudaMemcpy(d_u_old, h_u_old, size, cudaMemcpyHostToDevice);
    cudaMemcpyToSymbol(d_alpha, &alpha, sizeof(float));

    dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
    dim3 gridSize(GRID_SIZE, GRID_SIZE);

    implicitHeatKernel<<<gridSize, blockSize, (BLOCK_SIZE + 2) * (BLOCK_SIZE + 2) * sizeof(float)>>>(d_u_new, d_u_old, N);

    cudaMemcpy(h_u_new, d_u_new, size, cudaMemcpyDeviceToHost);

    // Free resources
    delete[] h_u_old;
    delete[] h_u_new;
    cudaFree(d_u_old);
    cudaFree(d_u_new);

    cudaDeviceReset();
    return 0;
}
	.file	"tmpxft_0007c9f5_00000000-6_cuda_code_050703.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6835:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE6835:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z18implicitHeatKernelPfS_iPfS_i
	.type	_Z41__device_stub__Z18implicitHeatKernelPfS_iPfS_i, @function
_Z41__device_stub__Z18implicitHeatKernelPfS_iPfS_i:
.LFB6857:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18implicitHeatKernelPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6857:
	.size	_Z41__device_stub__Z18implicitHeatKernelPfS_iPfS_i, .-_Z41__device_stub__Z18implicitHeatKernelPfS_iPfS_i
	.globl	_Z18implicitHeatKernelPfS_i
	.type	_Z18implicitHeatKernelPfS_i, @function
_Z18implicitHeatKernelPfS_i:
.LFB6858:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z18implicitHeatKernelPfS_iPfS_i
	.cfi_endproc
.LFE6858:
	.size	_Z18implicitHeatKernelPfS_i, .-_Z18implicitHeatKernelPfS_i
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB6832:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4194304, %edi
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movl	$0x38d1b717, 12(%rsp)
	call	_Znam@PLT
	movl	$4194304, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movq	%rax, %rbp
.L9:
	cvtsi2sdl	%r12d, %xmm0
	mulsd	.LC1(%rip), %xmm0
	mulsd	.LC2(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	call	sinf@PLT
	movss	%xmm0, (%rbx,%r12,4)
	incq	%r12
	cmpq	$262144, %r12
	jne	.L9
	leaq	16(%rsp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	xorl	%ecx, %ecx
	leaq	12(%rsp), %rsi
	movl	$1, %r8d
	movl	$4, %edx
	leaq	_ZL7d_alpha(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	xorl	%r9d, %r9d
	movl	$4624, %r8d
	movabsq	$137438953504, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$512, %edx
	call	_Z41__device_stub__Z18implicitHeatKernelPfS_iPfS_i
.L10:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$1048576, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6832:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"_Z18implicitHeatKernelPfS_i"
.LC4:
	.string	"d_alpha"
.LC5:
	.string	"_ZN50_INTERNAL_1953027d_19_cuda_code_050703_cu_5873ad534cuda3std3__419piecewise_constructE"
.LC6:
	.string	"_ZN50_INTERNAL_1953027d_19_cuda_code_050703_cu_5873ad534cuda3std6ranges3__45__cpo4swapE"
.LC7:
	.string	"_ZN50_INTERNAL_1953027d_19_cuda_code_050703_cu_5873ad534cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6860:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18implicitHeatKernelPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movl	$4, %r9d
	leaq	_ZL7d_alpha(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE6860:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL7d_alpha
	.comm	_ZL7d_alpha,4,4
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	1413754136
	.long	1075388923
	.align 8
.LC2:
	.long	0
	.long	1053818880
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
#include <cmath>

namespace cg = cooperative_groups;

#define BLOCK_SIZE 32
#define GRID_SIZE 16

__constant__ float d_alpha;

__global__ void implicitHeatKernel(float* d_u_new, float* d_u_old, int N) {
    extern __shared__ float shared_u[];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;

    if (idx >= N || idy >= N) return;

    int idx_s = threadIdx.x + 1;
    int idy_s = threadIdx.y + 1;

    // Load data into shared memory
    if (idx < N && idy < N) {
        shared_u[idy_s * (BLOCK_SIZE + 2) + idx_s] = d_u_old[idy * N + idx];
        if (threadIdx.x == 0) shared_u[idy_s * (BLOCK_SIZE + 2) + 0] = d_u_old[idy * N + (idx - 1 + N) % N];
        if (threadIdx.x == BLOCK_SIZE - 1) shared_u[idy_s * (BLOCK_SIZE + 2) + BLOCK_SIZE + 1] = d_u_old[idy * N + (idx + 1) % N];
        if (threadIdx.y == 0) shared_u[0 * (BLOCK_SIZE + 2) + idx_s] = d_u_old[((idy - 1 + N) % N) * N + idx];
        if (threadIdx.y == BLOCK_SIZE - 1) shared_u[(BLOCK_SIZE + 1) * (BLOCK_SIZE + 2) + idx_s] = d_u_old[((idy + 1) % N) * N + idx];
    }
    __syncthreads();

    // Solve tridiagonal system for each row using Thomas algorithm
    float a = -d_alpha;
    float b = 1 + 4 * d_alpha;
    float c = -d_alpha;

    float r[BLOCK_SIZE];
    float c_new[BLOCK_SIZE];
    float d_new[BLOCK_SIZE];

    // Forward sweep
    if (threadIdx.y < BLOCK_SIZE) {
        r[threadIdx.y] = shared_u[idy_s * (BLOCK_SIZE + 2) + idx_s];
        c_new[threadIdx.y] = c / b;
        d_new[threadIdx.y] = r[threadIdx.y] / b;

        for (int k = 1; k < BLOCK_SIZE; ++k) {
            float m = 1.0f / (b - a * c_new[k - 1]);
            c_new[k] = c * m;
            d_new[k] = (r[k] - a * d_new[k - 1]) * m;
        }

        // Backward sweep
        d_u_new[idy * N + idx] = d_new[BLOCK_SIZE - 1];
        for (int k = BLOCK_SIZE - 2; k >= 0; --k) {
            d_u_new[idy * N + idx] = d_new[k] - c_new[k] * d_u_new[idy * N + idx];
        }
    }
}

int main() {
    int N = 512;
    float alpha = 0.0001f;
    size_t size = N * N * sizeof(float);

    float* h_u_old = new float[size];
    float* h_u_new = new float[size];

    // Initialize data
    for (int i = 0; i < N * N; ++i) {
        h_u_old[i] = sinf(2 * M_PI * i / (N * N));
    }

    float* d_u_old;
    float* d_u_new;
    hipMalloc((void**)&d_u_old, size);
    hipMalloc((void**)&d_u_new, size);

    hipMemcpy(d_u_old, h_u_old, size, hipMemcpyHostToDevice);
    hipMemcpyToSymbol(HIP_SYMBOL(d_alpha), &alpha, sizeof(float));

    dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
    dim3 gridSize(GRID_SIZE, GRID_SIZE);

    implicitHeatKernel<<<gridSize, blockSize, (BLOCK_SIZE + 2) * (BLOCK_SIZE + 2) * sizeof(float)>>>(d_u_new, d_u_old, N);

    hipMemcpy(h_u_new, d_u_new, size, hipMemcpyDeviceToHost);

    // Free resources
    delete[] h_u_old;
    delete[] h_u_new;
    hipFree(d_u_old);
    hipFree(d_u_new);

    hipDeviceReset();
    return 0;
}
	.text
	.file	"cuda_code_050703.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__implicitHeatKernelPfS_i # -- Begin function _Z33__device_stub__implicitHeatKernelPfS_i
	.type	_Z33__device_stub__implicitHeatKernelPfS_i,@function
_Z33__device_stub__implicitHeatKernelPfS_i: # @_Z33__device_stub__implicitHeatKernelPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18implicitHeatKernelPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__implicitHeatKernelPfS_i, .Lfunc_end0-_Z33__device_stub__implicitHeatKernelPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x401921fb54442d18              # double 6.2831853071795862
.LCPI1_1:
	.quad	0x3ed0000000000000              # double 3.814697265625E-6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$953267991, 20(%rsp)            # imm = 0x38D1B717
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %rbx
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %r14
	xorl	%r15d, %r15d
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r15d, %xmm0
	mulsd	.LCPI1_0(%rip), %xmm0
	mulsd	.LCPI1_1(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	callq	sinf
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$262144, %r15                   # imm = 0x40000
	jne	.LBB1_1
# %bb.2:
	leaq	24(%rsp), %r15
	movl	$1048576, %esi                  # imm = 0x100000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	20(%rsp), %rsi
	movl	$d_alpha, %edi
	movl	$4, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movabsq	$68719476752, %rdi              # imm = 0x1000000010
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$4624, %r8d                     # imm = 0x1210
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$512, %edx                      # imm = 0x200
	callq	_Z33__device_stub__implicitHeatKernelPfS_i
.LBB1_4:
	movq	8(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18implicitHeatKernelPfS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$d_alpha, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_alpha,@object                 # @d_alpha
	.local	d_alpha
	.comm	d_alpha,4,4
	.type	_Z18implicitHeatKernelPfS_i,@object # @_Z18implicitHeatKernelPfS_i
	.section	.rodata,"a",@progbits
	.globl	_Z18implicitHeatKernelPfS_i
	.p2align	3, 0x0
_Z18implicitHeatKernelPfS_i:
	.quad	_Z33__device_stub__implicitHeatKernelPfS_i
	.size	_Z18implicitHeatKernelPfS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18implicitHeatKernelPfS_i"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"d_alpha"
	.size	.L__unnamed_2, 8

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__implicitHeatKernelPfS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_alpha
	.addrsig_sym _Z18implicitHeatKernelPfS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18implicitHeatKernelPfS_i ; -- Begin function _Z18implicitHeatKernelPfS_i
	.globl	_Z18implicitHeatKernelPfS_i
	.p2align	8
	.type	_Z18implicitHeatKernelPfS_i,@function
_Z18implicitHeatKernelPfS_i:            ; @_Z18implicitHeatKernelPfS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x10
	v_and_b32_e32 v6, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s14, s3, v[6:7]
	s_mov_b32 s3, exec_lo
	v_mad_u64_u32 v[4:5], null, s15, s4, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v0, v3, v4
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_27
; %bb.1:
	v_mul_lo_u32 v5, v4, s2
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_u32_u24_e32 v11, 34, v2
	s_mov_b32 s0, 0
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v5, v3
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v9, v[7:8], off
	v_add_nc_u32_e32 v8, 1, v6
	v_mad_u32_u24 v7, v2, 34, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v7, v7, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v9 offset:136
                                        ; implicit-def: $vgpr9
	v_cmpx_lt_i32_e32 30, v6
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %LeafBlock112
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
	v_cmpx_eq_u32_e32 31, v6
; %bb.3:
	s_mov_b32 s0, exec_lo
	v_add_nc_u32_e32 v10, 1, v3
	v_add_nc_u32_e32 v9, 0x43, v11
; %bb.4:                                ; %Flow125
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
                                        ; implicit-def: $vgpr11
.LBB0_5:                                ; %Flow124
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_9
; %bb.6:                                ; %LeafBlock
	s_mov_b32 s3, s0
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
	v_cmpx_eq_u32_e32 0, v6
; %bb.7:
	v_add_nc_u32_e32 v9, 34, v11
	v_add3_u32 v10, s2, -1, v3
	s_or_b32 s3, s0, exec_lo
; %bb.8:                                ; %Flow127
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s0, s0, s3
.LBB0_9:                                ; %Flow126
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ; %.sink.split
	s_ashr_i32 s0, s2, 31
	v_ashrrev_i32_e32 v13, 31, v10
	s_add_i32 s3, s2, s0
	v_lshl_add_u32 v9, v9, 2, 0
	s_xor_b32 s0, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v11, s0
	s_sub_i32 s3, 0, s0
	v_add_nc_u32_e32 v10, v10, v13
	v_rcp_iflag_f32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v10, v10, v13
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, 0x4f7ffffe, v11
	v_cvt_u32_f32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v12, s3, v11
	v_mul_hi_u32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, v11, v12
	v_mul_hi_u32 v11, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v11, s0
	v_sub_nc_u32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v11, s0, v10
	v_cmp_le_u32_e32 vcc_lo, s0, v10
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v11, s0, v10
	v_cmp_le_u32_e32 vcc_lo, s0, v10
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v10, v10, v13
	v_sub_nc_u32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v5
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s6, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v5, v[10:11], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v5
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s0, 0
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr9
	v_cmpx_lt_i32_e32 30, v2
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %LeafBlock116
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
	v_cmpx_eq_u32_e32 31, v2
; %bb.13:
	s_mov_b32 s0, exec_lo
	v_add_nc_u32_e32 v9, 1, v4
	v_add_nc_u32_e32 v8, 0x463, v6
; %bb.14:                               ; %Flow121
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_15:                               ; %Flow120
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_19
; %bb.16:                               ; %LeafBlock114
	s_mov_b32 s3, s0
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $vgpr9
	v_cmpx_eq_u32_e32 0, v2
; %bb.17:
	v_add3_u32 v9, s2, -1, v4
	s_or_b32 s3, s0, exec_lo
; %bb.18:                               ; %Flow123
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s0, s0, s3
.LBB0_19:                               ; %Flow122
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_21
; %bb.20:                               ; %.sink.split87
	s_ashr_i32 s0, s2, 31
	v_ashrrev_i32_e32 v6, 31, v9
	s_add_i32 s3, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s3, s0
	v_cvt_f32_u32_e32 v4, s0
	s_sub_i32 s3, 0, s0
	v_add_nc_u32_e32 v9, v9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v4
	v_xor_b32_e32 v9, v9, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v5, s3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v4, v5
	v_add_nc_u32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v9, v4
	v_mul_lo_u32 v4, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v9, v4
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_xor_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v4, v6
	v_mad_u64_u32 v[4:5], null, v6, s2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	v_lshl_add_u32 v4, v8, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
.LBB0_21:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_u32_e32 vcc_lo, 32, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.22:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_alpha@rel32@lo+4
	s_addc_u32 s1, s1, d_alpha@rel32@hi+12
	ds_load_b32 v5, v7 offset:136
	s_load_b32 s1, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v3, s1, 4.0, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v4, null, v3, v3, -s1
	v_div_scale_f32 v6, null, v3, v3, v5
	v_div_scale_f32 v11, vcc_lo, -s1, v3, -s1
	v_rcp_f32_e32 v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v4, v7, 1.0
	v_fma_f32 v10, -v6, v8, 1.0
	v_dual_fmac_f32 v7, v9, v7 :: v_dual_fmac_f32 v8, v10, v8
	v_div_scale_f32 v9, s0, v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, v11, v7
	v_mul_f32_e32 v12, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v4, v10, v11
	v_fma_f32 v14, -v6, v12, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v13, v7
	v_fmac_f32_e32 v12, v14, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v4, v10, v11
	v_fma_f32 v6, -v6, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v4, v4, v7, v10
	v_lshlrev_b32_e32 v7, 2, v2
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 4
	v_div_fmas_f32 v6, v6, v8, v12
	v_div_fixup_f32 v2, v4, v3, -s1
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v4, v6, v3, v5
	s_clause 0x1
	scratch_store_b32 v7, v2, off offset:144
	scratch_store_b32 v7, v4, off offset:272
	s_clause 0x1
	scratch_load_b32 v4, off, off offset:144
	scratch_load_b32 v2, off, off offset:272
	scratch_store_b32 v7, v5, off offset:16
.LBB0_23:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s0, 16
	s_waitcnt vmcnt(1)
	v_fma_f32 v4, s1, v4, v3
	scratch_load_b32 v5, off, s2
	s_add_i32 s2, s0, 0x90
	s_add_i32 s3, s0, 0x110
	s_add_i32 s0, s0, 4
	v_div_scale_f32 v6, null, v4, v4, 1.0
	v_div_scale_f32 v9, vcc_lo, 1.0, v4, 1.0
	s_cmpk_eq_i32 s0, 0x80
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, s1, v2
	v_fmac_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v9, v7
	v_fma_f32 v10, -v6, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v10, v7
	v_fma_f32 v6, -v6, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v7, v8
	v_div_fixup_f32 v6, v6, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v6, v5
	v_mul_f32_e64 v4, v6, -s1
	scratch_store_b32 off, v4, s2
	scratch_store_b32 off, v2, s3
	s_cbranch_scc0 .LBB0_23
; %bb.24:
	scratch_load_b32 v2, off, off offset:396
	s_movk_i32 s0, 0x78
.LBB0_25:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s0, 0x110
	s_add_i32 s2, s0, 0x90
	scratch_load_b32 v3, off, s1
	scratch_load_b32 v4, off, s2
	s_add_i32 s0, s0, -4
	s_cmp_lg_u32 s0, -4
	s_waitcnt vmcnt(0)
	v_fma_f32 v2, -v4, v2, v3
	s_cbranch_scc1 .LBB0_25
; %bb.26:                               ; %.loopexit
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_27:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18implicitHeatKernelPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 400
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18implicitHeatKernelPfS_i, .Lfunc_end0-_Z18implicitHeatKernelPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1504
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 400
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_alpha                 ; @d_alpha
	.type	d_alpha,@object
	.section	.bss,"aw",@nobits
	.globl	d_alpha
	.p2align	2, 0x0
d_alpha:
	.long	0x00000000                      ; float 0
	.size	d_alpha, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_alpha
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18implicitHeatKernelPfS_i
    .private_segment_fixed_size: 400
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18implicitHeatKernelPfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
