#include <iostream>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>

// Define the size of the filter and input
#define FILTER_SIZE 64
#define INPUT_SIZE 1024  // Example input size

// Kernel for sparse convolution
__global__ void sparseConvolutionKernel(
    const float* __restrict__ input,
    const float* __restrict__ filter,
    float* __restrict__ output,
    const int* __restrict__ input_indices,
    const int num_nonzero_elements) {
    
    // Shared memory to store the filter
    __shared__ float shared_filter[FILTER_SIZE * FILTER_SIZE];

    // Calculate the thread's position in the output
    int idx = blockIdx.x * blockDim.x + threadIdx.x;

    // Load the filter into shared memory
    if (threadIdx.x < FILTER_SIZE * FILTER_SIZE) {
        shared_filter[threadIdx.x] = filter[threadIdx.x];
    }
    __syncthreads();

    // Initialize the output to zero
    float sum = 0.0f;

    // Each thread processes one non-zero element of the input
    if (idx < num_nonzero_elements) {
        int input_idx = input_indices[idx];
        int row = input_idx / INPUT_SIZE;
        int col = input_idx % INPUT_SIZE;

        // Perform convolution for the non-zero element
        for (int i = 0; i < FILTER_SIZE; ++i) {
            for (int j = 0; j < FILTER_SIZE; ++j) {
                int input_row = row + i - FILTER_SIZE / 2;
                int input_col = col + j - FILTER_SIZE / 2;
                if (input_row >= 0 && input_row < INPUT_SIZE && input_col >= 0 && input_col < INPUT_SIZE) {
                    int input_linear_idx = input_row * INPUT_SIZE + input_col;
                    sum += input[input_linear_idx] * shared_filter[i * FILTER_SIZE + j];
                }
            }
        }
        // Write the result to the output array
        output[idx] = sum;
    }
}

int main() {
    // Initialize host data
    const int num_nonzero_elements = 100;  // Example number of non-zero elements
    float h_input[INPUT_SIZE * INPUT_SIZE] = {0};  // Sparse input matrix
    float h_filter[FILTER_SIZE * FILTER_SIZE];  // Filter matrix
    float h_output[num_nonzero_elements];  // Output array
    int h_input_indices[num_nonzero_elements];  // Indices of non-zero elements in input

    // Initialize filter with some values
    for (int i = 0; i < FILTER_SIZE * FILTER_SIZE; ++i) {
        h_filter[i] = 1.0f / (FILTER_SIZE * FILTER_SIZE);  // Simple averaging filter
    }

    // Initialize non-zero elements in the input matrix and their indices
    for (int i = 0; i < num_nonzero_elements; ++i) {
        h_input_indices[i] = i * (INPUT_SIZE / num_nonzero_elements);  // Example distribution
        h_input[h_input_indices[i]] = 1.0f;  // Non-zero value
    }

    // Allocate device memory
    float* d_input;
    float* d_filter;
    float* d_output;
    int* d_input_indices;
    cudaMalloc((void**)&d_input, sizeof(float) * INPUT_SIZE * INPUT_SIZE);
    cudaMalloc((void**)&d_filter, sizeof(float) * FILTER_SIZE * FILTER_SIZE);
    cudaMalloc((void**)&d_output, sizeof(float) * num_nonzero_elements);
    cudaMalloc((void**)&d_input_indices, sizeof(int) * num_nonzero_elements);

    // Copy data from host to device
    cudaMemcpy(d_input, h_input, sizeof(float) * INPUT_SIZE * INPUT_SIZE, cudaMemcpyHostToDevice);
    cudaMemcpy(d_filter, h_filter, sizeof(float) * FILTER_SIZE * FILTER_SIZE, cudaMemcpyHostToDevice);
    cudaMemcpy(d_input_indices, h_input_indices, sizeof(int) * num_nonzero_elements, cudaMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(num_nonzero_elements, 1, 1);
    dim3 gridSize(1, 1, 1);

    // Launch the kernel
    sparseConvolutionKernel<<<gridSize, blockSize>>>(d_input, d_filter, d_output, d_input_indices, num_nonzero_elements);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result from device to host
    cudaMemcpy(h_output, d_output, sizeof(float) * num_nonzero_elements, cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_filter);
    cudaFree(d_output);
    cudaFree(d_input_indices);

    // Print the output (for demonstration purposes)
    std::cout << "Output of sparse convolution:" << std::endl;
    for (int i = 0; i < num_nonzero_elements; ++i) {
        std::cout << h_output[i] << " ";
    }
    std::cout << std::endl;

    return 0;
}
	.file	"tmpxft_00009f20_00000000-6_cuda_code_065956.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z23sparseConvolutionKernelPKfS0_PfPKiiPKfS0_PfPKii
	.type	_Z53__device_stub__Z23sparseConvolutionKernelPKfS0_PfPKiiPKfS0_PfPKii, @function
_Z53__device_stub__Z23sparseConvolutionKernelPKfS0_PfPKiiPKfS0_PfPKii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z23sparseConvolutionKernelPKfS0_PfPKii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z53__device_stub__Z23sparseConvolutionKernelPKfS0_PfPKiiPKfS0_PfPKii, .-_Z53__device_stub__Z23sparseConvolutionKernelPKfS0_PfPKiiPKfS0_PfPKii
	.globl	_Z23sparseConvolutionKernelPKfS0_PfPKii
	.type	_Z23sparseConvolutionKernelPKfS0_PfPKii, @function
_Z23sparseConvolutionKernelPKfS0_PfPKii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z23sparseConvolutionKernelPKfS0_PfPKiiPKfS0_PfPKii
	.cfi_endproc
.LFE3661:
	.size	_Z23sparseConvolutionKernelPKfS0_PfPKii, .-_Z23sparseConvolutionKernelPKfS0_PfPKii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"CUDA error: "
.LC3:
	.string	"Output of sparse convolution:"
.LC4:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	-4210688(%rsp), %r11
	.cfi_def_cfa 11, 4210728
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$872, %rsp
	.cfi_def_cfa_offset 4211600
	movl	$1048576, %ecx
	movss	.LC0(%rip), %xmm0
	movq	%fs:40, %rax
	movq	%rax, 4211544(%rsp)
	xorl	%eax, %eax
	leaq	17240(%rsp), %rdi
	leaq	17240(%rsp), %rbp
	leaq	856(%rsp), %rbx
	rep stosl
	xorl	%eax, %eax
.L9:
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$4096, %rax
	jne	.L9
	leaq	456(%rsp), %rdx
	movss	.LC1(%rip), %xmm0
	movq	%rbp, %rcx
	xorl	%eax, %eax
	movq	%rdx, %r12
.L10:
	movl	%eax, (%rdx)
	addl	$10, %eax
	addq	$4, %rdx
	addq	$40, %rcx
	movss	%xmm0, -40(%rcx)
	cmpl	$1000, %eax
	jne	.L10
	movq	%rsp, %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$400, %edx
	call	cudaMemcpy@PLT
	movl	$1073741849, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$2, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$100, %r8d
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z53__device_stub__Z23sparseConvolutionKernelPKfS0_PfPKiiPKfS0_PfPKii
.L11:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L12
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L12:
	movq	16(%rsp), %rsi
	leaq	56(%rsp), %r12
	xorl	%ebx, %ebx
	movl	$2, %ecx
	movl	$400, %edx
	movq	%r12, %rdi
	leaq	_ZSt4cout(%rip), %rbp
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	leaq	.LC4(%rip), %r13
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rbp, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L14:
	movq	%rbp, %rdi
	cvtss2sd	(%r12,%rbx,4), %xmm0
	incq	%rbx
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	$100, %rbx
	jne	.L14
	movq	%rbp, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	xorl	%eax, %eax
.L8:
	movq	4211544(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$4211560, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z23sparseConvolutionKernelPKfS0_PfPKii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z23sparseConvolutionKernelPKfS0_PfPKii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	964689920
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>


// Define the size of the filter and input
#define FILTER_SIZE 64
#define INPUT_SIZE 1024  // Example input size

// Kernel for sparse convolution
__global__ void sparseConvolutionKernel(
    const float* __restrict__ input,
    const float* __restrict__ filter,
    float* __restrict__ output,
    const int* __restrict__ input_indices,
    const int num_nonzero_elements) {
    
    // Shared memory to store the filter
    __shared__ float shared_filter[FILTER_SIZE * FILTER_SIZE];

    // Calculate the thread's position in the output
    int idx = blockIdx.x * blockDim.x + threadIdx.x;

    // Load the filter into shared memory
    if (threadIdx.x < FILTER_SIZE * FILTER_SIZE) {
        shared_filter[threadIdx.x] = filter[threadIdx.x];
    }
    __syncthreads();

    // Initialize the output to zero
    float sum = 0.0f;

    // Each thread processes one non-zero element of the input
    if (idx < num_nonzero_elements) {
        int input_idx = input_indices[idx];
        int row = input_idx / INPUT_SIZE;
        int col = input_idx % INPUT_SIZE;

        // Perform convolution for the non-zero element
        for (int i = 0; i < FILTER_SIZE; ++i) {
            for (int j = 0; j < FILTER_SIZE; ++j) {
                int input_row = row + i - FILTER_SIZE / 2;
                int input_col = col + j - FILTER_SIZE / 2;
                if (input_row >= 0 && input_row < INPUT_SIZE && input_col >= 0 && input_col < INPUT_SIZE) {
                    int input_linear_idx = input_row * INPUT_SIZE + input_col;
                    sum += input[input_linear_idx] * shared_filter[i * FILTER_SIZE + j];
                }
            }
        }
        // Write the result to the output array
        output[idx] = sum;
    }
}

int main() {
    // Initialize host data
    const int num_nonzero_elements = 100;  // Example number of non-zero elements
    float h_input[INPUT_SIZE * INPUT_SIZE] = {0};  // Sparse input matrix
    float h_filter[FILTER_SIZE * FILTER_SIZE];  // Filter matrix
    float h_output[num_nonzero_elements];  // Output array
    int h_input_indices[num_nonzero_elements];  // Indices of non-zero elements in input

    // Initialize filter with some values
    for (int i = 0; i < FILTER_SIZE * FILTER_SIZE; ++i) {
        h_filter[i] = 1.0f / (FILTER_SIZE * FILTER_SIZE);  // Simple averaging filter
    }

    // Initialize non-zero elements in the input matrix and their indices
    for (int i = 0; i < num_nonzero_elements; ++i) {
        h_input_indices[i] = i * (INPUT_SIZE / num_nonzero_elements);  // Example distribution
        h_input[h_input_indices[i]] = 1.0f;  // Non-zero value
    }

    // Allocate device memory
    float* d_input;
    float* d_filter;
    float* d_output;
    int* d_input_indices;
    hipMalloc((void**)&d_input, sizeof(float) * INPUT_SIZE * INPUT_SIZE);
    hipMalloc((void**)&d_filter, sizeof(float) * FILTER_SIZE * FILTER_SIZE);
    hipMalloc((void**)&d_output, sizeof(float) * num_nonzero_elements);
    hipMalloc((void**)&d_input_indices, sizeof(int) * num_nonzero_elements);

    // Copy data from host to device
    hipMemcpy(d_input, h_input, sizeof(float) * INPUT_SIZE * INPUT_SIZE, hipMemcpyHostToDevice);
    hipMemcpy(d_filter, h_filter, sizeof(float) * FILTER_SIZE * FILTER_SIZE, hipMemcpyHostToDevice);
    hipMemcpy(d_input_indices, h_input_indices, sizeof(int) * num_nonzero_elements, hipMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(num_nonzero_elements, 1, 1);
    dim3 gridSize(1, 1, 1);

    // Launch the kernel
    sparseConvolutionKernel<<<gridSize, blockSize>>>(d_input, d_filter, d_output, d_input_indices, num_nonzero_elements);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result from device to host
    hipMemcpy(h_output, d_output, sizeof(float) * num_nonzero_elements, hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_input);
    hipFree(d_filter);
    hipFree(d_output);
    hipFree(d_input_indices);

    // Print the output (for demonstration purposes)
    std::cout << "Output of sparse convolution:" << std::endl;
    for (int i = 0; i < num_nonzero_elements; ++i) {
        std::cout << h_output[i] << " ";
    }
    std::cout << std::endl;

    return 0;
}
	.text
	.file	"cuda_code_065956.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii
	.type	_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii,@function
_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii: # @_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23sparseConvolutionKernelPKfS0_PfPKii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii, .Lfunc_end0-_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$4211528, %rsp                  # imm = 0x404348
	.cfi_def_cfa_offset 4211568
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	17216(%rsp), %rdi
	xorl	%ebx, %ebx
	movl	$4194304, %edx                  # imm = 0x400000
	xorl	%esi, %esi
	callq	memset@PLT
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$964689920, 832(%rsp,%rbx,4)    # imm = 0x39800000
	incq	%rbx
	cmpq	$4096, %rbx                     # imm = 0x1000
	jne	.LBB1_1
# %bb.2:                                # %.preheader.preheader
	leaq	32(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ecx, (%rax)
	movl	$1065353216, 17216(%rsp,%rcx,4) # imm = 0x3F800000
	addq	$10, %rcx
	addq	$4, %rax
	cmpq	$1000, %rcx                     # imm = 0x3E8
	jne	.LBB1_3
# %bb.4:
	leaq	24(%rsp), %r14
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rbx
	movl	$16384, %esi                    # imm = 0x4000
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hipMalloc
	leaq	8(%rsp), %r15
	movl	$400, %esi                      # imm = 0x190
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	leaq	17216(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	leaq	832(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	leaq	32(%rsp), %rsi
	movl	$400, %edx                      # imm = 0x190
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	99(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	$100, %r8d
	callq	_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii
.LBB1_6:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_9
# %bb.7:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_11
# %bb.8:
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%r14, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_12
.LBB1_9:
	movq	(%rsp), %rsi
	leaq	432(%rsp), %rdi
	movl	$400, %edx                      # imm = 0x190
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$29, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB1_10:                               # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	432(%rsp,%r15,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.2, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	$100, %r15
	jne	.LBB1_10
	jmp	.LBB1_13
.LBB1_11:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movl	$-1, %r14d
.LBB1_13:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	%r14d, %eax
	addq	$4211528, %rsp                  # imm = 0x404348
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23sparseConvolutionKernelPKfS0_PfPKii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23sparseConvolutionKernelPKfS0_PfPKii,@object # @_Z23sparseConvolutionKernelPKfS0_PfPKii
	.section	.rodata,"a",@progbits
	.globl	_Z23sparseConvolutionKernelPKfS0_PfPKii
	.p2align	3, 0x0
_Z23sparseConvolutionKernelPKfS0_PfPKii:
	.quad	_Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii
	.size	_Z23sparseConvolutionKernelPKfS0_PfPKii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Output of sparse convolution:"
	.size	.L.str.1, 30

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" "
	.size	.L.str.2, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z23sparseConvolutionKernelPKfS0_PfPKii"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__sparseConvolutionKernelPKfS0_PfPKii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23sparseConvolutionKernelPKfS0_PfPKii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23sparseConvolutionKernelPKfS0_PfPKii ; -- Begin function _Z23sparseConvolutionKernelPKfS0_PfPKii
	.globl	_Z23sparseConvolutionKernelPKfS0_PfPKii
	.p2align	8
	.type	_Z23sparseConvolutionKernelPKfS0_PfPKii,@function
_Z23sparseConvolutionKernelPKfS0_PfPKii: ; @_Z23sparseConvolutionKernelPKfS0_PfPKii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x8
	v_lshlrev_b32_e32 v3, 2, v0
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x20
	s_load_b32 s5, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	global_load_b32 v4, v3, s[2:3]
	s_and_b32 s2, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	s_mov_b32 s6, 0
	s_mov_b32 s7, 0
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v3, 22, v3
	v_add_nc_u32_e32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 10, v3
	v_and_b32_e32 v5, 0xfffffc00, v3
	v_mov_b32_e32 v3, 0
	v_mul_i32_i24_e32 v7, 0x400, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 0xffff7fe0, v5
	v_sub_nc_u32_e32 v7, v2, v7
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	v_add3_u32 v2, s7, v4, 0xffffffe0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v8, v7
	s_mov_b32 s8, 0
	v_cmp_gt_u32_e32 vcc_lo, 0x400, v2
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s0, 31, v8
	v_cmp_gt_i32_e64 s1, 0x420, v8
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	v_add_nc_u32_e32 v2, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	v_add_co_u32 v9, s0, s2, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s3, v10, s0
	s_add_i32 s0, s6, s8
	global_load_b32 v2, v[9:10], off
	v_mov_b32_e32 v9, s0
	ds_load_b32 v9, v9
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v5, v2, v9
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v8, 1, v8
	s_add_i32 s8, s8, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s8, 0x100
	s_cbranch_scc0 .LBB0_3
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v6, 0x400, v6
	s_add_i32 s7, s7, 1
	s_addk_i32 s6, 0x100
	s_cmp_eq_u32 s7, 64
	s_cbranch_scc0 .LBB0_2
; %bb.7:
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23sparseConvolutionKernelPKfS0_PfPKii
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23sparseConvolutionKernelPKfS0_PfPKii, .Lfunc_end0-_Z23sparseConvolutionKernelPKfS0_PfPKii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23sparseConvolutionKernelPKfS0_PfPKii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23sparseConvolutionKernelPKfS0_PfPKii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
