#include <iostream>
#include <cuda_runtime.h>

// Define the maximum level of the skip list
#define MAX_LEVEL 5

// Define the number of elements in the skip list
#define NUM_ELEMENTS 32

// Define the Node structure
struct Node {
    int value;
    Node* forward[MAX_LEVEL];
};

// Kernel to initialize the skip list
__global__ void initializeSkipList(Node* nodes, int numElements) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numElements) {
        nodes[idx].value = idx; // Initialize with index value for simplicity
        for (int level = 0; level < MAX_LEVEL; ++level) {
            nodes[idx].forward[level] = nullptr;
        }
    }
}

// Kernel to insert elements into the skip list
__global__ void insertIntoSkipList(Node* nodes, int numElements) {
    extern __shared__ Node* update[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numElements) {
        Node* current = &nodes[0];
        for (int level = MAX_LEVEL - 1; level >= 0; --level) {
            while (current->forward[level] != nullptr && current->forward[level]->value < nodes[idx].value) {
                current = current->forward[level];
            }
            update[level] = current;
        }
        current = current->forward[0];
        if (current == nullptr || current->value != nodes[idx].value) {
            Node* newNode = &nodes[idx];
            for (int level = 0; level < MAX_LEVEL; ++level) {
                newNode->forward[level] = update[level]->forward[level];
                update[level]->forward[level] = newNode;
            }
        }
    }
}

int main() {
    // Allocate Unified Memory for nodes
    Node* nodes;
    cudaError_t err = cudaMallocManaged(&nodes, NUM_ELEMENTS * sizeof(Node));
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate Unified Memory for nodes" << std::endl;
        return -1;
    }

    // Initialize the skip list
    int blockSize = 32;
    int numBlocks = (NUM_ELEMENTS + blockSize - 1) / blockSize;
    initializeSkipList<<<numBlocks, blockSize>>>(nodes, NUM_ELEMENTS);
    err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "Failed to launch initializeSkipList kernel (error code " << err << ")" << std::endl;
        cudaFree(nodes);
        return -1;
    }
    err = cudaDeviceSynchronize();
    if (err != cudaSuccess) {
        std::cerr << "Failed to synchronize after initializeSkipList (error code " << err << ")" << std::endl;
        cudaFree(nodes);
        return -1;
    }

    // Insert elements into the skip list
    insertIntoSkipList<<<numBlocks, blockSize, MAX_LEVEL * sizeof(Node*)>>>(nodes, NUM_ELEMENTS);
    err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "Failed to launch insertIntoSkipList kernel (error code " << err << ")" << std::endl;
        cudaFree(nodes);
        return -1;
    }
    err = cudaDeviceSynchronize();
    if (err != cudaSuccess) {
        std::cerr << "Failed to synchronize after insertIntoSkipList (error code " << err << ")" << std::endl;
        cudaFree(nodes);
        return -1;
    }

    // Free Unified Memory
    cudaFree(nodes);

    std::cout << "Skip list operations completed successfully." << std::endl;
    return 0;
}
	.file	"tmpxft_00134a0c_00000000-6_cuda_code_024427.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4295:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4295:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
	.type	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei, @function
_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z18initializeSkipListP4Nodei(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei, .-_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
	.globl	_Z18initializeSkipListP4Nodei
	.type	_Z18initializeSkipListP4Nodei, @function
_Z18initializeSkipListP4Nodei:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
	.cfi_endproc
.LFE3661:
	.size	_Z18initializeSkipListP4Nodei, .-_Z18initializeSkipListP4Nodei
	.globl	_Z43__device_stub__Z18insertIntoSkipListP4NodeiP4Nodei
	.type	_Z43__device_stub__Z18insertIntoSkipListP4NodeiP4Nodei, @function
_Z43__device_stub__Z18insertIntoSkipListP4NodeiP4Nodei:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z18insertIntoSkipListP4Nodei(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L9:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z43__device_stub__Z18insertIntoSkipListP4NodeiP4Nodei, .-_Z43__device_stub__Z18insertIntoSkipListP4NodeiP4Nodei
	.globl	_Z18insertIntoSkipListP4Nodei
	.type	_Z18insertIntoSkipListP4Nodei, @function
_Z18insertIntoSkipListP4Nodei:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18insertIntoSkipListP4NodeiP4Nodei
	.cfi_endproc
.LFE3663:
	.size	_Z18insertIntoSkipListP4Nodei, .-_Z18insertIntoSkipListP4Nodei
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Failed to allocate Unified Memory for nodes"
.LC1:
	.string	"Failed to launch initializeSkipList kernel (error code "
.LC2:
	.string	")"
.LC3:
	.string	"Failed to synchronize after initializeSkipList (error code "
.LC4:
	.string	"Failed to launch insertIntoSkipList kernel (error code "
.LC5:
	.string	"Failed to synchronize after insertIntoSkipList (error code "
.LC6:
	.string	"Skip list operations completed successfully."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$1, %edx
	movl	$1536, %esi
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	je	.L15
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	jmp	.L16
.L15:
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 36(%rsp)
	movq	%rdx, 28(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	8(%rsp), %rdi
	movl	$32, %esi
	call	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
.L17:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L18
	leaq	.LC1(%rip), %rsi
.L26:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
.L16:
	orl	$-1, %eax
	jmp	.L14
.L18:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC3(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L26
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	salq	$5, %rdx
	movl	$40, %r8d
	movl	$1, %esi
	movl	$1, 36(%rsp)
	movq	%rdx, 28(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	8(%rsp), %rdi
	movl	$32, %esi
	call	_Z43__device_stub__Z18insertIntoSkipListP4NodeiP4Nodei
.L21:
	call	cudaGetLastError@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L26
	call	cudaDeviceSynchronize@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L26
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	xorl	%eax, %eax
.L14:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z18insertIntoSkipListP4Nodei"
.LC8:
	.string	"_Z18initializeSkipListP4Nodei"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18insertIntoSkipListP4Nodei(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18initializeSkipListP4Nodei(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

// Define the maximum level of the skip list
#define MAX_LEVEL 5

// Define the number of elements in the skip list
#define NUM_ELEMENTS 32

// Define the Node structure
struct Node {
    int value;
    Node* forward[MAX_LEVEL];
};

// Kernel to initialize the skip list
__global__ void initializeSkipList(Node* nodes, int numElements) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numElements) {
        nodes[idx].value = idx; // Initialize with index value for simplicity
        for (int level = 0; level < MAX_LEVEL; ++level) {
            nodes[idx].forward[level] = nullptr;
        }
    }
}

// Kernel to insert elements into the skip list
__global__ void insertIntoSkipList(Node* nodes, int numElements) {
    extern __shared__ Node* update[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numElements) {
        Node* current = &nodes[0];
        for (int level = MAX_LEVEL - 1; level >= 0; --level) {
            while (current->forward[level] != nullptr && current->forward[level]->value < nodes[idx].value) {
                current = current->forward[level];
            }
            update[level] = current;
        }
        current = current->forward[0];
        if (current == nullptr || current->value != nodes[idx].value) {
            Node* newNode = &nodes[idx];
            for (int level = 0; level < MAX_LEVEL; ++level) {
                newNode->forward[level] = update[level]->forward[level];
                update[level]->forward[level] = newNode;
            }
        }
    }
}

int main() {
    // Allocate Unified Memory for nodes
    Node* nodes;
    hipError_t err = hipMallocManaged(&nodes, NUM_ELEMENTS * sizeof(Node));
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate Unified Memory for nodes" << std::endl;
        return -1;
    }

    // Initialize the skip list
    int blockSize = 32;
    int numBlocks = (NUM_ELEMENTS + blockSize - 1) / blockSize;
    initializeSkipList<<<numBlocks, blockSize>>>(nodes, NUM_ELEMENTS);
    err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "Failed to launch initializeSkipList kernel (error code " << err << ")" << std::endl;
        hipFree(nodes);
        return -1;
    }
    err = hipDeviceSynchronize();
    if (err != hipSuccess) {
        std::cerr << "Failed to synchronize after initializeSkipList (error code " << err << ")" << std::endl;
        hipFree(nodes);
        return -1;
    }

    // Insert elements into the skip list
    insertIntoSkipList<<<numBlocks, blockSize, MAX_LEVEL * sizeof(Node*)>>>(nodes, NUM_ELEMENTS);
    err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "Failed to launch insertIntoSkipList kernel (error code " << err << ")" << std::endl;
        hipFree(nodes);
        return -1;
    }
    err = hipDeviceSynchronize();
    if (err != hipSuccess) {
        std::cerr << "Failed to synchronize after insertIntoSkipList (error code " << err << ")" << std::endl;
        hipFree(nodes);
        return -1;
    }

    // Free Unified Memory
    hipFree(nodes);

    std::cout << "Skip list operations completed successfully." << std::endl;
    return 0;
}
	.text
	.file	"cuda_code_024427.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__initializeSkipListP4Nodei # -- Begin function _Z33__device_stub__initializeSkipListP4Nodei
	.type	_Z33__device_stub__initializeSkipListP4Nodei,@function
_Z33__device_stub__initializeSkipListP4Nodei: # @_Z33__device_stub__initializeSkipListP4Nodei
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18initializeSkipListP4Nodei, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__initializeSkipListP4Nodei, .Lfunc_end0-_Z33__device_stub__initializeSkipListP4Nodei
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__insertIntoSkipListP4Nodei # -- Begin function _Z33__device_stub__insertIntoSkipListP4Nodei
	.type	_Z33__device_stub__insertIntoSkipListP4Nodei,@function
_Z33__device_stub__insertIntoSkipListP4Nodei: # @_Z33__device_stub__insertIntoSkipListP4Nodei
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18insertIntoSkipListP4Nodei, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__insertIntoSkipListP4Nodei, .Lfunc_end1-_Z33__device_stub__insertIntoSkipListP4Nodei
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	leaq	8(%rsp), %rdi
	movl	$1536, %esi                     # imm = 0x600
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$43, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	jmp	.LBB2_11
.LBB2_2:
	movabsq	$4294967297, %r14               # imm = 0x100000001
	leaq	31(%r14), %rbx
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	8(%rsp), %rdi
	movl	$32, %esi
	callq	_Z33__device_stub__initializeSkipListP4Nodei
.LBB2_4:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB2_6
# %bb.5:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$55, %edx
	jmp	.LBB2_8
.LBB2_6:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB2_13
# %bb.7:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	movl	$59, %edx
.LBB2_8:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebp, %esi
.LBB2_9:
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.2, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB2_10:
	movq	8(%rsp), %rdi
	callq	hipFree
.LBB2_11:
	movl	$-1, %eax
.LBB2_12:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_13:
	.cfi_def_cfa_offset 48
	movl	$40, %r8d
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:
	movq	8(%rsp), %rdi
	movl	$32, %esi
	callq	_Z33__device_stub__insertIntoSkipListP4Nodei
.LBB2_15:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB2_17
# %bb.16:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.4, %esi
	movl	$55, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebx, %esi
	jmp	.LBB2_9
.LBB2_17:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB2_19
# %bb.18:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.5, %esi
	movl	$59, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.2, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB2_10
.LBB2_19:
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$44, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	xorl	%eax, %eax
	jmp	.LBB2_12
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18initializeSkipListP4Nodei, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18insertIntoSkipListP4Nodei, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18initializeSkipListP4Nodei,@object # @_Z18initializeSkipListP4Nodei
	.section	.rodata,"a",@progbits
	.globl	_Z18initializeSkipListP4Nodei
	.p2align	3, 0x0
_Z18initializeSkipListP4Nodei:
	.quad	_Z33__device_stub__initializeSkipListP4Nodei
	.size	_Z18initializeSkipListP4Nodei, 8

	.type	_Z18insertIntoSkipListP4Nodei,@object # @_Z18insertIntoSkipListP4Nodei
	.globl	_Z18insertIntoSkipListP4Nodei
	.p2align	3, 0x0
_Z18insertIntoSkipListP4Nodei:
	.quad	_Z33__device_stub__insertIntoSkipListP4Nodei
	.size	_Z18insertIntoSkipListP4Nodei, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Failed to allocate Unified Memory for nodes"
	.size	.L.str, 44

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Failed to launch initializeSkipList kernel (error code "
	.size	.L.str.1, 56

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	")"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to synchronize after initializeSkipList (error code "
	.size	.L.str.3, 60

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to launch insertIntoSkipList kernel (error code "
	.size	.L.str.4, 56

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to synchronize after insertIntoSkipList (error code "
	.size	.L.str.5, 60

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Skip list operations completed successfully."
	.size	.L.str.6, 45

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18initializeSkipListP4Nodei"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18insertIntoSkipListP4Nodei"
	.size	.L__unnamed_2, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__initializeSkipListP4Nodei
	.addrsig_sym _Z33__device_stub__insertIntoSkipListP4Nodei
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18initializeSkipListP4Nodei
	.addrsig_sym _Z18insertIntoSkipListP4Nodei
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18initializeSkipListP4Nodei ; -- Begin function _Z18initializeSkipListP4Nodei
	.globl	_Z18initializeSkipListP4Nodei
	.p2align	8
	.type	_Z18initializeSkipListP4Nodei,@function
_Z18initializeSkipListP4Nodei:          ; @_Z18initializeSkipListP4Nodei
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v3
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[0:1], null, v3, 48, s[0:1]
	s_mov_b64 s[0:1], 8
	global_store_b32 v[0:1], v3, off
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v4, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_mov_b32_e32 v3, v2
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 48
	global_store_b64 v[4:5], v[2:3], off
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18initializeSkipListP4Nodei
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18initializeSkipListP4Nodei, .Lfunc_end0-_Z18initializeSkipListP4Nodei
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18insertIntoSkipListP4Nodei ; -- Begin function _Z18insertIntoSkipListP4Nodei
	.globl	_Z18insertIntoSkipListP4Nodei
	.p2align	8
	.type	_Z18insertIntoSkipListP4Nodei,@function
_Z18insertIntoSkipListP4Nodei:          ; @_Z18insertIntoSkipListP4Nodei
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_12
; %bb.1:                                ; %.preheader37
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b32 s4, 4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[2:3], null, v1, 48, s[0:1]
	v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_mov_b32 s2, s4
	s_mov_b32 s6, s3
	s_lshl_b64 s[4:5], s[2:3], 3
                                        ; implicit-def: $sgpr7
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
	s_or_b32 s7, s7, exec_lo
	s_mov_b32 s8, exec_lo
	v_add_co_u32 v6, vcc_lo, v4, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
	flat_load_b64 v[6:7], v[6:7] offset:8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_ne_u64_e32 0, v[6:7]
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_3 Depth=2
	flat_load_b32 v0, v[6:7]
	global_load_b32 v8, v[2:3], off
	s_and_not1_b32 s7, s7, exec_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v0, v8
	s_and_b32 s9, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s7, s9
.LBB1_5:                                ; %Flow52
                                        ;   in Loop: Header=BB1_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s8, exec_lo, s7
	s_or_b32 s6, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_3
; %bb.6:                                ; %.critedge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_lshl_b32 s4, s2, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, 0
	v_mov_b32_e32 v0, s4
	s_add_i32 s4, s2, -1
	s_cmp_eq_u32 s2, 0
	ds_store_b64 v0, v[4:5]
	s_cbranch_scc0 .LBB1_2
; %bb.7:
	flat_load_b64 v[4:5], v[4:5] offset:8
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_eq_u64_e64 s2, 0, v[4:5]
	v_cmpx_ne_u64_e32 0, v[4:5]
	s_cbranch_execz .LBB1_9
; %bb.8:
	flat_load_b32 v0, v[4:5]
	global_load_b32 v2, v[2:3], off
	s_and_not1_b32 s2, s2, exec_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v0, v2
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s4
.LBB1_9:                                ; %Flow49
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_12
; %bb.10:
	v_mad_i64_i32 v[2:3], null, v1, 48, s[0:1]
	s_mov_b64 s[0:1], 8
	s_mov_b32 s2, 0
.LBB1_11:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v0, s2
	ds_load_b64 v[0:1], v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
	flat_load_b64 v[4:5], v[0:1]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_add_i32 s2, s2, 8
	s_cmp_lg_u32 s0, 48
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b64 v[6:7], v[4:5], off
	flat_store_b64 v[0:1], v[2:3]
	s_cbranch_scc1 .LBB1_11
.LBB1_12:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18insertIntoSkipListP4Nodei
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18insertIntoSkipListP4Nodei, .Lfunc_end1-_Z18insertIntoSkipListP4Nodei
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18initializeSkipListP4Nodei
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18initializeSkipListP4Nodei.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18insertIntoSkipListP4Nodei
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18insertIntoSkipListP4Nodei.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
