#include <iostream>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

// Define the number of non-zero elements
#define NNZ 128

// Kernel to perform sparse tensor multiplication
__global__ void sparseTensorMultiply(const half* __restrict__ A_vals, const int* __restrict__ A_cols, const int* __restrict__ A_rows,
                                    const half* __restrict__ B_vals, const int* __restrict__ B_cols, const int* __restrict__ B_rows,
                                    half* __restrict__ C_vals, int* __restrict__ C_cols, int* __restrict__ C_rows, int num_rows_A, int num_cols_B) {
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    if (row < num_rows_A && col < num_cols_B) {
        half sum = __float2half(0.0f);
        int startA = A_rows[row];
        int endA = A_rows[row + 1];
        int startB = B_rows[col];
        int endB = B_rows[col + 1];

        while (startA < endA && startB < endB) {
            if (A_cols[startA] < B_cols[startB]) {
                startA++;
            } else if (A_cols[startA] > B_cols[startB]) {
                startB++;
            } else {
                sum += A_vals[startA] * B_vals[startB];
                startA++;
                startB++;
            }
        }
        if (__half2float(sum) != 0.0f) {
            int pos = atomicAdd(&C_rows[row], 1);
            C_vals[pos] = sum;
            C_cols[pos] = col;
        }
    }
}

int main() {
    // Initialize CUDA
    cudaError_t err;
    int num_devices;
    cudaGetDeviceCount(&num_devices);
    if (num_devices < 1) {
        std::cerr << "No CUDA devices found!" << std::endl;
        return -1;
    }

    // Initialize data for sparse matrices A and B
    // For demonstration, we will use small matrices
    // A is a 4x4 matrix with 128 non-zero elements (repeated for demonstration)
    // B is a 4x4 matrix with 128 non-zero elements (repeated for demonstration)
    int num_rows_A = 4, num_cols_A = 4, num_rows_B = 4, num_cols_B = 4;
    int nnz_A = NNZ, nnz_B = NNZ;

    // Allocate Unified Memory for A and B
    half* A_vals, *B_vals, *C_vals;
    int* A_cols, *A_rows, *B_cols, *B_rows, *C_cols, *C_rows;
    err = cudaMallocManaged(&A_vals, nnz_A * sizeof(half));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for A_vals" << std::endl; return -1; }
    err = cudaMallocManaged(&A_cols, nnz_A * sizeof(int));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for A_cols" << std::endl; return -1; }
    err = cudaMallocManaged(&A_rows, (num_rows_A + 1) * sizeof(int));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for A_rows" << std::endl; return -1; }
    err = cudaMallocManaged(&B_vals, nnz_B * sizeof(half));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for B_vals" << std::endl; return -1; }
    err = cudaMallocManaged(&B_cols, nnz_B * sizeof(int));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for B_cols" << std::endl; return -1; }
    err = cudaMallocManaged(&B_rows, (num_cols_B + 1) * sizeof(int));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for B_rows" << std::endl; return -1; }

    // Initialize A and B (for demonstration purposes, we fill with dummy data)
    for (int i = 0; i < nnz_A; i++) {
        A_vals[i] = __float2half(1.0f);
        A_cols[i] = i % num_cols_A;
    }
    for (int i = 0; i <= num_rows_A; i++) {
        A_rows[i] = i * (nnz_A / num_rows_A);
    }
    for (int i = 0; i < nnz_B; i++) {
        B_vals[i] = __float2half(1.0f);
        B_cols[i] = i % num_cols_B;
    }
    for (int i = 0; i <= num_cols_B; i++) {
        B_rows[i] = i * (nnz_B / num_cols_B);
    }

    // Allocate Unified Memory for C
    int max_nnz_C = num_rows_A * num_cols_B;
    err = cudaMallocManaged(&C_vals, max_nnz_C * sizeof(half));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for C_vals" << std::endl; return -1; }
    err = cudaMallocManaged(&C_cols, max_nnz_C * sizeof(int));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for C_cols" << std::endl; return -1; }
    err = cudaMallocManaged(&C_rows, (num_rows_A + 1) * sizeof(int));
    if (err != cudaSuccess) { std::cerr << "Failed to allocate memory for C_rows" << std::endl; return -1; }

    // Initialize C_rows to 0
    for (int i = 0; i <= num_rows_A; i++) {
        C_rows[i] = 0;
    }

    // Define grid and block sizes
    dim3 blockSize(16, 16);
    dim3 gridSize((num_cols_B + blockSize.x - 1) / blockSize.x, (num_rows_A + blockSize.y - 1) / blockSize.y);

    // Launch the kernel
    sparseTensorMultiply<<<gridSize, blockSize>>>(A_vals, A_cols, A_rows, B_vals, B_cols, B_rows, C_vals, C_cols, C_rows, num_rows_A, num_cols_B);
    err = cudaGetLastError();
    if (err != cudaSuccess) { std::cerr << "Kernel launch failed: " << cudaGetErrorString(err) << std::endl; return -1; }

    // Wait for GPU to finish before accessing on host
    err = cudaDeviceSynchronize();
    if (err != cudaSuccess) { std::cerr << "Failed to synchronize: " << cudaGetErrorString(err) << std::endl; return -1; }

    // Output results
    int nnz_C = C_rows[num_rows_A];
    std::cout << "Resultant Sparse Matrix C (Non-zero elements: " << nnz_C << "):" << std::endl;
    for (int i = 0; i < nnz_C; i++) {
        std::cout << "C[" << C_rows[i / num_cols_B] << "][" << C_cols[i] << "] = " << __half2float(C_vals[i]) << std::endl;
    }

    // Free memory
    cudaFree(A_vals); cudaFree(A_cols); cudaFree(A_rows);
    cudaFree(B_vals); cudaFree(B_cols); cudaFree(B_rows);
    cudaFree(C_vals); cudaFree(C_cols); cudaFree(C_rows);

    return 0;
}
	.file	"tmpxft_00123952_00000000-6_cuda_code_019413.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL12__float2halff.constprop.0, @function
_ZL12__float2halff.constprop.0:
.LFB4669:
	.cfi_startproc
	movl	$15360, %eax
	ret
	.cfi_endproc
.LFE4669:
	.size	_ZL12__float2halff.constprop.0, .-_ZL12__float2halff.constprop.0
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4671:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4671:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z72__device_stub__Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_iiPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.type	_Z72__device_stub__Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_iiPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, @function
_Z72__device_stub__Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_iiPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii:
.LFB4034:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	256(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 56(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 64(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 32(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 72(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 96(%rsp)
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L4:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4034:
	.size	_Z72__device_stub__Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_iiPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, .-_Z72__device_stub__Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_iiPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.globl	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.type	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, @function
_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii:
.LFB4035:
	.cfi_startproc
	endbr64
	jmp	_Z72__device_stub__Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_iiPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.cfi_endproc
.LFE4035:
	.size	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, .-_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"No CUDA devices found!"
.LC1:
	.string	"Failed to allocate memory for A_vals"
.LC2:
	.string	"Failed to allocate memory for A_cols"
.LC3:
	.string	"Failed to allocate memory for A_rows"
.LC4:
	.string	"Failed to allocate memory for B_vals"
.LC5:
	.string	"Failed to allocate memory for B_cols"
.LC6:
	.string	"Failed to allocate memory for B_rows"
.LC7:
	.string	"Failed to allocate memory for C_vals"
.LC8:
	.string	"Failed to allocate memory for C_cols"
.LC9:
	.string	"Failed to allocate memory for C_rows"
.LC10:
	.string	"Kernel launch failed: "
.LC11:
	.string	"Failed to synchronize: "
.LC12:
	.string	"Resultant Sparse Matrix C (Non-zero elements: "
.LC13:
	.string	"):"
.LC14:
	.string	"C["
.LC15:
	.string	"]["
.LC16:
	.string	"] = "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4009:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$120, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
	cmpl	$0, 4(%rsp)
	leaq	.LC0(%rip), %rsi
	jle	.L46
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$256, %esi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	je	.L13
	leaq	.LC1(%rip), %rsi
.L46:
	leaq	_ZSt4cerr(%rip), %rdi
.L47:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	orl	$-1, %eax
	jmp	.L10
.L13:
	movl	$512, %esi
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC2(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
	movl	$20, %esi
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC3(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
	movl	$256, %esi
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC4(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
	movl	$512, %esi
	leaq	48(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC5(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
	movl	$1, %edx
	movl	$20, %esi
	leaq	56(%rsp), %rdi
	call	cudaMallocManaged@PLT
	xorl	%edx, %edx
	leaq	.LC6(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
.L19:
	call	_ZL12__float2halff.constprop.0
	movq	8(%rsp), %rcx
	movw	%ax, (%rcx,%rdx,2)
	movl	%edx, %ecx
	movq	32(%rsp), %rax
	andl	$3, %ecx
	movl	%ecx, (%rax,%rdx,4)
	incq	%rdx
	cmpq	$128, %rdx
	jne	.L19
	movq	40(%rsp), %rax
	movl	$1, %ebx
	xorl	%edx, %edx
	salq	$37, %rbx
	movq	%rbx, (%rax)
	movabsq	$412316860480, %rbx
	movq	%rbx, 8(%rax)
	movl	$128, 16(%rax)
.L20:
	call	_ZL12__float2halff.constprop.0
	movq	16(%rsp), %rcx
	movw	%ax, (%rcx,%rdx,2)
	movl	%edx, %ecx
	movq	48(%rsp), %rax
	andl	$3, %ecx
	movl	%ecx, (%rax,%rdx,4)
	incq	%rdx
	cmpq	$128, %rdx
	jne	.L20
	movq	56(%rsp), %rax
	movl	$1, %ebx
	movl	$32, %esi
	leaq	24(%rsp), %rdi
	salq	$37, %rbx
	movl	$1, %edx
	movq	%rbx, (%rax)
	movabsq	$412316860480, %rbx
	movq	%rbx, 8(%rax)
	movl	$128, 16(%rax)
	call	cudaMallocManaged@PLT
	leaq	.LC7(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
	movl	$64, %esi
	leaq	64(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC8(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
	movl	$20, %esi
	leaq	72(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC9(%rip), %rsi
	testl	%eax, %eax
	jne	.L46
	movq	72(%rsp), %rdi
	movl	$5, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movl	$1, 100(%rsp)
	rep stosl
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movq	%rdx, 80(%rsp)
	movq	%rdi, 92(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	%rax
	.cfi_def_cfa_offset 168
	pushq	$4
	.cfi_def_cfa_offset 176
	pushq	$4
	.cfi_def_cfa_offset 184
	pushq	96(%rsp)
	.cfi_def_cfa_offset 192
	pushq	96(%rsp)
	.cfi_def_cfa_offset 200
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	104(%rsp), %r9
	movq	96(%rsp), %r8
	movq	64(%rsp), %rcx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z72__device_stub__Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_iiPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	addq	$48, %rsp
	.cfi_def_cfa_offset 160
.L24:
	call	cudaGetLastError@PLT
	leaq	.LC10(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L48
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L26
	leaq	.LC11(%rip), %rsi
.L48:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	jmp	.L47
.L26:
	movq	72(%rsp), %rax
	leaq	_ZSt4cout(%rip), %r12
	leaq	.LC12(%rip), %rsi
	xorl	%ebx, %ebx
	movq	%r12, %rdi
	leaq	.LC14(%rip), %r13
	movl	16(%rax), %ebp
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movl	%ebp, %esi
	call	_ZNSolsEi@PLT
	leaq	.LC13(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L27:
	cmpl	%ebx, %ebp
	jle	.L49
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	72(%rsp), %rdx
	movq	%rax, %rdi
	movl	%ebx, %eax
	sarl	$2, %eax
	cltq
	movl	(%rdx,%rax,4), %esi
	call	_ZNSolsEi@PLT
	leaq	.LC15(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	64(%rsp), %rax
	movl	(%rax,%rbx,4), %esi
	call	_ZNSolsEi@PLT
	leaq	.LC16(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	24(%rsp), %rax
	movw	(%rax,%rbx,2), %dx
	movl	%edx, %eax
	movl	%edx, %ecx
	sall	$13, %edx
	shrw	$10, %ax
	shrw	$15, %cx
	andl	$8380416, %edx
	andl	$31, %eax
	movzwl	%cx, %ecx
	cmpw	$31, %ax
	jne	.L28
	movl	$255, %eax
	testl	%edx, %edx
	je	.L29
	xorl	%ecx, %ecx
	movl	$8388607, %edx
	jmp	.L29
.L28:
	testw	%ax, %ax
	jne	.L30
	xorl	%eax, %eax
	testl	%edx, %edx
	je	.L29
	movl	$113, %eax
.L31:
	movl	%edx, %esi
	decl	%eax
	addl	%edx, %edx
	andl	$4194304, %esi
	testl	%esi, %esi
	je	.L31
	andl	$8388607, %edx
	jmp	.L29
.L30:
	addl	$112, %eax
	movzwl	%ax, %eax
.L29:
	sall	$23, %eax
	sall	$31, %ecx
	incq	%rbx
	orl	%eax, %ecx
	orl	%edx, %ecx
	movd	%ecx, %xmm1
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	jmp	.L27
.L49:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L10:
	movq	104(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$120, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4009:
	.size	main, .-main
	.section	.rodata.str1.1
.LC17:
	.string	"_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>

// Define the number of non-zero elements
#define NNZ 128

// Kernel to perform sparse tensor multiplication
__global__ void sparseTensorMultiply(const half* __restrict__ A_vals, const int* __restrict__ A_cols, const int* __restrict__ A_rows,
                                    const half* __restrict__ B_vals, const int* __restrict__ B_cols, const int* __restrict__ B_rows,
                                    half* __restrict__ C_vals, int* __restrict__ C_cols, int* __restrict__ C_rows, int num_rows_A, int num_cols_B) {
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    if (row < num_rows_A && col < num_cols_B) {
        half sum = __float2half(0.0f);
        int startA = A_rows[row];
        int endA = A_rows[row + 1];
        int startB = B_rows[col];
        int endB = B_rows[col + 1];

        while (startA < endA && startB < endB) {
            if (A_cols[startA] < B_cols[startB]) {
                startA++;
            } else if (A_cols[startA] > B_cols[startB]) {
                startB++;
            } else {
                sum += A_vals[startA] * B_vals[startB];
                startA++;
                startB++;
            }
        }
        if (__half2float(sum) != 0.0f) {
            int pos = atomicAdd(&C_rows[row], 1);
            C_vals[pos] = sum;
            C_cols[pos] = col;
        }
    }
}

int main() {
    // Initialize CUDA
    hipError_t err;
    int num_devices;
    hipGetDeviceCount(&num_devices);
    if (num_devices < 1) {
        std::cerr << "No CUDA devices found!" << std::endl;
        return -1;
    }

    // Initialize data for sparse matrices A and B
    // For demonstration, we will use small matrices
    // A is a 4x4 matrix with 128 non-zero elements (repeated for demonstration)
    // B is a 4x4 matrix with 128 non-zero elements (repeated for demonstration)
    int num_rows_A = 4, num_cols_A = 4, num_rows_B = 4, num_cols_B = 4;
    int nnz_A = NNZ, nnz_B = NNZ;

    // Allocate Unified Memory for A and B
    half* A_vals, *B_vals, *C_vals;
    int* A_cols, *A_rows, *B_cols, *B_rows, *C_cols, *C_rows;
    err = hipMallocManaged(&A_vals, nnz_A * sizeof(half));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for A_vals" << std::endl; return -1; }
    err = hipMallocManaged(&A_cols, nnz_A * sizeof(int));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for A_cols" << std::endl; return -1; }
    err = hipMallocManaged(&A_rows, (num_rows_A + 1) * sizeof(int));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for A_rows" << std::endl; return -1; }
    err = hipMallocManaged(&B_vals, nnz_B * sizeof(half));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for B_vals" << std::endl; return -1; }
    err = hipMallocManaged(&B_cols, nnz_B * sizeof(int));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for B_cols" << std::endl; return -1; }
    err = hipMallocManaged(&B_rows, (num_cols_B + 1) * sizeof(int));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for B_rows" << std::endl; return -1; }

    // Initialize A and B (for demonstration purposes, we fill with dummy data)
    for (int i = 0; i < nnz_A; i++) {
        A_vals[i] = __float2half(1.0f);
        A_cols[i] = i % num_cols_A;
    }
    for (int i = 0; i <= num_rows_A; i++) {
        A_rows[i] = i * (nnz_A / num_rows_A);
    }
    for (int i = 0; i < nnz_B; i++) {
        B_vals[i] = __float2half(1.0f);
        B_cols[i] = i % num_cols_B;
    }
    for (int i = 0; i <= num_cols_B; i++) {
        B_rows[i] = i * (nnz_B / num_cols_B);
    }

    // Allocate Unified Memory for C
    int max_nnz_C = num_rows_A * num_cols_B;
    err = hipMallocManaged(&C_vals, max_nnz_C * sizeof(half));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for C_vals" << std::endl; return -1; }
    err = hipMallocManaged(&C_cols, max_nnz_C * sizeof(int));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for C_cols" << std::endl; return -1; }
    err = hipMallocManaged(&C_rows, (num_rows_A + 1) * sizeof(int));
    if (err != hipSuccess) { std::cerr << "Failed to allocate memory for C_rows" << std::endl; return -1; }

    // Initialize C_rows to 0
    for (int i = 0; i <= num_rows_A; i++) {
        C_rows[i] = 0;
    }

    // Define grid and block sizes
    dim3 blockSize(16, 16);
    dim3 gridSize((num_cols_B + blockSize.x - 1) / blockSize.x, (num_rows_A + blockSize.y - 1) / blockSize.y);

    // Launch the kernel
    sparseTensorMultiply<<<gridSize, blockSize>>>(A_vals, A_cols, A_rows, B_vals, B_cols, B_rows, C_vals, C_cols, C_rows, num_rows_A, num_cols_B);
    err = hipGetLastError();
    if (err != hipSuccess) { std::cerr << "Kernel launch failed: " << hipGetErrorString(err) << std::endl; return -1; }

    // Wait for GPU to finish before accessing on host
    err = hipDeviceSynchronize();
    if (err != hipSuccess) { std::cerr << "Failed to synchronize: " << hipGetErrorString(err) << std::endl; return -1; }

    // Output results
    int nnz_C = C_rows[num_rows_A];
    std::cout << "Resultant Sparse Matrix C (Non-zero elements: " << nnz_C << "):" << std::endl;
    for (int i = 0; i < nnz_C; i++) {
        std::cout << "C[" << C_rows[i / num_cols_B] << "][" << C_cols[i] << "] = " << __half2float(C_vals[i]) << std::endl;
    }

    // Free memory
    hipFree(A_vals); hipFree(A_cols); hipFree(A_rows);
    hipFree(B_vals); hipFree(B_cols); hipFree(B_rows);
    hipFree(C_vals); hipFree(C_cols); hipFree(C_rows);

    return 0;
}
	.text
	.file	"cuda_code_019413.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii # -- Begin function _Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.type	_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii,@function
_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii: # @_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, .Lfunc_end0-_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	76(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$0, (%rbx)
	jle	.LBB1_3
# %bb.1:
	leaq	64(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_4
# %bb.2:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	jmp	.LBB1_10
.LBB1_3:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$22, %edx
	jmp	.LBB1_11
.LBB1_4:
	leaq	40(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_6
# %bb.5:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.2, %esi
	jmp	.LBB1_10
.LBB1_6:
	leaq	32(%rsp), %rdi
	movl	$20, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_8
# %bb.7:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	jmp	.LBB1_10
.LBB1_8:
	leaq	56(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_14
# %bb.9:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.4, %esi
.LBB1_10:
	movl	$36, %edx
.LBB1_11:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_12:
	movl	$-1, %eax
.LBB1_13:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB1_14:
	.cfi_def_cfa_offset 112
	leaq	24(%rsp), %rdi
	movl	$512, %esi                      # imm = 0x200
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_16
# %bb.15:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.5, %esi
	jmp	.LBB1_32
.LBB1_16:
	leaq	16(%rsp), %rdi
	movl	$20, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_18
# %bb.17:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.6, %esi
	jmp	.LBB1_32
.LBB1_18:                               # %.preheader104.preheader
	xorl	%eax, %eax
.LBB1_19:                               # %.preheader104
                                        # =>This Inner Loop Header: Depth=1
	movq	64(%rsp), %rcx
	movw	$15360, (%rcx,%rax,2)           # imm = 0x3C00
	movl	%eax, %ecx
	andl	$3, %ecx
	movq	40(%rsp), %rdx
	movl	%ecx, (%rdx,%rax,4)
	incq	%rax
	cmpq	$128, %rax
	jne	.LBB1_19
# %bb.20:                               # %.preheader103
	movq	32(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_21:                               # =>This Inner Loop Header: Depth=1
	movl	%ecx, (%rax)
	addq	$32, %rcx
	addq	$4, %rax
	cmpq	$160, %rcx
	jne	.LBB1_21
# %bb.22:                               # %.preheader102.preheader
	xorl	%eax, %eax
.LBB1_23:                               # %.preheader102
                                        # =>This Inner Loop Header: Depth=1
	movq	56(%rsp), %rcx
	movw	$15360, (%rcx,%rax,2)           # imm = 0x3C00
	movl	%eax, %ecx
	andl	$3, %ecx
	movq	24(%rsp), %rdx
	movl	%ecx, (%rdx,%rax,4)
	incq	%rax
	cmpq	$128, %rax
	jne	.LBB1_23
# %bb.24:                               # %.preheader101
	movq	16(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_25:                               # =>This Inner Loop Header: Depth=1
	movl	%ecx, (%rax)
	addq	$32, %rcx
	addq	$4, %rax
	cmpq	$160, %rcx
	jne	.LBB1_25
# %bb.26:
	leaq	48(%rsp), %rdi
	movl	$32, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_28
# %bb.27:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	jmp	.LBB1_32
.LBB1_28:
	leaq	8(%rsp), %rdi
	movl	$64, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_30
# %bb.29:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.8, %esi
	jmp	.LBB1_32
.LBB1_30:
	movq	%rsp, %rdi
	movl	$20, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB1_34
# %bb.31:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.9, %esi
.LBB1_32:
	movl	$36, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
.LBB1_33:
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB1_12
.LBB1_34:                               # %.preheader
	movq	(%rsp), %rax
	pxor	%xmm0, %xmm0
	movdqu	%xmm0, (%rax)
	movl	$0, 16(%rax)
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_36
# %bb.35:
	movq	64(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	56(%rsp), %rcx
	movq	24(%rsp), %r8
	movq	16(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$4, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB1_36:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_38
# %bb.37:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.10, %esi
	movl	$22, %edx
	jmp	.LBB1_40
.LBB1_38:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB1_41
# %bb.39:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.11, %esi
	movl	$23, %edx
.LBB1_40:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cerr, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	jmp	.LBB1_33
.LBB1_41:
	movq	(%rsp), %rax
	movl	16(%rax), %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.12, %esi
	movl	$46, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.13, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	testl	%ebx, %ebx
	jle	.LBB1_44
# %bb.42:                               # %.lr.ph.preheader
	xorl	%r15d, %r15d
.LBB1_43:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rsp), %rax
	movl	%r15d, %ecx
	andl	$-4, %ecx
	movl	(%rax,%rcx), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.15, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%rsp), %rax
	movl	(%rax,%r15,4), %esi
	movq	%r14, %rdi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.16, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	48(%rsp), %rax
	pinsrw	$0, (%rax,%r15,2), %xmm0
	callq	__extendhfsf2@PLT
	cvtss2sd	%xmm0, %xmm0
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	incq	%r15
	cmpq	%r15, %rbx
	jne	.LBB1_43
.LBB1_44:                               # %._crit_edge
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB1_13
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii,@object # @_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.section	.rodata,"a",@progbits
	.globl	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.p2align	3, 0x0
_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii:
	.quad	_Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.size	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"No CUDA devices found!"
	.size	.L.str, 23

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Failed to allocate memory for A_vals"
	.size	.L.str.1, 37

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate memory for A_cols"
	.size	.L.str.2, 37

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate memory for A_rows"
	.size	.L.str.3, 37

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate memory for B_vals"
	.size	.L.str.4, 37

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to allocate memory for B_cols"
	.size	.L.str.5, 37

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to allocate memory for B_rows"
	.size	.L.str.6, 37

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to allocate memory for C_vals"
	.size	.L.str.7, 37

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate memory for C_cols"
	.size	.L.str.8, 37

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to allocate memory for C_rows"
	.size	.L.str.9, 37

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Kernel launch failed: "
	.size	.L.str.10, 23

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Failed to synchronize: "
	.size	.L.str.11, 24

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Resultant Sparse Matrix C (Non-zero elements: "
	.size	.L.str.12, 47

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"):"
	.size	.L.str.13, 3

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"C["
	.size	.L.str.14, 3

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"]["
	.size	.L.str.15, 3

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"] = "
	.size	.L.str.16, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii"
	.size	.L__unnamed_1, 59

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii ; -- Begin function _Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.globl	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
	.p2align	8
	.type	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii,@function
_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii: ; @_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x5c
	s_load_b64 s[2:3], s[0:1], 0x48
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s4, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	v_cmp_gt_i32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_15
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b256 s[4:11], s[0:1], 0x28
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[6:7], off
	global_load_b64 v[6:7], v[8:9], off
	s_waitcnt vmcnt(1)
	v_cmp_lt_i32_e32 vcc_lo, v4, v5
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e64 s2, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_13
; %bb.2:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x18
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v8, v4
	v_mov_b32_e32 v10, v6
	s_mov_b32 s1, 0
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v11, 31, v10
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[8:9]
	v_lshlrev_b64 v[14:15], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s14, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s18, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v15, vcc_lo
	global_load_b32 v4, v[12:13], off
	global_load_b32 v6, v[14:15], off
	s_waitcnt vmcnt(0)
	v_cmpx_ge_i32_e64 v4, v6
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_9
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_cmp_le_i32_e32 vcc_lo, v4, v6
	v_add_nc_u32_e32 v4, 1, v10
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	v_lshlrev_b64 v[12:13], 1, v[8:9]
	v_lshlrev_b64 v[14:15], 1, v[10:11]
	v_add_nc_u32_e32 v8, 1, v8
	v_add_nc_u32_e32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v13, vcc_lo
	v_add_co_u32 v13, vcc_lo, s16, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v15, vcc_lo
	global_load_u16 v4, v[11:12], off
	global_load_u16 v6, v[13:14], off
	s_waitcnt vmcnt(0)
	v_fmac_f16_e32 v1, v4, v6
                                        ; implicit-def: $vgpr4
.LBB0_6:                                ; %Flow65
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_not1_saveexec_b32 s3, s3
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v10, v4
; %bb.8:                                ; %Flow66
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_9:                                ; %Flow67
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_not1_saveexec_b32 s0, s0
; %bb.10:                               ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v8, 1, v8
; %bb.11:                               ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v8, v5
	v_cmp_ge_i32_e64 s0, v10, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_3
; %bb.12:                               ; %Flow68
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_13:                               ; %Flow69
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_neq_f16_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_mov_b32_e32 v4, 1
	global_atomic_add_u32 v2, v[2:3], v4, off glc
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 1, v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b16 v[4:5], v1, off
	global_store_b32 v[2:3], v0, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii, .Lfunc_end0-_Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 688
; NumSgprs: 22
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z20sparseTensorMultiplyPK6__halfPKiS3_S1_S3_S3_PS_PiS5_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
