// graph_coloring.cu
// CUDA implementation for graph coloring with 64 nodes using persistent threads
// Target architecture: Hopper

#include <iostream>
#include <cuda_runtime.h>

#define NUM_NODES 64
#define MAX_COLOR 10 // Assuming a maximum of 10 colors

__global__ void graphColoringKernel(int* adjMatrix, int* colors, int* conflict) {
    extern __shared__ int sharedColors[];

    int tid = threadIdx.x;
    int node = blockIdx.x * blockDim.x + threadIdx.x;

    if (node >= NUM_NODES) return;

    // Load initial color from global memory
    int myColor = colors[node];
    sharedColors[tid] = myColor;
    __syncthreads();

    // Check for conflicts
    for (int i = 0; i < NUM_NODES; ++i) {
        if (adjMatrix[node * NUM_NODES + i] == 1 && myColor == sharedColors[i]) {
            atomicAdd(conflict, 1);
        }
    }
    __syncthreads();

    // Resolve conflicts by changing color
    if (conflict[0] > 0) {
        int newColor = myColor + 1;
        while (newColor < MAX_COLOR) {
            bool hasConflict = false;
            for (int i = 0; i < NUM_NODES; ++i) {
                if (adjMatrix[node * NUM_NODES + i] == 1 && newColor == sharedColors[i]) {
                    hasConflict = true;
                    break;
                }
            }
            if (!hasConflict) {
                colors[node] = newColor;
                break;
            }
            newColor++;
        }
    }
}

int main() {
    // Adjacency matrix for the graph (64x64)
    int adjMatrix[NUM_NODES * NUM_NODES] = {0}; // Initialize with 0s
    // Example: Simple graph with 4 nodes (for demonstration, expand to 64)
    adjMatrix[0 * NUM_NODES + 1] = 1;
    adjMatrix[1 * NUM_NODES + 0] = 1;
    adjMatrix[1 * NUM_NODES + 2] = 1;
    adjMatrix[2 * NUM_NODES + 1] = 1;
    adjMatrix[2 * NUM_NODES + 3] = 1;
    adjMatrix[3 * NUM_NODES + 2] = 1;

    // Initial colors (all nodes start with color 0)
    int colors[NUM_NODES];
    for (int i = 0; i < NUM_NODES; ++i) {
        colors[i] = 0;
    }

    // Conflict flag
    int conflict = 0;

    // Allocate device memory
    int* d_adjMatrix, *d_colors, *d_conflict;
    cudaMalloc((void**)&d_adjMatrix, NUM_NODES * NUM_NODES * sizeof(int));
    cudaMalloc((void**)&d_colors, NUM_NODES * sizeof(int));
    cudaMalloc((void**)&d_conflict, sizeof(int));

    // Copy data to device
    cudaMemcpy(d_adjMatrix, adjMatrix, NUM_NODES * NUM_NODES * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_colors, colors, NUM_NODES * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_conflict, &conflict, sizeof(int), cudaMemcpyHostToDevice);

    // Kernel configuration
    int blockSize = 16; // Threads per block
    int numBlocks = (NUM_NODES + blockSize - 1) / blockSize;

    // Launch kernel
    graphColoringKernel<<<numBlocks, blockSize, blockSize * sizeof(int)>>>(d_adjMatrix, d_colors, d_conflict);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    cudaMemcpy(colors, d_colors, NUM_NODES * sizeof(int), cudaMemcpyDeviceToHost);
    cudaMemcpy(&conflict, d_conflict, sizeof(int), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_adjMatrix);
    cudaFree(d_colors);
    cudaFree(d_conflict);

    // Output the result
    std::cout << "Node colors after graph coloring:" << std::endl;
    for (int i = 0; i < NUM_NODES; ++i) {
        std::cout << "Node " << i << ": Color " << colors[i] << std::endl;
    }

    std::cout << "Conflict flag: " << conflict << std::endl;

    return 0;
}
	.file	"tmpxft_0014a1f9_00000000-6_cuda_code_056623.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z19graphColoringKernelPiS_S_PiS_S_
	.type	_Z43__device_stub__Z19graphColoringKernelPiS_S_PiS_S_, @function
_Z43__device_stub__Z19graphColoringKernelPiS_S_PiS_S_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19graphColoringKernelPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z43__device_stub__Z19graphColoringKernelPiS_S_PiS_S_, .-_Z43__device_stub__Z19graphColoringKernelPiS_S_PiS_S_
	.globl	_Z19graphColoringKernelPiS_S_
	.type	_Z19graphColoringKernelPiS_S_, @function
_Z19graphColoringKernelPiS_S_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z19graphColoringKernelPiS_S_PiS_S_
	.cfi_endproc
.LFE3661:
	.size	_Z19graphColoringKernelPiS_S_, .-_Z19graphColoringKernelPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
.LC1:
	.string	"Node colors after graph coloring:"
.LC2:
	.string	"Node "
.LC3:
	.string	": Color "
.LC4:
	.string	"Conflict flag: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	-16384(%rsp), %r11
	.cfi_def_cfa 11, 16424
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$328, %rsp
	.cfi_def_cfa_offset 16752
	movl	$4096, %ecx
	movl	$16384, %esi
	movq	%fs:40, %rax
	movq	%rax, 16696(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rbp
	leaq	4(%rsp), %r12
	leaq	312(%rsp), %rdi
	rep stosl
	movl	$64, %ecx
	movq	%rbp, %rdi
	movl	$1, 316(%rsp)
	rep stosl
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movl	$1, 568(%rsp)
	movl	$1, 576(%rsp)
	movl	$1, 828(%rsp)
	movl	$1, 836(%rsp)
	movl	$1, 1088(%rsp)
	movl	%eax, 4(%rsp)
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	leaq	312(%rsp), %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$268435457, %edx
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	salq	$4, %rdx
	salq	$2, %rdi
	movl	$64, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z43__device_stub__Z19graphColoringKernelPiS_S_PiS_S_
.L9:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L10
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L10:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%ebx, %ebx
	movl	$256, %edx
	leaq	.LC2(%rip), %r13
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$4, %edx
	leaq	_ZSt4cout(%rip), %r12
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC1(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L12:
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	0(%rbp,%rbx,4), %esi
	incq	%rbx
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpq	$64, %rbx
	jne	.L12
	leaq	.LC4(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	4(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	xorl	%eax, %eax
.L8:
	movq	16696(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$16712, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z19graphColoringKernelPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19graphColoringKernelPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// graph_coloring.cu
// CUDA implementation for graph coloring with 64 nodes using persistent threads
// Target architecture: Hopper

#include <iostream>
#include <hip/hip_runtime.h>

#define NUM_NODES 64
#define MAX_COLOR 10 // Assuming a maximum of 10 colors

__global__ void graphColoringKernel(int* adjMatrix, int* colors, int* conflict) {
    extern __shared__ int sharedColors[];

    int tid = threadIdx.x;
    int node = blockIdx.x * blockDim.x + threadIdx.x;

    if (node >= NUM_NODES) return;

    // Load initial color from global memory
    int myColor = colors[node];
    sharedColors[tid] = myColor;
    __syncthreads();

    // Check for conflicts
    for (int i = 0; i < NUM_NODES; ++i) {
        if (adjMatrix[node * NUM_NODES + i] == 1 && myColor == sharedColors[i]) {
            atomicAdd(conflict, 1);
        }
    }
    __syncthreads();

    // Resolve conflicts by changing color
    if (conflict[0] > 0) {
        int newColor = myColor + 1;
        while (newColor < MAX_COLOR) {
            bool hasConflict = false;
            for (int i = 0; i < NUM_NODES; ++i) {
                if (adjMatrix[node * NUM_NODES + i] == 1 && newColor == sharedColors[i]) {
                    hasConflict = true;
                    break;
                }
            }
            if (!hasConflict) {
                colors[node] = newColor;
                break;
            }
            newColor++;
        }
    }
}

int main() {
    // Adjacency matrix for the graph (64x64)
    int adjMatrix[NUM_NODES * NUM_NODES] = {0}; // Initialize with 0s
    // Example: Simple graph with 4 nodes (for demonstration, expand to 64)
    adjMatrix[0 * NUM_NODES + 1] = 1;
    adjMatrix[1 * NUM_NODES + 0] = 1;
    adjMatrix[1 * NUM_NODES + 2] = 1;
    adjMatrix[2 * NUM_NODES + 1] = 1;
    adjMatrix[2 * NUM_NODES + 3] = 1;
    adjMatrix[3 * NUM_NODES + 2] = 1;

    // Initial colors (all nodes start with color 0)
    int colors[NUM_NODES];
    for (int i = 0; i < NUM_NODES; ++i) {
        colors[i] = 0;
    }

    // Conflict flag
    int conflict = 0;

    // Allocate device memory
    int* d_adjMatrix, *d_colors, *d_conflict;
    hipMalloc((void**)&d_adjMatrix, NUM_NODES * NUM_NODES * sizeof(int));
    hipMalloc((void**)&d_colors, NUM_NODES * sizeof(int));
    hipMalloc((void**)&d_conflict, sizeof(int));

    // Copy data to device
    hipMemcpy(d_adjMatrix, adjMatrix, NUM_NODES * NUM_NODES * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_colors, colors, NUM_NODES * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_conflict, &conflict, sizeof(int), hipMemcpyHostToDevice);

    // Kernel configuration
    int blockSize = 16; // Threads per block
    int numBlocks = (NUM_NODES + blockSize - 1) / blockSize;

    // Launch kernel
    graphColoringKernel<<<numBlocks, blockSize, blockSize * sizeof(int)>>>(d_adjMatrix, d_colors, d_conflict);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    hipMemcpy(colors, d_colors, NUM_NODES * sizeof(int), hipMemcpyDeviceToHost);
    hipMemcpy(&conflict, d_conflict, sizeof(int), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_adjMatrix);
    hipFree(d_colors);
    hipFree(d_conflict);

    // Output the result
    std::cout << "Node colors after graph coloring:" << std::endl;
    for (int i = 0; i < NUM_NODES; ++i) {
        std::cout << "Node " << i << ": Color " << colors[i] << std::endl;
    }

    std::cout << "Conflict flag: " << conflict << std::endl;

    return 0;
}
	.text
	.file	"cuda_code_056623.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z34__device_stub__graphColoringKernelPiS_S_ # -- Begin function _Z34__device_stub__graphColoringKernelPiS_S_
	.type	_Z34__device_stub__graphColoringKernelPiS_S_,@function
_Z34__device_stub__graphColoringKernelPiS_S_: # @_Z34__device_stub__graphColoringKernelPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19graphColoringKernelPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__graphColoringKernelPiS_S_, .Lfunc_end0-_Z34__device_stub__graphColoringKernelPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$16680, %rsp                    # imm = 0x4128
	.cfi_def_cfa_offset 16736
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	288(%rsp), %rbx
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$1, %eax
	movl	%eax, 4(%rbx)
	movl	%eax, 256(%rbx)
	movl	%eax, 264(%rbx)
	movl	%eax, 516(%rbx)
	movl	%eax, 524(%rbx)
	movl	%eax, 776(%rbx)
	leaq	32(%rsp), %r15
	movl	$256, %edx                      # imm = 0x100
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	4(%rsp), %r14
	movl	$0, (%r14)
	leaq	24(%rsp), %r12
	movl	$16384, %esi                    # imm = 0x4000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r13
	movl	$256, %esi                      # imm = 0x100
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movl	$4, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$4, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	leaq	12(%rdi), %rdx
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z34__device_stub__graphColoringKernelPiS_S_
.LBB1_2:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_5
# %bb.3:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_4
# %bb.8:
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%r14, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_9
.LBB1_5:
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$33, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%ebx, %ebx
.LBB1_6:                                # =>This Inner Loop Header: Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.3, %esi
	movl	$8, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	32(%rsp,%rbx,4), %esi
	movq	%r14, %rdi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%rbx
	cmpq	$64, %rbx
	jne	.LBB1_6
# %bb.7:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	4(%rsp), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	xorl	%ebp, %ebp
	jmp	.LBB1_10
.LBB1_4:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_9:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movl	$-1, %ebp
.LBB1_10:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	%ebp, %eax
	addq	$16680, %rsp                    # imm = 0x4128
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19graphColoringKernelPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19graphColoringKernelPiS_S_,@object # @_Z19graphColoringKernelPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z19graphColoringKernelPiS_S_
	.p2align	3, 0x0
_Z19graphColoringKernelPiS_S_:
	.quad	_Z34__device_stub__graphColoringKernelPiS_S_
	.size	_Z19graphColoringKernelPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Node colors after graph coloring:"
	.size	.L.str.1, 34

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Node "
	.size	.L.str.2, 6

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	": Color "
	.size	.L.str.3, 9

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Conflict flag: "
	.size	.L.str.4, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19graphColoringKernelPiS_S_"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__graphColoringKernelPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19graphColoringKernelPiS_S_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19graphColoringKernelPiS_S_ ; -- Begin function _Z19graphColoringKernelPiS_S_
	.globl	_Z19graphColoringKernelPiS_S_
	.p2align	8
	.type	_Z19graphColoringKernelPiS_S_,@function
_Z19graphColoringKernelPiS_S_:          ; @_Z19graphColoringKernelPiS_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 64, v3
	s_cbranch_execz .LBB0_22
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshl_add_u32 v8, v0, 2, 0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s2, 0
	v_mov_b32_e32 v0, 0
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	v_lshlrev_b32_e32 v3, 6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v7, v[1:2], off
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[5:6], off
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 1, v8
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s4, s2, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s4
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v7, v8
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v8, s4, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_and_b32 s5, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s5
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s4, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s4
	global_atomic_add_u32 v0, v8, s[0:1]
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_i32 s2, s2, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s2, 0x100
	s_cbranch_scc0 .LBB0_2
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v0, v0, s[0:1]
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	s_cbranch_vccz .LBB0_22
; %bb.8:
	v_add_nc_u32_e32 v0, 1, v7
                                        ; implicit-def: $sgpr1
.LBB0_9:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	s_or_b32 s1, s1, exec_lo
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 10, v0
	s_cbranch_execz .LBB0_21
; %bb.10:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_9 Depth=1
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_mov_b32 s7, -1
	s_mov_b32 s6, 0
	s_mov_b32 s5, 0
	s_mov_b32 s12, 0
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $sgpr10
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr9
.LBB0_11:                               ; %.preheader
                                        ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v7, v[5:6], off
	s_mov_b32 s15, -1
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $sgpr13
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 1, v7
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=2
	v_mov_b32_e32 v7, s6
	s_mov_b32 s13, -1
	ds_load_b32 v7, v7
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v0, v7
	s_or_not1_b32 s15, vcc_lo, exec_lo
.LBB0_13:                               ; %Flow69
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s9, s9, exec_lo
	s_and_b32 s14, s13, exec_lo
	s_and_not1_b32 s11, s11, exec_lo
	s_or_b32 s9, s9, s14
	s_and_b32 s14, s7, exec_lo
	s_and_not1_b32 s10, s10, exec_lo
	s_and_b32 s16, s0, exec_lo
	s_mov_b32 s13, -1
	s_or_b32 s11, s11, s14
	s_or_b32 s10, s10, s16
	s_and_saveexec_b32 s14, s15
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_11 Depth=2
	s_add_i32 s15, s12, 1
	s_cmp_lt_u32 s12, 63
	v_add_co_u32 v5, vcc_lo, v5, 4
	s_cselect_b32 s16, -1, 0
	s_add_i32 s6, s6, 4
	s_cmp_eq_u32 s15, 64
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_cselect_b32 s12, -1, 0
	s_and_not1_b32 s11, s11, exec_lo
	s_and_b32 s7, s7, exec_lo
	s_and_not1_b32 s10, s10, exec_lo
	s_and_b32 s13, s16, exec_lo
	s_and_not1_b32 s9, s9, exec_lo
	s_or_b32 s11, s11, s7
	s_or_b32 s10, s10, s13
	s_or_not1_b32 s13, s12, exec_lo
	s_mov_b32 s12, s15
	s_mov_b32 s7, s16
.LBB0_15:                               ; %Flow70
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s13, exec_lo, s13
	s_or_b32 s5, s13, s5
	s_and_not1_b32 s8, s8, exec_lo
	s_and_b32 s13, s9, exec_lo
	s_and_not1_b32 s3, s3, exec_lo
	s_or_b32 s8, s8, s13
	s_and_b32 s13, s11, exec_lo
	s_and_not1_b32 s4, s4, exec_lo
	s_and_b32 s14, s10, exec_lo
	s_or_b32 s3, s3, s13
	s_or_b32 s4, s4, s14
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_11
; %bb.16:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_xor_b32 s6, s8, -1
                                        ; implicit-def: $sgpr5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s7, s6
	s_xor_b32 s6, exec_lo, s7
	s_cbranch_execz .LBB0_18
; %bb.17:                               ; %.critedge
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_and_b32 s5, s4, exec_lo
	global_store_b32 v[1:2], v0, off
.LBB0_18:                               ; %Flow
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_and_not1_saveexec_b32 s4, s6
; %bb.19:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v0, 1, v0
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s5, s3
; %bb.20:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_xor_b32 s3, s5, -1
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s3
.LBB0_21:                               ; %Flow71
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s1
	s_or_b32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_9
.LBB0_22:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19graphColoringKernelPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19graphColoringKernelPiS_S_, .Lfunc_end0-_Z19graphColoringKernelPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 800
; NumSgprs: 19
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19graphColoringKernelPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z19graphColoringKernelPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
