#include <iostream>
#include <cuda_runtime.h>
#include <cooperative_groups.h>
#include <curand_kernel.h>

namespace cg = cooperative_groups;

#define NUM_STATES 512
#define NUM_GPUS 2
#define NUM_THREADS 256

// Simulated Annealing kernel
__global__ void simulatedAnnealingKernel(curandState *states, float *energies, float temperature, float coolingRate) {
    extern __shared__ float sharedEnergies[];
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    int laneId = threadIdx.x % warpSize;
    int warpId = threadIdx.x / warpSize;
    cg::thread_block cta = cg::this_thread_block();
    cg::coalesced_group g = cg::coalesced_threads();

    // Initialize random number generator
    curandState localState = states[idx];
    float localEnergy = energies[idx];

    // Simulated Annealing logic
    for (int iter = 0; iter < 1000; ++iter) {
        // Generate a new state
        float newStateEnergy = localEnergy + (curand_uniform(&localState) - 0.5f) * 2.0f;
        float deltaEnergy = newStateEnergy - localEnergy;

        // Metropolis criterion
        if (deltaEnergy < 0 || curand_uniform(&localState) < exp(-deltaEnergy / temperature)) {
            localEnergy = newStateEnergy;
        }

        // Update temperature
        temperature *= coolingRate;
    }

    // Store local energy in shared memory
    sharedEnergies[threadIdx.x] = localEnergy;
    __syncthreads();

    // Reduce minimum energy in shared memory
    for (int s = blockDim.x / 2; s > 0; s >>= 1) {
        if (threadIdx.x < s) {
            sharedEnergies[threadIdx.x] = fminf(sharedEnergies[threadIdx.x], sharedEnergies[threadIdx.x + s]);
        }
        __syncthreads();
    }

    // Write minimum energy of the block to global memory
    if (threadIdx.x == 0) {
        energies[blockIdx.x] = sharedEnergies[0];
    }

    // Write back the random state
    states[idx] = localState;
}

void checkCudaError(cudaError_t err, const char *file, int line) {
    if (err != cudaSuccess) {
        std::cerr << file << "(" << line << "): CUDA Runtime API error " << err << ": " << cudaGetErrorString(err) << std::endl;
        exit(-1);
    }
}

#define CHECK_CUDA_ERROR(err) checkCudaError(err, __FILE__, __LINE__)

int main() {
    int deviceCount;
    cudaGetDeviceCount(&deviceCount);
    if (deviceCount < NUM_GPUS) {
        std::cerr << "Not enough GPUs available. Required: " << NUM_GPUS << ", Available: " << deviceCount << std::endl;
        return -1;
    }

    int statesPerGPU = NUM_STATES / NUM_GPUS;
    int threadsPerBlock = NUM_THREADS;
    int blocksPerGPU = (statesPerGPU + threadsPerBlock - 1) / threadsPerBlock;

    float *energies[NUM_GPUS];
    curandState *states[NUM_GPUS];
    cudaStream_t streams[NUM_GPUS];

    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        cudaSetDevice(gpu);
        cudaStreamCreate(&streams[gpu]);

        // Allocate memory for states and energies
        CHECK_CUDA_ERROR(cudaMalloc(&energies[gpu], statesPerGPU * sizeof(float)));
        CHECK_CUDA_ERROR(cudaMalloc(&states[gpu], statesPerGPU * sizeof(curandState)));

        // Initialize energies
        CHECK_CUDA_ERROR(cudaMemsetAsync(energies[gpu], 0, statesPerGPU * sizeof(float), streams[gpu]));

        // Initialize random states
        simulatedAnnealingKernel<<<blocksPerGPU, threadsPerBlock, threadsPerBlock * sizeof(float), streams[gpu]>>>(states[gpu], energies[gpu], 100.0f, 0.99f);
        CHECK_CUDA_ERROR(cudaGetLastError());
    }

    // Wait for all GPUs to finish
    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        cudaSetDevice(gpu);
        cudaStreamSynchronize(streams[gpu]);
    }

    // Find the minimum energy across all GPUs
    float minEnergy = INFINITY;
    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        cudaSetDevice(gpu);
        float *h_energies = new float[statesPerGPU];
        CHECK_CUDA_ERROR(cudaMemcpy(h_energies, energies[gpu], statesPerGPU * sizeof(float), cudaMemcpyDeviceToHost));

        for (int i = 0; i < statesPerGPU; ++i) {
            minEnergy = fminf(minEnergy, h_energies[i]);
        }

        delete[] h_energies;
    }

    std::cout << "Minimum energy found: " << minEnergy << std::endl;

    // Clean up
    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        cudaSetDevice(gpu);
        cudaFree(energies[gpu]);
        cudaFree(states[gpu]);
        cudaStreamDestroy(streams[gpu]);
    }

    return 0;
}
	.file	"tmpxft_000d5c43_00000000-6_cuda_code_045621.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB7039:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE7039:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"("
.LC1:
	.string	"): CUDA Runtime API error "
.LC2:
	.string	": "
	.text
	.globl	_Z14checkCudaError9cudaErrorPKci
	.type	_Z14checkCudaError9cudaErrorPKci, @function
_Z14checkCudaError9cudaErrorPKci:
.LFB7035:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE7035:
	.size	_Z14checkCudaError9cudaErrorPKci, .-_Z14checkCudaError9cudaErrorPKci
	.globl	_Z66__device_stub__Z24simulatedAnnealingKernelP17curandStateXORWOWPfffP17curandStateXORWOWPfff
	.type	_Z66__device_stub__Z24simulatedAnnealingKernelP17curandStateXORWOWPfffP17curandStateXORWOWPfff, @function
_Z66__device_stub__Z24simulatedAnnealingKernelP17curandStateXORWOWPfffP17curandStateXORWOWPfff:
.LFB7061:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	40(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	56(%rsp), %rdi
	leaq	68(%rsp), %rsi
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7061:
	.size	_Z66__device_stub__Z24simulatedAnnealingKernelP17curandStateXORWOWPfffP17curandStateXORWOWPfff, .-_Z66__device_stub__Z24simulatedAnnealingKernelP17curandStateXORWOWPfffP17curandStateXORWOWPfff
	.globl	_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff
	.type	_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff, @function
_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff:
.LFB7062:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z24simulatedAnnealingKernelP17curandStateXORWOWPfffP17curandStateXORWOWPfff
	.cfi_endproc
.LFE7062:
	.size	_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff, .-_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff
	.section	.rodata.str1.1
.LC4:
	.string	"Not enough GPUs available. Required: "
.LC5:
	.string	", Available: "
.LC6:
	.string	"/home/ubuntu/Datasets/cuda-codes-80k-from-llm-dedup/cuda_code_045621.cu"
.LC9:
	.string	"Minimum energy found: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB7036:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
	cmpl	$1, 28(%rsp)
	jg	.L14
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$2, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	28(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L13
.L14:
	leaq	56(%rsp), %rbx
	leaq	88(%rsp), %r13
	xorl	%r15d, %r15d
	leaq	72(%rsp), %r14
	movq	%rbx, %r12
	leaq	.LC6(%rip), %rbp
.L17:
	movl	%r15d, %edi
	call	cudaSetDevice@PLT
	movq	%r13, %rdi
	call	cudaStreamCreate@PLT
	movl	$1024, %esi
	movq	%rbx, %rdi
	call	cudaMalloc@PLT
	movl	$91, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movl	$12288, %esi
	movq	%r14, %rdi
	call	cudaMalloc@PLT
	movl	$92, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movq	0(%r13), %rcx
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	movl	$1024, %edx
	call	cudaMemsetAsync@PLT
	movl	$95, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movl	$16777217, %edx
	movq	0(%r13), %r9
	movabsq	$4294967297, %rdi
	salq	$8, %rdx
	movl	$1024, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movss	.LC7(%rip), %xmm1
	movss	.LC8(%rip), %xmm0
	movq	(%rbx), %rsi
	movq	(%r14), %rdi
	call	_Z66__device_stub__Z24simulatedAnnealingKernelP17curandStateXORWOWPfffP17curandStateXORWOWPfff
.L16:
	call	cudaGetLastError@PLT
	movl	$99, %edx
	movq	%rbp, %rsi
	addq	$8, %r13
	movl	%eax, %edi
	addq	$8, %rbx
	addq	$8, %r14
	call	_Z14checkCudaError9cudaErrorPKci
	testl	%r15d, %r15d
	jne	.L25
	movl	$1, %r15d
	jmp	.L17
.L25:
	xorl	%edi, %edi
	xorl	%r13d, %r13d
	call	cudaSetDevice@PLT
	movq	88(%rsp), %rdi
	call	cudaStreamSynchronize@PLT
	movl	$1, %edi
	call	cudaSetDevice@PLT
	movq	96(%rsp), %rdi
	call	cudaStreamSynchronize@PLT
	movss	.LC3(%rip), %xmm1
.L19:
	movl	%r13d, %edi
	movss	%xmm1, 12(%rsp)
	xorl	%r14d, %r14d
	call	cudaSetDevice@PLT
	movl	$1024, %edi
	call	_Znam@PLT
	movq	(%r12,%r13,8), %rsi
	movl	$2, %ecx
	movl	$1024, %edx
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movl	$113, %edx
	movq	%rbp, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movss	12(%rsp), %xmm1
.L18:
	movss	(%rbx,%r14,4), %xmm0
	incq	%r14
	call	fminf@PLT
	movaps	%xmm0, %xmm1
	cmpq	$256, %r14
	jne	.L18
	movq	%rbx, %rdi
	movss	%xmm0, 12(%rsp)
	call	_ZdaPv@PLT
	testq	%r13, %r13
	movss	12(%rsp), %xmm1
	jne	.L26
	movl	$1, %r13d
	jmp	.L19
.L26:
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	12(%rsp), %xmm1
	movq	%rax, %rdi
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movl	$1, %edi
	call	cudaSetDevice@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	xorl	%eax, %eax
.L13:
	movq	104(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7036:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff"
.LC11:
	.string	"precalc_xorwow_matrix"
.LC12:
	.string	"precalc_xorwow_offset_matrix"
.LC13:
	.string	"mrg32k3aM1"
.LC14:
	.string	"mrg32k3aM2"
.LC15:
	.string	"mrg32k3aM1SubSeq"
.LC16:
	.string	"mrg32k3aM2SubSeq"
.LC17:
	.string	"mrg32k3aM1Seq"
.LC18:
	.string	"mrg32k3aM2Seq"
.LC19:
	.string	"__cr_lgamma_table"
.LC20:
	.string	"_ZN50_INTERNAL_9c54650a_19_cuda_code_045621_cu_a41044784cuda3std3__419piecewise_constructE"
.LC21:
	.string	"_ZN50_INTERNAL_9c54650a_19_cuda_code_045621_cu_a41044784cuda3std6ranges3__45__cpo4swapE"
.LC22:
	.string	"_ZN50_INTERNAL_9c54650a_19_cuda_code_045621_cu_a41044784cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB7064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z24simulatedAnnealingKernelP17curandStateXORWOWPfff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE7064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	2139095040
	.align 4
.LC7:
	.long	1065185444
	.align 4
.LC8:
	.long	1120403456
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
#include <hiprand/hiprand_kernel.h>

namespace cg = cooperative_groups;

#define NUM_STATES 512
#define NUM_GPUS 2
#define NUM_THREADS 256

// Simulated Annealing kernel
__global__ void simulatedAnnealingKernel(hiprandState *states, float *energies, float temperature, float coolingRate) {
    extern __shared__ float sharedEnergies[];
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    int laneId = threadIdx.x % warpSize;
    int warpId = threadIdx.x / warpSize;
    cg::thread_block cta = cg::this_thread_block();
    cg::coalesced_group g = cg::coalesced_threads();

    // Initialize random number generator
    hiprandState localState = states[idx];
    float localEnergy = energies[idx];

    // Simulated Annealing logic
    for (int iter = 0; iter < 1000; ++iter) {
        // Generate a new state
        float newStateEnergy = localEnergy + (hiprand_uniform(&localState) - 0.5f) * 2.0f;
        float deltaEnergy = newStateEnergy - localEnergy;

        // Metropolis criterion
        if (deltaEnergy < 0 || hiprand_uniform(&localState) < exp(-deltaEnergy / temperature)) {
            localEnergy = newStateEnergy;
        }

        // Update temperature
        temperature *= coolingRate;
    }

    // Store local energy in shared memory
    sharedEnergies[threadIdx.x] = localEnergy;
    __syncthreads();

    // Reduce minimum energy in shared memory
    for (int s = blockDim.x / 2; s > 0; s >>= 1) {
        if (threadIdx.x < s) {
            sharedEnergies[threadIdx.x] = fminf(sharedEnergies[threadIdx.x], sharedEnergies[threadIdx.x + s]);
        }
        __syncthreads();
    }

    // Write minimum energy of the block to global memory
    if (threadIdx.x == 0) {
        energies[blockIdx.x] = sharedEnergies[0];
    }

    // Write back the random state
    states[idx] = localState;
}

void checkCudaError(hipError_t err, const char *file, int line) {
    if (err != hipSuccess) {
        std::cerr << file << "(" << line << "): CUDA Runtime API error " << err << ": " << hipGetErrorString(err) << std::endl;
        exit(-1);
    }
}

#define CHECK_CUDA_ERROR(err) checkCudaError(err, __FILE__, __LINE__)

int main() {
    int deviceCount;
    hipGetDeviceCount(&deviceCount);
    if (deviceCount < NUM_GPUS) {
        std::cerr << "Not enough GPUs available. Required: " << NUM_GPUS << ", Available: " << deviceCount << std::endl;
        return -1;
    }

    int statesPerGPU = NUM_STATES / NUM_GPUS;
    int threadsPerBlock = NUM_THREADS;
    int blocksPerGPU = (statesPerGPU + threadsPerBlock - 1) / threadsPerBlock;

    float *energies[NUM_GPUS];
    hiprandState *states[NUM_GPUS];
    hipStream_t streams[NUM_GPUS];

    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        hipSetDevice(gpu);
        hipStreamCreate(&streams[gpu]);

        // Allocate memory for states and energies
        CHECK_CUDA_ERROR(hipMalloc(&energies[gpu], statesPerGPU * sizeof(float)));
        CHECK_CUDA_ERROR(hipMalloc(&states[gpu], statesPerGPU * sizeof(hiprandState)));

        // Initialize energies
        CHECK_CUDA_ERROR(hipMemsetAsync(energies[gpu], 0, statesPerGPU * sizeof(float), streams[gpu]));

        // Initialize random states
        simulatedAnnealingKernel<<<blocksPerGPU, threadsPerBlock, threadsPerBlock * sizeof(float), streams[gpu]>>>(states[gpu], energies[gpu], 100.0f, 0.99f);
        CHECK_CUDA_ERROR(hipGetLastError());
    }

    // Wait for all GPUs to finish
    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        hipSetDevice(gpu);
        hipStreamSynchronize(streams[gpu]);
    }

    // Find the minimum energy across all GPUs
    float minEnergy = INFINITY;
    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        hipSetDevice(gpu);
        float *h_energies = new float[statesPerGPU];
        CHECK_CUDA_ERROR(hipMemcpy(h_energies, energies[gpu], statesPerGPU * sizeof(float), hipMemcpyDeviceToHost));

        for (int i = 0; i < statesPerGPU; ++i) {
            minEnergy = fminf(minEnergy, h_energies[i]);
        }

        delete[] h_energies;
    }

    std::cout << "Minimum energy found: " << minEnergy << std::endl;

    // Clean up
    for (int gpu = 0; gpu < NUM_GPUS; ++gpu) {
        hipSetDevice(gpu);
        hipFree(energies[gpu]);
        hipFree(states[gpu]);
        hipStreamDestroy(streams[gpu]);
    }

    return 0;
}
	.text
	.file	"cuda_code_045621.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff # -- Begin function _Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff
	.type	_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff,@function
_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff: # @_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	8(%rsp), %rsi
	movss	%xmm1, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rsi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24simulatedAnnealingKernelP12hiprandStatePfff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff, .Lfunc_end0-_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff
	.cfi_endproc
                                        # -- End function
	.globl	_Z14checkCudaError10hipError_tPKci # -- Begin function _Z14checkCudaError10hipError_tPKci
	.type	_Z14checkCudaError10hipError_tPKci,@function
_Z14checkCudaError10hipError_tPKci:     # @_Z14checkCudaError10hipError_tPKci
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB1_2
# %bb.1:
	retq
.LBB1_2:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%edi, %ebx
	movl	$_ZSt4cerr, %edi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z14checkCudaError10hipError_tPKci, .Lfunc_end1-_Z14checkCudaError10hipError_tPKci
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x42c80000                      # float 100
.LCPI2_1:
	.long	0x3f7d70a4                      # float 0.990000009
.LCPI2_2:
	.long	0x7f800000                      # float +Inf
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	12(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$1, (%rbx)
	jg	.LBB2_2
# %bb.1:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	movl	$37, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	$2, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.4, %esi
	movl	$13, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	12(%rsp), %esi
	movq	%rbx, %rdi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
	jmp	.LBB2_12
.LBB2_2:
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	movb	$1, %bpl
	xorl	%r13d, %r13d
	leaq	255(%rbx), %r14
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movl	%r13d, %edi
	callq	hipSetDevice
	leaq	(%rsp,%r13,8), %r12
	addq	$16, %r12
	movq	%r12, %rdi
	callq	hipStreamCreate
	leaq	(%rsp,%r13,8), %r15
	addq	$32, %r15
	movl	$1024, %esi                     # imm = 0x400
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$91, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	leaq	(%rsp,%r13,8), %r13
	addq	$48, %r13
	movl	$12288, %esi                    # imm = 0x3000
	movq	%r13, %rdi
	callq	hipMalloc
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$92, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movq	(%r15), %rdi
	movq	(%r12), %rcx
	movl	$1024, %edx                     # imm = 0x400
	xorl	%esi, %esi
	callq	hipMemsetAsync
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$95, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movq	(%r12), %r9
	movl	$1024, %r8d                     # imm = 0x400
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_3 Depth=1
	movq	(%r13), %rdi
	movq	(%r15), %rsi
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	callq	_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff
.LBB2_5:                                #   in Loop: Header=BB2_3 Depth=1
	callq	hipGetLastError
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$99, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movl	$1, %r13d
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB2_3
# %bb.6:                                # %.preheader56
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	hipSetDevice
	movq	16(%rsp), %rdi
	callq	hipStreamSynchronize
	movl	$1, %edi
	callq	hipSetDevice
	movq	24(%rsp), %rdi
	callq	hipStreamSynchronize
	movss	.LCPI2_2(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movb	$1, %bpl
.LBB2_7:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_8 Depth 2
	movl	%ebx, %edi
	callq	hipSetDevice
	movl	$1024, %edi                     # imm = 0x400
	callq	_Znam
	movq	%rax, %r14
	movq	32(%rsp,%rbx,8), %rsi
	movl	$1024, %edx                     # imm = 0x400
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	movl	$113, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	xorl	%eax, %eax
	movss	8(%rsp), %xmm3                  # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm0
.LBB2_8:                                #   Parent Loop BB2_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r14,%rax,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	cmpunordss	%xmm0, %xmm0
	movaps	%xmm0, %xmm2
	andps	%xmm1, %xmm2
	minss	%xmm3, %xmm1
	andnps	%xmm1, %xmm0
	orps	%xmm2, %xmm0
	movaps	%xmm0, %xmm3
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB2_8
# %bb.9:                                #   in Loop: Header=BB2_7 Depth=1
	movss	%xmm3, 8(%rsp)                  # 4-byte Spill
	movq	%r14, %rdi
	callq	_ZdaPv
	movl	$1, %ebx
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB2_7
# %bb.10:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movb	$1, %bpl
	xorl	%ebx, %ebx
.LBB2_11:                               # =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	hipSetDevice
	movq	32(%rsp,%rbx,8), %rdi
	callq	hipFree
	movq	48(%rsp,%rbx,8), %rdi
	callq	hipFree
	movq	16(%rsp,%rbx,8), %rdi
	callq	hipStreamDestroy
	movl	$1, %ebx
	xorl	%eax, %eax
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB2_11
.LBB2_12:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24simulatedAnnealingKernelP12hiprandStatePfff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24simulatedAnnealingKernelP12hiprandStatePfff,@object # @_Z24simulatedAnnealingKernelP12hiprandStatePfff
	.section	.rodata,"a",@progbits
	.globl	_Z24simulatedAnnealingKernelP12hiprandStatePfff
	.p2align	3, 0x0
_Z24simulatedAnnealingKernelP12hiprandStatePfff:
	.quad	_Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff
	.size	_Z24simulatedAnnealingKernelP12hiprandStatePfff, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"("
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"): CUDA Runtime API error "
	.size	.L.str.1, 27

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	": "
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Not enough GPUs available. Required: "
	.size	.L.str.3, 38

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	", Available: "
	.size	.L.str.4, 14

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"/home/ubuntu/Datasets/hip-codes-80k-from-llm-dedup-disassemble-sm89/cuda_code_045621.hip"
	.size	.L.str.5, 89

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Minimum energy found: "
	.size	.L.str.6, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z24simulatedAnnealingKernelP12hiprandStatePfff"
	.size	.L__unnamed_1, 48

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__simulatedAnnealingKernelP12hiprandStatePfff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24simulatedAnnealingKernelP12hiprandStatePfff
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24simulatedAnnealingKernelP12hiprandStatePfff ; -- Begin function _Z24simulatedAnnealingKernelP12hiprandStatePfff
	.globl	_Z24simulatedAnnealingKernelP12hiprandStatePfff
	.p2align	8
	.type	_Z24simulatedAnnealingKernelP12hiprandStatePfff,@function
_Z24simulatedAnnealingKernelP12hiprandStatePfff: ; @_Z24simulatedAnnealingKernelP12hiprandStatePfff
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	v_mad_i64_i32 v[9:10], null, v1, 48, s[4:5]
	s_clause 0x1
	global_load_b64 v[11:12], v[9:10], off offset:40
	global_load_b128 v[5:8], v[9:10], off offset:24
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_mov_b32_e32 v15, s0
	s_movk_i32 s0, 0x3e8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	s_clause 0x2
	global_load_b32 v17, v[9:10], off
	global_load_b128 v[18:21], v[9:10], off offset:4
	global_load_b32 v3, v[9:10], off offset:20
	global_load_b32 v16, v[1:2], off
	v_add_co_u32 v13, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	s_waitcnt vmcnt(2)
	scratch_store_b128 off, v[18:21], off offset:4
	s_waitcnt vmcnt(1)
	scratch_store_b32 off, v3, off offset:20
	v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v6, v11
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v2, 2, v5
	v_lshlrev_b32_e32 v3, 4, v6
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v5
	v_add_nc_u32_e32 v5, 0x587c5, v17
	v_lshlrev_b32_e32 v4, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v4
	v_mov_b32_e32 v4, v6
	v_xor3_b32 v19, v3, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v3, v8 :: v_dual_add_nc_u32 v2, v19, v5
	v_mov_b32_e32 v11, v19
	v_cvt_f32_u32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, 0x2f800000, v2, 0x2f800000
	v_add_f32_e32 v2, -0.5, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 2.0, v2, v16
	v_mov_b32_e32 v2, v7
	v_sub_f32_e32 v20, v18, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0, v20
	s_cbranch_execz .LBB0_5
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_div_scale_f32 v2, null, v15, v15, -v20
	v_div_scale_f32 v5, vcc_lo, -v20, v15, -v20
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v5, v3
	v_fma_f32 v11, -v2, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v11, v3
	v_fma_f32 v2, -v2, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v2, v2, v3, v4
	v_lshrrev_b32_e32 v4, 2, v1
	v_div_fixup_f32 v2, v2, v15, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v4, v1
	v_dual_mul_f32 v3, 0x3fb8aa3b, v2 :: v_dual_lshlrev_b32 v4, 4, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v11, 1, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	v_fma_f32 v5, 0x3fb8aa3b, v2, -v3
	v_rndne_f32_e32 v20, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v11, v4
	v_fmac_f32_e32 v5, 0x32a5705f, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v3, v20
	v_xor3_b32 v11, v4, v1, v19
	v_cvt_i32_f32_e32 v1, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, 0xb0f8a, v17
	v_exp_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v5
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v3, v1
	v_cvt_f32_u32_e32 v3, v4
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_f32_e32 v3, v1
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v16, v18
; %bb.4:                                ; %Flow111
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_dual_mov_b32 v4, v19 :: v_dual_mov_b32 v3, v6
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v1, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v18, v16
.LBB0_5:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_mul_f32_e32 v15, s1, v15
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v16, v18 :: v_dual_mov_b32 v17, v5
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v8, v4
	v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v6, v11
	v_mov_b32_e32 v7, v3
	s_branch .LBB0_1
.LBB0_7:
	v_lshl_add_u32 v6, v0, 2, 0
	s_cmp_lt_u32 s3, 2
	ds_store_b32 v6, v18
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
.LBB0_8:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_12
; %bb.9:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_lshr_b32 s0, s3, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=1
	v_lshl_add_u32 v7, s0, 2, v6
	ds_load_b32 v7, v7
	ds_load_b32 v8, v6
	s_waitcnt lgkmcnt(0)
	v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v8, v8, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_min_f32_e32 v7, v8, v7
	ds_store_b32 v6, v7
.LBB0_11:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s3, 4
	s_mov_b32 s3, s0
	s_branch .LBB0_8
.LBB0_12:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_u32 s2, s6, s2
	ds_load_b32 v6, v0
	s_addc_u32 s3, s7, s3
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v6, s[2:3]
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_clause 0x1
	scratch_load_b32 v0, off, off offset:20
	scratch_load_b128 v[15:18], off, off offset:4
	s_clause 0x1
	global_store_b32 v[9:10], v5, off
	global_store_b128 v[9:10], v[1:4], off offset:24
	s_waitcnt vmcnt(1)
	global_store_b32 v[13:14], v0, off offset:16
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b128 v[13:14], v[15:18], off
	global_store_b64 v[9:10], v[11:12], off offset:40
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24simulatedAnnealingKernelP12hiprandStatePfff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 24
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24simulatedAnnealingKernelP12hiprandStatePfff, .Lfunc_end0-_Z24simulatedAnnealingKernelP12hiprandStatePfff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 976
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 24
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24simulatedAnnealingKernelP12hiprandStatePfff
    .private_segment_fixed_size: 24
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24simulatedAnnealingKernelP12hiprandStatePfff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
