#include <iostream>
#include <cuda_runtime.h>

// Define the size of the matrix
#define N 1024

// Define the relaxation factor for SOR
#define OMEGA 1.25

// Kernel to perform the SOR iteration
__global__ void sor_kernel(float* d_A, float* d_b, float* d_x, float* d_x_new) {
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    if (row < N && col < N) {
        if (row == col) {
            // Diagonal element
            d_x_new[row] = d_b[row];
            for (int j = 0; j < N; j++) {
                if (j != row) {
                    d_x_new[row] -= d_A[row * N + j] * d_x[j];
                }
            }
            d_x_new[row] = (1 - OMEGA) * d_x[row] + (OMEGA / d_A[row * N + row]) * d_x_new[row];
        }
    }
}

// Function to initialize matrix A and vector b
void initialize(float* A, float* b) {
    for (int i = 0; i < N; i++) {
        b[i] = 1.0f;
        for (int j = 0; j < N; j++) {
            if (i == j) {
                A[i * N + j] = 4.0f;
            } else if (abs(i - j) == 1) {
                A[i * N + j] = -1.0f;
            } else {
                A[i * N + j] = 0.0f;
            }
        }
    }
}

int main() {
    // Declare pointers for matrix A, vector b, and solution vector x
    float* d_A;
    float* d_b;
    float* d_x;
    float* d_x_new;

    // Allocate Unified Memory – accessible from CPU or GPU
    cudaMallocManaged(&d_A, N * N * sizeof(float));
    cudaMallocManaged(&d_b, N * sizeof(float));
    cudaMallocManaged(&d_x, N * sizeof(float));
    cudaMallocManaged(&d_x_new, N * sizeof(float));

    // Initialize matrix A and vector b
    initialize(d_A, d_b);

    // Initialize solution vector x
    for (int i = 0; i < N; i++) {
        d_x[i] = 0.0f;
    }

    // Define block and grid sizes
    dim3 blockSize(16, 16);
    dim3 gridSize((N + blockSize.x - 1) / blockSize.x, (N + blockSize.y - 1) / blockSize.y);

    // Perform 100 iterations of SOR
    for (int iter = 0; iter < 100; iter++) {
        sor_kernel<<<gridSize, blockSize>>>(d_A, d_b, d_x, d_x_new);
        cudaDeviceSynchronize(); // Ensure all threads have completed

        // Swap d_x and d_x_new for the next iteration
        float* temp = d_x;
        d_x = d_x_new;
        d_x_new = temp;
    }

    // Output the first and last element of the solution vector
    std::cout << "x[0] = " << d_x[0] << ", x[" << N - 1 << "] = " << d_x[N - 1] << std::endl;

    // Free memory
    cudaFree(d_A);
    cudaFree(d_b);
    cudaFree(d_x);
    cudaFree(d_x_new);

    return 0;
}
	.file	"tmpxft_001b200c_00000000-6_cuda_code_058832.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10initializePfS_
	.type	_Z10initializePfS_, @function
_Z10initializePfS_:
.LFB3635:
	.cfi_startproc
	endbr64
	movss	.LC3(%rip), %xmm1
	xorl	%eax, %eax
.L5:
	movq	%rax, %rcx
	movss	%xmm1, (%rsi,%rax,4)
	movl	%eax, %r10d
	xorl	%edx, %edx
	salq	$12, %rcx
	addq	%rdi, %rcx
.L4:
	movss	.LC0(%rip), %xmm0
	cmpl	%edx, %eax
	je	.L3
	movl	%r10d, %r9d
	movss	.LC1(%rip), %xmm0
	subl	%edx, %r9d
	movl	%r9d, %r8d
	negl	%r8d
	cmovs	%r9d, %r8d
	decl	%r8d
	je	.L3
	xorps	%xmm0, %xmm0
.L3:
	movss	%xmm0, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	$1024, %rdx
	jne	.L4
	incq	%rax
	cmpq	$1024, %rax
	jne	.L5
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z10initializePfS_, .-_Z10initializePfS_
	.globl	_Z36__device_stub__Z10sor_kernelPfS_S_S_PfS_S_S_
	.type	_Z36__device_stub__Z10sor_kernelPfS_S_S_PfS_S_S_, @function
_Z36__device_stub__Z10sor_kernelPfS_S_S_PfS_S_S_:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10sor_kernelPfS_S_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L11:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z36__device_stub__Z10sor_kernelPfS_S_S_PfS_S_S_, .-_Z36__device_stub__Z10sor_kernelPfS_S_S_PfS_S_S_
	.globl	_Z10sor_kernelPfS_S_S_
	.type	_Z10sor_kernelPfS_S_S_, @function
_Z10sor_kernelPfS_S_S_:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10sor_kernelPfS_S_S_PfS_S_S_
	.cfi_endproc
.LFE3662:
	.size	_Z10sor_kernelPfS_S_S_, .-_Z10sor_kernelPfS_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"x[0] = "
.LC5:
	.string	", x["
.LC6:
	.string	"] = "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1, %edx
	movl	$4194304, %esi
	movabsq	$68719476752, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	$100, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMallocManaged@PLT
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$4096, %esi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$4096, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$4096, %esi
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	call	_Z10initializePfS_
	movq	16(%rsp), %rdi
	xorl	%eax, %eax
	movl	$1024, %ecx
	movl	$1, 40(%rsp)
	rep stosl
	movl	$1, 52(%rsp)
	movabsq	$274877907008, %rax
	movq	%rax, 44(%rsp)
.L18:
	movl	40(%rsp), %ecx
	movq	44(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	52(%rsp), %esi
	movq	%rbp, %rdx
	movq	%rbp, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z36__device_stub__Z10sor_kernelPfS_S_S_PfS_S_S_
.L17:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rax
	movq	24(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	%rdx, 16(%rsp)
	decl	%ebx
	jne	.L18
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	16(%rsp), %rax
	cvtss2sd	(%rax), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1023, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	16(%rsp), %rax
	cvtss2sd	4092(%rax), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$72, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z10sor_kernelPfS_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10sor_kernelPfS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1082130432
	.align 4
.LC1:
	.long	-1082130432
	.align 4
.LC3:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

// Define the size of the matrix
#define N 1024

// Define the relaxation factor for SOR
#define OMEGA 1.25

// Kernel to perform the SOR iteration
__global__ void sor_kernel(float* d_A, float* d_b, float* d_x, float* d_x_new) {
    int row = blockIdx.y * blockDim.y + threadIdx.y;
    int col = blockIdx.x * blockDim.x + threadIdx.x;

    if (row < N && col < N) {
        if (row == col) {
            // Diagonal element
            d_x_new[row] = d_b[row];
            for (int j = 0; j < N; j++) {
                if (j != row) {
                    d_x_new[row] -= d_A[row * N + j] * d_x[j];
                }
            }
            d_x_new[row] = (1 - OMEGA) * d_x[row] + (OMEGA / d_A[row * N + row]) * d_x_new[row];
        }
    }
}

// Function to initialize matrix A and vector b
void initialize(float* A, float* b) {
    for (int i = 0; i < N; i++) {
        b[i] = 1.0f;
        for (int j = 0; j < N; j++) {
            if (i == j) {
                A[i * N + j] = 4.0f;
            } else if (abs(i - j) == 1) {
                A[i * N + j] = -1.0f;
            } else {
                A[i * N + j] = 0.0f;
            }
        }
    }
}

int main() {
    // Declare pointers for matrix A, vector b, and solution vector x
    float* d_A;
    float* d_b;
    float* d_x;
    float* d_x_new;

    // Allocate Unified Memory – accessible from CPU or GPU
    hipMallocManaged(&d_A, N * N * sizeof(float));
    hipMallocManaged(&d_b, N * sizeof(float));
    hipMallocManaged(&d_x, N * sizeof(float));
    hipMallocManaged(&d_x_new, N * sizeof(float));

    // Initialize matrix A and vector b
    initialize(d_A, d_b);

    // Initialize solution vector x
    for (int i = 0; i < N; i++) {
        d_x[i] = 0.0f;
    }

    // Define block and grid sizes
    dim3 blockSize(16, 16);
    dim3 gridSize((N + blockSize.x - 1) / blockSize.x, (N + blockSize.y - 1) / blockSize.y);

    // Perform 100 iterations of SOR
    for (int iter = 0; iter < 100; iter++) {
        sor_kernel<<<gridSize, blockSize>>>(d_A, d_b, d_x, d_x_new);
        hipDeviceSynchronize(); // Ensure all threads have completed

        // Swap d_x and d_x_new for the next iteration
        float* temp = d_x;
        d_x = d_x_new;
        d_x_new = temp;
    }

    // Output the first and last element of the solution vector
    std::cout << "x[0] = " << d_x[0] << ", x[" << N - 1 << "] = " << d_x[N - 1] << std::endl;

    // Free memory
    hipFree(d_A);
    hipFree(d_b);
    hipFree(d_x);
    hipFree(d_x_new);

    return 0;
}
	.text
	.file	"cuda_code_058832.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__sor_kernelPfS_S_S_ # -- Begin function _Z25__device_stub__sor_kernelPfS_S_S_
	.type	_Z25__device_stub__sor_kernelPfS_S_S_,@function
_Z25__device_stub__sor_kernelPfS_S_S_:  # @_Z25__device_stub__sor_kernelPfS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10sor_kernelPfS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__sor_kernelPfS_S_S_, .Lfunc_end0-_Z25__device_stub__sor_kernelPfS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z10initializePfS_              # -- Begin function _Z10initializePfS_
	.type	_Z10initializePfS_,@function
_Z10initializePfS_:                     # @_Z10initializePfS_
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
	movq	%rdi, %rcx
	xorl	%edx, %edx
.LBB1_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	movl	$1065353216, (%rsi,%rdx,4)      # imm = 0x3F800000
	movq	%rdx, %r8
	shlq	$10, %r8
	addq	%rdx, %r8
	movl	%edx, %r9d
	xorl	%r10d, %r10d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%r10, %rax
	jne	.LBB1_6
# %bb.3:                                #   in Loop: Header=BB1_2 Depth=2
	movl	$1082130432, (%rdi,%r8,4)       # imm = 0x40800000
	jmp	.LBB1_9
.LBB1_6:                                #   in Loop: Header=BB1_2 Depth=2
	leal	1(%r9), %r11d
	testl	$-3, %r11d
	jne	.LBB1_8
# %bb.7:                                #   in Loop: Header=BB1_2 Depth=2
	movl	$-1082130432, (%rcx,%r10)       # imm = 0xBF800000
	jmp	.LBB1_9
.LBB1_8:                                #   in Loop: Header=BB1_2 Depth=2
	movl	$0, (%rcx,%r10)
.LBB1_9:                                #   in Loop: Header=BB1_2 Depth=2
	addq	$4, %r10
	decl	%r9d
	cmpq	$4096, %r10                     # imm = 0x1000
	jne	.LBB1_2
# %bb.4:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rdx
	addq	$4096, %rcx                     # imm = 0x1000
	addq	$4, %rax
	cmpq	$1024, %rdx                     # imm = 0x400
	jne	.LBB1_1
# %bb.5:
	retq
.Lfunc_end1:
	.size	_Z10initializePfS_, .Lfunc_end1-_Z10initializePfS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:                                # %.preheader.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	32(%rsp), %rbx
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	24(%rsp), %r14
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r14, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %r15
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r15, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%rbx), %rdi
	movq	(%r14), %rsi
	callq	_Z10initializePfS_
	movq	(%r15), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$100, %ebp
	movabsq	$274877907008, %rbx             # imm = 0x4000000040
	movabsq	$68719476752, %r14              # imm = 0x1000000010
.LBB2_1:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_3
# %bb.2:                                #   in Loop: Header=BB2_1 Depth=1
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rcx
	callq	_Z25__device_stub__sor_kernelPfS_S_S_
.LBB2_3:                                #   in Loop: Header=BB2_1 Depth=1
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rax
	movq	16(%rsp), %rcx
	movq	%rcx, 8(%rsp)
	movq	%rax, 16(%rsp)
	decl	%ebp
	jne	.LBB2_1
# %bb.4:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%rsp), %rax
	cvtss2sd	(%rax), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movl	$1023, %esi                     # imm = 0x3FF
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.2, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%rsp), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	4092(%rax), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10sor_kernelPfS_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10sor_kernelPfS_S_S_,@object  # @_Z10sor_kernelPfS_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z10sor_kernelPfS_S_S_
	.p2align	3, 0x0
_Z10sor_kernelPfS_S_S_:
	.quad	_Z25__device_stub__sor_kernelPfS_S_S_
	.size	_Z10sor_kernelPfS_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"x[0] = "
	.size	.L.str, 8

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	", x["
	.size	.L.str.1, 5

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"] = "
	.size	.L.str.2, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10sor_kernelPfS_S_S_"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__sor_kernelPfS_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10sor_kernelPfS_S_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10sor_kernelPfS_S_S_  ; -- Begin function _Z10sor_kernelPfS_S_S_
	.globl	_Z10sor_kernelPfS_S_S_
	.p2align	8
	.type	_Z10sor_kernelPfS_S_S_,@function
_Z10sor_kernelPfS_S_S_:                 ; @_Z10sor_kernelPfS_S_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_max_i32_e32 v2, v0, v1
	v_cmp_eq_u32_e64 s2, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0x400, v2
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	v_dual_mov_b32 v9, v0 :: v_dual_mov_b32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v4, vcc_lo
	s_mov_b64 s[2:3], 0
	global_load_b32 v5, v[1:2], off
	v_lshlrev_b32_e32 v1, 10, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v5, off
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v9
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v10, vcc_lo, v6, s2
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v7, vcc_lo
	s_add_u32 s8, s4, s2
	s_addc_u32 s9, s5, s3
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v8, s[8:9]
	s_waitcnt vmcnt(0)
	v_fma_f32 v5, -v10, v11, v5
	global_store_b32 v[1:2], v5, off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v9, -1, v9
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0x1000
	s_cbranch_scc0 .LBB0_2
; %bb.5:
	v_lshl_add_u32 v6, v0, 10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v0, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[6:7], v0
	global_load_b32 v0, v[3:4], off
	v_div_scale_f64 v[3:4], null, v[6:7], v[6:7], 0x3ff40000
	v_div_scale_f64 v[12:13], vcc_lo, 0x3ff40000, v[6:7], 0x3ff40000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[3:4], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[3:4], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	v_fma_f64 v[3:4], -v[3:4], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[12:13], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[3:4], v[3:4], v[8:9], v[10:11]
	v_ldexp_f64 v[8:9], -v[12:13], -2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[3:4], v[6:7], 0x3ff40000
	v_cvt_f64_f32_e32 v[5:6], v5
	v_fma_f64 v[3:4], v[3:4], v[5:6], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[3:4]
	global_store_b32 v[1:2], v0, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10sor_kernelPfS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10sor_kernelPfS_S_S_, .Lfunc_end0-_Z10sor_kernelPfS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 568
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10sor_kernelPfS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10sor_kernelPfS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
