#include <iostream>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

// Define some constants for the CNN
#define BATCH_SIZE 32
#define IN_CHANNELS 3
#define OUT_CHANNELS_1 32
#define OUT_CHANNELS_2 64
#define OUT_CHANNELS_3 128
#define OUT_CHANNELS_4 256
#define FILTER_SIZE 3
#define IMAGE_SIZE 32
#define STRIDE 1
#define PADDING 1

// Kernel for backpropagation through a single convolutional layer
__global__ void convBackwardKernel(
    const half* d_out, half* d_in, const half* d_filters, 
    int in_channels, int out_channels, int filter_size, 
    int image_size, int stride, int padding) {

    extern __shared__ half shared_data[];

    int bx = blockIdx.x, by = blockIdx.y, bz = blockIdx.z;
    int tx = threadIdx.x, ty = threadIdx.y, tz = threadIdx.z;

    int out_x = bx * blockDim.x + tx;
    int out_y = by * blockDim.y + ty;
    int out_c = bz * blockDim.z + tz;

    if (out_c >= out_channels || out_x >= image_size || out_y >= image_size) return;

    int in_x = out_x * stride - padding;
    int in_y = out_y * stride - padding;

    half grad_in = __float2half(0.0f);

    for (int c = 0; c < in_channels; ++c) {
        for (int ky = 0; ky < filter_size; ++ky) {
            for (int kx = 0; kx < filter_size; ++kx) {
                int in_x_k = in_x + kx;
                int in_y_k = in_y + ky;

                if (in_x_k >= 0 && in_x_k < image_size && in_y_k >= 0 && in_y_k < image_size) {
                    int filter_idx = c * filter_size * filter_size * out_channels + ky * filter_size * out_channels + kx * out_channels + out_c;
                    int out_idx = (bz * image_size + out_y) * image_size + out_x;
                    int in_idx = (c * image_size + in_y_k) * image_size + in_x_k;

                    grad_in += d_filters[filter_idx] * d_out[out_idx];
                }
            }
        }
    }

    d_in[out_c * image_size * image_size + out_y * image_size + out_x] = grad_in;
}

int main() {
    // Allocate memory for input, output, and filters on host
    size_t in_size = BATCH_SIZE * IN_CHANNELS * IMAGE_SIZE * IMAGE_SIZE * sizeof(half);
    size_t out_size = BATCH_SIZE * OUT_CHANNELS_4 * IMAGE_SIZE * IMAGE_SIZE * sizeof(half);
    size_t filter_size_1 = IN_CHANNELS * OUT_CHANNELS_1 * FILTER_SIZE * FILTER_SIZE * sizeof(half);
    size_t filter_size_2 = OUT_CHANNELS_1 * OUT_CHANNELS_2 * FILTER_SIZE * FILTER_SIZE * sizeof(half);
    size_t filter_size_3 = OUT_CHANNELS_2 * OUT_CHANNELS_3 * FILTER_SIZE * FILTER_SIZE * sizeof(half);
    size_t filter_size_4 = OUT_CHANNELS_3 * OUT_CHANNELS_4 * FILTER_SIZE * FILTER_SIZE * sizeof(half);

    half* h_in = (half*)malloc(in_size);
    half* h_out = (half*)malloc(out_size);
    half* h_filters_4 = (half*)malloc(filter_size_4);

    // Initialize host data
    for (size_t i = 0; i < in_size / sizeof(half); ++i) h_in[i] = __float2half(1.0f);
    for (size_t i = 0; i < out_size / sizeof(half); ++i) h_out[i] = __float2half(1.0f);
    for (size_t i = 0; i < filter_size_4 / sizeof(half); ++i) h_filters_4[i] = __float2half(0.5f);

    // Allocate memory on device
    half* d_in, *d_out, *d_filters_4;
    cudaMalloc((void**)&d_in, in_size);
    cudaMalloc((void**)&d_out, out_size);
    cudaMalloc((void**)&d_filters_4, filter_size_4);

    // Copy data from host to device
    cudaMemcpy(d_in, h_in, in_size, cudaMemcpyHostToDevice);
    cudaMemcpy(d_out, h_out, out_size, cudaMemcpyHostToDevice);
    cudaMemcpy(d_filters_4, h_filters_4, filter_size_4, cudaMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(8, 8, 4);
    dim3 gridSize((IMAGE_SIZE + blockSize.x - 1) / blockSize.x, 
                 (IMAGE_SIZE + blockSize.y - 1) / blockSize.y, 
                 (OUT_CHANNELS_4 + blockSize.z - 1) / blockSize.z);

    size_t sharedMemSize = 0; // No shared memory used in this example

    // Launch kernel
    convBackwardKernel<<<gridSize, blockSize, sharedMemSize>>>(d_out, d_in, d_filters_4, 
                                                               OUT_CHANNELS_3, OUT_CHANNELS_4, FILTER_SIZE, 
                                                               IMAGE_SIZE, STRIDE, PADDING);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    cudaMemcpy(h_in, d_in, in_size, cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_in);
    cudaFree(d_out);
    cudaFree(d_filters_4);

    // Free host memory
    free(h_in);
    free(h_out);
    free(h_filters_4);

    return 0;
}
	.file	"tmpxft_001856b2_00000000-6_cuda_code_026640.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL12__float2halff, @function
_ZL12__float2halff:
.LFB3763:
	.cfi_startproc
	movd	%xmm0, %ecx
	movl	%ecx, %edx
	movl	%ecx, %eax
	shrl	$16, %eax
	andl	$2147483647, %edx
	andl	$32768, %eax
	cmpl	$2139095039, %edx
	jbe	.L3
	orb	$124, %ah
	cmpl	$2139095040, %edx
	movl	$32767, %edx
	cmovne	%edx, %eax
	ret
.L3:
	cmpl	$1199566847, %edx
	jbe	.L5
	orw	$31743, %ax
	jmp	.L6
.L5:
	cmpl	$947912703, %edx
	jbe	.L7
	movl	%edx, %edi
	subl	$939524096, %edx
	shrl	$13, %edx
	sall	$19, %edi
	orl	%edx, %eax
	jmp	.L8
.L7:
	cmpl	$855638016, %edx
	jbe	.L4
	andl	$8388607, %ecx
	shrl	$23, %edx
	movl	%ecx, %esi
	leal	-94(%rdx), %ecx
	orl	$8388608, %esi
	movl	%esi, %edi
	sall	%cl, %edi
	movl	$126, %ecx
	subl	%edx, %ecx
	shrl	%cl, %esi
	orl	%esi, %eax
.L8:
	cmpl	$-2147483648, %edi
	ja	.L6
	jne	.L4
	testb	$1, %al
	je	.L4
.L6:
	incl	%eax
.L4:
	ret
	.cfi_endproc
.LFE3763:
	.size	_ZL12__float2halff, .-_ZL12__float2halff
	.globl	_Z57__device_stub__Z18convBackwardKernelPK6__halfPS_S1_iiiiiiPK6__halfPS_S1_iiiiii
	.type	_Z57__device_stub__Z18convBackwardKernelPK6__halfPS_S1_iiiiiiPK6__halfPS_S1_iiiiii, @function
_Z57__device_stub__Z18convBackwardKernelPK6__halfPS_S1_iiiiiiPK6__halfPS_S1_iiiiii:
.LFB4034:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L15:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4034:
	.size	_Z57__device_stub__Z18convBackwardKernelPK6__halfPS_S1_iiiiiiPK6__halfPS_S1_iiiiii, .-_Z57__device_stub__Z18convBackwardKernelPK6__halfPS_S1_iiiiiiPK6__halfPS_S1_iiiiii
	.globl	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii
	.type	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii, @function
_Z18convBackwardKernelPK6__halfPS_S1_iiiiii:
.LFB4035:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z18convBackwardKernelPK6__halfPS_S1_iiiiiiPK6__halfPS_S1_iiiiii
	.cfi_endproc
.LFE4035:
	.size	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii, .-_Z18convBackwardKernelPK6__halfPS_S1_iiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4009:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$196608, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$16777216, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$589824, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rbx, %r8
	leaq	196608(%rbx), %r9
	movq	%rax, %rbp
.L21:
	movss	.LC0(%rip), %xmm0
	addq	$2, %r8
	call	_ZL12__float2halff
	movw	%ax, -2(%r8)
	cmpq	%r9, %r8
	jne	.L21
	movq	%r12, %r8
	leaq	16777216(%r12), %r9
.L22:
	movss	.LC0(%rip), %xmm0
	addq	$2, %r8
	call	_ZL12__float2halff
	movw	%ax, -2(%r8)
	cmpq	%r9, %r8
	jne	.L22
	movq	%rbp, %r8
	leaq	589824(%rbp), %r9
.L23:
	movss	.LC1(%rip), %xmm0
	addq	$2, %r8
	call	_ZL12__float2halff
	movw	%ax, -2(%r8)
	cmpq	%r9, %r8
	jne	.L23
	leaq	8(%rsp), %rdi
	movl	$196608, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$16777216, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$589824, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$196608, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$16777216, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$589824, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4, %ecx
	movabsq	$34359738376, %rdx
	movl	$64, %esi
	movabsq	$17179869188, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	$3, %r9d
	movl	$256, %r8d
	movl	$128, %ecx
	pushq	$1
	.cfi_def_cfa_offset 128
	pushq	$1
	.cfi_def_cfa_offset 136
	pushq	$32
	.cfi_def_cfa_offset 144
	movq	56(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z57__device_stub__Z18convBackwardKernelPK6__halfPS_S1_iiiiiiPK6__halfPS_S1_iiiiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 112
.L24:
	call	cudaGetLastError@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	je	.L25
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L20
.L25:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$196608, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	xorl	%eax, %eax
.L20:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4009:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z18convBackwardKernelPK6__halfPS_S1_iiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	1056964608
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>

// Define some constants for the CNN
#define BATCH_SIZE 32
#define IN_CHANNELS 3
#define OUT_CHANNELS_1 32
#define OUT_CHANNELS_2 64
#define OUT_CHANNELS_3 128
#define OUT_CHANNELS_4 256
#define FILTER_SIZE 3
#define IMAGE_SIZE 32
#define STRIDE 1
#define PADDING 1

// Kernel for backpropagation through a single convolutional layer
__global__ void convBackwardKernel(
    const half* d_out, half* d_in, const half* d_filters, 
    int in_channels, int out_channels, int filter_size, 
    int image_size, int stride, int padding) {

    extern __shared__ half shared_data[];

    int bx = blockIdx.x, by = blockIdx.y, bz = blockIdx.z;
    int tx = threadIdx.x, ty = threadIdx.y, tz = threadIdx.z;

    int out_x = bx * blockDim.x + tx;
    int out_y = by * blockDim.y + ty;
    int out_c = bz * blockDim.z + tz;

    if (out_c >= out_channels || out_x >= image_size || out_y >= image_size) return;

    int in_x = out_x * stride - padding;
    int in_y = out_y * stride - padding;

    half grad_in = __float2half(0.0f);

    for (int c = 0; c < in_channels; ++c) {
        for (int ky = 0; ky < filter_size; ++ky) {
            for (int kx = 0; kx < filter_size; ++kx) {
                int in_x_k = in_x + kx;
                int in_y_k = in_y + ky;

                if (in_x_k >= 0 && in_x_k < image_size && in_y_k >= 0 && in_y_k < image_size) {
                    int filter_idx = c * filter_size * filter_size * out_channels + ky * filter_size * out_channels + kx * out_channels + out_c;
                    int out_idx = (bz * image_size + out_y) * image_size + out_x;
                    int in_idx = (c * image_size + in_y_k) * image_size + in_x_k;

                    grad_in += d_filters[filter_idx] * d_out[out_idx];
                }
            }
        }
    }

    d_in[out_c * image_size * image_size + out_y * image_size + out_x] = grad_in;
}

int main() {
    // Allocate memory for input, output, and filters on host
    size_t in_size = BATCH_SIZE * IN_CHANNELS * IMAGE_SIZE * IMAGE_SIZE * sizeof(half);
    size_t out_size = BATCH_SIZE * OUT_CHANNELS_4 * IMAGE_SIZE * IMAGE_SIZE * sizeof(half);
    size_t filter_size_1 = IN_CHANNELS * OUT_CHANNELS_1 * FILTER_SIZE * FILTER_SIZE * sizeof(half);
    size_t filter_size_2 = OUT_CHANNELS_1 * OUT_CHANNELS_2 * FILTER_SIZE * FILTER_SIZE * sizeof(half);
    size_t filter_size_3 = OUT_CHANNELS_2 * OUT_CHANNELS_3 * FILTER_SIZE * FILTER_SIZE * sizeof(half);
    size_t filter_size_4 = OUT_CHANNELS_3 * OUT_CHANNELS_4 * FILTER_SIZE * FILTER_SIZE * sizeof(half);

    half* h_in = (half*)malloc(in_size);
    half* h_out = (half*)malloc(out_size);
    half* h_filters_4 = (half*)malloc(filter_size_4);

    // Initialize host data
    for (size_t i = 0; i < in_size / sizeof(half); ++i) h_in[i] = __float2half(1.0f);
    for (size_t i = 0; i < out_size / sizeof(half); ++i) h_out[i] = __float2half(1.0f);
    for (size_t i = 0; i < filter_size_4 / sizeof(half); ++i) h_filters_4[i] = __float2half(0.5f);

    // Allocate memory on device
    half* d_in, *d_out, *d_filters_4;
    hipMalloc((void**)&d_in, in_size);
    hipMalloc((void**)&d_out, out_size);
    hipMalloc((void**)&d_filters_4, filter_size_4);

    // Copy data from host to device
    hipMemcpy(d_in, h_in, in_size, hipMemcpyHostToDevice);
    hipMemcpy(d_out, h_out, out_size, hipMemcpyHostToDevice);
    hipMemcpy(d_filters_4, h_filters_4, filter_size_4, hipMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(8, 8, 4);
    dim3 gridSize((IMAGE_SIZE + blockSize.x - 1) / blockSize.x, 
                 (IMAGE_SIZE + blockSize.y - 1) / blockSize.y, 
                 (OUT_CHANNELS_4 + blockSize.z - 1) / blockSize.z);

    size_t sharedMemSize = 0; // No shared memory used in this example

    // Launch kernel
    convBackwardKernel<<<gridSize, blockSize, sharedMemSize>>>(d_out, d_in, d_filters_4, 
                                                               OUT_CHANNELS_3, OUT_CHANNELS_4, FILTER_SIZE, 
                                                               IMAGE_SIZE, STRIDE, PADDING);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    hipMemcpy(h_in, d_in, in_size, hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_in);
    hipFree(d_out);
    hipFree(d_filters_4);

    // Free host memory
    free(h_in);
    free(h_out);
    free(h_filters_4);

    return 0;
}
	.text
	.file	"cuda_code_026640.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii # -- Begin function _Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii
	.type	_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii,@function
_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii: # @_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convBackwardKernelPK6__halfPS_S1_iiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii, .Lfunc_end0-_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$196608, %edi                   # imm = 0x30000
	callq	malloc
	movq	%rax, %rbx
	movl	$16777216, %edi                 # imm = 0x1000000
	callq	malloc
	movq	%rax, %r14
	movl	$589824, %edi                   # imm = 0x90000
	callq	malloc
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movw	$15360, (%rbx,%rax,2)           # imm = 0x3C00
	incq	%rax
	cmpq	$98304, %rax                    # imm = 0x18000
	jne	.LBB1_1
# %bb.2:                                # %.preheader52.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader52
                                        # =>This Inner Loop Header: Depth=1
	movw	$15360, (%r14,%rax,2)           # imm = 0x3C00
	incq	%rax
	cmpq	$8388608, %rax                  # imm = 0x800000
	jne	.LBB1_3
# %bb.4:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movw	$14336, (%r15,%rax,2)           # imm = 0x3800
	incq	%rax
	cmpq	$294912, %rax                   # imm = 0x48000
	jne	.LBB1_5
# %bb.6:
	movq	%rsp, %r12
	movl	$196608, %esi                   # imm = 0x30000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r13
	movl	$16777216, %esi                 # imm = 0x1000000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movl	$589824, %esi                   # imm = 0x90000
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$1, %r12d
	movl	$196608, %edx                   # imm = 0x30000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$16777216, %edx                 # imm = 0x1000000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$589824, %edx                   # imm = 0x90000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$17179869188, %rdi              # imm = 0x400000004
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$64, %esi
	movl	$4, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$128, %ecx
	movl	$256, %r8d                      # imm = 0x100
	movl	$3, %r9d
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	$32
	.cfi_adjust_cfa_offset 8
	callq	_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_8:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_13
# %bb.9:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_10
# %bb.11:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_12
.LBB1_13:
	movq	(%rsp), %rsi
	movl	$196608, %edx                   # imm = 0x30000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	jmp	.LBB1_14
.LBB1_10:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_14:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convBackwardKernelPK6__halfPS_S1_iiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii,@object # @_Z18convBackwardKernelPK6__halfPS_S1_iiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii
	.p2align	3, 0x0
_Z18convBackwardKernelPK6__halfPS_S1_iiiiii:
	.quad	_Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii
	.size	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convBackwardKernelPK6__halfPS_S1_iiiiii"
	.size	.L__unnamed_1, 44

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convBackwardKernelPK6__halfPS_S1_iiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convBackwardKernelPK6__halfPS_S1_iiiiii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii ; -- Begin function _Z18convBackwardKernelPK6__halfPS_S1_iiiiii
	.globl	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii
	.p2align	8
	.type	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii,@function
_Z18convBackwardKernelPK6__halfPS_S1_iiiiii: ; @_Z18convBackwardKernelPK6__halfPS_S1_iiiiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_lshr_b32 s8, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
	v_mad_u64_u32 v[0:1], null, s13, s2, v[4:5]
	v_mad_u64_u32 v[3:4], null, s14, s8, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s5, v2
	v_cmp_gt_i32_e64 s2, s7, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s7, v3
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_15
; %bb.1:
	s_clause 0x2
	s_load_b64 s[12:13], s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_13
; %bb.2:                                ; %.preheader89.lr.ph
	v_mad_u64_u32 v[4:5], null, s15, s7, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v7, v0, s12
	v_mul_lo_u32 v9, v3, s12
	s_cmp_gt_i32 s6, 0
	v_mov_b32_e32 v10, v2
	s_cselect_b32 s12, -1, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[5:6], null, v4, s7, v[0:1]
	v_mov_b32_e32 v1, 0
	v_subrev_nc_u32_e32 v8, s13, v7
	v_subrev_nc_u32_e32 v9, s13, v9
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 1, v[5:6]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_mul_i32 s8, s6, s5
	s_mov_b32 s9, 0
	s_mul_i32 s13, s8, s6
.LBB0_3:                                ; %.preheader89
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_12
; %bb.4:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v11, v10
	s_mov_b32 s14, 0
.LBB0_5:                                ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s14, v9
	s_mov_b32 s15, 0
	v_cmp_lt_i32_e32 vcc_lo, -1, v6
	v_cmp_gt_i32_e64 s0, s7, v6
	v_mov_b32_e32 v6, v11
.LBB0_6:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v7, s15, v8
	s_mov_b32 s16, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v7
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=3
	v_cmp_gt_i32_e64 s1, s7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, vcc_lo
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s17, s1
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=3
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 1, v[6:7]
	v_add_co_u32 v12, s1, s2, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s1, s3, v13, s1
	global_load_u16 v7, v[12:13], off
	global_load_u16 v12, v[4:5], off
	s_waitcnt vmcnt(0)
	v_fmac_f16_e32 v1, v7, v12
.LBB0_9:                                ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s17
.LBB0_10:                               ;   in Loop: Header=BB0_6 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
	v_add_nc_u32_e32 v6, s5, v6
	s_add_i32 s15, s15, 1
	s_cmp_eq_u32 s6, s15
	s_cbranch_scc0 .LBB0_6
; %bb.11:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v11, s8, v11
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s14, s6
	s_cbranch_scc0 .LBB0_5
.LBB0_12:                               ; %._crit_edge94
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v10, s13, v10
	s_add_i32 s9, s9, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s9, s4
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_14
.LBB0_13:
	v_mov_b32_e32 v1, 0
.LBB0_14:                               ; %._crit_edge98
	v_mad_u64_u32 v[4:5], null, v2, s7, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, s7, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 1, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b16 v[2:3], v1, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convBackwardKernelPK6__halfPS_S1_iiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convBackwardKernelPK6__halfPS_S1_iiiiii, .Lfunc_end0-_Z18convBackwardKernelPK6__halfPS_S1_iiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 596
; NumSgprs: 20
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convBackwardKernelPK6__halfPS_S1_iiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z18convBackwardKernelPK6__halfPS_S1_iiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
