#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>

#define NUM_ELEMENTS 4096
#define BLOCK_SIZE 256
#define MAX_LEVEL 16

struct Node {
    int key;
    int level;
    int next[MAX_LEVEL];
};

__global__ void initializeSkipList(Node* d_skipList, int numElements) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numElements) {
        d_skipList[idx].key = idx;
        d_skipList[idx].level = 0;
        for (int i = 0; i < MAX_LEVEL; i++) {
            d_skipList[idx].next[i] = -1; // -1 indicates no next node
        }
    }
}

__global__ void insertSkipList(Node* d_skipList, int* d_keys, int numElements, int maxLevel) {
    extern __shared__ Node sharedNodes[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;

    // Load data into shared memory
    if (idx < numElements) {
        sharedNodes[threadIdx.x] = d_skipList[idx];
    }
    __syncthreads();

    // Insert logic using shared memory
    if (idx < numElements) {
        int key = d_keys[idx];
        int current = 0;
        for (int level = maxLevel - 1; level >= 0; level--) {
            while (sharedNodes[current].next[level] != -1 && sharedNodes[sharedNodes[current].next[level]].key < key) {
                current = sharedNodes[current].next[level];
            }
        }
        current = sharedNodes[current].next[0];
        if (current == -1 || sharedNodes[current].key != key) {
            // Assuming a new node is created with level 0 for simplicity
            int newNodeIdx = idx;
            for (int level = 0; level < sharedNodes[newNodeIdx].level; level++) {
                sharedNodes[newNodeIdx].next[level] = sharedNodes[current].next[level];
                sharedNodes[current].next[level] = newNodeIdx;
            }
        }
    }
    __syncthreads();

    // Write back to global memory
    if (idx < numElements) {
        d_skipList[idx] = sharedNodes[threadIdx.x];
    }
}

void checkCudaError(cudaError_t err, const char* msg) {
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << msg << " (" << cudaGetErrorString(err) << ")" << std::endl;
        exit(EXIT_FAILURE);
    }
}

int main() {
    Node* d_skipList;
    int* d_keys;
    Node h_skipList[NUM_ELEMENTS];
    int h_keys[NUM_ELEMENTS];

    // Initialize host data
    for (int i = 0; i < NUM_ELEMENTS; i++) {
        h_keys[i] = i;
        h_skipList[i].key = i;
        h_skipList[i].level = 0;
        for (int j = 0; j < MAX_LEVEL; j++) {
            h_skipList[i].next[j] = -1;
        }
    }

    // Allocate device memory
    checkCudaError(cudaMalloc(&d_skipList, NUM_ELEMENTS * sizeof(Node)), "Failed to allocate device memory for skip list");
    checkCudaError(cudaMalloc(&d_keys, NUM_ELEMENTS * sizeof(int)), "Failed to allocate device memory for keys");

    // Copy data to device
    checkCudaError(cudaMemcpy(d_skipList, h_skipList, NUM_ELEMENTS * sizeof(Node), cudaMemcpyHostToDevice), "Failed to copy skip list to device");
    checkCudaError(cudaMemcpy(d_keys, h_keys, NUM_ELEMENTS * sizeof(int), cudaMemcpyHostToDevice), "Failed to copy keys to device");

    // Initialize skip list
    initializeSkipList<<<(NUM_ELEMENTS + BLOCK_SIZE - 1) / BLOCK_SIZE, BLOCK_SIZE>>>(d_skipList, NUM_ELEMENTS);
    checkCudaError(cudaGetLastError(), "Kernel launch failed for initializeSkipList");
    checkCudaError(cudaDeviceSynchronize(), "Failed to synchronize after initializeSkipList");

    // Insert elements into skip list
    insertSkipList<<<(NUM_ELEMENTS + BLOCK_SIZE - 1) / BLOCK_SIZE, BLOCK_SIZE, BLOCK_SIZE * sizeof(Node)>>>(d_skipList, d_keys, NUM_ELEMENTS, MAX_LEVEL);
    checkCudaError(cudaGetLastError(), "Kernel launch failed for insertSkipList");
    checkCudaError(cudaDeviceSynchronize(), "Failed to synchronize after insertSkipList");

    // Copy result back to host
    checkCudaError(cudaMemcpy(h_skipList, d_skipList, NUM_ELEMENTS * sizeof(Node), cudaMemcpyDeviceToHost), "Failed to copy skip list back to host");

    // Free device memory
    cudaFree(d_skipList);
    cudaFree(d_keys);

    // Print first few elements for demonstration
    for (int i = 0; i < 10; i++) {
        std::cout << "Node " << i << ": Key = " << h_skipList[i].key << ", Level = " << h_skipList[i].level;
        for (int j = 0; j < h_skipList[i].level; j++) {
            std::cout << ", Next[" << j << "] = " << h_skipList[i].next[j];
        }
        std::cout << std::endl;
    }

    return 0;
}
	.file	"tmpxft_001b91ce_00000000-6_cuda_code_009260.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3853:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3853:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
.LC1:
	.string	" ("
.LC2:
	.string	")"
	.text
	.globl	_Z14checkCudaError9cudaErrorPKc
	.type	_Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB3849:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	leaq	.LC0(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3849:
	.size	_Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
	.globl	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
	.type	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei, @function
_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei:
.LFB3875:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z18initializeSkipListP4Nodei(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3875:
	.size	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei, .-_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
	.globl	_Z18initializeSkipListP4Nodei
	.type	_Z18initializeSkipListP4Nodei, @function
_Z18initializeSkipListP4Nodei:
.LFB3876:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
	.cfi_endproc
.LFE3876:
	.size	_Z18initializeSkipListP4Nodei, .-_Z18initializeSkipListP4Nodei
	.globl	_Z42__device_stub__Z14insertSkipListP4NodePiiiP4NodePiii
	.type	_Z42__device_stub__Z14insertSkipListP4NodePiiiP4NodePiii, @function
_Z42__device_stub__Z14insertSkipListP4NodePiiiP4NodePiii:
.LFB3877:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14insertSkipListP4NodePiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3877:
	.size	_Z42__device_stub__Z14insertSkipListP4NodePiiiP4NodePiii, .-_Z42__device_stub__Z14insertSkipListP4NodePiiiP4NodePiii
	.globl	_Z14insertSkipListP4NodePiii
	.type	_Z14insertSkipListP4NodePiii, @function
_Z14insertSkipListP4NodePiii:
.LFB3878:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z14insertSkipListP4NodePiiiP4NodePiii
	.cfi_endproc
.LFE3878:
	.size	_Z14insertSkipListP4NodePiii, .-_Z14insertSkipListP4NodePiii
	.section	.rodata.str1.1
.LC3:
	.string	"Failed to allocate device memory for skip list"
.LC4:
	.string	"Failed to allocate device memory for keys"
.LC5:
	.string	"Failed to copy skip list to device"
.LC6:
	.string	"Failed to copy keys to device"
.LC7:
	.string	"Kernel launch failed for initializeSkipList"
.LC8:
	.string	"Failed to synchronize after initializeSkipList"
.LC9:
	.string	"Kernel launch failed for insertSkipList"
.LC10:
	.string	"Failed to synchronize after insertSkipList"
.LC11:
	.string	"Failed to copy skip list back to host"
.LC12:
	.string	"Node "
.LC13:
	.string	": Key = "
.LC14:
	.string	", Level = "
.LC15:
	.string	", Next["
.LC16:
	.string	"] = "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3850:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-311296(%rsp), %r11
	.cfi_def_cfa 11, 311352
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$56, %rsp
	.cfi_def_cfa_offset 311408
	xorl	%edx, %edx
	movq	%fs:40, %rax
	movq	%rax, 311336(%rsp)
	xorl	%eax, %eax
	leaq	16424(%rsp), %rbx
	movb	$-1, %al
	movq	%rbx, %rsi
.L19:
	xorl	%ecx, %ecx
	leaq	8(%rsi), %r8
	leaq	40(%rsp), %rbp
	movl	%edx, (%rsi)
	movl	%ecx, 4(%rsi)
	movq	%r8, %rdi
	movl	$64, %ecx
	addq	$72, %rsi
	movl	%edx, 0(%rbp,%rdx,4)
	incq	%rdx
	rep stosb
	cmpq	$4096, %rdx
	jne	.L19
	movq	%rsp, %rdi
	movl	$294912, %esi
	call	cudaMalloc@PLT
	leaq	.LC3(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	leaq	8(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$294912, %edx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	leaq	.LC6(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$268435457, %edi
	salq	$8, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$4, %rdi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	(%rsp), %rdi
	movl	$4096, %esi
	call	_Z43__device_stub__Z18initializeSkipListP4NodeiP4Nodei
.L20:
	call	cudaGetLastError@PLT
	leaq	.LC7(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	call	cudaDeviceSynchronize@PLT
	leaq	.LC8(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movl	$16777217, %edx
	movl	$268435457, %edi
	xorl	%r9d, %r9d
	salq	$8, %rdx
	salq	$4, %rdi
	movl	$18432, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$16, %ecx
	movl	$4096, %edx
	call	_Z42__device_stub__Z14insertSkipListP4NodePiiiP4NodePiii
.L21:
	call	cudaGetLastError@PLT
	leaq	.LC9(%rip), %rsi
	xorl	%ebp, %ebp
	leaq	.LC12(%rip), %r13
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	call	cudaDeviceSynchronize@PLT
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$294912, %edx
	call	cudaMemcpy@PLT
	leaq	.LC11(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
.L24:
	movq	%r13, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	xorl	%r12d, %r12d
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	leaq	.LC15(%rip), %r15
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC13(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	(%rbx), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	4(%rbx), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
.L22:
	movl	%r12d, %r14d
	cmpl	%r12d, 4(%rbx)
	jle	.L29
	movq	%r15, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC16(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	8(%rbx,%r12,4), %esi
	incq	%r12
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	jmp	.L22
.L29:
	leaq	_ZSt4cout(%rip), %rdi
	incl	%ebp
	addq	$72, %rbx
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpl	$10, %ebp
	jne	.L24
	movq	311336(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$311352, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3850:
	.size	main, .-main
	.section	.rodata.str1.1
.LC17:
	.string	"_Z14insertSkipListP4NodePiii"
.LC18:
	.string	"_Z18initializeSkipListP4Nodei"
.LC19:
	.string	"precalc_xorwow_matrix"
.LC20:
	.string	"precalc_xorwow_offset_matrix"
.LC21:
	.string	"mrg32k3aM1"
.LC22:
	.string	"mrg32k3aM2"
.LC23:
	.string	"mrg32k3aM1SubSeq"
.LC24:
	.string	"mrg32k3aM2SubSeq"
.LC25:
	.string	"mrg32k3aM1Seq"
.LC26:
	.string	"mrg32k3aM2Seq"
.LC27:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3880:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14insertSkipListP4NodePiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18initializeSkipListP4Nodei(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC26(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3880:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

#define NUM_ELEMENTS 4096
#define BLOCK_SIZE 256
#define MAX_LEVEL 16

struct Node {
    int key;
    int level;
    int next[MAX_LEVEL];
};

__global__ void initializeSkipList(Node* d_skipList, int numElements) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numElements) {
        d_skipList[idx].key = idx;
        d_skipList[idx].level = 0;
        for (int i = 0; i < MAX_LEVEL; i++) {
            d_skipList[idx].next[i] = -1; // -1 indicates no next node
        }
    }
}

__global__ void insertSkipList(Node* d_skipList, int* d_keys, int numElements, int maxLevel) {
    extern __shared__ Node sharedNodes[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;

    // Load data into shared memory
    if (idx < numElements) {
        sharedNodes[threadIdx.x] = d_skipList[idx];
    }
    __syncthreads();

    // Insert logic using shared memory
    if (idx < numElements) {
        int key = d_keys[idx];
        int current = 0;
        for (int level = maxLevel - 1; level >= 0; level--) {
            while (sharedNodes[current].next[level] != -1 && sharedNodes[sharedNodes[current].next[level]].key < key) {
                current = sharedNodes[current].next[level];
            }
        }
        current = sharedNodes[current].next[0];
        if (current == -1 || sharedNodes[current].key != key) {
            // Assuming a new node is created with level 0 for simplicity
            int newNodeIdx = idx;
            for (int level = 0; level < sharedNodes[newNodeIdx].level; level++) {
                sharedNodes[newNodeIdx].next[level] = sharedNodes[current].next[level];
                sharedNodes[current].next[level] = newNodeIdx;
            }
        }
    }
    __syncthreads();

    // Write back to global memory
    if (idx < numElements) {
        d_skipList[idx] = sharedNodes[threadIdx.x];
    }
}

void checkCudaError(hipError_t err, const char* msg) {
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << msg << " (" << hipGetErrorString(err) << ")" << std::endl;
        exit(EXIT_FAILURE);
    }
}

int main() {
    Node* d_skipList;
    int* d_keys;
    Node h_skipList[NUM_ELEMENTS];
    int h_keys[NUM_ELEMENTS];

    // Initialize host data
    for (int i = 0; i < NUM_ELEMENTS; i++) {
        h_keys[i] = i;
        h_skipList[i].key = i;
        h_skipList[i].level = 0;
        for (int j = 0; j < MAX_LEVEL; j++) {
            h_skipList[i].next[j] = -1;
        }
    }

    // Allocate device memory
    checkCudaError(hipMalloc(&d_skipList, NUM_ELEMENTS * sizeof(Node)), "Failed to allocate device memory for skip list");
    checkCudaError(hipMalloc(&d_keys, NUM_ELEMENTS * sizeof(int)), "Failed to allocate device memory for keys");

    // Copy data to device
    checkCudaError(hipMemcpy(d_skipList, h_skipList, NUM_ELEMENTS * sizeof(Node), hipMemcpyHostToDevice), "Failed to copy skip list to device");
    checkCudaError(hipMemcpy(d_keys, h_keys, NUM_ELEMENTS * sizeof(int), hipMemcpyHostToDevice), "Failed to copy keys to device");

    // Initialize skip list
    initializeSkipList<<<(NUM_ELEMENTS + BLOCK_SIZE - 1) / BLOCK_SIZE, BLOCK_SIZE>>>(d_skipList, NUM_ELEMENTS);
    checkCudaError(hipGetLastError(), "Kernel launch failed for initializeSkipList");
    checkCudaError(hipDeviceSynchronize(), "Failed to synchronize after initializeSkipList");

    // Insert elements into skip list
    insertSkipList<<<(NUM_ELEMENTS + BLOCK_SIZE - 1) / BLOCK_SIZE, BLOCK_SIZE, BLOCK_SIZE * sizeof(Node)>>>(d_skipList, d_keys, NUM_ELEMENTS, MAX_LEVEL);
    checkCudaError(hipGetLastError(), "Kernel launch failed for insertSkipList");
    checkCudaError(hipDeviceSynchronize(), "Failed to synchronize after insertSkipList");

    // Copy result back to host
    checkCudaError(hipMemcpy(h_skipList, d_skipList, NUM_ELEMENTS * sizeof(Node), hipMemcpyDeviceToHost), "Failed to copy skip list back to host");

    // Free device memory
    hipFree(d_skipList);
    hipFree(d_keys);

    // Print first few elements for demonstration
    for (int i = 0; i < 10; i++) {
        std::cout << "Node " << i << ": Key = " << h_skipList[i].key << ", Level = " << h_skipList[i].level;
        for (int j = 0; j < h_skipList[i].level; j++) {
            std::cout << ", Next[" << j << "] = " << h_skipList[i].next[j];
        }
        std::cout << std::endl;
    }

    return 0;
}
	.text
	.file	"cuda_code_009260.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__initializeSkipListP4Nodei # -- Begin function _Z33__device_stub__initializeSkipListP4Nodei
	.type	_Z33__device_stub__initializeSkipListP4Nodei,@function
_Z33__device_stub__initializeSkipListP4Nodei: # @_Z33__device_stub__initializeSkipListP4Nodei
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18initializeSkipListP4Nodei, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__initializeSkipListP4Nodei, .Lfunc_end0-_Z33__device_stub__initializeSkipListP4Nodei
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__insertSkipListP4NodePiii # -- Begin function _Z29__device_stub__insertSkipListP4NodePiii
	.type	_Z29__device_stub__insertSkipListP4NodePiii,@function
_Z29__device_stub__insertSkipListP4NodePiii: # @_Z29__device_stub__insertSkipListP4NodePiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14insertSkipListP4NodePiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__insertSkipListP4NodePiii, .Lfunc_end1-_Z29__device_stub__insertSkipListP4NodePiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
	.type	_Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc:      # @_Z14checkCudaError10hipError_tPKc
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB2_2
# %bb.1:
	retq
.LBB2_2:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r14, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z14checkCudaError10hipError_tPKc, .Lfunc_end2-_Z14checkCudaError10hipError_tPKc
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$311320, %rsp                   # imm = 0x4C018
	.cfi_def_cfa_offset 311376
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	16408(%rsp), %rax
	xorl	%ecx, %ecx
	pcmpeqd	%xmm0, %xmm0
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movl	%ecx, 16(%rsp,%rcx,4)
	movl	%ecx, -8(%rax)
	movl	$0, -4(%rax)
	movdqu	%xmm0, (%rax)
	movdqu	%xmm0, 16(%rax)
	movdqu	%xmm0, 32(%rax)
	movdqu	%xmm0, 48(%rax)
	incq	%rcx
	addq	$72, %rax
	cmpq	$4096, %rcx                     # imm = 0x1000
	jne	.LBB3_1
# %bb.2:
	movabsq	$4294967312, %rbx               # imm = 0x100000010
	movq	%rsp, %r15
	movl	$294912, %esi                   # imm = 0x48000
	movq	%r15, %rdi
	callq	hipMalloc
	movl	$.L.str.3, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	leaq	8(%rsp), %r14
	movl	$16384, %esi                    # imm = 0x4000
	movq	%r14, %rdi
	callq	hipMalloc
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movq	(%r15), %rdi
	leaq	16400(%rsp), %rsi
	movl	$294912, %edx                   # imm = 0x48000
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movq	(%r14), %rdi
	leaq	16(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.6, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	leaq	240(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	_Z33__device_stub__initializeSkipListP4Nodei
.LBB3_4:
	callq	hipGetLastError
	movl	$.L.str.7, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	callq	hipDeviceSynchronize
	movl	$.L.str.8, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movl	$18432, %r8d                    # imm = 0x4800
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movl	$16, %ecx
	callq	_Z29__device_stub__insertSkipListP4NodePiii
.LBB3_6:
	callq	hipGetLastError
	movl	$.L.str.9, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	callq	hipDeviceSynchronize
	movl	$.L.str.10, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movq	(%rsp), %rsi
	leaq	16400(%rsp), %rdi
	movl	$294912, %edx                   # imm = 0x48000
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.11, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	leaq	16408(%rsp), %r12
	xorl	%ebx, %ebx
	movl	$_ZSt4cout, %r13d
.LBB3_7:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_9 Depth 2
	movl	$_ZSt4cout, %edi
	movl	$.L.str.12, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.13, %esi
	movl	$8, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	(%rbx,%rbx,8), %r15
	movl	16400(%rsp,%r15,8), %esi
	movq	%r14, %rdi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.14, %esi
	movl	$10, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	16404(%rsp,%r15,8), %esi
	movq	%r14, %rdi
	callq	_ZNSolsEi
	cmpl	$0, 16404(%rsp,%r15,8)
	jle	.LBB3_10
# %bb.8:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB3_7 Depth=1
	leaq	(%rsp,%r15,8), %rbp
	addq	$16404, %rbp                    # imm = 0x4014
	xorl	%r14d, %r14d
.LBB3_9:                                # %.lr.ph
                                        #   Parent Loop BB3_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$_ZSt4cout, %edi
	movl	$.L.str.15, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.16, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%r12,%r14,4), %esi
	movq	%r15, %rdi
	callq	_ZNSolsEi
	incq	%r14
	movslq	(%rbp), %rax
	cmpq	%rax, %r14
	jl	.LBB3_9
.LBB3_10:                               # %._crit_edge
                                        #   in Loop: Header=BB3_7 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%rbx
	addq	$72, %r12
	cmpq	$10, %rbx
	jne	.LBB3_7
# %bb.11:
	xorl	%eax, %eax
	addq	$311320, %rsp                   # imm = 0x4C018
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18initializeSkipListP4Nodei, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14insertSkipListP4NodePiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18initializeSkipListP4Nodei,@object # @_Z18initializeSkipListP4Nodei
	.section	.rodata,"a",@progbits
	.globl	_Z18initializeSkipListP4Nodei
	.p2align	3, 0x0
_Z18initializeSkipListP4Nodei:
	.quad	_Z33__device_stub__initializeSkipListP4Nodei
	.size	_Z18initializeSkipListP4Nodei, 8

	.type	_Z14insertSkipListP4NodePiii,@object # @_Z14insertSkipListP4NodePiii
	.globl	_Z14insertSkipListP4NodePiii
	.p2align	3, 0x0
_Z14insertSkipListP4NodePiii:
	.quad	_Z29__device_stub__insertSkipListP4NodePiii
	.size	_Z14insertSkipListP4NodePiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" ("
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	")"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate device memory for skip list"
	.size	.L.str.3, 47

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate device memory for keys"
	.size	.L.str.4, 42

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to copy skip list to device"
	.size	.L.str.5, 35

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to copy keys to device"
	.size	.L.str.6, 30

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Kernel launch failed for initializeSkipList"
	.size	.L.str.7, 44

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to synchronize after initializeSkipList"
	.size	.L.str.8, 47

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Kernel launch failed for insertSkipList"
	.size	.L.str.9, 40

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Failed to synchronize after insertSkipList"
	.size	.L.str.10, 43

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Failed to copy skip list back to host"
	.size	.L.str.11, 38

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Node "
	.size	.L.str.12, 6

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	": Key = "
	.size	.L.str.13, 9

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	", Level = "
	.size	.L.str.14, 11

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	", Next["
	.size	.L.str.15, 8

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"] = "
	.size	.L.str.16, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18initializeSkipListP4Nodei"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14insertSkipListP4NodePiii"
	.size	.L__unnamed_2, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__initializeSkipListP4Nodei
	.addrsig_sym _Z29__device_stub__insertSkipListP4NodePiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18initializeSkipListP4Nodei
	.addrsig_sym _Z14insertSkipListP4NodePiii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18initializeSkipListP4Nodei ; -- Begin function _Z18initializeSkipListP4Nodei
	.globl	_Z18initializeSkipListP4Nodei
	.p2align	8
	.type	_Z18initializeSkipListP4Nodei,@function
_Z18initializeSkipListP4Nodei:          ; @_Z18initializeSkipListP4Nodei
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v4, -1
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[5:6], null, 0x48, v1, s[0:1]
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, 8
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
	global_store_b64 v[5:6], v[1:2], off
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v1, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v3, vcc_lo
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 64
	global_store_b32 v[1:2], v4, off
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18initializeSkipListP4Nodei
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18initializeSkipListP4Nodei, .Lfunc_end0-_Z18initializeSkipListP4Nodei
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 168
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14insertSkipListP4NodePiii ; -- Begin function _Z14insertSkipListP4NodePiii
	.globl	_Z14insertSkipListP4NodePiii
	.p2align	8
	.type	_Z14insertSkipListP4NodePiii,@function
_Z14insertSkipListP4NodePiii:           ; @_Z14insertSkipListP4NodePiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mad_i64_i32 v[18:19], null, 0x48, v1, s[4:5]
	v_mad_u32_u24 v22, 0x48, v0, 0
	s_clause 0x4
	global_load_b128 v[2:5], v[18:19], off offset:56
	global_load_b128 v[6:9], v[18:19], off offset:48
	global_load_b128 v[10:13], v[18:19], off offset:32
	global_load_b128 v[14:17], v[18:19], off offset:16
	global_load_b128 v[18:21], v[18:19], off
	s_waitcnt vmcnt(4)
	ds_store_2addr_b32 v22, v2, v3 offset0:14 offset1:15
	ds_store_2addr_b32 v22, v4, v5 offset0:16 offset1:17
	s_waitcnt vmcnt(3)
	ds_store_2addr_b32 v22, v8, v9 offset0:14 offset1:15
	ds_store_2addr_b32 v22, v6, v7 offset0:12 offset1:13
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v22, v12, v13 offset0:10 offset1:11
	ds_store_2addr_b32 v22, v10, v11 offset0:8 offset1:9
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v22, v16, v17 offset0:6 offset1:7
	ds_store_2addr_b32 v22, v14, v15 offset0:4 offset1:5
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v22, v20, v21 offset0:2 offset1:3
	ds_store_2addr_b32 v22, v18, v19 offset1:1
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB1_17
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_lt_i32 s3, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, s0, s6, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	global_load_b32 v2, v[2:3], off
	v_mov_b32_e32 v3, 0
	s_cbranch_scc1 .LBB1_11
; %bb.4:                                ; %.preheader.preheader
	s_mov_b32 s2, 0
.LBB1_5:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v3
	s_add_i32 s6, s3, -1
	s_mov_b32 s7, 0
	s_lshl_b32 s8, s6, 2
                                        ; implicit-def: $sgpr9
.LBB1_6:                                ;   Parent Loop BB1_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v4
	s_or_b32 s9, s9, exec_lo
	s_mov_b32 s10, exec_lo
	v_mul_lo_u32 v4, 0x48, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, s8, 0, v4
	ds_load_b32 v4, v4 offset:8
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u32_e32 -1, v4
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=2
	v_mad_u64_u32 v[5:6], null, 0x48, v4, s[2:3]
	s_and_not1_b32 s9, s9, exec_lo
	ds_load_b32 v5, v5
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ge_i32_e64 s0, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s9, s9, s0
.LBB1_8:                                ; %Flow69
                                        ;   in Loop: Header=BB1_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s9
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_6
; %bb.9:                                ; %.critedge
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmp_lt_i32 s3, 2
	s_cbranch_scc1 .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_5 Depth=1
	s_mov_b32 s3, s6
	s_branch .LBB1_5
.LBB1_11:                               ; %._crit_edge
	s_mov_b32 s2, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, 0x48, v3, s[2:3]
	ds_load_b32 v4, v4 offset:8
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e64 s3, -1, v4
	v_cmpx_ne_u32_e32 -1, v4
	s_cbranch_execz .LBB1_13
; %bb.12:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, 0x48, v4, s[2:3]
	s_and_not1_b32 s2, s3, exec_lo
	ds_load_b32 v3, v5
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u32_e64 s0, v3, v2
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s2, s0
.LBB1_13:                               ; %Flow66
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB1_17
; %bb.14:
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, 0x48, v1, s[2:3]
	ds_load_b32 v3, v2 offset:4
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_17
; %bb.15:                               ; %.lr.ph.preheader
	v_mul_lo_u32 v3, 0x48, v4
	v_mul_lo_u32 v4, 0x48, v1
	v_add_nc_u32_e32 v2, 4, v2
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v3, v3, 0, 8
	v_add3_u32 v4, v4, 0, 8
.LBB1_16:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v5, v3
	s_add_i32 s3, s3, 1
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v4, v5
	ds_store_b32 v3, v1
	ds_load_b32 v5, v2
	v_add_nc_u32_e32 v3, 4, v3
	v_add_nc_u32_e32 v4, 4, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e64 s0, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_16
.LBB1_17:                               ; %Flow73
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_19
; %bb.18:
	v_mad_u32_u24 v0, 0x48, v0, 0
	v_mad_i64_i32 v[22:23], null, 0x48, v1, s[4:5]
	ds_load_2addr_b32 v[2:3], v0 offset0:14 offset1:15
	ds_load_2addr_b32 v[4:5], v0 offset0:16 offset1:17
	ds_load_2addr_b32 v[6:7], v0 offset0:12 offset1:13
	ds_load_2addr_b32 v[12:13], v0 offset0:10 offset1:11
	ds_load_2addr_b32 v[10:11], v0 offset0:8 offset1:9
	ds_load_2addr_b32 v[16:17], v0 offset0:6 offset1:7
	ds_load_2addr_b32 v[14:15], v0 offset0:4 offset1:5
	ds_load_2addr_b32 v[20:21], v0 offset0:2 offset1:3
	ds_load_2addr_b32 v[18:19], v0 offset1:1
	s_waitcnt lgkmcnt(8)
	v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v9, v3
	s_waitcnt lgkmcnt(7)
	global_store_b128 v[22:23], v[2:5], off offset:56
	s_waitcnt lgkmcnt(6)
	global_store_b128 v[22:23], v[6:9], off offset:48
	s_waitcnt lgkmcnt(4)
	global_store_b128 v[22:23], v[10:13], off offset:32
	s_waitcnt lgkmcnt(2)
	global_store_b128 v[22:23], v[14:17], off offset:16
	s_waitcnt lgkmcnt(0)
	global_store_b128 v[22:23], v[18:21], off
.LBB1_19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14insertSkipListP4NodePiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14insertSkipListP4NodePiii, .Lfunc_end1-_Z14insertSkipListP4NodePiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 18
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18initializeSkipListP4Nodei
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18initializeSkipListP4Nodei.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14insertSkipListP4NodePiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14insertSkipListP4NodePiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
