#include <iostream>
#include <cuda_runtime.h>
#include <cooperative_groups.h>

namespace cg = cooperative_groups;

#define NUM_PATHS 512
#define NUM_STEPS 100
#define BLOCK_SIZE 256

__device__ float generate_random(cg::thread_block_tile<32> tile, unsigned int &seed) {
    // Simple LCG generator for demonstration purposes
    unsigned int a = 1664525;
    unsigned int c = 1013904223;
    seed = a * seed + c;
    float r = seed / (float)0xFFFFFFFF;
    return r;
}

__global__ void monte_carlo_kernel(float *prices, float S0, float mu, float sigma, float T) {
    extern __shared__ float shared_prices[];

    int path_id = blockIdx.x * blockDim.x + threadIdx.x;
    unsigned int seed = path_id * 12345 + 67890; // Initialize seed for each path

    float S = S0;
    float dt = T / NUM_STEPS;

    cg::thread_block cta = cg::this_thread_block();
    cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

    for (int step = 0; step < NUM_STEPS; ++step) {
        float epsilon = generate_random(tile32, seed);
        float dS = S * (mu * dt + sigma * sqrtf(dt) * (epsilon - 0.5f));
        S += dS;
        cg::sync(tile32);
    }

    if (threadIdx.x < NUM_PATHS / blockDim.x) {
        shared_prices[threadIdx.x] = S;
        cg::sync(cta);
        if (threadIdx.x == 0) {
            float sum = 0.0f;
            for (int i = 0; i < NUM_PATHS / blockDim.x; ++i) {
                sum += shared_prices[i];
            }
            prices[blockIdx.x] = sum / (NUM_PATHS / blockDim.x);
        }
    }
}

int main() {
    float *d_prices, *h_prices;
    float S0 = 100.0f; // Initial stock price
    float mu = 0.05f;  // Drift coefficient
    float sigma = 0.2f; // Volatility coefficient
    float T = 1.0f;    // Time to maturity

    h_prices = new float[NUM_PATHS / BLOCK_SIZE];
    cudaMalloc((void **)&d_prices, (NUM_PATHS / BLOCK_SIZE) * sizeof(float));

    monte_carlo_kernel<<<NUM_PATHS / BLOCK_SIZE, BLOCK_SIZE, BLOCK_SIZE * sizeof(float)>>>(d_prices, S0, mu, sigma, T);

    cudaMemcpy(h_prices, d_prices, (NUM_PATHS / BLOCK_SIZE) * sizeof(float), cudaMemcpyDeviceToHost);

    float final_price = 0.0f;
    for (int i = 0; i < NUM_PATHS / BLOCK_SIZE; ++i) {
        final_price += h_prices[i];
    }
    final_price /= (NUM_PATHS / BLOCK_SIZE);

    std::cout << "Estimated option price: " << final_price << std::endl;

    cudaFree(d_prices);
    delete[] h_prices;

    return 0;
}
	.file	"tmpxft_00130aa2_00000000-6_cuda_code_040226.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6836:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE6836:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15generate_randomN18cooperative_groups4__v117thread_block_tileILj32EvEERj
	.type	_Z15generate_randomN18cooperative_groups4__v117thread_block_tileILj32EvEERj, @function
_Z15generate_randomN18cooperative_groups4__v117thread_block_tileILj32EvEERj:
.LFB6832:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE6832:
	.size	_Z15generate_randomN18cooperative_groups4__v117thread_block_tileILj32EvEERj, .-_Z15generate_randomN18cooperative_groups4__v117thread_block_tileILj32EvEERj
	.globl	_Z42__device_stub__Z18monte_carlo_kernelPfffffPfffff
	.type	_Z42__device_stub__Z18monte_carlo_kernelPfffffPfffff, @function
_Z42__device_stub__Z18monte_carlo_kernelPfffffPfffff:
.LFB6858:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movss	%xmm0, 20(%rsp)
	leaq	60(%rsp), %rsi
	leaq	48(%rsp), %rdi
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movss	%xmm3, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18monte_carlo_kernelPfffff(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6858:
	.size	_Z42__device_stub__Z18monte_carlo_kernelPfffffPfffff, .-_Z42__device_stub__Z18monte_carlo_kernelPfffffPfffff
	.globl	_Z18monte_carlo_kernelPfffff
	.type	_Z18monte_carlo_kernelPfffff, @function
_Z18monte_carlo_kernelPfffff:
.LFB6859:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z18monte_carlo_kernelPfffffPfffff
	.cfi_endproc
.LFE6859:
	.size	_Z18monte_carlo_kernelPfffff, .-_Z18monte_carlo_kernelPfffff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC6:
	.string	"Estimated option price: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB6833:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$8, %edi
	subq	$64, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	leaq	24(%rsp), %rdi
	movl	$8, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movl	$16777217, %edx
	movl	$2147483649, %edi
	xorl	%r9d, %r9d
	salq	$8, %rdx
	addq	%rdi, %rdi
	movl	$1024, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movss	.LC0(%rip), %xmm3
	movss	.LC1(%rip), %xmm2
	movss	.LC2(%rip), %xmm1
	movss	.LC3(%rip), %xmm0
	movq	24(%rsp), %rdi
	call	_Z42__device_stub__Z18monte_carlo_kernelPfffffPfffff
.L11:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$8, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	xorps	%xmm0, %xmm0
	addss	(%rbx), %xmm0
	addss	4(%rbx), %xmm0
	mulss	.LC5(%rip), %xmm0
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movss	%xmm0, 12(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	12(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$64, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6833:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z18monte_carlo_kernelPfffff"
.LC8:
	.string	"_ZN50_INTERNAL_c82a3002_19_cuda_code_040226_cu_7374bc644cuda3std3__419piecewise_constructE"
.LC9:
	.string	"_ZN50_INTERNAL_c82a3002_19_cuda_code_040226_cu_7374bc644cuda3std6ranges3__45__cpo4swapE"
.LC10:
	.string	"_ZN50_INTERNAL_c82a3002_19_cuda_code_040226_cu_7374bc644cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6861:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18monte_carlo_kernelPfffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE6861:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	1045220557
	.align 4
.LC2:
	.long	1028443341
	.align 4
.LC3:
	.long	1120403456
	.align 4
.LC5:
	.long	1056964608
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>

namespace cg = cooperative_groups;

#define NUM_PATHS 512
#define NUM_STEPS 100
#define BLOCK_SIZE 256

__device__ float generate_random(cg::thread_block_tile<32> tile, unsigned int &seed) {
    // Simple LCG generator for demonstration purposes
    unsigned int a = 1664525;
    unsigned int c = 1013904223;
    seed = a * seed + c;
    float r = seed / (float)0xFFFFFFFF;
    return r;
}

__global__ void monte_carlo_kernel(float *prices, float S0, float mu, float sigma, float T) {
    extern __shared__ float shared_prices[];

    int path_id = blockIdx.x * blockDim.x + threadIdx.x;
    unsigned int seed = path_id * 12345 + 67890; // Initialize seed for each path

    float S = S0;
    float dt = T / NUM_STEPS;

    cg::thread_block cta = cg::this_thread_block();
    cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

    for (int step = 0; step < NUM_STEPS; ++step) {
        float epsilon = generate_random(tile32, seed);
        float dS = S * (mu * dt + sigma * sqrtf(dt) * (epsilon - 0.5f));
        S += dS;
        cg::sync(tile32);
    }

    if (threadIdx.x < NUM_PATHS / blockDim.x) {
        shared_prices[threadIdx.x] = S;
        cg::sync(cta);
        if (threadIdx.x == 0) {
            float sum = 0.0f;
            for (int i = 0; i < NUM_PATHS / blockDim.x; ++i) {
                sum += shared_prices[i];
            }
            prices[blockIdx.x] = sum / (NUM_PATHS / blockDim.x);
        }
    }
}

int main() {
    float *d_prices, *h_prices;
    float S0 = 100.0f; // Initial stock price
    float mu = 0.05f;  // Drift coefficient
    float sigma = 0.2f; // Volatility coefficient
    float T = 1.0f;    // Time to maturity

    h_prices = new float[NUM_PATHS / BLOCK_SIZE];
    hipMalloc((void **)&d_prices, (NUM_PATHS / BLOCK_SIZE) * sizeof(float));

    monte_carlo_kernel<<<NUM_PATHS / BLOCK_SIZE, BLOCK_SIZE, BLOCK_SIZE * sizeof(float)>>>(d_prices, S0, mu, sigma, T);

    hipMemcpy(h_prices, d_prices, (NUM_PATHS / BLOCK_SIZE) * sizeof(float), hipMemcpyDeviceToHost);

    float final_price = 0.0f;
    for (int i = 0; i < NUM_PATHS / BLOCK_SIZE; ++i) {
        final_price += h_prices[i];
    }
    final_price /= (NUM_PATHS / BLOCK_SIZE);

    std::cout << "Estimated option price: " << final_price << std::endl;

    hipFree(d_prices);
    delete[] h_prices;

    return 0;
}
	.text
	.file	"cuda_code_040226.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__monte_carlo_kernelPfffff # -- Begin function _Z33__device_stub__monte_carlo_kernelPfffff
	.type	_Z33__device_stub__monte_carlo_kernelPfffff,@function
_Z33__device_stub__monte_carlo_kernelPfffff: # @_Z33__device_stub__monte_carlo_kernelPfffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	16(%rsp), %rdx
	movss	%xmm1, (%rdx)
	leaq	12(%rsp), %rsi
	movss	%xmm2, (%rsi)
	leaq	8(%rsp), %rdi
	movss	%xmm3, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdi, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18monte_carlo_kernelPfffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__monte_carlo_kernelPfffff, .Lfunc_end0-_Z33__device_stub__monte_carlo_kernelPfffff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x42c80000                      # float 100
.LCPI1_1:
	.long	0x3d4ccccd                      # float 0.0500000007
.LCPI1_2:
	.long	0x3e4ccccd                      # float 0.200000003
.LCPI1_3:
	.long	0x3f800000                      # float 1
.LCPI1_4:
	.long	0x3f000000                      # float 0.5
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$8, %edi
	callq	_Znam
	movq	%rax, %rbx
	leaq	8(%rsp), %rdi
	movl	$8, %esi
	callq	hipMalloc
	movabsq	$4294967298, %rdi               # imm = 0x100000002
	leaq	254(%rdi), %rdx
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	8(%rsp), %rdi
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movss	.LCPI1_2(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movss	.LCPI1_3(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	callq	_Z33__device_stub__monte_carlo_kernelPfffff
.LBB1_2:
	movq	8(%rsp), %rsi
	movl	$8, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	addss	(%rbx), %xmm0
	addss	4(%rbx), %xmm0
	mulss	.LCPI1_4(%rip), %xmm0
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$24, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	20(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18monte_carlo_kernelPfffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18monte_carlo_kernelPfffff,@object # @_Z18monte_carlo_kernelPfffff
	.section	.rodata,"a",@progbits
	.globl	_Z18monte_carlo_kernelPfffff
	.p2align	3, 0x0
_Z18monte_carlo_kernelPfffff:
	.quad	_Z33__device_stub__monte_carlo_kernelPfffff
	.size	_Z18monte_carlo_kernelPfffff, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Estimated option price: "
	.size	.L.str, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18monte_carlo_kernelPfffff"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__monte_carlo_kernelPfffff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18monte_carlo_kernelPfffff
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18monte_carlo_kernelPfffff ; -- Begin function _Z18monte_carlo_kernelPfffff
	.globl	_Z18monte_carlo_kernelPfffff
	.p2align	8
	.type	_Z18monte_carlo_kernelPfffff,@function
_Z18monte_carlo_kernelPfffff:           ; @_Z18monte_carlo_kernelPfffff
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s3, s[0:1], 0x24
	s_mov_b32 s2, 0x42c80000
	s_mov_b32 s8, s15
	s_waitcnt lgkmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_div_scale_f32 v1, null, s2, s2, s7
	v_div_scale_f32 v4, vcc_lo, s7, 0x42c80000, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	v_fmac_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v4, v2
	v_fma_f32 v5, -v1, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v5, v2
	v_fma_f32 v1, -v1, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v2, v3
	v_div_fixup_f32 v5, v1, 0x42c80000, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v1, v5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, 1, v2
	v_add_nc_u32_e32 v3, -1, v2
	v_fma_f32 v7, -v4, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v3, v2, v1
	v_cmp_ge_f32_e64 s2, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v2, v2, v3, s2
	v_cmp_lt_f32_e64 s2, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v2, v4, s2
	s_and_b32 s2, s3, 0xffff
	s_movk_i32 s3, 0x3039
	v_mad_u64_u32 v[3:4], null, s8, s2, v[0:1]
	v_mul_f32_e32 v6, 0x37800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v6, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v1, 0x260
	v_cndmask_b32_e32 v4, v2, v1, vcc_lo
	v_mad_u64_u32 v[1:2], null, v3, s3, 0x10932
	v_dual_mul_f32 v3, s5, v5 :: v_dual_mov_b32 v2, s4
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v4, s6, v4
	s_movk_i32 s3, 0x64
	s_mov_b32 s4, 0x19660d
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, v1, s4, 0x3c6ef35f
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s3, 0
	v_cvt_f32_u32_e32 v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, 0x2f800000, v1, -0.5
	v_fma_f32 v6, v4, v1, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v1, v5 :: v_dual_fmac_f32 v2, v2, v6
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	v_cvt_f32_u32_e32 v1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x44000000, v3
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v3, v1, 0x44000000
	v_cvt_u32_f32_e32 v3, v3
	v_cmp_ge_f32_e64 s2, |v4|, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v3
	s_cmp_lg_u32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_addc_u32 s2, s3, 0
	s_mov_b32 s3, exec_lo
	s_and_b32 s2, s2, 0xffff
	v_cmpx_gt_u32_e64 s2, v0
	s_cbranch_execz .LBB0_7
; %bb.3:
	v_lshl_add_u32 v1, v0, 2, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader.preheader
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_mov_b32 s4, 0
.LBB0_5:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s4
	s_add_i32 s3, s3, 1
	s_add_i32 s4, s4, 4
	s_cmp_ge_u32 s3, s2
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v1
	s_cbranch_scc0 .LBB0_5
; %bb.6:
	v_cvt_f32_u32_e32 v1, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b32 s9, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[2:3], s[8:9], 2
	v_div_scale_f32 v2, null, v1, v1, v0
	v_div_scale_f32 v5, vcc_lo, v0, v1, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v3
	v_mul_f32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v2, v4, v5
	v_fmac_f32_e32 v4, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v4, v5
	v_div_fmas_f32 v2, v2, v3, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v0, v2, v1, v0
	v_mov_b32_e32 v1, 0
	global_store_b32 v1, v0, s[0:1]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18monte_carlo_kernelPfffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18monte_carlo_kernelPfffff, .Lfunc_end0-_Z18monte_carlo_kernelPfffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 772
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         144
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18monte_carlo_kernelPfffff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18monte_carlo_kernelPfffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
