#include <iostream>
#include <cuda_runtime.h>

// Define the size of the 32D grid
#define GRID_SIZE 128

// Define the radius of the stencil
#define RADIUS 11

// Define the total size of the stencil
#define STENCIL_SIZE ((2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1))

// Kernel to perform the 32D stencil computation
__global__ void stencil32DKernel(float* input, float* output, int size) {
    // Calculate the global index for each dimension
    int idx0 = blockIdx.x * blockDim.x + threadIdx.x;
    int idx1 = blockIdx.y * blockDim.y + threadIdx.y;
    int idx2 = blockIdx.z * blockDim.z + threadIdx.z;

    // Check if the thread is within the grid bounds
    if (idx0 < size && idx1 < size && idx2 < size) {
        float sum = 0.0f;
        // Perform the stencil operation
        for (int i = -RADIUS; i <= RADIUS; ++i) {
            for (int j = -RADIUS; j <= RADIUS; ++j) {
                for (int k = -RADIUS; k <= RADIUS; ++k) {
                    // Assuming the grid is padded to handle boundary conditions
                    int x = idx0 + i;
                    int y = idx1 + j;
                    int z = idx2 + k;
                    // Clamp the indices to the grid size
                    x = max(0, min(x, size - 1));
                    y = max(0, min(y, size - 1));
                    z = max(0, min(z, size - 1));
                    sum += input[z * size * size + y * size + x];
                }
            }
        }
        output[idx2 * size * size + idx1 * size + idx0] = sum / STENCIL_SIZE;
    }
}

int main() {
    // Define the size of the grid
    int size = GRID_SIZE;

    // Allocate memory for the input and output arrays using Unified Memory
    float *input, *output;
    cudaMallocManaged(&input, size * size * size * sizeof(float));
    cudaMallocManaged(&output, size * size * size * sizeof(float));

    // Initialize the input array with some values
    for (int i = 0; i < size * size * size; ++i) {
        input[i] = 1.0f; // Simple initialization
    }

    // Define the block size
    dim3 blockSize(8, 8, 8);
    // Calculate the grid size
    dim3 gridSize((size + blockSize.x - 1) / blockSize.x,
                 (size + blockSize.y - 1) / blockSize.y,
                 (size + blockSize.z - 1) / blockSize.z);

    // Launch the kernel
    stencil32DKernel<<<gridSize, blockSize>>>(input, output, size);

    // Check for errors in the kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Wait for the GPU to finish
    cudaDeviceSynchronize();

    // Free the Unified Memory
    cudaFree(input);
    cudaFree(output);

    return 0;
}
	.file	"tmpxft_00045764_00000000-6_cuda_code_031560.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z16stencil32DKernelPfS_iPfS_i
	.type	_Z39__device_stub__Z16stencil32DKernelPfS_iPfS_i, @function
_Z39__device_stub__Z16stencil32DKernelPfS_iPfS_i:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z16stencil32DKernelPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z39__device_stub__Z16stencil32DKernelPfS_iPfS_i, .-_Z39__device_stub__Z16stencil32DKernelPfS_iPfS_i
	.globl	_Z16stencil32DKernelPfS_i
	.type	_Z16stencil32DKernelPfS_i, @function
_Z16stencil32DKernelPfS_i:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z16stencil32DKernelPfS_iPfS_i
	.cfi_endproc
.LFE3661:
	.size	_Z16stencil32DKernelPfS_i, .-_Z16stencil32DKernelPfS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1, %edx
	movl	$8388608, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMallocManaged@PLT
	movl	$1, %edx
	leaq	8(%rsp), %rdi
	movl	$8388608, %esi
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rdx
	movss	.LC0(%rip), %xmm0
	xorl	%eax, %eax
.L9:
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$2097152, %rax
	jne	.L9
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8, %ecx
	movl	$16, %esi
	movabsq	$34359738376, %rdx
	movabsq	$68719476752, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$128, %edx
	call	_Z39__device_stub__Z16stencil32DKernelPfS_iPfS_i
.L10:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L11
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L11:
	call	cudaDeviceSynchronize@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L8:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z16stencil32DKernelPfS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16stencil32DKernelPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

// Define the size of the 32D grid
#define GRID_SIZE 128

// Define the radius of the stencil
#define RADIUS 11

// Define the total size of the stencil
#define STENCIL_SIZE ((2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1) * (2 * RADIUS + 1))

// Kernel to perform the 32D stencil computation
__global__ void stencil32DKernel(float* input, float* output, int size) {
    // Calculate the global index for each dimension
    int idx0 = blockIdx.x * blockDim.x + threadIdx.x;
    int idx1 = blockIdx.y * blockDim.y + threadIdx.y;
    int idx2 = blockIdx.z * blockDim.z + threadIdx.z;

    // Check if the thread is within the grid bounds
    if (idx0 < size && idx1 < size && idx2 < size) {
        float sum = 0.0f;
        // Perform the stencil operation
        for (int i = -RADIUS; i <= RADIUS; ++i) {
            for (int j = -RADIUS; j <= RADIUS; ++j) {
                for (int k = -RADIUS; k <= RADIUS; ++k) {
                    // Assuming the grid is padded to handle boundary conditions
                    int x = idx0 + i;
                    int y = idx1 + j;
                    int z = idx2 + k;
                    // Clamp the indices to the grid size
                    x = max(0, min(x, size - 1));
                    y = max(0, min(y, size - 1));
                    z = max(0, min(z, size - 1));
                    sum += input[z * size * size + y * size + x];
                }
            }
        }
        output[idx2 * size * size + idx1 * size + idx0] = sum / STENCIL_SIZE;
    }
}

int main() {
    // Define the size of the grid
    int size = GRID_SIZE;

    // Allocate memory for the input and output arrays using Unified Memory
    float *input, *output;
    hipMallocManaged(&input, size * size * size * sizeof(float));
    hipMallocManaged(&output, size * size * size * sizeof(float));

    // Initialize the input array with some values
    for (int i = 0; i < size * size * size; ++i) {
        input[i] = 1.0f; // Simple initialization
    }

    // Define the block size
    dim3 blockSize(8, 8, 8);
    // Calculate the grid size
    dim3 gridSize((size + blockSize.x - 1) / blockSize.x,
                 (size + blockSize.y - 1) / blockSize.y,
                 (size + blockSize.z - 1) / blockSize.z);

    // Launch the kernel
    stencil32DKernel<<<gridSize, blockSize>>>(input, output, size);

    // Check for errors in the kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Wait for the GPU to finish
    hipDeviceSynchronize();

    // Free the Unified Memory
    hipFree(input);
    hipFree(output);

    return 0;
}
	.text
	.file	"cuda_code_031560.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z31__device_stub__stencil32DKernelPfS_i # -- Begin function _Z31__device_stub__stencil32DKernelPfS_i
	.type	_Z31__device_stub__stencil32DKernelPfS_i,@function
_Z31__device_stub__stencil32DKernelPfS_i: # @_Z31__device_stub__stencil32DKernelPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16stencil32DKernelPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__stencil32DKernelPfS_i, .Lfunc_end0-_Z31__device_stub__stencil32DKernelPfS_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	8(%rsp), %rbx
	movl	$8388608, %esi                  # imm = 0x800000
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movl	$8388608, %esi                  # imm = 0x800000
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%eax, %eax
	movq	(%rbx), %rcx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rcx,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$2097152, %rax                  # imm = 0x200000
	jne	.LBB1_1
# %bb.2:
	movabsq	$68719476752, %rdi              # imm = 0x1000000010
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$16, %esi
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$128, %edx
	callq	_Z31__device_stub__stencil32DKernelPfS_i
.LBB1_4:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_9
# %bb.5:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_6
# %bb.7:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_8
.LBB1_9:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB1_10
.LBB1_6:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_10:
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16stencil32DKernelPfS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16stencil32DKernelPfS_i,@object # @_Z16stencil32DKernelPfS_i
	.section	.rodata,"a",@progbits
	.globl	_Z16stencil32DKernelPfS_i
	.p2align	3, 0x0
_Z16stencil32DKernelPfS_i:
	.quad	_Z31__device_stub__stencil32DKernelPfS_i
	.size	_Z16stencil32DKernelPfS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16stencil32DKernelPfS_i"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__stencil32DKernelPfS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16stencil32DKernelPfS_i
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16stencil32DKernelPfS_i ; -- Begin function _Z16stencil32DKernelPfS_i
	.globl	_Z16stencil32DKernelPfS_i
	.p2align	8
	.type	_Z16stencil32DKernelPfS_i,@function
_Z16stencil32DKernelPfS_i:              ; @_Z16stencil32DKernelPfS_i
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x24
	s_load_b32 s4, s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_bfe_u32 v4, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max3_i32 v3, v0, v1, v2
	v_cmpx_gt_i32_e64 s4, v3
	s_cbranch_execz .LBB0_8
; %bb.1:                                ; %.preheader52
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v5, 0
	s_add_i32 s5, s4, -1
	s_mov_b32 s6, -11
.LBB0_2:                                ; %.preheader51
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_4 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s6, v0
	s_mov_b32 s7, -11
	v_minmax_i32 v3, v3, s5, 0
.LBB0_3:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_4 Depth 3
	v_add_nc_u32_e32 v4, s7, v1
	s_mov_b32 s8, -11
	s_delay_alu instid0(VALU_DEP_1)
	v_minmax_i32 v4, v4, s5, 0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v6, s8, v2
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s8, 12
	v_minmax_i32 v8, v6, s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, s4, v[4:5]
	v_mad_u64_u32 v[7:8], null, v6, s4, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[6:7], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v6
	s_cbranch_scc0 .LBB0_4
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, 12
	s_cbranch_scc0 .LBB0_3
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 12
	s_cbranch_scc0 .LBB0_2
; %bb.7:
	v_div_scale_f32 v6, null, 0x4efd560d, 0x4efd560d, v5
	v_div_scale_f32 v8, vcc_lo, v5, 0x4efd560d, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v6, v7, 1.0
	v_fmac_f32_e32 v7, v3, v7
	v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, v8, v7
	v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v6, v4, v8
	v_fmac_f32_e32 v4, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_fma_f32 v0, -v6, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v3, v0, v7, v4
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v2, v3, 0x4efd560d, v5
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16stencil32DKernelPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16stencil32DKernelPfS_i, .Lfunc_end0-_Z16stencil32DKernelPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 488
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16stencil32DKernelPfS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16stencil32DKernelPfS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
