// navier_stokes.cu
#include <iostream>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

#define N 16384
#define BLOCK_SIZE 256

__global__ void navierStokesKernel(float* u, float* v, float* p, float* u_new, float* v_new, float* p_new, float dt, float dx, float dy, float Re) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < N) {
        // Simple finite difference approximation for Navier-Stokes equations
        // This is a very basic and simplified version for demonstration purposes
        int i = idx % N;
        int j = idx / N;

        float u_n = u[idx];
        float v_n = v[idx];
        float p_n = p[idx];

        // Compute new velocities using Euler method
        float du_dx = (u[(i + 1) % N + j * N] - u[(i - 1 + N) % N + j * N]) / (2 * dx);
        float du_dy = (u[i + ((j + 1) % N) * N] - u[i + ((j - 1 + N) % N) * N]) / (2 * dy);
        float dv_dx = (v[(i + 1) % N + j * N] - v[(i - 1 + N) % N + j * N]) / (2 * dx);
        float dv_dy = (v[i + ((j + 1) % N) * N] - v[i + ((j - 1 + N) % N) * N]) / (2 * dy);

        float dp_dx = (p[(i + 1) % N + j * N] - p[(i - 1 + N) % N + j * N]) / (2 * dx);
        float dp_dy = (p[i + ((j + 1) % N) * N] - p[i + ((j - 1 + N) % N) * N]) / (2 * dy);

        float d2u_dx2 = (u[(i + 1) % N + j * N] - 2 * u_n + u[(i - 1 + N) % N + j * N]) / (dx * dx);
        float d2u_dy2 = (u[i + ((j + 1) % N) * N] - 2 * u_n + u[i + ((j - 1 + N) % N) * N]) / (dy * dy);
        float d2v_dx2 = (v[(i + 1) % N + j * N] - 2 * v_n + v[(i - 1 + N) % N + j * N]) / (dx * dx);
        float d2v_dy2 = (v[i + ((j + 1) % N) * N] - 2 * v_n + v[i + ((j - 1 + N) % N) * N]) / (dy * dy);

        u_new[idx] = u_n - dt * (u_n * du_dx + v_n * du_dy) + (dt / Re) * (d2u_dx2 + d2u_dy2) - dt * dp_dx;
        v_new[idx] = v_n - dt * (u_n * dv_dx + v_n * dv_dy) + (dt / Re) * (d2v_dx2 + d2v_dy2) - dt * dp_dy;
    }
}

__global__ void updateKernel(float* u, float* v, float* p, float* u_new, float* v_new, float* p_new) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < N) {
        u[idx] = u_new[idx];
        v[idx] = v_new[idx];
        p[idx] = p_new[idx];
    }
}

int main() {
    // Initialize device and check for errors
    int device = 0;
    cudaSetDevice(device);
    cudaDeviceProp deviceProp;
    cudaGetDeviceProperties(&deviceProp, device);
    if (!deviceProp.managedMemory) {
        std::cerr << "Device does not support Unified Memory" << std::endl;
        return EXIT_FAILURE;
    }

    // Allocate Unified Memory -- accessible from CPU or GPU
    float *u, *v, *p, *u_new, *v_new, *p_new;
    cudaMallocManaged(&u, N * sizeof(float));
    cudaMallocManaged(&v, N * sizeof(float));
    cudaMallocManaged(&p, N * sizeof(float));
    cudaMallocManaged(&u_new, N * sizeof(float));
    cudaMallocManaged(&v_new, N * sizeof(float));
    cudaMallocManaged(&p_new, N * sizeof(float));

    // Initialize data
    for (int i = 0; i < N; i++) {
        u[i] = 0.0f;
        v[i] = 0.0f;
        p[i] = 0.0f;
        u_new[i] = 0.0f;
        v_new[i] = 0.0f;
        p_new[i] = 0.0f;
    }

    // Simulation parameters
    float dt = 0.01f;
    float dx = 1.0f;
    float dy = 1.0f;
    float Re = 100.0f;

    // Launch kernels
    int numBlocks = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
    for (int step = 0; step < 100; step++) {
        navierStokesKernel<<<numBlocks, BLOCK_SIZE>>>(u, v, p, u_new, v_new, p_new, dt, dx, dy, Re);
        cudaError_t err = cudaGetLastError();
        if (err != cudaSuccess) {
            std::cerr << "Failed to launch navierStokesKernel (error code " << err << ")" << std::endl;
            exit(EXIT_FAILURE);
        }

        updateKernel<<<numBlocks, BLOCK_SIZE>>>(u, v, p, u_new, v_new, p_new);
        err = cudaGetLastError();
        if (err != cudaSuccess) {
            std::cerr << "Failed to launch updateKernel (error code " << err << ")" << std::endl;
            exit(EXIT_FAILURE);
        }

        // Synchronize to make sure all threads are done before continuing
        cudaDeviceSynchronize();
    }

    // Free memory
    cudaFree(u);
    cudaFree(v);
    cudaFree(p);
    cudaFree(u_new);
    cudaFree(v_new);
    cudaFree(p_new);

    return 0;
}
	.file	"tmpxft_001c557f_00000000-6_cuda_code_061963.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
	.type	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff, @function
_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff:
.LFB4034:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movss	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z18navierStokesKernelPfS_S_S_S_S_ffff(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4034:
	.size	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff, .-_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
	.globl	_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.type	_Z18navierStokesKernelPfS_S_S_S_S_ffff, @function
_Z18navierStokesKernelPfS_S_S_S_S_ffff:
.LFB4035:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
	.cfi_endproc
.LFE4035:
	.size	_Z18navierStokesKernelPfS_S_S_S_S_ffff, .-_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.globl	_Z42__device_stub__Z12updateKernelPfS_S_S_S_S_PfS_S_S_S_S_
	.type	_Z42__device_stub__Z12updateKernelPfS_S_S_S_S_PfS_S_S_S_S_, @function
_Z42__device_stub__Z12updateKernelPfS_S_S_S_S_PfS_S_S_S_S_:
.LFB4036:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12updateKernelPfS_S_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4036:
	.size	_Z42__device_stub__Z12updateKernelPfS_S_S_S_S_PfS_S_S_S_S_, .-_Z42__device_stub__Z12updateKernelPfS_S_S_S_S_PfS_S_S_S_S_
	.globl	_Z12updateKernelPfS_S_S_S_S_
	.type	_Z12updateKernelPfS_S_S_S_S_, @function
_Z12updateKernelPfS_S_S_S_S_:
.LFB4037:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z12updateKernelPfS_S_S_S_S_PfS_S_S_S_S_
	.cfi_endproc
.LFE4037:
	.size	_Z12updateKernelPfS_S_S_S_S_, .-_Z12updateKernelPfS_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Device does not support Unified Memory"
.LC5:
	.string	"Failed to launch navierStokesKernel (error code "
.LC6:
	.string	")"
.LC7:
	.string	"Failed to launch updateKernel (error code "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4009:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$1120, %rsp
	.cfi_def_cfa_offset 1152
	movq	%fs:40, %rax
	movq	%rax, 1112(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	xorl	%esi, %esi
	leaq	80(%rsp), %rdi
	call	cudaGetDeviceProperties_v2@PLT
	cmpl	$0, 732(%rsp)
	jne	.L14
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %eax
	jmp	.L13
.L14:
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$65536, %esi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$65536, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$65536, %esi
	call	cudaMallocManaged@PLT
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	movl	$65536, %esi
	call	cudaMallocManaged@PLT
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	movl	$65536, %esi
	call	cudaMallocManaged@PLT
	leaq	48(%rsp), %rdi
	movl	$1, %edx
	movl	$65536, %esi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %r11
	movq	16(%rsp), %r10
	movq	24(%rsp), %r9
	movq	32(%rsp), %r8
	leaq	65535(%r11), %rbp
	movq	40(%rsp), %rsi
	movq	48(%rsp), %rdx
	leaq	65535(%r10), %rbx
	movq	%rbp, %rax
	movq	%rbp, %r12
	leaq	65535(%r9), %rdi
	subq	%r10, %rax
	leaq	65535(%r8), %rcx
	cmpq	$131070, %rax
	seta	%al
	subq	%r9, %r12
	cmpq	$131070, %r12
	seta	%r12b
	andl	%r12d, %eax
	movq	%rbp, %r12
	subq	%r8, %r12
	cmpq	$131070, %r12
	seta	%r12b
	andl	%r12d, %eax
	movq	%rbp, %r12
	subq	%rsi, %r12
	cmpq	$131070, %r12
	seta	%r12b
	subq	%rdx, %rbp
	andl	%r12d, %eax
	cmpq	$131070, %rbp
	seta	%bpl
	andl	%ebp, %eax
	movq	%rbx, %rbp
	subq	%r9, %rbp
	cmpq	$131070, %rbp
	seta	%bpl
	andl	%ebp, %eax
	movq	%rbx, %rbp
	subq	%r8, %rbp
	cmpq	$131070, %rbp
	seta	%bpl
	andl	%ebp, %eax
	movq	%rbx, %rbp
	subq	%rsi, %rbp
	cmpq	$131070, %rbp
	seta	%bpl
	subq	%rdx, %rbx
	andl	%ebp, %eax
	cmpq	$131070, %rbx
	seta	%bl
	andl	%ebx, %eax
	movq	%rdi, %rbx
	subq	%r8, %rbx
	cmpq	$131070, %rbx
	seta	%bl
	andl	%ebx, %eax
	movq	%rdi, %rbx
	subq	%rsi, %rbx
	cmpq	$131070, %rbx
	seta	%bl
	subq	%rdx, %rdi
	andl	%ebx, %eax
	cmpq	$131070, %rdi
	seta	%dil
	andl	%edi, %eax
	movq	%rcx, %rdi
	subq	%rsi, %rdi
	cmpq	$131070, %rdi
	seta	%dil
	subq	%rdx, %rcx
	andl	%edi, %eax
	cmpq	$131070, %rcx
	seta	%cl
	testb	%cl, %al
	je	.L24
	leaq	65535(%rsi), %rax
	subq	%rdx, %rax
	cmpq	$131070, %rax
	jbe	.L24
	xorl	%eax, %eax
	movl	$16384, %ecx
	movq	%r11, %rdi
	rep stosl
	movl	$16384, %ecx
	movq	%r10, %rdi
	rep stosl
	movl	$16384, %ecx
	movq	%r9, %rdi
	rep stosl
	movl	$16384, %ecx
	movq	%r8, %rdi
	rep stosl
	movl	$16384, %ecx
	movq	%rsi, %rdi
	rep stosl
	movl	$16384, %ecx
	movq	%rdx, %rdi
	rep stosl
	jmp	.L17
.L24:
	xorl	%eax, %eax
.L16:
	movl	$0x00000000, (%r11,%rax)
	movl	$0x00000000, (%r10,%rax)
	movl	$0x00000000, (%r9,%rax)
	movl	$0x00000000, (%r8,%rax)
	movl	$0x00000000, (%rsi,%rax)
	movl	$0x00000000, (%rdx,%rax)
	addq	$4, %rax
	cmpq	$65536, %rax
	jne	.L16
.L17:
	movl	$16777217, %ebx
	movl	$100, %r12d
	salq	$8, %rbx
.L22:
	movl	$67108865, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	salq	$6, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rbx, 68(%rsp)
	movl	$1, 76(%rsp)
	movq	%rdi, 56(%rsp)
	movl	$1, 64(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movss	.LC3(%rip), %xmm2
	movss	.LC2(%rip), %xmm3
	movss	.LC4(%rip), %xmm0
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movaps	%xmm2, %xmm1
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
.L18:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L19
	leaq	.LC5(%rip), %rsi
	jmp	.L34
.L19:
	movl	$67108865, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	salq	$6, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rbx, 68(%rsp)
	movl	$1, 76(%rsp)
	movq	%rdi, 56(%rsp)
	movl	$1, 64(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	48(%rsp), %r9
	movq	40(%rsp), %r8
	movq	32(%rsp), %rcx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z42__device_stub__Z12updateKernelPfS_S_S_S_S_PfS_S_S_S_S_
.L20:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L21
	leaq	.LC7(%rip), %rsi
.L34:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L21:
	call	cudaDeviceSynchronize@PLT
	decl	%r12d
	jne	.L22
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L13:
	movq	1112(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$1120, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4009:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z12updateKernelPfS_S_S_S_S_"
.LC9:
	.string	"_Z18navierStokesKernelPfS_S_S_S_S_ffff"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4039:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12updateKernelPfS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18navierStokesKernelPfS_S_S_S_S_ffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4039:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	1120403456
	.align 4
.LC3:
	.long	1065353216
	.align 4
.LC4:
	.long	1008981770
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// navier_stokes.cu
#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>

#define N 16384
#define BLOCK_SIZE 256

__global__ void navierStokesKernel(float* u, float* v, float* p, float* u_new, float* v_new, float* p_new, float dt, float dx, float dy, float Re) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < N) {
        // Simple finite difference approximation for Navier-Stokes equations
        // This is a very basic and simplified version for demonstration purposes
        int i = idx % N;
        int j = idx / N;

        float u_n = u[idx];
        float v_n = v[idx];
        float p_n = p[idx];

        // Compute new velocities using Euler method
        float du_dx = (u[(i + 1) % N + j * N] - u[(i - 1 + N) % N + j * N]) / (2 * dx);
        float du_dy = (u[i + ((j + 1) % N) * N] - u[i + ((j - 1 + N) % N) * N]) / (2 * dy);
        float dv_dx = (v[(i + 1) % N + j * N] - v[(i - 1 + N) % N + j * N]) / (2 * dx);
        float dv_dy = (v[i + ((j + 1) % N) * N] - v[i + ((j - 1 + N) % N) * N]) / (2 * dy);

        float dp_dx = (p[(i + 1) % N + j * N] - p[(i - 1 + N) % N + j * N]) / (2 * dx);
        float dp_dy = (p[i + ((j + 1) % N) * N] - p[i + ((j - 1 + N) % N) * N]) / (2 * dy);

        float d2u_dx2 = (u[(i + 1) % N + j * N] - 2 * u_n + u[(i - 1 + N) % N + j * N]) / (dx * dx);
        float d2u_dy2 = (u[i + ((j + 1) % N) * N] - 2 * u_n + u[i + ((j - 1 + N) % N) * N]) / (dy * dy);
        float d2v_dx2 = (v[(i + 1) % N + j * N] - 2 * v_n + v[(i - 1 + N) % N + j * N]) / (dx * dx);
        float d2v_dy2 = (v[i + ((j + 1) % N) * N] - 2 * v_n + v[i + ((j - 1 + N) % N) * N]) / (dy * dy);

        u_new[idx] = u_n - dt * (u_n * du_dx + v_n * du_dy) + (dt / Re) * (d2u_dx2 + d2u_dy2) - dt * dp_dx;
        v_new[idx] = v_n - dt * (u_n * dv_dx + v_n * dv_dy) + (dt / Re) * (d2v_dx2 + d2v_dy2) - dt * dp_dy;
    }
}

__global__ void updateKernel(float* u, float* v, float* p, float* u_new, float* v_new, float* p_new) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < N) {
        u[idx] = u_new[idx];
        v[idx] = v_new[idx];
        p[idx] = p_new[idx];
    }
}

int main() {
    // Initialize device and check for errors
    int device = 0;
    hipSetDevice(device);
    hipDeviceProp_t deviceProp;
    hipGetDeviceProperties(&deviceProp, device);
    if (!deviceProp.managedMemory) {
        std::cerr << "Device does not support Unified Memory" << std::endl;
        return EXIT_FAILURE;
    }

    // Allocate Unified Memory -- accessible from CPU or GPU
    float *u, *v, *p, *u_new, *v_new, *p_new;
    hipMallocManaged(&u, N * sizeof(float));
    hipMallocManaged(&v, N * sizeof(float));
    hipMallocManaged(&p, N * sizeof(float));
    hipMallocManaged(&u_new, N * sizeof(float));
    hipMallocManaged(&v_new, N * sizeof(float));
    hipMallocManaged(&p_new, N * sizeof(float));

    // Initialize data
    for (int i = 0; i < N; i++) {
        u[i] = 0.0f;
        v[i] = 0.0f;
        p[i] = 0.0f;
        u_new[i] = 0.0f;
        v_new[i] = 0.0f;
        p_new[i] = 0.0f;
    }

    // Simulation parameters
    float dt = 0.01f;
    float dx = 1.0f;
    float dy = 1.0f;
    float Re = 100.0f;

    // Launch kernels
    int numBlocks = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
    for (int step = 0; step < 100; step++) {
        navierStokesKernel<<<numBlocks, BLOCK_SIZE>>>(u, v, p, u_new, v_new, p_new, dt, dx, dy, Re);
        hipError_t err = hipGetLastError();
        if (err != hipSuccess) {
            std::cerr << "Failed to launch navierStokesKernel (error code " << err << ")" << std::endl;
            exit(EXIT_FAILURE);
        }

        updateKernel<<<numBlocks, BLOCK_SIZE>>>(u, v, p, u_new, v_new, p_new);
        err = hipGetLastError();
        if (err != hipSuccess) {
            std::cerr << "Failed to launch updateKernel (error code " << err << ")" << std::endl;
            exit(EXIT_FAILURE);
        }

        // Synchronize to make sure all threads are done before continuing
        hipDeviceSynchronize();
    }

    // Free memory
    hipFree(u);
    hipFree(v);
    hipFree(p);
    hipFree(u_new);
    hipFree(v_new);
    hipFree(p_new);

    return 0;
}
	.text
	.file	"cuda_code_061963.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff # -- Begin function _Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.type	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff,@function
_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff: # @_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	movq	%rsp, %r14
	movss	%xmm3, (%r14)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18navierStokesKernelPfS_S_S_S_S_ffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff, .Lfunc_end0-_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__updateKernelPfS_S_S_S_S_ # -- Begin function _Z27__device_stub__updateKernelPfS_S_S_S_S_
	.type	_Z27__device_stub__updateKernelPfS_S_S_S_S_,@function
_Z27__device_stub__updateKernelPfS_S_S_S_S_: # @_Z27__device_stub__updateKernelPfS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12updateKernelPfS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__updateKernelPfS_S_S_S_S_, .Lfunc_end1-_Z27__device_stub__updateKernelPfS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x3c23d70a                      # float 0.00999999977
.LCPI2_1:
	.long	0x3f800000                      # float 1
.LCPI2_2:
	.long	0x42c80000                      # float 100
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1528, %rsp                     # imm = 0x5F8
	.cfi_def_cfa_offset 1584
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%r14d, %r14d
	xorl	%edi, %edi
	callq	hipSetDevice
	leaq	56(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	cmpl	$0, 652(%rbx)
	je	.LBB2_1
# %bb.2:
	leaq	8(%rsp), %rdi
	movl	$65536, %esi                    # imm = 0x10000
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	48(%rsp), %rbx
	movl	$65536, %esi                    # imm = 0x10000
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	40(%rsp), %r15
	movl	$65536, %esi                    # imm = 0x10000
	movq	%r15, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	32(%rsp), %r12
	movl	$65536, %esi                    # imm = 0x10000
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	24(%rsp), %r13
	movl	$65536, %esi                    # imm = 0x10000
	movq	%r13, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %rbp
	movl	$65536, %esi                    # imm = 0x10000
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rax
	movq	(%rax), %rax
	movq	(%rbx), %rcx
	movq	(%r15), %rdx
	movq	(%r12), %rsi
	movq	(%r13), %rdi
	movq	(%rbp), %r8
	xorl	%r9d, %r9d
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movl	%r14d, (%rax,%r9)
	movl	%r14d, (%rcx,%r9)
	movl	%r14d, (%rdx,%r9)
	movl	%r14d, (%rsi,%r9)
	movl	%r14d, (%rdi,%r9)
	movl	%r14d, (%r8,%r9)
	addq	$4, %r9
	cmpq	$65536, %r9                     # imm = 0x10000
	jne	.LBB2_3
# %bb.4:                                # %.preheader.preheader
	movl	$100, %r15d
	movabsq	$4294967360, %rbx               # imm = 0x100000040
	leaq	192(%rbx), %r14
.LBB2_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.6:                                #   in Loop: Header=BB2_5 Depth=1
	movq	8(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rcx
	movq	24(%rsp), %r8
	movq	16(%rsp), %r9
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movaps	%xmm1, %xmm2
	movss	.LCPI2_2(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	callq	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
.LBB2_7:                                #   in Loop: Header=BB2_5 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.10:                               #   in Loop: Header=BB2_5 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.11:                               #   in Loop: Header=BB2_5 Depth=1
	movq	8(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rcx
	movq	24(%rsp), %r8
	movq	16(%rsp), %r9
	callq	_Z27__device_stub__updateKernelPfS_S_S_S_S_
.LBB2_12:                               #   in Loop: Header=BB2_5 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_13
# %bb.14:                               #   in Loop: Header=BB2_5 Depth=1
	callq	hipDeviceSynchronize
	decl	%r15d
	jne	.LBB2_5
# %bb.15:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB2_16
.LBB2_1:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$38, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$1, %eax
.LBB2_16:
	addq	$1528, %rsp                     # imm = 0x5F8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_13:
	.cfi_def_cfa_offset 1584
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	jmp	.LBB2_9
.LBB2_8:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
.LBB2_9:
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18navierStokesKernelPfS_S_S_S_S_ffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12updateKernelPfS_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18navierStokesKernelPfS_S_S_S_S_ffff,@object # @_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.section	.rodata,"a",@progbits
	.globl	_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.p2align	3, 0x0
_Z18navierStokesKernelPfS_S_S_S_S_ffff:
	.quad	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.size	_Z18navierStokesKernelPfS_S_S_S_S_ffff, 8

	.type	_Z12updateKernelPfS_S_S_S_S_,@object # @_Z12updateKernelPfS_S_S_S_S_
	.globl	_Z12updateKernelPfS_S_S_S_S_
	.p2align	3, 0x0
_Z12updateKernelPfS_S_S_S_S_:
	.quad	_Z27__device_stub__updateKernelPfS_S_S_S_S_
	.size	_Z12updateKernelPfS_S_S_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Device does not support Unified Memory"
	.size	.L.str, 39

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Failed to launch navierStokesKernel (error code "
	.size	.L.str.1, 49

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	")"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to launch updateKernel (error code "
	.size	.L.str.3, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18navierStokesKernelPfS_S_S_S_S_ffff"
	.size	.L__unnamed_1, 39

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12updateKernelPfS_S_S_S_S_"
	.size	.L__unnamed_2, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.addrsig_sym _Z27__device_stub__updateKernelPfS_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18navierStokesKernelPfS_S_S_S_S_ffff
	.addrsig_sym _Z12updateKernelPfS_S_S_S_S_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18navierStokesKernelPfS_S_S_S_S_ffff ; -- Begin function _Z18navierStokesKernelPfS_S_S_S_S_ffff
	.globl	_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.p2align	8
	.type	_Z18navierStokesKernelPfS_S_S_S_S_ffff,@function
_Z18navierStokesKernelPfS_S_S_S_S_ffff: ; @_Z18navierStokesKernelPfS_S_S_S_S_ffff
; %bb.0:
	s_load_b32 s2, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x4000, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[12:15], s[0:1], 0x30
	s_load_b64 s[16:17], s[0:1], 0x20
	v_lshrrev_b32_e32 v0, 18, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v1, v0
	v_ashrrev_i32_e32 v0, 14, v3
	v_and_b32_e32 v18, 0xffffc000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_i32_i24_e32 v4, 0x4000, v0
	v_add_nc_u32_e32 v5, 1, v0
	v_add_nc_u32_e32 v6, 0x3fff, v0
	v_sub_nc_u32_e32 v7, v1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v0, 18, v5
	v_lshrrev_b32_e32 v4, 18, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u16 v14, v7, 1
	v_add_nc_u32_e32 v8, -1, v7
	v_add_nc_u32_e32 v9, v5, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_nc_u32_e32 v4, v6, v4
	v_ashrrev_i16 v10, 15, v14
	v_bfi_b32 v2, 0x3fff, v8, v3
	v_and_b32_e32 v8, 0x3c000, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v4, 0x3c000, v4
	v_lshrrev_b16 v9, 2, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v2
	v_sub_nc_u32_e32 v8, v5, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v10, v6, v4
	v_add_nc_u16 v9, v14, v9
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_lshl_add_u32 v6, v8, 14, v7
	v_lshl_add_u32 v8, v10, 14, v7
	v_and_b32_e32 v15, 0xffffc000, v9
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_nc_u16 v16, v14, v15
	v_add_co_u32 v10, vcc_lo, s6, v0
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
	v_bfe_i32 v19, v16, 0, 16
	v_add_co_u32 v12, vcc_lo, s4, v2
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v18, v18, v19
	v_add_co_u32 v14, vcc_lo, s6, v2
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v16, vcc_lo, s4, v6
	v_ashrrev_i32_e32 v19, 31, v18
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v20, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v22, vcc_lo, s6, v6
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_ci_u32_e32 v23, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v24, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v25, vcc_lo, s7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v26, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v19, vcc_lo
	v_add_co_u32 v28, vcc_lo, s6, v18
	v_add_co_ci_u32_e32 v29, vcc_lo, s7, v19, vcc_lo
	v_add_co_u32 v18, vcc_lo, s8, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s8, v6
	s_clause 0x3
	global_load_b32 v26, v[26:27], off
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[16:17], off
	global_load_b32 v16, v[20:21], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	s_clause 0x3
	global_load_b32 v17, v[28:29], off
	global_load_b32 v14, v[14:15], off
	global_load_b32 v15, v[22:23], off
	global_load_b32 v20, v[24:25], off
	s_clause 0x3
	global_load_b32 v18, v[18:19], off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[6:7], off
	global_load_b32 v6, v[8:9], off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[10:11], off
	v_div_scale_f32 v7, null, s15, s15, s12
	v_div_scale_f32 v10, s2, s12, s15, s12
	v_add_f32_e64 v19, s14, s14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	v_mul_f32_e64 v21, s13, s13
	v_mul_f32_e64 v22, s14, s14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, v11, v8
	v_add_f32_e64 v11, s13, s13
	v_fma_f32 v7, -v7, v9, v10
	s_waitcnt vmcnt(8)
	v_sub_f32_e32 v24, v17, v14
	v_sub_f32_e32 v23, v13, v16
	s_waitcnt vmcnt(4)
	v_dual_sub_f32 v25, v15, v20 :: v_dual_sub_f32 v2, v18, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v29, null, v11, v11, v24
	v_div_scale_f32 v27, null, v19, v19, v23
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v17, -2.0, v5
	v_div_scale_f32 v33, null, v11, v11, v2
	v_sub_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v13, -2.0, v4 :: v_dual_add_f32 v14, v17, v14
	v_rcp_f32_e32 v17, v27
	v_rcp_f32_e32 v37, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v35, null, v19, v19, v3
	v_fmac_f32_e32 v15, -2.0, v5
	v_div_scale_f32 v28, s0, v23, v19, v23
	v_rcp_f32_e32 v38, v35
	v_div_scale_f32 v31, null, v19, v19, v25
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_fma_f32 v52, -v27, v17, 1.0
	v_sub_f32_e32 v10, v26, v12
	v_fma_f32 v55, -v33, v37, 1.0
	v_fmac_f32_e32 v26, -2.0, v4
	v_div_scale_f32 v43, null, v21, v21, v14
	v_fmac_f32_e32 v17, v52, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v37, v55, v37
	v_div_scale_f32 v6, null, v11, v11, v10
	v_add_f32_e32 v12, v26, v12
	v_add_f32_e32 v15, v15, v20
	v_fma_f32 v56, -v35, v38, 1.0
	v_add_f32_e32 v13, v13, v16
	v_rcp_f32_e32 v16, v6
	v_div_scale_f32 v39, null, v21, v21, v12
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v38, v56, v38
	v_rcp_f32_e32 v20, v29
	v_rcp_f32_e32 v26, v31
	v_div_scale_f32 v41, null, v22, v22, v13
	v_rcp_f32_e32 v47, v39
	v_mul_f32_e32 v56, v28, v17
	v_div_scale_f32 v45, null, v22, v22, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v48, v41
	v_rcp_f32_e32 v49, v43
	v_fma_f32 v51, -v6, v16, 1.0
	v_rcp_f32_e32 v50, v45
	v_div_scale_f32 v18, vcc_lo, v10, v11, v10
	v_div_scale_f32 v34, s4, v2, v11, v2
	v_fma_f32 v53, -v29, v20, 1.0
	v_fma_f32 v54, -v31, v26, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v16, v51, v16 :: v_dual_mul_f32 v59, v34, v37
	v_fma_f32 v51, -v39, v47, 1.0
	v_div_scale_f32 v32, s3, v25, v19, v25
	v_fmac_f32_e32 v26, v54, v26
	v_fma_f32 v52, -v41, v48, 1.0
	v_fma_f32 v54, -v45, v50, 1.0
	v_mul_f32_e32 v55, v18, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v47, v51, v47 :: v_dual_mul_f32 v58, v32, v26
	v_div_scale_f32 v40, s6, v12, v21, v12
	v_fmac_f32_e32 v20, v53, v20
	v_fma_f32 v53, -v43, v49, 1.0
	v_div_scale_f32 v30, s1, v24, v11, v24
	v_mul_f32_e32 v63, v40, v47
	v_div_scale_f32 v44, s8, v14, v21, v14
	v_div_scale_f32 v46, s9, v15, v22, v15
	v_dual_fmac_f32 v48, v52, v48 :: v_dual_fmac_f32 v49, v53, v49
	v_fmac_f32_e32 v50, v54, v50
	v_fma_f32 v51, -v6, v55, v18
	v_div_scale_f32 v36, s5, v3, v19, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v65, v44, v49
	v_mul_f32_e32 v57, v30, v20
	v_fma_f32 v52, -v27, v56, v28
	v_mul_f32_e32 v60, v36, v38
	v_dual_mul_f32 v66, v46, v50 :: v_dual_fmac_f32 v55, v51, v16
	v_div_scale_f32 v42, s7, v13, v22, v13
	v_fma_f32 v53, -v29, v57, v30
	v_fmac_f32_e32 v56, v52, v17
	v_fma_f32 v54, -v31, v58, v32
	v_fma_f32 v6, -v6, v55, v18
	v_fma_f32 v61, -v33, v59, v34
	v_fmac_f32_e32 v57, v53, v20
	v_mul_f32_e32 v64, v42, v48
	v_fma_f32 v18, -v27, v56, v28
	v_fma_f32 v62, -v35, v60, v36
	v_fmac_f32_e32 v59, v61, v37
	v_fma_f32 v51, -v39, v63, v40
	v_fmac_f32_e32 v58, v54, v26
	v_div_fmas_f32 v6, v6, v16, v55
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v52, -v41, v64, v42
	v_fmac_f32_e32 v63, v51, v47
	v_fma_f32 v27, -v29, v57, v30
	v_div_fmas_f32 v17, v18, v17, v56
	v_fma_f32 v53, -v43, v65, v44
	v_fmac_f32_e32 v60, v62, v38
	v_fma_f32 v28, -v31, v58, v32
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v29, -v33, v59, v34
	v_fmac_f32_e32 v65, v53, v49
	v_div_fmas_f32 v18, v27, v20, v57
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v17, v17, v19, v23
	v_fmac_f32_e32 v64, v52, v48
	v_fma_f32 v30, -v35, v60, v36
	v_div_fixup_f32 v6, v6, v11, v10
	v_div_fmas_f32 v10, v28, v26, v58
	v_mul_f32_e32 v17, v5, v17
	s_mov_b32 vcc_lo, s4
	v_fma_f32 v16, -v39, v63, v40
	v_div_fmas_f32 v20, v29, v37, v59
	s_mov_b32 vcc_lo, s5
	v_fma_f32 v31, -v41, v64, v42
	v_div_fmas_f32 v23, v30, v38, v60
	s_mov_b32 vcc_lo, s6
	v_fma_f32 v54, -v45, v66, v46
	v_div_fmas_f32 v16, v16, v47, v63
	s_mov_b32 vcc_lo, s7
	v_div_fixup_f32 v18, v18, v11, v24
	v_div_fmas_f32 v24, v31, v48, v64
	v_fma_f32 v32, -v43, v65, v44
	v_div_fixup_f32 v12, v16, v21, v12
	v_div_fixup_f32 v10, v10, v19, v25
	s_mov_b32 vcc_lo, s8
	v_div_fixup_f32 v13, v24, v22, v13
	v_fmac_f32_e32 v66, v54, v50
	v_div_fmas_f32 v25, v32, v49, v65
	s_mov_b32 vcc_lo, s9
	v_mul_f32_e32 v10, v5, v10
	v_fmac_f32_e32 v17, v4, v6
	v_fma_f32 v33, -v45, v66, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v4, v18
	v_fma_f32 v4, -v17, s12, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v6, v33, v50, v66
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v7, v7, v8, v9
	v_div_fixup_f32 v8, v25, v21, v14
	v_div_fixup_f32 v6, v6, v22, v15
	v_add_f32_e32 v9, v12, v13
	v_fma_f32 v5, -v10, s12, v5
	v_div_fixup_f32 v7, v7, s15, s12
	v_div_fixup_f32 v10, v23, v19, v3
	v_add_f32_e32 v6, v8, v6
	v_div_fixup_f32 v8, v20, v11, v2
	v_add_co_u32 v2, vcc_lo, s10, v0
	v_fmac_f32_e32 v4, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v5, v7, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_fma_f32 v4, -v8, s12, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v5, -v10, s12, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v5, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18navierStokesKernelPfS_S_S_S_S_ffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 67
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18navierStokesKernelPfS_S_S_S_S_ffff, .Lfunc_end0-_Z18navierStokesKernelPfS_S_S_S_S_ffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1768
; NumSgprs: 20
; NumVgprs: 67
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 67
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12updateKernelPfS_S_S_S_S_ ; -- Begin function _Z12updateKernelPfS_S_S_S_S_
	.globl	_Z12updateKernelPfS_S_S_S_S_
	.p2align	8
	.type	_Z12updateKernelPfS_S_S_S_S_,@function
_Z12updateKernelPfS_S_S_S_S_:           ; @_Z12updateKernelPfS_S_S_S_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x4000, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b128 s[0:3], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	global_load_b32 v6, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12updateKernelPfS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12updateKernelPfS_S_S_S_S_, .Lfunc_end1-_Z12updateKernelPfS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18navierStokesKernelPfS_S_S_S_S_ffff
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z18navierStokesKernelPfS_S_S_S_S_ffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     67
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12updateKernelPfS_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12updateKernelPfS_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
