#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>

// Define the number of paths per GPU and the number of GPUs
#define PATHS_PER_GPU 256
#define NUM_GPUS 4
#define TOTAL_PATHS (PATHS_PER_GPU * NUM_GPUS)

// Define the number of time steps
#define TIME_STEPS 1024

// Define the parameters for the Monte Carlo simulation
#define RISK_FREE_RATE 0.05
#define VOLATILITY 0.2
#define INITIAL_PRICE 100.0
#define STRIKE_PRICE 100.0
#define TIME_TO_MATURITY 1.0

// CUDA kernel to perform Monte Carlo simulation
__global__ void monteCarloSimulation(curandState *states, double *prices) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= PATHS_PER_GPU) return;

    double S = INITIAL_PRICE;
    double dt = TIME_TO_MATURITY / TIME_STEPS;
    double sqrt_dt = sqrt(dt);

    for (int t = 0; t < TIME_STEPS; t++) {
        double epsilon = curand_normal_double(&states[idx]);
        S *= exp((RISK_FREE_RATE - 0.5 * VOLATILITY * VOLATILITY) * dt + VOLATILITY * epsilon * sqrt_dt);
    }

    // Calculate the payoff for the European call option
    prices[idx] = fmax(0.0, S - STRIKE_PRICE) * exp(-RISK_FREE_RATE * TIME_TO_MATURITY);
}

// Function to check CUDA errors
void checkCudaError(cudaError_t err, const char *msg) {
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << msg << " (" << cudaGetErrorString(err) << ")" << std::endl;
        exit(EXIT_FAILURE);
    }
}

int main() {
    // Initialize random number generators
    curandState *devStates;
    checkCudaError(cudaMalloc((void **)&devStates, PATHS_PER_GPU * sizeof(curandState)), "Failed to allocate memory for states");

    // Initialize the prices array
    double *devPrices;
    checkCudaError(cudaMalloc((void **)&devPrices, PATHS_PER_GPU * sizeof(double)), "Failed to allocate memory for prices");

    // Initialize the random number generator states
    unsigned int seed = 1234;
    dim3 blockSize(256);
    dim3 gridSize((PATHS_PER_GPU + blockSize.x - 1) / blockSize.x);

    // Launch the kernel on each GPU
    for (int i = 0; i < NUM_GPUS; i++) {
        cudaSetDevice(i);
        monteCarloSimulation<<<gridSize, blockSize>>>(devStates, devPrices);
        checkCudaError(cudaGetLastError(), "Kernel launch failed");
        checkCudaError(cudaDeviceSynchronize(), "Failed to synchronize device");
    }

    // Copy the results back to the host
    double *prices = new double[PATHS_PER_GPU];
    double totalPayoff = 0.0;
    for (int i = 0; i < NUM_GPUS; i++) {
        cudaSetDevice(i);
        checkCudaError(cudaMemcpy(prices, devPrices, PATHS_PER_GPU * sizeof(double), cudaMemcpyDeviceToHost), "Failed to copy memory from device to host");
        for (int j = 0; j < PATHS_PER_GPU; j++) {
            totalPayoff += prices[j];
        }
    }

    // Calculate the average payoff
    double averagePayoff = totalPayoff / TOTAL_PATHS;
    std::cout << "Average payoff: " << averagePayoff << std::endl;

    // Free device memory
    checkCudaError(cudaFree(devStates), "Failed to free memory for states");
    checkCudaError(cudaFree(devPrices), "Failed to free memory for prices");

    // Free host memory
    delete[] prices;

    return 0;
}
	.file	"tmpxft_00146ebe_00000000-6_cuda_code_015612.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3853:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3853:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
.LC1:
	.string	" ("
.LC2:
	.string	")"
	.text
	.globl	_Z14checkCudaError9cudaErrorPKc
	.type	_Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB3849:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsi, %rbp
	leaq	.LC0(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3849:
	.size	_Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
	.globl	_Z60__device_stub__Z20monteCarloSimulationP17curandStateXORWOWPdP17curandStateXORWOWPd
	.type	_Z60__device_stub__Z20monteCarloSimulationP17curandStateXORWOWPdP17curandStateXORWOWPd, @function
_Z60__device_stub__Z20monteCarloSimulationP17curandStateXORWOWPdP17curandStateXORWOWPd:
.LFB3875:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z20monteCarloSimulationP17curandStateXORWOWPd(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3875:
	.size	_Z60__device_stub__Z20monteCarloSimulationP17curandStateXORWOWPdP17curandStateXORWOWPd, .-_Z60__device_stub__Z20monteCarloSimulationP17curandStateXORWOWPdP17curandStateXORWOWPd
	.globl	_Z20monteCarloSimulationP17curandStateXORWOWPd
	.type	_Z20monteCarloSimulationP17curandStateXORWOWPd, @function
_Z20monteCarloSimulationP17curandStateXORWOWPd:
.LFB3876:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z20monteCarloSimulationP17curandStateXORWOWPdP17curandStateXORWOWPd
	.cfi_endproc
.LFE3876:
	.size	_Z20monteCarloSimulationP17curandStateXORWOWPd, .-_Z20monteCarloSimulationP17curandStateXORWOWPd
	.section	.rodata.str1.1
.LC4:
	.string	"Failed to allocate memory for states"
.LC5:
	.string	"Failed to allocate memory for prices"
.LC6:
	.string	"Kernel launch failed"
.LC7:
	.string	"Failed to synchronize device"
.LC8:
	.string	"Failed to copy memory from device to host"
.LC10:
	.string	"Average payoff: "
.LC11:
	.string	"Failed to free memory for states"
.LC12:
	.string	"Failed to free memory for prices"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3850:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$12288, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	leaq	.LC6(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	leaq	24(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movl	$1, 52(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	%rax, 44(%rsp)
.L15:
	movl	%ebx, %edi
	call	cudaSetDevice@PLT
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	movl	$256, 32(%rsp)
	movq	44(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z60__device_stub__Z20monteCarloSimulationP17curandStateXORWOWPdP17curandStateXORWOWPd
.L14:
	call	cudaGetLastError@PLT
	movq	%rbp, %rsi
	incl	%ebx
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	call	cudaDeviceSynchronize@PLT
	leaq	.LC7(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	cmpl	$4, %ebx
	jne	.L15
	movl	$2048, %edi
	xorl	%ebp, %ebp
	leaq	.LC8(%rip), %r12
	call	_Znam@PLT
	xorps	%xmm0, %xmm0
	movq	%rax, %rbx
.L17:
	movl	%ebp, %edi
	movsd	%xmm0, 8(%rsp)
	call	cudaSetDevice@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$2048, %edx
	call	cudaMemcpy@PLT
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movsd	8(%rsp), %xmm0
	xorl	%eax, %eax
.L16:
	addsd	(%rbx,%rax,8), %xmm0
	incq	%rax
	cmpq	$256, %rax
	jne	.L16
	incl	%ebp
	cmpl	$4, %ebp
	jne	.L17
	mulsd	.LC9(%rip), %xmm0
	leaq	.LC10(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movsd	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC11(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC12(%rip), %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKc
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3850:
	.size	main, .-main
	.section	.rodata.str1.1
.LC13:
	.string	"_Z20monteCarloSimulationP17curandStateXORWOWPd"
.LC14:
	.string	"precalc_xorwow_matrix"
.LC15:
	.string	"precalc_xorwow_offset_matrix"
.LC16:
	.string	"mrg32k3aM1"
.LC17:
	.string	"mrg32k3aM2"
.LC18:
	.string	"mrg32k3aM1SubSeq"
.LC19:
	.string	"mrg32k3aM2SubSeq"
.LC20:
	.string	"mrg32k3aM1Seq"
.LC21:
	.string	"mrg32k3aM2Seq"
.LC22:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3878:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20monteCarloSimulationP17curandStateXORWOWPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3878:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC9:
	.long	0
	.long	1062207488
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

// Define the number of paths per GPU and the number of GPUs
#define PATHS_PER_GPU 256
#define NUM_GPUS 4
#define TOTAL_PATHS (PATHS_PER_GPU * NUM_GPUS)

// Define the number of time steps
#define TIME_STEPS 1024

// Define the parameters for the Monte Carlo simulation
#define RISK_FREE_RATE 0.05
#define VOLATILITY 0.2
#define INITIAL_PRICE 100.0
#define STRIKE_PRICE 100.0
#define TIME_TO_MATURITY 1.0

// CUDA kernel to perform Monte Carlo simulation
__global__ void monteCarloSimulation(hiprandState *states, double *prices) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= PATHS_PER_GPU) return;

    double S = INITIAL_PRICE;
    double dt = TIME_TO_MATURITY / TIME_STEPS;
    double sqrt_dt = sqrt(dt);

    for (int t = 0; t < TIME_STEPS; t++) {
        double epsilon = hiprand_normal_double(&states[idx]);
        S *= exp((RISK_FREE_RATE - 0.5 * VOLATILITY * VOLATILITY) * dt + VOLATILITY * epsilon * sqrt_dt);
    }

    // Calculate the payoff for the European call option
    prices[idx] = fmax(0.0, S - STRIKE_PRICE) * exp(-RISK_FREE_RATE * TIME_TO_MATURITY);
}

// Function to check CUDA errors
void checkCudaError(hipError_t err, const char *msg) {
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << msg << " (" << hipGetErrorString(err) << ")" << std::endl;
        exit(EXIT_FAILURE);
    }
}

int main() {
    // Initialize random number generators
    hiprandState *devStates;
    checkCudaError(hipMalloc((void **)&devStates, PATHS_PER_GPU * sizeof(hiprandState)), "Failed to allocate memory for states");

    // Initialize the prices array
    double *devPrices;
    checkCudaError(hipMalloc((void **)&devPrices, PATHS_PER_GPU * sizeof(double)), "Failed to allocate memory for prices");

    // Initialize the random number generator states
    unsigned int seed = 1234;
    dim3 blockSize(256);
    dim3 gridSize((PATHS_PER_GPU + blockSize.x - 1) / blockSize.x);

    // Launch the kernel on each GPU
    for (int i = 0; i < NUM_GPUS; i++) {
        hipSetDevice(i);
        monteCarloSimulation<<<gridSize, blockSize>>>(devStates, devPrices);
        checkCudaError(hipGetLastError(), "Kernel launch failed");
        checkCudaError(hipDeviceSynchronize(), "Failed to synchronize device");
    }

    // Copy the results back to the host
    double *prices = new double[PATHS_PER_GPU];
    double totalPayoff = 0.0;
    for (int i = 0; i < NUM_GPUS; i++) {
        hipSetDevice(i);
        checkCudaError(hipMemcpy(prices, devPrices, PATHS_PER_GPU * sizeof(double), hipMemcpyDeviceToHost), "Failed to copy memory from device to host");
        for (int j = 0; j < PATHS_PER_GPU; j++) {
            totalPayoff += prices[j];
        }
    }

    // Calculate the average payoff
    double averagePayoff = totalPayoff / TOTAL_PATHS;
    std::cout << "Average payoff: " << averagePayoff << std::endl;

    // Free device memory
    checkCudaError(hipFree(devStates), "Failed to free memory for states");
    checkCudaError(hipFree(devPrices), "Failed to free memory for prices");

    // Free host memory
    delete[] prices;

    return 0;
}
	.text
	.file	"cuda_code_015612.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z35__device_stub__monteCarloSimulationP12hiprandStatePd # -- Begin function _Z35__device_stub__monteCarloSimulationP12hiprandStatePd
	.type	_Z35__device_stub__monteCarloSimulationP12hiprandStatePd,@function
_Z35__device_stub__monteCarloSimulationP12hiprandStatePd: # @_Z35__device_stub__monteCarloSimulationP12hiprandStatePd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20monteCarloSimulationP12hiprandStatePd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__monteCarloSimulationP12hiprandStatePd, .Lfunc_end0-_Z35__device_stub__monteCarloSimulationP12hiprandStatePd
	.cfi_endproc
                                        # -- End function
	.globl	_Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
	.type	_Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc:      # @_Z14checkCudaError10hipError_tPKc
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB1_2
# %bb.1:
	retq
.LBB1_2:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r14, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x3f50000000000000              # double 9.765625E-4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	leaq	24(%rsp), %rdi
	movl	$12288, %esi                    # imm = 0x3000
	callq	hipMalloc
	movl	$.L.str.3, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	leaq	16(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	xorl	%r14d, %r14d
	leaq	255(%rbx), %r15
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	%r14d, %edi
	callq	hipSetDevice
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_3
# %bb.2:                                #   in Loop: Header=BB2_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z35__device_stub__monteCarloSimulationP12hiprandStatePd
.LBB2_3:                                #   in Loop: Header=BB2_1 Depth=1
	callq	hipGetLastError
	movl	$.L.str.5, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	callq	hipDeviceSynchronize
	movl	$.L.str.6, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	incl	%r14d
	cmpl	$4, %r14d
	jne	.LBB2_1
# %bb.4:
	movl	$2048, %edi                     # imm = 0x800
	callq	_Znam
	movq	%rax, %rbx
	xorpd	%xmm0, %xmm0
	xorl	%r14d, %r14d
.LBB2_5:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	%r14d, %edi
	callq	hipSetDevice
	movq	16(%rsp), %rsi
	movl	$2048, %edx                     # imm = 0x800
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.7, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	xorl	%eax, %eax
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	addsd	(%rbx,%rax,8), %xmm0
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB2_6
# %bb.7:                                #   in Loop: Header=BB2_5 Depth=1
	incl	%r14d
	cmpl	$4, %r14d
	jne	.LBB2_5
# %bb.8:
	mulsd	.LCPI2_0(%rip), %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.8, %esi
	movl	$16, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	24(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.9, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.10, %esi
	movl	%eax, %edi
	callq	_Z14checkCudaError10hipError_tPKc
	movq	%rbx, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20monteCarloSimulationP12hiprandStatePd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20monteCarloSimulationP12hiprandStatePd,@object # @_Z20monteCarloSimulationP12hiprandStatePd
	.section	.rodata,"a",@progbits
	.globl	_Z20monteCarloSimulationP12hiprandStatePd
	.p2align	3, 0x0
_Z20monteCarloSimulationP12hiprandStatePd:
	.quad	_Z35__device_stub__monteCarloSimulationP12hiprandStatePd
	.size	_Z20monteCarloSimulationP12hiprandStatePd, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" ("
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	")"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate memory for states"
	.size	.L.str.3, 37

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate memory for prices"
	.size	.L.str.4, 37

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Kernel launch failed"
	.size	.L.str.5, 21

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to synchronize device"
	.size	.L.str.6, 29

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to copy memory from device to host"
	.size	.L.str.7, 42

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Average payoff: "
	.size	.L.str.8, 17

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to free memory for states"
	.size	.L.str.9, 33

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Failed to free memory for prices"
	.size	.L.str.10, 33

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z20monteCarloSimulationP12hiprandStatePd"
	.size	.L__unnamed_1, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__monteCarloSimulationP12hiprandStatePd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20monteCarloSimulationP12hiprandStatePd
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20monteCarloSimulationP12hiprandStatePd ; -- Begin function _Z20monteCarloSimulationP12hiprandStatePd
	.globl	_Z20monteCarloSimulationP12hiprandStatePd
	.p2align	8
	.type	_Z20monteCarloSimulationP12hiprandStatePd,@function
_Z20monteCarloSimulationP12hiprandStatePd: ; @_Z20monteCarloSimulationP12hiprandStatePd
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x100, v4
	s_cbranch_execz .LBB0_8
; %bb.1:                                ; %.preheader
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v11, 0
	v_ashrrev_i32_e32 v5, 31, v4
	v_mov_b32_e32 v9, 0x40590000
	s_mov_b32 s4, 0x55555555
	s_mov_b32 s6, 0x6b47b09a
	s_mov_b32 s8, 0xbf559e2b
	s_mov_b32 s10, 0xd7f4df2e
	s_mov_b32 s12, 0x16291751
	s_mov_b32 s14, 0x9b27acf1
	s_mov_b32 s16, 0x998ef7b6
	s_mov_b32 s18, 0xfefa39ef
	s_mov_b32 s20, 0x3b39803f
	s_mov_b32 s22, 0x6fdffd2b
	s_mov_b32 s24, 0xf99eb0bb
	s_mov_b32 s26, 0xd5f14825
	s_mov_b32 s28, 0xcdfe9424
	s_mov_b32 s30, 0x67754fff
	s_mov_b32 s34, 0xe625be09
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[6:7], null, v4, 48, s[0:1]
	s_mov_b32 s36, 0x54442d18
	s_mov_b32 s38, 0xca1d4f33
	s_mov_b32 s40, 0x2e21c33
	s_mov_b32 s42, 0x7294bff9
	s_mov_b32 s44, 0x67b90b37
	s_mov_b32 s46, 0x7e3c325b
	global_load_b32 v10, v[6:7], off offset:8
	s_mov_b32 s48, 0x81b5a67
	s_mov_b32 s50, 0xc9be45de
	s_mov_b32 s52, 0x9999999a
	s_mov_b32 s54, 0xeb851eb8
	s_mov_b32 s56, 0x652b82fe
	s_mov_b32 s58, 0xfca7ab0c
	s_mov_b32 s60, 0x6a5dcb37
	s_mov_b32 s62, 0x623fde64
	s_mov_b32 s64, 0x7c89e6b0
	s_mov_b32 s66, 0x14761f6e
	s_mov_b32 s68, 0x1852b7b0
	s_mov_b32 s70, 0x11122322
	s_mov_b32 s72, 0x555502a1
	s_mov_b32 s74, 0x55555511
	s_mov_b32 s76, 11
	s_movk_i32 s33, 0x400
	s_mov_b32 s5, 0x3fe55555
	s_mov_b32 s7, 0x3fc38538
	s_mov_b32 s9, 0x3fc3ab76
	s_mov_b32 s11, 0x3fc7474d
	s_mov_b32 s13, 0x3fcc71c0
	s_mov_b32 s15, 0x3fd24924
	s_mov_b32 s17, 0x3fd99999
	s_mov_b32 s19, 0xbfe62e42
	s_mov_b32 s21, 0xbc7abc9e
	s_mov_b32 s23, 0xbf7e2fe7
	s_mov_b32 s25, 0x3f3e357e
	s_mov_b32 s27, 0x3fb50782
	s_mov_b32 s29, 0xbfe32d2c
	s_mov_b32 s31, 0x400466bc
	s_mov_b32 s35, 0xc014abbc
	s_mov_b32 s37, 0x400921fb
	s_mov_b32 s39, 0x3f5f9c89
	s_mov_b32 s41, 0xbf1b1673
	s_mov_b32 s43, 0xbf9a6d1e
	s_mov_b32 s45, 0x3fce1f50
	s_mov_b32 s47, 0xbff55d3c
	s_mov_b32 s49, 0x40103c1f
	s_mov_b32 s51, 0xc013bd3c
	s_mov_b32 s53, 0x3fc99999
	s_mov_b32 s55, 0x3efeb851
	s_mov_b32 s57, 0x3ff71547
	s_mov_b32 s59, 0x3e928af3
	s_mov_b32 s61, 0x3e5ade15
	s_mov_b32 s63, 0x3ec71dee
	s_mov_b32 s65, 0x3efa0199
	s_mov_b32 s67, 0x3f2a01a0
	s_mov_b32 s69, 0x3f56c16c
	s_mov_b32 s71, 0x3f811111
	s_mov_b32 s73, 0x3fa55555
	s_mov_b32 s75, 0x3fc55555
	s_mov_b32 s77, 0x3fe00000
	s_mov_b32 s78, 0x55555780
	s_mov_b32 s81, 0x3fe62e42
	s_mov_b32 s83, 0x3c7abc9e
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr0
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v10
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[0:1], v[6:7], off offset:16
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_cvt_f32_f64_e32 v0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[12:13], v0
.LBB0_4:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s84, s1
	v_mov_b32_e32 v10, s0
	s_xor_b32 exec_lo, exec_lo, s84
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b128 v[12:15], v[6:7], off offset:24
	global_load_b32 v0, v[6:7], off offset:40
	global_load_b32 v35, v[6:7], off
	s_mov_b32 s79, s5
	s_mov_b32 s80, s18
	s_mov_b32 s82, s20
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v1, 2, v12
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v2, 4, v0
	v_lshrrev_b32_e32 v10, 2, v13
	v_lshrrev_b32_e32 v32, 2, v15
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v36, 0x161f14, v35
	v_xor_b32_e32 v1, v1, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v32, v32, v15
	v_lshlrev_b32_e32 v3, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v3, v2
	v_xor_b32_e32 v3, v10, v13
	v_xor3_b32 v1, v2, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 1, v3
	v_lshlrev_b32_e32 v10, 4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v10
	v_xor3_b32 v2, v2, v3, v1
	v_add3_u32 v3, v35, v1, 0x587c5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v10, v35, v2, 0xb0f8a
	v_lshlrev_b64 v[12:13], 21, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_u32_e32 v[16:17], v13
	v_xor_b32_e32 v3, v12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_u32_e32 v[12:13], v3
	v_ldexp_f64 v[16:17], v[16:17], 32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[16:17], v[12:13]
	v_fma_f64 v[12:13], 0x3ca00000, v[12:13], 0x3ca00000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f64_e32 v[16:17], v[12:13]
	v_cmp_eq_f64_e64 s0, 0x7ff00000, v[12:13]
	v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[16:17]
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[16:17], v[16:17], v3
	v_frexp_exp_i32_f64_e32 v3, v[12:13]
	v_add_f64 v[18:19], v[16:17], 1.0
	v_add_f64 v[24:25], v[16:17], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_rcp_f64_e32 v[20:21], v[18:19]
	v_add_f64 v[26:27], v[18:19], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[24:25], v[20:21]
	v_mul_f64 v[28:29], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[22:23], v[18:19], -v[28:29]
	v_fma_f64 v[16:17], v[22:23], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[28:29], v[16:17]
	v_add_f64 v[26:27], v[24:25], -v[18:19]
	v_add_f64 v[28:29], v[18:19], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[24:25], -v[26:27]
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[24:25], -v[18:19]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[26:27], v[16:17]
	v_mul_f64 v[16:17], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[22:23], v[16:17]
	v_mul_f64 v[20:21], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[20:21], s[8:9], s[6:7]
	v_mul_f64 v[26:27], v[18:19], v[20:21]
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[12:13]
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[16:17]
	v_fma_f64 v[20:21], v[20:21], v[24:25], s[78:79]
	v_ldexp_f64 v[24:25], v[18:19], 1
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[20:21], v[26:27], v[20:21]
	v_cvt_f64_i32_e32 v[26:27], v3
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_lshrrev_b32_e32 v3, 2, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v14
	v_lshlrev_b32_e32 v14, 4, v2
	v_lshlrev_b32_e32 v10, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v10, v10, v14
	v_xor3_b32 v3, v10, v3, v2
	v_lshlrev_b32_e32 v10, 1, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v33, 4, v3
	v_xor_b32_e32 v10, v10, v33
	v_mov_b32_e32 v33, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_xor3_b32 v37, v10, v32, v3
	v_add_f64 v[22:23], v[24:25], v[20:21]
	v_mul_f64 v[28:29], v[26:27], s[80:81]
	v_ldexp_f64 v[16:17], v[16:17], 1
	v_add3_u32 v10, v35, v3, 0x10974f
	v_add_nc_u32_e32 v32, v37, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[32:33], 21, v[32:33]
	v_cvt_f64_u32_e32 v[33:34], v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, v32, v10
	v_add_f64 v[18:19], v[22:23], -v[24:25]
	v_fma_f64 v[24:25], v[26:27], s[80:81], -v[28:29]
	v_add_f64 v[18:19], v[20:21], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[26:27], s[82:83], v[24:25]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[28:29], v[20:21]
	v_add_f64 v[24:25], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[18:19], -v[28:29]
	v_add_f64 v[26:27], v[18:19], v[24:25]
	v_add_f64 v[22:23], v[24:25], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[20:21], -v[14:15]
	v_add_f64 v[30:31], v[26:27], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_cvt_f64_u32_e32 v[22:23], v10
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	v_add_f64 v[20:21], v[24:25], -v[30:31]
	v_ldexp_f64 v[24:25], v[33:34], 32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[28:29]
	v_add_f64 v[28:29], v[14:15], v[16:17]
	v_add_f64 v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[24:25], v[22:23]
	v_add_f64 v[22:23], v[28:29], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[28:29], v[18:19]
	v_fma_f64 v[20:21], 0x3cb00000, v[20:21], 0x3cb00000
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[28:29], -v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_add_f64 v[28:29], v[26:27], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[30:31], v[20:21], 0.5
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[28:29], -v[26:27]
	v_fract_f64_e32 v[24:25], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[16:17], v[14:15]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[30:31]
	v_add_f64 v[16:17], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[24:25], v[24:25]
	v_add_f64 v[14:15], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, 0, v18, vcc_lo
	v_cndmask_b32_e32 v16, 0, v19, vcc_lo
	v_cmp_lt_f64_e32 vcc_lo, 1.0, v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[28:29], v[14:15]
	v_dual_cndmask_b32 v17, v21, v16 :: v_dual_cndmask_b32 v16, v20, v10
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[16:17], v[16:17]
	v_cndmask_b32_e64 v15, v15, v13, s0
	v_cndmask_b32_e64 v14, v14, v12, s0
	v_cmp_lg_f64_e64 s0, 0x7ff00000, v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[14:15], -2.0
	v_rndne_f64_e32 v[18:19], v[18:19]
	v_cndmask_b32_e32 v10, 0x7ff80000, v15, vcc_lo
	v_cmp_nge_f64_e32 vcc_lo, 0, v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[12:13]
	v_cndmask_b32_e32 v15, 0x7ff00000, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[14:15]
	v_cndmask_b32_e64 v10, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v10, 8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[12:13], v[14:15], v10
	v_fma_f64 v[14:15], v[18:19], -0.5, v[16:17]
	v_cvt_i32_f64_e32 v10, v[18:19]
	v_rsq_f64_e32 v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[22:23], v[14:15], v[14:15]
	v_cmp_class_f64_e64 s1, v[12:13], 0x260
	v_fma_f64 v[24:25], v[22:23], s[24:25], s[22:23]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[28:29], v[12:13], v[16:17]
	v_mul_f64 v[16:17], v[16:17], 0.5
	v_fma_f64 v[26:27], v[22:23], s[40:41], s[38:39]
	v_mul_f64 v[32:33], v[14:15], v[22:23]
	v_fma_f64 v[24:25], v[22:23], v[24:25], s[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[30:31], -v[16:17], v[28:29], 0.5
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[22:23], v[24:25], s[28:29]
	v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[44:45]
	v_fma_f64 v[16:17], v[16:17], v[30:31], v[16:17]
	v_fma_f64 v[24:25], v[22:23], v[24:25], s[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[30:31], -v[28:29], v[28:29], v[12:13]
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[22:23], v[24:25], s[34:35]
	v_fma_f64 v[28:29], v[30:31], v[16:17], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[48:49]
	v_mul_f64 v[24:25], v[32:33], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], -v[28:29], v[28:29], v[12:13]
	v_fma_f64 v[26:27], v[22:23], v[26:27], s[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], s[36:37], v[24:25]
	v_fma_f64 v[16:17], v[30:31], v[16:17], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[22:23], v[26:27], 1.0
	v_cndmask_b32_e64 v23, 0, 0xffffff80, vcc_lo
	v_and_b32_e32 v22, 1, v10
	v_lshlrev_b32_e32 v10, 30, v10
	v_cmp_eq_u32_e32 vcc_lo, 0, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v20, v10, v21
	v_and_b32_e32 v10, 0x80000000, v10
	v_and_b32_e32 v20, 0x80000000, v20
	v_xor_b32_e32 v21, 0x80000000, v15
	v_ldexp_f64 v[16:17], v[16:17], v23
	v_dual_cndmask_b32 v15, v19, v15 :: v_dual_cndmask_b32 v22, v18, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v19, v21, v19 :: v_dual_cndmask_b32 v18, v14, v18
	v_xor_b32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, v22, s0
	v_xor_b32_e32 v10, v19, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, 0, v18, s0
	v_cndmask_b32_e64 v15, 0x7ff80000, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, 0x7ff80000, v10, s0
	v_mov_b32_e32 v10, 1
	v_cndmask_b32_e64 v13, v17, v13, s1
	v_cndmask_b32_e64 v12, v16, v12, s1
	v_mul_f64 v[16:17], v[12:13], v[18:19]
	v_mul_f64 v[12:13], v[12:13], v[14:15]
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off offset:24
	global_store_b32 v[6:7], v37, off offset:40
	global_store_b32 v[6:7], v36, off
	global_store_b64 v[6:7], v[16:17], off offset:16
.LBB0_6:                                ; %_Z21hiprand_normal_doubleI12hiprandStateEdPT_.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s84
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[12:13], s[52:53]
	s_add_i32 s33, s33, -1
	v_fma_f64 v[0:1], 0x3fa00000, v[0:1], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[2:3], v[0:1], s[56:57]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[0:1]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[0:1]
	v_rndne_f64_e32 v[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[2:3], s[18:19], v[0:1]
	v_cvt_i32_f64_e32 v16, v[2:3]
	v_fma_f64 v[12:13], v[2:3], s[20:21], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], s[60:61], s[58:59]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[64:65]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[68:69]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[72:73]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[74:75]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[76:77]
	v_fma_f64 v[14:15], v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[12:13], v[14:15], 1.0
	v_ldexp_f64 v[2:3], v[2:3], v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0x7ff00000, v3, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_cmp_eq_u32 s33, 0
	v_cndmask_b32_e32 v0, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, 0, v3, s0
	v_mul_f64 v[8:9], v[8:9], v[0:1]
	s_cbranch_scc0 .LBB0_2
; %bb.7:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], 0xc0590000, v[8:9]
	s_mov_b32 s0, 0xb0a726a6
	s_mov_b32 s1, 0x3fee7078
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_max_f64 v[0:1], v[0:1], 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[0:1]
	global_store_b32 v[6:7], v10, off offset:8
	global_store_b64 v[2:3], v[0:1], off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20monteCarloSimulationP12hiprandStatePd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 85
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20monteCarloSimulationP12hiprandStatePd, .Lfunc_end0-_Z20monteCarloSimulationP12hiprandStatePd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2864
; NumSgprs: 87
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 87
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20monteCarloSimulationP12hiprandStatePd
    .private_segment_fixed_size: 0
    .sgpr_count:     87
    .sgpr_spill_count: 0
    .symbol:         _Z20monteCarloSimulationP12hiprandStatePd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
