#include <iostream>
#include <cuda_runtime.h>
#include <cufft.h>
#include <cmath>

#define N 32

__global__ void dct_kernel(float *input, float *output) {
    extern __shared__ float shared_data[];

    int tid = threadIdx.x;
    int bid = blockIdx.x;
    int idx = bid * blockDim.x + tid;

    // Load data into shared memory
    shared_data[tid] = input[idx];
    __syncthreads();

    // Perform 32-point DCT using shared memory
    for (int k = 0; k < N; k++) {
        float sum = 0.0f;
        for (int n = 0; n < N; n++) {
            sum += shared_data[n] * cosf(M_PI * k * (2 * n + 1) / (2 * N));
        }
        if (k == 0) sum *= sqrtf(1.0f / N);
        else sum *= sqrtf(2.0f / N);
        if (tid == k) output[idx] = sum;
    }
}

int main() {
    float *h_input, *h_output, *d_input, *d_output;
    h_input = (float *)malloc(N * N * sizeof(float));
    h_output = (float *)malloc(N * N * sizeof(float));

    // Initialize input data
    for (int i = 0; i < N * N; i++) {
        h_input[i] = sinf(i * 0.1f); // Example signal
    }

    // Allocate device memory
    cudaMalloc((void **)&d_input, N * N * sizeof(float));
    cudaMalloc((void **)&d_output, N * N * sizeof(float));

    // Asynchronous memory copy to device
    cudaMemcpyAsync(d_input, h_input, N * N * sizeof(float), cudaMemcpyHostToDevice, 0);

    // Kernel launch configuration
    dim3 threadsPerBlock(N);
    dim3 numBlocks(N);

    // Launch kernel with shared memory
    dct_kernel<<<numBlocks, threadsPerBlock, N * sizeof(float)>>>(d_input, d_output);

    // Asynchronous memory copy from device to host
    cudaMemcpyAsync(h_output, d_output, N * N * sizeof(float), cudaMemcpyDeviceToHost, 0);

    // Synchronize to ensure all operations are complete
    cudaDeviceSynchronize();

    // Check for errors
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_output);

    // Free host memory
    free(h_input);
    free(h_output);

    return 0;
}
	.file	"tmpxft_0014f8bf_00000000-6_cuda_code_067740.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3661:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3661:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z10dct_kernelPfS_PfS_
	.type	_Z32__device_stub__Z10dct_kernelPfS_PfS_, @function
_Z32__device_stub__Z10dct_kernelPfS_PfS_:
.LFB3683:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10dct_kernelPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3683:
	.size	_Z32__device_stub__Z10dct_kernelPfS_PfS_, .-_Z32__device_stub__Z10dct_kernelPfS_PfS_
	.globl	_Z10dct_kernelPfS_
	.type	_Z10dct_kernelPfS_, @function
_Z10dct_kernelPfS_:
.LFB3684:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10dct_kernelPfS_PfS_
	.cfi_endproc
.LFE3684:
	.size	_Z10dct_kernelPfS_, .-_Z10dct_kernelPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3658:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4096, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4096, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rax, %r12
.L9:
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC0(%rip), %xmm0
	call	sinf@PLT
	movss	%xmm0, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	$1024, %rbp
	jne	.L9
	movq	%rsp, %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$4096, %edx
	call	cudaMemcpyAsync@PLT
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	movl	$128, %r8d
	salq	$5, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z32__device_stub__Z10dct_kernelPfS_PfS_
.L10:
	movq	8(%rsp), %rsi
	xorl	%r8d, %r8d
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$4096, %edx
	call	cudaMemcpyAsync@PLT
	call	cudaDeviceSynchronize@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L11
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L11:
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	xorl	%eax, %eax
.L8:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3658:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z10dct_kernelPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3686:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10dct_kernelPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3686:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1036831949
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <cmath>

#define N 32

__global__ void dct_kernel(float *input, float *output) {
    extern __shared__ float shared_data[];

    int tid = threadIdx.x;
    int bid = blockIdx.x;
    int idx = bid * blockDim.x + tid;

    // Load data into shared memory
    shared_data[tid] = input[idx];
    __syncthreads();

    // Perform 32-point DCT using shared memory
    for (int k = 0; k < N; k++) {
        float sum = 0.0f;
        for (int n = 0; n < N; n++) {
            sum += shared_data[n] * cosf(M_PI * k * (2 * n + 1) / (2 * N));
        }
        if (k == 0) sum *= sqrtf(1.0f / N);
        else sum *= sqrtf(2.0f / N);
        if (tid == k) output[idx] = sum;
    }
}

int main() {
    float *h_input, *h_output, *d_input, *d_output;
    h_input = (float *)malloc(N * N * sizeof(float));
    h_output = (float *)malloc(N * N * sizeof(float));

    // Initialize input data
    for (int i = 0; i < N * N; i++) {
        h_input[i] = sinf(i * 0.1f); // Example signal
    }

    // Allocate device memory
    hipMalloc((void **)&d_input, N * N * sizeof(float));
    hipMalloc((void **)&d_output, N * N * sizeof(float));

    // Asynchronous memory copy to device
    hipMemcpyAsync(d_input, h_input, N * N * sizeof(float), hipMemcpyHostToDevice, 0);

    // Kernel launch configuration
    dim3 threadsPerBlock(N);
    dim3 numBlocks(N);

    // Launch kernel with shared memory
    dct_kernel<<<numBlocks, threadsPerBlock, N * sizeof(float)>>>(d_input, d_output);

    // Asynchronous memory copy from device to host
    hipMemcpyAsync(h_output, d_output, N * N * sizeof(float), hipMemcpyDeviceToHost, 0);

    // Synchronize to ensure all operations are complete
    hipDeviceSynchronize();

    // Check for errors
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Free device memory
    hipFree(d_input);
    hipFree(d_output);

    // Free host memory
    free(h_input);
    free(h_output);

    return 0;
}
	.text
	.file	"cuda_code_067740.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__dct_kernelPfS_ # -- Begin function _Z25__device_stub__dct_kernelPfS_
	.type	_Z25__device_stub__dct_kernelPfS_,@function
_Z25__device_stub__dct_kernelPfS_:      # @_Z25__device_stub__dct_kernelPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10dct_kernelPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__dct_kernelPfS_, .Lfunc_end0-_Z25__device_stub__dct_kernelPfS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3dcccccd                      # float 0.100000001
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %rbx
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r14
	xorl	%r15d, %r15d
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15d, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	callq	sinf
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB1_1
# %bb.2:
	leaq	16(%rsp), %r15
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rbx, %rsi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movabsq	$4294967328, %rdi               # imm = 0x100000020
	movl	$128, %r8d
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z25__device_stub__dct_kernelPfS_
.LBB1_4:
	movq	8(%rsp), %rsi
	xorl	%r15d, %r15d
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r14, %rdi
	movl	$2, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	callq	hipDeviceSynchronize
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_9
# %bb.5:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_6
# %bb.7:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_8
.LBB1_9:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	jmp	.LBB1_10
.LBB1_6:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %r15d
.LBB1_10:
	movl	%r15d, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10dct_kernelPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10dct_kernelPfS_,@object      # @_Z10dct_kernelPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z10dct_kernelPfS_
	.p2align	3, 0x0
_Z10dct_kernelPfS_:
	.quad	_Z25__device_stub__dct_kernelPfS_
	.size	_Z10dct_kernelPfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10dct_kernelPfS_"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__dct_kernelPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10dct_kernelPfS_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10dct_kernelPfS_      ; -- Begin function _Z10dct_kernelPfS_
	.globl	_Z10dct_kernelPfS_
	.p2align	8
	.type	_Z10dct_kernelPfS_,@function
_Z10dct_kernelPfS_:                     ; @_Z10dct_kernelPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mov_b32_e32 v6, 0x3e3504f3
	v_lshl_add_u32 v8, v0, 2, 0
	s_mov_b32 s3, 0xb94c1982
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_mov_b32 s2, 0
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_mov_b32 s0, 0x54442d18
	s_mov_b32 s1, 0x400921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s4, 0x37d75334
	global_load_b32 v5, v[1:2], off
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v7, 0x3e800000, v6
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[5:6], v[1:2], s[0:1]
	v_mov_b32_e32 v8, 0
	s_mov_b32 s5, 0
	s_mov_b32 s6, 1
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[9:10], s6
	v_mul_f64 v[9:10], v[5:6], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[9:10], v[9:10], -6
	v_cvt_f32_f64_e32 v10, v[9:10]
	v_mov_b32_e32 v9, s5
	ds_load_b32 v9, v9
	v_cmp_ngt_f32_e64 s8, 0x48000000, |v10|
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_bitset0_b32 s7, 31
	s_and_b32 s8, s7, 0x7fffff
	s_lshr_b32 s7, s7, 23
	s_bitset1_b32 s8, 23
	s_addk_i32 s7, 0xff88
	s_mul_hi_u32 s9, s8, 0xfe5163ab
	s_mul_i32 s10, s8, 0x3c439041
	s_mul_hi_u32 s11, s8, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s8, 0xdb629599
	s_mul_hi_u32 s12, s8, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s8, 0xf534ddc0
	s_mul_hi_u32 s13, s8, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s8, 0xfc2757d1
	s_mul_hi_u32 s14, s8, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s14
	s_mul_i32 s14, s8, 0x4e441529
	s_mul_hi_u32 s15, s8, 0x4e441529
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s15
	s_cmp_gt_u32 s7, 63
	s_mul_i32 s15, s8, 0xfe5163ab
	s_mul_hi_u32 s16, s8, 0xa2f9836e
	s_mul_i32 s8, s8, 0xa2f9836e
	s_cselect_b32 s17, s10, s12
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s15, s10
	s_add_u32 s8, s14, s8
	s_addc_u32 s14, 0, s16
	s_cmp_gt_u32 s7, 63
	s_cselect_b32 s15, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s8, s12, s8
	s_cselect_b32 s12, s13, s14
	s_add_i32 s15, s15, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s15, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s8
	s_cselect_b32 s8, s8, s12
	s_cselect_b32 s11, s17, s11
	s_cselect_b32 s12, s9, s17
	s_cselect_b32 s9, s10, s9
	s_add_i32 s7, s7, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s7, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s8, s13, s8
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s9, s9, s12
	s_add_i32 s10, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s7, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v11, s7
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v12, s8, s13, v11
	v_alignbit_b32 v13, s13, s11, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s7, v12
	v_cndmask_b32_e64 v12, v13, s13, s10
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s7, s8, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v13, s7, v12, 30
	s_bfe_u32 s8, s7, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, 0, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v13, s12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v13
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v16, 23, v14
	v_alignbit_b32 v11, s11, s9, v11
	v_sub_nc_u32_e32 v15, 31, v14
	v_cndmask_b32_e64 v11, v11, s11, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v12, v12, v11, 30
	v_alignbit_b32 v11, v11, s9, 30
	s_lshr_b32 s9, s7, 29
	s_lshr_b32 s7, s7, 30
	s_lshl_b32 s9, s9, 31
	v_xor_b32_e32 v12, s12, v12
	v_xor_b32_e32 v11, s12, v11
	s_or_b32 s10, s9, 0.5
	s_add_i32 s8, s8, s7
	v_sub_nc_u32_e32 v16, s10, v16
	v_alignbit_b32 v13, v13, v12, v15
	v_alignbit_b32 v11, v12, v11, v15
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v13, v11, 9
	v_lshrrev_b32_e32 v13, 9, v13
	v_clz_i32_u32_e32 v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v15, 32, v15
	v_sub_nc_u32_e32 v17, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v12, v11, v17
	v_or_b32_e32 v12, v13, v16
	v_add_nc_u32_e32 v14, v15, v14
	v_lshrrev_b32_e32 v11, 9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, 0x3fc90fda, v12 :: v_dual_lshlrev_b32 v13, 23, v14
	v_sub_nc_u32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0x3fc90fda, v12, -v14
	v_add_nc_u32_e32 v11, 0x33000000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, 0x33a22168, v12
	v_or_b32_e32 v11, s9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, 0x3fc90fda, v11
	v_add_f32_e32 v11, v14, v13
	s_branch .LBB0_5
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=2
	s_mov_b32 s7, -1
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $vgpr11
.LBB0_5:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=2
	v_mov_b32_e32 v12, s8
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=2
	v_mul_f32_e64 v11, 0x3f22f983, |v10|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v12, v11
	v_fma_f32 v11, 0xbfc90fda, v12, |v10|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, 0xb3a22168, v12
	v_fmac_f32_e32 v11, 0xa7c234c4, v12
	v_cvt_i32_f32_e32 v12, v12
.LBB0_7:                                ; %_ZL4cosff.exit
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v13, v11, v11 :: v_dual_and_b32 v16, 1, v12
	s_add_i32 s6, s6, 2
	s_add_i32 s5, s5, 4
	s_cmpk_eq_i32 s6, 0x41
	v_fmaak_f32 v14, s3, v13, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v16
	v_lshlrev_b32_e32 v12, 30, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v14, v13, v14, 0xbe2aaa9d
	v_fmaak_f32 v15, s4, v13, 0xbab64f3b
	v_and_b32_e32 v12, 0x80000000, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v14, v13, v14
	v_fmaak_f32 v15, v13, v15, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v11, v14
	v_fmaak_f32 v15, v13, v15, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, v13, v15, 1.0
	v_cndmask_b32_e64 v11, -v11, v13, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v11, v12, v11
	v_cndmask_b32_e32 v10, 0x7fc00000, v11, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v8, v9, v10
	s_cbranch_scc0 .LBB0_2
; %bb.8:                                ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s5, exec_lo
	v_cmpx_eq_u32_e64 s2, v0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_1 Depth=1
	v_mul_f32_e32 v5, v7, v8
	global_store_b32 v[3:4], v5, off
.LBB0_10:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_add_f64 v[1:2], v[1:2], 1.0
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 32
	s_cbranch_scc0 .LBB0_1
; %bb.11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10dct_kernelPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10dct_kernelPfS_, .Lfunc_end0-_Z10dct_kernelPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1244
; NumSgprs: 20
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10dct_kernelPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z10dct_kernelPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
