#include <iostream>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>

// Define constants for the problem
#define WIDTH 7680
#define HEIGHT 4320
#define CHANNELS 3
#define BLOCK_WIDTH 16
#define BLOCK_HEIGHT 16

// Kernel to process video frames
__global__ void processFrameKernel(unsigned char* d_input, unsigned char* d_output, int width, int height, int channels) {
    // Calculate global thread indices
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;

    // Check if the thread is within the image bounds
    if (x < width && y < height) {
        // Calculate the starting index for this pixel in the image
        int idx = (y * width + x) * channels;

        // Shared memory declaration
        __shared__ unsigned char s_input[BLOCK_HEIGHT + 2][BLOCK_WIDTH + 2][CHANNELS];

        // Load data into shared memory with halo for edge handling
        int s_x = threadIdx.x + 1;
        int s_y = threadIdx.y + 1;

        if (x > 0 && x < width - 1 && y > 0 && y < height - 1) {
            s_input[s_y][s_x][0] = d_input[idx];
            s_input[s_y][s_x][1] = d_input[idx + 1];
            s_input[s_y][s_x][2] = d_input[idx + 2];
        }

        // Load halo data
        if (threadIdx.x == 0 && x > 0) {
            int halo_idx = idx - channels;
            s_input[s_y][0][0] = d_input[halo_idx];
            s_input[s_y][0][1] = d_input[halo_idx + 1];
            s_input[s_y][0][2] = d_input[halo_idx + 2];
        }
        if (threadIdx.x == BLOCK_WIDTH - 1 && x < width - 2) {
            int halo_idx = idx + BLOCK_WIDTH * channels;
            s_input[s_y][BLOCK_WIDTH + 1][0] = d_input[halo_idx];
            s_input[s_y][BLOCK_WIDTH + 1][1] = d_input[halo_idx + 1];
            s_input[s_y][BLOCK_WIDTH + 1][2] = d_input[halo_idx + 2];
        }
        if (threadIdx.y == 0 && y > 0) {
            int halo_idx = idx - width * channels;
            s_input[0][s_x][0] = d_input[halo_idx];
            s_input[0][s_x][1] = d_input[halo_idx + 1];
            s_input[0][s_x][2] = d_input[halo_idx + 2];
        }
        if (threadIdx.y == BLOCK_HEIGHT - 1 && y < height - 2) {
            int halo_idx = idx + BLOCK_HEIGHT * width * channels;
            s_input[BLOCK_HEIGHT + 1][s_x][0] = d_input[halo_idx];
            s_input[BLOCK_HEIGHT + 1][s_x][1] = d_input[halo_idx + 1];
            s_input[BLOCK_HEIGHT + 1][s_x][2] = d_input[halo_idx + 2];
        }

        // Synchronize to ensure all data is loaded into shared memory
        __syncthreads();

        // Simple example processing: grayscale conversion
        if (x > 0 && x < width - 1 && y > 0 && y < height - 1) {
            int gray = 0.299f * s_input[s_y][s_x][0] + 0.587f * s_input[s_y][s_x][1] + 0.114f * s_input[s_y][s_x][2];
            d_output[idx] = gray;
            d_output[idx + 1] = gray;
            d_output[idx + 2] = gray;
        }
    }
}

int main() {
    // Allocate memory for input and output frames
    unsigned char* h_input = new unsigned char[WIDTH * HEIGHT * CHANNELS];
    unsigned char* h_output = new unsigned char[WIDTH * HEIGHT * CHANNELS];

    // Initialize input frame with some data (e.g., random values)
    for (int i = 0; i < WIDTH * HEIGHT * CHANNELS; ++i) {
        h_input[i] = static_cast<unsigned char>(rand() % 256);
    }

    // Allocate device memory
    unsigned char* d_input;
    unsigned char* d_output;
    size_t size = WIDTH * HEIGHT * CHANNELS * sizeof(unsigned char);
    cudaError_t err = cudaMalloc(&d_input, size);
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate device input memory" << std::endl;
        return -1;
    }
    err = cudaMalloc(&d_output, size);
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate device output memory" << std::endl;
        cudaFree(d_input);
        return -1;
    }

    // Copy input data to device
    err = cudaMemcpy(d_input, h_input, size, cudaMemcpyHostToDevice);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy input data to device" << std::endl;
        cudaFree(d_input);
        cudaFree(d_output);
        return -1;
    }

    // Define grid and block dimensions
    dim3 blockSize(BLOCK_WIDTH, BLOCK_HEIGHT);
    dim3 gridSize((WIDTH + blockSize.x - 1) / blockSize.x, (HEIGHT + blockSize.y - 1) / blockSize.y);

    // Launch kernel
    processFrameKernel<<<gridSize, blockSize>>>(d_input, d_output, WIDTH, HEIGHT, CHANNELS);
    err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "Kernel launch failed: " << cudaGetErrorString(err) << std::endl;
        cudaFree(d_input);
        cudaFree(d_output);
        return -1;
    }

    // Copy output data back to host
    err = cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy output data to host" << std::endl;
        cudaFree(d_input);
        cudaFree(d_output);
        return -1;
    }

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_output);

    // Free host memory
    delete[] h_input;
    delete[] h_output;

    std::cout << "Processing complete." << std::endl;
    return 0;
}
	.file	"tmpxft_001b926b_00000000-6_cuda_code_005909.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4293:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4293:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z43__device_stub__Z18processFrameKernelPhS_iiiPhS_iii
	.type	_Z43__device_stub__Z18processFrameKernelPhS_iiiPhS_iii, @function
_Z43__device_stub__Z18processFrameKernelPhS_iiiPhS_iii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18processFrameKernelPhS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L3:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z43__device_stub__Z18processFrameKernelPhS_iiiPhS_iii, .-_Z43__device_stub__Z18processFrameKernelPhS_iiiPhS_iii
	.globl	_Z18processFrameKernelPhS_iii
	.type	_Z18processFrameKernelPhS_iii, @function
_Z18processFrameKernelPhS_iii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z18processFrameKernelPhS_iiiPhS_iii
	.cfi_endproc
.LFE3661:
	.size	_Z18processFrameKernelPhS_iii, .-_Z18processFrameKernelPhS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Failed to allocate device input memory"
.LC1:
	.string	"Failed to allocate device output memory"
.LC2:
	.string	"Failed to copy input data to device"
.LC3:
	.string	"Kernel launch failed: "
.LC4:
	.string	"Failed to copy output data to host"
.LC5:
	.string	"Processing complete."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$99532800, %edi
	movl	$256, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$99532800, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movq	%rax, %rbp
.L10:
	call	rand@PLT
	cltd
	idivl	%r13d
	movb	%dl, (%rbx,%r12)
	incq	%r12
	cmpq	$99532800, %r12
	jne	.L10
	movq	%rsp, %rdi
	movl	$99532800, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L11
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	jmp	.L12
.L11:
	leaq	8(%rsp), %rdi
	movl	$99532800, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L13
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	(%rsp), %rdi
.L22:
	call	cudaFree@PLT
.L12:
	orl	$-1, %eax
	jmp	.L9
.L13:
	movq	(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$99532800, %edx
	call	cudaMemcpy@PLT
	leaq	.LC2(%rip), %rsi
	testl	%eax, %eax
	jne	.L24
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movabsq	$1159641170400, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$3, %r8d
	movl	$4320, %ecx
	movl	$7680, %edx
	call	_Z43__device_stub__Z18processFrameKernelPhS_iiiPhS_iii
.L16:
	call	cudaGetLastError@PLT
	movl	%eax, %r12d
	testl	%eax, %eax
	je	.L17
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	jmp	.L23
.L17:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$99532800, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L18
	leaq	.LC4(%rip), %rsi
.L24:
	leaq	_ZSt4cerr(%rip), %rdi
.L23:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	jmp	.L22
.L18:
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	leaq	.LC5(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	xorl	%eax, %eax
.L9:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z18processFrameKernelPhS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18processFrameKernelPhS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>


// Define constants for the problem
#define WIDTH 7680
#define HEIGHT 4320
#define CHANNELS 3
#define BLOCK_WIDTH 16
#define BLOCK_HEIGHT 16

// Kernel to process video frames
__global__ void processFrameKernel(unsigned char* d_input, unsigned char* d_output, int width, int height, int channels) {
    // Calculate global thread indices
    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;

    // Check if the thread is within the image bounds
    if (x < width && y < height) {
        // Calculate the starting index for this pixel in the image
        int idx = (y * width + x) * channels;

        // Shared memory declaration
        __shared__ unsigned char s_input[BLOCK_HEIGHT + 2][BLOCK_WIDTH + 2][CHANNELS];

        // Load data into shared memory with halo for edge handling
        int s_x = threadIdx.x + 1;
        int s_y = threadIdx.y + 1;

        if (x > 0 && x < width - 1 && y > 0 && y < height - 1) {
            s_input[s_y][s_x][0] = d_input[idx];
            s_input[s_y][s_x][1] = d_input[idx + 1];
            s_input[s_y][s_x][2] = d_input[idx + 2];
        }

        // Load halo data
        if (threadIdx.x == 0 && x > 0) {
            int halo_idx = idx - channels;
            s_input[s_y][0][0] = d_input[halo_idx];
            s_input[s_y][0][1] = d_input[halo_idx + 1];
            s_input[s_y][0][2] = d_input[halo_idx + 2];
        }
        if (threadIdx.x == BLOCK_WIDTH - 1 && x < width - 2) {
            int halo_idx = idx + BLOCK_WIDTH * channels;
            s_input[s_y][BLOCK_WIDTH + 1][0] = d_input[halo_idx];
            s_input[s_y][BLOCK_WIDTH + 1][1] = d_input[halo_idx + 1];
            s_input[s_y][BLOCK_WIDTH + 1][2] = d_input[halo_idx + 2];
        }
        if (threadIdx.y == 0 && y > 0) {
            int halo_idx = idx - width * channels;
            s_input[0][s_x][0] = d_input[halo_idx];
            s_input[0][s_x][1] = d_input[halo_idx + 1];
            s_input[0][s_x][2] = d_input[halo_idx + 2];
        }
        if (threadIdx.y == BLOCK_HEIGHT - 1 && y < height - 2) {
            int halo_idx = idx + BLOCK_HEIGHT * width * channels;
            s_input[BLOCK_HEIGHT + 1][s_x][0] = d_input[halo_idx];
            s_input[BLOCK_HEIGHT + 1][s_x][1] = d_input[halo_idx + 1];
            s_input[BLOCK_HEIGHT + 1][s_x][2] = d_input[halo_idx + 2];
        }

        // Synchronize to ensure all data is loaded into shared memory
        __syncthreads();

        // Simple example processing: grayscale conversion
        if (x > 0 && x < width - 1 && y > 0 && y < height - 1) {
            int gray = 0.299f * s_input[s_y][s_x][0] + 0.587f * s_input[s_y][s_x][1] + 0.114f * s_input[s_y][s_x][2];
            d_output[idx] = gray;
            d_output[idx + 1] = gray;
            d_output[idx + 2] = gray;
        }
    }
}

int main() {
    // Allocate memory for input and output frames
    unsigned char* h_input = new unsigned char[WIDTH * HEIGHT * CHANNELS];
    unsigned char* h_output = new unsigned char[WIDTH * HEIGHT * CHANNELS];

    // Initialize input frame with some data (e.g., random values)
    for (int i = 0; i < WIDTH * HEIGHT * CHANNELS; ++i) {
        h_input[i] = static_cast<unsigned char>(rand() % 256);
    }

    // Allocate device memory
    unsigned char* d_input;
    unsigned char* d_output;
    size_t size = WIDTH * HEIGHT * CHANNELS * sizeof(unsigned char);
    hipError_t err = hipMalloc(&d_input, size);
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate device input memory" << std::endl;
        return -1;
    }
    err = hipMalloc(&d_output, size);
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate device output memory" << std::endl;
        hipFree(d_input);
        return -1;
    }

    // Copy input data to device
    err = hipMemcpy(d_input, h_input, size, hipMemcpyHostToDevice);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy input data to device" << std::endl;
        hipFree(d_input);
        hipFree(d_output);
        return -1;
    }

    // Define grid and block dimensions
    dim3 blockSize(BLOCK_WIDTH, BLOCK_HEIGHT);
    dim3 gridSize((WIDTH + blockSize.x - 1) / blockSize.x, (HEIGHT + blockSize.y - 1) / blockSize.y);

    // Launch kernel
    processFrameKernel<<<gridSize, blockSize>>>(d_input, d_output, WIDTH, HEIGHT, CHANNELS);
    err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "Kernel launch failed: " << hipGetErrorString(err) << std::endl;
        hipFree(d_input);
        hipFree(d_output);
        return -1;
    }

    // Copy output data back to host
    err = hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy output data to host" << std::endl;
        hipFree(d_input);
        hipFree(d_output);
        return -1;
    }

    // Free device memory
    hipFree(d_input);
    hipFree(d_output);

    // Free host memory
    delete[] h_input;
    delete[] h_output;

    std::cout << "Processing complete." << std::endl;
    return 0;
}
	.text
	.file	"cuda_code_005909.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__processFrameKernelPhS_iii # -- Begin function _Z33__device_stub__processFrameKernelPhS_iii
	.type	_Z33__device_stub__processFrameKernelPhS_iii,@function
_Z33__device_stub__processFrameKernelPhS_iii: # @_Z33__device_stub__processFrameKernelPhS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18processFrameKernelPhS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__processFrameKernelPhS_iii, .Lfunc_end0-_Z33__device_stub__processFrameKernelPhS_iii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$99532800, %edi                 # imm = 0x5EEC000
	callq	_Znam
	movq	%rax, %rbx
	movl	$99532800, %edi                 # imm = 0x5EEC000
	callq	_Znam
	movq	%rax, %r14
	xorl	%r15d, %r15d
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	movb	%al, (%rbx,%r15)
	incq	%r15
	cmpq	$99532800, %r15                 # imm = 0x5EEC000
	jne	.LBB1_1
# %bb.2:
	leaq	8(%rsp), %rdi
	movl	$99532800, %esi                 # imm = 0x5EEC000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_4
# %bb.3:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$38, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	jmp	.LBB1_20
.LBB1_4:
	leaq	16(%rsp), %rdi
	movl	$99532800, %esi                 # imm = 0x5EEC000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_6
# %bb.5:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$39, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	jmp	.LBB1_19
.LBB1_6:
	movq	8(%rsp), %rdi
	movl	$99532800, %edx                 # imm = 0x5EEC000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_8
# %bb.7:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.2, %esi
	movl	$35, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	jmp	.LBB1_17
.LBB1_8:
	movabsq	$1159641170400, %rdi            # imm = 0x10E000001E0
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.9:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	$7680, %edx                     # imm = 0x1E00
	movl	$4320, %ecx                     # imm = 0x10E0
	movl	$3, %r8d
	callq	_Z33__device_stub__processFrameKernelPhS_iii
.LBB1_10:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_13
# %bb.11:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_15
# %bb.12:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_16
.LBB1_13:
	movq	16(%rsp), %rsi
	movl	$99532800, %edx                 # imm = 0x5EEC000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_22
# %bb.14:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.4, %esi
	movl	$34, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB1_18
.LBB1_15:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_16:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
.LBB1_17:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_18:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
.LBB1_19:
	callq	hipFree
.LBB1_20:
	movl	$-1, %eax
.LBB1_21:
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_22:
	.cfi_def_cfa_offset 64
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	xorl	%eax, %eax
	jmp	.LBB1_21
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18processFrameKernelPhS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18processFrameKernelPhS_iii,@object # @_Z18processFrameKernelPhS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z18processFrameKernelPhS_iii
	.p2align	3, 0x0
_Z18processFrameKernelPhS_iii:
	.quad	_Z33__device_stub__processFrameKernelPhS_iii
	.size	_Z18processFrameKernelPhS_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Failed to allocate device input memory"
	.size	.L.str, 39

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Failed to allocate device output memory"
	.size	.L.str.1, 40

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to copy input data to device"
	.size	.L.str.2, 36

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Kernel launch failed: "
	.size	.L.str.3, 23

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to copy output data to host"
	.size	.L.str.4, 35

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Processing complete."
	.size	.L.str.5, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18processFrameKernelPhS_iii"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__processFrameKernelPhS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18processFrameKernelPhS_iii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18processFrameKernelPhS_iii ; -- Begin function _Z18processFrameKernelPhS_iii
	.globl	_Z18processFrameKernelPhS_iii
	.p2align	8
	.type	_Z18processFrameKernelPhS_iii,@function
_Z18processFrameKernelPhS_iii:          ; @_Z18processFrameKernelPhS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[8:11], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s9, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_15
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[5:6], null, v2, s8, v[4:5]
	v_cmp_lt_i32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v3, v5, s10
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.2:
	s_add_i32 s0, s8, -1
	s_add_i32 s1, s9, -1
	v_cmp_gt_i32_e64 s0, s0, v4
	v_cmp_gt_i32_e64 s1, s1, v2
	v_cmp_lt_i32_e64 s2, 0, v2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_ashrrev_i32_e32 v7, 31, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s0, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	s_clause 0x1
	global_load_u16 v8, v[6:7], off
	global_load_u8 v6, v[6:7], off offset:2
	v_mul_u32_u24_e32 v7, 3, v1
	v_mad_u32_u24 v7, v0, 54, v7
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v9, 8, v8
	ds_store_b8 v7, v8 offset:57
	ds_store_b8 v7, v9 offset:58
	s_waitcnt vmcnt(0)
	ds_store_b8 v7, v6 offset:59
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_eq_u32_e64 s0, 0, v1
	v_mul_u32_u24_e32 v6, 54, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_subrev_nc_u32_e32 v7, s10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, s0, s4, v7
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	s_clause 0x1
	global_load_u16 v9, v[7:8], off
	global_load_u8 v7, v[7:8], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v8, 8, v9
	v_and_b32_e32 v9, 0xff, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b16 v8, 8, v8
	v_or_b32_e32 v8, v9, v8
	ds_store_b16 v6, v8 offset:54
	s_waitcnt vmcnt(0)
	ds_store_b8 v6, v7 offset:56
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s1, s8, -2
	v_cmp_eq_u32_e64 s0, 15, v1
	v_cmp_gt_i32_e64 s1, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_lshl_add_u32 v7, s10, 4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, s0, s4, v7
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	s_clause 0x1
	global_load_u16 v9, v[7:8], off
	global_load_i8 v7, v[7:8], off offset:2
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v8, 8, v9
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v7, 8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, 0xff, v8
	v_or_b32_e32 v7, v8, v7
	ds_store_b8 v6, v9 offset:105
	ds_store_b16 v6, v7 offset:106
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e64 s1, 0, v0
	v_cmp_lt_i32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_subrev_nc_u32_e32 v6, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s10
	v_ashrrev_i32_e32 v7, 31, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s1, s4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s1, s5, v7, s1
	s_clause 0x1
	global_load_u16 v8, v[6:7], off
	global_load_u8 v6, v[6:7], off offset:2
	v_mul_u32_u24_e32 v7, 3, v1
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v9, 8, v8
	ds_store_b8 v7, v8 offset:3
	ds_store_b8 v7, v9 offset:4
	s_waitcnt vmcnt(0)
	ds_store_b8 v7, v6 offset:5
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s2, s9, -2
	v_cmp_eq_u32_e64 s1, 15, v0
	v_cmp_gt_i32_e64 s2, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_lshl_add_u32 v5, s8, 4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v5, s10
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, s1, s4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s1, s5, v6, s1
	s_clause 0x1
	global_load_u16 v7, v[5:6], off
	global_load_u8 v5, v[5:6], off offset:2
	v_mul_u32_u24_e32 v6, 3, v1
	s_waitcnt vmcnt(1)
	v_lshrrev_b32_e32 v8, 8, v7
	ds_store_b8 v6, v7 offset:921
	ds_store_b8 v6, v8 offset:922
	s_waitcnt vmcnt(0)
	ds_store_b8 v6, v5 offset:923
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.13:
	s_add_i32 s1, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s1, v4
	s_add_i32 s1, s9, -1
	v_cmp_gt_i32_e64 s1, s1, v2
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_mul_u32_u24_e32 v1, 3, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, 54, v1
	ds_load_u8 v1, v0 offset:58
	ds_load_u8 v2, v0 offset:57
	ds_load_u8 v0, v0 offset:59
	s_waitcnt lgkmcnt(2)
	v_cvt_f32_ubyte0_e32 v1, v1
	s_waitcnt lgkmcnt(1)
	v_cvt_f32_ubyte0_e32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_ubyte0_e32 v0, v0
	v_mul_f32_e32 v1, 0x3f1645a2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, v2, 0x3e991687, v1
	v_fmamk_f32 v0, v0, 0x3de978d5, v1
	v_ashrrev_i32_e32 v1, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v2, v0
	v_add_co_u32 v0, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b16 v4, 8, v2
	v_and_b32_e32 v5, 0xff, v2
	v_or_b32_e32 v3, v5, v4
	s_clause 0x1
	global_store_b8 v[0:1], v2, off offset:2
	global_store_b16 v[0:1], v3, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18processFrameKernelPhS_iii
		.amdhsa_group_segment_fixed_size 972
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18processFrameKernelPhS_iii, .Lfunc_end0-_Z18processFrameKernelPhS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1120
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 972 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 972
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18processFrameKernelPhS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18processFrameKernelPhS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
