#include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>

#define N 8192
#define RADIUS 15
#define TILE_WIDTH 16

// Kernel function for stencil computation
__global__ void stencil_2d(const float* __restrict__ input, float* __restrict__ output) {
    __shared__ float tile[TILE_WIDTH + 2 * RADIUS][TILE_WIDTH + 2 * RADIUS];

    int tx = threadIdx.x, ty = threadIdx.y;
    int bx = blockIdx.x, by = blockIdx.y;

    int row = by * TILE_WIDTH + ty - RADIUS;
    int col = bx * TILE_WIDTH + tx - RADIUS;

    // Load data into shared memory
    if ((row >= 0) && (row < N) && (col >= 0) && (col < N)) {
        tile[ty + RADIUS][tx + RADIUS] = input[row * N + col];
    } else {
        tile[ty + RADIUS][tx + RADIUS] = 0.0f;
    }

    // Load halo data into shared memory
    if (ty < RADIUS) {
        if ((row - RADIUS >= 0) && (col >= 0) && (col < N)) {
            tile[ty][tx + RADIUS] = input[(row - RADIUS) * N + col];
        } else {
            tile[ty][tx + RADIUS] = 0.0f;
        }
    }
    if (ty >= TILE_WIDTH - RADIUS) {
        if ((row + TILE_WIDTH < N) && (col >= 0) && (col < N)) {
            tile[ty + 2 * RADIUS][tx + RADIUS] = input[(row + TILE_WIDTH) * N + col];
        } else {
            tile[ty + 2 * RADIUS][tx + RADIUS] = 0.0f;
        }
    }
    if (tx < RADIUS) {
        if ((row >= 0) && (col - RADIUS >= 0) && (row < N)) {
            tile[ty + RADIUS][tx] = input[row * N + col - RADIUS];
        } else {
            tile[ty + RADIUS][tx] = 0.0f;
        }
    }
    if (tx >= TILE_WIDTH - RADIUS) {
        if ((row >= 0) && (col + TILE_WIDTH < N) && (row < N)) {
            tile[ty + RADIUS][tx + 2 * RADIUS] = input[row * N + col + TILE_WIDTH];
        } else {
            tile[ty + RADIUS][tx + 2 * RADIUS] = 0.0f;
        }
    }

    __syncthreads();

    // Compute the stencil result
    float result = 0.0f;
    if ((row >= 0) && (row < N) && (col >= 0) && (col < N)) {
        for (int r = -RADIUS; r <= RADIUS; ++r) {
            for (int c = -RADIUS; c <= RADIUS; ++c) {
                result += tile[ty + RADIUS + r][tx + RADIUS + c];
            }
        }
        output[row * N + col] = result;
    }
}

int main() {
    float* h_input = new float[N * N];
    float* h_output = new float[N * N];

    // Initialize input data
    for (int i = 0; i < N * N; ++i) {
        h_input[i] = 1.0f; // Simple initialization
    }

    float* d_input, *d_output;
    size_t size = N * N * sizeof(float);

    // Allocate device memory
    cudaError_t err = cudaMalloc((void**)&d_input, size);
    if (err != cudaSuccess) {
        std::cerr << "Error allocating d_input: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }
    err = cudaMalloc((void**)&d_output, size);
    if (err != cudaSuccess) {
        std::cerr << "Error allocating d_output: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy input data to device
    err = cudaMemcpy(d_input, h_input, size, cudaMemcpyHostToDevice);
    if (err != cudaSuccess) {
        std::cerr << "Error copying input to device: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Define grid and block dimensions
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 dimGrid((N + TILE_WIDTH - 1) / TILE_WIDTH, (N + TILE_WIDTH - 1) / TILE_WIDTH);

    // Launch kernel
    stencil_2d<<<dimGrid, dimBlock>>>(d_input, d_output);

    // Check for kernel launch errors
    err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "Kernel launch error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy output data back to host
    err = cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost);
    if (err != cudaSuccess) {
        std::cerr << "Error copying output to host: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_output);

    // Clean up host memory
    delete[] h_input;
    delete[] h_output;

    std::cout << "Stencil computation completed successfully." << std::endl;
    return 0;
}
	.file	"tmpxft_0010f0ec_00000000-6_cuda_code_044070.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4292:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4292:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z33__device_stub__Z10stencil_2dPKfPfPKfPf
	.type	_Z33__device_stub__Z10stencil_2dPKfPfPKfPf, @function
_Z33__device_stub__Z10stencil_2dPKfPfPKfPf:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10stencil_2dPKfPf(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z33__device_stub__Z10stencil_2dPKfPfPKfPf, .-_Z33__device_stub__Z10stencil_2dPKfPfPKfPf
	.globl	_Z10stencil_2dPKfPf
	.type	_Z10stencil_2dPKfPf, @function
_Z10stencil_2dPKfPf:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10stencil_2dPKfPfPKfPf
	.cfi_endproc
.LFE3661:
	.size	_Z10stencil_2dPKfPf, .-_Z10stencil_2dPKfPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Error allocating d_input: "
.LC2:
	.string	"Error allocating d_output: "
.LC3:
	.string	"Error copying input to device: "
.LC4:
	.string	"Kernel launch error: "
.LC5:
	.string	"Error copying output to host: "
.LC6:
	.string	"Stencil computation completed successfully."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$268435456, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$268435456, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movss	.LC0(%rip), %xmm0
	movq	%rax, %rbp
	xorl	%eax, %eax
.L10:
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$67108864, %rax
	jne	.L10
	movl	$268435456, %esi
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	leaq	.LC1(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L22
	leaq	8(%rsp), %rdi
	movl	$268435456, %esi
	call	cudaMalloc@PLT
	movl	%eax, %r12d
	testl	%eax, %eax
	je	.L13
	leaq	.LC2(%rip), %rsi
.L22:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	orl	$-1, %eax
	jmp	.L9
.L13:
	movq	(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$268435456, %edx
	call	cudaMemcpy@PLT
	leaq	.LC3(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L22
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movabsq	$2199023256064, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z33__device_stub__Z10stencil_2dPKfPfPKfPf
.L16:
	call	cudaGetLastError@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L22
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$268435456, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L22
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	xorl	%eax, %eax
.L9:
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z10stencil_2dPKfPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10stencil_2dPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>


#define N 8192
#define RADIUS 15
#define TILE_WIDTH 16

// Kernel function for stencil computation
__global__ void stencil_2d(const float* __restrict__ input, float* __restrict__ output) {
    __shared__ float tile[TILE_WIDTH + 2 * RADIUS][TILE_WIDTH + 2 * RADIUS];

    int tx = threadIdx.x, ty = threadIdx.y;
    int bx = blockIdx.x, by = blockIdx.y;

    int row = by * TILE_WIDTH + ty - RADIUS;
    int col = bx * TILE_WIDTH + tx - RADIUS;

    // Load data into shared memory
    if ((row >= 0) && (row < N) && (col >= 0) && (col < N)) {
        tile[ty + RADIUS][tx + RADIUS] = input[row * N + col];
    } else {
        tile[ty + RADIUS][tx + RADIUS] = 0.0f;
    }

    // Load halo data into shared memory
    if (ty < RADIUS) {
        if ((row - RADIUS >= 0) && (col >= 0) && (col < N)) {
            tile[ty][tx + RADIUS] = input[(row - RADIUS) * N + col];
        } else {
            tile[ty][tx + RADIUS] = 0.0f;
        }
    }
    if (ty >= TILE_WIDTH - RADIUS) {
        if ((row + TILE_WIDTH < N) && (col >= 0) && (col < N)) {
            tile[ty + 2 * RADIUS][tx + RADIUS] = input[(row + TILE_WIDTH) * N + col];
        } else {
            tile[ty + 2 * RADIUS][tx + RADIUS] = 0.0f;
        }
    }
    if (tx < RADIUS) {
        if ((row >= 0) && (col - RADIUS >= 0) && (row < N)) {
            tile[ty + RADIUS][tx] = input[row * N + col - RADIUS];
        } else {
            tile[ty + RADIUS][tx] = 0.0f;
        }
    }
    if (tx >= TILE_WIDTH - RADIUS) {
        if ((row >= 0) && (col + TILE_WIDTH < N) && (row < N)) {
            tile[ty + RADIUS][tx + 2 * RADIUS] = input[row * N + col + TILE_WIDTH];
        } else {
            tile[ty + RADIUS][tx + 2 * RADIUS] = 0.0f;
        }
    }

    __syncthreads();

    // Compute the stencil result
    float result = 0.0f;
    if ((row >= 0) && (row < N) && (col >= 0) && (col < N)) {
        for (int r = -RADIUS; r <= RADIUS; ++r) {
            for (int c = -RADIUS; c <= RADIUS; ++c) {
                result += tile[ty + RADIUS + r][tx + RADIUS + c];
            }
        }
        output[row * N + col] = result;
    }
}

int main() {
    float* h_input = new float[N * N];
    float* h_output = new float[N * N];

    // Initialize input data
    for (int i = 0; i < N * N; ++i) {
        h_input[i] = 1.0f; // Simple initialization
    }

    float* d_input, *d_output;
    size_t size = N * N * sizeof(float);

    // Allocate device memory
    hipError_t err = hipMalloc((void**)&d_input, size);
    if (err != hipSuccess) {
        std::cerr << "Error allocating d_input: " << hipGetErrorString(err) << std::endl;
        return -1;
    }
    err = hipMalloc((void**)&d_output, size);
    if (err != hipSuccess) {
        std::cerr << "Error allocating d_output: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy input data to device
    err = hipMemcpy(d_input, h_input, size, hipMemcpyHostToDevice);
    if (err != hipSuccess) {
        std::cerr << "Error copying input to device: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Define grid and block dimensions
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 dimGrid((N + TILE_WIDTH - 1) / TILE_WIDTH, (N + TILE_WIDTH - 1) / TILE_WIDTH);

    // Launch kernel
    stencil_2d<<<dimGrid, dimBlock>>>(d_input, d_output);

    // Check for kernel launch errors
    err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "Kernel launch error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy output data back to host
    err = hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost);
    if (err != hipSuccess) {
        std::cerr << "Error copying output to host: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Free device memory
    hipFree(d_input);
    hipFree(d_output);

    // Clean up host memory
    delete[] h_input;
    delete[] h_output;

    std::cout << "Stencil computation completed successfully." << std::endl;
    return 0;
}
	.text
	.file	"cuda_code_044070.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__stencil_2dPKfPf # -- Begin function _Z25__device_stub__stencil_2dPKfPf
	.type	_Z25__device_stub__stencil_2dPKfPf,@function
_Z25__device_stub__stencil_2dPKfPf:     # @_Z25__device_stub__stencil_2dPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10stencil_2dPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__stencil_2dPKfPf, .Lfunc_end0-_Z25__device_stub__stencil_2dPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	$268435456, %edi                # imm = 0x10000000
	callq	_Znam
	movq	%rax, %rbx
	movl	$268435456, %edi                # imm = 0x10000000
	callq	_Znam
	movq	%rax, %r14
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rbx,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$67108864, %rax                 # imm = 0x4000000
	jne	.LBB1_1
# %bb.2:
	leaq	8(%rsp), %rdi
	movl	$268435456, %esi                # imm = 0x10000000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_4
# %bb.3:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$26, %edx
	jmp	.LBB1_12
.LBB1_4:
	movq	%rsp, %rdi
	movl	$268435456, %esi                # imm = 0x10000000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_6
# %bb.5:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$27, %edx
	jmp	.LBB1_12
.LBB1_6:
	movq	8(%rsp), %rdi
	movl	$268435456, %edx                # imm = 0x10000000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_8
# %bb.7:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.2, %esi
	movl	$31, %edx
	jmp	.LBB1_12
.LBB1_8:
	movabsq	$2199023256064, %rdi            # imm = 0x20000000200
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.9:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z25__device_stub__stencil_2dPKfPf
.LBB1_10:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_18
# %bb.11:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	movl	$21, %edx
.LBB1_12:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_14
# %bb.13:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_15
.LBB1_14:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_15:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_16:
	movl	$-1, %eax
.LBB1_17:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_18:
	.cfi_def_cfa_offset 48
	movq	(%rsp), %rsi
	movl	$268435456, %edx                # imm = 0x10000000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_20
# %bb.19:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.4, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cerr, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB1_16
.LBB1_20:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$43, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	xorl	%eax, %eax
	jmp	.LBB1_17
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10stencil_2dPKfPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10stencil_2dPKfPf,@object     # @_Z10stencil_2dPKfPf
	.section	.rodata,"a",@progbits
	.globl	_Z10stencil_2dPKfPf
	.p2align	3, 0x0
_Z10stencil_2dPKfPf:
	.quad	_Z25__device_stub__stencil_2dPKfPf
	.size	_Z10stencil_2dPKfPf, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error allocating d_input: "
	.size	.L.str, 27

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Error allocating d_output: "
	.size	.L.str.1, 28

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Error copying input to device: "
	.size	.L.str.2, 32

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Kernel launch error: "
	.size	.L.str.3, 22

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Error copying output to host: "
	.size	.L.str.4, 31

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Stencil computation completed successfully."
	.size	.L.str.5, 44

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10stencil_2dPKfPf"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__stencil_2dPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10stencil_2dPKfPf
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10stencil_2dPKfPf     ; -- Begin function _Z10stencil_2dPKfPf
	.globl	_Z10stencil_2dPKfPf
	.p2align	8
	.type	_Z10stencil_2dPKfPf,@function
_Z10stencil_2dPKfPf:                    ; @_Z10stencil_2dPKfPf
; %bb.0:
	v_bfe_u32 v7, v0, 10, 10
	s_load_b64 s[6:7], s[0:1], 0x0
	v_and_b32_e32 v5, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v6, s15, 4, v7
	v_lshl_add_u32 v3, s14, 4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, -15, v6
	v_add_nc_u32_e32 v0, -15, v3
	v_cmp_lt_i32_e32 vcc_lo, 14, v3
	v_cmp_gt_i32_e64 s2, 0x200f, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_u32_e64 s3, 0x2000, v4
	v_lshl_add_u32 v0, v4, 13, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s3, s3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s8, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s8
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, s3, s6, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s3, s7, v2, s3
	global_load_b32 v1, v[1:2], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s4
	s_load_b64 s[4:5], s[0:1], 0x8
	v_lshlrev_b32_e32 v2, 2, v5
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v2, 0xb8, v7, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1 offset:2820
	v_cmpx_gt_u32_e32 15, v7
	s_cbranch_execz .LBB0_6
; %bb.3:
	v_cmp_lt_i32_e64 s0, 29, v6
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_b32 s0, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_lshl_add_u32 v1, v6, 13, 0xfffc4000
	v_ashrrev_i32_e32 v9, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v1
	v_add_co_u32 v8, s0, v1, v3
	v_add_co_ci_u32_e64 v9, s0, v10, v9, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, s0, s6, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, s7, v9, s0
	global_load_b32 v1, v[8:9], off offset:-60
.LBB0_5:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1 offset:60
.LBB0_6:                                ; %Flow149
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u32_e32 0, v7
	s_cbranch_execz .LBB0_10
; %bb.7:
	v_cmp_gt_i32_e64 s0, 0x1fff, v6
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_b32 s2, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_lshl_add_u32 v1, v6, 13, 0x2000
	v_ashrrev_i32_e32 v8, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v1
	v_add_co_u32 v7, vcc_lo, v1, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, v9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v1, v[7:8], off offset:-60
.LBB0_9:                                ; %.sink.split128
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1 offset:5580
.LBB0_10:                               ; %Flow148
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_lt_i32_e32 vcc_lo, 14, v6
	v_cmp_gt_i32_e64 s0, 0x200f, v6
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 15, v5
	s_cbranch_execz .LBB0_14
; %bb.11:
	v_cmp_lt_i32_e64 s1, 29, v3
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s1, s6, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s1, s7, v7, s1
	global_load_b32 v1, v[6:7], off offset:-60
.LBB0_13:                               ; %.sink.split133
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1 offset:2760
.LBB0_14:                               ; %Flow147
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e32 0, v5
	s_cbranch_execz .LBB0_18
; %bb.15:
	v_cmp_gt_i32_e64 s1, 0x1fff, v3
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s1, s0
	s_and_b32 s1, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_lshlrev_b32_e32 v1, 13, v4
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v1
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v1, v[3:4], off offset:4
.LBB0_17:                               ; %.sink.split137
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1 offset:2880
.LBB0_18:                               ; %Flow146
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s8
	s_cbranch_execz .LBB0_24
; %bb.19:                               ; %.preheader116
	v_mov_b32_e32 v3, 0
	s_mov_b32 s0, -15
.LBB0_20:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_21 Depth 2
	s_movk_i32 s1, 0xff84
.LBB0_21:                               ;   Parent Loop BB0_20 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s1, v2
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s1, 0
	ds_load_b32 v1, v1 offset:124
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v1
	s_cbranch_scc0 .LBB0_21
; %bb.22:                               ;   in Loop: Header=BB0_20 Depth=1
	v_add_nc_u32_e32 v2, 0xb8, v2
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 16
	s_cbranch_scc0 .LBB0_20
; %bb.23:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10stencil_2dPKfPf
		.amdhsa_group_segment_fixed_size 8464
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10stencil_2dPKfPf, .Lfunc_end0-_Z10stencil_2dPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 948
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8464 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 8464
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10stencil_2dPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10stencil_2dPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
