#include <iostream>
#include <cuda_runtime.h>

// Define constants for simplicity
#define BATCH_SIZE 32
#define INPUT_CHANNELS 3
#define INPUT_WIDTH 32
#define INPUT_HEIGHT 32
#define FILTER_SIZE 3
#define NUM_FILTERS 64
#define STRIDE 1
#define PADDING 1

// CUDA kernel for backpropagation in a convolutional layer
__global__ void convBackwardKernel(
    float* d_input, float* d_output, float* d_filters, float* d_filters_grad,
    float* d_input_grad, int batch_size, int input_channels, int input_width, int input_height,
    int num_filters, int filter_size, int stride, int padding) {

    int n = blockIdx.x * blockDim.x + threadIdx.x;
    int m = blockIdx.y * blockDim.y + threadIdx.y;
    int c = blockIdx.z * blockDim.z + threadIdx.z;

    if (n >= batch_size || m >= num_filters || c >= input_channels) return;

    int output_width = (input_width - filter_size + 2 * padding) / stride + 1;
    int output_height = (input_height - filter_size + 2 * padding) / stride + 1;

    // Initialize gradient for this filter
    float filter_grad = 0.0f;

    // Loop over output image
    for (int h = 0; h < output_height; ++h) {
        for (int w = 0; w < output_width; ++w) {
            int in_h = h * stride - padding;
            int in_w = w * stride - padding;

            // Loop over filter size
            for (int fh = 0; fh < filter_size; ++fh) {
                for (int fw = 0; fw < filter_size; ++fw) {
                    if (in_h + fh >= 0 && in_h + fh < input_height && in_w + fw >= 0 && in_w + fw < input_width) {
                        // Compute gradient for the filter
                        filter_grad += d_output[n * num_filters * output_height * output_width +
                                               m * output_height * output_width +
                                               h * output_width + w] *
                                       d_input[n * input_channels * input_height * input_width +
                                               c * input_height * input_width +
                                               (in_h + fh) * input_width + (in_w + fw)];

                        // Compute gradient for the input
                        atomicAdd(&d_input_grad[n * input_channels * input_height * input_width +
                                                c * input_height * input_width +
                                                (in_h + fh) * input_width + (in_w + fw)],
                                  d_output[n * num_filters * output_height * output_width +
                                             m * output_height * output_width +
                                             h * output_width + w] *
                                  d_filters[m * input_channels * filter_size * filter_size +
                                            c * filter_size * filter_size +
                                            fh * filter_size + fw]);
                    }
                }
            }
        }
    }

    // Store the computed filter gradient
    d_filters_grad[m * input_channels * filter_size * filter_size +
                   c * filter_size * filter_size +
                   threadIdx.y * filter_size + threadIdx.x] = filter_grad;
}

int main() {
    // Allocate and initialize data on the host
    size_t input_size = BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float);
    size_t output_size = BATCH_SIZE * NUM_FILTERS * ((INPUT_WIDTH - FILTER_SIZE + 2 * PADDING) / STRIDE + 1) *
                         ((INPUT_HEIGHT - FILTER_SIZE + 2 * PADDING) / STRIDE + 1) * sizeof(float);
    size_t filters_size = NUM_FILTERS * INPUT_CHANNELS * FILTER_SIZE * FILTER_SIZE * sizeof(float);
    size_t grad_size = filters_size;

    float *h_input, *h_output, *h_filters, *h_filters_grad, *h_input_grad;

    cudaMallocManaged(&h_input, input_size);
    cudaMallocManaged(&h_output, output_size);
    cudaMallocManaged(&h_filters, filters_size);
    cudaMallocManaged(&h_filters_grad, grad_size);
    cudaMallocManaged(&h_input_grad, input_size);

    // Initialize with some values (e.g., zeros or random values)
    cudaMemset(h_input, 0, input_size);
    cudaMemset(h_output, 0, output_size);
    cudaMemset(h_filters, 0, filters_size);
    cudaMemset(h_filters_grad, 0, grad_size);
    cudaMemset(h_input_grad, 0, input_size);

    // Define grid and block sizes
    dim3 blockSize(4, 4, 4);
    dim3 gridSize((BATCH_SIZE + blockSize.x - 1) / blockSize.x,
                 (NUM_FILTERS + blockSize.y - 1) / blockSize.y,
                 (INPUT_CHANNELS + blockSize.z - 1) / blockSize.z);

    // Launch kernel for each convolutional layer
    for (int layer = 0; layer < 5; ++layer) {
        convBackwardKernel<<<gridSize, blockSize>>>(
            h_input, h_output, h_filters, h_filters_grad, h_input_grad,
            BATCH_SIZE, INPUT_CHANNELS, INPUT_WIDTH, INPUT_HEIGHT,
            NUM_FILTERS, FILTER_SIZE, STRIDE, PADDING);

        // Synchronize to check for errors
        cudaError_t err = cudaGetLastError();
        if (err != cudaSuccess) {
            std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
            return -1;
        }

        // For demonstration, assume h_output and h_input are updated for the next layer
        // In practice, you would load the next layer's input and output here
    }

    // Free allocated memory
    cudaFree(h_input);
    cudaFree(h_output);
    cudaFree(h_filters);
    cudaFree(h_filters_grad);
    cudaFree(h_input_grad);

    std::cout << "Convolutional backpropagation completed successfully." << std::endl;
    return 0;
}
	.file	"tmpxft_001b5b78_00000000-6_cuda_code_012163.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z54__device_stub__Z18convBackwardKernelPfS_S_S_S_iiiiiiiiPfS_S_S_S_iiiiiiii
	.type	_Z54__device_stub__Z18convBackwardKernelPfS_S_S_S_iiiiiiiiPfS_S_S_S_iiiiiiii, @function
_Z54__device_stub__Z18convBackwardKernelPfS_S_S_S_iiiiiiiiPfS_S_S_S_iiiiiiii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 256
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z54__device_stub__Z18convBackwardKernelPfS_S_S_S_iiiiiiiiPfS_S_S_S_iiiiiiii, .-_Z54__device_stub__Z18convBackwardKernelPfS_S_S_S_iiiiiiiiPfS_S_S_S_iiiiiiii
	.globl	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii
	.type	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii, @function
_Z18convBackwardKernelPfS_S_S_S_iiiiiiii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z18convBackwardKernelPfS_S_S_S_iiiiiiiiPfS_S_S_S_iiiiiiii
	.cfi_endproc
.LFE3661:
	.size	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii, .-_Z18convBackwardKernelPfS_S_S_S_iiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error: "
.LC1:
	.string	"Convolutional backpropagation completed successfully."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1, %edx
	movl	$393216, %esi
	movabsq	$17179869188, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	$5, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$8388608, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$6912, %esi
	call	cudaMallocManaged@PLT
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	movl	$6912, %esi
	call	cudaMallocManaged@PLT
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	movl	$393216, %esi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %rdi
	movl	$393216, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	16(%rsp), %rdi
	movl	$8388608, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	24(%rsp), %rdi
	movl	$6912, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	32(%rsp), %rdi
	movl	$6912, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	40(%rsp), %rdi
	movl	$393216, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movl	$1, 68(%rsp)
	movabsq	$68719476744, %rax
	movq	%rax, 60(%rsp)
.L12:
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$4, %ecx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	$32, %r9d
	pushq	$1
	.cfi_def_cfa_offset 128
	pushq	$1
	.cfi_def_cfa_offset 136
	pushq	$3
	.cfi_def_cfa_offset 144
	pushq	$64
	.cfi_def_cfa_offset 152
	pushq	$32
	.cfi_def_cfa_offset 160
	pushq	$32
	.cfi_def_cfa_offset 168
	pushq	$3
	.cfi_def_cfa_offset 176
	movq	104(%rsp), %r8
	movq	96(%rsp), %rcx
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	_Z54__device_stub__Z18convBackwardKernelPfS_S_S_S_iiiiiiiiPfS_S_S_S_iiiiiiii
	addq	$64, %rsp
	.cfi_def_cfa_offset 112
.L9:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L10
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L10:
	decl	%ebp
	jne	.L12
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	xorl	%eax, %eax
.L8:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z18convBackwardKernelPfS_S_S_S_iiiiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

// Define constants for simplicity
#define BATCH_SIZE 32
#define INPUT_CHANNELS 3
#define INPUT_WIDTH 32
#define INPUT_HEIGHT 32
#define FILTER_SIZE 3
#define NUM_FILTERS 64
#define STRIDE 1
#define PADDING 1

// CUDA kernel for backpropagation in a convolutional layer
__global__ void convBackwardKernel(
    float* d_input, float* d_output, float* d_filters, float* d_filters_grad,
    float* d_input_grad, int batch_size, int input_channels, int input_width, int input_height,
    int num_filters, int filter_size, int stride, int padding) {

    int n = blockIdx.x * blockDim.x + threadIdx.x;
    int m = blockIdx.y * blockDim.y + threadIdx.y;
    int c = blockIdx.z * blockDim.z + threadIdx.z;

    if (n >= batch_size || m >= num_filters || c >= input_channels) return;

    int output_width = (input_width - filter_size + 2 * padding) / stride + 1;
    int output_height = (input_height - filter_size + 2 * padding) / stride + 1;

    // Initialize gradient for this filter
    float filter_grad = 0.0f;

    // Loop over output image
    for (int h = 0; h < output_height; ++h) {
        for (int w = 0; w < output_width; ++w) {
            int in_h = h * stride - padding;
            int in_w = w * stride - padding;

            // Loop over filter size
            for (int fh = 0; fh < filter_size; ++fh) {
                for (int fw = 0; fw < filter_size; ++fw) {
                    if (in_h + fh >= 0 && in_h + fh < input_height && in_w + fw >= 0 && in_w + fw < input_width) {
                        // Compute gradient for the filter
                        filter_grad += d_output[n * num_filters * output_height * output_width +
                                               m * output_height * output_width +
                                               h * output_width + w] *
                                       d_input[n * input_channels * input_height * input_width +
                                               c * input_height * input_width +
                                               (in_h + fh) * input_width + (in_w + fw)];

                        // Compute gradient for the input
                        atomicAdd(&d_input_grad[n * input_channels * input_height * input_width +
                                                c * input_height * input_width +
                                                (in_h + fh) * input_width + (in_w + fw)],
                                  d_output[n * num_filters * output_height * output_width +
                                             m * output_height * output_width +
                                             h * output_width + w] *
                                  d_filters[m * input_channels * filter_size * filter_size +
                                            c * filter_size * filter_size +
                                            fh * filter_size + fw]);
                    }
                }
            }
        }
    }

    // Store the computed filter gradient
    d_filters_grad[m * input_channels * filter_size * filter_size +
                   c * filter_size * filter_size +
                   threadIdx.y * filter_size + threadIdx.x] = filter_grad;
}

int main() {
    // Allocate and initialize data on the host
    size_t input_size = BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float);
    size_t output_size = BATCH_SIZE * NUM_FILTERS * ((INPUT_WIDTH - FILTER_SIZE + 2 * PADDING) / STRIDE + 1) *
                         ((INPUT_HEIGHT - FILTER_SIZE + 2 * PADDING) / STRIDE + 1) * sizeof(float);
    size_t filters_size = NUM_FILTERS * INPUT_CHANNELS * FILTER_SIZE * FILTER_SIZE * sizeof(float);
    size_t grad_size = filters_size;

    float *h_input, *h_output, *h_filters, *h_filters_grad, *h_input_grad;

    hipMallocManaged(&h_input, input_size);
    hipMallocManaged(&h_output, output_size);
    hipMallocManaged(&h_filters, filters_size);
    hipMallocManaged(&h_filters_grad, grad_size);
    hipMallocManaged(&h_input_grad, input_size);

    // Initialize with some values (e.g., zeros or random values)
    hipMemset(h_input, 0, input_size);
    hipMemset(h_output, 0, output_size);
    hipMemset(h_filters, 0, filters_size);
    hipMemset(h_filters_grad, 0, grad_size);
    hipMemset(h_input_grad, 0, input_size);

    // Define grid and block sizes
    dim3 blockSize(4, 4, 4);
    dim3 gridSize((BATCH_SIZE + blockSize.x - 1) / blockSize.x,
                 (NUM_FILTERS + blockSize.y - 1) / blockSize.y,
                 (INPUT_CHANNELS + blockSize.z - 1) / blockSize.z);

    // Launch kernel for each convolutional layer
    for (int layer = 0; layer < 5; ++layer) {
        convBackwardKernel<<<gridSize, blockSize>>>(
            h_input, h_output, h_filters, h_filters_grad, h_input_grad,
            BATCH_SIZE, INPUT_CHANNELS, INPUT_WIDTH, INPUT_HEIGHT,
            NUM_FILTERS, FILTER_SIZE, STRIDE, PADDING);

        // Synchronize to check for errors
        hipError_t err = hipGetLastError();
        if (err != hipSuccess) {
            std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
            return -1;
        }

        // For demonstration, assume h_output and h_input are updated for the next layer
        // In practice, you would load the next layer's input and output here
    }

    // Free allocated memory
    hipFree(h_input);
    hipFree(h_output);
    hipFree(h_filters);
    hipFree(h_filters_grad);
    hipFree(h_input_grad);

    std::cout << "Convolutional backpropagation completed successfully." << std::endl;
    return 0;
}
	.text
	.file	"cuda_code_012163.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii # -- Begin function _Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii
	.type	_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii,@function
_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii: # @_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convBackwardKernelPfS_S_S_S_iiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii, .Lfunc_end0-_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	32(%rsp), %r14
	movl	$393216, %esi                   # imm = 0x60000
	movq	%r14, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	24(%rsp), %rbp
	movl	$8388608, %esi                  # imm = 0x800000
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %r12
	movl	$6912, %esi                     # imm = 0x1B00
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %r13
	movl	$6912, %esi                     # imm = 0x1B00
	movq	%r13, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rbx
	movl	$393216, %esi                   # imm = 0x60000
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%r14), %rdi
	movl	$393216, %edx                   # imm = 0x60000
	xorl	%esi, %esi
	callq	hipMemset
	movq	(%rbp), %rdi
	movl	$8388608, %edx                  # imm = 0x800000
	xorl	%esi, %esi
	callq	hipMemset
	movq	(%r12), %rdi
	movl	$6912, %edx                     # imm = 0x1B00
	xorl	%esi, %esi
	callq	hipMemset
	movq	(%r13), %rdi
	movl	$6912, %edx                     # imm = 0x1B00
	xorl	%esi, %esi
	callq	hipMemset
	movq	(%rbx), %rdi
	movl	$393216, %edx                   # imm = 0x60000
	xorl	%esi, %esi
	callq	hipMemset
	movl	$5, %r12d
	movabsq	$68719476744, %rbx              # imm = 0x1000000008
	movabsq	$17179869188, %r14              # imm = 0x400000004
	movl	$3, %r13d
	movl	$32, %r15d
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$4, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$32, %r9d
	movl	$1, %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	$64
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.4:                                #   in Loop: Header=BB1_1 Depth=1
	decl	%r12d
	jne	.LBB1_1
# %bb.5:
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$53, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%ebp, %ebp
	jmp	.LBB1_10
.LBB1_6:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_8
# %bb.7:
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%r14, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_9
.LBB1_8:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_9:
	movl	$-1, %ebp
.LBB1_10:
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	%ebp, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convBackwardKernelPfS_S_S_S_iiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii,@object # @_Z18convBackwardKernelPfS_S_S_S_iiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii
	.p2align	3, 0x0
_Z18convBackwardKernelPfS_S_S_S_iiiiiiii:
	.quad	_Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii
	.size	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Convolutional backpropagation completed successfully."
	.size	.L.str.1, 54

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convBackwardKernelPfS_S_S_S_iiiiiiii"
	.size	.L__unnamed_1, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convBackwardKernelPfS_S_S_S_iiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convBackwardKernelPfS_S_S_S_iiiiiiii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii ; -- Begin function _Z18convBackwardKernelPfS_S_S_S_iiiiiiii
	.globl	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii
	.p2align	8
	.type	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii,@function
_Z18convBackwardKernelPfS_S_S_S_iiiiiiii: ; @_Z18convBackwardKernelPfS_S_S_S_iiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x54
	s_load_b256 s[4:11], s[0:1], 0x28
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[6:7], null, s13, s2, v[1:2]
	v_mad_u64_u32 v[3:4], null, s14, s12, v[2:3]
	v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s4, v6
	v_cmp_gt_i32_e64 s2, s8, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s5, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_24
; %bb.1:
	s_ashr_i32 s20, s10, 31
	s_lshl_b32 s21, s11, 1
	s_add_i32 s2, s10, s20
	s_load_b256 s[12:19], s[0:1], 0x0
	s_xor_b32 s4, s2, s20
	s_sub_i32 s2, s7, s9
	v_cvt_f32_u32_e32 v0, s4
	s_sub_i32 s3, 0, s4
	s_add_i32 s2, s2, s21
	s_load_b64 s[0:1], s[0:1], 0x20
	s_ashr_i32 s23, s2, 31
	v_rcp_iflag_f32_e32 v0, v0
	s_add_i32 s2, s2, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_xor_b32 s2, s2, s23
	s_xor_b32 s23, s23, s20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s22, v0
	s_mul_i32 s3, s3, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s22, s3
	s_add_i32 s22, s22, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s2, s22
	s_mul_i32 s24, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s2, s2, s24
	s_add_i32 s24, s3, 1
	s_sub_i32 s25, s2, s4
	s_cmp_ge_u32 s2, s4
	s_cselect_b32 s3, s24, s3
	s_cselect_b32 s2, s25, s2
	s_add_i32 s24, s3, 1
	s_cmp_ge_u32 s2, s4
	s_cselect_b32 s2, s24, s3
	s_mov_b32 s3, 0
	s_xor_b32 s2, s2, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s2, s2, s23
	s_cmp_gt_i32 s2, -1
	s_cbranch_scc0 .LBB0_19
; %bb.2:                                ; %.preheader141.lr.ph
	s_sub_i32 s23, s6, s9
	v_mad_u64_u32 v[7:8], null, v6, s8, v[3:4]
	s_add_i32 s21, s23, s21
	v_mad_u64_u32 v[8:9], null, v6, s5, v[4:5]
	s_ashr_i32 s23, s21, 31
	v_mad_u64_u32 v[9:10], null, v3, s5, v[4:5]
	s_add_i32 s21, s21, s23
	s_xor_b32 s20, s23, s20
	s_xor_b32 s21, s21, s23
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, v7, s2, v[7:8]
	s_mul_hi_u32 s22, s21, s22
	v_mul_lo_u32 v13, v8, s7
	s_mul_i32 s8, s22, s4
	v_mul_lo_u32 v12, v9, s9
	s_sub_i32 s8, s21, s8
	s_add_i32 s21, s22, 1
	s_sub_i32 s23, s8, s4
	s_cmp_ge_u32 s8, s4
	v_mov_b32_e32 v0, 0
	s_cselect_b32 s21, s21, s22
	s_cselect_b32 s8, s23, s8
	s_add_i32 s22, s21, 1
	s_cmp_ge_u32 s8, s4
	s_cselect_b32 s4, s22, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, s20
	s_sub_i32 s4, s4, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s4, 1
	s_cmp_gt_i32 s4, -1
	s_cselect_b32 s20, -1, 0
	s_cmp_gt_i32 s9, 0
	s_cselect_b32 s21, -1, 0
.LBB0_3:                                ; %.preheader141
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
                                        ;           Child Loop BB0_11 Depth 5
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_17
; %bb.4:                                ; %.lr.ph151
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v6, s3, v5
	s_mul_i32 s22, s3, s10
	s_mov_b32 s23, 0
	s_sub_i32 s22, s22, s11
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v14, v6, s8
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_8 Depth 4
                                        ;           Child Loop BB0_11 Depth 5
	s_and_not1_b32 vcc_lo, exec_lo, s21
	s_cbranch_vccnz .LBB0_15
; %bb.6:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s23, v14
	s_mul_i32 s24, s23, s10
	s_mov_b32 s25, 0
	s_sub_i32 s24, s24, s11
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s14, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
.LBB0_7:                                ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_8 Depth 4
                                        ;           Child Loop BB0_11 Depth 5
	s_add_i32 s26, s25, s22
	v_add_nc_u32_e32 v8, s25, v12
	v_add_nc_u32_e32 v9, s26, v13
	s_cmp_gt_i32 s26, -1
	s_cselect_b32 s27, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v16, v8, s9
	v_mul_lo_u32 v15, v9, s6
	s_cmp_lt_i32 s26, s7
	s_cselect_b32 s26, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s26, s27, s26
	s_mov_b32 s27, 0
.LBB0_8:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_11 Depth 5
	s_and_not1_b32 vcc_lo, exec_lo, s26
	s_cbranch_vccnz .LBB0_13
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=4
	s_add_i32 s28, s27, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s28, 0
	s_cselect_b32 s29, -1, 0
	s_cmp_ge_i32 s28, s6
	s_cselect_b32 s30, -1, 0
	s_or_b32 s29, s29, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccnz .LBB0_13
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=4
	global_load_b32 v19, v[6:7], off
	v_add_nc_u32_e32 v8, s28, v15
	v_add_nc_u32_e32 v10, s27, v16
	s_mov_b32 s28, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v17, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v18, vcc_lo, s13, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s16, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s17, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v17, v[17:18], off
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[8:9], off
	s_waitcnt vmcnt(2)
	v_fmac_f32_e32 v0, v19, v17
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v17, v19, v10
.LBB0_11:                               ; %atomicrmw.start
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ;         Parent Loop BB0_8 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v10, v11, v17
	global_atomic_cmpswap_b32 v10, v[8:9], v[10:11], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v10, v11
	v_mov_b32_e32 v11, v10
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_11
; %bb.12:                               ; %Flow
                                        ;   in Loop: Header=BB0_8 Depth=4
	s_or_b32 exec_lo, exec_lo, s28
.LBB0_13:                               ;   in Loop: Header=BB0_8 Depth=4
	s_add_i32 s27, s27, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s27, s9
	s_cbranch_scc0 .LBB0_8
; %bb.14:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_add_i32 s25, s25, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s25, s9
	s_cbranch_scc0 .LBB0_7
.LBB0_15:                               ; %._crit_edge146
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s24, s23, 1
	s_cmp_eq_u32 s23, s4
	s_cbranch_scc1 .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_5 Depth=2
	s_mov_b32 s23, s24
	s_branch .LBB0_5
.LBB0_17:                               ; %._crit_edge152
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s22, s3, 1
	s_cmp_eq_u32 s3, s2
	s_cbranch_scc1 .LBB0_20
; %bb.18:                               ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s3, s22
	s_branch .LBB0_3
.LBB0_19:
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr12
	s_branch .LBB0_21
.LBB0_20:                               ; %Flow212
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s0, 0
.LBB0_21:                               ; %Flow213
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_23
; %bb.22:                               ; %.._crit_edge157_crit_edge
	v_mad_u64_u32 v[5:6], null, v3, s5, v[4:5]
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v12, v5, s9
.LBB0_23:                               ; %._crit_edge157
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v12, v2
	v_mad_u64_u32 v[2:3], null, v4, s9, v[1:2]
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	v_add_co_u32 v1, vcc_lo, s18, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s19, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convBackwardKernelPfS_S_S_S_iiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convBackwardKernelPfS_S_S_S_iiiiiiii, .Lfunc_end0-_Z18convBackwardKernelPfS_S_S_S_iiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1084
; NumSgprs: 33
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convBackwardKernelPfS_S_S_S_iiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         _Z18convBackwardKernelPfS_S_S_S_iiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
