#include <iostream>
#include <cuda_runtime.h>
#include <cooperative_groups.h>

namespace cg = cooperative_groups;

#define TILE_WIDTH 16

__global__ void sparseConvolutionKernel(const int *inputIndices, const float *inputValues, const float *filter, float *output, int numNonZeroElements, int filterSize) {
    extern __shared__ float sharedMem[];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int row = by * TILE_WIDTH + ty;
    int col = bx * TILE_WIDTH + tx;

    // Initialize the accumulator for the output value
    float acc = 0.0f;

    // Loop over the filter tiles required to compute the output element
    for (int m = 0; m < (filterSize + TILE_WIDTH - 1) / TILE_WIDTH; ++m) {
        // Load filter tiles into shared memory
        if (ty < TILE_WIDTH && m * TILE_WIDTH + tx < filterSize) {
            sharedMem[ty * TILE_WIDTH + tx] = filter[(ty + row % filterSize) * filterSize + m * TILE_WIDTH + tx];
        } else {
            sharedMem[ty * TILE_WIDTH + tx] = 0.0f;
        }

        __syncthreads();

        // Perform the sparse convolution for the current tile
        for (int e = 0; e < numNonZeroElements; ++e) {
            int inputRow = inputIndices[e * 2];
            int inputCol = inputIndices[e * 2 + 1];
            if (inputRow >= row && inputRow < row + TILE_WIDTH && inputCol >= col && inputCol < col + TILE_WIDTH) {
                int localRow = inputRow - row;
                int localCol = inputCol - col;
                acc += inputValues[e] * sharedMem[localRow * TILE_WIDTH + localCol];
            }
        }

        __syncthreads();
    }

    // Write the result to the output matrix
    if (row < 256 && col < 256) {
        output[row * 256 + col] = acc;
    }
}

int main() {
    const int filterSize = 256;
    const int numNonZeroElements = 100; // Example number of non-zero elements

    // Allocate host memory
    int *h_inputIndices = new int[numNonZeroElements * 2];
    float *h_inputValues = new float[numNonZeroElements];
    float *h_filter = new float[filterSize * filterSize];
    float *h_output = new float[256 * 256];

    // Initialize host memory (example data)
    for (int i = 0; i < numNonZeroElements; ++i) {
        h_inputIndices[i * 2] = i % 256; // Example row index
        h_inputIndices[i * 2 + 1] = i % 256; // Example column index
        h_inputValues[i] = static_cast<float>(i) / numNonZeroElements;
    }
    for (int i = 0; i < filterSize * filterSize; ++i) {
        h_filter[i] = static_cast<float>(i) / (filterSize * filterSize);
    }

    // Allocate device memory
    int *d_inputIndices;
    float *d_inputValues;
    float *d_filter;
    float *d_output;
    cudaMalloc((void **)&d_inputIndices, numNonZeroElements * 2 * sizeof(int));
    cudaMalloc((void **)&d_inputValues, numNonZeroElements * sizeof(float));
    cudaMalloc((void **)&d_filter, filterSize * filterSize * sizeof(float));
    cudaMalloc((void **)&d_output, 256 * 256 * sizeof(float));

    // Copy data from host to device
    cudaMemcpy(d_inputIndices, h_inputIndices, numNonZeroElements * 2 * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_inputValues, h_inputValues, numNonZeroElements * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_filter, h_filter, filterSize * filterSize * sizeof(float), cudaMemcpyHostToDevice);

    // Define grid and block dimensions
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 dimGrid((256 + TILE_WIDTH - 1) / TILE_WIDTH, (256 + TILE_WIDTH - 1) / TILE_WIDTH);

    // Launch kernel
    size_t sharedMemSize = TILE_WIDTH * TILE_WIDTH * sizeof(float);
    sparseConvolutionKernel<<<dimGrid, dimBlock, sharedMemSize>>>(d_inputIndices, d_inputValues, d_filter, d_output, numNonZeroElements, filterSize);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result from device to host
    cudaMemcpy(h_output, d_output, 256 * 256 * sizeof(float), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_inputIndices);
    cudaFree(d_inputValues);
    cudaFree(d_filter);
    cudaFree(d_output);

    // Free host memory
    delete[] h_inputIndices;
    delete[] h_inputValues;
    delete[] h_filter;
    delete[] h_output;

    return 0;
}
	.file	"tmpxft_001b7fdb_00000000-6_cuda_code_022416.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6835:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE6835:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z54__device_stub__Z23sparseConvolutionKernelPKiPKfS2_PfiiPKiPKfS2_Pfii
	.type	_Z54__device_stub__Z23sparseConvolutionKernelPKiPKfS2_PfiiPKiPKfS2_Pfii, @function
_Z54__device_stub__Z23sparseConvolutionKernelPKiPKfS2_PfiiPKiPKfS2_Pfii:
.LFB6857:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z23sparseConvolutionKernelPKiPKfS2_Pfii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6857:
	.size	_Z54__device_stub__Z23sparseConvolutionKernelPKiPKfS2_PfiiPKiPKfS2_Pfii, .-_Z54__device_stub__Z23sparseConvolutionKernelPKiPKfS2_PfiiPKiPKfS2_Pfii
	.globl	_Z23sparseConvolutionKernelPKiPKfS2_Pfii
	.type	_Z23sparseConvolutionKernelPKiPKfS2_Pfii, @function
_Z23sparseConvolutionKernelPKiPKfS2_Pfii:
.LFB6858:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z23sparseConvolutionKernelPKiPKfS2_PfiiPKiPKfS2_Pfii
	.cfi_endproc
.LFE6858:
	.size	_Z23sparseConvolutionKernelPKiPKfS2_Pfii, .-_Z23sparseConvolutionKernelPKiPKfS2_Pfii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB6832:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$800, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$400, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movl	$262144, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$262144, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movss	.LC0(%rip), %xmm1
	movq	%rax, %r13
	xorl	%eax, %eax
.L9:
	cvtsi2ssl	%eax, %xmm0
	movl	%eax, (%rbx,%rax,8)
	movl	%eax, 4(%rbx,%rax,8)
	divss	%xmm1, %xmm0
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$100, %rax
	jne	.L9
	movss	.LC1(%rip), %xmm1
	xorl	%eax, %eax
.L10:
	cvtsi2ssl	%eax, %xmm0
	mulss	%xmm1, %xmm0
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$65536, %rax
	jne	.L10
	movq	%rsp, %rdi
	movl	$800, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$400, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$800, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$400, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	movl	$1024, %r8d
	movabsq	$68719476752, %rdi
	movq	%rdi, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$256, %r9d
	movl	$100, %r8d
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z54__device_stub__Z23sparseConvolutionKernelPKiPKfS2_PfiiPKiPKfS2_Pfii
.L11:
	call	cudaGetLastError@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	je	.L12
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L12:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$262144, %edx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L8:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6832:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z23sparseConvolutionKernelPKiPKfS2_Pfii"
.LC4:
	.string	"_ZN50_INTERNAL_0823b161_19_cuda_code_022416_cu_342fdfe54cuda3std3__419piecewise_constructE"
.LC5:
	.string	"_ZN50_INTERNAL_0823b161_19_cuda_code_022416_cu_342fdfe54cuda3std6ranges3__45__cpo4swapE"
.LC6:
	.string	"_ZN50_INTERNAL_0823b161_19_cuda_code_022416_cu_342fdfe54cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6860:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z23sparseConvolutionKernelPKiPKfS2_Pfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE6860:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1120403456
	.align 4
.LC1:
	.long	931135488
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>

namespace cg = cooperative_groups;

#define TILE_WIDTH 16

__global__ void sparseConvolutionKernel(const int *inputIndices, const float *inputValues, const float *filter, float *output, int numNonZeroElements, int filterSize) {
    extern __shared__ float sharedMem[];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int row = by * TILE_WIDTH + ty;
    int col = bx * TILE_WIDTH + tx;

    // Initialize the accumulator for the output value
    float acc = 0.0f;

    // Loop over the filter tiles required to compute the output element
    for (int m = 0; m < (filterSize + TILE_WIDTH - 1) / TILE_WIDTH; ++m) {
        // Load filter tiles into shared memory
        if (ty < TILE_WIDTH && m * TILE_WIDTH + tx < filterSize) {
            sharedMem[ty * TILE_WIDTH + tx] = filter[(ty + row % filterSize) * filterSize + m * TILE_WIDTH + tx];
        } else {
            sharedMem[ty * TILE_WIDTH + tx] = 0.0f;
        }

        __syncthreads();

        // Perform the sparse convolution for the current tile
        for (int e = 0; e < numNonZeroElements; ++e) {
            int inputRow = inputIndices[e * 2];
            int inputCol = inputIndices[e * 2 + 1];
            if (inputRow >= row && inputRow < row + TILE_WIDTH && inputCol >= col && inputCol < col + TILE_WIDTH) {
                int localRow = inputRow - row;
                int localCol = inputCol - col;
                acc += inputValues[e] * sharedMem[localRow * TILE_WIDTH + localCol];
            }
        }

        __syncthreads();
    }

    // Write the result to the output matrix
    if (row < 256 && col < 256) {
        output[row * 256 + col] = acc;
    }
}

int main() {
    const int filterSize = 256;
    const int numNonZeroElements = 100; // Example number of non-zero elements

    // Allocate host memory
    int *h_inputIndices = new int[numNonZeroElements * 2];
    float *h_inputValues = new float[numNonZeroElements];
    float *h_filter = new float[filterSize * filterSize];
    float *h_output = new float[256 * 256];

    // Initialize host memory (example data)
    for (int i = 0; i < numNonZeroElements; ++i) {
        h_inputIndices[i * 2] = i % 256; // Example row index
        h_inputIndices[i * 2 + 1] = i % 256; // Example column index
        h_inputValues[i] = static_cast<float>(i) / numNonZeroElements;
    }
    for (int i = 0; i < filterSize * filterSize; ++i) {
        h_filter[i] = static_cast<float>(i) / (filterSize * filterSize);
    }

    // Allocate device memory
    int *d_inputIndices;
    float *d_inputValues;
    float *d_filter;
    float *d_output;
    hipMalloc((void **)&d_inputIndices, numNonZeroElements * 2 * sizeof(int));
    hipMalloc((void **)&d_inputValues, numNonZeroElements * sizeof(float));
    hipMalloc((void **)&d_filter, filterSize * filterSize * sizeof(float));
    hipMalloc((void **)&d_output, 256 * 256 * sizeof(float));

    // Copy data from host to device
    hipMemcpy(d_inputIndices, h_inputIndices, numNonZeroElements * 2 * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_inputValues, h_inputValues, numNonZeroElements * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_filter, h_filter, filterSize * filterSize * sizeof(float), hipMemcpyHostToDevice);

    // Define grid and block dimensions
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 dimGrid((256 + TILE_WIDTH - 1) / TILE_WIDTH, (256 + TILE_WIDTH - 1) / TILE_WIDTH);

    // Launch kernel
    size_t sharedMemSize = TILE_WIDTH * TILE_WIDTH * sizeof(float);
    sparseConvolutionKernel<<<dimGrid, dimBlock, sharedMemSize>>>(d_inputIndices, d_inputValues, d_filter, d_output, numNonZeroElements, filterSize);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result from device to host
    hipMemcpy(h_output, d_output, 256 * 256 * sizeof(float), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_inputIndices);
    hipFree(d_inputValues);
    hipFree(d_filter);
    hipFree(d_output);

    // Free host memory
    delete[] h_inputIndices;
    delete[] h_inputValues;
    delete[] h_filter;
    delete[] h_output;

    return 0;
}
	.text
	.file	"cuda_code_022416.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii
	.type	_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii,@function
_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii: # @_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23sparseConvolutionKernelPKiPKfS2_Pfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii, .Lfunc_end0-_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x42c80000                      # float 100
.LCPI1_1:
	.long	0x37800000                      # float 1.52587891E-5
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$800, %edi                      # imm = 0x320
	callq	_Znam
	movq	%rax, %rbx
	movl	$400, %edi                      # imm = 0x190
	callq	_Znam
	movq	%rax, %r14
	movl	$262144, %edi                   # imm = 0x40000
	callq	_Znam
	movq	%rax, %r15
	movl	$262144, %edi                   # imm = 0x40000
	callq	_Znam
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rbx,%rax,8)
	movl	%eax, 4(%rbx,%rax,8)
	xorps	%xmm1, %xmm1
	cvtsi2ss	%eax, %xmm1
	divss	%xmm0, %xmm1
	movss	%xmm1, (%r14,%rax,4)
	incq	%rax
	cmpq	$100, %rax
	jne	.LBB1_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
	movss	.LCPI1_1(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
.LBB1_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm1, %xmm1
	cvtsi2ss	%eax, %xmm1
	mulss	%xmm0, %xmm1
	movss	%xmm1, (%r15,%rax,4)
	incq	%rax
	cmpq	$65536, %rax                    # imm = 0x10000
	jne	.LBB1_3
# %bb.4:
	leaq	24(%rsp), %r12
	movl	$800, %esi                      # imm = 0x320
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rbp
	movl	$400, %esi                      # imm = 0x190
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$262144, %esi                   # imm = 0x40000
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$262144, %esi                   # imm = 0x40000
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$800, %edx                      # imm = 0x320
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$68719476752, %rdi              # imm = 0x1000000010
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	$100, %r8d
	movl	$256, %r9d                      # imm = 0x100
	callq	_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii
.LBB1_6:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_11
# %bb.7:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_8
# %bb.9:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_10
.LBB1_11:
	movq	(%rsp), %rsi
	movl	$262144, %edx                   # imm = 0x40000
	movq	32(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_12
.LBB1_8:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_10:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_12:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23sparseConvolutionKernelPKiPKfS2_Pfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23sparseConvolutionKernelPKiPKfS2_Pfii,@object # @_Z23sparseConvolutionKernelPKiPKfS2_Pfii
	.section	.rodata,"a",@progbits
	.globl	_Z23sparseConvolutionKernelPKiPKfS2_Pfii
	.p2align	3, 0x0
_Z23sparseConvolutionKernelPKiPKfS2_Pfii:
	.quad	_Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii
	.size	_Z23sparseConvolutionKernelPKiPKfS2_Pfii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z23sparseConvolutionKernelPKiPKfS2_Pfii"
	.size	.L__unnamed_1, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__sparseConvolutionKernelPKiPKfS2_Pfii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23sparseConvolutionKernelPKiPKfS2_Pfii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23sparseConvolutionKernelPKiPKfS2_Pfii ; -- Begin function _Z23sparseConvolutionKernelPKiPKfS2_Pfii
	.globl	_Z23sparseConvolutionKernelPKiPKfS2_Pfii
	.p2align	8
	.type	_Z23sparseConvolutionKernelPKiPKfS2_Pfii,@function
_Z23sparseConvolutionKernelPKiPKfS2_Pfii: ; @_Z23sparseConvolutionKernelPKiPKfS2_Pfii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[12:13], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s15, 4, v3
	v_lshl_add_u32 v1, s14, 4, v2
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s13, 1
	s_cbranch_scc1 .LBB0_11
; %bb.1:                                ; %.lr.ph81
	s_add_i32 s0, s13, 15
	v_ashrrev_i32_e32 v6, 31, v0
	s_lshr_b32 s20, s0, 4
	s_cmp_gt_i32 s12, 0
	s_mov_b32 s22, 0
	s_cselect_b32 s21, -1, 0
	s_ashr_i32 s0, s13, 31
	v_add_nc_u32_e32 v7, v0, v6
	s_add_i32 s1, s13, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s1, s0
	v_cvt_f32_u32_e32 v4, s0
	s_sub_i32 s1, 0, s0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	v_xor_b32_e32 v7, v7, v6
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v5, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v4, v5
	v_add_nc_u32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v7, v4
	v_mul_lo_u32 v4, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v7, v4
	v_add_nc_u32_e32 v7, 16, v1
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_subrev_nc_u32_e32 v5, s0, v4
	v_cmp_le_u32_e32 vcc_lo, s0, v4
	v_cmp_gt_u32_e64 s0, 16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_lshl_add_u32 v5, v3, 4, v2
	v_xor_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v6
	v_add_nc_u32_e32 v6, v4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v4, v5, 2, 0
	v_add_nc_u32_e32 v5, 16, v0
	v_mov_b32_e32 v3, 0
	v_mul_lo_u32 v6, v6, s13
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	v_mov_b32_e32 v8, 0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshl_add_u32 v9, s22, 4, v2
	v_mov_b32_e32 v8, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s13, v9
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v8, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
.LBB0_5:                                ; %Flow108
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b64 s[14:15], s[6:7]
	s_and_not1_b32 vcc_lo, exec_lo, s21
	s_mov_b64 s[16:17], s[4:5]
	s_mov_b32 s23, s12
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_10
.LBB0_7:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_u32 s2, s16, -4
	s_addc_u32 s3, s17, -1
	s_load_b64 s[18:19], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, s18, v0
	v_cmp_ge_i32_e64 s1, s19, v1
	v_cmp_lt_i32_e64 s2, s18, v5
	v_cmp_lt_i32_e64 s3, s19, v7
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	v_sub_nc_u32_e32 v8, s18, v0
	v_sub_nc_u32_e32 v9, s19, v1
	s_load_b32 s2, s[14:15], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v8, v8, 4, v9
	v_lshl_add_u32 v8, v8, 2, 0
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, s2, v8
.LBB0_9:                                ;   in Loop: Header=BB0_7 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s23, s23, -1
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s14, s14, 4
	s_addc_u32 s15, s15, 0
	s_cmp_eq_u32 s23, 0
	s_cbranch_scc0 .LBB0_7
.LBB0_10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s22, s22, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s22, s20
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_12
.LBB0_11:
	v_mov_b32_e32 v3, 0
.LBB0_12:                               ; %Flow110
	v_max_i32_e32 v2, v0, v1
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x100, v2
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_lshl_add_u32 v0, v0, 8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23sparseConvolutionKernelPKiPKfS2_Pfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23sparseConvolutionKernelPKiPKfS2_Pfii, .Lfunc_end0-_Z23sparseConvolutionKernelPKiPKfS2_Pfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 740
; NumSgprs: 26
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23sparseConvolutionKernelPKiPKfS2_Pfii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z23sparseConvolutionKernelPKiPKfS2_Pfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
