#include <iostream>
#include <cuda_runtime.h>

// Constants
#define NUM_PARTICLES 32
#define DIM 3
#define DT 0.001f
#define CUTOFF 1.0f
#define EPSILON 1.0f
#define SIGMA 1.0f

// Kernel to update positions using velocity Verlet
__global__ void update_positions(float* pos, float* vel, float* acc, int num_particles, float dt) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < num_particles) {
        for (int d = 0; d < DIM; ++d) {
            pos[idx * DIM + d] += vel[idx * DIM + d] * dt + 0.5f * acc[idx * DIM + d] * dt * dt;
        }
    }
}

// Kernel to calculate forces and update velocities using velocity Verlet
__global__ void calculate_forces(float* pos, float* vel, float* acc, int num_particles, float dt) {
    extern __shared__ float shared_pos[];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < num_particles) {
        // Load positions into shared memory
        for (int d = 0; d < DIM; ++d) {
            shared_pos[threadIdx.x * DIM + d] = pos[idx * DIM + d];
        }
        __syncthreads();

        float new_acc[DIM] = {0.0f, 0.0f, 0.0f};
        for (int j = 0; j < num_particles; ++j) {
            if (j != idx) {
                float r[DIM];
                float r2 = 0.0f;
                for (int d = 0; d < DIM; ++d) {
                    r[d] = shared_pos[j * DIM + d] - pos[idx * DIM + d];
                    r2 += r[d] * r[d];
                }
                if (r2 < CUTOFF * CUTOFF) {
                    float r6 = r2 * r2 * r2;
                    float force = 24.0f * EPSILON * (2.0f * SIGMA * SIGMA * SIGMA * SIGMA * SIGMA * SIGMA / r6 / r6 / r6 - SIGMA * SIGMA * SIGMA * SIGMA * SIGMA / r6) / r2;
                    for (int d = 0; d < DIM; ++d) {
                        new_acc[d] += force * r[d];
                    }
                }
            }
        }
        __syncthreads();

        // Update velocities
        for (int d = 0; d < DIM; ++d) {
            vel[idx * DIM + d] += 0.5f * (acc[idx * DIM + d] + new_acc[d]) * dt;
            acc[idx * DIM + d] = new_acc[d];
        }
    }
}

int main() {
    // Allocate host memory
    float* h_pos = new float[NUM_PARTICLES * DIM];
    float* h_vel = new float[NUM_PARTICLES * DIM];
    float* h_acc = new float[NUM_PARTICLES * DIM];

    // Initialize positions, velocities, and accelerations
    for (int i = 0; i < NUM_PARTICLES * DIM; ++i) {
        h_pos[i] = static_cast<float>(rand()) / RAND_MAX * 10.0f;
        h_vel[i] = 0.0f;
        h_acc[i] = 0.0f;
    }

    // Allocate device memory
    float* d_pos, *d_vel, *d_acc;
    cudaMalloc(&d_pos, NUM_PARTICLES * DIM * sizeof(float));
    cudaMalloc(&d_vel, NUM_PARTICLES * DIM * sizeof(float));
    cudaMalloc(&d_acc, NUM_PARTICLES * DIM * sizeof(float));

    // Copy data from host to device
    cudaMemcpy(d_pos, h_pos, NUM_PARTICLES * DIM * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_vel, h_vel, NUM_PARTICLES * DIM * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_acc, h_acc, NUM_PARTICLES * DIM * sizeof(float), cudaMemcpyHostToDevice);

    // Define block and grid sizes
    int blockSize = 32;
    int gridSize = (NUM_PARTICLES + blockSize - 1) / blockSize;

    // Kernel launch
    update_positions<<<gridSize, blockSize>>>(d_pos, d_vel, d_acc, NUM_PARTICLES, DT);
    cudaDeviceSynchronize();
    calculate_forces<<<gridSize, blockSize, blockSize * DIM * sizeof(float)>>>(d_pos, d_vel, d_acc, NUM_PARTICLES, DT);
    cudaDeviceSynchronize();

    // Copy results back to host
    cudaMemcpy(h_pos, d_pos, NUM_PARTICLES * DIM * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_vel, d_vel, NUM_PARTICLES * DIM * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_acc, d_acc, NUM_PARTICLES * DIM * sizeof(float), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_pos);
    cudaFree(d_vel);
    cudaFree(d_acc);

    // Free host memory
    delete[] h_pos;
    delete[] h_vel;
    delete[] h_acc;

    // Check for any errors launching the kernel
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    return 0;
}
	.file	"tmpxft_00107b5b_00000000-6_cuda_code_045833.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z16update_positionsPfS_S_ifPfS_S_if
	.type	_Z42__device_stub__Z16update_positionsPfS_S_ifPfS_S_if, @function
_Z42__device_stub__Z16update_positionsPfS_S_ifPfS_S_if:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16update_positionsPfS_S_if(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z42__device_stub__Z16update_positionsPfS_S_ifPfS_S_if, .-_Z42__device_stub__Z16update_positionsPfS_S_ifPfS_S_if
	.globl	_Z16update_positionsPfS_S_if
	.type	_Z16update_positionsPfS_S_if, @function
_Z16update_positionsPfS_S_if:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z16update_positionsPfS_S_ifPfS_S_if
	.cfi_endproc
.LFE3661:
	.size	_Z16update_positionsPfS_S_if, .-_Z16update_positionsPfS_S_if
	.globl	_Z42__device_stub__Z16calculate_forcesPfS_S_ifPfS_S_if
	.type	_Z42__device_stub__Z16calculate_forcesPfS_S_ifPfS_S_if, @function
_Z42__device_stub__Z16calculate_forcesPfS_S_ifPfS_S_if:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16calculate_forcesPfS_S_if(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z42__device_stub__Z16calculate_forcesPfS_S_ifPfS_S_if, .-_Z42__device_stub__Z16calculate_forcesPfS_S_ifPfS_S_if
	.globl	_Z16calculate_forcesPfS_S_if
	.type	_Z16calculate_forcesPfS_S_if, @function
_Z16calculate_forcesPfS_S_if:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z16calculate_forcesPfS_S_ifPfS_S_if
	.cfi_endproc
.LFE3663:
	.size	_Z16calculate_forcesPfS_S_if, .-_Z16calculate_forcesPfS_S_if
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$384, %edi
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$384, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$384, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movq	%rax, %rbx
.L14:
	call	rand@PLT
	movl	$0x00000000, (%rbx,%r13)
	movl	$0x00000000, 0(%rbp,%r13)
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	mulss	.LC1(%rip), %xmm0
	movss	%xmm0, (%r12,%r13)
	addq	$4, %r13
	cmpq	$384, %r13
	jne	.L14
	leaq	8(%rsp), %rdi
	movl	$384, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$384, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$384, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$32, %ecx
	movss	.LC3(%rip), %xmm0
	movq	8(%rsp), %rdi
	call	_Z42__device_stub__Z16update_positionsPfS_S_ifPfS_S_if
.L15:
	call	cudaDeviceSynchronize@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rdi
	salq	$5, %rdx
	movl	$384, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$32, %ecx
	movss	.LC3(%rip), %xmm0
	movq	8(%rsp), %rdi
	call	_Z42__device_stub__Z16calculate_forcesPfS_S_ifPfS_S_if
.L16:
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$384, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	xorl	%eax, %eax
	testl	%ebx, %ebx
	je	.L13
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
.L13:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z16calculate_forcesPfS_S_if"
.LC6:
	.string	"_Z16update_positionsPfS_S_if"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16calculate_forcesPfS_S_if(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16update_positionsPfS_S_if(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.align 4
.LC1:
	.long	1092616192
	.align 4
.LC3:
	.long	981668463
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

// Constants
#define NUM_PARTICLES 32
#define DIM 3
#define DT 0.001f
#define CUTOFF 1.0f
#define EPSILON 1.0f
#define SIGMA 1.0f

// Kernel to update positions using velocity Verlet
__global__ void update_positions(float* pos, float* vel, float* acc, int num_particles, float dt) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < num_particles) {
        for (int d = 0; d < DIM; ++d) {
            pos[idx * DIM + d] += vel[idx * DIM + d] * dt + 0.5f * acc[idx * DIM + d] * dt * dt;
        }
    }
}

// Kernel to calculate forces and update velocities using velocity Verlet
__global__ void calculate_forces(float* pos, float* vel, float* acc, int num_particles, float dt) {
    extern __shared__ float shared_pos[];

    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < num_particles) {
        // Load positions into shared memory
        for (int d = 0; d < DIM; ++d) {
            shared_pos[threadIdx.x * DIM + d] = pos[idx * DIM + d];
        }
        __syncthreads();

        float new_acc[DIM] = {0.0f, 0.0f, 0.0f};
        for (int j = 0; j < num_particles; ++j) {
            if (j != idx) {
                float r[DIM];
                float r2 = 0.0f;
                for (int d = 0; d < DIM; ++d) {
                    r[d] = shared_pos[j * DIM + d] - pos[idx * DIM + d];
                    r2 += r[d] * r[d];
                }
                if (r2 < CUTOFF * CUTOFF) {
                    float r6 = r2 * r2 * r2;
                    float force = 24.0f * EPSILON * (2.0f * SIGMA * SIGMA * SIGMA * SIGMA * SIGMA * SIGMA / r6 / r6 / r6 - SIGMA * SIGMA * SIGMA * SIGMA * SIGMA / r6) / r2;
                    for (int d = 0; d < DIM; ++d) {
                        new_acc[d] += force * r[d];
                    }
                }
            }
        }
        __syncthreads();

        // Update velocities
        for (int d = 0; d < DIM; ++d) {
            vel[idx * DIM + d] += 0.5f * (acc[idx * DIM + d] + new_acc[d]) * dt;
            acc[idx * DIM + d] = new_acc[d];
        }
    }
}

int main() {
    // Allocate host memory
    float* h_pos = new float[NUM_PARTICLES * DIM];
    float* h_vel = new float[NUM_PARTICLES * DIM];
    float* h_acc = new float[NUM_PARTICLES * DIM];

    // Initialize positions, velocities, and accelerations
    for (int i = 0; i < NUM_PARTICLES * DIM; ++i) {
        h_pos[i] = static_cast<float>(rand()) / RAND_MAX * 10.0f;
        h_vel[i] = 0.0f;
        h_acc[i] = 0.0f;
    }

    // Allocate device memory
    float* d_pos, *d_vel, *d_acc;
    hipMalloc(&d_pos, NUM_PARTICLES * DIM * sizeof(float));
    hipMalloc(&d_vel, NUM_PARTICLES * DIM * sizeof(float));
    hipMalloc(&d_acc, NUM_PARTICLES * DIM * sizeof(float));

    // Copy data from host to device
    hipMemcpy(d_pos, h_pos, NUM_PARTICLES * DIM * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_vel, h_vel, NUM_PARTICLES * DIM * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_acc, h_acc, NUM_PARTICLES * DIM * sizeof(float), hipMemcpyHostToDevice);

    // Define block and grid sizes
    int blockSize = 32;
    int gridSize = (NUM_PARTICLES + blockSize - 1) / blockSize;

    // Kernel launch
    update_positions<<<gridSize, blockSize>>>(d_pos, d_vel, d_acc, NUM_PARTICLES, DT);
    hipDeviceSynchronize();
    calculate_forces<<<gridSize, blockSize, blockSize * DIM * sizeof(float)>>>(d_pos, d_vel, d_acc, NUM_PARTICLES, DT);
    hipDeviceSynchronize();

    // Copy results back to host
    hipMemcpy(h_pos, d_pos, NUM_PARTICLES * DIM * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_vel, d_vel, NUM_PARTICLES * DIM * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_acc, d_acc, NUM_PARTICLES * DIM * sizeof(float), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_pos);
    hipFree(d_vel);
    hipFree(d_acc);

    // Free host memory
    delete[] h_pos;
    delete[] h_vel;
    delete[] h_acc;

    // Check for any errors launching the kernel
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    return 0;
}
	.text
	.file	"cuda_code_045833.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z31__device_stub__update_positionsPfS_S_if # -- Begin function _Z31__device_stub__update_positionsPfS_S_if
	.type	_Z31__device_stub__update_positionsPfS_S_if,@function
_Z31__device_stub__update_positionsPfS_S_if: # @_Z31__device_stub__update_positionsPfS_S_if
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movss	%xmm0, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16update_positionsPfS_S_if, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__update_positionsPfS_S_if, .Lfunc_end0-_Z31__device_stub__update_positionsPfS_S_if
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__calculate_forcesPfS_S_if # -- Begin function _Z31__device_stub__calculate_forcesPfS_S_if
	.type	_Z31__device_stub__calculate_forcesPfS_S_if,@function
_Z31__device_stub__calculate_forcesPfS_S_if: # @_Z31__device_stub__calculate_forcesPfS_S_if
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movss	%xmm0, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16calculate_forcesPfS_S_if, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__calculate_forcesPfS_S_if, .Lfunc_end1-_Z31__device_stub__calculate_forcesPfS_S_if
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI2_1:
	.long	0x41200000                      # float 10
.LCPI2_2:
	.long	0x3a83126f                      # float 0.00100000005
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$384, %edi                      # imm = 0x180
	callq	_Znam
	movq	%rax, %rbx
	movl	$384, %edi                      # imm = 0x180
	callq	_Znam
	movq	%rax, %r14
	movl	$384, %edi                      # imm = 0x180
	callq	_Znam
	movq	%rax, %r15
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI2_0(%rip), %xmm0
	mulss	.LCPI2_1(%rip), %xmm0
	movss	%xmm0, (%rbx,%r13,4)
	movl	%r12d, (%r14,%r13,4)
	movl	%r12d, (%r15,%r13,4)
	incq	%r13
	cmpq	$96, %r13
	jne	.LBB2_1
# %bb.2:
	leaq	16(%rsp), %r12
	movl	$384, %esi                      # imm = 0x180
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movl	$384, %esi                      # imm = 0x180
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	%rsp, %r13
	movl	$384, %esi                      # imm = 0x180
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$384, %edx                      # imm = 0x180
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$384, %edx                      # imm = 0x180
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movabsq	$4294967297, %r13               # imm = 0x100000001
	movl	$384, %edx                      # imm = 0x180
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	31(%r13), %rbp
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movss	.LCPI2_2(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$32, %ecx
	callq	_Z31__device_stub__update_positionsPfS_S_if
.LBB2_4:
	callq	hipDeviceSynchronize
	xorl	%r12d, %r12d
	movl	$384, %r8d                      # imm = 0x180
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movss	.LCPI2_2(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$32, %ecx
	callq	_Z31__device_stub__calculate_forcesPfS_S_if
.LBB2_6:
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rsi
	movl	$384, %edx                      # imm = 0x180
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$384, %edx                      # imm = 0x180
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	movl	$384, %edx                      # imm = 0x180
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB2_11
# %bb.7:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB2_8
# %bb.9:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB2_10
.LBB2_8:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_10:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %r12d
.LBB2_11:
	movl	%r12d, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16update_positionsPfS_S_if, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16calculate_forcesPfS_S_if, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16update_positionsPfS_S_if,@object # @_Z16update_positionsPfS_S_if
	.section	.rodata,"a",@progbits
	.globl	_Z16update_positionsPfS_S_if
	.p2align	3, 0x0
_Z16update_positionsPfS_S_if:
	.quad	_Z31__device_stub__update_positionsPfS_S_if
	.size	_Z16update_positionsPfS_S_if, 8

	.type	_Z16calculate_forcesPfS_S_if,@object # @_Z16calculate_forcesPfS_S_if
	.globl	_Z16calculate_forcesPfS_S_if
	.p2align	3, 0x0
_Z16calculate_forcesPfS_S_if:
	.quad	_Z31__device_stub__calculate_forcesPfS_S_if
	.size	_Z16calculate_forcesPfS_S_if, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16update_positionsPfS_S_if"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16calculate_forcesPfS_S_if"
	.size	.L__unnamed_2, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__update_positionsPfS_S_if
	.addrsig_sym _Z31__device_stub__calculate_forcesPfS_S_if
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16update_positionsPfS_S_if
	.addrsig_sym _Z16calculate_forcesPfS_S_if
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16update_positionsPfS_S_if ; -- Begin function _Z16update_positionsPfS_S_if
	.globl	_Z16update_positionsPfS_S_if
	.p2align	8
	.type	_Z16update_positionsPfS_S_if,@function
_Z16update_positionsPfS_S_if:           ; @_Z16update_positionsPfS_S_if
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_lshl_add_u32 v0, v1, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v6, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v10, v[6:7], off
	v_add_co_u32 v6, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[8:9], off
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 12
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v10, 0.5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, s3, v10
	v_mul_f32_e32 v10, s3, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, s3, v6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v7, v10
	global_store_b32 v[8:9], v6, off
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16update_positionsPfS_S_if
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16update_positionsPfS_S_if, .Lfunc_end0-_Z16update_positionsPfS_S_if
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 288
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16calculate_forcesPfS_S_if ; -- Begin function _Z16calculate_forcesPfS_S_if
	.globl	_Z16calculate_forcesPfS_S_if
	.p2align	8
	.type	_Z16calculate_forcesPfS_S_if,@function
_Z16calculate_forcesPfS_S_if:           ; @_Z16calculate_forcesPfS_S_if
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s2, v6
	s_cbranch_execz .LBB1_15
; %bb.1:                                ; %.preheader68
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	v_lshl_add_u32 v1, v6, 1, v6
	v_mul_u32_u24_e32 v0, 3, v0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v2, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
	v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v[0:1], off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_nc_u32_e32 v4, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 12
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3
	s_cbranch_scc0 .LBB1_2
; %bb.3:
	s_mov_b32 s8, 0
	s_cmp_lt_i32 s2, 1
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	v_mov_b32_e32 v2, s10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_13
; %bb.4:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	v_mov_b32_e32 v2, s10
	s_mov_b32 s9, 0
                                        ; implicit-def: $vgpr3_vgpr4_vgpr5
.LBB1_5:                                ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_7 Depth 2
                                        ;     Child Loop BB1_10 Depth 2
	s_mov_b32 s10, exec_lo
	v_cmpx_ne_u32_e64 s8, v6
	s_cbranch_execz .LBB1_12
; %bb.6:                                ; %.preheader
                                        ;   in Loop: Header=BB1_5 Depth=1
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, v10
	v_mov_b32_e32 v11, v9
	s_mov_b64 s[4:5], 0
	s_mov_b32 s11, s9
.LBB1_7:                                ;   Parent Loop BB1_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v14, v[11:12], off
	v_mov_b32_e32 v15, s11
	v_add_co_u32 v11, vcc_lo, v11, 4
	s_cmp_eq_u32 s4, 2
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	ds_load_b32 v15, v15
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s4, 0
	s_cselect_b32 s1, -1, 0
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_add_i32 s11, s11, 4
	s_cmp_eq_u32 s4, 3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v14, vcc_lo
	v_cndmask_b32_e64 v4, v4, v14, s0
	v_cndmask_b32_e64 v3, v3, v14, s1
	v_fmac_f32_e32 v13, v14, v14
	s_cbranch_scc0 .LBB1_7
; %bb.8:                                ;   in Loop: Header=BB1_5 Depth=1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_f32_e32 1.0, v13
	s_cbranch_execz .LBB1_11
; %bb.9:                                ;   in Loop: Header=BB1_5 Depth=1
	v_mul_f32_e32 v11, v13, v13
	s_mov_b64 s[4:5], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v13, v11
	v_div_scale_f32 v12, null, v11, v11, 2.0
	v_div_scale_f32 v16, vcc_lo, 2.0, v11, 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v12, v14, 1.0
	v_fmac_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v16, v14
	v_fma_f32 v17, -v12, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v17, v14
	v_fma_f32 v12, -v12, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v12, v12, v14, v15
	v_div_fixup_f32 v12, v12, v11, 2.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v14, null, v11, v11, v12
	v_div_scale_f32 v17, vcc_lo, v12, v11, v12
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v16, v15
	v_mul_f32_e32 v16, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v14, v16, v17
	v_fmac_f32_e32 v16, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v14, v16, v17
	v_div_fmas_f32 v14, v14, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v12, v14, v11, v12
	v_div_scale_f32 v14, null, v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v14, v16, 1.0
	v_fmac_f32_e32 v16, v18, v16
	v_div_scale_f32 v15, null, v11, v11, -1.0
	v_div_scale_f32 v20, vcc_lo, v12, v11, v12
	v_div_scale_f32 v18, s0, -1.0, v11, -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v15, v17, 1.0
	v_fmac_f32_e32 v17, v19, v17
	v_mul_f32_e32 v19, v20, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v18, v17
	v_fma_f32 v22, -v14, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, -v15, v21, v18
	v_fmac_f32_e32 v19, v22, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, v23, v17
	v_fma_f32 v14, -v14, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v15, v21, v18
	v_div_fmas_f32 v14, v14, v16, v19
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v15, v15, v17, v21
	v_div_fixup_f32 v12, v14, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v15, v11, -1.0
	v_add_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x41c00000, v11
	v_div_scale_f32 v12, null, v13, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v12, v14, 1.0
	v_fmac_f32_e32 v14, v15, v14
	v_div_scale_f32 v15, vcc_lo, v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, v15, v14
	v_fma_f32 v17, -v12, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v17, v14
	v_fma_f32 v12, -v12, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v12, v12, v14, v16
	v_div_fixup_f32 v11, v12, v13, v11
.LBB1_10:                               ;   Parent Loop BB1_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 2
	v_dual_cndmask_b32 v12, v3, v4 :: v_dual_cndmask_b32 v13, v0, v1
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s4, 0
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v5, s0
	v_cndmask_b32_e64 v13, v13, v2, s0
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 3
	v_fmac_f32_e32 v13, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v2, v13, s0
	v_cndmask_b32_e32 v1, v1, v13, vcc_lo
	v_cndmask_b32_e64 v0, v0, v13, s1
	s_cbranch_scc1 .LBB1_10
.LBB1_11:                               ; %Flow135
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB1_12:                               ; %Flow136
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, 1
	s_add_i32 s9, s9, 12
	s_cmp_eq_u32 s8, s2
	s_cbranch_scc0 .LBB1_5
.LBB1_13:                               ; %Flow138
	v_add_co_u32 v3, vcc_lo, s12, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
	s_mov_b64 s[0:1], 0
	s_barrier
	buffer_gl0_inv
.LBB1_14:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v7, v[3:4], off
	global_load_b32 v8, v[5:6], off
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v9, v0, v1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 3
	v_cndmask_b32_e32 v9, v9, v2, vcc_lo
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v9, v7
	v_mul_f32_e32 v7, 0.5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v8, s3, v7
	global_store_b32 v[5:6], v8, off
	global_store_b32 v[3:4], v9, off
	v_add_co_u32 v3, vcc_lo, v3, 4
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_cbranch_scc1 .LBB1_14
.LBB1_15:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16calculate_forcesPfS_S_if
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16calculate_forcesPfS_S_if, .Lfunc_end1-_Z16calculate_forcesPfS_S_if
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1232
; NumSgprs: 18
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16update_positionsPfS_S_if
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16update_positionsPfS_S_if.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16calculate_forcesPfS_S_if
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16calculate_forcesPfS_S_if.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
