#include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>

#define BLOCK_SIZE 16
#define N 4096

__global__ void navierStokesKernel(float* u, float* v, float* p, float* f, float* g, float* h, float dt, float dx, float dy, float Re) {
    extern __shared__ float shared_u[];
    float* shared_v = &shared_u[BLOCK_SIZE * BLOCK_SIZE];
    float* shared_p = &shared_v[BLOCK_SIZE * BLOCK_SIZE];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int i = bx * BLOCK_SIZE + tx;
    int j = by * BLOCK_SIZE + ty;

    // Load data into shared memory
    if (i < N && j < N) {
        shared_u[ty * BLOCK_SIZE + tx] = u[j * N + i];
        shared_v[ty * BLOCK_SIZE + tx] = v[j * N + i];
        shared_p[ty * BLOCK_SIZE + tx] = p[j * N + i];
    } else {
        shared_u[ty * BLOCK_SIZE + tx] = 0.0f;
        shared_v[ty * BLOCK_SIZE + tx] = 0.0f;
        shared_p[ty * BLOCK_SIZE + tx] = 0.0f;
    }

    __syncthreads();

    // Boundary conditions
    if (i == 0 || i == N - 1 || j == 0 || j == N - 1) {
        if (i < N && j < N) {
            u[j * N + i] = 0.0f;
            v[j * N + i] = 0.0f;
            p[j * N + i] = 0.0f;
        }
        return;
    }

    // Update velocities using Navier-Stokes equations
    if (i > 0 && i < N - 1 && j > 0 && j < N - 1) {
        float u_n = shared_u[(ty - 1) * BLOCK_SIZE + tx];
        float u_s = shared_u[(ty + 1) * BLOCK_SIZE + tx];
        float u_e = shared_u[ty * BLOCK_SIZE + (tx + 1)];
        float u_w = shared_u[ty * BLOCK_SIZE + (tx - 1)];
        float v_n = shared_v[(ty - 1) * BLOCK_SIZE + tx];
        float v_s = shared_v[(ty + 1) * BLOCK_SIZE + tx];
        float v_e = shared_v[ty * BLOCK_SIZE + (tx + 1)];
        float v_w = shared_v[ty * BLOCK_SIZE + (tx - 1)];
        float p_n = shared_p[(ty - 1) * BLOCK_SIZE + tx];
        float p_s = shared_p[(ty + 1) * BLOCK_SIZE + tx];
        float p_e = shared_p[ty * BLOCK_SIZE + (tx + 1)];
        float p_w = shared_p[ty * BLOCK_SIZE + (tx - 1)];

        float du_dt = (u_e - 2 * shared_u[ty * BLOCK_SIZE + tx] + u_w) / (dx * dx) +
                      (u_n - 2 * shared_u[ty * BLOCK_SIZE + tx] + u_s) / (dy * dy) -
                      (shared_u[ty * BLOCK_SIZE + tx] * (u_e - u_w) / (2 * dx) +
                       shared_v[ty * BLOCK_SIZE + tx] * (u_n - u_s) / (2 * dy)) -
                      (p_e - p_w) / (2 * dx) +
                      f[j * N + i] / Re;

        float dv_dt = (v_e - 2 * shared_v[ty * BLOCK_SIZE + tx] + v_w) / (dx * dx) +
                      (v_n - 2 * shared_v[ty * BLOCK_SIZE + tx] + v_s) / (dy * dy) -
                      (shared_u[ty * BLOCK_SIZE + tx] * (v_e - v_w) / (2 * dx) +
                       shared_v[ty * BLOCK_SIZE + tx] * (v_n - v_s) / (2 * dy)) -
                      (p_n - p_s) / (2 * dy) +
                      g[j * N + i] / Re;

        u[j * N + i] += du_dt * dt;
        v[j * N + i] += dv_dt * dt;
    }
}

int main() {
    float* d_u, *d_v, *d_p, *d_f, *d_g, *d_h;
    float* h_u = new float[N * N];
    float* h_v = new float[N * N];
    float* h_p = new float[N * N];
    float* h_f = new float[N * N];
    float* h_g = new float[N * N];
    float* h_h = new float[N * N];

    // Initialize data
    for (int i = 0; i < N * N; ++i) {
        h_u[i] = 0.0f;
        h_v[i] = 0.0f;
        h_p[i] = 0.0f;
        h_f[i] = 0.0f;
        h_g[i] = 0.0f;
        h_h[i] = 0.0f;
    }

    // Allocate device memory
    cudaMalloc(&d_u, N * N * sizeof(float));
    cudaMalloc(&d_v, N * N * sizeof(float));
    cudaMalloc(&d_p, N * N * sizeof(float));
    cudaMalloc(&d_f, N * N * sizeof(float));
    cudaMalloc(&d_g, N * N * sizeof(float));
    cudaMalloc(&d_h, N * N * sizeof(float));

    // Copy data to device
    cudaMemcpy(d_u, h_u, N * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_v, h_v, N * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_p, h_p, N * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_f, h_f, N * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_g, h_g, N * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_h, h_h, N * N * sizeof(float), cudaMemcpyHostToDevice);

    // Define parameters
    float dt = 0.01f;
    float dx = 1.0f / (N - 1);
    float dy = 1.0f / (N - 1);
    float Re = 100.0f;

    // Define grid and block dimensions
    dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    dim3 dimGrid((N + BLOCK_SIZE - 1) / BLOCK_SIZE, (N + BLOCK_SIZE - 1) / BLOCK_SIZE);

    // Launch kernel
    navierStokesKernel<<<dimGrid, dimBlock, 3 * BLOCK_SIZE * BLOCK_SIZE * sizeof(float)>>>(d_u, d_v, d_p, d_f, d_g, d_h, dt, dx, dy, Re);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    cudaMemcpy(h_u, d_u, N * N * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_v, d_v, N * N * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_p, d_p, N * N * sizeof(float), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_u);
    cudaFree(d_v);
    cudaFree(d_p);
    cudaFree(d_f);
    cudaFree(d_g);
    cudaFree(d_h);

    // Free host memory
    delete[] h_u;
    delete[] h_v;
    delete[] h_p;
    delete[] h_f;
    delete[] h_g;
    delete[] h_h;

    return 0;
}
	.file	"tmpxft_0002d45a_00000000-6_cuda_code_086186.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
	.type	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff, @function
_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movss	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z18navierStokesKernelPfS_S_S_S_S_ffff(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff, .-_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
	.globl	_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.type	_Z18navierStokesKernelPfS_S_S_S_S_ffff, @function
_Z18navierStokesKernelPfS_S_S_S_S_ffff:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
	.cfi_endproc
.LFE3661:
	.size	_Z18navierStokesKernelPfS_S_S_S_S_ffff, .-_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$67108864, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$67108864, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$67108864, %edi
	movq	%rax, 8(%rsp)
	call	_Znam@PLT
	movl	$67108864, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movl	$67108864, %edi
	movq	%rax, %r15
	call	_Znam@PLT
	movl	$67108864, %edi
	movq	%rax, %r14
	call	_Znam@PLT
	movl	$16777216, %ecx
	movq	%r12, %rdi
	movl	$67108864, %esi
	movq	%rax, %r13
	xorl	%eax, %eax
	rep stosl
	movq	8(%rsp), %rdi
	movl	$16777216, %ecx
	rep stosl
	movl	$16777216, %ecx
	movq	%rbx, %rdi
	rep stosl
	movl	$16777216, %ecx
	movq	%r15, %rdi
	rep stosl
	movl	$16777216, %ecx
	movq	%r14, %rdi
	rep stosl
	movl	$16777216, %ecx
	movq	%r13, %rdi
	rep stosl
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	movl	$3072, %r8d
	movabsq	$68719476752, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$1099511628032, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movss	.LC1(%rip), %xmm2
	movss	.LC0(%rip), %xmm3
	movss	.LC2(%rip), %xmm0
	movq	56(%rsp), %r9
	movq	48(%rsp), %r8
	movq	40(%rsp), %rcx
	movaps	%xmm2, %xmm1
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z52__device_stub__Z18navierStokesKernelPfS_S_S_S_S_ffffPfS_S_S_S_S_ffff
.L9:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L10
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L10:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$67108864, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	8(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r15, %rdi
	call	_ZdaPv@PLT
	movq	%r14, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L8:
	movq	88(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z18navierStokesKernelPfS_S_S_S_S_ffff"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18navierStokesKernelPfS_S_S_S_S_ffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1120403456
	.align 4
.LC1:
	.long	964691969
	.align 4
.LC2:
	.long	1008981770
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>


#define BLOCK_SIZE 16
#define N 4096

__global__ void navierStokesKernel(float* u, float* v, float* p, float* f, float* g, float* h, float dt, float dx, float dy, float Re) {
    extern __shared__ float shared_u[];
    float* shared_v = &shared_u[BLOCK_SIZE * BLOCK_SIZE];
    float* shared_p = &shared_v[BLOCK_SIZE * BLOCK_SIZE];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int i = bx * BLOCK_SIZE + tx;
    int j = by * BLOCK_SIZE + ty;

    // Load data into shared memory
    if (i < N && j < N) {
        shared_u[ty * BLOCK_SIZE + tx] = u[j * N + i];
        shared_v[ty * BLOCK_SIZE + tx] = v[j * N + i];
        shared_p[ty * BLOCK_SIZE + tx] = p[j * N + i];
    } else {
        shared_u[ty * BLOCK_SIZE + tx] = 0.0f;
        shared_v[ty * BLOCK_SIZE + tx] = 0.0f;
        shared_p[ty * BLOCK_SIZE + tx] = 0.0f;
    }

    __syncthreads();

    // Boundary conditions
    if (i == 0 || i == N - 1 || j == 0 || j == N - 1) {
        if (i < N && j < N) {
            u[j * N + i] = 0.0f;
            v[j * N + i] = 0.0f;
            p[j * N + i] = 0.0f;
        }
        return;
    }

    // Update velocities using Navier-Stokes equations
    if (i > 0 && i < N - 1 && j > 0 && j < N - 1) {
        float u_n = shared_u[(ty - 1) * BLOCK_SIZE + tx];
        float u_s = shared_u[(ty + 1) * BLOCK_SIZE + tx];
        float u_e = shared_u[ty * BLOCK_SIZE + (tx + 1)];
        float u_w = shared_u[ty * BLOCK_SIZE + (tx - 1)];
        float v_n = shared_v[(ty - 1) * BLOCK_SIZE + tx];
        float v_s = shared_v[(ty + 1) * BLOCK_SIZE + tx];
        float v_e = shared_v[ty * BLOCK_SIZE + (tx + 1)];
        float v_w = shared_v[ty * BLOCK_SIZE + (tx - 1)];
        float p_n = shared_p[(ty - 1) * BLOCK_SIZE + tx];
        float p_s = shared_p[(ty + 1) * BLOCK_SIZE + tx];
        float p_e = shared_p[ty * BLOCK_SIZE + (tx + 1)];
        float p_w = shared_p[ty * BLOCK_SIZE + (tx - 1)];

        float du_dt = (u_e - 2 * shared_u[ty * BLOCK_SIZE + tx] + u_w) / (dx * dx) +
                      (u_n - 2 * shared_u[ty * BLOCK_SIZE + tx] + u_s) / (dy * dy) -
                      (shared_u[ty * BLOCK_SIZE + tx] * (u_e - u_w) / (2 * dx) +
                       shared_v[ty * BLOCK_SIZE + tx] * (u_n - u_s) / (2 * dy)) -
                      (p_e - p_w) / (2 * dx) +
                      f[j * N + i] / Re;

        float dv_dt = (v_e - 2 * shared_v[ty * BLOCK_SIZE + tx] + v_w) / (dx * dx) +
                      (v_n - 2 * shared_v[ty * BLOCK_SIZE + tx] + v_s) / (dy * dy) -
                      (shared_u[ty * BLOCK_SIZE + tx] * (v_e - v_w) / (2 * dx) +
                       shared_v[ty * BLOCK_SIZE + tx] * (v_n - v_s) / (2 * dy)) -
                      (p_n - p_s) / (2 * dy) +
                      g[j * N + i] / Re;

        u[j * N + i] += du_dt * dt;
        v[j * N + i] += dv_dt * dt;
    }
}

int main() {
    float* d_u, *d_v, *d_p, *d_f, *d_g, *d_h;
    float* h_u = new float[N * N];
    float* h_v = new float[N * N];
    float* h_p = new float[N * N];
    float* h_f = new float[N * N];
    float* h_g = new float[N * N];
    float* h_h = new float[N * N];

    // Initialize data
    for (int i = 0; i < N * N; ++i) {
        h_u[i] = 0.0f;
        h_v[i] = 0.0f;
        h_p[i] = 0.0f;
        h_f[i] = 0.0f;
        h_g[i] = 0.0f;
        h_h[i] = 0.0f;
    }

    // Allocate device memory
    hipMalloc(&d_u, N * N * sizeof(float));
    hipMalloc(&d_v, N * N * sizeof(float));
    hipMalloc(&d_p, N * N * sizeof(float));
    hipMalloc(&d_f, N * N * sizeof(float));
    hipMalloc(&d_g, N * N * sizeof(float));
    hipMalloc(&d_h, N * N * sizeof(float));

    // Copy data to device
    hipMemcpy(d_u, h_u, N * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_v, h_v, N * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_p, h_p, N * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_f, h_f, N * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_g, h_g, N * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_h, h_h, N * N * sizeof(float), hipMemcpyHostToDevice);

    // Define parameters
    float dt = 0.01f;
    float dx = 1.0f / (N - 1);
    float dy = 1.0f / (N - 1);
    float Re = 100.0f;

    // Define grid and block dimensions
    dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
    dim3 dimGrid((N + BLOCK_SIZE - 1) / BLOCK_SIZE, (N + BLOCK_SIZE - 1) / BLOCK_SIZE);

    // Launch kernel
    navierStokesKernel<<<dimGrid, dimBlock, 3 * BLOCK_SIZE * BLOCK_SIZE * sizeof(float)>>>(d_u, d_v, d_p, d_f, d_g, d_h, dt, dx, dy, Re);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    hipMemcpy(h_u, d_u, N * N * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_v, d_v, N * N * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_p, d_p, N * N * sizeof(float), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_u);
    hipFree(d_v);
    hipFree(d_p);
    hipFree(d_f);
    hipFree(d_g);
    hipFree(d_h);

    // Free host memory
    delete[] h_u;
    delete[] h_v;
    delete[] h_p;
    delete[] h_f;
    delete[] h_g;
    delete[] h_h;

    return 0;
}
	.text
	.file	"cuda_code_086186.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff # -- Begin function _Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.type	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff,@function
_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff: # @_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	movq	%rsp, %r14
	movss	%xmm3, (%r14)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18navierStokesKernelPfS_S_S_S_S_ffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff, .Lfunc_end0-_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3c23d70a                      # float 0.00999999977
.LCPI1_1:
	.long	0x39800801                      # float 2.44200259E-4
.LCPI1_2:
	.long	0x42c80000                      # float 100
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	_Znam
	movq	%rax, %r15
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	_Znam
	movq	%rax, %r14
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	_Znam
	movq	%rax, %r12
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	_Znam
	movq	%rax, %r13
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	_Znam
	movq	%rax, %rbp
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	_Znam
	movq	%rax, %rbx
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%rbp, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	40(%rsp), %r15
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r14
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%r14, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	56(%rsp), %r15                  # 8-byte Reload
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movq	64(%rsp), %r14                  # 8-byte Reload
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%rbx, 48(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$1099511628032, %rdi            # imm = 0x10000000100
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$3072, %r8d                     # imm = 0xC00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movss	.LCPI1_2(%rip), %xmm3           # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm1, %xmm2
	callq	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
.LBB1_2:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_7
# %bb.3:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_4
# %bb.5:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_6
.LBB1_7:
	movq	40(%rsp), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_ZdaPv
	movq	%r13, %rdi
	callq	_ZdaPv
	movq	%rbp, %rdi
	callq	_ZdaPv
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_8
.LBB1_4:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_6:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_8:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18navierStokesKernelPfS_S_S_S_S_ffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18navierStokesKernelPfS_S_S_S_S_ffff,@object # @_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.section	.rodata,"a",@progbits
	.globl	_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.p2align	3, 0x0
_Z18navierStokesKernelPfS_S_S_S_S_ffff:
	.quad	_Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.size	_Z18navierStokesKernelPfS_S_S_S_S_ffff, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18navierStokesKernelPfS_S_S_S_S_ffff"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__navierStokesKernelPfS_S_S_S_S_ffff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18navierStokesKernelPfS_S_S_S_S_ffff
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18navierStokesKernelPfS_S_S_S_S_ffff ; -- Begin function _Z18navierStokesKernelPfS_S_S_S_S_ffff
	.globl	_Z18navierStokesKernelPfS_S_S_S_S_ffff
	.p2align	8
	.type	_Z18navierStokesKernelPfS_S_S_S_S_ffff,@function
_Z18navierStokesKernelPfS_S_S_S_S_ffff: ; @_Z18navierStokesKernelPfS_S_S_S_S_ffff
; %bb.0:
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_load_b256 s[16:23], s[0:1], 0x0
                                        ; implicit-def: $sgpr4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v3, s14, 4, v1
	v_lshl_add_u32 v2, s15, 4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v4, v3, v2
	v_cmp_gt_i32_e64 s2, 0x1000, v4
	v_cmp_lt_i32_e32 vcc_lo, 0xfff, v4
	v_lshl_add_u32 v4, v0, 4, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshl_add_u32 v4, v0, 4, v1
	v_mov_b32_e32 v6, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v5, v4, 2, 0
	ds_store_2addr_stride64_b32 v5, v6, v6 offset1:4
.LBB0_2:                                ; %Flow208
	s_or_saveexec_b32 s3, s3
	v_mov_b32_e32 v5, s4
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_lshl_add_u32 v5, v2, 12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v9, vcc_lo, s18, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s20, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s21, v6, vcc_lo
	global_load_b32 v7, v[7:8], off
	global_load_b32 v8, v[9:10], off
	global_load_b32 v5, v[5:6], off
	v_lshl_add_u32 v6, v4, 2, 0
	s_waitcnt vmcnt(1)
	ds_store_2addr_stride64_b32 v6, v7, v8 offset1:4
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cmp_ne_u32_e64 s3, 0xfff, v3
	v_cmp_ne_u32_e64 s4, 0, v2
	v_cmp_ne_u32_e64 s5, 0xfff, v2
	v_lshl_add_u32 v4, v4, 2, 0
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s3, vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s3, s4
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5 offset:2048
	s_and_b32 s3, s3, s5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s4
	s_cbranch_execz .LBB0_8
; %bb.5:
	v_add_nc_u32_e32 v4, -1, v3
	v_cmp_gt_u32_e64 s3, 0xfff, v2
	v_cmp_lt_i32_e64 s4, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_u32_e32 vcc_lo, 0xffe, v4
	s_and_b32 s3, vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s7, s3
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_lshl_add_u32 v2, v2, 12, v3
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 4, v0
	s_add_i32 s12, 0, 0x800
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_lshl_u32 v0, v1, v0, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, 0, v0
	v_add_co_u32 v4, vcc_lo, s22, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v3, vcc_lo
	v_subrev_nc_u32_e32 v16, 64, v0
	v_add_nc_u32_e32 v8, s12, v0
	v_add_nc_u32_e32 v6, -4, v1
	global_load_b32 v14, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v3, vcc_lo
	v_add_nc_u32_e32 v10, -4, v8
	global_load_b32 v15, v[4:5], off
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x20
	s_load_b128 s[8:11], s[0:1], 0x30
	s_add_i32 s0, 0, 0x400
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v17, s0, v0
	ds_load_2addr_b32 v[0:1], v1 offset0:1 offset1:16
	v_add_nc_u32_e32 v9, 0, v16
	ds_load_2addr_b32 v[6:7], v6 offset1:1
	ds_load_b32 v18, v9
	ds_load_2addr_b32 v[8:9], v8 offset0:1 offset1:16
	ds_load_b32 v19, v10
	v_add_nc_u32_e32 v12, s0, v16
	v_add_nc_u32_e32 v16, s12, v16
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v21, s9, s9
	v_add_f32_e64 v23, s9, s9
	v_mul_f32_e64 v22, s10, s10
	v_add_f32_e64 v24, s10, s10
	v_dual_sub_f32 v8, v8, v19 :: v_dual_add_nc_u32 v11, -4, v17
	ds_load_2addr_b32 v[10:11], v11 offset1:1
	ds_load_b32 v20, v12
	v_add_co_u32 v12, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v3, vcc_lo
	v_fma_f32 v25, -2.0, v7, v18
	v_sub_f32_e32 v18, v18, v1
	v_div_scale_f32 v19, s0, v8, v23, v8
	global_load_b32 v12, v[12:13], off
	v_fma_f32 v13, -2.0, v7, v0
	v_dual_sub_f32 v0, v0, v6 :: v_dual_add_f32 v1, v1, v25
	ds_load_b32 v16, v16
	v_add_f32_e32 v6, v6, v13
	v_mul_f32_e32 v0, v0, v7
	v_div_scale_f32 v27, null, v22, v22, v1
	s_waitcnt lgkmcnt(2)
	v_mul_f32_e32 v13, v18, v11
	v_div_scale_f32 v18, null, v23, v23, v8
	v_div_scale_f32 v25, null, v21, v21, v6
	v_div_scale_f32 v28, null, v23, v23, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v30, v18
	v_rcp_f32_e32 v31, v25
	v_rcp_f32_e32 v32, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v33, v28
	v_div_scale_f32 v26, vcc_lo, v6, v21, v6
	v_div_scale_f32 v36, s3, v0, v23, v0
	v_div_scale_f32 v29, null, v24, v24, v13
	v_fma_f32 v38, -v18, v30, 1.0
	v_fma_f32 v39, -v25, v31, 1.0
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_fma_f32 v40, -v27, v32, 1.0
	v_fma_f32 v41, -v28, v33, 1.0
	v_rcp_f32_e32 v34, v29
	v_div_scale_f32 v35, s1, v1, v22, v1
	v_fmac_f32_e32 v31, v39, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v33, v41, v33 :: v_dual_fmac_f32 v30, v38, v30
	v_fmac_f32_e32 v32, v40, v32
	v_div_scale_f32 v37, s4, v13, v24, v13
	v_mul_f32_e32 v39, v26, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_dual_mul_f32 v41, v36, v33 :: v_dual_mul_f32 v38, v19, v30
	v_fma_f32 v42, -v29, v34, 1.0
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v9, v16, v9
	v_fma_f32 v44, -v25, v39, v26
	v_fma_f32 v47, -v28, v41, v36
	v_fma_f32 v43, -v18, v38, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v34, v42, v34 :: v_dual_fmac_f32 v39, v44, v31
	v_fmac_f32_e32 v41, v47, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v38, v43, v30
	v_mul_f32_e32 v42, v37, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -v18, v38, v19
	v_fma_f32 v19, -v25, v39, v26
	v_fma_f32 v48, -v29, v42, v37
	v_fma_f32 v26, -v28, v41, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v19, v19, v31, v39
	v_fmac_f32_e32 v42, v48, v34
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v6, v19, v21, v6
	v_mul_f32_e32 v40, v35, v32
	v_fma_f32 v46, -v27, v40, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v40, v46, v32
	v_fma_f32 v25, -v27, v40, v35
	v_fma_f32 v27, -v29, v42, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v25, v25, v32, v40
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v26, v26, v33, v41
	s_mov_b32 vcc_lo, s4
	v_div_fixup_f32 v1, v25, v22, v1
	v_div_fmas_f32 v27, v27, v34, v42
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v0, v26, v23, v0
	v_div_fmas_f32 v18, v18, v30, v38
	v_add_f32_e32 v1, v6, v1
	v_div_fixup_f32 v13, v27, v24, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v8, v18, v23, v8
	v_add_f32_e32 v0, v0, v13
	v_fma_f32 v13, -2.0, v11, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v1, v0
	v_sub_f32_e32 v0, v0, v8
	s_waitcnt vmcnt(2)
	v_div_scale_f32 v45, null, s11, s11, v14
	v_div_scale_f32 v29, s5, v14, s11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 vcc_lo, s5
	v_rcp_f32_e32 v43, v45
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v45, v43, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v43, v28, v43
	v_mul_f32_e32 v28, v29, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v45, v28, v29
	v_fmac_f32_e32 v28, v19, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v45, v28, v29
	v_div_fmas_f32 v1, v6, v43, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v1, v1, s11, v14
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v29, null, s11, s11, v12
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v15, s8, v0
	v_add_co_u32 v0, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v3, vcc_lo
	global_store_b32 v[4:5], v15, off
	ds_load_2addr_b32 v[2:3], v17 offset0:1 offset1:16
	global_load_b32 v4, v[0:1], off
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v13, v3, v13
	v_sub_f32_e32 v3, v20, v3
	v_fma_f32 v5, -2.0, v11, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v15, null, v22, v22, v13
	v_mul_f32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v10, v5
	v_div_scale_f32 v19, null, v24, v24, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v6, null, v21, v21, v5
	v_div_scale_f32 v16, s3, v3, v24, v3
	v_rcp_f32_e32 v25, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v19, v25, 1.0
	v_fma_f32 v14, -v6, v8, 1.0
	v_dual_fmac_f32 v25, v27, v25 :: v_dual_sub_f32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v8, v14, v8
	v_rcp_f32_e32 v10, v15
	v_div_scale_f32 v27, null, v24, v24, v9
	v_mul_f32_e32 v2, v2, v7
	v_div_scale_f32 v7, vcc_lo, v5, v21, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v14, null, v23, v23, v2
	v_mul_f32_e32 v17, v7, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v15, v10, 1.0
	v_rcp_f32_e32 v11, v14
	v_fma_f32 v20, -v6, v17, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v18, v10
	v_div_scale_f32 v18, s0, v13, v22, v13
	v_dual_fmac_f32 v17, v20, v8 :: v_dual_mul_f32 v20, v18, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v14, v11, 1.0
	v_fma_f32 v6, -v6, v17, v7
	v_fma_f32 v7, -v15, v20, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v11, v26, v11
	v_div_scale_f32 v26, s1, v2, v23, v2
	v_div_fmas_f32 v6, v6, v8, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v17, v16, v25 :: v_dual_fmac_f32 v20, v7, v10
	v_mul_f32_e32 v28, v26, v11
	v_rcp_f32_e32 v7, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v5, v6, v21, v5
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v6, -v15, v20, v18
	v_fma_f32 v8, -v14, v28, v26
	v_rcp_f32_e32 v15, v29
	v_div_fmas_f32 v6, v6, v10, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_fmac_f32_e32 v28, v8, v11
	v_fma_f32 v8, -v19, v17, v16
	v_fma_f32 v18, -v27, v7, 1.0
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v6, v6, v22, v13
	v_fma_f32 v10, -v14, v28, v26
	v_fmac_f32_e32 v17, v8, v25
	v_fmac_f32_e32 v7, v18, v7
	v_div_scale_f32 v8, s0, v9, v24, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v10, v10, v11, v28
	v_fma_f32 v16, -v19, v17, v16
	s_mov_b32 vcc_lo, s3
	v_fma_f32 v14, -v29, v15, 1.0
	v_mul_f32_e32 v11, v8, v7
	v_div_fixup_f32 v2, v10, v23, v2
	v_div_fmas_f32 v16, v16, v25, v17
	v_add_f32_e32 v5, v5, v6
	v_fmac_f32_e32 v15, v14, v15
	v_div_scale_f32 v14, s1, v12, s11, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v16, v24, v3
	v_fma_f32 v18, -v27, v11, v8
	s_mov_b32 vcc_lo, s0
	v_add_f32_e32 v2, v2, v3
	v_mul_f32_e32 v17, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v11, v18, v7 :: v_dual_sub_f32 v2, v5, v2
	v_fma_f32 v10, -v29, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v27, v11, v8
	v_fmac_f32_e32 v17, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v6, v7, v11
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v6, -v29, v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v3, v3, v24, v9
	v_div_fmas_f32 v5, v6, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v2, v3
	v_div_fixup_f32 v3, v5, s11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, s8, v2
	global_store_b32 v[0:1], v4, off
.LBB0_7:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr3
.LBB0_8:                                ; %Flow207
	s_and_not1_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_11
; %bb.9:
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_lshl_add_u32 v0, v2, 12, v3
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	global_store_b32 v[4:5], v6, off
	global_store_b32 v[2:3], v6, off
	global_store_b32 v[0:1], v6, off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18navierStokesKernelPfS_S_S_S_S_ffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 64
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 49
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18navierStokesKernelPfS_S_S_S_S_ffff, .Lfunc_end0-_Z18navierStokesKernelPfS_S_S_S_S_ffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2120
; NumSgprs: 26
; NumVgprs: 49
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 49
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 64
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18navierStokesKernelPfS_S_S_S_S_ffff
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z18navierStokesKernelPfS_S_S_S_S_ffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     49
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
