#include <iostream>
#include <cuda_runtime.h>
#include <cassert>

// Define the dimensions of the input, filter, and output
#define INPUT_WIDTH 28
#define INPUT_HEIGHT 28
#define FILTER_WIDTH 5
#define FILTER_HEIGHT 5
#define NUM_FILTERS 32
#define BATCH_SIZE 16
#define STRIDE 1
#define PADDING 2
#define OUTPUT_WIDTH ((INPUT_WIDTH - FILTER_WIDTH + 2 * PADDING) / STRIDE + 1)
#define OUTPUT_HEIGHT ((INPUT_HEIGHT - FILTER_HEIGHT + 2 * PADDING) / STRIDE + 1)

// CUDA kernel for backpropagation in convolutional layer
__global__ void convBackwardKernel(
    float* d_input_grad, const float* d_output_grad, const float* d_filter, 
    int input_width, int input_height, int filter_width, int filter_height, 
    int num_filters, int batch_size, int stride, int padding) {

    // Shared memory to store the input patch and filter
    extern __shared__ float shared_memory[];

    // Calculate the starting index for the input and output
    int n = blockIdx.x; // Batch index
    int f = blockIdx.y; // Filter index
    int h_out = blockIdx.z / blockDim.y; // Output height index
    int w_out = blockIdx.z % blockDim.y; // Output width index

    // Calculate the corresponding input indices
    int h_in = h_out * stride - padding;
    int w_in = w_out * stride - padding;

    // Calculate the gradient for the input
    float input_grad = 0.0f;

    // Load filter into shared memory
    int filter_idx = f * filter_height * filter_width + threadIdx.y * filter_width + threadIdx.x;
    shared_memory[threadIdx.y * blockDim.x + threadIdx.x] = d_filter[filter_idx];
    __syncthreads();

    // Perform the convolution backpropagation
    for (int fh = 0; fh < filter_height; ++fh) {
        for (int fw = 0; fw < filter_width; ++fw) {
            int h = h_in + fh;
            int w = w_in + fw;
            if (h >= 0 && h < input_height && w >= 0 && w < input_width) {
                int output_idx = n * num_filters * OUTPUT_HEIGHT * OUTPUT_WIDTH + 
                                 f * OUTPUT_HEIGHT * OUTPUT_WIDTH + 
                                 h_out * OUTPUT_WIDTH + w_out;
                int input_idx = n * input_height * input_width + h * input_width + w;
                input_grad += d_output_grad[output_idx] * shared_memory[fh * filter_width + fw];
            }
        }
    }

    // Write the result to global memory
    int input_grad_idx = n * num_filters * input_height * input_width + 
                         f * input_height * input_width + 
                         h_in * input_width + w_in;
    atomicAdd(&d_input_grad[input_grad_idx], input_grad);
}

int main() {
    // Allocate and initialize host memory
    size_t input_size = BATCH_SIZE * INPUT_HEIGHT * INPUT_WIDTH * sizeof(float);
    size_t filter_size = NUM_FILTERS * FILTER_HEIGHT * FILTER_WIDTH * sizeof(float);
    size_t output_size = BATCH_SIZE * NUM_FILTERS * OUTPUT_HEIGHT * OUTPUT_WIDTH * sizeof(float);

    float* h_input_grad = (float*)malloc(input_size);
    float* h_output_grad = (float*)malloc(output_size);
    float* h_filter = (float*)malloc(filter_size);

    // Initialize data
    for (size_t i = 0; i < input_size / sizeof(float); ++i) h_input_grad[i] = 0.0f;
    for (size_t i = 0; i < output_size / sizeof(float); ++i) h_output_grad[i] = 1.0f; // Example gradient
    for (size_t i = 0; i < filter_size / sizeof(float); ++i) h_filter[i] = 0.5f; // Example filter weights

    // Allocate Unified Memory
    float* d_input_grad;
    float* d_output_grad;
    float* d_filter;
    cudaMallocManaged(&d_input_grad, input_size);
    cudaMallocManaged(&d_output_grad, output_size);
    cudaMallocManaged(&d_filter, filter_size);

    // Copy data to device
    cudaMemcpy(d_output_grad, h_output_grad, output_size, cudaMemcpyHostToDevice);
    cudaMemcpy(d_filter, h_filter, filter_size, cudaMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(FILTER_WIDTH, FILTER_HEIGHT);
    dim3 gridSize(BATCH_SIZE, NUM_FILTERS, OUTPUT_HEIGHT * OUTPUT_WIDTH);

    // Launch kernel
    size_t sharedMemSize = FILTER_HEIGHT * FILTER_WIDTH * sizeof(float);
    convBackwardKernel<<<gridSize, blockSize, sharedMemSize>>>(d_input_grad, d_output_grad, d_filter, 
                                                            INPUT_WIDTH, INPUT_HEIGHT, FILTER_WIDTH, FILTER_HEIGHT, 
                                                            NUM_FILTERS, BATCH_SIZE, STRIDE, PADDING);

    // Synchronize and check for errors
    cudaError_t err = cudaDeviceSynchronize();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    cudaMemcpy(h_input_grad, d_input_grad, input_size, cudaMemcpyDeviceToHost);

    // Free memory
    cudaFree(d_input_grad);
    cudaFree(d_output_grad);
    cudaFree(d_filter);
    free(h_input_grad);
    free(h_output_grad);
    free(h_filter);

    return 0;
}
	.file	"tmpxft_000e2575_00000000-6_cuda_code_075220.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z18convBackwardKernelPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.type	_Z52__device_stub__Z18convBackwardKernelPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, @function
_Z52__device_stub__Z18convBackwardKernelPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z18convBackwardKernelPfPKfS1_iiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z52__device_stub__Z18convBackwardKernelPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, .-_Z52__device_stub__Z18convBackwardKernelPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.globl	_Z18convBackwardKernelPfPKfS1_iiiiiiii
	.type	_Z18convBackwardKernelPfPKfS1_iiiiiiii, @function
_Z18convBackwardKernelPfPKfS1_iiiiiiii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z18convBackwardKernelPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.cfi_endproc
.LFE3661:
	.size	_Z18convBackwardKernelPfPKfS1_iiiiiiii, .-_Z18convBackwardKernelPfPKfS1_iiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$50176, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$1605632, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$3200, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$12544, %ecx
	movq	%rbx, %rdi
	movss	.LC0(%rip), %xmm0
	movq	%rax, %rbp
	xorl	%eax, %eax
	rep stosl
	xorl	%eax, %eax
.L9:
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$401408, %rax
	jne	.L9
	movss	.LC1(%rip), %xmm0
	xorl	%eax, %eax
.L10:
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$800, %rax
	jne	.L10
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$50176, %esi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$1605632, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$3200, %esi
	call	cudaMallocManaged@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$1605632, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$3200, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	movl	$100, %r8d
	movabsq	$21474836485, %rdx
	movl	$1, %ecx
	movl	$784, %esi
	movabsq	$137438953488, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	$5, %r9d
	movl	$28, %r8d
	movl	$28, %ecx
	pushq	$2
	.cfi_def_cfa_offset 128
	pushq	$1
	.cfi_def_cfa_offset 136
	pushq	$16
	.cfi_def_cfa_offset 144
	pushq	$32
	.cfi_def_cfa_offset 152
	pushq	$5
	.cfi_def_cfa_offset 160
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z52__device_stub__Z18convBackwardKernelPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	addq	$48, %rsp
	.cfi_def_cfa_offset 112
.L11:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %r13d
	testl	%eax, %eax
	je	.L12
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L12:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$50176, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	xorl	%eax, %eax
.L8:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z18convBackwardKernelPfPKfS1_iiiiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convBackwardKernelPfPKfS1_iiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	1056964608
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <cassert>

// Define the dimensions of the input, filter, and output
#define INPUT_WIDTH 28
#define INPUT_HEIGHT 28
#define FILTER_WIDTH 5
#define FILTER_HEIGHT 5
#define NUM_FILTERS 32
#define BATCH_SIZE 16
#define STRIDE 1
#define PADDING 2
#define OUTPUT_WIDTH ((INPUT_WIDTH - FILTER_WIDTH + 2 * PADDING) / STRIDE + 1)
#define OUTPUT_HEIGHT ((INPUT_HEIGHT - FILTER_HEIGHT + 2 * PADDING) / STRIDE + 1)

// CUDA kernel for backpropagation in convolutional layer
__global__ void convBackwardKernel(
    float* d_input_grad, const float* d_output_grad, const float* d_filter, 
    int input_width, int input_height, int filter_width, int filter_height, 
    int num_filters, int batch_size, int stride, int padding) {

    // Shared memory to store the input patch and filter
    extern __shared__ float shared_memory[];

    // Calculate the starting index for the input and output
    int n = blockIdx.x; // Batch index
    int f = blockIdx.y; // Filter index
    int h_out = blockIdx.z / blockDim.y; // Output height index
    int w_out = blockIdx.z % blockDim.y; // Output width index

    // Calculate the corresponding input indices
    int h_in = h_out * stride - padding;
    int w_in = w_out * stride - padding;

    // Calculate the gradient for the input
    float input_grad = 0.0f;

    // Load filter into shared memory
    int filter_idx = f * filter_height * filter_width + threadIdx.y * filter_width + threadIdx.x;
    shared_memory[threadIdx.y * blockDim.x + threadIdx.x] = d_filter[filter_idx];
    __syncthreads();

    // Perform the convolution backpropagation
    for (int fh = 0; fh < filter_height; ++fh) {
        for (int fw = 0; fw < filter_width; ++fw) {
            int h = h_in + fh;
            int w = w_in + fw;
            if (h >= 0 && h < input_height && w >= 0 && w < input_width) {
                int output_idx = n * num_filters * OUTPUT_HEIGHT * OUTPUT_WIDTH + 
                                 f * OUTPUT_HEIGHT * OUTPUT_WIDTH + 
                                 h_out * OUTPUT_WIDTH + w_out;
                int input_idx = n * input_height * input_width + h * input_width + w;
                input_grad += d_output_grad[output_idx] * shared_memory[fh * filter_width + fw];
            }
        }
    }

    // Write the result to global memory
    int input_grad_idx = n * num_filters * input_height * input_width + 
                         f * input_height * input_width + 
                         h_in * input_width + w_in;
    atomicAdd(&d_input_grad[input_grad_idx], input_grad);
}

int main() {
    // Allocate and initialize host memory
    size_t input_size = BATCH_SIZE * INPUT_HEIGHT * INPUT_WIDTH * sizeof(float);
    size_t filter_size = NUM_FILTERS * FILTER_HEIGHT * FILTER_WIDTH * sizeof(float);
    size_t output_size = BATCH_SIZE * NUM_FILTERS * OUTPUT_HEIGHT * OUTPUT_WIDTH * sizeof(float);

    float* h_input_grad = (float*)malloc(input_size);
    float* h_output_grad = (float*)malloc(output_size);
    float* h_filter = (float*)malloc(filter_size);

    // Initialize data
    for (size_t i = 0; i < input_size / sizeof(float); ++i) h_input_grad[i] = 0.0f;
    for (size_t i = 0; i < output_size / sizeof(float); ++i) h_output_grad[i] = 1.0f; // Example gradient
    for (size_t i = 0; i < filter_size / sizeof(float); ++i) h_filter[i] = 0.5f; // Example filter weights

    // Allocate Unified Memory
    float* d_input_grad;
    float* d_output_grad;
    float* d_filter;
    hipMallocManaged(&d_input_grad, input_size);
    hipMallocManaged(&d_output_grad, output_size);
    hipMallocManaged(&d_filter, filter_size);

    // Copy data to device
    hipMemcpy(d_output_grad, h_output_grad, output_size, hipMemcpyHostToDevice);
    hipMemcpy(d_filter, h_filter, filter_size, hipMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(FILTER_WIDTH, FILTER_HEIGHT);
    dim3 gridSize(BATCH_SIZE, NUM_FILTERS, OUTPUT_HEIGHT * OUTPUT_WIDTH);

    // Launch kernel
    size_t sharedMemSize = FILTER_HEIGHT * FILTER_WIDTH * sizeof(float);
    convBackwardKernel<<<gridSize, blockSize, sharedMemSize>>>(d_input_grad, d_output_grad, d_filter, 
                                                            INPUT_WIDTH, INPUT_HEIGHT, FILTER_WIDTH, FILTER_HEIGHT, 
                                                            NUM_FILTERS, BATCH_SIZE, STRIDE, PADDING);

    // Synchronize and check for errors
    hipError_t err = hipDeviceSynchronize();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    hipMemcpy(h_input_grad, d_input_grad, input_size, hipMemcpyDeviceToHost);

    // Free memory
    hipFree(d_input_grad);
    hipFree(d_output_grad);
    hipFree(d_filter);
    free(h_input_grad);
    free(h_output_grad);
    free(h_filter);

    return 0;
}
	.text
	.file	"cuda_code_075220.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii # -- Begin function _Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii
	.type	_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii,@function
_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii: # @_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convBackwardKernelPfPKfS1_iiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii, .Lfunc_end0-_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:                                # %.preheader46.preheader
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1, %edi
	movl	$50176, %esi                    # imm = 0xC400
	callq	calloc@PLT
	movq	%rax, %rbx
	movl	$1605632, %edi                  # imm = 0x188000
	callq	malloc
	movq	%rax, %r14
	movl	$3200, %edi                     # imm = 0xC80
	callq	malloc
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB1_1:                                # %.preheader46
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r14,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$401408, %rax                   # imm = 0x62000
	jne	.LBB1_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$1056964608, (%r15,%rax,4)      # imm = 0x3F000000
	incq	%rax
	cmpq	$800, %rax                      # imm = 0x320
	jne	.LBB1_3
# %bb.4:
	movq	%rsp, %rdi
	movl	$50176, %esi                    # imm = 0xC400
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %r12
	movl	$1605632, %esi                  # imm = 0x188000
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %r13
	movl	$3200, %esi                     # imm = 0xC80
	movq	%r13, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%r12), %rdi
	movl	$1605632, %edx                  # imm = 0x188000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$3200, %edx                     # imm = 0xC80
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$137438953488, %rdi             # imm = 0x2000000010
	movabsq	$21474836485, %rdx              # imm = 0x500000005
	movl	$100, %r8d
	movl	$784, %esi                      # imm = 0x310
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$28, %ecx
	movl	$28, %r8d
	movl	$5, %r9d
	pushq	$2
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	pushq	$16
	.cfi_adjust_cfa_offset 8
	pushq	$32
	.cfi_adjust_cfa_offset 8
	pushq	$5
	.cfi_adjust_cfa_offset 8
	callq	_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB1_6:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB1_11
# %bb.7:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_8
# %bb.9:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_10
.LBB1_11:
	movq	(%rsp), %rsi
	movl	$50176, %edx                    # imm = 0xC400
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	jmp	.LBB1_12
.LBB1_8:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_10:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_12:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convBackwardKernelPfPKfS1_iiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convBackwardKernelPfPKfS1_iiiiiiii,@object # @_Z18convBackwardKernelPfPKfS1_iiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z18convBackwardKernelPfPKfS1_iiiiiiii
	.p2align	3, 0x0
_Z18convBackwardKernelPfPKfS1_iiiiiiii:
	.quad	_Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii
	.size	_Z18convBackwardKernelPfPKfS1_iiiiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convBackwardKernelPfPKfS1_iiiiiiii"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convBackwardKernelPfPKfS1_iiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convBackwardKernelPfPKfS1_iiiiiiii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convBackwardKernelPfPKfS1_iiiiiiii ; -- Begin function _Z18convBackwardKernelPfPKfS1_iiiiiiii
	.globl	_Z18convBackwardKernelPfPKfS1_iiiiiiii
	.p2align	8
	.type	_Z18convBackwardKernelPfPKfS1_iiiiiiii,@function
_Z18convBackwardKernelPfPKfS1_iiiiiiii: ; @_Z18convBackwardKernelPfPKfS1_iiiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x44
	s_load_b64 s[8:9], s[0:1], 0x30
	s_load_b32 s11, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, s14, s7, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s6, v[0:1]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_lshr_b32 s2, s10, 16
	s_and_b32 s17, s2, 0xffff
	global_load_b32 v2, v[2:3], off
	v_cvt_f32_u32_e32 v3, s17
	s_sub_i32 s3, 0, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v3
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s2, s3
	s_add_i32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s12, s15, s2
	s_mul_i32 s2, s12, s17
	s_add_i32 s18, s12, 1
	s_sub_i32 s16, s15, s2
	s_load_b128 s[0:3], s[0:1], 0x0
	s_sub_i32 s19, s16, s17
	s_cmp_ge_u32 s16, s17
	s_cselect_b32 s12, s18, s12
	s_cselect_b32 s16, s19, s16
	s_add_i32 s18, s12, 1
	s_cmp_ge_u32 s16, s17
	s_mov_b32 s16, 0
	s_cselect_b32 s12, s18, s12
	s_and_b32 s10, s10, 0xffff
	s_mul_i32 s17, s12, s17
	v_mad_u32_u24 v0, v1, s10, v0
	s_sub_i32 s15, s15, s17
	s_mul_i32 s10, s12, s8
	s_cmp_gt_i32 s7, 0
	s_mul_i32 s17, s15, s8
	v_lshl_add_u32 v0, v0, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_2
; %bb.1:                                ; %.._crit_edge75_crit_edge
	s_mul_i32 s8, s13, s11
	s_mov_b32 s18, 0
	s_add_i32 s8, s8, s14
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr18
                                        ; implicit-def: $sgpr8
.LBB0_3:                                ; %Flow121
	v_mov_b32_e32 v0, s18
	s_sub_i32 s10, s10, s9
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_sub_i32 s9, s17, s9
	s_cbranch_vccnz .LBB0_12
; %bb.4:                                ; %.preheader.lr.ph
	s_cmp_gt_i32 s6, 0
	s_mul_i32 s8, s13, s11
	s_cselect_b32 s11, -1, 0
	s_add_i32 s8, s8, s14
	s_mul_i32 s12, s12, 28
	s_mul_i32 s13, s8, 0x310
	v_mov_b32_e32 v0, 0
	s_add_i32 s12, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s14, s12, s15
	s_mov_b32 s12, 0
	s_ashr_i32 s15, s14, 31
	s_lshl_b64 s[14:15], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s2, s14
	s_addc_u32 s3, s3, s15
	s_lshl_b32 s13, s6, 2
	s_mov_b32 s14, 0
.LBB0_5:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_11
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_add_i32 s17, s14, s10
	s_mov_b32 s15, s9
	s_cmp_gt_i32 s17, -1
	s_mov_b32 s18, s12
	s_cselect_b32 s16, -1, 0
	s_cmp_lt_i32 s17, s5
	s_mov_b32 s19, s6
	s_cselect_b32 s17, -1, 0
.LBB0_7:                                ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_10
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=2
	s_cmp_gt_i32 s15, -1
	s_cselect_b32 s20, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s20, s17, s20
	s_cmp_lt_i32 s15, s4
	s_cselect_b32 s21, -1, 0
	s_and_b32 s20, s20, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=2
	v_mov_b32_e32 v1, s18
	s_load_b32 s20, s[2:3], 0x0
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v0, s20, v1
.LBB0_10:                               ;   in Loop: Header=BB0_7 Depth=2
	s_add_i32 s19, s19, -1
	s_add_i32 s18, s18, 4
	s_add_i32 s15, s15, 1
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc0 .LBB0_7
.LBB0_11:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_add_i32 s14, s14, 1
	s_add_i32 s12, s12, s13
	s_cmp_eq_u32 s14, s7
	s_cbranch_scc0 .LBB0_5
.LBB0_12:                               ; %._crit_edge75
	s_mov_b32 s3, exec_lo
	s_mov_b32 s2, 0
	v_mbcnt_lo_u32_b32 v1, s3, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_15
; %bb.13:
	s_mul_i32 s5, s8, s5
	v_mov_b32_e32 v3, 0
	s_add_i32 s5, s10, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s5, s4
	s_add_i32 s4, s4, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s5, s4, 31
	s_lshl_b64 s[4:5], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	s_bcnt1_i32_b32 s3, s3
	s_load_b32 s4, s[0:1], 0x0
	v_cvt_f32_ubyte0_e32 v1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v2, v0, v1 :: v_dual_mov_b32 v1, s4
.LBB0_14:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v2
	global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_14
.LBB0_15:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convBackwardKernelPfPKfS1_iiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convBackwardKernelPfPKfS1_iiiiiiii, .Lfunc_end0-_Z18convBackwardKernelPfPKfS1_iiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 760
; NumSgprs: 24
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         176
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convBackwardKernelPfPKfS1_iiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z18convBackwardKernelPfPKfS1_iiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
