#include <iostream>
#include <cuda_runtime.h>
#include <vector>

// Define the size of the sparse tensor
#define NUM_NON_ZERO 4096

// Kernel to perform sparse tensor operations
__global__ void sparseTensorKernel(const int* row_indices, const int* col_indices, const float* values, float* result, int num_non_zero) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < num_non_zero) {
        atomicAdd(&result[row_indices[idx]], values[idx] * values[col_indices[idx]]);
    }
}

int main() {
    // Initialize device
    int deviceCount;
    cudaGetDeviceCount(&deviceCount);
    if (deviceCount == 0) {
        std::cerr << "No CUDA-capable devices found." << std::endl;
        return -1;
    }
    cudaSetDevice(0); // Use the first GPU

    // Host data
    std::vector<int> h_row_indices(NUM_NON_ZERO);
    std::vector<int> h_col_indices(NUM_NON_ZERO);
    std::vector<float> h_values(NUM_NON_ZERO);
    std::vector<float> h_result(4096, 0.0f); // Assuming a square matrix of size 4096

    // Fill with dummy data for demonstration
    for (int i = 0; i < NUM_NON_ZERO; ++i) {
        h_row_indices[i] = i % 4096;
        h_col_indices[i] = (i * 2) % 4096;
        h_values[i] = 1.0f;
    }

    // Device data
    int* d_row_indices;
    int* d_col_indices;
    float* d_values;
    float* d_result;

    // Allocate device memory
    cudaMalloc((void**)&d_row_indices, NUM_NON_ZERO * sizeof(int));
    cudaMalloc((void**)&d_col_indices, NUM_NON_ZERO * sizeof(int));
    cudaMalloc((void**)&d_values, NUM_NON_ZERO * sizeof(float));
    cudaMalloc((void**)&d_result, 4096 * sizeof(float));

    // Copy data from host to device
    cudaMemcpy(d_row_indices, h_row_indices.data(), NUM_NON_ZERO * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_col_indices, h_col_indices.data(), NUM_NON_ZERO * sizeof(int), cudaMemcpyHostToDevice);
    cudaMemcpy(d_values, h_values.data(), NUM_NON_ZERO * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_result, h_result.data(), 4096 * sizeof(float), cudaMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(256);
    dim3 gridSize((NUM_NON_ZERO + blockSize.x - 1) / blockSize.x);

    // Launch kernel
    sparseTensorKernel<<<gridSize, blockSize>>>(d_row_indices, d_col_indices, d_values, d_result, NUM_NON_ZERO);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA kernel launch failed: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    cudaMemcpy(h_result.data(), d_result, 4096 * sizeof(float), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_row_indices);
    cudaFree(d_col_indices);
    cudaFree(d_values);
    cudaFree(d_result);

    // Output result for verification
    std::cout << "First 10 results: ";
    for (int i = 0; i < 10; ++i) {
        std::cout << h_result[i] << " ";
    }
    std::cout << std::endl;

    return 0;
}
	.file	"tmpxft_000f7add_00000000-6_cuda_code_074178.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4001:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4001:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z18sparseTensorKernelPKiS0_PKfPfiPKiS0_PKfPfi
	.type	_Z48__device_stub__Z18sparseTensorKernelPKiS0_PKfPfiPKiS0_PKfPfi, @function
_Z48__device_stub__Z18sparseTensorKernelPKiS0_PKfPfiPKiS0_PKfPfi:
.LFB4023:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z18sparseTensorKernelPKiS0_PKfPfi(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4023:
	.size	_Z48__device_stub__Z18sparseTensorKernelPKiS0_PKfPfiPKiS0_PKfPfi, .-_Z48__device_stub__Z18sparseTensorKernelPKiS0_PKfPfiPKiS0_PKfPfi
	.globl	_Z18sparseTensorKernelPKiS0_PKfPfi
	.type	_Z18sparseTensorKernelPKiS0_PKfPfi, @function
_Z18sparseTensorKernelPKiS0_PKfPfi:
.LFB4024:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z18sparseTensorKernelPKiS0_PKfPfiPKiS0_PKfPfi
	.cfi_endproc
.LFE4024:
	.size	_Z18sparseTensorKernelPKiS0_PKfPfi, .-_Z18sparseTensorKernelPKiS0_PKfPfi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18sparseTensorKernelPKiS0_PKfPfi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4026:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18sparseTensorKernelPKiS0_PKfPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4026:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIiSaIiEED2Ev
	.type	_ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4339:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L10
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L10:
	ret
	.cfi_endproc
.LFE4339:
	.size	_ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
	.weak	_ZNSt6vectorIiSaIiEED1Ev
	.set	_ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
	.section	.text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEED2Ev
	.type	_ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4351:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L12
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L12:
	ret
	.cfi_endproc
.LFE4351:
	.size	_ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
	.weak	_ZNSt6vectorIfSaIfEED1Ev
	.set	_ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
	.section	.rodata.str1.1
.LC1:
	.string	"No CUDA-capable devices found."
.LC4:
	.string	"CUDA kernel launch failed: "
.LC5:
	.string	"First 10 results: "
.LC6:
	.string	" "
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB3998:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA3998
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$184, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rdi
.LEHB0:
	call	cudaGetDeviceCount@PLT
	cmpl	$0, 12(%rsp)
	jne	.L15
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	orl	$-1, %ebx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	jmp	.L14
.L15:
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	movl	$16384, %edi
	call	_Znwm@PLT
.LEHE0:
	xorl	%r9d, %r9d
	leaq	16384(%rax), %rdx
	movq	%rax, 72(%rsp)
	movq	%rax, %r13
	movq	%rdx, 88(%rsp)
	movl	%r9d, (%rax)
	xorl	%eax, %eax
.L17:
	addq	$4, %rax
	cmpq	$16384, %rax
	je	.L49
	xorl	%r8d, %r8d
	movl	%r8d, 0(%r13,%rax)
	jmp	.L17
.L49:
	xorl	%edi, %edi
	movq	%rdx, 80(%rsp)
	movq	%rdi, 104(%rsp)
	movq	%rdi, 112(%rsp)
	movl	$16384, %edi
.LEHB1:
	call	_Znwm@PLT
.LEHE1:
	leaq	16384(%rax), %rdx
	xorl	%esi, %esi
	movq	%rax, 96(%rsp)
	movq	%rax, %r12
	movq	%rdx, 112(%rsp)
	movl	%esi, (%rax)
	xorl	%eax, %eax
.L19:
	addq	$4, %rax
	cmpq	$16384, %rax
	je	.L50
	xorl	%ecx, %ecx
	movl	%ecx, (%r12,%rax)
	jmp	.L19
.L50:
	movq	%rdx, 104(%rsp)
	movl	$16384, %edi
	xorl	%edx, %edx
	movq	%rdx, 128(%rsp)
	movq	%rdx, 136(%rsp)
.LEHB2:
	call	_Znwm@PLT
.LEHE2:
	leaq	16384(%rax), %rdx
	movq	%rax, 120(%rsp)
	movq	%rax, %rbp
	movq	%rdx, 136(%rsp)
	movl	$0x00000000, (%rax)
	xorl	%eax, %eax
.L21:
	addq	$4, %rax
	cmpq	$16384, %rax
	je	.L51
	movl	$0x00000000, 0(%rbp,%rax)
	jmp	.L21
.L51:
	xorl	%eax, %eax
	movl	$16384, %edi
	movq	%rdx, 128(%rsp)
	movq	%rax, 152(%rsp)
	movq	%rax, 160(%rsp)
.LEHB3:
	call	_Znwm@PLT
.LEHE3:
	leaq	16384(%rax), %rdx
	movq	%rax, 144(%rsp)
	movq	%rax, %rbx
	xorl	%eax, %eax
	movq	%rdx, 160(%rsp)
.L23:
	movl	$0x00000000, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$16384, %rax
	jne	.L23
	movq	%rdx, 152(%rsp)
	movss	.LC3(%rip), %xmm0
	xorl	%eax, %eax
.L24:
	leal	(%rax,%rax), %edx
	movl	%eax, 0(%r13,%rax,4)
	andl	$4095, %edx
	movss	%xmm0, 0(%rbp,%rax,4)
	movl	%edx, (%r12,%rax,4)
	incq	%rax
	cmpq	$4096, %rax
	jne	.L24
	leaq	16(%rsp), %rdi
	movl	$16384, %esi
.LEHB4:
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$16384, %edx
	movq	%r13, %rsi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$16384, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$16384, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movl	$16384, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movl	$16777217, %edx
	movl	$268435457, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	movl	$1, %ecx
	salq	$4, %rdi
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L25
.L27:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L28
	jmp	.L52
.L25:
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	$4096, %r8d
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z48__device_stub__Z18sparseTensorKernelPKiS0_PKfPfiPKiS0_PKfPfi
	jmp	.L27
.L52:
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rax, %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %ebx
	jmp	.L29
.L28:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$16384, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	_ZSt4cout(%rip), %r12
	leaq	.LC5(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	xorl	%ebp, %ebp
	leaq	.LC6(%rip), %r13
.L30:
	movq	%r12, %rdi
	cvtss2sd	(%rbx,%rbp,4), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	movq	%r13, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	incq	%rbp
	cmpq	$10, %rbp
	jne	.L30
	movq	%r12, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE4:
	xorl	%ebx, %ebx
.L29:
	leaq	144(%rsp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	leaq	120(%rsp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	leaq	96(%rsp), %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	leaq	72(%rsp), %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	jmp	.L14
.L41:
	endbr64
	movq	%rax, %rbx
.L31:
	leaq	144(%rsp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L32
.L40:
	endbr64
	movq	%rax, %rbx
.L32:
	leaq	120(%rsp), %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L33
.L39:
	endbr64
	movq	%rax, %rbx
.L33:
	leaq	96(%rsp), %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	jmp	.L34
.L38:
	endbr64
	movq	%rax, %rbx
.L34:
	leaq	72(%rsp), %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L48
	movq	%rbx, %rdi
.LEHB5:
	call	_Unwind_Resume@PLT
.LEHE5:
.L14:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
.L48:
	call	__stack_chk_fail@PLT
.L36:
	addq	$184, %rsp
	.cfi_def_cfa_offset 40
	movl	%ebx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3998:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA3998:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE3998-.LLSDACSB3998
.LLSDACSB3998:
	.uleb128 .LEHB0-.LFB3998
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB3998
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L38-.LFB3998
	.uleb128 0
	.uleb128 .LEHB2-.LFB3998
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L39-.LFB3998
	.uleb128 0
	.uleb128 .LEHB3-.LFB3998
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L40-.LFB3998
	.uleb128 0
	.uleb128 .LEHB4-.LFB3998
	.uleb128 .LEHE4-.LEHB4
	.uleb128 .L41-.LFB3998
	.uleb128 0
	.uleb128 .LEHB5-.LFB3998
	.uleb128 .LEHE5-.LEHB5
	.uleb128 0
	.uleb128 0
.LLSDACSE3998:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1065353216
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <vector>

// Define the size of the sparse tensor
#define NUM_NON_ZERO 4096

// Kernel to perform sparse tensor operations
__global__ void sparseTensorKernel(const int* row_indices, const int* col_indices, const float* values, float* result, int num_non_zero) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < num_non_zero) {
        atomicAdd(&result[row_indices[idx]], values[idx] * values[col_indices[idx]]);
    }
}

int main() {
    // Initialize device
    int deviceCount;
    hipGetDeviceCount(&deviceCount);
    if (deviceCount == 0) {
        std::cerr << "No CUDA-capable devices found." << std::endl;
        return -1;
    }
    hipSetDevice(0); // Use the first GPU

    // Host data
    std::vector<int> h_row_indices(NUM_NON_ZERO);
    std::vector<int> h_col_indices(NUM_NON_ZERO);
    std::vector<float> h_values(NUM_NON_ZERO);
    std::vector<float> h_result(4096, 0.0f); // Assuming a square matrix of size 4096

    // Fill with dummy data for demonstration
    for (int i = 0; i < NUM_NON_ZERO; ++i) {
        h_row_indices[i] = i % 4096;
        h_col_indices[i] = (i * 2) % 4096;
        h_values[i] = 1.0f;
    }

    // Device data
    int* d_row_indices;
    int* d_col_indices;
    float* d_values;
    float* d_result;

    // Allocate device memory
    hipMalloc((void**)&d_row_indices, NUM_NON_ZERO * sizeof(int));
    hipMalloc((void**)&d_col_indices, NUM_NON_ZERO * sizeof(int));
    hipMalloc((void**)&d_values, NUM_NON_ZERO * sizeof(float));
    hipMalloc((void**)&d_result, 4096 * sizeof(float));

    // Copy data from host to device
    hipMemcpy(d_row_indices, h_row_indices.data(), NUM_NON_ZERO * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_col_indices, h_col_indices.data(), NUM_NON_ZERO * sizeof(int), hipMemcpyHostToDevice);
    hipMemcpy(d_values, h_values.data(), NUM_NON_ZERO * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_result, h_result.data(), 4096 * sizeof(float), hipMemcpyHostToDevice);

    // Define block and grid sizes
    dim3 blockSize(256);
    dim3 gridSize((NUM_NON_ZERO + blockSize.x - 1) / blockSize.x);

    // Launch kernel
    sparseTensorKernel<<<gridSize, blockSize>>>(d_row_indices, d_col_indices, d_values, d_result, NUM_NON_ZERO);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA kernel launch failed: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy result back to host
    hipMemcpy(h_result.data(), d_result, 4096 * sizeof(float), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_row_indices);
    hipFree(d_col_indices);
    hipFree(d_values);
    hipFree(d_result);

    // Output result for verification
    std::cout << "First 10 results: ";
    for (int i = 0; i < 10; ++i) {
        std::cout << h_result[i] << " ";
    }
    std::cout << std::endl;

    return 0;
}
	.text
	.file	"cuda_code_074178.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi # -- Begin function _Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi
	.type	_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi,@function
_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi: # @_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18sparseTensorKernelPKiS0_PKfPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi, .Lfunc_end0-_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$0, (%rbx)
	je	.LBB1_1
# %bb.2:
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znwm
	movq	%rax, %rbx
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp0:
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znwm
.Ltmp1:
# %bb.3:
	movq	%rax, %r14
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp3:
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znwm
.Ltmp4:
# %bb.4:
	movq	%rax, %r15
	xorl	%r13d, %r13d
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp6:
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znwm
.Ltmp7:
# %bb.5:                                # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader
	movq	%rax, %r12
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	xorl	%eax, %eax
.LBB1_6:                                # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rbx,%rax,4)
	movl	%r13d, %ecx
	andl	$4094, %ecx                     # imm = 0xFFE
	movl	%ecx, (%r14,%rax,4)
	movl	$1065353216, (%r15,%rax,4)      # imm = 0x3F800000
	incq	%rax
	addl	$2, %r13d
	cmpq	$4096, %rax                     # imm = 0x1000
	jne	.LBB1_6
# %bb.7:
.Ltmp9:
	leaq	24(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
.Ltmp10:
# %bb.8:
.Ltmp11:
	leaq	16(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
.Ltmp12:
# %bb.9:
.Ltmp13:
	leaq	8(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
.Ltmp14:
# %bb.10:
.Ltmp15:
	movq	%rsp, %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
.Ltmp16:
# %bb.11:
	movq	24(%rsp), %rdi
.Ltmp17:
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp18:
# %bb.12:
	movq	16(%rsp), %rdi
.Ltmp19:
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp20:
# %bb.13:
	movq	8(%rsp), %rdi
.Ltmp21:
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp22:
# %bb.14:
	movq	(%rsp), %rdi
.Ltmp23:
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp24:
# %bb.15:
.Ltmp26:
	movabsq	$4294967312, %rdi               # imm = 0x100000010
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp27:
# %bb.16:
	testl	%eax, %eax
	jne	.LBB1_18
# %bb.17:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
.Ltmp28:
	movl	$4096, %r8d                     # imm = 0x1000
	callq	_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi
.Ltmp29:
.LBB1_18:
.Ltmp31:
	callq	hipGetLastError
.Ltmp32:
# %bb.19:
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.LBB1_32
# %bb.20:
.Ltmp33:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$27, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp34:
# %bb.21:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp35:
	movl	%ebp, %edi
	callq	hipGetErrorString
.Ltmp36:
# %bb.22:
	movq	%rax, %r13
	testq	%rax, %rax
	je	.LBB1_23
# %bb.27:
	movq	%r13, %rdi
	callq	strlen
.Ltmp37:
	movl	$_ZSt4cerr, %edi
	movq	%r13, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
	jmp	.LBB1_28
.LBB1_1:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %ebp
	jmp	.LBB1_46
.LBB1_32:
	movq	(%rsp), %rsi
.Ltmp47:
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp48:
# %bb.33:
	movq	24(%rsp), %rdi
.Ltmp49:
	callq	hipFree
.Ltmp50:
# %bb.34:
	movq	16(%rsp), %rdi
.Ltmp51:
	callq	hipFree
.Ltmp52:
# %bb.35:
	movq	8(%rsp), %rdi
.Ltmp53:
	callq	hipFree
.Ltmp54:
# %bb.36:
	movq	(%rsp), %rdi
.Ltmp55:
	callq	hipFree
.Ltmp56:
# %bb.37:
.Ltmp57:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$18, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp58:
# %bb.38:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit47.preheader.preheader
	xorl	%r13d, %r13d
.LBB1_39:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit47.preheader
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12,%r13,4), %xmm0
.Ltmp59:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp60:
# %bb.40:                               # %_ZNSolsEf.exit
                                        #   in Loop: Header=BB1_39 Depth=1
.Ltmp61:
	movl	$.L.str.3, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp62:
# %bb.41:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit52
                                        #   in Loop: Header=BB1_39 Depth=1
	incq	%r13
	cmpq	$10, %r13
	jne	.LBB1_39
# %bb.42:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %edi
	addq	-24(%rax), %rdi
.Ltmp64:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp65:
# %bb.43:                               # %.noexc75
.Ltmp66:
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
.Ltmp67:
# %bb.44:                               # %.noexc76
	xorl	%ebp, %ebp
.Ltmp68:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp69:
	jmp	.LBB1_45
.LBB1_23:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
.Ltmp39:
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp40:
.LBB1_28:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %edi
	addq	-24(%rax), %rdi
.Ltmp41:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp42:
# %bb.29:                               # %.noexc72
.Ltmp43:
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
.Ltmp44:
# %bb.30:                               # %.noexc73
	movl	$-1, %ebp
.Ltmp45:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp46:
.LBB1_45:                               # %_ZNSt6vectorIiSaIiEED2Ev.exit57
	movq	%r12, %rdi
	callq	_ZdlPv
	movq	%r15, %rdi
	callq	_ZdlPv
	movq	%r14, %rdi
	callq	_ZdlPv
	movq	%rbx, %rdi
	callq	_ZdlPv
.LBB1_46:
	movl	%ebp, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_26:
	.cfi_def_cfa_offset 96
.Ltmp8:
	movq	%rax, %r13
	jmp	.LBB1_49
.LBB1_25:
.Ltmp5:
	movq	%rax, %r13
	jmp	.LBB1_50
.LBB1_24:
.Ltmp2:
	movq	%rax, %r13
	jmp	.LBB1_51
.LBB1_52:
.Ltmp30:
	jmp	.LBB1_48
.LBB1_47:
.Ltmp25:
	jmp	.LBB1_48
.LBB1_31:
.Ltmp70:
	jmp	.LBB1_48
.LBB1_53:
.Ltmp63:
.LBB1_48:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit59
	movq	%rax, %r13
	movq	%r12, %rdi
	callq	_ZdlPv
.LBB1_49:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit61
	movq	%r15, %rdi
	callq	_ZdlPv
.LBB1_50:                               # %_ZNSt6vectorIiSaIiEED2Ev.exit63
	movq	%r14, %rdi
	callq	_ZdlPv
.LBB1_51:                               # %_ZNSt6vectorIiSaIiEED2Ev.exit65
	movq	%rbx, %rdi
	callq	_ZdlPv
	movq	%r13, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table1:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp1-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp3-.Ltmp1                  #   Call between .Ltmp1 and .Ltmp3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp4-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Ltmp6-.Ltmp4                  #   Call between .Ltmp4 and .Ltmp6
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 6 <<
	.uleb128 .Ltmp7-.Ltmp6                  #   Call between .Ltmp6 and .Ltmp7
	.uleb128 .Ltmp8-.Lfunc_begin0           #     jumps to .Ltmp8
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp7-.Lfunc_begin0           # >> Call Site 7 <<
	.uleb128 .Ltmp9-.Ltmp7                  #   Call between .Ltmp7 and .Ltmp9
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp9-.Lfunc_begin0           # >> Call Site 8 <<
	.uleb128 .Ltmp24-.Ltmp9                 #   Call between .Ltmp9 and .Ltmp24
	.uleb128 .Ltmp25-.Lfunc_begin0          #     jumps to .Ltmp25
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp26-.Lfunc_begin0          # >> Call Site 9 <<
	.uleb128 .Ltmp29-.Ltmp26                #   Call between .Ltmp26 and .Ltmp29
	.uleb128 .Ltmp30-.Lfunc_begin0          #     jumps to .Ltmp30
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp31-.Lfunc_begin0          # >> Call Site 10 <<
	.uleb128 .Ltmp38-.Ltmp31                #   Call between .Ltmp31 and .Ltmp38
	.uleb128 .Ltmp70-.Lfunc_begin0          #     jumps to .Ltmp70
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp38-.Lfunc_begin0          # >> Call Site 11 <<
	.uleb128 .Ltmp47-.Ltmp38                #   Call between .Ltmp38 and .Ltmp47
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp47-.Lfunc_begin0          # >> Call Site 12 <<
	.uleb128 .Ltmp58-.Ltmp47                #   Call between .Ltmp47 and .Ltmp58
	.uleb128 .Ltmp70-.Lfunc_begin0          #     jumps to .Ltmp70
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp59-.Lfunc_begin0          # >> Call Site 13 <<
	.uleb128 .Ltmp62-.Ltmp59                #   Call between .Ltmp59 and .Ltmp62
	.uleb128 .Ltmp63-.Lfunc_begin0          #     jumps to .Ltmp63
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp64-.Lfunc_begin0          # >> Call Site 14 <<
	.uleb128 .Ltmp46-.Ltmp64                #   Call between .Ltmp64 and .Ltmp46
	.uleb128 .Ltmp70-.Lfunc_begin0          #     jumps to .Ltmp70
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp46-.Lfunc_begin0          # >> Call Site 15 <<
	.uleb128 .Lfunc_end1-.Ltmp46            #   Call between .Ltmp46 and .Lfunc_end1
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18sparseTensorKernelPKiS0_PKfPfi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18sparseTensorKernelPKiS0_PKfPfi,@object # @_Z18sparseTensorKernelPKiS0_PKfPfi
	.section	.rodata,"a",@progbits
	.globl	_Z18sparseTensorKernelPKiS0_PKfPfi
	.p2align	3, 0x0
_Z18sparseTensorKernelPKiS0_PKfPfi:
	.quad	_Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi
	.size	_Z18sparseTensorKernelPKiS0_PKfPfi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"No CUDA-capable devices found."
	.size	.L.str, 31

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CUDA kernel launch failed: "
	.size	.L.str.1, 28

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"First 10 results: "
	.size	.L.str.2, 19

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" "
	.size	.L.str.3, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18sparseTensorKernelPKiS0_PKfPfi"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__sparseTensorKernelPKiS0_PKfPfi
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z18sparseTensorKernelPKiS0_PKfPfi
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18sparseTensorKernelPKiS0_PKfPfi ; -- Begin function _Z18sparseTensorKernelPKiS0_PKfPfi
	.globl	_Z18sparseTensorKernelPKiS0_PKfPfi
	.p2align	8
	.type	_Z18sparseTensorKernelPKiS0_PKfPfi,@function
_Z18sparseTensorKernelPKiS0_PKfPfi:     ; @_Z18sparseTensorKernelPKiS0_PKfPfi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s3, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v4, v[4:5], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[6:7], off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v4, v4, v2
.LBB0_2:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_2
.LBB0_3:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18sparseTensorKernelPKiS0_PKfPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18sparseTensorKernelPKiS0_PKfPfi, .Lfunc_end0-_Z18sparseTensorKernelPKiS0_PKfPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18sparseTensorKernelPKiS0_PKfPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18sparseTensorKernelPKiS0_PKfPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
