#include <iostream>
#include <cuda_runtime.h>
#include <vector>

#define WIDTH 1024
#define HEIGHT 1024
#define THRESHOLD 20
#define MAX_ITERATIONS 10

__device__ int getLinearIndex(int x, int y) {
    return y * WIDTH + x;
}

__device__ bool isValidPixel(int x, int y) {
    return x >= 0 && x < WIDTH && y >= 0 && y < HEIGHT;
}

__device__ int getPixelValue(unsigned char* image, int x, int y) {
    return image[getLinearIndex(x, y)];
}

__global__ void regionGrowingKernel(unsigned char* image, unsigned char* output, int seedX, int seedY, int* queue, int* queueTail) {
    extern __shared__ int sharedQueue[];

    int tid = threadIdx.x;
    int queueHead = 0;

    // Load initial seed into shared memory
    if (tid == 0) {
        sharedQueue[0] = getLinearIndex(seedX, seedY);
        atomicExch(queueTail, 1);
    }
    __syncthreads();

    while (queueHead < *queueTail) {
        int pixelIndex = sharedQueue[queueHead++];
        int x = pixelIndex % WIDTH;
        int y = pixelIndex / WIDTH;

        // Only the first thread in the warp processes the pixel
        if (tid % warpSize == 0) {
            if (output[pixelIndex] == 0) {
                int seedValue = getPixelValue(image, seedX, seedY);
                int pixelValue = getPixelValue(image, x, y);

                if (abs(seedValue - pixelValue) <= THRESHOLD) {
                    output[pixelIndex] = 255;

                    // Add neighbors to the queue
                    int neighbors[4][2] = {{x - 1, y}, {x + 1, y}, {x, y - 1}, {x, y + 1}};
                    for (int i = 0; i < 4; ++i) {
                        int nx = neighbors[i][0];
                        int ny = neighbors[i][1];
                        if (isValidPixel(nx, ny) && output[getLinearIndex(nx, ny)] == 0) {
                            int newTail = atomicAdd(queueTail, 1);
                            if (newTail < WIDTH * HEIGHT) {
                                queue[newTail] = getLinearIndex(nx, ny);
                            }
                        }
                    }
                }
            }
        }
        __syncthreads();

        // Warp divergence handled by ensuring only valid threads write to shared memory
        if (tid < *queueTail - queueHead) {
            sharedQueue[tid] = queue[queueHead + tid];
        }
        __syncthreads();
    }
}

int main() {
    unsigned char* h_image = new unsigned char[WIDTH * HEIGHT];
    unsigned char* h_output = new unsigned char[WIDTH * HEIGHT];
    unsigned char* d_image;
    unsigned char* d_output;
    int* d_queue;
    int* d_queueTail;
    int* h_queue = new int[WIDTH * HEIGHT];
    int h_queueTail = 0;

    // Initialize image and output
    for (int i = 0; i < WIDTH * HEIGHT; ++i) {
        h_image[i] = rand() % 256;
        h_output[i] = 0;
    }

    // Allocate device memory
    cudaError_t err = cudaMalloc(&d_image, WIDTH * HEIGHT * sizeof(unsigned char));
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate d_image (error code " << err << ")" << std::endl;
        return -1;
    }

    err = cudaMalloc(&d_output, WIDTH * HEIGHT * sizeof(unsigned char));
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate d_output (error code " << err << ")" << std::endl;
        return -1;
    }

    err = cudaMalloc(&d_queue, WIDTH * HEIGHT * sizeof(int));
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate d_queue (error code " << err << ")" << std::endl;
        return -1;
    }

    err = cudaMalloc(&d_queueTail, sizeof(int));
    if (err != cudaSuccess) {
        std::cerr << "Failed to allocate d_queueTail (error code " << err << ")" << std::endl;
        return -1;
    }

    // Copy data to device
    err = cudaMemcpy(d_image, h_image, WIDTH * HEIGHT * sizeof(unsigned char), cudaMemcpyHostToDevice);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy h_image to d_image (error code " << err << ")" << std::endl;
        return -1;
    }

    err = cudaMemcpy(d_queue, h_queue, WIDTH * HEIGHT * sizeof(int), cudaMemcpyHostToDevice);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy h_queue to d_queue (error code " << err << ")" << std::endl;
        return -1;
    }

    err = cudaMemcpy(d_queueTail, &h_queueTail, sizeof(int), cudaMemcpyHostToDevice);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy h_queueTail to d_queueTail (error code " << err << ")" << std::endl;
        return -1;
    }

    // Launch kernel
    int blockSize = 256;
    int sharedMemSize = blockSize * sizeof(int);
    regionGrowingKernel<<<1, blockSize, sharedMemSize>>>(d_image, d_output, WIDTH / 2, HEIGHT / 2, d_queue, d_queueTail);

    // Check for errors in kernel launch
    err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "Failed to launch regionGrowingKernel (error code " << err << ")" << std::endl;
        return -1;
    }

    // Copy result back to host
    err = cudaMemcpy(h_output, d_output, WIDTH * HEIGHT * sizeof(unsigned char), cudaMemcpyDeviceToHost);
    if (err != cudaSuccess) {
        std::cerr << "Failed to copy d_output to h_output (error code " << err << ")" << std::endl;
        return -1;
    }

    // Free device memory
    cudaFree(d_image);
    cudaFree(d_output);
    cudaFree(d_queue);
    cudaFree(d_queueTail);

    // Clean up
    delete[] h_image;
    delete[] h_output;
    delete[] h_queue;

    return 0;
}
	.file	"tmpxft_001b05ef_00000000-6_cuda_code_016301.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4004:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4004:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4660:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4660:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z14getLinearIndexii
	.type	_Z14getLinearIndexii, @function
_Z14getLinearIndexii:
.LFB3998:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3998:
	.size	_Z14getLinearIndexii, .-_Z14getLinearIndexii
	.globl	_Z12isValidPixelii
	.type	_Z12isValidPixelii, @function
_Z12isValidPixelii:
.LFB3999:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3999:
	.size	_Z12isValidPixelii, .-_Z12isValidPixelii
	.globl	_Z13getPixelValuePhii
	.type	_Z13getPixelValuePhii, @function
_Z13getPixelValuePhii:
.LFB4000:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4000:
	.size	_Z13getPixelValuePhii, .-_Z13getPixelValuePhii
	.globl	_Z48__device_stub__Z19regionGrowingKernelPhS_iiPiS0_PhS_iiPiS0_
	.type	_Z48__device_stub__Z19regionGrowingKernelPhS_iiPiS0_PhS_iiPiS0_, @function
_Z48__device_stub__Z19regionGrowingKernelPhS_iiPiS0_PhS_iiPiS0_:
.LFB4026:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z19regionGrowingKernelPhS_iiPiS0_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L9:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4026:
	.size	_Z48__device_stub__Z19regionGrowingKernelPhS_iiPiS0_PhS_iiPiS0_, .-_Z48__device_stub__Z19regionGrowingKernelPhS_iiPiS0_PhS_iiPiS0_
	.globl	_Z19regionGrowingKernelPhS_iiPiS0_
	.type	_Z19regionGrowingKernelPhS_iiPiS0_, @function
_Z19regionGrowingKernelPhS_iiPiS0_:
.LFB4027:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z19regionGrowingKernelPhS_iiPiS0_PhS_iiPiS0_
	.cfi_endproc
.LFE4027:
	.size	_Z19regionGrowingKernelPhS_iiPiS0_, .-_Z19regionGrowingKernelPhS_iiPiS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Failed to allocate d_image (error code "
.LC1:
	.string	")"
.LC2:
	.string	"Failed to allocate d_output (error code "
.LC3:
	.string	"Failed to allocate d_queue (error code "
.LC4:
	.string	"Failed to allocate d_queueTail (error code "
.LC5:
	.string	"Failed to copy h_image to d_image (error code "
.LC6:
	.string	"Failed to copy h_queue to d_queue (error code "
.LC7:
	.string	"Failed to copy h_queueTail to d_queueTail (error code "
.LC8:
	.string	"Failed to launch regionGrowingKernel (error code "
.LC9:
	.string	"Failed to copy d_output to h_output (error code "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4001:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$1048576, %edi
	movl	$256, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$1048576, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$4194304, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movq	%rax, %r13
	xorl	%eax, %eax
	movl	%eax, 12(%rsp)
.L16:
	call	rand@PLT
	movb	$0, (%rbx,%r12)
	cltd
	idivl	%r14d
	movb	%dl, 0(%rbp,%r12)
	incq	%r12
	cmpq	$1048576, %r12
	jne	.L16
	movl	$1048576, %esi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC0(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	movl	%eax, %r12d
	testl	%eax, %eax
	je	.L19
	leaq	.LC2(%rip), %rsi
.L32:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	orl	$-1, %eax
	jmp	.L15
.L19:
	movl	$4194304, %esi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC3(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	movl	$4, %esi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	movq	16(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	movq	32(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	leaq	.LC6(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	movq	40(%rsp), %rdi
	leaq	12(%rsp), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	leaq	.LC7(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	movl	$1024, %r8d
	movl	$1, %ecx
	salq	$8, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	40(%rsp), %r9
	movq	32(%rsp), %r8
	movl	$512, %ecx
	movl	$512, %edx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z48__device_stub__Z19regionGrowingKernelPhS_iiPiS0_PhS_iiPiS0_
.L26:
	call	cudaGetLastError@PLT
	leaq	.LC8(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$1048576, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC9(%rip), %rsi
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	.L32
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L15:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4001:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z19regionGrowingKernelPhS_iiPiS0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19regionGrowingKernelPhS_iiPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4029:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <vector>

#define WIDTH 1024
#define HEIGHT 1024
#define THRESHOLD 20
#define MAX_ITERATIONS 10

__device__ int getLinearIndex(int x, int y) {
    return y * WIDTH + x;
}

__device__ bool isValidPixel(int x, int y) {
    return x >= 0 && x < WIDTH && y >= 0 && y < HEIGHT;
}

__device__ int getPixelValue(unsigned char* image, int x, int y) {
    return image[getLinearIndex(x, y)];
}

__global__ void regionGrowingKernel(unsigned char* image, unsigned char* output, int seedX, int seedY, int* queue, int* queueTail) {
    extern __shared__ int sharedQueue[];

    int tid = threadIdx.x;
    int queueHead = 0;

    // Load initial seed into shared memory
    if (tid == 0) {
        sharedQueue[0] = getLinearIndex(seedX, seedY);
        atomicExch(queueTail, 1);
    }
    __syncthreads();

    while (queueHead < *queueTail) {
        int pixelIndex = sharedQueue[queueHead++];
        int x = pixelIndex % WIDTH;
        int y = pixelIndex / WIDTH;

        // Only the first thread in the warp processes the pixel
        if (tid % warpSize == 0) {
            if (output[pixelIndex] == 0) {
                int seedValue = getPixelValue(image, seedX, seedY);
                int pixelValue = getPixelValue(image, x, y);

                if (abs(seedValue - pixelValue) <= THRESHOLD) {
                    output[pixelIndex] = 255;

                    // Add neighbors to the queue
                    int neighbors[4][2] = {{x - 1, y}, {x + 1, y}, {x, y - 1}, {x, y + 1}};
                    for (int i = 0; i < 4; ++i) {
                        int nx = neighbors[i][0];
                        int ny = neighbors[i][1];
                        if (isValidPixel(nx, ny) && output[getLinearIndex(nx, ny)] == 0) {
                            int newTail = atomicAdd(queueTail, 1);
                            if (newTail < WIDTH * HEIGHT) {
                                queue[newTail] = getLinearIndex(nx, ny);
                            }
                        }
                    }
                }
            }
        }
        __syncthreads();

        // Warp divergence handled by ensuring only valid threads write to shared memory
        if (tid < *queueTail - queueHead) {
            sharedQueue[tid] = queue[queueHead + tid];
        }
        __syncthreads();
    }
}

int main() {
    unsigned char* h_image = new unsigned char[WIDTH * HEIGHT];
    unsigned char* h_output = new unsigned char[WIDTH * HEIGHT];
    unsigned char* d_image;
    unsigned char* d_output;
    int* d_queue;
    int* d_queueTail;
    int* h_queue = new int[WIDTH * HEIGHT];
    int h_queueTail = 0;

    // Initialize image and output
    for (int i = 0; i < WIDTH * HEIGHT; ++i) {
        h_image[i] = rand() % 256;
        h_output[i] = 0;
    }

    // Allocate device memory
    hipError_t err = hipMalloc(&d_image, WIDTH * HEIGHT * sizeof(unsigned char));
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate d_image (error code " << err << ")" << std::endl;
        return -1;
    }

    err = hipMalloc(&d_output, WIDTH * HEIGHT * sizeof(unsigned char));
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate d_output (error code " << err << ")" << std::endl;
        return -1;
    }

    err = hipMalloc(&d_queue, WIDTH * HEIGHT * sizeof(int));
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate d_queue (error code " << err << ")" << std::endl;
        return -1;
    }

    err = hipMalloc(&d_queueTail, sizeof(int));
    if (err != hipSuccess) {
        std::cerr << "Failed to allocate d_queueTail (error code " << err << ")" << std::endl;
        return -1;
    }

    // Copy data to device
    err = hipMemcpy(d_image, h_image, WIDTH * HEIGHT * sizeof(unsigned char), hipMemcpyHostToDevice);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy h_image to d_image (error code " << err << ")" << std::endl;
        return -1;
    }

    err = hipMemcpy(d_queue, h_queue, WIDTH * HEIGHT * sizeof(int), hipMemcpyHostToDevice);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy h_queue to d_queue (error code " << err << ")" << std::endl;
        return -1;
    }

    err = hipMemcpy(d_queueTail, &h_queueTail, sizeof(int), hipMemcpyHostToDevice);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy h_queueTail to d_queueTail (error code " << err << ")" << std::endl;
        return -1;
    }

    // Launch kernel
    int blockSize = 256;
    int sharedMemSize = blockSize * sizeof(int);
    regionGrowingKernel<<<1, blockSize, sharedMemSize>>>(d_image, d_output, WIDTH / 2, HEIGHT / 2, d_queue, d_queueTail);

    // Check for errors in kernel launch
    err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "Failed to launch regionGrowingKernel (error code " << err << ")" << std::endl;
        return -1;
    }

    // Copy result back to host
    err = hipMemcpy(h_output, d_output, WIDTH * HEIGHT * sizeof(unsigned char), hipMemcpyDeviceToHost);
    if (err != hipSuccess) {
        std::cerr << "Failed to copy d_output to h_output (error code " << err << ")" << std::endl;
        return -1;
    }

    // Free device memory
    hipFree(d_image);
    hipFree(d_output);
    hipFree(d_queue);
    hipFree(d_queueTail);

    // Clean up
    delete[] h_image;
    delete[] h_output;
    delete[] h_queue;

    return 0;
}
	.text
	.file	"cuda_code_016301.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_ # -- Begin function _Z34__device_stub__regionGrowingKernelPhS_iiPiS0_
	.type	_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_,@function
_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_: # @_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19regionGrowingKernelPhS_iiPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_, .Lfunc_end0-_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1048576, %edi                  # imm = 0x100000
	callq	_Znam
	movq	%rax, %rbx
	movl	$1048576, %edi                  # imm = 0x100000
	callq	_Znam
	movq	%rax, %r14
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %r15
	movl	$0, 44(%rsp)
	xorl	%r12d, %r12d
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	movb	%al, (%rbx,%r12)
	movb	$0, (%r14,%r12)
	incq	%r12
	cmpq	$1048576, %r12                  # imm = 0x100000
	jne	.LBB1_1
# %bb.2:
	leaq	32(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_5
# %bb.3:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
.LBB1_4:
	movl	$39, %edx
	jmp	.LBB1_7
.LBB1_5:
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_10
# %bb.6:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.2, %esi
	movl	$40, %edx
.LBB1_7:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_8:
	movl	$-1, %eax
.LBB1_9:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_10:
	.cfi_def_cfa_offset 96
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_12
# %bb.11:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	jmp	.LBB1_4
.LBB1_12:
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_14
# %bb.13:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.4, %esi
	movl	$43, %edx
	jmp	.LBB1_7
.LBB1_14:
	movq	32(%rsp), %rdi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_16
# %bb.15:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.5, %esi
	jmp	.LBB1_18
.LBB1_16:
	movq	16(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_20
# %bb.17:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.6, %esi
.LBB1_18:
	movl	$46, %edx
.LBB1_19:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB1_8
.LBB1_20:
	movq	8(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_22
# %bb.21:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	movl	$54, %edx
	jmp	.LBB1_19
.LBB1_22:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	255(%rdi), %rdx
	movl	$1024, %r8d                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_24
# %bb.23:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movl	$512, %edx                      # imm = 0x200
	movl	$512, %ecx                      # imm = 0x200
	callq	_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_
.LBB1_24:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_26
# %bb.25:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.8, %esi
	movl	$49, %edx
	jmp	.LBB1_19
.LBB1_26:
	movq	24(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_28
# %bb.27:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.9, %esi
	movl	$48, %edx
	jmp	.LBB1_19
.LBB1_28:
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_9
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19regionGrowingKernelPhS_iiPiS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19regionGrowingKernelPhS_iiPiS0_,@object # @_Z19regionGrowingKernelPhS_iiPiS0_
	.section	.rodata,"a",@progbits
	.globl	_Z19regionGrowingKernelPhS_iiPiS0_
	.p2align	3, 0x0
_Z19regionGrowingKernelPhS_iiPiS0_:
	.quad	_Z34__device_stub__regionGrowingKernelPhS_iiPiS0_
	.size	_Z19regionGrowingKernelPhS_iiPiS0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Failed to allocate d_image (error code "
	.size	.L.str, 40

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	")"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate d_output (error code "
	.size	.L.str.2, 41

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate d_queue (error code "
	.size	.L.str.3, 40

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate d_queueTail (error code "
	.size	.L.str.4, 44

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to copy h_image to d_image (error code "
	.size	.L.str.5, 47

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to copy h_queue to d_queue (error code "
	.size	.L.str.6, 47

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to copy h_queueTail to d_queueTail (error code "
	.size	.L.str.7, 55

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to launch regionGrowingKernel (error code "
	.size	.L.str.8, 50

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to copy d_output to h_output (error code "
	.size	.L.str.9, 49

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19regionGrowingKernelPhS_iiPiS0_"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__regionGrowingKernelPhS_iiPiS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19regionGrowingKernelPhS_iiPiS0_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19regionGrowingKernelPhS_iiPiS0_ ; -- Begin function _Z19regionGrowingKernelPhS_iiPiS0_
	.globl	_Z19regionGrowingKernelPhS_iiPiS0_
	.p2align	8
	.type	_Z19regionGrowingKernelPhS_iiPiS0_,@function
_Z19regionGrowingKernelPhS_iiPiS0_:     ; @_Z19regionGrowingKernelPhS_iiPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x18
	s_mov_b32 s8, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s9, s3, 10
	v_mov_b32_e32 v3, 1
	s_add_i32 s9, s9, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s9
	ds_store_b32 v1, v2
	global_atomic_swap_b32 v1, v3, s[6:7]
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v1, v3, s[6:7]
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 1, v1
	s_cbranch_vccnz .LBB0_18
; %bb.3:                                ; %.lr.ph
	s_load_b128 s[8:11], s[0:1], 0x0
	v_and_b32_e32 v1, 31, v0
	s_lshl_b32 s0, s3, 10
	v_lshl_add_u32 v4, v0, 2, 0
	s_add_i32 s1, s0, s2
	v_mov_b32_e32 v5, 0xff
	s_ashr_i32 s3, s1, 31
	v_cmp_eq_u32_e64 s0, 0, v1
	s_mov_b32 s13, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s8, s1
	s_addc_u32 s3, s9, s3
	s_add_u32 s1, s4, 4
	s_addc_u32 s12, s5, 0
.LBB0_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_15
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	s_lshl_b32 s15, s13, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s15, s15, 0
	v_mov_b32_e32 v1, s15
	ds_load_b32 v6, v1
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v6
	v_add_co_u32 v1, vcc_lo, s10, v6
	v_readfirstlane_b32 s15, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	global_load_u8 v7, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v7
	s_cbranch_vccnz .LBB0_15
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_ashr_i32 s16, s15, 31
	s_add_u32 s18, s8, s15
	s_addc_u32 s19, s9, s16
	s_clause 0x1
	global_load_u8 v6, v3, s[2:3]
	global_load_u8 v7, v3, s[18:19]
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, 0, v6
	v_max_i32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 20, v6
	s_cbranch_vccnz .LBB0_15
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	s_lshr_b32 s16, s16, 22
	global_store_b8 v[1:2], v5, off
	s_add_i32 s16, s15, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s17, s16, 0xfffffc00
	s_ashr_i32 s16, s16, 10
	s_sub_i32 s15, s15, s17
	v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v10, s15
	s_add_i32 s17, s15, -1
	s_add_i32 s18, s15, 1
	v_dual_mov_b32 v6, s17 :: v_dual_mov_b32 v9, s16
	s_add_i32 s15, s16, -1
	s_add_i32 s16, s16, 1
	v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v12, v10
	s_mov_b32 s15, 0
	s_clause 0x1
	scratch_store_b128 off, v[6:9], off offset:16
	scratch_store_b128 off, v[10:13], off offset:32
.LBB0_8:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s16, s15, 16
	scratch_load_b64 v[1:2], off, s16
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(0)
	v_or_b32_e32 v6, v2, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x400, v6
	s_cbranch_execz .LBB0_14
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=2
	v_lshl_add_u32 v6, v2, 10, v1
	global_load_u8 v1, v6, s[10:11]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=2
	s_mov_b32 s18, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v1, s18, 0
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_8 Depth=2
	s_bcnt1_i32_b32 s18, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s18
	global_atomic_add_u32 v2, v3, v2, s[6:7] glc
.LBB0_12:                               ;   in Loop: Header=BB0_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s17, v1
	v_cmp_gt_i32_e32 vcc_lo, 0x100000, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_8 Depth=2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_store_b32 v[1:2], v6, off
.LBB0_14:                               ;   in Loop: Header=BB0_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s15, s15, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s15, 32
	s_cbranch_scc0 .LBB0_8
.LBB0_15:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v1, v3, s[6:7]
	s_add_i32 s14, s13, 1
	s_mov_b32 s15, exec_lo
	s_waitcnt vmcnt(0)
	v_subrev_nc_u32_e32 v1, s14, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v0, v1
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v1, s13, s13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, null, 0, 0, s13
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s1, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1
.LBB0_17:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_b32 v1, v3, s[6:7]
	s_mov_b32 s13, s14
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, s14, v1
	s_cbranch_vccnz .LBB0_4
.LBB0_18:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19regionGrowingKernelPhS_iiPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 48
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19regionGrowingKernelPhS_iiPiS0_, .Lfunc_end0-_Z19regionGrowingKernelPhS_iiPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 836
; NumSgprs: 22
; NumVgprs: 14
; ScratchSize: 48
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19regionGrowingKernelPhS_iiPiS0_
    .private_segment_fixed_size: 48
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z19regionGrowingKernelPhS_iiPiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
