#include <iostream>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

#define CUDA_CHECK(call) \
    { \
        cudaError_t err = call; \
        if (err != cudaSuccess) { \
            std::cerr << "CUDA error in " << __FILE__ << ":" << __LINE__ << ". Error: " << cudaGetErrorString(err) << std::endl; \
            exit(EXIT_FAILURE); \
        } \
    }

// Kernel for backpropagation in a convolutional layer
__global__ void convBackpropKernel(float* d_input, float* d_output, float* d_kernel, float* d_kernel_grad, float* d_output_grad, int input_width, int input_height, int output_width, int output_height, int kernel_size, int num_channels) {
    // Define block size and thread indices
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int bz = blockIdx.z;

    // Calculate the output gradient index
    int out_x = bx * blockDim.x + tx;
    int out_y = by * blockDim.y + ty;
    int channel = bz;

    // Check if the output gradient index is within bounds
    if (out_x >= output_width || out_y >= output_height) return;

    // Shared memory for input and kernel
    extern __shared__ float shared_memory[];
    float* shared_input = shared_memory;
    float* shared_kernel = &shared_memory[num_channels * kernel_size * kernel_size];

    // Load kernel into shared memory
    int kx = tx;
    int ky = ty;
    if (kx < kernel_size && ky < kernel_size) {
        for (int c = 0; c < num_channels; ++c) {
            int kernel_idx = c * kernel_size * kernel_size + ky * kernel_size + kx;
            shared_kernel[kernel_idx] = d_kernel[kernel_idx];
        }
    }
    __syncthreads();

    // Load input into shared memory
    int in_x = out_x;
    int in_y = out_y;
    if (tx < num_channels && ty < input_height) {
        for (int c = 0; c < num_channels; ++c) {
            int input_idx = c * input_height * input_width + ty * input_width + in_x;
            shared_input[ty * input_width + in_x] = d_input[input_idx];
        }
    }
    __syncthreads();

    // Compute the gradient for the kernel
    float grad_sum = 0.0f;
    if (out_x < output_width && out_y < output_height) {
        for (int c = 0; c < num_channels; ++c) {
            for (int ky = 0; ky < kernel_size; ++ky) {
                for (int kx = 0; kx < kernel_size; ++kx) {
                    int in_x = out_x + kx;
                    int in_y = out_y + ky;
                    if (in_x < input_width && in_y < input_height) {
                        int input_idx = c * input_height * input_width + in_y * input_width + in_x;
                        int kernel_idx = c * kernel_size * kernel_size + ky * kernel_size + kx;
                        int output_idx = channel * output_height * output_width + out_y * output_width + out_x;
                        grad_sum += d_input[input_idx] * d_output_grad[output_idx];
                    }
                }
            }
        }
    }
    __syncthreads();

    // Store the kernel gradient
    if (tx < num_channels && ty < kernel_size * kernel_size) {
        int kernel_idx = channel * kernel_size * kernel_size + ty * kernel_size + tx;
        atomicAdd(&d_kernel_grad[kernel_idx], grad_sum);
    }
}

int main() {
    // Problem dimensions
    int input_width = 32, input_height = 32, output_width = 30, output_height = 30, kernel_size = 3, num_channels = 3;

    // Allocate Unified Memory for input, output, kernel, kernel gradient, and output gradient
    float* d_input;
    float* d_output;
    float* d_kernel;
    float* d_kernel_grad;
    float* d_output_grad;
    CUDA_CHECK(cudaMallocManaged(&d_input, num_channels * input_height * input_width * sizeof(float)));
    CUDA_CHECK(cudaMallocManaged(&d_output, num_channels * output_height * output_width * sizeof(float)));
    CUDA_CHECK(cudaMallocManaged(&d_kernel, num_channels * kernel_size * kernel_size * sizeof(float)));
    CUDA_CHECK(cudaMallocManaged(&d_kernel_grad, num_channels * kernel_size * kernel_size * sizeof(float)));
    CUDA_CHECK(cudaMallocManaged(&d_output_grad, num_channels * output_height * output_width * sizeof(float)));

    // Initialize data
    for (int i = 0; i < num_channels * input_height * input_width; ++i) d_input[i] = 1.0f;
    for (int i = 0; i < num_channels * output_height * output_width; ++i) d_output[i] = 1.0f;
    for (int i = 0; i < num_channels * kernel_size * kernel_size; ++i) d_kernel[i] = 0.5f;
    for (int i = 0; i < num_channels * output_height * output_width; ++i) d_output_grad[i] = 0.1f;
    for (int i = 0; i < num_channels * kernel_size * kernel_size; ++i) d_kernel_grad[i] = 0.0f;

    // Define block and grid sizes
    dim3 blockSize(16, 16, 1);
    dim3 gridSize((output_width + blockSize.x - 1) / blockSize.x, (output_height + blockSize.y - 1) / blockSize.y, num_channels);

    // Launch kernel
    size_t sharedMemSize = num_channels * (kernel_size * kernel_size + input_height * input_width) * sizeof(float);
    convBackpropKernel<<<gridSize, blockSize, sharedMemSize>>>(d_input, d_output, d_kernel, d_kernel_grad, d_output_grad, input_width, input_height, output_width, output_height, kernel_size, num_channels);
    CUDA_CHECK(cudaGetLastError());
    CUDA_CHECK(cudaDeviceSynchronize());

    // Print kernel gradient
    std::cout << "Kernel Gradient:" << std::endl;
    for (int c = 0; c < num_channels; ++c) {
        for (int ky = 0; ky < kernel_size; ++ky) {
            for (int kx = 0; kx < kernel_size; ++kx) {
                int idx = c * kernel_size * kernel_size + ky * kernel_size + kx;
                std::cout << d_kernel_grad[idx] << " ";
            }
            std::cout << std::endl;
        }
        std::cout << std::endl;
    }

    // Free memory
    CUDA_CHECK(cudaFree(d_input));
    CUDA_CHECK(cudaFree(d_output));
    CUDA_CHECK(cudaFree(d_kernel));
    CUDA_CHECK(cudaFree(d_kernel_grad));
    CUDA_CHECK(cudaFree(d_output_grad));

    return 0;
}
	.file	"tmpxft_000d9910_00000000-6_cuda_code_017690.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4668:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4668:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
	.type	_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, @function
_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii:
.LFB4034:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z18convBackpropKernelPfS_S_S_S_iiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L3:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4034:
	.size	_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, .-_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
	.globl	_Z18convBackpropKernelPfS_S_S_S_iiiiii
	.type	_Z18convBackpropKernelPfS_S_S_S_iiiiii, @function
_Z18convBackpropKernelPfS_S_S_S_iiiiii:
.LFB4035:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
	.cfi_endproc
.LFE4035:
	.size	_Z18convBackpropKernelPfS_S_S_S_iiiiii, .-_Z18convBackpropKernelPfS_S_S_S_iiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error in "
.LC1:
	.string	"/home/ubuntu/Datasets/cuda-codes-80k-from-llm-dedup/cuda_code_017690.cu"
.LC2:
	.string	":"
.LC3:
	.string	". Error: "
.LC7:
	.string	"Kernel Gradient:"
.LC8:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1, %edx
	movl	$12288, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	je	.L10
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	movl	%eax, %ebx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$95, %esi
	movq	%rax, %rdi
	jmp	.L39
.L10:
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$10800, %esi
	call	cudaMallocManaged@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L11
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$96, %esi
	movq	%rax, %rdi
.L39:
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	$1, %edi
	call	exit@PLT
.L11:
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$108, %esi
	call	cudaMallocManaged@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L12
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$97, %esi
	movq	%rax, %rdi
	jmp	.L39
.L12:
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	movl	$108, %esi
	call	cudaMallocManaged@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L13
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$98, %esi
	movq	%rax, %rdi
	jmp	.L39
.L13:
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	movl	$10800, %esi
	call	cudaMallocManaged@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L14
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$99, %esi
	movq	%rax, %rdi
	jmp	.L39
.L14:
	movq	8(%rsp), %rdx
	movss	.LC4(%rip), %xmm0
	xorl	%eax, %eax
.L15:
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$3072, %rax
	jne	.L15
	movq	16(%rsp), %rdx
	xorl	%eax, %eax
.L16:
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$2700, %rax
	jne	.L16
	movq	24(%rsp), %rdx
	movss	.LC5(%rip), %xmm0
	xorl	%eax, %eax
.L17:
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$27, %rax
	jne	.L17
	movq	40(%rsp), %rdx
	movss	.LC6(%rip), %xmm0
	xorl	%eax, %eax
.L18:
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	cmpq	$2700, %rax
	jne	.L18
	movq	32(%rsp), %rdi
	xorl	%eax, %eax
	movl	$27, %ecx
	xorl	%r9d, %r9d
	movabsq	$68719476752, %rdx
	movl	$12396, %r8d
	movl	$3, %esi
	movl	$3, 68(%rsp)
	rep stosl
	movl	$1, %ecx
	movabsq	$8589934594, %rdi
	movq	%rdx, 48(%rsp)
	movq	%rdi, 60(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	$32, %r9d
	pushq	$3
	.cfi_def_cfa_offset 160
	pushq	$3
	.cfi_def_cfa_offset 168
	pushq	$30
	.cfi_def_cfa_offset 176
	pushq	$30
	.cfi_def_cfa_offset 184
	pushq	$32
	.cfi_def_cfa_offset 192
	movq	88(%rsp), %r8
	movq	80(%rsp), %rcx
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
	addq	$48, %rsp
	.cfi_def_cfa_offset 144
.L19:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L20
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$115, %esi
	movq	%rax, %rdi
	jmp	.L39
.L20:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L21
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$116, %esi
	movq	%rax, %rdi
	jmp	.L39
.L21:
	leaq	_ZSt4cout(%rip), %r13
	leaq	.LC7(%rip), %rsi
	xorl	%r12d, %r12d
	movq	%r13, %rdi
	leaq	.LC8(%rip), %r14
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L22:
	xorl	%ebp, %ebp
.L26:
	imulq	$12, %rbp, %rbx
	xorl	%r15d, %r15d
	addq	%r12, %rbx
.L23:
	movq	32(%rsp), %rax
	movq	%r13, %rdi
	incl	%r15d
	cvtss2sd	(%rax,%rbx), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r14, %rsi
	addq	$4, %rbx
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpl	$3, %r15d
	jne	.L23
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%r13, %rdi
	incq	%rbp
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpq	$3, %rbp
	jne	.L26
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%r13, %rdi
	addq	$36, %r12
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpq	$108, %r12
	jne	.L22
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L27
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$132, %esi
	movq	%rax, %rdi
	jmp	.L39
.L27:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L28
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$133, %esi
	movq	%rax, %rdi
	jmp	.L39
.L28:
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L29
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$134, %esi
	movq	%rax, %rdi
	jmp	.L39
.L29:
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L30
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$135, %esi
	movq	%rax, %rdi
	jmp	.L39
.L30:
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L31
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$136, %esi
	movq	%rax, %rdi
	jmp	.L39
.L31:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4009:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z18convBackpropKernelPfS_S_S_S_iiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convBackpropKernelPfS_S_S_S_iiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	1065353216
	.align 4
.LC5:
	.long	1056964608
	.align 4
.LC6:
	.long	1036831949
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>

#define CUDA_CHECK(call) \
    { \
        hipError_t err = call; \
        if (err != hipSuccess) { \
            std::cerr << "CUDA error in " << __FILE__ << ":" << __LINE__ << ". Error: " << hipGetErrorString(err) << std::endl; \
            exit(EXIT_FAILURE); \
        } \
    }

// Kernel for backpropagation in a convolutional layer
__global__ void convBackpropKernel(float* d_input, float* d_output, float* d_kernel, float* d_kernel_grad, float* d_output_grad, int input_width, int input_height, int output_width, int output_height, int kernel_size, int num_channels) {
    // Define block size and thread indices
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int bx = blockIdx.x;
    int by = blockIdx.y;
    int bz = blockIdx.z;

    // Calculate the output gradient index
    int out_x = bx * blockDim.x + tx;
    int out_y = by * blockDim.y + ty;
    int channel = bz;

    // Check if the output gradient index is within bounds
    if (out_x >= output_width || out_y >= output_height) return;

    // Shared memory for input and kernel
    extern __shared__ float shared_memory[];
    float* shared_input = shared_memory;
    float* shared_kernel = &shared_memory[num_channels * kernel_size * kernel_size];

    // Load kernel into shared memory
    int kx = tx;
    int ky = ty;
    if (kx < kernel_size && ky < kernel_size) {
        for (int c = 0; c < num_channels; ++c) {
            int kernel_idx = c * kernel_size * kernel_size + ky * kernel_size + kx;
            shared_kernel[kernel_idx] = d_kernel[kernel_idx];
        }
    }
    __syncthreads();

    // Load input into shared memory
    int in_x = out_x;
    int in_y = out_y;
    if (tx < num_channels && ty < input_height) {
        for (int c = 0; c < num_channels; ++c) {
            int input_idx = c * input_height * input_width + ty * input_width + in_x;
            shared_input[ty * input_width + in_x] = d_input[input_idx];
        }
    }
    __syncthreads();

    // Compute the gradient for the kernel
    float grad_sum = 0.0f;
    if (out_x < output_width && out_y < output_height) {
        for (int c = 0; c < num_channels; ++c) {
            for (int ky = 0; ky < kernel_size; ++ky) {
                for (int kx = 0; kx < kernel_size; ++kx) {
                    int in_x = out_x + kx;
                    int in_y = out_y + ky;
                    if (in_x < input_width && in_y < input_height) {
                        int input_idx = c * input_height * input_width + in_y * input_width + in_x;
                        int kernel_idx = c * kernel_size * kernel_size + ky * kernel_size + kx;
                        int output_idx = channel * output_height * output_width + out_y * output_width + out_x;
                        grad_sum += d_input[input_idx] * d_output_grad[output_idx];
                    }
                }
            }
        }
    }
    __syncthreads();

    // Store the kernel gradient
    if (tx < num_channels && ty < kernel_size * kernel_size) {
        int kernel_idx = channel * kernel_size * kernel_size + ty * kernel_size + tx;
        atomicAdd(&d_kernel_grad[kernel_idx], grad_sum);
    }
}

int main() {
    // Problem dimensions
    int input_width = 32, input_height = 32, output_width = 30, output_height = 30, kernel_size = 3, num_channels = 3;

    // Allocate Unified Memory for input, output, kernel, kernel gradient, and output gradient
    float* d_input;
    float* d_output;
    float* d_kernel;
    float* d_kernel_grad;
    float* d_output_grad;
    CUDA_CHECK(hipMallocManaged(&d_input, num_channels * input_height * input_width * sizeof(float)));
    CUDA_CHECK(hipMallocManaged(&d_output, num_channels * output_height * output_width * sizeof(float)));
    CUDA_CHECK(hipMallocManaged(&d_kernel, num_channels * kernel_size * kernel_size * sizeof(float)));
    CUDA_CHECK(hipMallocManaged(&d_kernel_grad, num_channels * kernel_size * kernel_size * sizeof(float)));
    CUDA_CHECK(hipMallocManaged(&d_output_grad, num_channels * output_height * output_width * sizeof(float)));

    // Initialize data
    for (int i = 0; i < num_channels * input_height * input_width; ++i) d_input[i] = 1.0f;
    for (int i = 0; i < num_channels * output_height * output_width; ++i) d_output[i] = 1.0f;
    for (int i = 0; i < num_channels * kernel_size * kernel_size; ++i) d_kernel[i] = 0.5f;
    for (int i = 0; i < num_channels * output_height * output_width; ++i) d_output_grad[i] = 0.1f;
    for (int i = 0; i < num_channels * kernel_size * kernel_size; ++i) d_kernel_grad[i] = 0.0f;

    // Define block and grid sizes
    dim3 blockSize(16, 16, 1);
    dim3 gridSize((output_width + blockSize.x - 1) / blockSize.x, (output_height + blockSize.y - 1) / blockSize.y, num_channels);

    // Launch kernel
    size_t sharedMemSize = num_channels * (kernel_size * kernel_size + input_height * input_width) * sizeof(float);
    convBackpropKernel<<<gridSize, blockSize, sharedMemSize>>>(d_input, d_output, d_kernel, d_kernel_grad, d_output_grad, input_width, input_height, output_width, output_height, kernel_size, num_channels);
    CUDA_CHECK(hipGetLastError());
    CUDA_CHECK(hipDeviceSynchronize());

    // Print kernel gradient
    std::cout << "Kernel Gradient:" << std::endl;
    for (int c = 0; c < num_channels; ++c) {
        for (int ky = 0; ky < kernel_size; ++ky) {
            for (int kx = 0; kx < kernel_size; ++kx) {
                int idx = c * kernel_size * kernel_size + ky * kernel_size + kx;
                std::cout << d_kernel_grad[idx] << " ";
            }
            std::cout << std::endl;
        }
        std::cout << std::endl;
    }

    // Free memory
    CUDA_CHECK(hipFree(d_input));
    CUDA_CHECK(hipFree(d_output));
    CUDA_CHECK(hipFree(d_kernel));
    CUDA_CHECK(hipFree(d_kernel_grad));
    CUDA_CHECK(hipFree(d_output_grad));

    return 0;
}
	.text
	.file	"cuda_code_017690.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii # -- Begin function _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
	.type	_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii,@function
_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii: # @_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convBackpropKernelPfS_S_S_S_iiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii, .Lfunc_end0-_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	32(%rsp), %rdi
	movl	$12288, %esi                    # imm = 0x3000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.3:
	leaq	24(%rsp), %rdi
	movl	$10800, %esi                    # imm = 0x2A30
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.5:
	leaq	16(%rsp), %rdi
	movl	$108, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.7:
	movq	%rsp, %rdi
	movl	$108, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.9:
	leaq	8(%rsp), %rdi
	movl	$10800, %esi                    # imm = 0x2A30
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_41
# %bb.10:                               # %.preheader145
	movq	32(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_11:                               # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rax,%rcx,4)      # imm = 0x3F800000
	incq	%rcx
	cmpq	$3072, %rcx                     # imm = 0xC00
	jne	.LBB1_11
# %bb.12:                               # %.preheader144
	movq	24(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_13:                               # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rax,%rcx,4)      # imm = 0x3F800000
	incq	%rcx
	cmpq	$2700, %rcx                     # imm = 0xA8C
	jne	.LBB1_13
# %bb.14:                               # %.preheader143
	movq	16(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_15:                               # =>This Inner Loop Header: Depth=1
	movl	$1056964608, (%rax,%rcx,4)      # imm = 0x3F000000
	incq	%rcx
	cmpq	$27, %rcx
	jne	.LBB1_15
# %bb.16:                               # %.preheader142
	movq	8(%rsp), %rax
	xorl	%ecx, %ecx
.LBB1_17:                               # =>This Inner Loop Header: Depth=1
	movl	$1036831949, (%rax,%rcx,4)      # imm = 0x3DCCCCCD
	incq	%rcx
	cmpq	$2700, %rcx                     # imm = 0xA8C
	jne	.LBB1_17
# %bb.18:                               # %.preheader141
	movq	(%rsp), %rax
	xorps	%xmm0, %xmm0
	movups	%xmm0, 92(%rax)
	movups	%xmm0, 80(%rax)
	movups	%xmm0, 64(%rax)
	movups	%xmm0, 48(%rax)
	movups	%xmm0, 32(%rax)
	movups	%xmm0, 16(%rax)
	movups	%xmm0, (%rax)
	movabsq	$8589934594, %rdi               # imm = 0x200000002
	movl	$3, %ebx
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$12396, %r8d                    # imm = 0x306C
	movl	$3, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_20
# %bb.19:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	(%rsp), %rcx
	movq	8(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$30, %eax
	movl	$32, %r9d
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	$32
	.cfi_adjust_cfa_offset 8
	callq	_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB1_20:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.22:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_23
# %bb.24:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$16, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB1_25:                               # %.preheader140
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_26 Depth 2
                                        #       Child Loop BB1_27 Depth 3
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB1_26:                               # %.preheader
                                        #   Parent Loop BB1_25 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_27 Depth 3
	xorl	%ebp, %ebp
.LBB1_27:                               #   Parent Loop BB1_25 Depth=1
                                        #     Parent Loop BB1_26 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	(%rsp), %rax
	addq	%r12, %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%rbp,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.5, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbp
	cmpq	$3, %rbp
	jne	.LBB1_27
# %bb.28:                               #   in Loop: Header=BB1_26 Depth=2
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r13
	addq	$12, %r12
	cmpq	$3, %r13
	jne	.LBB1_26
# %bb.29:                               #   in Loop: Header=BB1_25 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r15
	addq	$36, %r14
	cmpq	$3, %r15
	jne	.LBB1_25
# %bb.30:
	movq	32(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_31
# %bb.32:
	movq	24(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_33
# %bb.34:
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_35
# %bb.36:
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_37
# %bb.38:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_39
# %bb.40:
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:
	.cfi_def_cfa_offset 96
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$95, %esi
	jmp	.LBB1_2
.LBB1_4:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$96, %esi
	jmp	.LBB1_2
.LBB1_6:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$97, %esi
	jmp	.LBB1_2
.LBB1_8:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$98, %esi
	jmp	.LBB1_2
.LBB1_41:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$99, %esi
	jmp	.LBB1_2
.LBB1_21:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$115, %esi
	jmp	.LBB1_2
.LBB1_23:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$116, %esi
	jmp	.LBB1_2
.LBB1_31:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$132, %esi
	jmp	.LBB1_2
.LBB1_33:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$133, %esi
	jmp	.LBB1_2
.LBB1_35:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$134, %esi
	jmp	.LBB1_2
.LBB1_37:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$135, %esi
	jmp	.LBB1_2
.LBB1_39:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	$136, %esi
.LBB1_2:
	callq	_ZNSolsEi
	movl	$.L.str.3, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convBackpropKernelPfS_S_S_S_iiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convBackpropKernelPfS_S_S_S_iiiiii,@object # @_Z18convBackpropKernelPfS_S_S_S_iiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z18convBackpropKernelPfS_S_S_S_iiiiii
	.p2align	3, 0x0
_Z18convBackpropKernelPfS_S_S_S_iiiiii:
	.quad	_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
	.size	_Z18convBackpropKernelPfS_S_S_S_iiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error in "
	.size	.L.str, 15

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/hip-codes-80k-from-llm-dedup-disassemble-sm89/cuda_code_017690.hip"
	.size	.L.str.1, 89

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	":"
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	". Error: "
	.size	.L.str.3, 10

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Kernel Gradient:"
	.size	.L.str.4, 17

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	" "
	.size	.L.str.5, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convBackpropKernelPfS_S_S_S_iiiiii"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convBackpropKernelPfS_S_S_S_iiiiii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convBackpropKernelPfS_S_S_S_iiiiii ; -- Begin function _Z18convBackpropKernelPfS_S_S_S_iiiiii
	.globl	_Z18convBackpropKernelPfS_S_S_S_iiiiii
	.p2align	8
	.type	_Z18convBackpropKernelPfS_S_S_S_iiiiii,@function
_Z18convBackpropKernelPfS_S_S_S_iiiiii: ; @_Z18convBackpropKernelPfS_S_S_S_iiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[8:11], s[0:1], 0x28
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s16, s13, s3
	v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
	v_add_nc_u32_e32 v3, s16, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s10, v3
	v_cmp_gt_i32_e64 s2, s11, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_20
; %bb.1:
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x38
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[12:13], s[0:1], 0x20
	v_max_i32_e32 v4, v1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v4
	s_cmp_gt_i32 s3, 0
	s_mul_i32 s14, s2, s2
	s_cselect_b32 s17, -1, 0
	s_and_b32 s19, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s18, s19
	s_cbranch_execz .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
	s_mul_i32 s19, s3, s14
	s_mov_b32 s20, s3
	s_lshl_b32 s19, s19, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v5, 2, v4
	v_add3_u32 v6, 0, s19, v5
	s_lshl_b32 s19, s14, 2
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s20, s20, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s20, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s14, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v5, v[7:8], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v5
	v_add_nc_u32_e32 v6, s19, v6
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %Flow211
	s_or_b32 exec_lo, exec_lo, s18
	s_load_b64 s[4:5], s[0:1], 0x0
	v_cmp_gt_i32_e64 s0, s3, v1
	v_cmp_gt_i32_e32 vcc_lo, s9, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s1, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s18, s1, s17
	s_and_saveexec_b32 s1, s18
	s_cbranch_execz .LBB0_6
; %bb.5:                                ; %.lr.ph150
	s_add_i32 s18, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s18, s9, v[0:1]
	v_mad_u64_u32 v[5:6], null, v4, s8, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_lshlrev_b32_e32 v6, 2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_mul_lo_u32 v5, v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v5, 2, v5
	v_add3_u32 v5, 0, v6, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
.LBB0_6:                                ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s17
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_16
; %bb.7:                                ; %.preheader144.lr.ph
	v_mad_u64_u32 v[4:5], null, s15, s11, v[2:3]
	v_mul_lo_u32 v7, s8, v2
	s_cmp_gt_i32 s2, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, v4, s10, v[3:4]
	v_add3_u32 v7, v1, v7, s16
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	s_mul_i32 s12, s9, s8
.LBB0_8:                                ; %.preheader144
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_10 Depth 2
                                        ;       Child Loop BB0_11 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_15
; %bb.9:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_mov_b32_e32 v8, v7
	s_mov_b32 s13, 0
.LBB0_10:                               ; %.preheader
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_11 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, s13, v2
	s_mov_b32 s16, 0
	v_cmp_gt_i32_e32 vcc_lo, s9, v9
.LBB0_11:                               ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_10 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v9, s16, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s1, s8, v9
	s_and_b32 s1, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s17, s1
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=3
	v_add_nc_u32_e32 v9, s16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s1, s4, v9
	v_add_co_ci_u32_e64 v10, s1, s5, v10, s1
	global_load_b32 v9, v[9:10], off
	global_load_b32 v10, v[4:5], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v9, v10
.LBB0_13:                               ;   in Loop: Header=BB0_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s17
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, s16
	s_cbranch_scc0 .LBB0_11
; %bb.14:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_10 Depth=2
	v_add_nc_u32_e32 v8, s8, v8
	s_add_i32 s13, s13, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s13, s2
	s_cbranch_scc0 .LBB0_10
.LBB0_15:                               ; %._crit_edge156
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_add_nc_u32_e32 v7, s12, v7
	s_add_i32 s11, s11, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, s3
	s_cbranch_scc0 .LBB0_8
	s_branch .LBB0_17
.LBB0_16:
	v_mov_b32_e32 v6, 0
.LBB0_17:                               ; %._crit_edge160
	v_cmp_gt_u32_e32 vcc_lo, s14, v0
	s_barrier
	buffer_gl0_inv
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_20
; %bb.18:
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v3, v[0:1], off
.LBB0_19:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v3, v6
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_19
.LBB0_20:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convBackpropKernelPfS_S_S_S_iiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convBackpropKernelPfS_S_S_S_iiiiii, .Lfunc_end0-_Z18convBackpropKernelPfS_S_S_S_iiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 23
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         184
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convBackpropKernelPfS_S_S_S_iiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z18convBackpropKernelPfS_S_S_S_iiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
