#include <iostream>
#include <cuda_runtime.h>
#include <cuda_fp16.h>

#define DIM 64
#define RADIUS 15
#define BLOCK_SIZE 16

__global__ void stencil64D(float* input, float* output) {
    __shared__ float sharedMem[BLOCK_SIZE + 2 * RADIUS][BLOCK_SIZE + 2 * RADIUS];

    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;

    // Load data into shared memory, including halo regions
    int sharedX = threadIdx.x + RADIUS;
    int sharedY = threadIdx.y + RADIUS;

    // Avoid bank conflicts by offsetting each row by one element
    int offset = threadIdx.y & 1;

    if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
        sharedMem[sharedY][sharedX] = input[(y + offset) * DIM + (x + offset)];
    } else {
        sharedMem[sharedY][sharedX] = 0.0f;
    }

    // Load halo regions
    if (threadIdx.x < RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY][sharedX - RADIUS] = input[(y + offset) * DIM + (x - RADIUS + offset)];
        } else {
            sharedMem[sharedY][sharedX - RADIUS] = 0.0f;
        }
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS + BLOCK_SIZE && y < DIM - RADIUS) {
            sharedMem[sharedY + BLOCK_SIZE][sharedX - RADIUS] = input[(y + BLOCK_SIZE + offset) * DIM + (x - RADIUS + offset)];
        } else {
            sharedMem[sharedY + BLOCK_SIZE][sharedX - RADIUS] = 0.0f;
        }
    }
    if (threadIdx.x >= blockDim.x - RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY][sharedX + RADIUS] = input[(y + offset) * DIM + (x + RADIUS + offset)];
        } else {
            sharedMem[sharedY][sharedX + RADIUS] = 0.0f;
        }
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS + BLOCK_SIZE && y < DIM - RADIUS) {
            sharedMem[sharedY + BLOCK_SIZE][sharedX + RADIUS] = input[(y + BLOCK_SIZE + offset) * DIM + (x + RADIUS + offset)];
        } else {
            sharedMem[sharedY + BLOCK_SIZE][sharedX + RADIUS] = 0.0f;
        }
    }
    if (threadIdx.y < RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY - RADIUS][sharedX] = input[(y - RADIUS + offset) * DIM + (x + offset)];
        } else {
            sharedMem[sharedY - RADIUS][sharedX] = 0.0f;
        }
        if (x >= RADIUS + BLOCK_SIZE && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY - RADIUS][sharedX + BLOCK_SIZE] = input[(y - RADIUS + offset) * DIM + (x + BLOCK_SIZE + offset)];
        } else {
            sharedMem[sharedY - RADIUS][sharedX + BLOCK_SIZE] = 0.0f;
        }
    }
    if (threadIdx.y >= blockDim.y - RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY + RADIUS][sharedX] = input[(y + RADIUS + offset) * DIM + (x + offset)];
        } else {
            sharedMem[sharedY + RADIUS][sharedX] = 0.0f;
        }
        if (x >= RADIUS + BLOCK_SIZE && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY + RADIUS][sharedX + BLOCK_SIZE] = input[(y + RADIUS + offset) * DIM + (x + BLOCK_SIZE + offset)];
        } else {
            sharedMem[sharedY + RADIUS][sharedX + BLOCK_SIZE] = 0.0f;
        }
    }

    __syncthreads();

    // Perform stencil operation
    float result = 0.0f;
    for (int dy = -RADIUS; dy <= RADIUS; ++dy) {
        for (int dx = -RADIUS; dx <= RADIUS; ++dx) {
            result += sharedMem[sharedY + dy][sharedX + dx];
        }
    }

    // Store result back to global memory
    if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
        output[y * DIM + x] = result;
    }
}

int main() {
    float *input, *output;
    size_t size = DIM * DIM * sizeof(float);

    // Allocate Unified Memory -- accessible from CPU or GPU
    cudaMallocManaged(&input, size);
    cudaMallocManaged(&output, size);

    // Initialize input data
    for (int i = 0; i < DIM * DIM; i++) {
        input[i] = static_cast<float>(i % 10);
    }

    // Launch kernel
    dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
    dim3 numBlocks((DIM + BLOCK_SIZE - 1) / BLOCK_SIZE, (DIM + BLOCK_SIZE - 1) / BLOCK_SIZE);
    stencil64D<<<numBlocks, threadsPerBlock>>>(input, output);

    // Wait for GPU to finish before accessing on host
    cudaDeviceSynchronize();

    // Check for any errors launching the kernel
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        fprintf(stderr, "Failed to launch stencil64D kernel (error code %s)!\n", cudaGetErrorString(err));
        exit(EXIT_FAILURE);
    }

    // Free memory
    cudaFree(input);
    cudaFree(output);

    return 0;
}
	.file	"tmpxft_00036cc7_00000000-6_cuda_code_007164.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z10stencil64DPfS_PfS_
	.type	_Z32__device_stub__Z10stencil64DPfS_PfS_, @function
_Z32__device_stub__Z10stencil64DPfS_PfS_:
.LFB4034:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10stencil64DPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4034:
	.size	_Z32__device_stub__Z10stencil64DPfS_PfS_, .-_Z32__device_stub__Z10stencil64DPfS_PfS_
	.globl	_Z10stencil64DPfS_
	.type	_Z10stencil64DPfS_, @function
_Z10stencil64DPfS_:
.LFB4035:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10stencil64DPfS_PfS_
	.cfi_endproc
.LFE4035:
	.size	_Z10stencil64DPfS_, .-_Z10stencil64DPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Failed to launch stencil64D kernel (error code %s)!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4009:
	.cfi_startproc
	endbr64
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movl	$1, %edx
	movl	$16384, %esi
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMallocManaged@PLT
	leaq	8(%rsp), %rdi
	movl	$16384, %esi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rdi
	xorl	%ecx, %ecx
	movl	$10, %esi
.L9:
	movl	%ecx, %eax
	cltd
	idivl	%esi
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rdi,%rcx,4)
	incq	%rcx
	cmpq	$4096, %rcx
	jne	.L9
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movabsq	$17179869188, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z32__device_stub__Z10stencil64DPfS_PfS_
.L10:
	call	cudaDeviceSynchronize@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L11
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L11:
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4009:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z10stencil64DPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10stencil64DPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>

#define DIM 64
#define RADIUS 15
#define BLOCK_SIZE 16

__global__ void stencil64D(float* input, float* output) {
    __shared__ float sharedMem[BLOCK_SIZE + 2 * RADIUS][BLOCK_SIZE + 2 * RADIUS];

    int x = blockIdx.x * blockDim.x + threadIdx.x;
    int y = blockIdx.y * blockDim.y + threadIdx.y;

    // Load data into shared memory, including halo regions
    int sharedX = threadIdx.x + RADIUS;
    int sharedY = threadIdx.y + RADIUS;

    // Avoid bank conflicts by offsetting each row by one element
    int offset = threadIdx.y & 1;

    if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
        sharedMem[sharedY][sharedX] = input[(y + offset) * DIM + (x + offset)];
    } else {
        sharedMem[sharedY][sharedX] = 0.0f;
    }

    // Load halo regions
    if (threadIdx.x < RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY][sharedX - RADIUS] = input[(y + offset) * DIM + (x - RADIUS + offset)];
        } else {
            sharedMem[sharedY][sharedX - RADIUS] = 0.0f;
        }
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS + BLOCK_SIZE && y < DIM - RADIUS) {
            sharedMem[sharedY + BLOCK_SIZE][sharedX - RADIUS] = input[(y + BLOCK_SIZE + offset) * DIM + (x - RADIUS + offset)];
        } else {
            sharedMem[sharedY + BLOCK_SIZE][sharedX - RADIUS] = 0.0f;
        }
    }
    if (threadIdx.x >= blockDim.x - RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY][sharedX + RADIUS] = input[(y + offset) * DIM + (x + RADIUS + offset)];
        } else {
            sharedMem[sharedY][sharedX + RADIUS] = 0.0f;
        }
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS + BLOCK_SIZE && y < DIM - RADIUS) {
            sharedMem[sharedY + BLOCK_SIZE][sharedX + RADIUS] = input[(y + BLOCK_SIZE + offset) * DIM + (x + RADIUS + offset)];
        } else {
            sharedMem[sharedY + BLOCK_SIZE][sharedX + RADIUS] = 0.0f;
        }
    }
    if (threadIdx.y < RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY - RADIUS][sharedX] = input[(y - RADIUS + offset) * DIM + (x + offset)];
        } else {
            sharedMem[sharedY - RADIUS][sharedX] = 0.0f;
        }
        if (x >= RADIUS + BLOCK_SIZE && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY - RADIUS][sharedX + BLOCK_SIZE] = input[(y - RADIUS + offset) * DIM + (x + BLOCK_SIZE + offset)];
        } else {
            sharedMem[sharedY - RADIUS][sharedX + BLOCK_SIZE] = 0.0f;
        }
    }
    if (threadIdx.y >= blockDim.y - RADIUS) {
        if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY + RADIUS][sharedX] = input[(y + RADIUS + offset) * DIM + (x + offset)];
        } else {
            sharedMem[sharedY + RADIUS][sharedX] = 0.0f;
        }
        if (x >= RADIUS + BLOCK_SIZE && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
            sharedMem[sharedY + RADIUS][sharedX + BLOCK_SIZE] = input[(y + RADIUS + offset) * DIM + (x + BLOCK_SIZE + offset)];
        } else {
            sharedMem[sharedY + RADIUS][sharedX + BLOCK_SIZE] = 0.0f;
        }
    }

    __syncthreads();

    // Perform stencil operation
    float result = 0.0f;
    for (int dy = -RADIUS; dy <= RADIUS; ++dy) {
        for (int dx = -RADIUS; dx <= RADIUS; ++dx) {
            result += sharedMem[sharedY + dy][sharedX + dx];
        }
    }

    // Store result back to global memory
    if (x >= RADIUS && x < DIM - RADIUS && y >= RADIUS && y < DIM - RADIUS) {
        output[y * DIM + x] = result;
    }
}

int main() {
    float *input, *output;
    size_t size = DIM * DIM * sizeof(float);

    // Allocate Unified Memory -- accessible from CPU or GPU
    hipMallocManaged(&input, size);
    hipMallocManaged(&output, size);

    // Initialize input data
    for (int i = 0; i < DIM * DIM; i++) {
        input[i] = static_cast<float>(i % 10);
    }

    // Launch kernel
    dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
    dim3 numBlocks((DIM + BLOCK_SIZE - 1) / BLOCK_SIZE, (DIM + BLOCK_SIZE - 1) / BLOCK_SIZE);
    stencil64D<<<numBlocks, threadsPerBlock>>>(input, output);

    // Wait for GPU to finish before accessing on host
    hipDeviceSynchronize();

    // Check for any errors launching the kernel
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        fprintf(stderr, "Failed to launch stencil64D kernel (error code %s)!\n", hipGetErrorString(err));
        exit(EXIT_FAILURE);
    }

    // Free memory
    hipFree(input);
    hipFree(output);

    return 0;
}
	.text
	.file	"cuda_code_007164.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__stencil64DPfS_ # -- Begin function _Z25__device_stub__stencil64DPfS_
	.type	_Z25__device_stub__stencil64DPfS_,@function
_Z25__device_stub__stencil64DPfS_:      # @_Z25__device_stub__stencil64DPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10stencil64DPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__stencil64DPfS_, .Lfunc_end0-_Z25__device_stub__stencil64DPfS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	8(%rsp), %rbx
	movl	$16384, %esi                    # imm = 0x4000
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movl	$16384, %esi                    # imm = 0x4000
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%eax, %eax
	movq	(%rbx), %rcx
	movl	$65535, %edx                    # imm = 0xFFFF
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, %esi
	andl	%edx, %esi
	imull	$52429, %esi, %esi              # imm = 0xCCCD
	shrl	$18, %esi
	andl	$-2, %esi
	leal	(%rsi,%rsi,4), %esi
	movl	%eax, %edi
	subl	%esi, %edi
	andl	%edx, %edi
	xorps	%xmm0, %xmm0
	cvtsi2ss	%edi, %xmm0
	movss	%xmm0, (%rcx,%rax,4)
	incq	%rax
	cmpq	$4096, %rax                     # imm = 0x1000
	jne	.LBB1_1
# %bb.2:
	movabsq	$17179869188, %rdi              # imm = 0x400000004
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z25__device_stub__stencil64DPfS_
.LBB1_4:
	callq	hipDeviceSynchronize
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB1_6:
	.cfi_def_cfa_offset 32
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10stencil64DPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10stencil64DPfS_,@object      # @_Z10stencil64DPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z10stencil64DPfS_
	.p2align	3, 0x0
_Z10stencil64DPfS_:
	.quad	_Z25__device_stub__stencil64DPfS_
	.size	_Z10stencil64DPfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Failed to launch stencil64D kernel (error code %s)!\n"
	.size	.L.str, 53

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10stencil64DPfS_"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__stencil64DPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10stencil64DPfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10stencil64DPfS_      ; -- Begin function _Z10stencil64DPfS_
	.globl	_Z10stencil64DPfS_
	.p2align	8
	.type	_Z10stencil64DPfS_,@function
_Z10stencil64DPfS_:                     ; @_Z10stencil64DPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	v_mov_b32_e32 v9, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s2, 0xffff
	s_lshr_b32 s3, s2, 16
	v_mad_u64_u32 v[1:2], null, s14, s8, v[5:6]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_bfe_u32 v3, v0, 10, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, -15, v1
	v_add_nc_u32_e32 v7, -15, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_lshl_u32 v6, v2, v3, 6
	v_cmp_gt_u32_e64 s0, 34, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e32 vcc_lo, 34, v7
	s_and_b32 s2, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_add3_u32 v9, v1, v3, v6
	v_mov_b32_e32 v10, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, s1, s4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s1, s5, v10, s1
	global_load_b32 v9, v[9:10], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s9
	v_lshlrev_b32_e32 v0, 2, v5
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v0, 0xb8, v4, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v9 offset:2820
	v_cmpx_gt_u32_e32 15, v5
	s_cbranch_execz .LBB0_8
; %bb.3:
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_add3_u32 v10, v8, v3, v6
	v_mov_b32_e32 v11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, s1, s4, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s1, s5, v11, s1
	global_load_b32 v10, v[10:11], off
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s10
	v_subrev_nc_u32_e32 v11, 31, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v10 offset:2760
	v_cmp_gt_u32_e64 s1, 18, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s10, s1
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v6, v8, 0x400
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, s4, v8
	v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
	global_load_b32 v9, v[8:9], off
.LBB0_7:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v9 offset:5704
.LBB0_8:                                ; %Flow254
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s8, s8, -15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s1, s8, v5
	s_and_saveexec_b32 s8, s1
	s_cbranch_execz .LBB0_14
; %bb.9:
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 0
	s_and_saveexec_b32 s9, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_add_nc_u32_e32 v8, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, v8, v6
	v_add_co_ci_u32_e64 v9, null, 0, 0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, s1, s4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
	global_load_b32 v8, v[8:9], off offset:60
.LBB0_11:
	s_or_b32 exec_lo, exec_lo, s9
	v_subrev_nc_u32_e32 v9, 31, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v8 offset:2880
	v_cmp_gt_u32_e64 s1, 18, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_add3_u32 v8, v1, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, s4, v8
	v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, 0x1000, v5
	v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
	global_load_b32 v5, v[8:9], off offset:60
.LBB0_13:                               ; %.sink.split224
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v5 offset:5824
.LBB0_14:                               ; %Flow253
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 15, v4
	s_cbranch_execz .LBB0_20
; %bb.15:
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 0
	v_add_lshl_u32 v7, v7, v3, 6
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB0_17
; %bb.16:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v1, v3, v7
	v_mov_b32_e32 v9, 0
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, s4, v8
	v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
	global_load_b32 v8, v[8:9], off
.LBB0_17:
	s_or_b32 exec_lo, exec_lo, s8
	v_subrev_nc_u32_e32 v9, 31, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v8 offset:60
	v_cmp_gt_u32_e64 s0, 18, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_add_nc_u32_e32 v5, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, v5, v7
	v_add_co_ci_u32_e64 v8, null, 0, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, s0, s4, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	global_load_b32 v5, v[7:8], off offset:64
.LBB0_19:                               ; %.sink.split229
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v5 offset:124
.LBB0_20:                               ; %Flow252
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s3, s3, -15
	s_mov_b32 s1, exec_lo
	v_cmpx_le_u32_e64 s3, v4
	s_cbranch_execz .LBB0_26
; %bb.21:
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_add_nc_u32_e32 v5, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, v5, v6
	v_add_co_ci_u32_e64 v8, null, 0, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, s0, s4, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
	global_load_b32 v5, v[7:8], off offset:3840
.LBB0_23:
	s_or_b32 exec_lo, exec_lo, s3
	v_subrev_nc_u32_e32 v7, 31, v1
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v5 offset:5580
	v_cmp_gt_u32_e64 s0, 18, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s0, vcc_lo
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_25
; %bb.24:
	v_add3_u32 v3, v1, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off offset:3904
.LBB0_25:                               ; %.sink.split236
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v4 offset:5644
.LBB0_26:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	s_mov_b32 s0, -15
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_27:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_28 Depth 2
	s_movk_i32 s1, 0xff84
.LBB0_28:                               ;   Parent Loop BB0_27 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s1, v0
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s1, 0
	ds_load_b32 v4, v4 offset:124
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	s_cbranch_scc0 .LBB0_28
; %bb.29:                               ;   in Loop: Header=BB0_27 Depth=1
	v_add_nc_u32_e32 v0, 0xb8, v0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 16
	s_cbranch_scc0 .LBB0_27
; %bb.30:
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_32
; %bb.31:
	v_lshl_add_u32 v0, v2, 6, v1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_32:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10stencil64DPfS_
		.amdhsa_group_segment_fixed_size 8464
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10stencil64DPfS_, .Lfunc_end0-_Z10stencil64DPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1260
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8464 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8464
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10stencil64DPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10stencil64DPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
