// argon2_cuda.cu
// A research-grade CUDA implementation of Argon2 for secure hashing, optimized for multi-GPU scaling.
// Target architecture: Turing
// Uses CUDA Unified Memory for simplified memory management.

#include <iostream>
#include <cuda_runtime.h>
#include <string.h>
#include <stdint.h>
#include <stdio.h>

// Constants for Argon2
#define ARGON2_BLOCK_SIZE 1024
#define ARGON2_SYNC_POINTS 4
#define ARGON2_QWORDS_IN_BLOCK (ARGON2_BLOCK_SIZE / 8)
#define ARGON2_SYNC_POINTS 4

// Structure to hold Argon2 parameters
typedef struct Argon2Params {
    uint32_t m_cost;  // Memory cost (in KiB)
    uint32_t t_cost;  // Time cost
    uint32_t lanes;   // Parallelism degree
    uint32_t threads; // Number of threads
} Argon2Params;

// CUDA kernel to perform Argon2 hashing
__global__ void argon2Kernel(uint64_t *memory, const Argon2Params params, const uint8_t *password, const uint32_t passwordLength) {
    uint32_t lane = blockIdx.x * blockDim.x + threadIdx.x;
    uint32_t segmentLength = (params.m_cost / params.lanes) / ARGON2_SYNC_POINTS;

    // Initialize the first block
    if (threadIdx.x < ARGON2_QWORDS_IN_BLOCK) {
        memory[lane * ARGON2_QWORDS_IN_BLOCK + threadIdx.x] = (uint64_t)lane;
    }
    __syncthreads();

    // Perform the Argon2 iterations
    for (uint32_t pass = 0; pass < params.t_cost; pass++) {
        for (uint32_t slice = 0; slice < ARGON2_SYNC_POINTS; slice++) {
            for (uint32_t index = 0; index < segmentLength; index++) {
                uint32_t referenceLane = lane;
                uint32_t referenceIndex = index + slice * segmentLength;

                // Select reference block
                if (slice == 0) {
                    if (pass == 0) {
                        referenceLane = 0;
                        referenceIndex = index;
                    } else {
                        referenceLane = lane;
                        referenceIndex = index + (segmentLength * (ARGON2_SYNC_POINTS - 1));
                    }
                } else {
                    referenceLane = lane;
                    referenceIndex = index + (segmentLength * (slice - 1));
                }

                // Perform block mixing
                if (threadIdx.x < ARGON2_QWORDS_IN_BLOCK) {
                    uint64_t block[ARGON2_QWORDS_IN_BLOCK];
                    for (uint32_t i = 0; i < ARGON2_QWORDS_IN_BLOCK; i++) {
                        block[i] = memory[referenceLane * ARGON2_QWORDS_IN_BLOCK + i];
                    }
                    block[threadIdx.x] ^= memory[lane * ARGON2_QWORDS_IN_BLOCK + threadIdx.x];
                    for (uint32_t i = 0; i < ARGON2_QWORDS_IN_BLOCK; i++) {
                        memory[lane * ARGON2_QWORDS_IN_BLOCK + i] = block[i];
                    }
                }
                __syncthreads();
            }
        }
    }
}

// Helper function to check CUDA errors
void checkCudaError(cudaError_t err, const char *file, int line) {
    if (err != cudaSuccess) {
        std::cerr << "CUDA error at " << file << ":" << line << " - " << cudaGetErrorString(err) << std::endl;
        exit(EXIT_FAILURE);
    }
}

#define CHECK_CUDA_ERROR(err) checkCudaError(err, __FILE__, __LINE__)

int main() {
    // Define Argon2 parameters
    Argon2Params params = {1024, 3, 4, 256}; // Example parameters

    // Allocate unified memory for password, memory blocks, and parameters
    uint8_t *password;
    uint64_t *memory;
    Argon2Params *d_params;

    const char *passwordStr = "password123";
    uint32_t passwordLength = strlen(passwordStr);

    CHECK_CUDA_ERROR(cudaMallocManaged(&password, passwordLength));
    CHECK_CUDA_ERROR(cudaMallocManaged(&memory, params.m_cost * 1024 / sizeof(uint64_t)));
    CHECK_CUDA_ERROR(cudaMallocManaged(&d_params, sizeof(Argon2Params)));

    // Copy password and parameters to device
    memcpy(password, passwordStr, passwordLength);
    memcpy(d_params, &params, sizeof(Argon2Params));

    // Launch kernel
    dim3 blockSize(ARGON2_QWORDS_IN_BLOCK);
    dim3 gridSize(params.lanes);
    argon2Kernel<<<gridSize, blockSize>>>(memory, *d_params, password, passwordLength);
    CHECK_CUDA_ERROR(cudaGetLastError());
    CHECK_CUDA_ERROR(cudaDeviceSynchronize());

    // Print the first block of the final memory state (for demonstration)
    std::cout << "Final memory block (first 8 qwords):" << std::endl;
    for (uint32_t i = 0; i < 8; i++) {
        std::cout << memory[i] << " ";
    }
    std::cout << std::endl;

    // Free memory
    CHECK_CUDA_ERROR(cudaFree(password));
    CHECK_CUDA_ERROR(cudaFree(memory));
    CHECK_CUDA_ERROR(cudaFree(d_params));

    return 0;
}
	.file	"tmpxft_001be16b_00000000-6_cuda_code_051321.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error at "
.LC1:
	.string	":"
.LC2:
	.string	" - "
	.text
	.globl	_Z14checkCudaError9cudaErrorPKci
	.type	_Z14checkCudaError9cudaErrorPKci, @function
_Z14checkCudaError9cudaErrorPKci:
.LFB3635:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rsi, %r12
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%edi, %ebx
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z14checkCudaError9cudaErrorPKci, .-_Z14checkCudaError9cudaErrorPKci
	.globl	_Z50__device_stub__Z12argon2KernelPm12Argon2ParamsPKhjPmRK12Argon2ParamsPKhj
	.type	_Z50__device_stub__Z12argon2KernelPm12Argon2ParamsPKhjPmRK12Argon2ParamsPKhj, @function
_Z50__device_stub__Z12argon2KernelPm12Argon2ParamsPKhjPmRK12Argon2ParamsPKhj:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rsi, 112(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12argon2KernelPm12Argon2ParamsPKhj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z50__device_stub__Z12argon2KernelPm12Argon2ParamsPKhjPmRK12Argon2ParamsPKhj, .-_Z50__device_stub__Z12argon2KernelPm12Argon2ParamsPKhjPmRK12Argon2ParamsPKhj
	.globl	_Z12argon2KernelPm12Argon2ParamsPKhj
	.type	_Z12argon2KernelPm12Argon2ParamsPKhj, @function
_Z12argon2KernelPm12Argon2ParamsPKhj:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, (%rsp)
	movq	%rsp, %rsi
	movq	%rdx, 8(%rsp)
	movq	%rcx, %rdx
	movl	%r8d, %ecx
	call	_Z50__device_stub__Z12argon2KernelPm12Argon2ParamsPKhjPmRK12Argon2ParamsPKhj
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z12argon2KernelPm12Argon2ParamsPKhj, .-_Z12argon2KernelPm12Argon2ParamsPKhj
	.section	.rodata.str1.1
.LC3:
	.string	"/home/ubuntu/Datasets/cuda-codes-80k-from-llm-dedup/cuda_code_051321.cu"
.LC4:
	.string	"Final memory block (first 8 qwords):"
.LC5:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$1, %edx
	movl	$11, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	.LC3(%rip), %rbx
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	movl	$97, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$131072, %esi
	call	cudaMallocManaged@PLT
	movl	$98, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$16, %esi
	call	cudaMallocManaged@PLT
	movl	$99, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movq	8(%rsp), %rax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$12582913, %edx
	movl	$1073741825, %edi
	movabsq	$7237970109966541168, %rcx
	movl	$1, %esi
	movq	%rcx, (%rax)
	salq	$10, %rdx
	salq	$2, %rdi
	movabsq	$1099511627780, %rcx
	movl	$858927460, 7(%rax)
	movq	24(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rdx, (%rax)
	movl	$33554433, %edx
	movq	%rcx, 8(%rax)
	salq	$7, %rdx
	movl	$1, %ecx
	movq	%rdx, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	24(%rsp), %rax
	movq	8(%rsp), %rdx
	leaq	56(%rsp), %rsi
	movl	$11, %ecx
	movq	16(%rsp), %rdi
	movups	(%rax), %xmm0
	movups	%xmm0, 56(%rsp)
	call	_Z50__device_stub__Z12argon2KernelPm12Argon2ParamsPKhjPmRK12Argon2ParamsPKhj
.L15:
	call	cudaGetLastError@PLT
	movl	$109, %edx
	movq	%rbx, %rsi
	xorl	%ebp, %ebp
	movl	%eax, %edi
	leaq	_ZSt4cout(%rip), %r12
	leaq	.LC5(%rip), %r13
	call	_Z14checkCudaError9cudaErrorPKci
	call	cudaDeviceSynchronize@PLT
	movl	$110, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	leaq	.LC4(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L16:
	movq	16(%rsp), %rax
	movq	%r12, %rdi
	movq	(%rax,%rbp), %rsi
	addq	$8, %rbp
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cmpq	$64, %rbp
	jne	.L16
	movq	%r12, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	$120, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movl	$121, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	$122, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z14checkCudaError9cudaErrorPKci
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z12argon2KernelPm12Argon2ParamsPKhj"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12argon2KernelPm12Argon2ParamsPKhj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// argon2_cuda.cu
// A research-grade CUDA implementation of Argon2 for secure hashing, optimized for multi-GPU scaling.
// Target architecture: Turing
// Uses CUDA Unified Memory for simplified memory management.

#include <iostream>
#include <hip/hip_runtime.h>
#include <string.h>
#include <stdint.h>
#include <stdio.h>

// Constants for Argon2
#define ARGON2_BLOCK_SIZE 1024
#define ARGON2_SYNC_POINTS 4
#define ARGON2_QWORDS_IN_BLOCK (ARGON2_BLOCK_SIZE / 8)
#define ARGON2_SYNC_POINTS 4

// Structure to hold Argon2 parameters
typedef struct Argon2Params {
    uint32_t m_cost;  // Memory cost (in KiB)
    uint32_t t_cost;  // Time cost
    uint32_t lanes;   // Parallelism degree
    uint32_t threads; // Number of threads
} Argon2Params;

// CUDA kernel to perform Argon2 hashing
__global__ void argon2Kernel(uint64_t *memory, const Argon2Params params, const uint8_t *password, const uint32_t passwordLength) {
    uint32_t lane = blockIdx.x * blockDim.x + threadIdx.x;
    uint32_t segmentLength = (params.m_cost / params.lanes) / ARGON2_SYNC_POINTS;

    // Initialize the first block
    if (threadIdx.x < ARGON2_QWORDS_IN_BLOCK) {
        memory[lane * ARGON2_QWORDS_IN_BLOCK + threadIdx.x] = (uint64_t)lane;
    }
    __syncthreads();

    // Perform the Argon2 iterations
    for (uint32_t pass = 0; pass < params.t_cost; pass++) {
        for (uint32_t slice = 0; slice < ARGON2_SYNC_POINTS; slice++) {
            for (uint32_t index = 0; index < segmentLength; index++) {
                uint32_t referenceLane = lane;
                uint32_t referenceIndex = index + slice * segmentLength;

                // Select reference block
                if (slice == 0) {
                    if (pass == 0) {
                        referenceLane = 0;
                        referenceIndex = index;
                    } else {
                        referenceLane = lane;
                        referenceIndex = index + (segmentLength * (ARGON2_SYNC_POINTS - 1));
                    }
                } else {
                    referenceLane = lane;
                    referenceIndex = index + (segmentLength * (slice - 1));
                }

                // Perform block mixing
                if (threadIdx.x < ARGON2_QWORDS_IN_BLOCK) {
                    uint64_t block[ARGON2_QWORDS_IN_BLOCK];
                    for (uint32_t i = 0; i < ARGON2_QWORDS_IN_BLOCK; i++) {
                        block[i] = memory[referenceLane * ARGON2_QWORDS_IN_BLOCK + i];
                    }
                    block[threadIdx.x] ^= memory[lane * ARGON2_QWORDS_IN_BLOCK + threadIdx.x];
                    for (uint32_t i = 0; i < ARGON2_QWORDS_IN_BLOCK; i++) {
                        memory[lane * ARGON2_QWORDS_IN_BLOCK + i] = block[i];
                    }
                }
                __syncthreads();
            }
        }
    }
}

// Helper function to check CUDA errors
void checkCudaError(hipError_t err, const char *file, int line) {
    if (err != hipSuccess) {
        std::cerr << "CUDA error at " << file << ":" << line << " - " << hipGetErrorString(err) << std::endl;
        exit(EXIT_FAILURE);
    }
}

#define CHECK_CUDA_ERROR(err) checkCudaError(err, __FILE__, __LINE__)

int main() {
    // Define Argon2 parameters
    Argon2Params params = {1024, 3, 4, 256}; // Example parameters

    // Allocate unified memory for password, memory blocks, and parameters
    uint8_t *password;
    uint64_t *memory;
    Argon2Params *d_params;

    const char *passwordStr = "password123";
    uint32_t passwordLength = strlen(passwordStr);

    CHECK_CUDA_ERROR(hipMallocManaged(&password, passwordLength));
    CHECK_CUDA_ERROR(hipMallocManaged(&memory, params.m_cost * 1024 / sizeof(uint64_t)));
    CHECK_CUDA_ERROR(hipMallocManaged(&d_params, sizeof(Argon2Params)));

    // Copy password and parameters to device
    memcpy(password, passwordStr, passwordLength);
    memcpy(d_params, &params, sizeof(Argon2Params));

    // Launch kernel
    dim3 blockSize(ARGON2_QWORDS_IN_BLOCK);
    dim3 gridSize(params.lanes);
    argon2Kernel<<<gridSize, blockSize>>>(memory, *d_params, password, passwordLength);
    CHECK_CUDA_ERROR(hipGetLastError());
    CHECK_CUDA_ERROR(hipDeviceSynchronize());

    // Print the first block of the final memory state (for demonstration)
    std::cout << "Final memory block (first 8 qwords):" << std::endl;
    for (uint32_t i = 0; i < 8; i++) {
        std::cout << memory[i] << " ";
    }
    std::cout << std::endl;

    // Free memory
    CHECK_CUDA_ERROR(hipFree(password));
    CHECK_CUDA_ERROR(hipFree(memory));
    CHECK_CUDA_ERROR(hipFree(d_params));

    return 0;
}
	.text
	.file	"cuda_code_051321.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj # -- Begin function _Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj
	.type	_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj,@function
_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj: # @_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rsi, (%rax)
	movq	%rdx, 8(%rax)
	leaq	40(%rsp), %rdx
	movq	%rdi, (%rdx)
	leaq	32(%rsp), %rsi
	movq	%rcx, (%rsi)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rdx, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rcx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12argon2KernelPm12Argon2ParamsPKhj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj, .Lfunc_end0-_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj
	.cfi_endproc
                                        # -- End function
	.globl	_Z14checkCudaError10hipError_tPKci # -- Begin function _Z14checkCudaError10hipError_tPKci
	.type	_Z14checkCudaError10hipError_tPKci,@function
_Z14checkCudaError10hipError_tPKci:     # @_Z14checkCudaError10hipError_tPKci
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB1_2
# %bb.1:
	retq
.LBB1_2:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %r14
	movl	%edi, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r14, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z14checkCudaError10hipError_tPKci, .Lfunc_end1-_Z14checkCudaError10hipError_tPKci
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	1024                            # 0x400
	.long	3                               # 0x3
	.long	4                               # 0x4
	.long	256                             # 0x100
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	16(%rsp), %rbx
	movl	$11, %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$97, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movq	%rsp, %rdi
	movl	$131072, %esi                   # imm = 0x20000
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$98, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	leaq	8(%rsp), %r14
	movl	$16, %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$99, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movq	(%rbx), %rax
	movabsq	$7237970109966541168, %rcx      # imm = 0x64726F7773736170
	movq	%rcx, (%rax)
	movl	$858927460, 7(%rax)             # imm = 0x33323164
	movq	(%r14), %rax
	movaps	.LCPI2_0(%rip), %xmm0           # xmm0 = [1024,3,4,256]
	movups	%xmm0, (%rax)
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	leaq	124(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rax
	movq	(%rax), %rsi
	movq	8(%rax), %rdx
	movq	16(%rsp), %rcx
	movl	$11, %r8d
	callq	_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj
.LBB2_2:
	callq	hipGetLastError
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$109, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	callq	hipDeviceSynchronize
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$110, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$36, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%ebx, %ebx
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movq	(%rsp), %rax
	movq	(%rax,%rbx,8), %rsi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbx
	cmpq	$8, %rbx
	jne	.LBB2_3
# %bb.4:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$120, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$121, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.4, %esi
	movl	%eax, %edi
	movl	$122, %edx
	callq	_Z14checkCudaError10hipError_tPKci
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12argon2KernelPm12Argon2ParamsPKhj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12argon2KernelPm12Argon2ParamsPKhj,@object # @_Z12argon2KernelPm12Argon2ParamsPKhj
	.section	.rodata,"a",@progbits
	.globl	_Z12argon2KernelPm12Argon2ParamsPKhj
	.p2align	3, 0x0
_Z12argon2KernelPm12Argon2ParamsPKhj:
	.quad	_Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj
	.size	_Z12argon2KernelPm12Argon2ParamsPKhj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error at "
	.size	.L.str, 15

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	":"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" - "
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"password123"
	.size	.L.str.3, 12

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"/home/ubuntu/Datasets/hip-codes-80k-from-llm-dedup-disassemble-sm89/cuda_code_051321.hip"
	.size	.L.str.4, 89

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Final memory block (first 8 qwords):"
	.size	.L.str.5, 37

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	" "
	.size	.L.str.6, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12argon2KernelPm12Argon2ParamsPKhj"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__argon2KernelPm12Argon2ParamsPKhj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12argon2KernelPm12Argon2ParamsPKhj
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12argon2KernelPm12Argon2ParamsPKhj ; -- Begin function _Z12argon2KernelPm12Argon2ParamsPKhj
	.globl	_Z12argon2KernelPm12Argon2ParamsPKhj
	.p2align	8
	.type	_Z12argon2KernelPm12Argon2ParamsPKhj,@function
_Z12argon2KernelPm12Argon2ParamsPKhj:   ; @_Z12argon2KernelPm12Argon2ParamsPKhj
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	v_cmp_gt_u32_e64 s0, 0x80, v0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, v1, 7, v0
	v_mov_b32_e32 v3, 0
	v_lshlrev_b64 v[4:5], 3, v[2:3]
	v_mov_b32_e32 v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_store_b64 v[4:5], v[1:2], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_eq_u32 s5, 0
	s_mov_b32 s1, 0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_15
; %bb.3:                                ; %.preheader45.lr.ph
	v_cvt_f32_u32_e32 v2, s6
	s_sub_i32 s8, 0, s6
	v_mov_b32_e32 v4, 0
	v_lshl_add_u32 v11, v0, 3, 16
	v_lshlrev_b32_e32 v1, 7, v1
	v_rcp_iflag_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v3, v1, v0
	v_lshlrev_b64 v[5:6], 3, v[3:4]
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v2, v2
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	v_readfirstlane_b32 s7, v2
	v_mov_b32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s8, s8, s7
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s7, s7, s8
	s_mul_hi_u32 s7, s4, s7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v7, vcc_lo, s2, v2
	s_mul_i32 s8, s7, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v3, vcc_lo
	s_sub_i32 s4, s4, s8
	s_add_i32 s8, s7, 1
	s_sub_i32 s9, s4, s6
	s_cmp_ge_u32 s4, s6
	s_cselect_b32 s7, s8, s7
	s_cselect_b32 s4, s9, s4
	s_add_i32 s8, s7, 1
	s_cmp_ge_u32 s4, s6
	s_cselect_b32 s6, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s4, s6, 2
	s_cmp_gt_u32 s6, 3
	s_cselect_b32 s6, -1, 0
.LBB0_4:                                ; %.preheader45
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;         Child Loop BB0_11 Depth 4
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;         Child Loop BB0_11 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_13
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 s8, s7, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s8, 0
	s_mov_b32 s8, 0
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v3, 0, v1, vcc_lo
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
.LBB0_7:                                ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_9 Depth 4
                                        ;         Child Loop BB0_11 Depth 4
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_12
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v10, v3 :: v_dual_mov_b32 v9, v2
	s_mov_b32 s10, 0
.LBB0_9:                                ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b64 v[12:13], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_add_i32 s11, s10, 16
	s_add_i32 s10, s10, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s10, 0x400
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[12:13], s11
	s_cbranch_scc0 .LBB0_9
; %bb.10:                               ;   in Loop: Header=BB0_7 Depth=3
	global_load_b64 v[9:10], v[5:6], off
	scratch_load_b64 v[12:13], v11, off
	s_mov_b32 s10, 0
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v13, v13, v10
	v_xor_b32_e32 v12, v12, v9
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	scratch_store_b64 v11, v[12:13], off
.LBB0_11:                               ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_7 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_add_i32 s11, s10, 16
	s_add_i32 s10, s10, 8
	scratch_load_b64 v[12:13], off, s11
	s_cmpk_eq_i32 s10, 0x400
	s_waitcnt vmcnt(0)
	global_store_b64 v[9:10], v[12:13], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_cbranch_scc0 .LBB0_11
.LBB0_12:                               ; %Flow
                                        ;   in Loop: Header=BB0_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s8, s8, 1
	s_waitcnt_vscnt null, 0x0
	s_cmp_ge_u32 s8, s4
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_7
.LBB0_13:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, 4
	s_cbranch_scc0 .LBB0_5
; %bb.14:                               ;   in Loop: Header=BB0_4 Depth=1
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, s5
	s_cbranch_scc0 .LBB0_4
.LBB0_15:                               ; %._crit_edge51
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12argon2KernelPm12Argon2ParamsPKhj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 1040
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12argon2KernelPm12Argon2ParamsPKhj, .Lfunc_end0-_Z12argon2KernelPm12Argon2ParamsPKhj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 644
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 1040
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           16
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12argon2KernelPm12Argon2ParamsPKhj
    .private_segment_fixed_size: 1040
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12argon2KernelPm12Argon2ParamsPKhj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
