#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>

// Define the number of parameters and GPUs
#define NUM_PARAMETERS 1024
#define NUM_GPUS 2

// Kernel to perform gradient descent update
__global__ void gradientDescentUpdate(float* parameters, float* gradients, float learningRate, int numParams) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numParams) {
        parameters[idx] -= learningRate * gradients[idx];
    }
}

// Initialize random parameters and gradients
void initializeData(float* parameters, float* gradients, int numParams) {
    curandGenerator_t gen;
    curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
    curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);

    curandGenerateUniform(gen, parameters, numParams);
    curandGenerateNormal(gen, gradients, numParams, 0.0f, 1.0f);

    curandDestroyGenerator(gen);
}

int main() {
    // Parameters and gradients for each GPU
    float* h_parameters[NUM_GPUS];
    float* h_gradients[NUM_GPUS];
    float* d_parameters[NUM_GPUS];
    float* d_gradients[NUM_GPUS];

    int numParamsPerGPU = NUM_PARAMETERS / NUM_GPUS;
    float learningRate = 0.01f;

    // Allocate host memory
    for (int i = 0; i < NUM_GPUS; ++i) {
        cudaSetDevice(i);
        cudaMallocHost((void**)&h_parameters[i], numParamsPerGPU * sizeof(float));
        cudaMallocHost((void**)&h_gradients[i], numParamsPerGPU * sizeof(float));
        initializeData(h_parameters[i], h_gradients[i], numParamsPerGPU);
    }

    // Allocate device memory
    for (int i = 0; i < NUM_GPUS; ++i) {
        cudaSetDevice(i);
        cudaMalloc((void**)&d_parameters[i], numParamsPerGPU * sizeof(float));
        cudaMalloc((void**)&d_gradients[i], numParamsPerGPU * sizeof(float));
    }

    // Asynchronous memory copies and kernel launches
    cudaStream_t streams[NUM_GPUS];
    for (int i = 0; i < NUM_GPUS; ++i) {
        cudaSetDevice(i);
        cudaStreamCreate(&streams[i]);
        cudaMemcpyAsync(d_parameters[i], h_parameters[i], numParamsPerGPU * sizeof(float), cudaMemcpyHostToDevice, streams[i]);
        cudaMemcpyAsync(d_gradients[i], h_gradients[i], numParamsPerGPU * sizeof(float), cudaMemcpyHostToDevice, streams[i]);
    }

    // Launch kernels
    int blockSize = 256;
    int numBlocks = (numParamsPerGPU + blockSize - 1) / blockSize;
    for (int i = 0; i < NUM_GPUS; ++i) {
        cudaSetDevice(i);
        gradientDescentUpdate<<<numBlocks, blockSize, 0, streams[i]>>>(d_parameters[i], d_gradients[i], learningRate, numParamsPerGPU);
    }

    // Copy results back to host
    for (int i = 0; i < NUM_GPUS; ++i) {
        cudaSetDevice(i);
        cudaMemcpyAsync(h_parameters[i], d_parameters[i], numParamsPerGPU * sizeof(float), cudaMemcpyDeviceToHost, streams[i]);
    }

    // Synchronize and clean up
    for (int i = 0; i < NUM_GPUS; ++i) {
        cudaSetDevice(i);
        cudaStreamSynchronize(streams[i]);
        cudaStreamDestroy(streams[i]);
        cudaFree(d_parameters[i]);
        cudaFree(d_gradients[i]);
        cudaFreeHost(h_parameters[i]);
        cudaFreeHost(h_gradients[i]);
    }

    std::cout << "Gradient descent completed successfully on " << NUM_GPUS << " GPUs." << std::endl;

    return 0;
}
	.file	"tmpxft_00122d10_00000000-6_cuda_code_028703.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3853:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3853:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14initializeDataPfS_i
	.type	_Z14initializeDataPfS_i, @function
_Z14initializeDataPfS_i:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	movl	$100, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movslq	%edx, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	curandCreateGenerator@PLT
	movq	(%rsp), %rdi
	movl	$1234, %esi
	call	curandSetPseudoRandomGeneratorSeed@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r12, %rsi
	call	curandGenerateUniform@PLT
	movq	(%rsp), %rdi
	xorps	%xmm0, %xmm0
	movq	%rbx, %rdx
	movss	.LC0(%rip), %xmm1
	movq	%rbp, %rsi
	call	curandGenerateNormal@PLT
	movq	(%rsp), %rdi
	call	curandDestroyGenerator@PLT
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L3
	call	__stack_chk_fail@PLT
.L3:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	_Z14initializeDataPfS_i, .-_Z14initializeDataPfS_i
	.globl	_Z45__device_stub__Z21gradientDescentUpdatePfS_fiPfS_fi
	.type	_Z45__device_stub__Z21gradientDescentUpdatePfS_fiPfS_fi, @function
_Z45__device_stub__Z21gradientDescentUpdatePfS_fiPfS_fi:
.LFB3875:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21gradientDescentUpdatePfS_fi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L6:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3875:
	.size	_Z45__device_stub__Z21gradientDescentUpdatePfS_fiPfS_fi, .-_Z45__device_stub__Z21gradientDescentUpdatePfS_fiPfS_fi
	.globl	_Z21gradientDescentUpdatePfS_fi
	.type	_Z21gradientDescentUpdatePfS_fi, @function
_Z21gradientDescentUpdatePfS_fi:
.LFB3876:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z21gradientDescentUpdatePfS_fiPfS_fi
	.cfi_endproc
.LFE3876:
	.size	_Z21gradientDescentUpdatePfS_fi, .-_Z21gradientDescentUpdatePfS_fi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"Gradient descent completed successfully on "
.LC4:
	.string	" GPUs."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3850:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %r14
	leaq	72(%rsp), %r12
	call	cudaSetDevice@PLT
	movl	$2048, %esi
	movq	%r14, %rdi
	leaq	88(%rsp), %rbp
	call	cudaMallocHost@PLT
	leaq	56(%rsp), %rax
	movl	$2048, %esi
	leaq	104(%rsp), %rbx
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	movq	%rbx, %r15
	call	cudaMallocHost@PLT
	movq	56(%rsp), %rsi
	movq	40(%rsp), %rdi
	movl	$512, %edx
	call	_Z14initializeDataPfS_i
	movl	$1, %edi
	call	cudaSetDevice@PLT
	leaq	48(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMallocHost@PLT
	leaq	64(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMallocHost@PLT
	movq	64(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	$512, %edx
	call	_Z14initializeDataPfS_i
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	movl	$2048, %esi
	movq	%r12, %rdi
	call	cudaMalloc@PLT
	movl	$2048, %esi
	movq	%rbp, %rdi
	call	cudaMalloc@PLT
	movl	$1, %edi
	call	cudaSetDevice@PLT
	leaq	80(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	leaq	96(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
.L12:
	movl	%r13d, %edi
	call	cudaSetDevice@PLT
	movq	%rbx, %rdi
	addq	$8, %rbx
	call	cudaStreamCreate@PLT
	movq	-8(%rbx), %r8
	movq	(%r14,%r13,8), %rsi
	movl	$1, %ecx
	movq	(%r12,%r13,8), %rdi
	movl	$2048, %edx
	call	cudaMemcpyAsync@PLT
	movq	8(%rsp), %rax
	movq	-8(%rbx), %r8
	movl	$1, %ecx
	movq	0(%rbp,%r13,8), %rdi
	movl	$2048, %edx
	movq	(%rax,%r13,8), %rsi
	call	cudaMemcpyAsync@PLT
	testq	%r13, %r13
	jne	.L21
	movl	$1, %r13d
	jmp	.L12
.L21:
	xorl	%ebx, %ebx
.L14:
	movl	%ebx, %edi
	call	cudaSetDevice@PLT
	movl	$16777217, %eax
	movl	$2147483649, %edi
	xorl	%r8d, %r8d
	salq	$8, %rax
	movq	(%r15,%rbx,8), %r9
	addq	%rdi, %rdi
	movl	$1, %ecx
	movq	%rax, %rdx
	movl	$1, %esi
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	0(%rbp,%rbx,8), %rsi
	movq	(%r12,%rbx,8), %rdi
	movl	$512, %edx
	movss	.LC2(%rip), %xmm0
	call	_Z45__device_stub__Z21gradientDescentUpdatePfS_fiPfS_fi
.L13:
	testq	%rbx, %rbx
	jne	.L22
	movq	%r13, %rbx
	jmp	.L14
.L22:
	xorl	%edi, %edi
	xorl	%r13d, %r13d
	call	cudaSetDevice@PLT
	movq	104(%rsp), %r8
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	40(%rsp), %rdi
	movl	$2048, %edx
	call	cudaMemcpyAsync@PLT
	movl	$1, %edi
	call	cudaSetDevice@PLT
	movq	112(%rsp), %r8
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movq	48(%rsp), %rdi
	movl	$2048, %edx
	call	cudaMemcpyAsync@PLT
.L15:
	movl	%r13d, %edi
	call	cudaSetDevice@PLT
	movq	(%r15,%r13,8), %rdi
	call	cudaStreamSynchronize@PLT
	movq	(%r15,%r13,8), %rdi
	call	cudaStreamDestroy@PLT
	movq	(%r12,%r13,8), %rdi
	call	cudaFree@PLT
	movq	0(%rbp,%r13,8), %rdi
	call	cudaFree@PLT
	movq	(%r14,%r13,8), %rdi
	call	cudaFreeHost@PLT
	movq	8(%rsp), %rax
	movq	(%rax,%r13,8), %rdi
	call	cudaFreeHost@PLT
	testq	%r13, %r13
	jne	.L23
	movq	%rbx, %r13
	jmp	.L15
.L23:
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$2, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3850:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z21gradientDescentUpdatePfS_fi"
.LC6:
	.string	"precalc_xorwow_matrix"
.LC7:
	.string	"precalc_xorwow_offset_matrix"
.LC8:
	.string	"mrg32k3aM1"
.LC9:
	.string	"mrg32k3aM2"
.LC10:
	.string	"mrg32k3aM1SubSeq"
.LC11:
	.string	"mrg32k3aM2SubSeq"
.LC12:
	.string	"mrg32k3aM1Seq"
.LC13:
	.string	"mrg32k3aM2Seq"
.LC14:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3878:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21gradientDescentUpdatePfS_fi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3878:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC2:
	.long	1008981770
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

// Define the number of parameters and GPUs
#define NUM_PARAMETERS 1024
#define NUM_GPUS 2

// Kernel to perform gradient descent update
__global__ void gradientDescentUpdate(float* parameters, float* gradients, float learningRate, int numParams) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < numParams) {
        parameters[idx] -= learningRate * gradients[idx];
    }
}

// Initialize random parameters and gradients
void initializeData(float* parameters, float* gradients, int numParams) {
    hiprandGenerator_t gen;
    hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
    hiprandSetPseudoRandomGeneratorSeed(gen, 1234ULL);

    hiprandGenerateUniform(gen, parameters, numParams);
    hiprandGenerateNormal(gen, gradients, numParams, 0.0f, 1.0f);

    hiprandDestroyGenerator(gen);
}

int main() {
    // Parameters and gradients for each GPU
    float* h_parameters[NUM_GPUS];
    float* h_gradients[NUM_GPUS];
    float* d_parameters[NUM_GPUS];
    float* d_gradients[NUM_GPUS];

    int numParamsPerGPU = NUM_PARAMETERS / NUM_GPUS;
    float learningRate = 0.01f;

    // Allocate host memory
    for (int i = 0; i < NUM_GPUS; ++i) {
        hipSetDevice(i);
        hipHostMalloc((void**)&h_parameters[i], numParamsPerGPU * sizeof(float), hipHostMallocDefault);
        hipHostMalloc((void**)&h_gradients[i], numParamsPerGPU * sizeof(float), hipHostMallocDefault);
        initializeData(h_parameters[i], h_gradients[i], numParamsPerGPU);
    }

    // Allocate device memory
    for (int i = 0; i < NUM_GPUS; ++i) {
        hipSetDevice(i);
        hipMalloc((void**)&d_parameters[i], numParamsPerGPU * sizeof(float));
        hipMalloc((void**)&d_gradients[i], numParamsPerGPU * sizeof(float));
    }

    // Asynchronous memory copies and kernel launches
    hipStream_t streams[NUM_GPUS];
    for (int i = 0; i < NUM_GPUS; ++i) {
        hipSetDevice(i);
        hipStreamCreate(&streams[i]);
        hipMemcpyAsync(d_parameters[i], h_parameters[i], numParamsPerGPU * sizeof(float), hipMemcpyHostToDevice, streams[i]);
        hipMemcpyAsync(d_gradients[i], h_gradients[i], numParamsPerGPU * sizeof(float), hipMemcpyHostToDevice, streams[i]);
    }

    // Launch kernels
    int blockSize = 256;
    int numBlocks = (numParamsPerGPU + blockSize - 1) / blockSize;
    for (int i = 0; i < NUM_GPUS; ++i) {
        hipSetDevice(i);
        gradientDescentUpdate<<<numBlocks, blockSize, 0, streams[i]>>>(d_parameters[i], d_gradients[i], learningRate, numParamsPerGPU);
    }

    // Copy results back to host
    for (int i = 0; i < NUM_GPUS; ++i) {
        hipSetDevice(i);
        hipMemcpyAsync(h_parameters[i], d_parameters[i], numParamsPerGPU * sizeof(float), hipMemcpyDeviceToHost, streams[i]);
    }

    // Synchronize and clean up
    for (int i = 0; i < NUM_GPUS; ++i) {
        hipSetDevice(i);
        hipStreamSynchronize(streams[i]);
        hipStreamDestroy(streams[i]);
        hipFree(d_parameters[i]);
        hipFree(d_gradients[i]);
        hipHostFree(h_parameters[i]);
        hipHostFree(h_gradients[i]);
    }

    std::cout << "Gradient descent completed successfully on " << NUM_GPUS << " GPUs." << std::endl;

    return 0;
}
	.text
	.file	"cuda_code_028703.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z36__device_stub__gradientDescentUpdatePfS_fi # -- Begin function _Z36__device_stub__gradientDescentUpdatePfS_fi
	.type	_Z36__device_stub__gradientDescentUpdatePfS_fi,@function
_Z36__device_stub__gradientDescentUpdatePfS_fi: # @_Z36__device_stub__gradientDescentUpdatePfS_fi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	8(%rsp), %rdi
	movl	%edx, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21gradientDescentUpdatePfS_fi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__gradientDescentUpdatePfS_fi, .Lfunc_end0-_Z36__device_stub__gradientDescentUpdatePfS_fi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z14initializeDataPfS_i
.LCPI1_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	_Z14initializeDataPfS_i
	.type	_Z14initializeDataPfS_i,@function
_Z14initializeDataPfS_i:                # @_Z14initializeDataPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %r14
	movq	%rdi, %r15
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hiprandCreateGenerator
	movq	(%rbx), %rdi
	movl	$1234, %esi                     # imm = 0x4D2
	callq	hiprandSetPseudoRandomGeneratorSeed
	movq	(%rbx), %rdi
	movslq	%ebp, %r12
	movq	%r15, %rsi
	movq	%r12, %rdx
	callq	hiprandGenerateUniform
	movq	(%rbx), %rdi
	movss	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	movq	%r14, %rsi
	movq	%r12, %rdx
	callq	hiprandGenerateNormal
	movq	(%rbx), %rdi
	callq	hiprandDestroyGenerator
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z14initializeDataPfS_i, .Lfunc_end1-_Z14initializeDataPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x3c23d70a                      # float 0.00999999977
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:                                # %.preheader69.preheader.critedge
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	hipSetDevice
	leaq	32(%rsp), %r14
	movl	$2048, %esi                     # imm = 0x800
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	64(%rsp), %r15
	movl	$2048, %esi                     # imm = 0x800
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	(%r14), %rdi
	movq	(%r15), %rsi
	movl	$512, %edx                      # imm = 0x200
	callq	_Z14initializeDataPfS_i
	movl	$1, %edi
	callq	hipSetDevice
	leaq	40(%rsp), %r14
	movl	$2048, %esi                     # imm = 0x800
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	72(%rsp), %r15
	movl	$2048, %esi                     # imm = 0x800
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	(%r14), %rdi
	movq	(%r15), %rsi
	movl	$512, %edx                      # imm = 0x200
	callq	_Z14initializeDataPfS_i
	xorl	%edi, %edi
	callq	hipSetDevice
	movq	%rsp, %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movl	$1, %edi
	callq	hipSetDevice
	leaq	8(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	movb	$1, %bpl
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	hipSetDevice
	leaq	(%rsp,%rbx,8), %r14
	addq	$16, %r14
	movq	%r14, %rdi
	callq	hipStreamCreate
	movq	(%rsp,%rbx,8), %rdi
	movq	32(%rsp,%rbx,8), %rsi
	movq	(%r14), %r8
	movl	$2048, %edx                     # imm = 0x800
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	48(%rsp,%rbx,8), %rdi
	movq	64(%rsp,%rbx,8), %rsi
	movq	(%r14), %r8
	movl	$2048, %edx                     # imm = 0x800
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movl	$1, %ebx
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB2_1
# %bb.2:                                # %.preheader68.preheader
	movb	$1, %bpl
	movabsq	$4294967298, %rbx               # imm = 0x100000002
	xorl	%r15d, %r15d
	leaq	254(%rbx), %r14
.LBB2_3:                                # %.preheader68
                                        # =>This Inner Loop Header: Depth=1
	movl	%r15d, %edi
	callq	hipSetDevice
	movq	16(%rsp,%r15,8), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_3 Depth=1
	movq	(%rsp,%r15,8), %rdi
	movq	48(%rsp,%r15,8), %rsi
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$512, %edx                      # imm = 0x200
	callq	_Z36__device_stub__gradientDescentUpdatePfS_fi
.LBB2_5:                                #   in Loop: Header=BB2_3 Depth=1
	movl	$1, %r15d
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB2_3
# %bb.6:                                # %.preheader67
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	hipSetDevice
	movq	32(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	16(%rsp), %r8
	movl	$2048, %edx                     # imm = 0x800
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movl	$1, %edi
	callq	hipSetDevice
	movq	40(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	24(%rsp), %r8
	movl	$2048, %edx                     # imm = 0x800
	movl	$2, %ecx
	callq	hipMemcpyAsync
	movb	$1, %bpl
.LBB2_7:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	hipSetDevice
	movq	16(%rsp,%rbx,8), %rdi
	callq	hipStreamSynchronize
	movq	16(%rsp,%rbx,8), %rdi
	callq	hipStreamDestroy
	movq	(%rsp,%rbx,8), %rdi
	callq	hipFree
	movq	48(%rsp,%rbx,8), %rdi
	callq	hipFree
	movq	32(%rsp,%rbx,8), %rdi
	callq	hipHostFree
	movq	64(%rsp,%rbx,8), %rdi
	callq	hipHostFree
	movl	$1, %ebx
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB2_7
# %bb.8:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$43, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$2, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$6, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21gradientDescentUpdatePfS_fi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21gradientDescentUpdatePfS_fi,@object # @_Z21gradientDescentUpdatePfS_fi
	.section	.rodata,"a",@progbits
	.globl	_Z21gradientDescentUpdatePfS_fi
	.p2align	3, 0x0
_Z21gradientDescentUpdatePfS_fi:
	.quad	_Z36__device_stub__gradientDescentUpdatePfS_fi
	.size	_Z21gradientDescentUpdatePfS_fi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Gradient descent completed successfully on "
	.size	.L.str, 44

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" GPUs."
	.size	.L.str.1, 7

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21gradientDescentUpdatePfS_fi"
	.size	.L__unnamed_1, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__gradientDescentUpdatePfS_fi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21gradientDescentUpdatePfS_fi
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21gradientDescentUpdatePfS_fi ; -- Begin function _Z21gradientDescentUpdatePfS_fi
	.globl	_Z21gradientDescentUpdatePfS_fi
	.p2align	8
	.type	_Z21gradientDescentUpdatePfS_fi,@function
_Z21gradientDescentUpdatePfS_fi:        ; @_Z21gradientDescentUpdatePfS_fi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v2, -v2, s2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21gradientDescentUpdatePfS_fi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21gradientDescentUpdatePfS_fi, .Lfunc_end0-_Z21gradientDescentUpdatePfS_fi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21gradientDescentUpdatePfS_fi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21gradientDescentUpdatePfS_fi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
