#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#include <cmath>

#define NUM_POINTS 2048
#define NUM_DIMS 5
#define NUM_CLUSTERS 8
#define MAX_ITERATIONS 100
#define EPSILON 1e-4

__device__ float euclidean_distance(const float* a, const float* b, int dims) {
    float dist = 0.0f;
    for (int i = 0; i < dims; ++i) {
        float diff = a[i] - b[i];
        dist += diff * diff;
    }
    return sqrtf(dist);
}

__global__ void initialize_clusters(float* clusters, int num_clusters, int num_dims) {
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    if (idx < num_clusters * num_dims) {
        curandState state;
        curand_init((unsigned long long)clock() + idx, 0, 0, &state);
        clusters[idx] = curand_uniform(&state) * 10.0f; // Random value between 0 and 10
    }
}

__global__ void assign_clusters(float* points, float* clusters, int* labels, int num_points, int num_clusters, int num_dims) {
    extern __shared__ float shared_clusters[];

    // Load clusters into shared memory
    int cluster_idx = threadIdx.x;
    while (cluster_idx < num_clusters * num_dims) {
        shared_clusters[cluster_idx] = clusters[cluster_idx];
        cluster_idx += blockDim.x;
    }
    __syncthreads();

    int point_idx = blockIdx.x;
    if (point_idx < num_points) {
        float min_dist = INFINITY;
        int closest_cluster = -1;
        for (int c = 0; c < num_clusters; ++c) {
            float dist = euclidean_distance(&points[point_idx * num_dims], &shared_clusters[c * num_dims], num_dims);
            if (dist < min_dist) {
                min_dist = dist;
                closest_cluster = c;
            }
        }
        labels[point_idx] = closest_cluster;
    }
}

__global__ void update_clusters(float* points, float* clusters, int* labels, int num_points, int num_clusters, int num_dims) {
    extern __shared__ float shared_clusters[];

    // Initialize shared memory for new cluster centers
    int cluster_idx = threadIdx.x;
    while (cluster_idx < num_clusters * num_dims) {
        shared_clusters[cluster_idx] = 0.0f;
        cluster_idx += blockDim.x;
    }
    __syncthreads();

    int point_idx = blockIdx.x;
    if (point_idx < num_points) {
        int cluster_id = labels[point_idx];
        atomicAdd(&shared_clusters[cluster_id * num_dims + 0], points[point_idx * num_dims + 0]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 1], points[point_idx * num_dims + 1]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 2], points[point_idx * num_dims + 2]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 3], points[point_idx * num_dims + 3]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 4], points[point_idx * num_dims + 4]);
    }
    __syncthreads();

    // Count number of points per cluster
    int count_idx = threadIdx.x;
    while (count_idx < num_clusters) {
        atomicAdd(&shared_clusters[count_idx * num_dims + 5], 1);
        count_idx += blockDim.x;
    }
    __syncthreads();

    // Update cluster centers
    if (threadIdx.x < num_clusters * num_dims) {
        int cluster_id = threadIdx.x / num_dims;
        int dim = threadIdx.x % num_dims;
        int count = shared_clusters[cluster_id * num_dims + 5];
        if (count > 0) {
            clusters[threadIdx.x] = shared_clusters[threadIdx.x] / count;
        }
    }
}

int main() {
    float* d_points;
    float* d_clusters;
    int* d_labels;
    float* h_points = new float[NUM_POINTS * NUM_DIMS];
    float* h_clusters = new float[NUM_CLUSTERS * NUM_DIMS];
    int* h_labels = new int[NUM_POINTS];

    // Initialize points with random values
    curandGenerator_t gen;
    curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
    curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
    curandGenerateUniform(gen, h_points, NUM_POINTS * NUM_DIMS);
    curandDestroyGenerator(gen);

    // Allocate device memory
    cudaMalloc((void**)&d_points, NUM_POINTS * NUM_DIMS * sizeof(float));
    cudaMalloc((void**)&d_clusters, NUM_CLUSTERS * NUM_DIMS * sizeof(float));
    cudaMalloc((void**)&d_labels, NUM_POINTS * sizeof(int));

    // Copy points to device
    cudaMemcpy(d_points, h_points, NUM_POINTS * NUM_DIMS * sizeof(float), cudaMemcpyHostToDevice);

    // Initialize clusters
    int block_size = 256;
    int grid_size = (NUM_CLUSTERS * NUM_DIMS + block_size - 1) / block_size;
    initialize_clusters<<<grid_size, block_size>>>(d_clusters, NUM_CLUSTERS, NUM_DIMS);
    cudaDeviceSynchronize();

    // K-means iterations
    for (int iter = 0; iter < MAX_ITERATIONS; ++iter) {
        // Assign clusters
        block_size = 256;
        grid_size = NUM_POINTS;
        assign_clusters<<<grid_size, block_size, NUM_CLUSTERS * NUM_DIMS * sizeof(float)>>>(d_points, d_clusters, d_labels, NUM_POINTS, NUM_CLUSTERS, NUM_DIMS);
        cudaDeviceSynchronize();

        // Update clusters
        update_clusters<<<grid_size, block_size, NUM_CLUSTERS * (NUM_DIMS + 1) * sizeof(float)>>>(d_points, d_clusters, d_labels, NUM_POINTS, NUM_CLUSTERS, NUM_DIMS);
        cudaDeviceSynchronize();
    }

    // Copy clusters and labels back to host
    cudaMemcpy(h_clusters, d_clusters, NUM_CLUSTERS * NUM_DIMS * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_labels, d_labels, NUM_POINTS * sizeof(int), cudaMemcpyDeviceToHost);

    // Clean up
    cudaFree(d_points);
    cudaFree(d_clusters);
    cudaFree(d_labels);
    delete[] h_points;
    delete[] h_clusters;
    delete[] h_labels;

    return 0;
}
	.file	"tmpxft_000d525f_00000000-6_cuda_code_046011.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3853:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3853:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z18euclidean_distancePKfS0_i
	.type	_Z18euclidean_distancePKfS0_i, @function
_Z18euclidean_distancePKfS0_i:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3849:
	.size	_Z18euclidean_distancePKfS0_i, .-_Z18euclidean_distancePKfS0_i
	.globl	_Z41__device_stub__Z19initialize_clustersPfiiPfii
	.type	_Z41__device_stub__Z19initialize_clustersPfiiPfii, @function
_Z41__device_stub__Z19initialize_clustersPfiiPfii:
.LFB3875:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z19initialize_clustersPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3875:
	.size	_Z41__device_stub__Z19initialize_clustersPfiiPfii, .-_Z41__device_stub__Z19initialize_clustersPfiiPfii
	.globl	_Z19initialize_clustersPfii
	.type	_Z19initialize_clustersPfii, @function
_Z19initialize_clustersPfii:
.LFB3876:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z19initialize_clustersPfiiPfii
	.cfi_endproc
.LFE3876:
	.size	_Z19initialize_clustersPfii, .-_Z19initialize_clustersPfii
	.globl	_Z42__device_stub__Z15assign_clustersPfS_PiiiiPfS_Piiii
	.type	_Z42__device_stub__Z15assign_clustersPfS_PiiiiPfS_Piiii, @function
_Z42__device_stub__Z15assign_clustersPfS_PiiiiPfS_Piiii:
.LFB3877:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15assign_clustersPfS_Piiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L10:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3877:
	.size	_Z42__device_stub__Z15assign_clustersPfS_PiiiiPfS_Piiii, .-_Z42__device_stub__Z15assign_clustersPfS_PiiiiPfS_Piiii
	.globl	_Z15assign_clustersPfS_Piiii
	.type	_Z15assign_clustersPfS_Piiii, @function
_Z15assign_clustersPfS_Piiii:
.LFB3878:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z15assign_clustersPfS_PiiiiPfS_Piiii
	.cfi_endproc
.LFE3878:
	.size	_Z15assign_clustersPfS_Piiii, .-_Z15assign_clustersPfS_Piiii
	.globl	_Z42__device_stub__Z15update_clustersPfS_PiiiiPfS_Piiii
	.type	_Z42__device_stub__Z15update_clustersPfS_PiiiiPfS_Piiii, @function
_Z42__device_stub__Z15update_clustersPfS_PiiiiPfS_Piiii:
.LFB3879:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15update_clustersPfS_Piiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L15:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3879:
	.size	_Z42__device_stub__Z15update_clustersPfS_PiiiiPfS_Piiii, .-_Z42__device_stub__Z15update_clustersPfS_PiiiiPfS_Piiii
	.globl	_Z15update_clustersPfS_Piiii
	.type	_Z15update_clustersPfS_Piiii, @function
_Z15update_clustersPfS_Piiii:
.LFB3880:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z15update_clustersPfS_PiiiiPfS_Piiii
	.cfi_endproc
.LFE3880:
	.size	_Z15update_clustersPfS_Piiii, .-_Z15update_clustersPfS_Piiii
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3850:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$40960, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$160, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movl	$8192, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	leaq	24(%rsp), %rdi
	movl	$100, %esi
	movq	%rax, %rbp
	call	curandCreateGenerator@PLT
	movq	24(%rsp), %rdi
	movl	$1234, %esi
	call	curandSetPseudoRandomGeneratorSeed@PLT
	movq	24(%rsp), %rdi
	movl	$10240, %edx
	movq	%rbx, %rsi
	call	curandGenerateUniform@PLT
	movq	24(%rsp), %rdi
	call	curandDestroyGenerator@PLT
	movq	%rsp, %rdi
	movl	$40960, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$160, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$8192, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$40960, %edx
	call	cudaMemcpy@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	8(%rsp), %rdi
	movl	$5, %edx
	movl	$8, %esi
	call	_Z41__device_stub__Z19initialize_clustersPfiiPfii
.L21:
	call	cudaDeviceSynchronize@PLT
	movl	$100, %r15d
	movabsq	$4294967552, %r13
	movabsq	$4294969344, %r14
.L24:
	xorl	%r9d, %r9d
	movl	$160, %r8d
	movq	%r13, %rdx
	movq	%r14, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r13, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%r14, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$5, %r9d
	movl	$8, %r8d
	movq	(%rsp), %rdi
	movl	$2048, %ecx
	call	_Z42__device_stub__Z15assign_clustersPfS_PiiiiPfS_Piiii
.L22:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	movq	%r13, %rdx
	movl	$1, %ecx
	movl	$192, %r8d
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%r14, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$5, %r9d
	movl	$8, %r8d
	movq	(%rsp), %rdi
	movl	$2048, %ecx
	call	_Z42__device_stub__Z15update_clustersPfS_PiiiiPfS_Piiii
.L23:
	call	cudaDeviceSynchronize@PLT
	decl	%r15d
	jne	.L24
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$160, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$8192, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3850:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15update_clustersPfS_Piiii"
.LC1:
	.string	"_Z15assign_clustersPfS_Piiii"
.LC2:
	.string	"_Z19initialize_clustersPfii"
.LC3:
	.string	"precalc_xorwow_matrix"
.LC4:
	.string	"precalc_xorwow_offset_matrix"
.LC5:
	.string	"mrg32k3aM1"
.LC6:
	.string	"mrg32k3aM2"
.LC7:
	.string	"mrg32k3aM1SubSeq"
.LC8:
	.string	"mrg32k3aM2SubSeq"
.LC9:
	.string	"mrg32k3aM1Seq"
.LC10:
	.string	"mrg32k3aM2Seq"
.LC11:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3882:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15update_clustersPfS_Piiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15assign_clustersPfS_Piiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z19initialize_clustersPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3882:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <cmath>

#define NUM_POINTS 2048
#define NUM_DIMS 5
#define NUM_CLUSTERS 8
#define MAX_ITERATIONS 100
#define EPSILON 1e-4

__device__ float euclidean_distance(const float* a, const float* b, int dims) {
    float dist = 0.0f;
    for (int i = 0; i < dims; ++i) {
        float diff = a[i] - b[i];
        dist += diff * diff;
    }
    return sqrtf(dist);
}

__global__ void initialize_clusters(float* clusters, int num_clusters, int num_dims) {
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    if (idx < num_clusters * num_dims) {
        hiprandState state;
        hiprand_init((unsigned long long)clock() + idx, 0, 0, &state);
        clusters[idx] = hiprand_uniform(&state) * 10.0f; // Random value between 0 and 10
    }
}

__global__ void assign_clusters(float* points, float* clusters, int* labels, int num_points, int num_clusters, int num_dims) {
    extern __shared__ float shared_clusters[];

    // Load clusters into shared memory
    int cluster_idx = threadIdx.x;
    while (cluster_idx < num_clusters * num_dims) {
        shared_clusters[cluster_idx] = clusters[cluster_idx];
        cluster_idx += blockDim.x;
    }
    __syncthreads();

    int point_idx = blockIdx.x;
    if (point_idx < num_points) {
        float min_dist = INFINITY;
        int closest_cluster = -1;
        for (int c = 0; c < num_clusters; ++c) {
            float dist = euclidean_distance(&points[point_idx * num_dims], &shared_clusters[c * num_dims], num_dims);
            if (dist < min_dist) {
                min_dist = dist;
                closest_cluster = c;
            }
        }
        labels[point_idx] = closest_cluster;
    }
}

__global__ void update_clusters(float* points, float* clusters, int* labels, int num_points, int num_clusters, int num_dims) {
    extern __shared__ float shared_clusters[];

    // Initialize shared memory for new cluster centers
    int cluster_idx = threadIdx.x;
    while (cluster_idx < num_clusters * num_dims) {
        shared_clusters[cluster_idx] = 0.0f;
        cluster_idx += blockDim.x;
    }
    __syncthreads();

    int point_idx = blockIdx.x;
    if (point_idx < num_points) {
        int cluster_id = labels[point_idx];
        atomicAdd(&shared_clusters[cluster_id * num_dims + 0], points[point_idx * num_dims + 0]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 1], points[point_idx * num_dims + 1]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 2], points[point_idx * num_dims + 2]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 3], points[point_idx * num_dims + 3]);
        atomicAdd(&shared_clusters[cluster_id * num_dims + 4], points[point_idx * num_dims + 4]);
    }
    __syncthreads();

    // Count number of points per cluster
    int count_idx = threadIdx.x;
    while (count_idx < num_clusters) {
        atomicAdd(&shared_clusters[count_idx * num_dims + 5], 1);
        count_idx += blockDim.x;
    }
    __syncthreads();

    // Update cluster centers
    if (threadIdx.x < num_clusters * num_dims) {
        int cluster_id = threadIdx.x / num_dims;
        int dim = threadIdx.x % num_dims;
        int count = shared_clusters[cluster_id * num_dims + 5];
        if (count > 0) {
            clusters[threadIdx.x] = shared_clusters[threadIdx.x] / count;
        }
    }
}

int main() {
    float* d_points;
    float* d_clusters;
    int* d_labels;
    float* h_points = new float[NUM_POINTS * NUM_DIMS];
    float* h_clusters = new float[NUM_CLUSTERS * NUM_DIMS];
    int* h_labels = new int[NUM_POINTS];

    // Initialize points with random values
    hiprandGenerator_t gen;
    hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
    hiprandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
    hiprandGenerateUniform(gen, h_points, NUM_POINTS * NUM_DIMS);
    hiprandDestroyGenerator(gen);

    // Allocate device memory
    hipMalloc((void**)&d_points, NUM_POINTS * NUM_DIMS * sizeof(float));
    hipMalloc((void**)&d_clusters, NUM_CLUSTERS * NUM_DIMS * sizeof(float));
    hipMalloc((void**)&d_labels, NUM_POINTS * sizeof(int));

    // Copy points to device
    hipMemcpy(d_points, h_points, NUM_POINTS * NUM_DIMS * sizeof(float), hipMemcpyHostToDevice);

    // Initialize clusters
    int block_size = 256;
    int grid_size = (NUM_CLUSTERS * NUM_DIMS + block_size - 1) / block_size;
    initialize_clusters<<<grid_size, block_size>>>(d_clusters, NUM_CLUSTERS, NUM_DIMS);
    hipDeviceSynchronize();

    // K-means iterations
    for (int iter = 0; iter < MAX_ITERATIONS; ++iter) {
        // Assign clusters
        block_size = 256;
        grid_size = NUM_POINTS;
        assign_clusters<<<grid_size, block_size, NUM_CLUSTERS * NUM_DIMS * sizeof(float)>>>(d_points, d_clusters, d_labels, NUM_POINTS, NUM_CLUSTERS, NUM_DIMS);
        hipDeviceSynchronize();

        // Update clusters
        update_clusters<<<grid_size, block_size, NUM_CLUSTERS * (NUM_DIMS + 1) * sizeof(float)>>>(d_points, d_clusters, d_labels, NUM_POINTS, NUM_CLUSTERS, NUM_DIMS);
        hipDeviceSynchronize();
    }

    // Copy clusters and labels back to host
    hipMemcpy(h_clusters, d_clusters, NUM_CLUSTERS * NUM_DIMS * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_labels, d_labels, NUM_POINTS * sizeof(int), hipMemcpyDeviceToHost);

    // Clean up
    hipFree(d_points);
    hipFree(d_clusters);
    hipFree(d_labels);
    delete[] h_points;
    delete[] h_clusters;
    delete[] h_labels;

    return 0;
}
	.text
	.file	"cuda_code_046011.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z34__device_stub__initialize_clustersPfii # -- Begin function _Z34__device_stub__initialize_clustersPfii
	.type	_Z34__device_stub__initialize_clustersPfii,@function
_Z34__device_stub__initialize_clustersPfii: # @_Z34__device_stub__initialize_clustersPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19initialize_clustersPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__initialize_clustersPfii, .Lfunc_end0-_Z34__device_stub__initialize_clustersPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__assign_clustersPfS_Piiii # -- Begin function _Z30__device_stub__assign_clustersPfS_Piiii
	.type	_Z30__device_stub__assign_clustersPfS_Piiii,@function
_Z30__device_stub__assign_clustersPfS_Piiii: # @_Z30__device_stub__assign_clustersPfS_Piiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15assign_clustersPfS_Piiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__assign_clustersPfS_Piiii, .Lfunc_end1-_Z30__device_stub__assign_clustersPfS_Piiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__update_clustersPfS_Piiii # -- Begin function _Z30__device_stub__update_clustersPfS_Piiii
	.type	_Z30__device_stub__update_clustersPfS_Piiii,@function
_Z30__device_stub__update_clustersPfS_Piiii: # @_Z30__device_stub__update_clustersPfS_Piiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15update_clustersPfS_Piiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z30__device_stub__update_clustersPfS_Piiii, .Lfunc_end2-_Z30__device_stub__update_clustersPfS_Piiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967552, %r12               # imm = 0x100000100
	movl	$40960, %edi                    # imm = 0xA000
	callq	_Znam
	movq	%rax, %rbx
	movl	$160, %edi
	callq	_Znam
	movq	%rax, %r14
	movl	$8192, %edi                     # imm = 0x2000
	callq	_Znam
	movq	%rax, %r15
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hiprandCreateGenerator
	movq	(%r13), %rdi
	movl	$1234, %esi                     # imm = 0x4D2
	callq	hiprandSetPseudoRandomGeneratorSeed
	movq	(%r13), %rdi
	movl	$10240, %edx                    # imm = 0x2800
	movq	%rbx, %rsi
	callq	hiprandGenerateUniform
	movq	(%r13), %rdi
	callq	hiprandDestroyGenerator
	leaq	24(%rsp), %r13
	movl	$40960, %esi                    # imm = 0xA000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$160, %esi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$8192, %esi                     # imm = 0x2000
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$40960, %edx                    # imm = 0xA000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-255(%r12), %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	8(%rsp), %rdi
	movl	$8, %esi
	movl	$5, %edx
	callq	_Z34__device_stub__initialize_clustersPfii
.LBB3_2:
	callq	hipDeviceSynchronize
	movl	$100, %ebp
	leaq	1792(%r12), %r13
.LBB3_3:                                # =>This Inner Loop Header: Depth=1
	movl	$160, %r8d
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_5
# %bb.4:                                #   in Loop: Header=BB3_3 Depth=1
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$2048, %ecx                     # imm = 0x800
	movl	$8, %r8d
	movl	$5, %r9d
	callq	_Z30__device_stub__assign_clustersPfS_Piiii
.LBB3_5:                                #   in Loop: Header=BB3_3 Depth=1
	callq	hipDeviceSynchronize
	movl	$192, %r8d
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_7
# %bb.6:                                #   in Loop: Header=BB3_3 Depth=1
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$2048, %ecx                     # imm = 0x800
	movl	$8, %r8d
	movl	$5, %r9d
	callq	_Z30__device_stub__update_clustersPfS_Piiii
.LBB3_7:                                #   in Loop: Header=BB3_3 Depth=1
	callq	hipDeviceSynchronize
	decl	%ebp
	jne	.LBB3_3
# %bb.8:
	movq	8(%rsp), %rsi
	movl	$160, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movl	$8192, %edx                     # imm = 0x2000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19initialize_clustersPfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15assign_clustersPfS_Piiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15update_clustersPfS_Piiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19initialize_clustersPfii,@object # @_Z19initialize_clustersPfii
	.section	.rodata,"a",@progbits
	.globl	_Z19initialize_clustersPfii
	.p2align	3, 0x0
_Z19initialize_clustersPfii:
	.quad	_Z34__device_stub__initialize_clustersPfii
	.size	_Z19initialize_clustersPfii, 8

	.type	_Z15assign_clustersPfS_Piiii,@object # @_Z15assign_clustersPfS_Piiii
	.globl	_Z15assign_clustersPfS_Piiii
	.p2align	3, 0x0
_Z15assign_clustersPfS_Piiii:
	.quad	_Z30__device_stub__assign_clustersPfS_Piiii
	.size	_Z15assign_clustersPfS_Piiii, 8

	.type	_Z15update_clustersPfS_Piiii,@object # @_Z15update_clustersPfS_Piiii
	.globl	_Z15update_clustersPfS_Piiii
	.p2align	3, 0x0
_Z15update_clustersPfS_Piiii:
	.quad	_Z30__device_stub__update_clustersPfS_Piiii
	.size	_Z15update_clustersPfS_Piiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19initialize_clustersPfii"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15assign_clustersPfS_Piiii"
	.size	.L__unnamed_2, 29

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z15update_clustersPfS_Piiii"
	.size	.L__unnamed_3, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__initialize_clustersPfii
	.addrsig_sym _Z30__device_stub__assign_clustersPfS_Piiii
	.addrsig_sym _Z30__device_stub__update_clustersPfS_Piiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19initialize_clustersPfii
	.addrsig_sym _Z15assign_clustersPfS_Piiii
	.addrsig_sym _Z15update_clustersPfS_Piiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19initialize_clustersPfii ; -- Begin function _Z19initialize_clustersPfii
	.globl	_Z19initialize_clustersPfii
	.p2align	8
	.type	_Z19initialize_clustersPfii,@function
_Z19initialize_clustersPfii:            ; @_Z19initialize_clustersPfii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_mul_i32 s2, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v0, vcc_lo, s2, v1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v2, vcc_lo
	v_xor_b32_e32 v0, 0x2c7f967f, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, 0xa03697cb, v3
	v_mul_lo_u32 v0, 0x493c4aa1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 0x75bcd15, v0
	v_add_nc_u32_e32 v6, 0x583f19, v0
	v_lshrrev_b32_e32 v5, 2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v4
	v_lshlrev_b32_e32 v4, 4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v7, 1, v5
	v_xor_b32_e32 v7, v4, v7
	v_mad_u64_u32 v[3:4], null, 0x7b99840d, v8, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v0, v7, v6, v5
	v_add3_u32 v0, v3, v0, 0x6a788e
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, v0
	v_fmaak_f32 v3, 0x2f800000, v0, 0x2f800000
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x41200000, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19initialize_clustersPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19initialize_clustersPfii, .Lfunc_end0-_Z19initialize_clustersPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15assign_clustersPfS_Piiii ; -- Begin function _Z15assign_clustersPfS_Piiii
	.globl	_Z15assign_clustersPfS_Piiii
	.p2align	8
	.type	_Z15assign_clustersPfS_Piiii,@function
_Z15assign_clustersPfS_Piiii:           ; @_Z15assign_clustersPfS_Piiii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s7, exec_lo
	s_mul_i32 s3, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s3, v0
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s0, s[0:1], 0x34
	v_lshl_add_u32 v2, v0, 2, 0
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s14, s0, 2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v0, s0, v0
	v_add_co_u32 v3, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s3, v0
	global_load_b32 v1, v[3:4], off
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1
	v_add_nc_u32_e32 v2, s14, v2
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %Flow69
	s_or_b32 exec_lo, exec_lo, s7
	s_cmp_ge_i32 s2, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_12
; %bb.4:                                ; %.preheader
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB1_10
; %bb.5:                                ; %.lr.ph37
	s_mul_i32 s0, s2, s6
	v_mov_b32_e32 v0, 0x7f800000
	s_ashr_i32 s1, s0, 31
	s_mov_b32 s3, 0
	s_lshl_b64 s[0:1], s[0:1], 2
	s_mov_b32 s4, -1
	s_add_u32 s8, s8, s0
	s_addc_u32 s9, s9, s1
	s_cmp_gt_i32 s6, 0
	s_mov_b32 s11, 0
	s_cselect_b32 s7, -1, 0
	s_lshl_b32 s10, s6, 2
.LBB1_6:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_8 Depth 2
	v_mov_b32_e32 v1, 0
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB1_9
; %bb.7:                                ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_mov_b64 s[0:1], s[8:9]
	s_mov_b32 s14, s6
	s_mov_b32 s15, s3
.LBB1_8:                                ; %.lr.ph.i
                                        ;   Parent Loop BB1_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s15
	s_load_b32 s16, s[0:1], 0x0
	s_add_i32 s15, s15, 4
	s_add_i32 s14, s14, -1
	s_add_u32 s0, s0, 4
	ds_load_b32 v2, v2
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s14, 0
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v2, s16, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v1, v2, v2
	s_cbranch_scc1 .LBB1_8
.LBB1_9:                                ; %_Z18euclidean_distancePKfS0_i.exit
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x4f800000, v1
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v2
	v_add_nc_u32_e32 v4, 1, v2
	v_fma_f32 v5, -v3, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v4, v2, v1
	v_cmp_ge_f32_e64 s0, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v2, v3, s0
	v_cmp_lt_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v2, v4, s0
	v_mul_f32_e32 v3, 0x37800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v1, 0x260
	v_cndmask_b32_e32 v1, v2, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_lt_f32_e32 vcc_lo, v1, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s4, s11, s4
	s_add_i32 s11, s11, 1
	s_add_i32 s3, s3, s10
	s_cmp_eq_u32 s11, s5
	s_cbranch_scc0 .LBB1_6
	s_branch .LBB1_11
.LBB1_10:
	s_mov_b32 s4, -1
.LBB1_11:                               ; %Flow66
	s_ashr_i32 s3, s2, 31
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s12, s0
	s_addc_u32 s1, s13, s1
	global_store_b32 v0, v1, s[0:1]
.LBB1_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15assign_clustersPfS_Piiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15assign_clustersPfS_Piiii, .Lfunc_end1-_Z15assign_clustersPfS_Piiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 19
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15update_clustersPfS_Piiii ; -- Begin function _Z15update_clustersPfS_Piiii
	.globl	_Z15update_clustersPfS_Piiii
	.p2align	8
	.type	_Z15update_clustersPfS_Piiii,@function
_Z15update_clustersPfS_Piiii:           ; @_Z15update_clustersPfS_Piiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_mov_b32 s2, s15
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s7, v0
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s8, s[0:1], 0x34
	v_lshl_add_u32 v1, v0, 2, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s10, s8, 2
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s8, v3
	ds_store_b32 v1, v2
	v_add_nc_u32_e32 v1, s10, v1
	v_cmp_le_i32_e32 vcc_lo, s7, v3
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB2_2
.LBB2_3:                                ; %Flow88
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	s_cmp_ge_i32 s2, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_15
; %bb.4:
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s14, exec_lo
	s_lshl_b64 s[16:17], s[2:3], 2
	s_mul_i32 s2, s2, s6
	s_add_u32 s12, s12, s16
	s_addc_u32 s13, s13, s17
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_load_b32 s3, s[12:13], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s3, s6
	s_ashr_i32 s3, s2, 31
	s_lshl_b32 s4, s4, 2
	s_lshl_b64 s[2:3], s[2:3], 2
	s_add_i32 s4, s4, 0
	s_add_u32 s2, s8, s2
	s_addc_u32 s3, s9, s3
	s_mov_b32 s8, exec_lo
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_6
; %bb.5:
	s_load_b32 s9, s[2:3], 0x0
	s_bcnt1_i32_b32 s12, s14
	v_mov_b32_e32 v2, s4
	v_cvt_f32_ubyte0_e32 v1, s12
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, s9, v1
	ds_add_f32 v2, v1
.LBB2_6:
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 s9, exec_lo
	s_mov_b32 s8, exec_lo
	v_mbcnt_lo_u32_b32 v1, s9, 0
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_8
; %bb.7:
	s_load_b32 s12, s[2:3], 0x4
	s_bcnt1_i32_b32 s9, s9
	v_mov_b32_e32 v2, s4
	v_cvt_f32_ubyte0_e32 v1, s9
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, s12, v1
	ds_add_f32 v2, v1 offset:4
.LBB2_8:
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 s9, exec_lo
	s_mov_b32 s8, exec_lo
	v_mbcnt_lo_u32_b32 v1, s9, 0
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_10
; %bb.9:
	s_load_b32 s12, s[2:3], 0x8
	s_bcnt1_i32_b32 s9, s9
	v_mov_b32_e32 v2, s4
	v_cvt_f32_ubyte0_e32 v1, s9
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, s12, v1
	ds_add_f32 v2, v1 offset:8
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 s9, exec_lo
	s_mov_b32 s8, exec_lo
	v_mbcnt_lo_u32_b32 v1, s9, 0
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_12
; %bb.11:
	s_load_b32 s12, s[2:3], 0xc
	s_bcnt1_i32_b32 s9, s9
	v_mov_b32_e32 v2, s4
	v_cvt_f32_ubyte0_e32 v1, s9
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, s12, v1
	ds_add_f32 v2, v1 offset:12
.LBB2_12:
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 s9, exec_lo
	s_mov_b32 s8, exec_lo
	v_mbcnt_lo_u32_b32 v1, s9, 0
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_14
; %bb.13:
	s_load_b32 s2, s[2:3], 0x10
	s_bcnt1_i32_b32 s3, s9
	v_mov_b32_e32 v2, s4
	v_cvt_f32_ubyte0_e32 v1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, s2, v1
	ds_add_f32 v2, v1 offset:16
.LBB2_14:                               ; %Flow85
	s_or_b32 exec_lo, exec_lo, s8
.LBB2_15:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s5, v0
	s_cbranch_execz .LBB2_18
; %bb.16:                               ; %.lr.ph57
	s_load_b32 s0, s[0:1], 0x34
	v_mul_lo_u32 v1, v0, s6
	v_mov_b32_e32 v3, v0
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, 1.0 :: v_dual_lshlrev_b32 v1, 2, v1
	v_add3_u32 v1, v1, 0, 20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s6, s0
	s_lshl_b32 s3, s3, 2
.LBB2_17:                               ; =>This Inner Loop Header: Depth=1
	ds_add_f32 v1, v2
	v_add_nc_u32_e32 v3, s0, v3
	v_add_nc_u32_e32 v1, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s5, v3
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_17
.LBB2_18:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e64 s7, v0
	s_cbranch_execz .LBB2_21
; %bb.19:
	v_cvt_f32_u32_e32 v1, s6
	s_sub_i32 s0, 0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s0, v1
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s6
	v_sub_nc_u32_e32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s6, v1
	v_cmp_le_u32_e32 vcc_lo, s6, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s6, v1
	v_cmp_le_u32_e32 vcc_lo, s6, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v0, v1
	v_lshl_add_u32 v1, v1, 2, 0
	ds_load_b32 v1, v1 offset:20
	s_waitcnt lgkmcnt(0)
	v_cvt_i32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_21
; %bb.20:
	v_lshl_add_u32 v2, v0, 2, 0
	v_cvt_f32_i32_e32 v1, v1
	v_lshlrev_b32_e32 v0, 2, v0
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v3, null, v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v4
	v_fma_f32 v7, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v4
	v_fma_f32 v3, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v6
	v_div_fixup_f32 v1, v3, v1, v2
	global_store_b32 v0, v1, s[10:11]
.LBB2_21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15update_clustersPfS_Piiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z15update_clustersPfS_Piiii, .Lfunc_end2-_Z15update_clustersPfS_Piiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1068
; NumSgprs: 20
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym shared_clusters
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19initialize_clustersPfii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19initialize_clustersPfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15assign_clustersPfS_Piiii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z15assign_clustersPfS_Piiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15update_clustersPfS_Piiii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z15update_clustersPfS_Piiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
