#include <iostream>
#include <cuda_runtime.h>

// Define constants
#define TILE_WIDTH 16
#define FILTER_SIZE 3
#define CHANNELS 3
#define BATCH_SIZE 64

// Kernel for backpropagation in convolutional layer
__global__ void convBackpropKernel(float* d_input, float* d_output, float* d_filter, float* d_inputGrad, float* d_filterGrad, int width, int height) {
    __shared__ float sharedInput[TILE_WIDTH + FILTER_SIZE - 1][TILE_WIDTH + FILTER_SIZE - 1];
    __shared__ float sharedFilter[FILTER_SIZE][FILTER_SIZE];

    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;

    int outputX = bx * TILE_WIDTH + tx;
    int outputY = by * TILE_WIDTH + ty;

    int inputX = outputX + FILTER_SIZE / 2;
    int inputY = outputY + FILTER_SIZE / 2;

    int filterRow = ty;
    int filterCol = tx;

    // Load filter into shared memory
    if (filterRow < FILTER_SIZE && filterCol < FILTER_SIZE) {
        for (int c = 0; c < CHANNELS; ++c) {
            sharedFilter[filterRow][filterCol] = d_filter[c * FILTER_SIZE * FILTER_SIZE + filterRow * FILTER_SIZE + filterCol];
        }
    }

    // Load input into shared memory
    for (int c = 0; c < CHANNELS; ++c) {
        int row = inputY - FILTER_SIZE / 2 + filterRow;
        int col = inputX - FILTER_SIZE / 2 + filterCol;
        if (row >= 0 && row < height && col >= 0 && col < width) {
            sharedInput[filterRow][filterCol] = d_input[c * height * width + row * width + col];
        } else {
            sharedInput[filterRow][filterCol] = 0.0f;
        }
    }

    __syncthreads();

    float inputGrad = 0.0f;
    float filterGrad[CHANNELS] = {0.0f};

    if (outputX < width && outputY < height) {
        for (int c = 0; c < CHANNELS; ++c) {
            for (int i = 0; i < FILTER_SIZE; ++i) {
                for (int j = 0; j < FILTER_SIZE; ++j) {
                    inputGrad += d_output[c * height * width + outputY * width + outputX] * sharedFilter[i][j];
                    filterGrad[c] += d_output[c * height * width + outputY * width + outputX] * sharedInput[i][j];
                }
            }
        }
    }

    // Write results to global memory
    if (outputX < width && outputY < height) {
        for (int c = 0; c < CHANNELS; ++c) {
            atomicAdd(&d_inputGrad[c * height * width + inputY * width + inputX], inputGrad);
            atomicAdd(&d_filterGrad[c * FILTER_SIZE * FILTER_SIZE + filterRow * FILTER_SIZE + filterCol], filterGrad[c]);
        }
    }
}

int main() {
    int width = 28;
    int height = 28;
    int inputSize = BATCH_SIZE * CHANNELS * height * width;
    int outputSize = BATCH_SIZE * CHANNELS * height * width;
    int filterSize = CHANNELS * FILTER_SIZE * FILTER_SIZE;

    float* h_input = new float[inputSize];
    float* h_output = new float[outputSize];
    float* h_filter = new float[filterSize];
    float* h_inputGrad = new float[inputSize];
    float* h_filterGrad = new float[filterSize];

    // Initialize host data
    for (int i = 0; i < inputSize; ++i) h_input[i] = 1.0f;
    for (int i = 0; i < outputSize; ++i) h_output[i] = 1.0f;
    for (int i = 0; i < filterSize; ++i) h_filter[i] = 1.0f;
    for (int i = 0; i < inputSize; ++i) h_inputGrad[i] = 0.0f;
    for (int i = 0; i < filterSize; ++i) h_filterGrad[i] = 0.0f;

    float* d_input;
    float* d_output;
    float* d_filter;
    float* d_inputGrad;
    float* d_filterGrad;

    // Allocate device memory
    cudaMalloc((void**)&d_input, inputSize * sizeof(float));
    cudaMalloc((void**)&d_output, outputSize * sizeof(float));
    cudaMalloc((void**)&d_filter, filterSize * sizeof(float));
    cudaMalloc((void**)&d_inputGrad, inputSize * sizeof(float));
    cudaMalloc((void**)&d_filterGrad, filterSize * sizeof(float));

    // Copy data from host to device
    cudaMemcpy(d_input, h_input, inputSize * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_output, h_output, outputSize * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_filter, h_filter, filterSize * sizeof(float), cudaMemcpyHostToDevice);

    // Define block and grid dimensions
    dim3 threadsPerBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 blocksPerGrid((width + TILE_WIDTH - 1) / TILE_WIDTH, (height + TILE_WIDTH - 1) / TILE_WIDTH);

    // Launch kernel
    convBackpropKernel<<<blocksPerGrid, threadsPerBlock>>>(d_input, d_output, d_filter, d_inputGrad, d_filterGrad, width, height);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results from device to host
    cudaMemcpy(h_inputGrad, d_inputGrad, inputSize * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_filterGrad, d_filterGrad, filterSize * sizeof(float), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_output);
    cudaFree(d_filter);
    cudaFree(d_inputGrad);
    cudaFree(d_filterGrad);

    // Free host memory
    delete[] h_input;
    delete[] h_output;
    delete[] h_filter;
    delete[] h_inputGrad;
    delete[] h_filterGrad;

    return 0;
}
	.file	"tmpxft_0018e8fd_00000000-6_cuda_code_033389.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_iiPfS_S_S_S_ii
	.type	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_iiPfS_S_S_S_ii, @function
_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_iiPfS_S_S_S_ii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18convBackpropKernelPfS_S_S_S_ii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_iiPfS_S_S_S_ii, .-_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_iiPfS_S_S_S_ii
	.globl	_Z18convBackpropKernelPfS_S_S_S_ii
	.type	_Z18convBackpropKernelPfS_S_S_S_ii, @function
_Z18convBackpropKernelPfS_S_S_S_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_iiPfS_S_S_S_ii
	.cfi_endproc
.LFE3661:
	.size	_Z18convBackpropKernelPfS_S_S_S_ii, .-_Z18convBackpropKernelPfS_S_S_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$602112, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$602112, %edi
	movq	%rax, %r14
	call	_Znam@PLT
	movl	$108, %edi
	movq	%rax, %r13
	call	_Znam@PLT
	movl	$602112, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$108, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movss	.LC0(%rip), %xmm0
	movq	%rax, %rbx
	xorl	%eax, %eax
.L9:
	movss	%xmm0, (%r14,%rax,4)
	incq	%rax
	cmpq	$150528, %rax
	jne	.L9
	xorl	%eax, %eax
.L10:
	movss	%xmm0, 0(%r13,%rax,4)
	incq	%rax
	cmpq	$150528, %rax
	jne	.L10
	xorl	%edx, %edx
.L11:
	movss	%xmm0, (%r12,%rdx,4)
	incq	%rdx
	cmpq	$27, %rdx
	jne	.L11
	xorl	%eax, %eax
	movl	$150528, %ecx
	movq	%rbp, %rdi
	movl	$602112, %esi
	rep stosl
	movq	%rdx, %rcx
	movq	%rbx, %rdi
	rep stosl
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$602112, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$108, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$602112, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$108, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$602112, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$602112, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$108, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	movabsq	$8589934594, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	$28, %r9d
	pushq	$28
	.cfi_def_cfa_offset 160
	movq	56(%rsp), %r8
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_iiPfS_S_S_S_ii
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L12:
	call	cudaGetLastError@PLT
	movl	%eax, %r15d
	testl	%eax, %eax
	je	.L13
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r15d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L13:
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movl	$602112, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$108, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r14, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L8:
	movq	72(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z18convBackpropKernelPfS_S_S_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convBackpropKernelPfS_S_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>

// Define constants
#define TILE_WIDTH 16
#define FILTER_SIZE 3
#define CHANNELS 3
#define BATCH_SIZE 64

// Kernel for backpropagation in convolutional layer
__global__ void convBackpropKernel(float* d_input, float* d_output, float* d_filter, float* d_inputGrad, float* d_filterGrad, int width, int height) {
    __shared__ float sharedInput[TILE_WIDTH + FILTER_SIZE - 1][TILE_WIDTH + FILTER_SIZE - 1];
    __shared__ float sharedFilter[FILTER_SIZE][FILTER_SIZE];

    int bx = blockIdx.x;
    int by = blockIdx.y;
    int tx = threadIdx.x;
    int ty = threadIdx.y;

    int outputX = bx * TILE_WIDTH + tx;
    int outputY = by * TILE_WIDTH + ty;

    int inputX = outputX + FILTER_SIZE / 2;
    int inputY = outputY + FILTER_SIZE / 2;

    int filterRow = ty;
    int filterCol = tx;

    // Load filter into shared memory
    if (filterRow < FILTER_SIZE && filterCol < FILTER_SIZE) {
        for (int c = 0; c < CHANNELS; ++c) {
            sharedFilter[filterRow][filterCol] = d_filter[c * FILTER_SIZE * FILTER_SIZE + filterRow * FILTER_SIZE + filterCol];
        }
    }

    // Load input into shared memory
    for (int c = 0; c < CHANNELS; ++c) {
        int row = inputY - FILTER_SIZE / 2 + filterRow;
        int col = inputX - FILTER_SIZE / 2 + filterCol;
        if (row >= 0 && row < height && col >= 0 && col < width) {
            sharedInput[filterRow][filterCol] = d_input[c * height * width + row * width + col];
        } else {
            sharedInput[filterRow][filterCol] = 0.0f;
        }
    }

    __syncthreads();

    float inputGrad = 0.0f;
    float filterGrad[CHANNELS] = {0.0f};

    if (outputX < width && outputY < height) {
        for (int c = 0; c < CHANNELS; ++c) {
            for (int i = 0; i < FILTER_SIZE; ++i) {
                for (int j = 0; j < FILTER_SIZE; ++j) {
                    inputGrad += d_output[c * height * width + outputY * width + outputX] * sharedFilter[i][j];
                    filterGrad[c] += d_output[c * height * width + outputY * width + outputX] * sharedInput[i][j];
                }
            }
        }
    }

    // Write results to global memory
    if (outputX < width && outputY < height) {
        for (int c = 0; c < CHANNELS; ++c) {
            atomicAdd(&d_inputGrad[c * height * width + inputY * width + inputX], inputGrad);
            atomicAdd(&d_filterGrad[c * FILTER_SIZE * FILTER_SIZE + filterRow * FILTER_SIZE + filterCol], filterGrad[c]);
        }
    }
}

int main() {
    int width = 28;
    int height = 28;
    int inputSize = BATCH_SIZE * CHANNELS * height * width;
    int outputSize = BATCH_SIZE * CHANNELS * height * width;
    int filterSize = CHANNELS * FILTER_SIZE * FILTER_SIZE;

    float* h_input = new float[inputSize];
    float* h_output = new float[outputSize];
    float* h_filter = new float[filterSize];
    float* h_inputGrad = new float[inputSize];
    float* h_filterGrad = new float[filterSize];

    // Initialize host data
    for (int i = 0; i < inputSize; ++i) h_input[i] = 1.0f;
    for (int i = 0; i < outputSize; ++i) h_output[i] = 1.0f;
    for (int i = 0; i < filterSize; ++i) h_filter[i] = 1.0f;
    for (int i = 0; i < inputSize; ++i) h_inputGrad[i] = 0.0f;
    for (int i = 0; i < filterSize; ++i) h_filterGrad[i] = 0.0f;

    float* d_input;
    float* d_output;
    float* d_filter;
    float* d_inputGrad;
    float* d_filterGrad;

    // Allocate device memory
    hipMalloc((void**)&d_input, inputSize * sizeof(float));
    hipMalloc((void**)&d_output, outputSize * sizeof(float));
    hipMalloc((void**)&d_filter, filterSize * sizeof(float));
    hipMalloc((void**)&d_inputGrad, inputSize * sizeof(float));
    hipMalloc((void**)&d_filterGrad, filterSize * sizeof(float));

    // Copy data from host to device
    hipMemcpy(d_input, h_input, inputSize * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_output, h_output, outputSize * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_filter, h_filter, filterSize * sizeof(float), hipMemcpyHostToDevice);

    // Define block and grid dimensions
    dim3 threadsPerBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 blocksPerGrid((width + TILE_WIDTH - 1) / TILE_WIDTH, (height + TILE_WIDTH - 1) / TILE_WIDTH);

    // Launch kernel
    convBackpropKernel<<<blocksPerGrid, threadsPerBlock>>>(d_input, d_output, d_filter, d_inputGrad, d_filterGrad, width, height);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results from device to host
    hipMemcpy(h_inputGrad, d_inputGrad, inputSize * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_filterGrad, d_filterGrad, filterSize * sizeof(float), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_input);
    hipFree(d_output);
    hipFree(d_filter);
    hipFree(d_inputGrad);
    hipFree(d_filterGrad);

    // Free host memory
    delete[] h_input;
    delete[] h_output;
    delete[] h_filter;
    delete[] h_inputGrad;
    delete[] h_filterGrad;

    return 0;
}
	.text
	.file	"cuda_code_033389.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii # -- Begin function _Z33__device_stub__convBackpropKernelPfS_S_S_S_ii
	.type	_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii,@function
_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii: # @_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convBackpropKernelPfS_S_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii, .Lfunc_end0-_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$602112, %edi                   # imm = 0x93000
	callq	_Znam
	movq	%rax, %rbx
	movl	$602112, %edi                   # imm = 0x93000
	callq	_Znam
	movq	%rax, %r14
	movl	$108, %edi
	callq	_Znam
	movq	%rax, %r15
	movl	$602112, %edi                   # imm = 0x93000
	callq	_Znam
	movq	%rax, %r12
	movl	$108, %edi
	callq	_Znam
	movq	%rax, %r13
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rbx,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$150528, %rax                   # imm = 0x24C00
	jne	.LBB1_1
# %bb.2:                                # %.preheader77.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader77
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r14,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$150528, %rax                   # imm = 0x24C00
	jne	.LBB1_3
# %bb.4:                                # %.preheader76.preheader
	xorl	%eax, %eax
.LBB1_5:                                # %.preheader76
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%r15,%rax,4)      # imm = 0x3F800000
	incq	%rax
	cmpq	$27, %rax
	jne	.LBB1_5
# %bb.6:                                # %.preheader75.preheader
	movl	$602112, %edx                   # imm = 0x93000
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	xorps	%xmm0, %xmm0
	movups	%xmm0, (%r13)
	movups	%xmm0, 16(%r13)
	movups	%xmm0, 32(%r13)
	movups	%xmm0, 48(%r13)
	movups	%xmm0, 64(%r13)
	movups	%xmm0, 80(%r13)
	movups	%xmm0, 92(%r13)
	leaq	40(%rsp), %rbp
	movl	$602112, %esi                   # imm = 0x93000
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r12
	movl	$602112, %esi                   # imm = 0x93000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$108, %esi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$602112, %esi                   # imm = 0x93000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$108, %esi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$602112, %edx                   # imm = 0x93000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$602112, %edx                   # imm = 0x93000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	$108, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$8589934594, %rdi               # imm = 0x200000002
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movl	$28, (%rsp)
	movl	$28, %r9d
	callq	_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii
.LBB1_8:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_13
# %bb.9:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_10
# %bb.11:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_12
.LBB1_13:
	movq	16(%rsp), %rsi
	movl	$602112, %edx                   # imm = 0x93000
	movq	48(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$108, %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_ZdaPv
	movq	%r13, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_14
.LBB1_10:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_14:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convBackpropKernelPfS_S_S_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convBackpropKernelPfS_S_S_S_ii,@object # @_Z18convBackpropKernelPfS_S_S_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z18convBackpropKernelPfS_S_S_S_ii
	.p2align	3, 0x0
_Z18convBackpropKernelPfS_S_S_S_ii:
	.quad	_Z33__device_stub__convBackpropKernelPfS_S_S_S_ii
	.size	_Z18convBackpropKernelPfS_S_S_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convBackpropKernelPfS_S_S_S_ii"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convBackpropKernelPfS_S_S_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convBackpropKernelPfS_S_S_S_ii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convBackpropKernelPfS_S_S_S_ii ; -- Begin function _Z18convBackpropKernelPfS_S_S_S_ii
	.globl	_Z18convBackpropKernelPfS_S_S_S_ii
	.p2align	8
	.type	_Z18convBackpropKernelPfS_S_S_S_ii,@function
_Z18convBackpropKernelPfS_S_S_S_ii:     ; @_Z18convBackpropKernelPfS_S_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x20
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_mov_b32 s12, 3
	s_mov_b32 s13, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 2, v5
	v_max_u32_e32 v0, v6, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 3, v0
	s_cbranch_execz .LBB0_2
; %bb.1:                                ; %.preheader125
	v_mul_u32_u24_e32 v0, 3, v6
	v_mad_u32_u24 v1, v6, 12, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_lshl_u32 v0, v0, v5, 2
	s_waitcnt lgkmcnt(0)
	global_load_b32 v0, v0, s[8:9] offset:72
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v0 offset:1296
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt lgkmcnt(0)
	s_load_b64 s[8:9], s[0:1], 0x28
	s_lshl_b32 s13, s14, 4
	v_lshl_add_u32 v4, s15, 4, v6
	v_add_nc_u32_e32 v3, s13, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v4, v6
	v_add_nc_u32_e32 v1, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v7, v0, v1
	v_cmp_lt_i32_e64 s1, -1, v7
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v8, s8, v0
	v_cmp_gt_i32_e32 vcc_lo, s9, v0
	v_lshlrev_b32_e32 v0, 1, v5
	v_cmp_gt_i32_e64 s0, s8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_and_b32 s0, vcc_lo, s0
	v_add3_u32 v0, v8, s13, v0
	s_and_b32 s0, s0, s1
	s_mul_i32 s1, s9, s8
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v1, 0
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_co_u32 v7, vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v1, v[7:8], off
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v0, s1, v0
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc0 .LBB0_3
; %bb.6:
	v_mad_u32_u24 v0, 0x48, v6, v2
	v_mov_b32_e32 v2, 0
	v_cmp_gt_i32_e32 vcc_lo, s8, v3
	v_cmp_gt_i32_e64 s0, s9, v4
	s_mov_b32 s12, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v1
	v_mov_b32_e32 v1, v2
	v_mov_b32_e32 v0, v2
	v_mov_b32_e32 v10, v2
	s_and_b32 s4, vcc_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB0_13
; %bb.7:                                ; %.preheader122.preheader
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_mov_b32_e32 v0, s12
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s13
	v_mov_b32_e32 v2, s14
.LBB0_8:                                ; %.preheader122
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
	v_mad_u64_u32 v[7:8], null, s12, s9, v[4:5]
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0
	s_movk_i32 s15, 0x510
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v7, s8, v[3:4]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[8:9]
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
.LBB0_9:                                ; %.preheader121
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
	s_mov_b32 s16, 0
.LBB0_10:                               ;   Parent Loop BB0_8 Depth=1
                                        ;     Parent Loop BB0_9 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s13, s16
	s_add_i32 s1, s15, s16
	v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v9, s1
	s_cmp_eq_u32 s12, 1
	ds_load_b32 v8, v8
	ds_load_b32 v9, v9
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s12, 2
	v_cndmask_b32_e32 v11, v0, v1, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s12, 0
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v11, v11, v2, s0
	s_add_i32 s16, s16, 4
	s_cmp_eq_u32 s16, 12
	s_waitcnt vmcnt(0) lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v7, v8
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v10, v7, v9 :: v_dual_cndmask_b32 v1, v1, v11
	v_cndmask_b32_e64 v2, v2, v11, s0
	v_cndmask_b32_e64 v0, v0, v11, s1
	s_cbranch_scc0 .LBB0_10
; %bb.11:                               ;   in Loop: Header=BB0_9 Depth=2
	s_add_i32 s14, s14, 1
	s_add_i32 s15, s15, 12
	s_addk_i32 s13, 0x48
	s_cmp_eq_u32 s14, 3
	s_cbranch_scc0 .LBB0_9
; %bb.12:                               ;   in Loop: Header=BB0_8 Depth=1
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 3
	s_cbranch_scc0 .LBB0_8
.LBB0_13:                               ; %Flow191
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_20
; %bb.14:                               ; %.preheader
	v_add_nc_u32_e32 v4, 1, v4
	v_mad_u32_u24 v5, v6, 3, v5
	v_ashrrev_i32_e32 v11, 31, v3
	v_mov_b32_e32 v12, 0
	s_add_u32 s0, s10, 4
	s_addc_u32 s1, s11, 0
	s_mov_b32 s4, 0
.LBB0_15:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_16 Depth 2
                                        ;     Child Loop BB0_18 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s4, s9, v[4:5]
	s_mov_b32 s5, 0
	v_mul_lo_u32 v6, v6, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v6, vcc_lo, v3, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, v11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b32 v9, v[6:7], off
.LBB0_16:                               ; %atomicrmw.start
                                        ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v8, v9, v10
	global_atomic_cmpswap_b32 v8, v[6:7], v[8:9], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v8, v9
	v_mov_b32_e32 v9, v8
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_16
; %bb.17:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB0_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_mad_u64_u32 v[6:7], null, s4, 9, v[5:6]
	v_mov_b32_e32 v7, v12
	s_cmp_eq_u32 s4, 1
	s_mov_b32 s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 2
	v_cndmask_b32_e32 v8, v0, v1, vcc_lo
	global_load_b32 v9, v[6:7], off
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v13, v8, v2, vcc_lo
.LBB0_18:                               ; %atomicrmw.start153
                                        ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v8, v9, v13
	global_atomic_cmpswap_b32 v8, v[6:7], v[8:9], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v8, v9
	v_mov_b32_e32 v9, v8
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_18
; %bb.19:                               ; %atomicrmw.end152
                                        ;   in Loop: Header=BB0_15 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s4, 3
	s_cbranch_scc1 .LBB0_15
.LBB0_20:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convBackpropKernelPfS_S_S_S_ii
		.amdhsa_group_segment_fixed_size 1332
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convBackpropKernelPfS_S_S_S_ii, .Lfunc_end0-_Z18convBackpropKernelPfS_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 976
; NumSgprs: 19
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1332 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1332
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convBackpropKernelPfS_S_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z18convBackpropKernelPfS_S_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
