#include <iostream>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <vector>
#include <cmath>

#define N 128
#define BLOCK_SIZE 32
#define GRID_SIZE (N + BLOCK_SIZE - 1) / BLOCK_SIZE

// Kernel to compute forces using particle mesh
__global__ void computeForces(float4 *pos, float4 *forces, float4 *mesh, int nx, int ny, int nz, float dx, float dy, float dz) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= N) return;

    float4 p = pos[idx];
    float4 f = {0.0f, 0.0f, 0.0f, 0.0f};

    // Compute grid cell indices
    int ix = static_cast<int>(p.x / dx);
    int iy = static_cast<int>(p.y / dy);
    int iz = static_cast<int>(p.z / dz);

    // Interpolate forces from the mesh
    for (int i = -1; i <= 1; ++i) {
        for (int j = -1; j <= 1; ++j) {
            for (int k = -1; k <= 1; ++k) {
                int nx_i = (ix + i + nx) % nx;
                int ny_j = (iy + j + ny) % ny;
                int nz_k = (iz + k + nz) % nz;
                float4 meshForce = mesh[nz_k * nx * ny + ny_j * nx + nx_i];
                float wx = 1.0f - std::abs(p.x - (nx_i + 0.5f) * dx) / dx;
                float wy = 1.0f - std::abs(p.y - (ny_j + 0.5f) * dy) / dy;
                float wz = 1.0f - std::abs(p.z - (nz_k + 0.5f) * dz) / dz;
                float weight = wx * wy * wz;
                f.x += weight * meshForce.x;
                f.y += weight * meshForce.y;
                f.z += weight * meshForce.z;
            }
        }
    }

    forces[idx] = f;
}

// Kernel to update positions based on forces
__global__ void updatePositions(float4 *pos, float4 *forces, float dt) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= N) return;

    float4 p = pos[idx];
    float4 f = forces[idx];
    p.x += f.x * dt;
    p.y += f.y * dt;
    p.z += f.z * dt;
    pos[idx] = p;
}

int main() {
    // Parameters
    int nx = 16, ny = 16, nz = 16;
    float dx = 1.0f / nx, dy = 1.0f / ny, dz = 1.0f / nz;
    float dt = 0.01f;

    // Allocate host memory
    std::vector<float4> h_pos(N);
    std::vector<float4> h_forces(N);
    std::vector<float4> h_mesh(nx * ny * nz);

    // Initialize positions and mesh
    for (int i = 0; i < N; ++i) {
        h_pos[i] = {static_cast<float>(i % nx) * dx + 0.5f * dx,
                    static_cast<float>((i / nx) % ny) * dy + 0.5f * dy,
                    static_cast<float>(i / (nx * ny)) * dz + 0.5f * dz,
                    0.0f};
    }
    for (int i = 0; i < nx * ny * nz; ++i) {
        h_mesh[i] = {0.0f, 0.0f, 0.0f, 0.0f};
    }

    // Allocate device memory
    float4 *d_pos, *d_forces, *d_mesh;
    cudaMalloc(&d_pos, N * sizeof(float4));
    cudaMalloc(&d_forces, N * sizeof(float4));
    cudaMalloc(&d_mesh, nx * ny * nz * sizeof(float4));

    // Copy data to device
    cudaMemcpy(d_pos, h_pos.data(), N * sizeof(float4), cudaMemcpyHostToDevice);
    cudaMemcpy(d_mesh, h_mesh.data(), nx * ny * nz * sizeof(float4), cudaMemcpyHostToDevice);

    // Launch kernels
    computeForces<<<GRID_SIZE, BLOCK_SIZE>>>(d_pos, d_forces, d_mesh, nx, ny, nz, dx, dy, dz);
    cudaDeviceSynchronize();
    updatePositions<<<GRID_SIZE, BLOCK_SIZE>>>(d_pos, d_forces, dt);
    cudaDeviceSynchronize();

    // Copy results back to host
    cudaMemcpy(h_pos.data(), d_pos, N * sizeof(float4), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_pos);
    cudaFree(d_forces);
    cudaFree(d_mesh);

    // Output first particle's position
    std::cout << "Final position of particle 0: (" << h_pos[0].x << ", " << h_pos[0].y << ", " << h_pos[0].z << ")" << std::endl;

    return 0;
}
	.file	"tmpxft_0001c91f_00000000-6_cuda_code_030888.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4375:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4375:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z51__device_stub__Z13computeForcesP6float4S0_S0_iiifffP6float4S0_S0_iiifff
	.type	_Z51__device_stub__Z13computeForcesP6float4S0_S0_iiifffP6float4S0_S0_iiifff, @function
_Z51__device_stub__Z13computeForcesP6float4S0_S0_iiifffP6float4S0_S0_iiifff:
.LFB4397:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movss	%xmm1, 4(%rsp)
	movss	%xmm2, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z13computeForcesP6float4S0_S0_iiifff(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4397:
	.size	_Z51__device_stub__Z13computeForcesP6float4S0_S0_iiifffP6float4S0_S0_iiifff, .-_Z51__device_stub__Z13computeForcesP6float4S0_S0_iiifffP6float4S0_S0_iiifff
	.globl	_Z13computeForcesP6float4S0_S0_iiifff
	.type	_Z13computeForcesP6float4S0_S0_iiifff, @function
_Z13computeForcesP6float4S0_S0_iiifff:
.LFB4398:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z13computeForcesP6float4S0_S0_iiifffP6float4S0_S0_iiifff
	.cfi_endproc
.LFE4398:
	.size	_Z13computeForcesP6float4S0_S0_iiifff, .-_Z13computeForcesP6float4S0_S0_iiifff
	.globl	_Z45__device_stub__Z15updatePositionsP6float4S0_fP6float4S0_f
	.type	_Z45__device_stub__Z15updatePositionsP6float4S0_fP6float4S0_f, @function
_Z45__device_stub__Z15updatePositionsP6float4S0_fP6float4S0_f:
.LFB4399:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	48(%rsp), %rdi
	leaq	60(%rsp), %rsi
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15updatePositionsP6float4S0_f(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4399:
	.size	_Z45__device_stub__Z15updatePositionsP6float4S0_fP6float4S0_f, .-_Z45__device_stub__Z15updatePositionsP6float4S0_fP6float4S0_f
	.globl	_Z15updatePositionsP6float4S0_f
	.type	_Z15updatePositionsP6float4S0_f, @function
_Z15updatePositionsP6float4S0_f:
.LFB4400:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z15updatePositionsP6float4S0_fP6float4S0_f
	.cfi_endproc
.LFE4400:
	.size	_Z15updatePositionsP6float4S0_f, .-_Z15updatePositionsP6float4S0_f
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15updatePositionsP6float4S0_f"
.LC1:
	.string	"_Z13computeForcesP6float4S0_S0_iiifff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4402:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15updatePositionsP6float4S0_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13computeForcesP6float4S0_S0_iiifff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4402:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_.str1.1,"aMS",@progbits,1
.LC2:
	.string	"cannot create std::vector larger than max_size()"
	.section	.text._ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_,"axG",@progbits,_ZNSt6vectorI6float4SaIS0_EEC5EmRKS1_,comdat
	.align 2
	.weak	_ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_
	.type	_ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_, @function
_ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_:
.LFB4709:
	.cfi_startproc
	endbr64
	movabsq	$576460752303423487, %rax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	cmpq	%rsi, %rax
	jnb	.L16
	leaq	.LC2(%rip), %rdi
	call	_ZSt20__throw_length_errorPKc@PLT
.L16:
	xorl	%eax, %eax
	movq	%rsi, %r12
	movq	%rdi, %rbx
	movq	%rsi, %rbp
	movq	%rax, (%rdi)
	salq	$4, %r12
	movq	%rax, 8(%rdi)
	movq	%rax, 16(%rdi)
	xorl	%eax, %eax
	testq	%rsi, %rsi
	je	.L17
	movq	%r12, %rdi
	call	_Znwm@PLT
.L17:
	addq	%rax, %r12
	movq	%rax, (%rbx)
	movq	%rax, %rdx
	movq	%rax, 8(%rbx)
	movq	%r12, 16(%rbx)
	testq	%rbp, %rbp
	je	.L18
	xorps	%xmm0, %xmm0
	decq	%rbp
	leaq	16(%rax), %rdx
	movaps	%xmm0, (%rax)
	je	.L18
.L19:
	cmpq	%rdx, %r12
	je	.L18
	movaps	(%rax), %xmm1
	addq	$16, %rdx
	movaps	%xmm1, -16(%rdx)
	jmp	.L19
.L18:
	movq	%rdx, 8(%rbx)
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4709:
	.size	_ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_, .-_ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_
	.weak	_ZNSt6vectorI6float4SaIS0_EEC1EmRKS1_
	.set	_ZNSt6vectorI6float4SaIS0_EEC1EmRKS1_,_ZNSt6vectorI6float4SaIS0_EEC2EmRKS1_
	.section	.text._ZNSt6vectorI6float4SaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorI6float4SaIS0_EED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorI6float4SaIS0_EED2Ev
	.type	_ZNSt6vectorI6float4SaIS0_EED2Ev, @function
_ZNSt6vectorI6float4SaIS0_EED2Ev:
.LFB4712:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L29
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L29:
	ret
	.cfi_endproc
.LFE4712:
	.size	_ZNSt6vectorI6float4SaIS0_EED2Ev, .-_ZNSt6vectorI6float4SaIS0_EED2Ev
	.weak	_ZNSt6vectorI6float4SaIS0_EED1Ev
	.set	_ZNSt6vectorI6float4SaIS0_EED1Ev,_ZNSt6vectorI6float4SaIS0_EED2Ev
	.section	.rodata.str1.1
.LC7:
	.string	"Final position of particle 0: ("
.LC8:
	.string	", "
.LC9:
	.string	")"
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB4372:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4372
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$128, %esi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	addq	$-128, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	96(%rsp), %r13
	leaq	48(%rsp), %rbp
	movq	%r13, %rdx
	movq	%rbp, %rdi
	leaq	72(%rsp), %r12
.LEHB0:
	call	_ZNSt6vectorI6float4SaIS0_EEC1EmRKS1_
.LEHE0:
	movq	%r13, %rdx
	movl	$128, %esi
	movq	%r12, %rdi
.LEHB1:
	call	_ZNSt6vectorI6float4SaIS0_EEC1EmRKS1_
.LEHE1:
	leaq	36(%rsp), %rdx
	movl	$4096, %esi
	movq	%r13, %rdi
.LEHB2:
	call	_ZNSt6vectorI6float4SaIS0_EEC1EmRKS1_
.LEHE2:
	movq	48(%rsp), %rbx
	movss	.LC4(%rip), %xmm1
	xorl	%edx, %edx
	movq	%rbx, %rax
.L32:
	movl	%edx, %ecx
	movl	$0x00000000, 12(%rax)
	addq	$16, %rax
	andl	$15, %ecx
	movss	%xmm1, -8(%rax)
	cvtsi2ssl	%ecx, %xmm0
	mulss	.LC3(%rip), %xmm0
	movl	%edx, %ecx
	incl	%edx
	sarl	$4, %ecx
	addss	%xmm1, %xmm0
	movss	%xmm0, -16(%rax)
	cvtsi2ssl	%ecx, %xmm0
	mulss	.LC3(%rip), %xmm0
	addss	%xmm1, %xmm0
	movss	%xmm0, -12(%rax)
	cmpl	$128, %edx
	jne	.L32
	movq	96(%rsp), %r14
	movl	$16384, %ecx
	xorl	%eax, %eax
	movl	$2048, %esi
	movq	%r14, %rdi
	rep stosl
	movq	%rsp, %rdi
.LEHB3:
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$65536, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$2048, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$65536, %edx
	movq	%r14, %rsi
	call	cudaMemcpy@PLT
	movl	$134217729, %edx
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L33
.L35:
	call	cudaDeviceSynchronize@PLT
	jmp	.L52
.L33:
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$16, %r9d
	movl	$16, %r8d
	movss	.LC3(%rip), %xmm2
	movq	(%rsp), %rdi
	movl	$16, %ecx
	movaps	%xmm2, %xmm1
	movaps	%xmm2, %xmm0
	call	_Z51__device_stub__Z13computeForcesP6float4S0_S0_iiifffP6float4S0_S0_iiifff
	jmp	.L35
.L52:
	movl	$134217729, %edx
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L36
.L38:
	call	cudaDeviceSynchronize@PLT
	jmp	.L53
.L36:
	movss	.LC6(%rip), %xmm0
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z45__device_stub__Z15updatePositionsP6float4S0_fP6float4S0_f
	jmp	.L38
.L53:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$2048, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	cvtss2sd	(%rbx), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC8(%rip), %r14
	movq	%rax, %rdi
	movq	%r14, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	cvtss2sd	4(%rbx), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	movq	%r14, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	cvtss2sd	8(%rbx), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC9(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE3:
	movq	%r13, %rdi
	call	_ZNSt6vectorI6float4SaIS0_EED1Ev
	movq	%r12, %rdi
	call	_ZNSt6vectorI6float4SaIS0_EED1Ev
	movq	%rbp, %rdi
	call	_ZNSt6vectorI6float4SaIS0_EED1Ev
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	jmp	.L50
.L46:
	endbr64
	movq	%rax, %rbx
.L39:
	movq	%r13, %rdi
	call	_ZNSt6vectorI6float4SaIS0_EED1Ev
	jmp	.L40
.L45:
	endbr64
	movq	%rax, %rbx
.L40:
	movq	%r12, %rdi
	call	_ZNSt6vectorI6float4SaIS0_EED1Ev
	jmp	.L41
.L44:
	endbr64
	movq	%rax, %rbx
.L41:
	movq	%rbp, %rdi
	call	_ZNSt6vectorI6float4SaIS0_EED1Ev
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L50
	movq	%rbx, %rdi
.LEHB4:
	call	_Unwind_Resume@PLT
.LEHE4:
.L50:
	call	__stack_chk_fail@PLT
.L43:
	subq	$-128, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4372:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA4372:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4372-.LLSDACSB4372
.LLSDACSB4372:
	.uleb128 .LEHB0-.LFB4372
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB4372
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L44-.LFB4372
	.uleb128 0
	.uleb128 .LEHB2-.LFB4372
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L45-.LFB4372
	.uleb128 0
	.uleb128 .LEHB3-.LFB4372
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L46-.LFB4372
	.uleb128 0
	.uleb128 .LEHB4-.LFB4372
	.uleb128 .LEHE4-.LEHB4
	.uleb128 0
	.uleb128 0
.LLSDACSE4372:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1031798784
	.align 4
.LC4:
	.long	1023410176
	.align 4
.LC6:
	.long	1008981770
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
#include <vector>
#include <cmath>

#define N 128
#define BLOCK_SIZE 32
#define GRID_SIZE (N + BLOCK_SIZE - 1) / BLOCK_SIZE

// Kernel to compute forces using particle mesh
__global__ void computeForces(float4 *pos, float4 *forces, float4 *mesh, int nx, int ny, int nz, float dx, float dy, float dz) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= N) return;

    float4 p = pos[idx];
    float4 f = {0.0f, 0.0f, 0.0f, 0.0f};

    // Compute grid cell indices
    int ix = static_cast<int>(p.x / dx);
    int iy = static_cast<int>(p.y / dy);
    int iz = static_cast<int>(p.z / dz);

    // Interpolate forces from the mesh
    for (int i = -1; i <= 1; ++i) {
        for (int j = -1; j <= 1; ++j) {
            for (int k = -1; k <= 1; ++k) {
                int nx_i = (ix + i + nx) % nx;
                int ny_j = (iy + j + ny) % ny;
                int nz_k = (iz + k + nz) % nz;
                float4 meshForce = mesh[nz_k * nx * ny + ny_j * nx + nx_i];
                float wx = 1.0f - std::abs(p.x - (nx_i + 0.5f) * dx) / dx;
                float wy = 1.0f - std::abs(p.y - (ny_j + 0.5f) * dy) / dy;
                float wz = 1.0f - std::abs(p.z - (nz_k + 0.5f) * dz) / dz;
                float weight = wx * wy * wz;
                f.x += weight * meshForce.x;
                f.y += weight * meshForce.y;
                f.z += weight * meshForce.z;
            }
        }
    }

    forces[idx] = f;
}

// Kernel to update positions based on forces
__global__ void updatePositions(float4 *pos, float4 *forces, float dt) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx >= N) return;

    float4 p = pos[idx];
    float4 f = forces[idx];
    p.x += f.x * dt;
    p.y += f.y * dt;
    p.z += f.z * dt;
    pos[idx] = p;
}

int main() {
    // Parameters
    int nx = 16, ny = 16, nz = 16;
    float dx = 1.0f / nx, dy = 1.0f / ny, dz = 1.0f / nz;
    float dt = 0.01f;

    // Allocate host memory
    std::vector<float4> h_pos(N);
    std::vector<float4> h_forces(N);
    std::vector<float4> h_mesh(nx * ny * nz);

    // Initialize positions and mesh
    for (int i = 0; i < N; ++i) {
        h_pos[i] = {static_cast<float>(i % nx) * dx + 0.5f * dx,
                    static_cast<float>((i / nx) % ny) * dy + 0.5f * dy,
                    static_cast<float>(i / (nx * ny)) * dz + 0.5f * dz,
                    0.0f};
    }
    for (int i = 0; i < nx * ny * nz; ++i) {
        h_mesh[i] = {0.0f, 0.0f, 0.0f, 0.0f};
    }

    // Allocate device memory
    float4 *d_pos, *d_forces, *d_mesh;
    hipMalloc(&d_pos, N * sizeof(float4));
    hipMalloc(&d_forces, N * sizeof(float4));
    hipMalloc(&d_mesh, nx * ny * nz * sizeof(float4));

    // Copy data to device
    hipMemcpy(d_pos, h_pos.data(), N * sizeof(float4), hipMemcpyHostToDevice);
    hipMemcpy(d_mesh, h_mesh.data(), nx * ny * nz * sizeof(float4), hipMemcpyHostToDevice);

    // Launch kernels
    computeForces<<<GRID_SIZE, BLOCK_SIZE>>>(d_pos, d_forces, d_mesh, nx, ny, nz, dx, dy, dz);
    hipDeviceSynchronize();
    updatePositions<<<GRID_SIZE, BLOCK_SIZE>>>(d_pos, d_forces, dt);
    hipDeviceSynchronize();

    // Copy results back to host
    hipMemcpy(h_pos.data(), d_pos, N * sizeof(float4), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_pos);
    hipFree(d_forces);
    hipFree(d_mesh);

    // Output first particle's position
    std::cout << "Final position of particle 0: (" << h_pos[0].x << ", " << h_pos[0].y << ", " << h_pos[0].z << ")" << std::endl;

    return 0;
}
	.text
	.file	"cuda_code_030888.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff # -- Begin function _Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.type	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff,@function
_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff: # @_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	4(%rsp), %r10
	movss	%xmm1, (%r10)
	movq	%rsp, %r11
	movss	%xmm2, (%r11)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff, .Lfunc_end0-_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f # -- Begin function _Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.type	_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f,@function
_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f: # @_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f, .Lfunc_end1-_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x3d800000                      # float 0.0625
.LCPI2_1:
	.long	0x3d000000                      # float 0.03125
.LCPI2_2:
	.long	0x3c23d70a                      # float 0.00999999977
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$2048, %edi                     # imm = 0x800
	callq	_Znwm
	movq	%rax, %rbx
	movl	$2048, %edx                     # imm = 0x800
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp0:
	movl	$65536, %edi                    # imm = 0x10000
	callq	_Znwm
.Ltmp1:
# %bb.1:
	movq	%rax, %r14
	xorl	%r15d, %r15d
	movl	$65536, %edx                    # imm = 0x10000
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movss	.LCPI2_1(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movq	%rbx, %rax
.LBB2_2:                                # =>This Inner Loop Header: Depth=1
	movl	%r15d, %ecx
	andl	$15, %ecx
	xorps	%xmm3, %xmm3
	cvtsi2ss	%ecx, %xmm3
	mulss	%xmm0, %xmm3
	addss	%xmm1, %xmm3
	movl	%r15d, %ecx
	shrl	$4, %ecx
	xorps	%xmm4, %xmm4
	cvtsi2ss	%ecx, %xmm4
	mulss	%xmm0, %xmm4
	addss	%xmm1, %xmm4
	unpcklps	%xmm4, %xmm3                    # xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
	movlhps	%xmm2, %xmm3                    # xmm3 = xmm3[0],xmm2[0]
	movaps	%xmm3, (%rax)
	incq	%r15
	addq	$16, %rax
	cmpq	$128, %r15
	jne	.LBB2_2
# %bb.3:                                # %.preheader.preheader
	movl	$65536, %edx                    # imm = 0x10000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp3:
	leaq	8(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
.Ltmp4:
# %bb.4:                                # %_ZL9hipMallocI15HIP_vector_typeIfLj4EEE10hipError_tPPT_m.exit
.Ltmp5:
	leaq	24(%rsp), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
.Ltmp6:
# %bb.5:                                # %_ZL9hipMallocI15HIP_vector_typeIfLj4EEE10hipError_tPPT_m.exit63
.Ltmp7:
	leaq	16(%rsp), %rdi
	movl	$65536, %esi                    # imm = 0x10000
	callq	hipMalloc
.Ltmp8:
# %bb.6:                                # %_ZL9hipMallocI15HIP_vector_typeIfLj4EEE10hipError_tPPT_m.exit64
	movq	8(%rsp), %rdi
.Ltmp9:
	movl	$2048, %edx                     # imm = 0x800
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp10:
# %bb.7:
	movq	16(%rsp), %rdi
.Ltmp11:
	movl	$65536, %edx                    # imm = 0x10000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp12:
# %bb.8:
.Ltmp13:
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	movabsq	$4294967328, %rdx               # imm = 0x100000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp14:
# %bb.9:
	testl	%eax, %eax
	jne	.LBB2_11
# %bb.10:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
.Ltmp15:
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$16, %ecx
	movl	$16, %r8d
	movl	$16, %r9d
	movaps	%xmm0, %xmm1
	movaps	%xmm0, %xmm2
	callq	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
.Ltmp16:
.LBB2_11:
.Ltmp17:
	callq	hipDeviceSynchronize
.Ltmp18:
# %bb.12:
.Ltmp19:
	movabsq	$4294967300, %rdi               # imm = 0x100000004
	movabsq	$4294967328, %rdx               # imm = 0x100000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp20:
# %bb.13:
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
.Ltmp21:
	movss	.LCPI2_2(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	callq	_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f
.Ltmp22:
.LBB2_15:
.Ltmp23:
	callq	hipDeviceSynchronize
.Ltmp24:
# %bb.16:
	movq	8(%rsp), %rsi
.Ltmp25:
	movl	$2048, %edx                     # imm = 0x800
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp26:
# %bb.17:
	movq	8(%rsp), %rdi
.Ltmp27:
	callq	hipFree
.Ltmp28:
# %bb.18:
	movq	24(%rsp), %rdi
.Ltmp29:
	callq	hipFree
.Ltmp30:
# %bb.19:
	movq	16(%rsp), %rdi
.Ltmp31:
	callq	hipFree
.Ltmp32:
# %bb.20:
.Ltmp33:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp34:
# %bb.21:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
.Ltmp35:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp36:
# %bb.22:                               # %_ZNSolsEf.exit
.Ltmp37:
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.23:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit65
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rbx), %xmm0
.Ltmp39:
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp40:
# %bb.24:                               # %_ZNSolsEf.exit66
.Ltmp41:
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp42:
# %bb.25:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit67
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rbx), %xmm0
.Ltmp43:
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp44:
# %bb.26:                               # %_ZNSolsEf.exit68
.Ltmp45:
	movq	%rax, %r15
	movl	$.L.str.2, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp46:
# %bb.27:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit69
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
.Ltmp47:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp48:
# %bb.28:                               # %.noexc
.Ltmp49:
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
.Ltmp50:
# %bb.29:                               # %.noexc82
.Ltmp51:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp52:
# %bb.30:                               # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EED2Ev.exit75
	movq	%r14, %rdi
	callq	_ZdlPv
	movq	%rbx, %rdi
	callq	_ZdlPv
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB2_31:
	.cfi_def_cfa_offset 64
.Ltmp2:
	movq	%rax, %r15
	jmp	.LBB2_32
.LBB2_33:                               # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EED2Ev.exit
.Ltmp53:
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	_ZdlPv
.LBB2_32:                               # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EED2Ev.exit79
	movq	%rbx, %rdi
	callq	_ZdlPv
	movq	%r15, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table2:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp1-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp3-.Ltmp1                  #   Call between .Ltmp1 and .Ltmp3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp52-.Ltmp3                 #   Call between .Ltmp3 and .Ltmp52
	.uleb128 .Ltmp53-.Lfunc_begin0          #     jumps to .Ltmp53
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp52-.Lfunc_begin0          # >> Call Site 5 <<
	.uleb128 .Lfunc_end2-.Ltmp52            #   Call between .Ltmp52 and .Lfunc_end2
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff,@object # @_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.section	.rodata,"a",@progbits
	.globl	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.p2align	3, 0x0
_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff:
	.quad	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.size	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff, 8

	.type	_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f,@object # @_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.globl	_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.p2align	3, 0x0
_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f:
	.quad	_Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.size	_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Final position of particle 0: ("
	.size	.L.str, 32

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	", "
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	")"
	.size	.L.str.2, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff"
	.size	.L__unnamed_1, 55

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f"
	.size	.L__unnamed_2, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.addrsig_sym _Z30__device_stub__updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.addrsig_sym _Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff ; -- Begin function _Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.globl	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
	.p2align	8
	.type	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff,@function
_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff: ; @_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
; %bb.0:
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x80, v1
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 4, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
	global_load_b96 v[3:5], v[0:1], off
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[4:5], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s0, s8, 31
	s_ashr_i32 s1, s9, 31
	s_add_i32 s12, s8, s0
	s_ashr_i32 s14, s10, 31
	s_xor_b32 s12, s12, s0
	s_add_i32 s13, s9, s1
	v_cvt_f32_u32_e32 v1, s12
	s_add_i32 s15, s10, s14
	s_xor_b32 s13, s13, s1
	s_xor_b32 s14, s15, s14
	v_cvt_f32_u32_e32 v2, s13
	v_rcp_iflag_f32_e32 v1, v1
	v_cvt_f32_u32_e32 v11, s14
	v_mov_b32_e32 v0, 0
	s_sub_i32 s15, 0, s12
	v_rcp_iflag_f32_e32 v2, v2
	s_sub_i32 s16, 0, s13
	v_rcp_iflag_f32_e32 v11, v11
	s_sub_i32 s17, 0, s14
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, 0x4f7ffffe, v11
	v_cvt_u32_f32_e32 v25, v11
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v8, null, s11, s11, v3
	v_div_scale_f32 v9, null, s4, s4, v4
	v_div_scale_f32 v10, null, s5, s5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v12, v8
	v_rcp_f32_e32 v13, v9
	v_div_scale_f32 v15, vcc_lo, v3, s11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v14, v10
	v_div_scale_f32 v16, s0, v4, s4, v4
	v_div_scale_f32 v20, s1, v5, s5, v5
	v_fma_f32 v17, -v8, v12, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v9, v13, 1.0
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_fma_f32 v19, -v10, v14, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v12, v17, v12 :: v_dual_fmac_f32 v13, v18, v13
	v_cvt_u32_f32_e32 v17, v1
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v1, v15, v12 :: v_dual_mul_f32 v18, v16, v13
	v_mul_lo_u32 v21, s15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v11, s16, v2
	v_fma_f32 v22, -v8, v1, v15
	v_fmac_f32_e32 v14, v19, v14
	v_fma_f32 v23, -v9, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, v22, v12
	v_dual_mul_f32 v19, v20, v14 :: v_dual_fmac_f32 v18, v23, v13
	v_mul_hi_u32 v21, v17, v21
	v_mul_lo_u32 v22, s17, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v8, -v8, v1, v15
	v_fma_f32 v24, -v10, v19, v20
	v_fma_f32 v9, -v9, v18, v16
	v_mul_hi_u32 v11, v2, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v1, v8, v12, v1
	v_fmac_f32_e32 v19, v24, v14
	s_mov_b32 vcc_lo, s0
	v_mul_hi_u32 v12, v25, v22
	v_div_fmas_f32 v8, v9, v13, v18
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v10, -v10, v19, v20
	v_div_fixup_f32 v13, v1, s11, v3
	v_mov_b32_e32 v1, 0
	v_div_fixup_f32 v8, v8, s4, v4
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v11, v2, v11
	v_div_fmas_f32 v9, v10, v14, v19
	v_cvt_i32_f32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_i32_f32_e32 v8, v8
	v_add_nc_u32_e32 v10, v17, v21
	v_add_nc_u32_e32 v12, v25, v12
	v_div_fixup_f32 v9, v9, s5, v5
	v_add_nc_u32_e32 v13, s8, v13
	v_add_nc_u32_e32 v14, s9, v8
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v9, v9
	v_add_nc_u32_e32 v15, s10, v9
.LBB0_2:                                ; %.preheader60
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_4 Depth 3
	v_add_nc_u32_e32 v8, s0, v13
	s_mov_b32 s1, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v8, v8, v9
	v_mul_hi_u32 v16, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v16, v16, s12
	v_sub_nc_u32_e32 v8, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v16, s12, v8
	v_cmp_le_u32_e32 vcc_lo, s12, v8
	v_cndmask_b32_e32 v8, v8, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v16, s12, v8
	v_cmp_le_u32_e32 vcc_lo, s12, v8
	v_cndmask_b32_e32 v8, v8, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v8, v8, v9
	v_sub_nc_u32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v9, v8
	v_add_f32_e32 v9, 0.5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v9, s11, v3
	v_and_b32_e32 v16, 0x7fffffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v17, null, s11, s11, v16
	v_div_scale_f32 v16, vcc_lo, v16, s11, v16
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v18
	v_mul_f32_e32 v19, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v17, v19, v16
	v_fmac_f32_e32 v19, v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v17, v19, v16
	v_div_fmas_f32 v16, v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v9, v16, s11, |v9|
	v_sub_f32_e32 v16, 1.0, v9
.LBB0_3:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_4 Depth 3
	v_add_nc_u32_e32 v9, s1, v14
	s_mov_b32 s10, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v9
	v_add_nc_u32_e32 v9, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v9, v9, v17
	v_mul_hi_u32 v18, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v18, s13
	v_sub_nc_u32_e32 v9, v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v18, s13, v9
	v_cmp_le_u32_e32 vcc_lo, s13, v9
	v_cndmask_b32_e32 v9, v9, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v18, s13, v9
	v_cmp_le_u32_e32 vcc_lo, s13, v9
	v_cndmask_b32_e32 v9, v9, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v9, v9, v17
	v_sub_nc_u32_e32 v9, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v17, v9
	v_add_f32_e32 v17, 0.5, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v17, s4, v4
	v_and_b32_e32 v18, 0x7fffffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v19, null, s4, s4, v18
	v_div_scale_f32 v18, vcc_lo, v18, s4, v18
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v19, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v21, v20
	v_mul_f32_e32 v21, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v22, -v19, v21, v18
	v_fmac_f32_e32 v21, v22, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v19, v21, v18
	v_div_fmas_f32 v18, v18, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v17, v18, s4, |v17|
	v_sub_f32_e32 v17, 1.0, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v17, v16, v17
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v18, s10, v15
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s10, 2
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v18, v18, v19
	v_xor_b32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v20, v18, v12
	v_mul_lo_u32 v20, v20, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, v18, v20
	v_subrev_nc_u32_e32 v20, s14, v18
	v_cmp_le_u32_e32 vcc_lo, s14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v18, v18, v20, vcc_lo
	v_subrev_nc_u32_e32 v20, s14, v18
	v_cmp_le_u32_e32 vcc_lo, s14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v18, v18, v20, vcc_lo
	v_xor_b32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v21, v18, v19
	v_mad_u64_u32 v[18:19], null, v21, s9, v[9:10]
	v_cvt_f32_i32_e32 v21, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v21, 0.5, v21
	v_mad_u64_u32 v[19:20], null, v18, s8, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v21, s5, v5
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v22, 0x7fffffff, v21
	v_lshlrev_b64 v[18:19], 4, v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v23, null, s5, s5, v22
	v_rcp_f32_e32 v24, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, s2, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
	v_div_scale_f32 v22, vcc_lo, v22, s5, v22
	global_load_b96 v[18:20], v[18:19], off
	v_fma_f32 v25, -v23, v24, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v25, v24
	v_mul_f32_e32 v25, v22, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v23, v25, v22
	v_fmac_f32_e32 v25, v26, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v22, -v23, v25, v22
	v_div_fmas_f32 v22, v22, v24, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v21, v22, s5, |v21|
	v_sub_f32_e32 v21, 1.0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v17, v21
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, v20, v21
	v_fmac_f32_e32 v0, v18, v21
	v_fmac_f32_e32 v1, v19, v21
	s_cbranch_scc0 .LBB0_4
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 2
	s_cbranch_scc0 .LBB0_3
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 2
	s_cbranch_scc0 .LBB0_2
; %bb.7:
	v_add_co_u32 v4, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
	v_mov_b32_e32 v3, 0
	global_store_b128 v[4:5], v[0:3], off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff, .Lfunc_end0-_Z13computeForcesP15HIP_vector_typeIfLj4EES1_S1_iiifff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1472
; NumSgprs: 20
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f ; -- Begin function _Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.globl	_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
	.p2align	8
	.type	_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f,@function
_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f: ; @_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x80, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b32 s0, s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v3, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v1, vcc_lo
	global_load_b96 v[0:2], v[6:7], off
	global_load_b96 v[3:5], v[3:4], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v0, s0, v3, v0
	v_fma_f32 v1, s0, v4, v1
	v_fmac_f32_e32 v2, s0, v5
	global_store_b96 v[6:7], v[0:2], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f, .Lfunc_end1-_Z15updatePositionsP15HIP_vector_typeIfLj4EES1_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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  - 2
...

	.end_amdgpu_metadata
