#include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>

#define BLOCK_SIZE 16
#define FILTER_SIZE 64
#define TILE_WIDTH BLOCK_SIZE + FILTER_SIZE - 1

// Kernel to perform sparse convolution
__global__ void sparseConvolutionKernel(
    const float* __restrict__ d_input, const int* __restrict__ d_input_indices,
    const float* __restrict__ d_filter, float* __restrict__ d_output,
    int num_nonzero, int input_width, int input_height, int output_width, int output_height) {

    __shared__ float s_input[TILE_WIDTH][TILE_WIDTH];
    __shared__ float s_filter[FILTER_SIZE][FILTER_SIZE];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int row_o = by * BLOCK_SIZE + ty;
    int col_o = bx * BLOCK_SIZE + tx;

    int row_i = row_o - FILTER_SIZE / 2;
    int col_i = col_o - FILTER_SIZE / 2;

    // Load filter into shared memory
    if (ty < FILTER_SIZE && tx < FILTER_SIZE) {
        s_filter[ty][tx] = d_filter[ty * FILTER_SIZE + tx];
    }
    __syncthreads();

    float accum = 0.0f;

    // Iterate over non-zero elements of the input
    for (int n = 0; n < num_nonzero; ++n) {
        int input_row = d_input_indices[n * 2];
        int input_col = d_input_indices[n * 2 + 1];
        float input_val = d_input[n];

        int local_row = input_row - row_i;
        int local_col = input_col - col_i;

        // Load input into shared memory with bank conflict avoidance
        if (input_row >= row_i && input_row < row_i + TILE_WIDTH &&
            input_col >= col_i && input_col < col_i + TILE_WIDTH) {
            s_input[local_row][local_col] = input_val;
        } else {
            s_input[local_row][local_col] = 0.0f;
        }
        __syncthreads();

        // Perform convolution
        if (row_o < output_height && col_o < output_width) {
            for (int f = 0; f < FILTER_SIZE; ++f) {
                for (int g = 0; g < FILTER_SIZE; ++g) {
                    accum += s_filter[f][g] * s_input[ty + f][tx + g];
                }
            }
        }
        __syncthreads();
    }

    // Store result
    if (row_o < output_height && col_o < output_width) {
        d_output[row_o * output_width + col_o] = accum;
    }
}

int main() {
    // Example input and filter sizes
    int input_width = 128, input_height = 128;
    int output_width = input_width - FILTER_SIZE + 1, output_height = input_height - FILTER_SIZE + 1;
    int num_nonzero = 100; // Number of non-zero elements in the input

    // Allocate and initialize host memory
    float* h_input = new float[num_nonzero];
    int* h_input_indices = new int[num_nonzero * 2];
    float* h_filter = new float[FILTER_SIZE * FILTER_SIZE];
    float* h_output = new float[output_width * output_height];

    // Initialize input, filter, and output with example data
    for (int i = 0; i < num_nonzero; ++i) {
        h_input[i] = 1.0f; // Example value
        h_input_indices[i * 2] = i / input_width; // Example row index
        h_input_indices[i * 2 + 1] = i % input_width; // Example column index
    }
    for (int i = 0; i < FILTER_SIZE * FILTER_SIZE; ++i) {
        h_filter[i] = 1.0f / (FILTER_SIZE * FILTER_SIZE); // Example value
    }
    for (int i = 0; i < output_width * output_height; ++i) {
        h_output[i] = 0.0f;
    }

    // Allocate device memory
    float* d_input, *d_filter, *d_output;
    int* d_input_indices;
    cudaError_t err;

    err = cudaMalloc((void**)&d_input, num_nonzero * sizeof(float));
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }
    err = cudaMalloc((void**)&d_input_indices, num_nonzero * 2 * sizeof(int));
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }
    err = cudaMalloc((void**)&d_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float));
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }
    err = cudaMalloc((void**)&d_output, output_width * output_height * sizeof(float));
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }

    // Copy data from host to device
    err = cudaMemcpy(d_input, h_input, num_nonzero * sizeof(float), cudaMemcpyHostToDevice);
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }
    err = cudaMemcpy(d_input_indices, h_input_indices, num_nonzero * 2 * sizeof(int), cudaMemcpyHostToDevice);
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }
    err = cudaMemcpy(d_filter, h_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float), cudaMemcpyHostToDevice);
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }

    // Launch kernel
    dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
    dim3 blocksPerGrid((output_width + BLOCK_SIZE - 1) / BLOCK_SIZE, (output_height + BLOCK_SIZE - 1) / BLOCK_SIZE);

    sparseConvolutionKernel<<<blocksPerGrid, threadsPerBlock>>>(
        d_input, d_input_indices, d_filter, d_output, num_nonzero, input_width, input_height, output_width, output_height);

    // Check for kernel launch errors
    err = cudaGetLastError();
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }

    // Copy result from device to host
    err = cudaMemcpy(h_output, d_output, output_width * output_height * sizeof(float), cudaMemcpyDeviceToHost);
    if (err != cudaSuccess) { std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl; return -1; }

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_input_indices);
    cudaFree(d_filter);
    cudaFree(d_output);

    // Free host memory
    delete[] h_input;
    delete[] h_input_indices;
    delete[] h_filter;
    delete[] h_output;

    std::cout << "Sparse convolution completed successfully." << std::endl;

    return 0;
}
	.file	"tmpxft_00034d5b_00000000-6_cuda_code_080004.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4292:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4292:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z57__device_stub__Z23sparseConvolutionKernelPKfPKiS0_PfiiiiiPKfPKiS0_Pfiiiii
	.type	_Z57__device_stub__Z23sparseConvolutionKernelPKfPKiS0_PfiiiiiPKfPKiS0_Pfiiiii, @function
_Z57__device_stub__Z23sparseConvolutionKernelPKfPKiS0_PfiiiiiPKfPKiS0_Pfiiiii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L3:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z57__device_stub__Z23sparseConvolutionKernelPKfPKiS0_PfiiiiiPKfPKiS0_Pfiiiii, .-_Z57__device_stub__Z23sparseConvolutionKernelPKfPKiS0_PfiiiiiPKfPKiS0_Pfiiiii
	.globl	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.type	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii, @function
_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z23sparseConvolutionKernelPKfPKiS0_PfiiiiiPKfPKiS0_Pfiiiii
	.cfi_endproc
.LFE3661:
	.size	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii, .-_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"CUDA error: "
.LC3:
	.string	"Sparse convolution completed successfully."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$400, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$800, %edi
	movq	%rax, %r13
	call	_Znam@PLT
	movl	$16384, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$16900, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movss	.LC0(%rip), %xmm0
	movq	%rax, %rbx
	xorl	%eax, %eax
.L10:
	xorl	%edx, %edx
	movl	%eax, 4(%rbp,%rax,8)
	movl	%edx, 0(%rbp,%rax,8)
	movss	%xmm0, 0(%r13,%rax,4)
	incq	%rax
	cmpq	$100, %rax
	jne	.L10
	movss	.LC1(%rip), %xmm0
	xorl	%eax, %eax
.L11:
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$4096, %rax
	jne	.L11
	xorl	%eax, %eax
	movl	$4225, %ecx
	movq	%rbx, %rdi
	movl	$400, %esi
	rep stosl
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	leaq	24(%rsp), %rdi
	movl	$800, %esi
	call	cudaMalloc@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	je	.L14
.L28:
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	orl	$-1, %eax
	jmp	.L9
.L14:
	leaq	8(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	leaq	16(%rsp), %rdi
	movl	$16900, %esi
	call	cudaMalloc@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$400, %edx
	movq	%r13, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$800, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$16384, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movabsq	$21474836485, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	%rax
	.cfi_def_cfa_offset 120
	movl	$128, %r9d
	movl	$100, %r8d
	pushq	$65
	.cfi_def_cfa_offset 128
	pushq	$65
	.cfi_def_cfa_offset 136
	pushq	$128
	.cfi_def_cfa_offset 144
	movq	48(%rsp), %rcx
	movq	40(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z57__device_stub__Z23sparseConvolutionKernelPKfPKiS0_PfiiiiiPKfPKiS0_Pfiiiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 112
.L21:
	call	cudaGetLastError@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$16900, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	.L28
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	leaq	.LC3(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	xorl	%eax, %eax
.L9:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC1:
	.long	964689920
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>


#define BLOCK_SIZE 16
#define FILTER_SIZE 64
#define TILE_WIDTH BLOCK_SIZE + FILTER_SIZE - 1

// Kernel to perform sparse convolution
__global__ void sparseConvolutionKernel(
    const float* __restrict__ d_input, const int* __restrict__ d_input_indices,
    const float* __restrict__ d_filter, float* __restrict__ d_output,
    int num_nonzero, int input_width, int input_height, int output_width, int output_height) {

    __shared__ float s_input[TILE_WIDTH][TILE_WIDTH];
    __shared__ float s_filter[FILTER_SIZE][FILTER_SIZE];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int row_o = by * BLOCK_SIZE + ty;
    int col_o = bx * BLOCK_SIZE + tx;

    int row_i = row_o - FILTER_SIZE / 2;
    int col_i = col_o - FILTER_SIZE / 2;

    // Load filter into shared memory
    if (ty < FILTER_SIZE && tx < FILTER_SIZE) {
        s_filter[ty][tx] = d_filter[ty * FILTER_SIZE + tx];
    }
    __syncthreads();

    float accum = 0.0f;

    // Iterate over non-zero elements of the input
    for (int n = 0; n < num_nonzero; ++n) {
        int input_row = d_input_indices[n * 2];
        int input_col = d_input_indices[n * 2 + 1];
        float input_val = d_input[n];

        int local_row = input_row - row_i;
        int local_col = input_col - col_i;

        // Load input into shared memory with bank conflict avoidance
        if (input_row >= row_i && input_row < row_i + TILE_WIDTH &&
            input_col >= col_i && input_col < col_i + TILE_WIDTH) {
            s_input[local_row][local_col] = input_val;
        } else {
            s_input[local_row][local_col] = 0.0f;
        }
        __syncthreads();

        // Perform convolution
        if (row_o < output_height && col_o < output_width) {
            for (int f = 0; f < FILTER_SIZE; ++f) {
                for (int g = 0; g < FILTER_SIZE; ++g) {
                    accum += s_filter[f][g] * s_input[ty + f][tx + g];
                }
            }
        }
        __syncthreads();
    }

    // Store result
    if (row_o < output_height && col_o < output_width) {
        d_output[row_o * output_width + col_o] = accum;
    }
}

int main() {
    // Example input and filter sizes
    int input_width = 128, input_height = 128;
    int output_width = input_width - FILTER_SIZE + 1, output_height = input_height - FILTER_SIZE + 1;
    int num_nonzero = 100; // Number of non-zero elements in the input

    // Allocate and initialize host memory
    float* h_input = new float[num_nonzero];
    int* h_input_indices = new int[num_nonzero * 2];
    float* h_filter = new float[FILTER_SIZE * FILTER_SIZE];
    float* h_output = new float[output_width * output_height];

    // Initialize input, filter, and output with example data
    for (int i = 0; i < num_nonzero; ++i) {
        h_input[i] = 1.0f; // Example value
        h_input_indices[i * 2] = i / input_width; // Example row index
        h_input_indices[i * 2 + 1] = i % input_width; // Example column index
    }
    for (int i = 0; i < FILTER_SIZE * FILTER_SIZE; ++i) {
        h_filter[i] = 1.0f / (FILTER_SIZE * FILTER_SIZE); // Example value
    }
    for (int i = 0; i < output_width * output_height; ++i) {
        h_output[i] = 0.0f;
    }

    // Allocate device memory
    float* d_input, *d_filter, *d_output;
    int* d_input_indices;
    hipError_t err;

    err = hipMalloc((void**)&d_input, num_nonzero * sizeof(float));
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }
    err = hipMalloc((void**)&d_input_indices, num_nonzero * 2 * sizeof(int));
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }
    err = hipMalloc((void**)&d_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float));
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }
    err = hipMalloc((void**)&d_output, output_width * output_height * sizeof(float));
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }

    // Copy data from host to device
    err = hipMemcpy(d_input, h_input, num_nonzero * sizeof(float), hipMemcpyHostToDevice);
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }
    err = hipMemcpy(d_input_indices, h_input_indices, num_nonzero * 2 * sizeof(int), hipMemcpyHostToDevice);
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }
    err = hipMemcpy(d_filter, h_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float), hipMemcpyHostToDevice);
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }

    // Launch kernel
    dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
    dim3 blocksPerGrid((output_width + BLOCK_SIZE - 1) / BLOCK_SIZE, (output_height + BLOCK_SIZE - 1) / BLOCK_SIZE);

    sparseConvolutionKernel<<<blocksPerGrid, threadsPerBlock>>>(
        d_input, d_input_indices, d_filter, d_output, num_nonzero, input_width, input_height, output_width, output_height);

    // Check for kernel launch errors
    err = hipGetLastError();
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }

    // Copy result from device to host
    err = hipMemcpy(h_output, d_output, output_width * output_height * sizeof(float), hipMemcpyDeviceToHost);
    if (err != hipSuccess) { std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl; return -1; }

    // Free device memory
    hipFree(d_input);
    hipFree(d_input_indices);
    hipFree(d_filter);
    hipFree(d_output);

    // Free host memory
    delete[] h_input;
    delete[] h_input_indices;
    delete[] h_filter;
    delete[] h_output;

    std::cout << "Sparse convolution completed successfully." << std::endl;

    return 0;
}
	.text
	.file	"cuda_code_080004.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.type	_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii,@function
_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii: # @_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii, .Lfunc_end0-_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$400, %edi                      # imm = 0x190
	callq	_Znam
	movq	%rax, %rbx
	movl	$800, %edi                      # imm = 0x320
	callq	_Znam
	movq	%rax, %r14
	movl	$16384, %edi                    # imm = 0x4000
	callq	_Znam
	movq	%rax, %r15
	movl	$16900, %edi                    # imm = 0x4204
	callq	_Znam
	movq	%rax, %r12
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rbx,%rax,4)      # imm = 0x3F800000
	movl	$0, (%r14,%rax,8)
	movl	%eax, 4(%r14,%rax,8)
	incq	%rax
	cmpq	$100, %rax
	jne	.LBB1_1
# %bb.2:                                # %.preheader105.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader105
                                        # =>This Inner Loop Header: Depth=1
	movl	$964689920, (%r15,%rax,4)       # imm = 0x39800000
	incq	%rax
	cmpq	$4096, %rax                     # imm = 0x1000
	jne	.LBB1_3
# %bb.4:                                # %.preheader.preheader
	movl	$16900, %edx                    # imm = 0x4204
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	24(%rsp), %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.5:
	movq	%rsp, %rdi
	movl	$800, %esi                      # imm = 0x320
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.6:
	leaq	16(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	leaq	8(%rsp), %rdi
	movl	$16900, %esi                    # imm = 0x4204
	callq	hipMalloc
	testl	%eax, %eax
	je	.LBB1_14
.LBB1_8:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_10
# %bb.9:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_11
.LBB1_10:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_11:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_12:
	movl	$-1, %eax
.LBB1_13:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_14:
	.cfi_def_cfa_offset 80
	movq	24(%rsp), %rdi
	movl	$400, %edx                      # imm = 0x190
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.15:
	movq	(%rsp), %rdi
	movl	$800, %edx                      # imm = 0x320
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.16:
	movq	16(%rsp), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.17:
	movabsq	$21474836485, %rdi              # imm = 0x500000005
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_19
# %bb.18:
	movq	24(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$65, %eax
	movl	$100, %r8d
	movl	$128, %r9d
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	$128
	.cfi_adjust_cfa_offset 8
	callq	_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_19:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_21
# %bb.20:
	movq	8(%rsp), %rsi
	movl	$16900, %edx                    # imm = 0x4204
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB1_22
.LBB1_21:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cerr, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB1_12
.LBB1_22:
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_ZdaPv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$42, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	xorl	%eax, %eax
	jmp	.LBB1_13
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii,@object # @_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.p2align	3, 0x0
_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii:
	.quad	_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.size	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Sparse convolution completed successfully."
	.size	.L.str.1, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii"
	.size	.L__unnamed_1, 44

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii ; -- Begin function _Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.globl	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
	.p2align	8
	.type	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii,@function
_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii: ; @_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
; %bb.0:
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v7, 2, v3
	v_or_b32_e32 v0, v2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[4:5], s[0:1], 0x10
	v_lshlrev_b32_e32 v0, 6, v2
	v_lshl_add_u32 v1, v2, 8, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_lshl_u32 v0, v0, v3, 2
	s_waitcnt lgkmcnt(0)
	global_load_b32 v0, v0, s[4:5]
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v0 offset:24976
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x2
	s_load_b64 s[10:11], s[0:1], 0x2c
	s_load_b32 s16, s[0:1], 0x20
	s_load_b64 s[8:9], s[0:1], 0x18
	v_lshl_add_u32 v1, s15, 4, v2
	v_lshl_add_u32 v0, s14, 4, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s11, v1
	v_cmp_gt_i32_e64 s2, s10, v0
	s_cmp_lt_i32 s16, 1
	s_cbranch_scc1 .LBB0_12
; %bb.3:                                ; %.lr.ph
	s_load_b128 s[4:7], s[0:1], 0x0
	v_subrev_nc_u32_e32 v3, 32, v1
	v_subrev_nc_u32_e32 v4, 32, v0
	v_add_nc_u32_e32 v5, 47, v1
	v_add_nc_u32_e32 v6, 47, v0
	v_mad_u32_u24 v7, 0x13c, v2, v7
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, 0
	s_and_b32 s17, vcc_lo, s2
	s_mov_b32 s12, s3
.LBB0_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
                                        ;       Child Loop BB0_9 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s2, s12, 1
	v_mov_b32_e32 v8, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	s_load_b64 s[14:15], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, s14, v3
	v_cmp_ge_i32_e64 s0, s15, v4
	v_cmp_lt_i32_e64 s1, s14, v5
	v_cmp_lt_i32_e64 s2, s15, v6
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s13, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[18:19], s[12:13], 2
	s_add_u32 s18, s4, s18
	s_addc_u32 s19, s5, s19
	s_load_b32 s1, s[18:19], 0x0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v8, s1
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_nc_u32_e32 v9, s14, v1
	v_sub_nc_u32_e32 v10, s15, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v9, 0x13c, v9
	v_lshl_add_u32 v9, v10, 2, v9
	ds_store_b32 v9, v8 offset:10240
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s17
	s_cbranch_execz .LBB0_11
; %bb.7:                                ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_mov_b32_e32 v8, v7
	s_mov_b32 s1, 0
	s_movk_i32 s2, 0x6190
.LBB0_8:                                ; %.preheader
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_9 Depth 3
	s_mov_b32 s13, 0
.LBB0_9:                                ;   Parent Loop BB0_4 Depth=1
                                        ;     Parent Loop BB0_8 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s14, s2, s13
	v_dual_mov_b32 v10, s14 :: v_dual_add_nc_u32 v9, s13, v8
	s_add_i32 s13, s13, 4
	ds_load_b32 v9, v9
	ds_load_b32 v10, v10
	s_cmpk_eq_i32 s13, 0x100
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v10, v9
	s_cbranch_scc0 .LBB0_9
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=2
	v_add_nc_u32_e32 v8, 0x13c, v8
	s_add_i32 s1, s1, 1
	s_addk_i32 s2, 0x100
	s_cmp_eq_u32 s1, 64
	s_cbranch_scc0 .LBB0_8
.LBB0_11:                               ; %Flow111
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, s16
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
	s_branch .LBB0_13
.LBB0_12:
	v_mov_b32_e32 v2, 0
.LBB0_13:                               ; %Flow113
	v_cmp_gt_i32_e32 vcc_lo, s11, v1
	v_cmp_gt_i32_e64 s0, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_mad_u64_u32 v[3:4], null, v1, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
		.amdhsa_group_segment_fixed_size 41360
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 52
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii, .Lfunc_end0-_Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 664
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 41360 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 41360
    .kernarg_segment_align: 8
    .kernarg_segment_size: 52
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z23sparseConvolutionKernelPKfPKiS0_Pfiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
