#include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>
#include <device_launch_parameters.h>

// Define constants for the convolutional layers
#define NUM_CONV_LAYERS 4
#define FILTER_WIDTH 3
#define FILTER_HEIGHT 3
#define BATCH_SIZE 64
#define INPUT_CHANNELS 3
#define OUTPUT_CHANNELS 32
#define INPUT_WIDTH 32
#define INPUT_HEIGHT 32
#define OUTPUT_WIDTH 30
#define OUTPUT_HEIGHT 30

// CUDA kernel for backpropagation in convolutional layers
__global__ void convBackpropKernel(float* d_input, float* d_output, float* d_filters, float* d_gradOutput, float* d_gradInput, float* d_gradFilters) {
    // Define shared memory for input and filters to improve memory access pattern
    __shared__ float s_input[FILTER_HEIGHT][FILTER_WIDTH];
    __shared__ float s_filters[FILTER_HEIGHT][FILTER_WIDTH];

    // Thread identifiers
    int bx = blockIdx.x, by = blockIdx.y, bz = blockIdx.z;
    int tx = threadIdx.x, ty = threadIdx.y;

    // Calculate output element index
    int ox = tx + bx * blockDim.x;
    int oy = ty + by * blockDim.y;
    int oc = bz;
    int ic = tx + ty * blockDim.x; // Assuming a simple mapping for demonstration

    // Calculate gradient input element index
    int gi_ox = ox + FILTER_WIDTH / 2;
    int gi_oy = oy + FILTER_HEIGHT / 2;

    // Initialize gradient input and gradient filters to zero
    if (gi_ox < INPUT_WIDTH && gi_oy < INPUT_HEIGHT && oc < OUTPUT_CHANNELS) {
        d_gradInput[gi_ox + gi_oy * INPUT_WIDTH + oc * INPUT_WIDTH * INPUT_HEIGHT] = 0.0f;
    }
    if (tx < FILTER_WIDTH && ty < FILTER_HEIGHT && oc < OUTPUT_CHANNELS && ic < INPUT_CHANNELS) {
        d_gradFilters[tx + ty * FILTER_WIDTH + oc * FILTER_WIDTH * FILTER_HEIGHT + ic * FILTER_WIDTH * FILTER_HEIGHT * OUTPUT_CHANNELS] = 0.0f;
    }

    // Synchronize to ensure all threads have initialized their data
    __syncthreads();

    // Load input and filter data into shared memory
    if (gi_ox < INPUT_WIDTH && gi_oy < INPUT_HEIGHT && ic < INPUT_CHANNELS) {
        s_input[ty][tx] = d_input[gi_ox + gi_oy * INPUT_WIDTH + ic * INPUT_WIDTH * INPUT_HEIGHT];
    }
    if (tx < FILTER_WIDTH && ty < FILTER_HEIGHT && oc < OUTPUT_CHANNELS && ic < INPUT_CHANNELS) {
        s_filters[ty][tx] = d_filters[tx + ty * FILTER_WIDTH + oc * FILTER_WIDTH * FILTER_HEIGHT + ic * FILTER_WIDTH * FILTER_HEIGHT * OUTPUT_CHANNELS];
    }

    // Synchronize to ensure all data is loaded into shared memory
    __syncthreads();

    // Compute gradient input and gradient filters
    if (ox < OUTPUT_WIDTH && oy < OUTPUT_HEIGHT && oc < OUTPUT_CHANNELS) {
        float gradOutput = d_gradOutput[ox + oy * OUTPUT_WIDTH + oc * OUTPUT_WIDTH * OUTPUT_HEIGHT];
        for (int fy = 0; fy < FILTER_HEIGHT; ++fy) {
            for (int fx = 0; fx < FILTER_WIDTH; ++fx) {
                int iix = gi_ox - fx;
                int iiy = gi_oy - fy;
                if (iix >= 0 && iix < INPUT_WIDTH && iiy >= 0 && iiy < INPUT_HEIGHT) {
                    atomicAdd(&d_gradInput[iix + iiy * INPUT_WIDTH + ic * INPUT_WIDTH * INPUT_HEIGHT], gradOutput * s_filters[fy][fx]);
                    atomicAdd(&d_gradFilters[fx + fy * FILTER_WIDTH + oc * FILTER_WIDTH * FILTER_HEIGHT + ic * FILTER_WIDTH * FILTER_HEIGHT * OUTPUT_CHANNELS], gradOutput * s_input[fy][fx]);
                }
            }
        }
    }
}

int main() {
    // Allocate memory for input, output, filters, and gradients on host
    float* h_input = new float[BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT];
    float* h_output = new float[BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT];
    float* h_filters = new float[OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT];
    float* h_gradOutput = new float[BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT];
    float* h_gradInput = new float[BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT];
    float* h_gradFilters = new float[OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT];

    // Initialize host memory (random values for demonstration)
    for (int i = 0; i < BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT; ++i) h_input[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT; ++i) h_output[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT; ++i) h_filters[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT; ++i) h_gradOutput[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT; ++i) h_gradInput[i] = 0.0f;
    for (int i = 0; i < OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT; ++i) h_gradFilters[i] = 0.0f;

    // Allocate memory for input, output, filters, and gradients on device
    float* d_input, *d_output, *d_filters, *d_gradOutput, *d_gradInput, *d_gradFilters;
    cudaMalloc((void**)&d_input, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float));
    cudaMalloc((void**)&d_output, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float));
    cudaMalloc((void**)&d_filters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float));
    cudaMalloc((void**)&d_gradOutput, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float));
    cudaMalloc((void**)&d_gradInput, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float));
    cudaMalloc((void**)&d_gradFilters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float));

    // Copy data from host to device
    cudaMemcpy(d_input, h_input, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_output, h_output, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_filters, h_filters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_gradOutput, h_gradOutput, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float), cudaMemcpyHostToDevice);

    // Define block and grid dimensions
    dim3 blockSize(FILTER_WIDTH, FILTER_HEIGHT);
    dim3 gridSize((OUTPUT_WIDTH + FILTER_WIDTH - 1) / FILTER_WIDTH, (OUTPUT_HEIGHT + FILTER_HEIGHT - 1) / FILTER_HEIGHT, OUTPUT_CHANNELS);

    // Launch the kernel
    convBackpropKernel<<<gridSize, blockSize>>>(d_input, d_output, d_filters, d_gradOutput, d_gradInput, d_gradFilters);

    // Check for errors in kernel launch
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        std::cerr << "CUDA error: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    cudaMemcpy(h_gradInput, d_gradInput, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(h_gradFilters, d_gradFilters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float), cudaMemcpyDeviceToHost);

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_output);
    cudaFree(d_filters);
    cudaFree(d_gradOutput);
    cudaFree(d_gradInput);
    cudaFree(d_gradFilters);

    // Free host memory
    delete[] h_input;
    delete[] h_output;
    delete[] h_filters;
    delete[] h_gradOutput;
    delete[] h_gradInput;
    delete[] h_gradFilters;

    return 0;
}
	.file	"tmpxft_00004eeb_00000000-6_cuda_code_065484.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_S_PfS_S_S_S_S_
	.type	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_S_PfS_S_S_S_S_, @function
_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_S_PfS_S_S_S_S_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18convBackpropKernelPfS_S_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_S_PfS_S_S_S_S_, .-_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_S_PfS_S_S_S_S_
	.globl	_Z18convBackpropKernelPfS_S_S_S_S_
	.type	_Z18convBackpropKernelPfS_S_S_S_S_, @function
_Z18convBackpropKernelPfS_S_S_S_S_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_S_PfS_S_S_S_S_
	.cfi_endproc
.LFE3661:
	.size	_Z18convBackpropKernelPfS_S_S_S_S_, .-_Z18convBackpropKernelPfS_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"CUDA error: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$786432, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$7372800, %edi
	movq	%rax, %r15
	call	_Znam@PLT
	movl	$3456, %edi
	movq	%rax, %r14
	call	_Znam@PLT
	movl	$7372800, %edi
	movq	%rax, %r13
	call	_Znam@PLT
	movl	$786432, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movl	$3456, %edi
	movq	%rax, 8(%rsp)
	call	_Znam@PLT
	movq	%rax, %rbx
.L9:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, (%r15,%rbp,4)
	incq	%rbp
	cmpq	$196608, %rbp
	jne	.L9
	xorl	%ebp, %ebp
.L10:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, (%r14,%rbp,4)
	incq	%rbp
	cmpq	$1843200, %rbp
	jne	.L10
	xorl	%ebp, %ebp
.L11:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, 0(%r13,%rbp,4)
	incq	%rbp
	cmpq	$864, %rbp
	jne	.L11
	xorl	%ebp, %ebp
.L12:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, (%r12,%rbp,4)
	incq	%rbp
	cmpq	$1843200, %rbp
	jne	.L12
	movq	8(%rsp), %rdi
	xorl	%eax, %eax
	movl	$196608, %ecx
	movl	$786432, %esi
	rep stosl
	movl	$864, %ecx
	movq	%rbx, %rdi
	rep stosl
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$7372800, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$3456, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$7372800, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$786432, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$3456, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$786432, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$7372800, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$3456, %edx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$7372800, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$12884901891, %rdx
	movl	$32, %esi
	movabsq	$42949672970, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	56(%rsp), %r9
	movq	48(%rsp), %r8
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z48__device_stub__Z18convBackpropKernelPfS_S_S_S_S_PfS_S_S_S_S_
.L13:
	call	cudaGetLastError@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L14
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	orl	$-1, %eax
	jmp	.L8
.L14:
	movq	48(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$786432, %edx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$3456, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r15, %rdi
	call	_ZdaPv@PLT
	movq	%r14, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	8(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	xorl	%eax, %eax
.L8:
	movq	88(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z18convBackpropKernelPfS_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convBackpropKernelPfS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>



// Define constants for the convolutional layers
#define NUM_CONV_LAYERS 4
#define FILTER_WIDTH 3
#define FILTER_HEIGHT 3
#define BATCH_SIZE 64
#define INPUT_CHANNELS 3
#define OUTPUT_CHANNELS 32
#define INPUT_WIDTH 32
#define INPUT_HEIGHT 32
#define OUTPUT_WIDTH 30
#define OUTPUT_HEIGHT 30

// CUDA kernel for backpropagation in convolutional layers
__global__ void convBackpropKernel(float* d_input, float* d_output, float* d_filters, float* d_gradOutput, float* d_gradInput, float* d_gradFilters) {
    // Define shared memory for input and filters to improve memory access pattern
    __shared__ float s_input[FILTER_HEIGHT][FILTER_WIDTH];
    __shared__ float s_filters[FILTER_HEIGHT][FILTER_WIDTH];

    // Thread identifiers
    int bx = blockIdx.x, by = blockIdx.y, bz = blockIdx.z;
    int tx = threadIdx.x, ty = threadIdx.y;

    // Calculate output element index
    int ox = tx + bx * blockDim.x;
    int oy = ty + by * blockDim.y;
    int oc = bz;
    int ic = tx + ty * blockDim.x; // Assuming a simple mapping for demonstration

    // Calculate gradient input element index
    int gi_ox = ox + FILTER_WIDTH / 2;
    int gi_oy = oy + FILTER_HEIGHT / 2;

    // Initialize gradient input and gradient filters to zero
    if (gi_ox < INPUT_WIDTH && gi_oy < INPUT_HEIGHT && oc < OUTPUT_CHANNELS) {
        d_gradInput[gi_ox + gi_oy * INPUT_WIDTH + oc * INPUT_WIDTH * INPUT_HEIGHT] = 0.0f;
    }
    if (tx < FILTER_WIDTH && ty < FILTER_HEIGHT && oc < OUTPUT_CHANNELS && ic < INPUT_CHANNELS) {
        d_gradFilters[tx + ty * FILTER_WIDTH + oc * FILTER_WIDTH * FILTER_HEIGHT + ic * FILTER_WIDTH * FILTER_HEIGHT * OUTPUT_CHANNELS] = 0.0f;
    }

    // Synchronize to ensure all threads have initialized their data
    __syncthreads();

    // Load input and filter data into shared memory
    if (gi_ox < INPUT_WIDTH && gi_oy < INPUT_HEIGHT && ic < INPUT_CHANNELS) {
        s_input[ty][tx] = d_input[gi_ox + gi_oy * INPUT_WIDTH + ic * INPUT_WIDTH * INPUT_HEIGHT];
    }
    if (tx < FILTER_WIDTH && ty < FILTER_HEIGHT && oc < OUTPUT_CHANNELS && ic < INPUT_CHANNELS) {
        s_filters[ty][tx] = d_filters[tx + ty * FILTER_WIDTH + oc * FILTER_WIDTH * FILTER_HEIGHT + ic * FILTER_WIDTH * FILTER_HEIGHT * OUTPUT_CHANNELS];
    }

    // Synchronize to ensure all data is loaded into shared memory
    __syncthreads();

    // Compute gradient input and gradient filters
    if (ox < OUTPUT_WIDTH && oy < OUTPUT_HEIGHT && oc < OUTPUT_CHANNELS) {
        float gradOutput = d_gradOutput[ox + oy * OUTPUT_WIDTH + oc * OUTPUT_WIDTH * OUTPUT_HEIGHT];
        for (int fy = 0; fy < FILTER_HEIGHT; ++fy) {
            for (int fx = 0; fx < FILTER_WIDTH; ++fx) {
                int iix = gi_ox - fx;
                int iiy = gi_oy - fy;
                if (iix >= 0 && iix < INPUT_WIDTH && iiy >= 0 && iiy < INPUT_HEIGHT) {
                    atomicAdd(&d_gradInput[iix + iiy * INPUT_WIDTH + ic * INPUT_WIDTH * INPUT_HEIGHT], gradOutput * s_filters[fy][fx]);
                    atomicAdd(&d_gradFilters[fx + fy * FILTER_WIDTH + oc * FILTER_WIDTH * FILTER_HEIGHT + ic * FILTER_WIDTH * FILTER_HEIGHT * OUTPUT_CHANNELS], gradOutput * s_input[fy][fx]);
                }
            }
        }
    }
}

int main() {
    // Allocate memory for input, output, filters, and gradients on host
    float* h_input = new float[BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT];
    float* h_output = new float[BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT];
    float* h_filters = new float[OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT];
    float* h_gradOutput = new float[BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT];
    float* h_gradInput = new float[BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT];
    float* h_gradFilters = new float[OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT];

    // Initialize host memory (random values for demonstration)
    for (int i = 0; i < BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT; ++i) h_input[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT; ++i) h_output[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT; ++i) h_filters[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT; ++i) h_gradOutput[i] = static_cast<float>(rand()) / RAND_MAX;
    for (int i = 0; i < BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT; ++i) h_gradInput[i] = 0.0f;
    for (int i = 0; i < OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT; ++i) h_gradFilters[i] = 0.0f;

    // Allocate memory for input, output, filters, and gradients on device
    float* d_input, *d_output, *d_filters, *d_gradOutput, *d_gradInput, *d_gradFilters;
    hipMalloc((void**)&d_input, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float));
    hipMalloc((void**)&d_output, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float));
    hipMalloc((void**)&d_filters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float));
    hipMalloc((void**)&d_gradOutput, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float));
    hipMalloc((void**)&d_gradInput, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float));
    hipMalloc((void**)&d_gradFilters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float));

    // Copy data from host to device
    hipMemcpy(d_input, h_input, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_output, h_output, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_filters, h_filters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_gradOutput, h_gradOutput, BATCH_SIZE * OUTPUT_CHANNELS * OUTPUT_WIDTH * OUTPUT_HEIGHT * sizeof(float), hipMemcpyHostToDevice);

    // Define block and grid dimensions
    dim3 blockSize(FILTER_WIDTH, FILTER_HEIGHT);
    dim3 gridSize((OUTPUT_WIDTH + FILTER_WIDTH - 1) / FILTER_WIDTH, (OUTPUT_HEIGHT + FILTER_HEIGHT - 1) / FILTER_HEIGHT, OUTPUT_CHANNELS);

    // Launch the kernel
    convBackpropKernel<<<gridSize, blockSize>>>(d_input, d_output, d_filters, d_gradOutput, d_gradInput, d_gradFilters);

    // Check for errors in kernel launch
    hipError_t err = hipGetLastError();
    if (err != hipSuccess) {
        std::cerr << "CUDA error: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Copy results back to host
    hipMemcpy(h_gradInput, d_gradInput, BATCH_SIZE * INPUT_CHANNELS * INPUT_WIDTH * INPUT_HEIGHT * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(h_gradFilters, d_gradFilters, OUTPUT_CHANNELS * INPUT_CHANNELS * FILTER_WIDTH * FILTER_HEIGHT * sizeof(float), hipMemcpyDeviceToHost);

    // Free device memory
    hipFree(d_input);
    hipFree(d_output);
    hipFree(d_filters);
    hipFree(d_gradOutput);
    hipFree(d_gradInput);
    hipFree(d_gradFilters);

    // Free host memory
    delete[] h_input;
    delete[] h_output;
    delete[] h_filters;
    delete[] h_gradOutput;
    delete[] h_gradInput;
    delete[] h_gradFilters;

    return 0;
}
	.text
	.file	"cuda_code_065484.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_ # -- Begin function _Z33__device_stub__convBackpropKernelPfS_S_S_S_S_
	.type	_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_,@function
_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_: # @_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convBackpropKernelPfS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_, .Lfunc_end0-_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x30000000                      # float 4.65661287E-10
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$786432, %edi                   # imm = 0xC0000
	callq	_Znam
	movq	%rax, %rbx
	movl	$7372800, %edi                  # imm = 0x708000
	callq	_Znam
	movq	%rax, %r14
	movl	$3456, %edi                     # imm = 0xD80
	callq	_Znam
	movq	%rax, %r15
	movl	$7372800, %edi                  # imm = 0x708000
	callq	_Znam
	movq	%rax, %r12
	movl	$786432, %edi                   # imm = 0xC0000
	callq	_Znam
	movq	%rax, %rbp
	movl	$3456, %edi                     # imm = 0xD80
	callq	_Znam
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	xorl	%r13d, %r13d
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	movss	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r13,4)
	incq	%r13
	cmpq	$196608, %r13                   # imm = 0x30000
	jne	.LBB1_1
# %bb.2:                                # %.preheader57.preheader
	xorl	%r13d, %r13d
.LBB1_3:                                # %.preheader57
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, (%r14,%r13,4)
	incq	%r13
	cmpq	$1843200, %r13                  # imm = 0x1C2000
	jne	.LBB1_3
# %bb.4:                                # %.preheader56.preheader
	xorl	%r13d, %r13d
.LBB1_5:                                # %.preheader56
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, (%r15,%r13,4)
	incq	%r13
	cmpq	$864, %r13                      # imm = 0x360
	jne	.LBB1_5
# %bb.6:                                # %.preheader55.preheader
	xorl	%r13d, %r13d
.LBB1_7:                                # %.preheader55
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, (%r12,%r13,4)
	incq	%r13
	cmpq	$1843200, %r13                  # imm = 0x1C2000
	jne	.LBB1_7
# %bb.8:                                # %.preheader54.preheader
	movl	$786432, %edx                   # imm = 0xC0000
	movq	%rbp, 64(%rsp)                  # 8-byte Spill
	movq	%rbp, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$3456, %edx                     # imm = 0xD80
	movq	40(%rsp), %rdi                  # 8-byte Reload
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	56(%rsp), %rbp
	movl	$786432, %esi                   # imm = 0xC0000
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	48(%rsp), %r13
	movl	$7372800, %esi                  # imm = 0x708000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$3456, %esi                     # imm = 0xD80
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$7372800, %esi                  # imm = 0x708000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$786432, %esi                   # imm = 0xC0000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$3456, %esi                     # imm = 0xD80
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$786432, %edx                   # imm = 0xC0000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$7372800, %edx                  # imm = 0x708000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movl	$3456, %edx                     # imm = 0xD80
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movl	$7372800, %edx                  # imm = 0x708000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$42949672970, %rdi              # imm = 0xA0000000A
	movabsq	$12884901891, %rdx              # imm = 0x300000003
	movl	$32, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.9:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	callq	_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_
.LBB1_10:
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB1_15
# %bb.11:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_12
# %bb.13:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_14
.LBB1_15:
	movq	16(%rsp), %rsi
	movl	$786432, %edx                   # imm = 0xC0000
	movq	64(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movl	$3456, %edx                     # imm = 0xD80
	movq	40(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_ZdaPv
	movq	%r13, %rdi
	callq	_ZdaPv
	movq	%rbp, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	jmp	.LBB1_16
.LBB1_12:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_14:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$-1, %eax
.LBB1_16:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convBackpropKernelPfS_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convBackpropKernelPfS_S_S_S_S_,@object # @_Z18convBackpropKernelPfS_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z18convBackpropKernelPfS_S_S_S_S_
	.p2align	3, 0x0
_Z18convBackpropKernelPfS_S_S_S_S_:
	.quad	_Z33__device_stub__convBackpropKernelPfS_S_S_S_S_
	.size	_Z18convBackpropKernelPfS_S_S_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error: "
	.size	.L.str, 13

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convBackpropKernelPfS_S_S_S_S_"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convBackpropKernelPfS_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convBackpropKernelPfS_S_S_S_S_
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convBackpropKernelPfS_S_S_S_S_ ; -- Begin function _Z18convBackpropKernelPfS_S_S_S_S_
	.globl	_Z18convBackpropKernelPfS_S_S_S_S_
	.p2align	8
	.type	_Z18convBackpropKernelPfS_S_S_S_S_,@function
_Z18convBackpropKernelPfS_S_S_S_S_:     ; @_Z18convBackpropKernelPfS_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x10
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s12, s2, 16
	v_mad_u64_u32 v[0:1], null, s13, s3, v[4:5]
	v_mad_u64_u32 v[1:2], null, s14, s12, v[3:4]
	s_cmp_lt_i32 s15, 32
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 1, v0
	v_max_i32_e32 v2, v0, v1
	v_add_nc_u32_e32 v6, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 31, v2
	v_lshlrev_b32_e32 v9, 5, v6
	s_and_b32 s2, s13, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s12, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_lshl_b32 s2, s15, 10
	v_mov_b32_e32 v5, 0
	v_add3_u32 v10, v7, s2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s2, s8, v10
	v_add_co_ci_u32_e64 v11, s2, s9, v11, s2
	global_store_b32 v[10:11], v5, off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s12
	v_max_u32_e32 v8, v4, v3
	v_mad_u32_u24 v5, v3, s3, v4
	v_mad_u32_u24 v11, v3, 3, v4
	s_mul_i32 s12, s15, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_u32_e64 s3, 3, v8
	v_mul_lo_u32 v10, 0x120, v5
	v_cmp_gt_u32_e64 s2, 3, v5
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s3, s13, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s14, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s16, s14
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v12, v11, s12, v10
	v_mov_b32_e32 v8, 0
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, s3, s10, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s3, s11, v13, s3
	global_store_b32 v[12:13], v8, off
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s16
	v_lshlrev_b32_e32 v4, 2, v4
	v_lshlrev_b32_e32 v8, 10, v5
	s_and_b32 s3, vcc_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_6
; %bb.5:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add3_u32 v12, v8, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
	global_load_b32 v9, v[12:13], off
	v_mad_u32_u24 v12, v3, 12, v4
	s_waitcnt vmcnt(0)
	ds_store_b32 v12, v9
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s14
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_add3_u32 v9, v11, s12, v10
	v_mad_u32_u24 v3, v3, 12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v9, v[9:10], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v9 offset:48
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, 30, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s0, s13, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_18
; %bb.9:
	v_mul_lo_u32 v1, v1, 30
	s_mulk_i32 s15, 0x384
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, s15, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v9, v[0:1], off
	v_mad_u64_u32 v[0:1], null, 0x120, v5, s[12:13]
.LBB0_10:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
                                        ;       Child Loop BB0_13 Depth 3
                                        ;       Child Loop BB0_15 Depth 3
	v_subrev_nc_u32_e32 v3, s2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s2, 3, v[0:1]
	s_mul_i32 s3, s2, 12
	s_mov_b32 s4, 0
	v_cmp_lt_i32_e32 vcc_lo, -1, v3
	v_cmp_gt_i32_e64 s0, 32, v3
	v_lshl_add_u32 v10, v3, 5, v8
.LBB0_11:                               ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_13 Depth 3
                                        ;       Child Loop BB0_15 Depth 3
	v_subrev_nc_u32_e32 v2, s4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s1, 32, v2
	s_and_b32 s1, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s0
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB0_16
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=2
	v_add_nc_u32_e32 v2, v10, v2
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s8, v2
	v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
	s_lshl_b32 s1, s4, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s3, s1
	global_load_b32 v5, v[2:3], off
	v_mov_b32_e32 v4, s6
	ds_load_b32 v4, v4 offset:48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f32_e32 v11, v9, v4
.LBB0_13:                               ; %atomicrmw.start
                                        ;   Parent Loop BB0_10 Depth=1
                                        ;     Parent Loop BB0_11 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v5, v11
	global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s1, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s7, s1, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v4, s6
	s_mov_b32 s6, 0
	ds_load_b32 v4, v4
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v11, v9, v4 :: v_dual_add_nc_u32 v2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s10, v2
	v_add_co_ci_u32_e64 v3, s1, s11, v3, s1
	global_load_b32 v5, v[2:3], off
.LBB0_15:                               ; %atomicrmw.start136
                                        ;   Parent Loop BB0_10 Depth=1
                                        ;     Parent Loop BB0_11 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v5, v11
	global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s1, v4, v5
	v_mov_b32_e32 v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s6, s1, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_15
.LBB0_16:                               ; %Flow156
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 3
	s_cbranch_scc0 .LBB0_11
; %bb.17:                               ;   in Loop: Header=BB0_10 Depth=1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 3
	s_cbranch_scc0 .LBB0_10
.LBB0_18:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convBackpropKernelPfS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 84
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convBackpropKernelPfS_S_S_S_S_, .Lfunc_end0-_Z18convBackpropKernelPfS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1028
; NumSgprs: 19
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 84 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 84
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convBackpropKernelPfS_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z18convBackpropKernelPfS_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
