#include <iostream>
#include <cuda_runtime.h>
#include <cassert>

// Define constants
#define FILTER_SIZE 32
#define TILE_WIDTH FILTER_SIZE
#define BLOCK_WIDTH (TILE_WIDTH + FILTER_SIZE - 1)

// CUDA kernel for 2D convolution with persistent threads
__global__ void convolveKernel(const float* d_input, float* d_output, const float* d_filter, int width, int height) {
    __shared__ float s_input[BLOCK_WIDTH][BLOCK_WIDTH];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int row = by * TILE_WIDTH + ty;
    int col = bx * TILE_WIDTH + tx;

    // Load input data into shared memory
    if (row < height && col < width) {
        s_input[ty][tx] = d_input[row * width + col];
    } else {
        s_input[ty][tx] = 0.0f;
    }

    // Load halo data into shared memory
    if (ty < FILTER_SIZE) {
        int haloRow = row - FILTER_SIZE + 1;
        if (haloRow >= 0 && haloRow < height) {
            s_input[ty - FILTER_SIZE][tx] = d_input[haloRow * width + col];
        } else {
            s_input[ty - FILTER_SIZE][tx] = 0.0f;
        }
    }
    if (ty >= TILE_WIDTH && ty < TILE_WIDTH + FILTER_SIZE - 1) {
        int haloRow = row + TILE_WIDTH;
        if (haloRow >= 0 && haloRow < height) {
            s_input[ty + FILTER_SIZE - 1][tx] = d_input[haloRow * width + col];
        } else {
            s_input[ty + FILTER_SIZE - 1][tx] = 0.0f;
        }
    }
    if (tx < FILTER_SIZE) {
        int haloCol = col - FILTER_SIZE + 1;
        if (haloCol >= 0 && haloCol < width) {
            s_input[ty][tx - FILTER_SIZE] = d_input[row * width + haloCol];
        } else {
            s_input[ty][tx - FILTER_SIZE] = 0.0f;
        }
    }
    if (tx >= TILE_WIDTH && tx < TILE_WIDTH + FILTER_SIZE - 1) {
        int haloCol = col + TILE_WIDTH;
        if (haloCol >= 0 && haloCol < width) {
            s_input[ty][tx + FILTER_SIZE - 1] = d_input[row * width + haloCol];
        } else {
            s_input[ty][tx + FILTER_SIZE - 1] = 0.0f;
        }
    }

    __syncthreads();

    // Compute the convolution
    float sum = 0.0f;
    if (row < height && col < width) {
        for (int f = 0; f < FILTER_SIZE; ++f) {
            for (int g = 0; g < FILTER_SIZE; ++g) {
                sum += s_input[ty + f][tx + g] * d_filter[f * FILTER_SIZE + g];
            }
        }
        d_output[row * width + col] = sum;
    }
}

int main() {
    // Input image dimensions
    int width = 1024, height = 1024;

    // Allocate host memory
    float* h_input = new float[width * height];
    float* h_output = new float[width * height];
    float* h_filter = new float[FILTER_SIZE * FILTER_SIZE];

    // Initialize input image and filter
    for (int i = 0; i < width * height; ++i) {
        h_input[i] = static_cast<float>(i % 256);
    }
    for (int i = 0; i < FILTER_SIZE * FILTER_SIZE; ++i) {
        h_filter[i] = 1.0f / (FILTER_SIZE * FILTER_SIZE); // Simple averaging filter
    }

    // Allocate device memory
    float* d_input, *d_output, *d_filter;
    cudaError_t err;
    err = cudaMalloc((void**)&d_input, width * height * sizeof(float));
    assert(err == cudaSuccess);
    err = cudaMalloc((void**)&d_output, width * height * sizeof(float));
    assert(err == cudaSuccess);
    err = cudaMalloc((void**)&d_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float));
    assert(err == cudaSuccess);

    // Copy data from host to device
    err = cudaMemcpy(d_input, h_input, width * height * sizeof(float), cudaMemcpyHostToDevice);
    assert(err == cudaSuccess);
    err = cudaMemcpy(d_filter, h_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float), cudaMemcpyHostToDevice);
    assert(err == cudaSuccess);

    // Launch kernel
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 dimGrid((width + TILE_WIDTH - 1) / TILE_WIDTH, (height + TILE_WIDTH - 1) / TILE_WIDTH);
    convolveKernel<<<dimGrid, dimBlock>>>(d_input, d_output, d_filter, width, height);

    // Copy result back to host
    err = cudaMemcpy(h_output, d_output, width * height * sizeof(float), cudaMemcpyDeviceToHost);
    assert(err == cudaSuccess);

    // Free device memory
    cudaFree(d_input);
    cudaFree(d_output);
    cudaFree(d_filter);

    // Free host memory
    delete[] h_input;
    delete[] h_output;
    delete[] h_filter;

    // Check for any errors launching the kernel
    err = cudaGetLastError();
    assert(err == cudaSuccess);

    std::cout << "Convolution completed successfully." << std::endl;

    return 0;
}
	.file	"tmpxft_0014566f_00000000-6_cuda_code_053350.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z14convolveKernelPKfPfS0_iiPKfPfS0_ii
	.type	_Z42__device_stub__Z14convolveKernelPKfPfS0_iiPKfPfS0_ii, @function
_Z42__device_stub__Z14convolveKernelPKfPfS0_iiPKfPfS0_ii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14convolveKernelPKfPfS0_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z42__device_stub__Z14convolveKernelPKfPfS0_iiPKfPfS0_ii, .-_Z42__device_stub__Z14convolveKernelPKfPfS0_iiPKfPfS0_ii
	.globl	_Z14convolveKernelPKfPfS0_ii
	.type	_Z14convolveKernelPKfPfS0_ii, @function
_Z14convolveKernelPKfPfS0_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z14convolveKernelPKfPfS0_iiPKfPfS0_ii
	.cfi_endproc
.LFE3661:
	.size	_Z14convolveKernelPKfPfS0_ii, .-_Z14convolveKernelPKfPfS0_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Convolution completed successfully."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4194304, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movl	$4194304, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$4096, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L9:
	movzbl	%al, %edx
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$1048576, %rax
	jne	.L9
	movss	.LC0(%rip), %xmm0
	xorl	%eax, %eax
.L10:
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$1024, %rax
	jne	.L10
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1024, %ecx
	movl	$1024, %r8d
	movq	8(%rsp), %rdi
	call	_Z42__device_stub__Z14convolveKernelPKfPfS0_iiPKfPfS0_ii
.L11:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$4194304, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	call	cudaGetLastError@PLT
	leaq	_ZSt4cout(%rip), %rdi
	leaq	.LC1(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z14convolveKernelPKfPfS0_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14convolveKernelPKfPfS0_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	981467136
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <cassert>

// Define constants
#define FILTER_SIZE 32
#define TILE_WIDTH FILTER_SIZE
#define BLOCK_WIDTH (TILE_WIDTH + FILTER_SIZE - 1)

// CUDA kernel for 2D convolution with persistent threads
__global__ void convolveKernel(const float* d_input, float* d_output, const float* d_filter, int width, int height) {
    __shared__ float s_input[BLOCK_WIDTH][BLOCK_WIDTH];

    int bx = blockIdx.x, by = blockIdx.y;
    int tx = threadIdx.x, ty = threadIdx.y;

    int row = by * TILE_WIDTH + ty;
    int col = bx * TILE_WIDTH + tx;

    // Load input data into shared memory
    if (row < height && col < width) {
        s_input[ty][tx] = d_input[row * width + col];
    } else {
        s_input[ty][tx] = 0.0f;
    }

    // Load halo data into shared memory
    if (ty < FILTER_SIZE) {
        int haloRow = row - FILTER_SIZE + 1;
        if (haloRow >= 0 && haloRow < height) {
            s_input[ty - FILTER_SIZE][tx] = d_input[haloRow * width + col];
        } else {
            s_input[ty - FILTER_SIZE][tx] = 0.0f;
        }
    }
    if (ty >= TILE_WIDTH && ty < TILE_WIDTH + FILTER_SIZE - 1) {
        int haloRow = row + TILE_WIDTH;
        if (haloRow >= 0 && haloRow < height) {
            s_input[ty + FILTER_SIZE - 1][tx] = d_input[haloRow * width + col];
        } else {
            s_input[ty + FILTER_SIZE - 1][tx] = 0.0f;
        }
    }
    if (tx < FILTER_SIZE) {
        int haloCol = col - FILTER_SIZE + 1;
        if (haloCol >= 0 && haloCol < width) {
            s_input[ty][tx - FILTER_SIZE] = d_input[row * width + haloCol];
        } else {
            s_input[ty][tx - FILTER_SIZE] = 0.0f;
        }
    }
    if (tx >= TILE_WIDTH && tx < TILE_WIDTH + FILTER_SIZE - 1) {
        int haloCol = col + TILE_WIDTH;
        if (haloCol >= 0 && haloCol < width) {
            s_input[ty][tx + FILTER_SIZE - 1] = d_input[row * width + haloCol];
        } else {
            s_input[ty][tx + FILTER_SIZE - 1] = 0.0f;
        }
    }

    __syncthreads();

    // Compute the convolution
    float sum = 0.0f;
    if (row < height && col < width) {
        for (int f = 0; f < FILTER_SIZE; ++f) {
            for (int g = 0; g < FILTER_SIZE; ++g) {
                sum += s_input[ty + f][tx + g] * d_filter[f * FILTER_SIZE + g];
            }
        }
        d_output[row * width + col] = sum;
    }
}

int main() {
    // Input image dimensions
    int width = 1024, height = 1024;

    // Allocate host memory
    float* h_input = new float[width * height];
    float* h_output = new float[width * height];
    float* h_filter = new float[FILTER_SIZE * FILTER_SIZE];

    // Initialize input image and filter
    for (int i = 0; i < width * height; ++i) {
        h_input[i] = static_cast<float>(i % 256);
    }
    for (int i = 0; i < FILTER_SIZE * FILTER_SIZE; ++i) {
        h_filter[i] = 1.0f / (FILTER_SIZE * FILTER_SIZE); // Simple averaging filter
    }

    // Allocate device memory
    float* d_input, *d_output, *d_filter;
    hipError_t err;
    err = hipMalloc((void**)&d_input, width * height * sizeof(float));
    assert(err == hipSuccess);
    err = hipMalloc((void**)&d_output, width * height * sizeof(float));
    assert(err == hipSuccess);
    err = hipMalloc((void**)&d_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float));
    assert(err == hipSuccess);

    // Copy data from host to device
    err = hipMemcpy(d_input, h_input, width * height * sizeof(float), hipMemcpyHostToDevice);
    assert(err == hipSuccess);
    err = hipMemcpy(d_filter, h_filter, FILTER_SIZE * FILTER_SIZE * sizeof(float), hipMemcpyHostToDevice);
    assert(err == hipSuccess);

    // Launch kernel
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
    dim3 dimGrid((width + TILE_WIDTH - 1) / TILE_WIDTH, (height + TILE_WIDTH - 1) / TILE_WIDTH);
    convolveKernel<<<dimGrid, dimBlock>>>(d_input, d_output, d_filter, width, height);

    // Copy result back to host
    err = hipMemcpy(h_output, d_output, width * height * sizeof(float), hipMemcpyDeviceToHost);
    assert(err == hipSuccess);

    // Free device memory
    hipFree(d_input);
    hipFree(d_output);
    hipFree(d_filter);

    // Free host memory
    delete[] h_input;
    delete[] h_output;
    delete[] h_filter;

    // Check for any errors launching the kernel
    err = hipGetLastError();
    assert(err == hipSuccess);

    std::cout << "Convolution completed successfully." << std::endl;

    return 0;
}
	.text
	.file	"cuda_code_053350.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z29__device_stub__convolveKernelPKfPfS0_ii # -- Begin function _Z29__device_stub__convolveKernelPKfPfS0_ii
	.type	_Z29__device_stub__convolveKernelPKfPfS0_ii,@function
_Z29__device_stub__convolveKernelPKfPfS0_ii: # @_Z29__device_stub__convolveKernelPKfPfS0_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14convolveKernelPKfPfS0_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__convolveKernelPKfPfS0_ii, .Lfunc_end0-_Z29__device_stub__convolveKernelPKfPfS0_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %rbx
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %r14
	movl	$4096, %edi                     # imm = 0x1000
	callq	_Znam
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movzbl	%al, %ecx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$1048576, %rax                  # imm = 0x100000
	jne	.LBB1_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$981467136, (%r15,%rax,4)       # imm = 0x3A800000
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB1_3
# %bb.4:
	leaq	24(%rsp), %r12
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	leaq	16(%rsp), %r13
	movl	$4096, %esi                     # imm = 0x1000
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$137438953504, %rdi             # imm = 0x2000000020
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$1024, %ecx                     # imm = 0x400
	movl	$1024, %r8d                     # imm = 0x400
	callq	_Z29__device_stub__convolveKernelPKfPfS0_ii
.LBB1_6:
	movq	8(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	callq	hipGetLastError
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$35, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14convolveKernelPKfPfS0_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14convolveKernelPKfPfS0_ii,@object # @_Z14convolveKernelPKfPfS0_ii
	.section	.rodata,"a",@progbits
	.globl	_Z14convolveKernelPKfPfS0_ii
	.p2align	3, 0x0
_Z14convolveKernelPKfPfS0_ii:
	.quad	_Z29__device_stub__convolveKernelPKfPfS0_ii
	.size	_Z14convolveKernelPKfPfS0_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Convolution completed successfully."
	.size	.L.str, 36

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14convolveKernelPKfPfS0_ii"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__convolveKernelPKfPfS0_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14convolveKernelPKfPfS0_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14convolveKernelPKfPfS0_ii ; -- Begin function _Z14convolveKernelPKfPfS0_ii
	.globl	_Z14convolveKernelPKfPfS0_ii
	.p2align	8
	.type	_Z14convolveKernelPKfPfS0_ii,@function
_Z14convolveKernelPKfPfS0_ii:           ; @_Z14convolveKernelPKfPfS0_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v4, v0, 10, 10
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v3, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, s15, 5, v4
	v_lshl_add_u32 v0, s14, 5, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s11, v1
	v_cmp_gt_i32_e64 s0, s10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s0
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mad_u64_u32 v[5:6], null, v1, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v6, v[5:6], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b32_e32 v5, 2, v3
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v2, 0xfc, v4, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v6
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB0_6
; %bb.3:
	v_subrev_nc_u32_e32 v7, 31, v1
	v_cmp_lt_i32_e32 vcc_lo, 30, v1
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s11, v7
	s_and_b32 s3, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_mad_u64_u32 v[8:9], null, v7, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[6:7], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
.LBB0_5:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s0
	v_or_b32_e32 v7, 0xffffe0, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i32_i24 v5, 0xfc, v7, v5
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v6
.LBB0_6:                                ; %Flow163
	s_or_b32 exec_lo, exec_lo, s2
	v_subrev_nc_u32_e32 v5, 32, v4
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 31, v5
	s_cbranch_execz .LBB0_10
; %bb.7:
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, 32, v1
	v_cmp_lt_i32_e32 vcc_lo, 0xffffffdf, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s11, v5
	s_and_b32 s3, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mad_u64_u32 v[6:7], null, v5, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v6, v[5:6], off
.LBB0_9:                                ; %.sink.split127
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v6 offset:7812
.LBB0_10:                               ; %Flow162
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 32, v3
	s_cbranch_execz .LBB0_14
; %bb.11:
	v_subrev_nc_u32_e32 v5, 31, v0
	v_cmp_lt_i32_e32 vcc_lo, 30, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s10, v5
	v_mov_b32_e32 v5, 0
	s_and_b32 s3, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_mul_lo_u32 v5, v1, s10
	v_ashrrev_i32_e32 v6, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v5
	v_add_co_u32 v5, vcc_lo, v5, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v5, v[5:6], off offset:-124
.LBB0_13:                               ; %.sink.split131
	s_or_b32 exec_lo, exec_lo, s0
	v_lshl_or_b32 v6, v3, 2, 0xffffff80
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v4, 0xfc, v4, v6
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
.LBB0_14:                               ; %Flow161
	s_or_b32 exec_lo, exec_lo, s2
	v_subrev_nc_u32_e32 v3, 32, v3
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 31, v3
	s_cbranch_execz .LBB0_18
; %bb.15:
	v_add_nc_u32_e32 v3, 32, v0
	v_cmp_lt_i32_e32 vcc_lo, 0xffffffdf, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s10, v3
	v_mov_b32_e32 v3, 0
	s_and_b32 s3, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_mul_lo_u32 v3, v1, s10
	v_ashrrev_i32_e32 v4, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v3
	v_add_co_u32 v3, vcc_lo, v3, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off offset:128
.LBB0_17:                               ; %.sink.split135
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v3 offset:124
.LBB0_18:                               ; %Flow160
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_24
; %bb.19:                               ; %.preheader.preheader
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, 0
.LBB0_20:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_21 Depth 2
	s_mov_b64 s[0:1], s[8:9]
	s_mov_b32 s3, 0
.LBB0_21:                               ;   Parent Loop BB0_20 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s3, v2
	s_load_b32 s4, s[0:1], 0x0
	s_add_i32 s3, s3, 4
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	ds_load_b32 v4, v4
	s_cmpk_eq_i32 s3, 0x80
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, s4, v4
	s_cbranch_scc0 .LBB0_21
; %bb.22:                               ;   in Loop: Header=BB0_20 Depth=1
	s_add_i32 s2, s2, 1
	v_add_nc_u32_e32 v2, 0xfc, v2
	s_add_u32 s8, s8, 0x80
	s_addc_u32 s9, s9, 0
	s_cmp_eq_u32 s2, 32
	s_cbranch_scc0 .LBB0_20
; %bb.23:
	v_mad_u64_u32 v[4:5], null, v1, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB0_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14convolveKernelPKfPfS0_ii
		.amdhsa_group_segment_fixed_size 15876
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14convolveKernelPKfPfS0_ii, .Lfunc_end0-_Z14convolveKernelPKfPfS0_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 952
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 15876 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 15876
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14convolveKernelPKfPfS0_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14convolveKernelPKfPfS0_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
