#include <iostream>
#include <cuda_runtime.h>
#include <cmath>

// Constants
const int NUM_PARTICLES = 2048;
const float DT = 0.01f; // Time step
const float EPSILON = 1e-10f; // Small value to avoid division by zero

// CUDA kernel for Verlet integration
__global__ void verletIntegration(float4 *positions, float4 *velocities, float4 *forces, float4 *newForces, float mass) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NUM_PARTICLES) {
        // Verlet integration formula
        positions[idx].x += velocities[idx].x * DT + 0.5f * forces[idx].x / mass * DT * DT;
        positions[idx].y += velocities[idx].y * DT + 0.5f * forces[idx].y / mass * DT * DT;
        positions[idx].z += velocities[idx].z * DT + 0.5f * forces[idx].z / mass * DT * DT;

        // Update velocity using new force
        velocities[idx].x += 0.5f * (forces[idx].x + newForces[idx].x) / mass * DT;
        velocities[idx].y += 0.5f * (forces[idx].y + newForces[idx].y) / mass * DT;
        velocities[idx].z += 0.5f * (forces[idx].z + newForces[idx].z) / mass * DT;
    }
}

// Simple force calculation (Lennard-Jones potential)
__global__ void computeForces(float4 *positions, float4 *forces, float epsilon, float sigma, float cutoff) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NUM_PARTICLES) {
        forces[idx].x = 0.0f;
        forces[idx].y = 0.0f;
        forces[idx].z = 0.0f;
        for (int j = 0; j < NUM_PARTICLES; j++) {
            if (j != idx) {
                float dx = positions[j].x - positions[idx].x;
                float dy = positions[j].y - positions[idx].y;
                float dz = positions[j].z - positions[idx].z;
                float r2 = dx * dx + dy * dy + dz * dz;
                if (r2 < cutoff * cutoff) {
                    float r6 = r2 * r2 * r2;
                    float force = 24.0f * epsilon * (2.0f / (r6 * r6) - 1.0f / r6) / r2;
                    forces[idx].x += force * dx;
                    forces[idx].y += force * dy;
                    forces[idx].z += force * dz;
                }
            }
        }
    }
}

int main() {
    // Initialize CUDA
    cudaError_t err = cudaSetDevice(0);
    if (err != cudaSuccess) {
        std::cerr << "Error setting device: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Allocate Unified Memory for positions, velocities, forces, and newForces
    float4 *positions, *velocities, *forces, *newForces;
    err = cudaMallocManaged(&positions, NUM_PARTICLES * sizeof(float4));
    if (err != cudaSuccess) {
        std::cerr << "Error allocating Unified Memory for positions: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }
    err = cudaMallocManaged(&velocities, NUM_PARTICLES * sizeof(float4));
    if (err != cudaSuccess) {
        std::cerr << "Error allocating Unified Memory for velocities: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }
    err = cudaMallocManaged(&forces, NUM_PARTICLES * sizeof(float4));
    if (err != cudaSuccess) {
        std::cerr << "Error allocating Unified Memory for forces: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }
    err = cudaMallocManaged(&newForces, NUM_PARTICLES * sizeof(float4));
    if (err != cudaSuccess) {
        std::cerr << "Error allocating Unified Memory for newForces: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Initialize positions and velocities
    for (int i = 0; i < NUM_PARTICLES; i++) {
        positions[i] = make_float4(i, i, i, 0.0f);
        velocities[i] = make_float4(0.0f, 0.0f, 0.0f, 0.0f);
    }

    // Parameters for Lennard-Jones potential
    float epsilon = 1.0f;
    float sigma = 1.0f;
    float cutoff = 2.5f;

    // Compute initial forces
    int blockSize = 256;
    int numBlocks = (NUM_PARTICLES + blockSize - 1) / blockSize;
    computeForces<<<numBlocks, blockSize>>>(positions, forces, epsilon, sigma, cutoff);
    err = cudaDeviceSynchronize();
    if (err != cudaSuccess) {
        std::cerr << "Error in computeForces kernel: " << cudaGetErrorString(err) << std::endl;
        return -1;
    }

    // Perform a few steps of Verlet integration
    for (int step = 0; step < 10; step++) {
        // Compute new forces
        computeForces<<<numBlocks, blockSize>>>(positions, newForces, epsilon, sigma, cutoff);
        err = cudaDeviceSynchronize();
        if (err != cudaSuccess) {
            std::cerr << "Error in computeForces kernel: " << cudaGetErrorString(err) << std::endl;
            return -1;
        }

        // Perform Verlet integration step
        verletIntegration<<<numBlocks, blockSize>>>(positions, velocities, forces, newForces, 1.0f);
        err = cudaDeviceSynchronize();
        if (err != cudaSuccess) {
            std::cerr << "Error in verletIntegration kernel: " << cudaGetErrorString(err) << std::endl;
            return -1;
        }

        // Swap forces and newForces for next iteration
        float4 *temp = forces;
        forces = newForces;
        newForces = temp;
    }

    // Free Unified Memory
    cudaFree(positions);
    cudaFree(velocities);
    cudaFree(forces);
    cudaFree(newForces);

    return 0;
}
	.file	"tmpxft_000cd632_00000000-6_cuda_code_006610.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4295:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4295:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z53__device_stub__Z17verletIntegrationP6float4S0_S0_S0_fP6float4S0_S0_S0_f
	.type	_Z53__device_stub__Z17verletIntegrationP6float4S0_S0_S0_fP6float4S0_S0_S0_f, @function
_Z53__device_stub__Z17verletIntegrationP6float4S0_S0_S0_fP6float4S0_S0_S0_f:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z17verletIntegrationP6float4S0_S0_S0_f(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L3:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z53__device_stub__Z17verletIntegrationP6float4S0_S0_S0_fP6float4S0_S0_S0_f, .-_Z53__device_stub__Z17verletIntegrationP6float4S0_S0_S0_fP6float4S0_S0_S0_f
	.globl	_Z17verletIntegrationP6float4S0_S0_S0_f
	.type	_Z17verletIntegrationP6float4S0_S0_S0_f, @function
_Z17verletIntegrationP6float4S0_S0_S0_f:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z17verletIntegrationP6float4S0_S0_S0_fP6float4S0_S0_S0_f
	.cfi_endproc
.LFE3661:
	.size	_Z17verletIntegrationP6float4S0_S0_S0_f, .-_Z17verletIntegrationP6float4S0_S0_S0_f
	.globl	_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff
	.type	_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff, @function
_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	48(%rsp), %rdi
	leaq	60(%rsp), %rsi
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13computeForcesP6float4S0_fff(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L9:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff, .-_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff
	.globl	_Z13computeForcesP6float4S0_fff
	.type	_Z13computeForcesP6float4S0_fff, @function
_Z13computeForcesP6float4S0_fff:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff
	.cfi_endproc
.LFE3663:
	.size	_Z13computeForcesP6float4S0_fff, .-_Z13computeForcesP6float4S0_fff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Error setting device: "
.LC1:
	.string	"Error allocating Unified Memory for positions: "
.LC2:
	.string	"Error allocating Unified Memory for velocities: "
.LC3:
	.string	"Error allocating Unified Memory for forces: "
.LC4:
	.string	"Error allocating Unified Memory for newForces: "
.LC8:
	.string	"Error in computeForces kernel: "
.LC9:
	.string	"Error in verletIntegration kernel: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	leaq	.LC0(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L35
	movq	%rsp, %rdi
	movl	$1, %edx
	movl	$32768, %esi
	call	cudaMallocManaged@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L17
	leaq	.LC1(%rip), %rsi
.L35:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
.L36:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	orl	$-1, %eax
	jmp	.L14
.L17:
	movl	$32768, %esi
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC2(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L35
	movl	$32768, %esi
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC3(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L35
	movl	$32768, %esi
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	leaq	.LC4(%rip), %rsi
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L35
	movq	(%rsp), %rsi
	movq	8(%rsp), %rcx
	xorl	%eax, %eax
	xorl	%edx, %edx
.L22:
	cvtsi2ssl	%edx, %xmm0
	incl	%edx
	movl	$0x00000000, 12(%rsi,%rax)
	movss	%xmm0, (%rsi,%rax)
	movss	%xmm0, 4(%rsi,%rax)
	movss	%xmm0, 8(%rsi,%rax)
	movl	$0x00000000, (%rcx,%rax)
	movl	$0x00000000, 4(%rcx,%rax)
	movl	$0x00000000, 8(%rcx,%rax)
	movl	$0x00000000, 12(%rcx,%rax)
	addq	$16, %rax
	cmpl	$2048, %edx
	jne	.L22
	movl	$16777217, %edx
	movl	$536870913, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movss	.LC7(%rip), %xmm1
	movss	.LC6(%rip), %xmm2
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdi
	movaps	%xmm1, %xmm0
	call	_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff
.L23:
	call	cudaDeviceSynchronize@PLT
	movl	$16777217, %ebx
	movl	$10, %r12d
	movl	%eax, %ebp
	salq	$8, %rbx
	testl	%eax, %eax
	jne	.L38
.L24:
	movl	$536870913, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rbx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movss	.LC7(%rip), %xmm1
	movss	.LC6(%rip), %xmm2
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movaps	%xmm1, %xmm0
	call	_Z45__device_stub__Z13computeForcesP6float4S0_fffP6float4S0_fff
.L25:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L26
.L38:
	leaq	.LC8(%rip), %rsi
	jmp	.L37
.L26:
	movl	$536870913, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rbx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movss	.LC7(%rip), %xmm0
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z53__device_stub__Z17verletIntegrationP6float4S0_S0_S0_fP6float4S0_S0_S0_f
.L27:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	je	.L28
	leaq	.LC9(%rip), %rsi
.L37:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebp, %edi
	movq	%rax, %rbx
	call	cudaGetErrorString@PLT
	movq	%rbx, %rdi
	movq	%rax, %rsi
	jmp	.L36
.L28:
	movq	16(%rsp), %rax
	movq	24(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	%rdx, 16(%rsp)
	decl	%r12d
	jne	.L24
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L14:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z13computeForcesP6float4S0_fff"
.LC11:
	.string	"_Z17verletIntegrationP6float4S0_S0_S0_f"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13computeForcesP6float4S0_fff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17verletIntegrationP6float4S0_S0_S0_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC6:
	.long	1075838976
	.align 4
.LC7:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <cmath>

// Constants
const int NUM_PARTICLES = 2048;
const float DT = 0.01f; // Time step
const float EPSILON = 1e-10f; // Small value to avoid division by zero

// CUDA kernel for Verlet integration
__global__ void verletIntegration(float4 *positions, float4 *velocities, float4 *forces, float4 *newForces, float mass) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NUM_PARTICLES) {
        // Verlet integration formula
        positions[idx].x += velocities[idx].x * DT + 0.5f * forces[idx].x / mass * DT * DT;
        positions[idx].y += velocities[idx].y * DT + 0.5f * forces[idx].y / mass * DT * DT;
        positions[idx].z += velocities[idx].z * DT + 0.5f * forces[idx].z / mass * DT * DT;

        // Update velocity using new force
        velocities[idx].x += 0.5f * (forces[idx].x + newForces[idx].x) / mass * DT;
        velocities[idx].y += 0.5f * (forces[idx].y + newForces[idx].y) / mass * DT;
        velocities[idx].z += 0.5f * (forces[idx].z + newForces[idx].z) / mass * DT;
    }
}

// Simple force calculation (Lennard-Jones potential)
__global__ void computeForces(float4 *positions, float4 *forces, float epsilon, float sigma, float cutoff) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < NUM_PARTICLES) {
        forces[idx].x = 0.0f;
        forces[idx].y = 0.0f;
        forces[idx].z = 0.0f;
        for (int j = 0; j < NUM_PARTICLES; j++) {
            if (j != idx) {
                float dx = positions[j].x - positions[idx].x;
                float dy = positions[j].y - positions[idx].y;
                float dz = positions[j].z - positions[idx].z;
                float r2 = dx * dx + dy * dy + dz * dz;
                if (r2 < cutoff * cutoff) {
                    float r6 = r2 * r2 * r2;
                    float force = 24.0f * epsilon * (2.0f / (r6 * r6) - 1.0f / r6) / r2;
                    forces[idx].x += force * dx;
                    forces[idx].y += force * dy;
                    forces[idx].z += force * dz;
                }
            }
        }
    }
}

int main() {
    // Initialize CUDA
    hipError_t err = hipSetDevice(0);
    if (err != hipSuccess) {
        std::cerr << "Error setting device: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Allocate Unified Memory for positions, velocities, forces, and newForces
    float4 *positions, *velocities, *forces, *newForces;
    err = hipMallocManaged(&positions, NUM_PARTICLES * sizeof(float4));
    if (err != hipSuccess) {
        std::cerr << "Error allocating Unified Memory for positions: " << hipGetErrorString(err) << std::endl;
        return -1;
    }
    err = hipMallocManaged(&velocities, NUM_PARTICLES * sizeof(float4));
    if (err != hipSuccess) {
        std::cerr << "Error allocating Unified Memory for velocities: " << hipGetErrorString(err) << std::endl;
        return -1;
    }
    err = hipMallocManaged(&forces, NUM_PARTICLES * sizeof(float4));
    if (err != hipSuccess) {
        std::cerr << "Error allocating Unified Memory for forces: " << hipGetErrorString(err) << std::endl;
        return -1;
    }
    err = hipMallocManaged(&newForces, NUM_PARTICLES * sizeof(float4));
    if (err != hipSuccess) {
        std::cerr << "Error allocating Unified Memory for newForces: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Initialize positions and velocities
    for (int i = 0; i < NUM_PARTICLES; i++) {
        positions[i] = make_float4(i, i, i, 0.0f);
        velocities[i] = make_float4(0.0f, 0.0f, 0.0f, 0.0f);
    }

    // Parameters for Lennard-Jones potential
    float epsilon = 1.0f;
    float sigma = 1.0f;
    float cutoff = 2.5f;

    // Compute initial forces
    int blockSize = 256;
    int numBlocks = (NUM_PARTICLES + blockSize - 1) / blockSize;
    computeForces<<<numBlocks, blockSize>>>(positions, forces, epsilon, sigma, cutoff);
    err = hipDeviceSynchronize();
    if (err != hipSuccess) {
        std::cerr << "Error in computeForces kernel: " << hipGetErrorString(err) << std::endl;
        return -1;
    }

    // Perform a few steps of Verlet integration
    for (int step = 0; step < 10; step++) {
        // Compute new forces
        computeForces<<<numBlocks, blockSize>>>(positions, newForces, epsilon, sigma, cutoff);
        err = hipDeviceSynchronize();
        if (err != hipSuccess) {
            std::cerr << "Error in computeForces kernel: " << hipGetErrorString(err) << std::endl;
            return -1;
        }

        // Perform Verlet integration step
        verletIntegration<<<numBlocks, blockSize>>>(positions, velocities, forces, newForces, 1.0f);
        err = hipDeviceSynchronize();
        if (err != hipSuccess) {
            std::cerr << "Error in verletIntegration kernel: " << hipGetErrorString(err) << std::endl;
            return -1;
        }

        // Swap forces and newForces for next iteration
        float4 *temp = forces;
        forces = newForces;
        newForces = temp;
    }

    // Free Unified Memory
    hipFree(positions);
    hipFree(velocities);
    hipFree(forces);
    hipFree(newForces);

    return 0;
}
	.text
	.file	"cuda_code_006610.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f # -- Begin function _Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.type	_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f,@function
_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f: # @_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f, .Lfunc_end0-_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff # -- Begin function _Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.type	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff,@function
_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff: # @_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	8(%rsp), %rsi
	movss	%xmm1, (%rsi)
	leaq	4(%rsp), %rdi
	movss	%xmm2, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rsi, 24(%rbx)
	movq	%rdi, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff, .Lfunc_end1-_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI2_0:
	.long	0x3f800000                      # float 1
.LCPI2_1:
	.long	0x40200000                      # float 2.5
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$22, %edx
	jmp	.LBB2_8
.LBB2_2:
	leaq	24(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB2_4
# %bb.3:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$47, %edx
	jmp	.LBB2_8
.LBB2_4:
	leaq	32(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB2_6
# %bb.5:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.2, %esi
	movl	$48, %edx
	jmp	.LBB2_8
.LBB2_6:
	leaq	16(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB2_14
# %bb.7:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.3, %esi
	movl	$44, %edx
.LBB2_8:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB2_10
# %bb.9:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cerr, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB2_11
.LBB2_10:
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cerr(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_11:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cerr(%rip), %rax
	movl	$_ZSt4cerr, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB2_12:
	movl	$-1, %eax
.LBB2_13:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_14:
	.cfi_def_cfa_offset 80
	leaq	8(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	je	.LBB2_16
# %bb.15:
	movl	%eax, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.4, %esi
	movl	$47, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebx, %edi
	jmp	.LBB2_23
.LBB2_16:                               # %.preheader97.preheader
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
	xorl	%ecx, %ecx
.LBB2_17:                               # %.preheader97
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm1, %xmm1
	cvtsi2ss	%ecx, %xmm1
	movq	%xmm1, %xmm2                    # xmm2 = xmm1[0],zero
	shufps	$128, %xmm2, %xmm1              # xmm1 = xmm1[0,0],xmm2[0,2]
	movq	24(%rsp), %rdx
	movaps	%xmm1, (%rdx,%rax)
	movq	32(%rsp), %rdx
	incq	%rcx
	movaps	%xmm0, (%rdx,%rax)
	addq	$16, %rax
	cmpq	$2048, %rcx                     # imm = 0x800
	jne	.LBB2_17
# %bb.18:
	movabsq	$4294967304, %rbx               # imm = 0x100000008
	leaq	248(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_20
# %bb.19:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI2_1(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm1
	callq	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff
.LBB2_20:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	je	.LBB2_24
.LBB2_21:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.5, %esi
	movl	$31, %edx
.LBB2_22:                               # %.thread
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	%ebp, %edi
.LBB2_23:                               # %.thread
	callq	hipGetErrorString
	movl	$_ZSt4cerr, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	jmp	.LBB2_12
.LBB2_24:                               # %.preheader.preheader
	movl	$10, %r15d
.LBB2_25:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_27
# %bb.26:                               #   in Loop: Header=BB2_25 Depth=1
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm1
	movss	.LCPI2_1(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	callq	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff
.LBB2_27:                               #   in Loop: Header=BB2_25 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB2_21
# %bb.28:                               #   in Loop: Header=BB2_25 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_30
# %bb.29:                               #   in Loop: Header=BB2_25 Depth=1
	movq	24(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movss	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	callq	_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
.LBB2_30:                               #   in Loop: Header=BB2_25 Depth=1
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB2_33
# %bb.31:                               #   in Loop: Header=BB2_25 Depth=1
	movq	16(%rsp), %rax
	movq	8(%rsp), %rcx
	movq	%rcx, 16(%rsp)
	movq	%rax, 8(%rsp)
	decl	%r15d
	jne	.LBB2_25
# %bb.32:
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB2_13
.LBB2_33:
	movl	%eax, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.6, %esi
	movl	$35, %edx
	jmp	.LBB2_22
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f,@object # @_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.section	.rodata,"a",@progbits
	.globl	_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.p2align	3, 0x0
_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f:
	.quad	_Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.size	_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f, 8

	.type	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff,@object # @_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.globl	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.p2align	3, 0x0
_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff:
	.quad	_Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.size	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Error setting device: "
	.size	.L.str, 23

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Error allocating Unified Memory for positions: "
	.size	.L.str.1, 48

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Error allocating Unified Memory for velocities: "
	.size	.L.str.2, 49

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Error allocating Unified Memory for forces: "
	.size	.L.str.3, 45

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Error allocating Unified Memory for newForces: "
	.size	.L.str.4, 48

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Error in computeForces kernel: "
	.size	.L.str.5, 32

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Error in verletIntegration kernel: "
	.size	.L.str.6, 36

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f"
	.size	.L__unnamed_1, 57

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff"
	.size	.L__unnamed_2, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.addrsig_sym _Z28__device_stub__computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.addrsig_sym _Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f ; -- Begin function _Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.globl	_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
	.p2align	8
	.type	_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f,@function
_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f: ; @_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x800, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b32 s0, s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 4, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v11, v[5:6], off
	v_add_co_u32 v9, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v12, v[7:8], off
	global_load_b96 v[0:2], v[9:10], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v11, 0.5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v13, null, s0, s0, v11
	v_rcp_f32_e32 v14, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v13, v14, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v15, v14
	v_div_scale_f32 v16, vcc_lo, v11, s0, v11
	v_mul_f32_e32 v15, v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v13, v15, v16
	v_fmac_f32_e32 v15, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v13, v15, v16
	v_div_fmas_f32 v13, v13, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v11, v13, s0, v11
	v_mul_f32_e32 v11, 0x3c23d70a, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x3c23d70a, v11
	s_waitcnt vmcnt(1)
	v_fmac_f32_e32 v11, 0x3c23d70a, v12
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v11
	global_store_b32 v[9:10], v0, off
	global_load_b32 v0, v[5:6], off offset:4
	global_load_b32 v11, v[7:8], off offset:4
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v0, 0.5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v12, null, s0, s0, v0
	v_div_scale_f32 v15, vcc_lo, v0, s0, v0
	v_rcp_f32_e32 v13, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v12, v13, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v14, v13
	v_mul_f32_e32 v14, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, -v12, v14, v15
	v_fmac_f32_e32 v14, v16, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v12, v14, v15
	v_div_fmas_f32 v12, v12, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v12, s0, v0
	v_mul_f32_e32 v0, 0x3c23d70a, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, 0x3c23d70a, v0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, 0x3c23d70a, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v0
	global_store_b32 v[9:10], v0, off offset:4
	global_load_b32 v0, v[5:6], off offset:8
	global_load_b32 v1, v[7:8], off offset:8
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v0, 0.5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v11, null, s0, s0, v0
	v_div_scale_f32 v14, vcc_lo, v0, s0, v0
	v_rcp_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v11, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v12
	v_mul_f32_e32 v13, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, -v11, v13, v14
	v_fmac_f32_e32 v13, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, -v11, v13, v14
	v_div_fmas_f32 v11, v11, v12, v13
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v11, s0, v0
	v_mul_f32_e32 v0, 0x3c23d70a, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, 0x3c23d70a, v0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, 0x3c23d70a, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v2, v0
	global_store_b32 v[9:10], v0, off offset:8
	global_load_b32 v9, v[5:6], off
	global_load_b32 v10, v[3:4], off
	global_load_b96 v[0:2], v[7:8], off
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, 0.5, v9
	v_div_scale_f32 v10, null, s0, s0, v9
	v_div_scale_f32 v13, vcc_lo, v9, s0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v10, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v11, v12
	v_div_fixup_f32 v9, v10, s0, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v0, v9, 0x3c23d70a, v0
	global_store_b32 v[7:8], v0, off
	global_load_b32 v0, v[5:6], off offset:4
	global_load_b32 v9, v[3:4], off offset:4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, 0.5, v0
	v_div_scale_f32 v9, null, s0, s0, v0
	v_div_scale_f32 v12, vcc_lo, v0, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v12, v10
	v_fma_f32 v13, -v9, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v13, v10
	v_fma_f32 v9, -v9, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v10, v11
	v_div_fixup_f32 v0, v9, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v0, v0, 0x3c23d70a, v1
	global_store_b32 v[7:8], v0, off offset:4
	global_load_b32 v0, v[5:6], off offset:8
	global_load_b32 v1, v[3:4], off offset:8
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, 0.5, v0
	v_div_scale_f32 v1, null, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v1, v3, 1.0
	v_fmac_f32_e32 v3, v4, v3
	v_div_scale_f32 v4, vcc_lo, v0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v4, v3
	v_fma_f32 v6, -v1, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v3
	v_fma_f32 v1, -v1, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v3, v5
	v_div_fixup_f32 v0, v1, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x3c23d70a, v0
	global_store_b32 v[7:8], v2, off offset:8
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f, .Lfunc_end0-_Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1108
; NumSgprs: 18
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff ; -- Begin function _Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.globl	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
	.p2align	8
	.type	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff,@function
_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff: ; @_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x800, v6
	s_cbranch_execz .LBB1_7
; %bb.1:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s0, s[0:1], 0x10
	v_ashrrev_i32_e32 v7, 31, v6
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 0
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 4, v[6:7]
	v_mov_b32_e32 v1, v0
	v_mov_b32_e32 v2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v4, vcc_lo
	v_mul_f32_e64 v11, s2, s2
	v_mul_f32_e64 v12, 0x41c00000, s0
	v_mov_b32_e32 v4, v0
	v_mov_b32_e32 v3, v0
	s_add_u32 s2, s4, 4
	s_addc_u32 s3, s5, 0
	global_store_b96 v[7:8], v[0:2], off
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s4, exec_lo
	v_cmpx_ne_u32_e64 s1, v6
	s_cbranch_execz .LBB1_6
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	global_load_b96 v[13:15], v0, s[2:3] offset:-4
	global_load_b96 v[16:18], v[9:10], off
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v1, v14, v17 :: v_dual_sub_f32 v2, v15, v18
	v_sub_f32_e32 v13, v13, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, v1, v1
	v_fmac_f32_e32 v14, v13, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v2, v2
	v_cmpx_lt_f32_e32 v14, v11
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mul_f32_e32 v15, v14, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v14, v15
	v_mul_f32_e32 v16, v15, v15
	v_div_scale_f32 v18, null, v15, v15, -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v17, null, v16, v16, 2.0
	v_rcp_f32_e32 v20, v18
	v_div_scale_f32 v23, vcc_lo, 2.0, v16, 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v18, v20, 1.0
	v_fma_f32 v21, -v17, v19, 1.0
	v_dual_fmac_f32 v20, v22, v20 :: v_dual_fmac_f32 v19, v21, v19
	v_div_scale_f32 v21, s0, -1.0, v15, -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, v23, v19
	v_mul_f32_e32 v24, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v17, v22, v23
	v_fma_f32 v26, -v18, v24, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v25, v19
	v_fma_f32 v17, -v17, v22, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v17, v17, v19, v22
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v16, v17, v16, 2.0
	v_fmac_f32_e32 v24, v26, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v18, -v18, v24, v21
	v_div_fmas_f32 v18, v18, v20, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v15, v18, v15, -1.0
	v_add_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v12, v15
	v_div_scale_f32 v16, null, v14, v14, v15
	v_div_scale_f32 v19, vcc_lo, v15, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v16, v17, 1.0
	v_fmac_f32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v17
	v_fma_f32 v20, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v20, v17
	v_fma_f32 v16, -v16, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v16, v16, v17, v18
	v_div_fixup_f32 v14, v16, v14, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v13, v14
	v_fmac_f32_e32 v4, v1, v14
	v_fmac_f32_e32 v5, v2, v14
	global_store_b96 v[7:8], v[3:5], off
.LBB1_5:                                ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s1, s1, 1
	s_add_u32 s2, s2, 16
	s_addc_u32 s3, s3, 0
	s_cmpk_lg_i32 s1, 0x800
	s_cbranch_scc1 .LBB1_2
.LBB1_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff, .Lfunc_end1-_Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 640
; NumSgprs: 18
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17verletIntegrationP15HIP_vector_typeIfLj4EES1_S1_S1_f.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13computeForcesP15HIP_vector_typeIfLj4EES1_fff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
