#include <iostream>
#include <cuda_runtime.h>
#include <curand_kernel.h>

// Constants for the neural network
#define LAYERS 8
#define NEURONS 1024
#define THREADS_PER_BLOCK 256

// Kernel to initialize weights and biases
__global__ void initialize(curandState *state, float *weights, float *biases, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        curandState localState = state[idx];
        weights[idx] = curand_normal(&localState) * 0.01f;
        biases[idx] = curand_normal(&localState) * 0.01f;
        state[idx] = localState;
    }
}

// Forward pass kernel
__global__ void forward(float *inputs, float *weights, float *biases, float *outputs, int layer) {
    extern __shared__ float sharedMem[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int neuronIdx = threadIdx.x;

    if (neuronIdx < NEURONS) {
        float sum = biases[layer * NEURONS + neuronIdx];
        for (int i = 0; i < NEURONS; i += blockDim.x) {
            int inputIdx = i + threadIdx.x;
            if (inputIdx < NEURONS) {
                sharedMem[threadIdx.x] = inputs[inputIdx];
                __syncthreads();
                sum += sharedMem[threadIdx.x] * weights[(layer * NEURONS + neuronIdx) * NEURONS + inputIdx];
                __syncthreads();
            }
        }
        outputs[neuronIdx] = tanhf(sum);
    }
}

// Backward pass kernel
__global__ void backward(float *deltas, float *weights, float *deltasPrev, int layer) {
    extern __shared__ float sharedMem[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int neuronIdx = threadIdx.x;

    if (neuronIdx < NEURONS) {
        float sum = 0.0f;
        for (int i = 0; i < NEURONS; i += blockDim.x) {
            int nextIdx = i + threadIdx.x;
            if (nextIdx < NEURONS) {
                sharedMem[threadIdx.x] = deltas[nextIdx] * weights[(layer * NEURONS + nextIdx) * NEURONS + neuronIdx];
                __syncthreads();
                sum += sharedMem[threadIdx.x];
                __syncthreads();
            }
        }
        deltasPrev[neuronIdx] = sum * (1.0f - deltasPrev[neuronIdx] * deltasPrev[neuronIdx]);
    }
}

// Main function to demonstrate the usage of the kernels
int main() {
    int size = LAYERS * NEURONS * NEURONS;
    int dataSize = NEURONS;

    // Allocate memory for weights, biases, inputs, outputs, and deltas
    float *h_weights, *h_biases, *h_inputs, *h_outputs, *h_deltas;
    float *d_weights, *d_biases, *d_inputs, *d_outputs, *d_deltas;
    curandState *d_state;

    h_weights = (float *)malloc(size * sizeof(float));
    h_biases = (float *)malloc(LAYERS * NEURONS * sizeof(float));
    h_inputs = (float *)malloc(dataSize * sizeof(float));
    h_outputs = (float *)malloc(dataSize * sizeof(float));
    h_deltas = (float *)malloc(dataSize * sizeof(float));

    cudaMalloc((void **)&d_weights, size * sizeof(float));
    cudaMalloc((void **)&d_biases, LAYERS * NEURONS * sizeof(float));
    cudaMalloc((void **)&d_inputs, dataSize * sizeof(float));
    cudaMalloc((void **)&d_outputs, dataSize * sizeof(float));
    cudaMalloc((void **)&d_deltas, dataSize * sizeof(float));
    cudaMalloc((void **)&d_state, dataSize * sizeof(curandState));

    // Initialize inputs
    for (int i = 0; i < dataSize; i++) {
        h_inputs[i] = static_cast<float>(rand()) / RAND_MAX;
    }

    // Initialize curand states
    int blocks = (dataSize + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK;
    initialize<<<blocks, THREADS_PER_BLOCK>>>(d_state, d_weights, d_biases, size);
    cudaDeviceSynchronize();

    // Copy inputs to device
    cudaMemcpy(d_inputs, h_inputs, dataSize * sizeof(float), cudaMemcpyHostToDevice);

    // Forward pass
    for (int l = 0; l < LAYERS; l++) {
        forward<<<blocks, THREADS_PER_BLOCK, THREADS_PER_BLOCK * sizeof(float)>>>(
            (l == 0) ? d_inputs : d_outputs, d_weights, d_biases, d_outputs, l);
        cudaDeviceSynchronize();
    }

    // Backward pass
    for (int l = LAYERS - 1; l >= 0; l--) {
        if (l == LAYERS - 1) {
            // Assume some loss derivative for the last layer
            cudaMemcpy(d_deltas, d_outputs, dataSize * sizeof(float), cudaMemcpyDeviceToDevice);
            for (int i = 0; i < dataSize; i++) {
                h_deltas[i] = 1.0f - h_outputs[i] * h_outputs[i]; // Derivative of tanh
            }
            cudaMemcpy(d_deltas, h_deltas, dataSize * sizeof(float), cudaMemcpyHostToDevice);
        }
        backward<<<blocks, THREADS_PER_BLOCK, THREADS_PER_BLOCK * sizeof(float)>>>(
            d_deltas, d_weights, (l == 0) ? d_deltas : d_deltas, l);
        cudaDeviceSynchronize();
    }

    // Free memory
    free(h_weights);
    free(h_biases);
    free(h_inputs);
    free(h_outputs);
    free(h_deltas);
    cudaFree(d_weights);
    cudaFree(d_biases);
    cudaFree(d_inputs);
    cudaFree(d_outputs);
    cudaFree(d_deltas);
    cudaFree(d_state);

    return 0;
}
	.file	"tmpxft_0007a12b_00000000-6_cuda_code_035613.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3852:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3852:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z54__device_stub__Z10initializeP17curandStateXORWOWPfS1_iP17curandStateXORWOWPfS1_i
	.type	_Z54__device_stub__Z10initializeP17curandStateXORWOWPfS1_iP17curandStateXORWOWPfS1_i, @function
_Z54__device_stub__Z10initializeP17curandStateXORWOWPfS1_iP17curandStateXORWOWPfS1_i:
.LFB3874:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10initializeP17curandStateXORWOWPfS1_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3874:
	.size	_Z54__device_stub__Z10initializeP17curandStateXORWOWPfS1_iP17curandStateXORWOWPfS1_i, .-_Z54__device_stub__Z10initializeP17curandStateXORWOWPfS1_iP17curandStateXORWOWPfS1_i
	.globl	_Z10initializeP17curandStateXORWOWPfS1_i
	.type	_Z10initializeP17curandStateXORWOWPfS1_i, @function
_Z10initializeP17curandStateXORWOWPfS1_i:
.LFB3875:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z10initializeP17curandStateXORWOWPfS1_iP17curandStateXORWOWPfS1_i
	.cfi_endproc
.LFE3875:
	.size	_Z10initializeP17curandStateXORWOWPfS1_i, .-_Z10initializeP17curandStateXORWOWPfS1_i
	.globl	_Z33__device_stub__Z7forwardPfS_S_S_iPfS_S_S_i
	.type	_Z33__device_stub__Z7forwardPfS_S_S_iPfS_S_S_i, @function
_Z33__device_stub__Z7forwardPfS_S_S_iPfS_S_S_i:
.LFB3876:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z7forwardPfS_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L8:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3876:
	.size	_Z33__device_stub__Z7forwardPfS_S_S_iPfS_S_S_i, .-_Z33__device_stub__Z7forwardPfS_S_S_iPfS_S_S_i
	.globl	_Z7forwardPfS_S_S_i
	.type	_Z7forwardPfS_S_S_i, @function
_Z7forwardPfS_S_S_i:
.LFB3877:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z7forwardPfS_S_S_iPfS_S_S_i
	.cfi_endproc
.LFE3877:
	.size	_Z7forwardPfS_S_S_i, .-_Z7forwardPfS_S_S_i
	.globl	_Z32__device_stub__Z8backwardPfS_S_iPfS_S_i
	.type	_Z32__device_stub__Z8backwardPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8backwardPfS_S_iPfS_S_i:
.LFB3878:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8backwardPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3878:
	.size	_Z32__device_stub__Z8backwardPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8backwardPfS_S_iPfS_S_i
	.globl	_Z8backwardPfS_S_i
	.type	_Z8backwardPfS_S_i, @function
_Z8backwardPfS_S_i:
.LFB3879:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8backwardPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3879:
	.size	_Z8backwardPfS_S_i, .-_Z8backwardPfS_S_i
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3849:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$4096, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4096, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$4096, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rsp, %rdi
	movl	$33554432, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$32768, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$49152, %esi
	call	cudaMalloc@PLT
.L19:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC0(%rip), %xmm0
	movss	%xmm0, 0(%rbp,%r12,4)
	incq	%r12
	cmpq	$1024, %r12
	jne	.L19
	movl	$16777217, %edx
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	8(%rsp), %rdx
	movq	(%rsp), %rsi
	movl	$8388608, %ecx
	movq	40(%rsp), %rdi
	call	_Z54__device_stub__Z10initializeP17curandStateXORWOWPfS1_iP17curandStateXORWOWPfS1_i
.L20:
	call	cudaDeviceSynchronize@PLT
	movq	%rbp, %rsi
	xorl	%r12d, %r12d
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$4096, %edx
	movabsq	$4294967552, %r14
	call	cudaMemcpy@PLT
.L23:
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	movq	%r14, %rdx
	movl	$1, %ecx
	salq	$2, %rdi
	movl	$1024, %r8d
	movl	$1, %esi
	movq	%r14, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	24(%rsp), %rcx
	movq	8(%rsp), %rdx
	movq	(%rsp), %rsi
	movq	%rcx, %rdi
	testl	%r12d, %r12d
	jne	.L22
	movq	16(%rsp), %rdi
.L22:
	movl	%r12d, %r8d
	call	_Z33__device_stub__Z7forwardPfS_S_S_iPfS_S_S_i
.L21:
	call	cudaDeviceSynchronize@PLT
	incl	%r12d
	cmpl	$8, %r12d
	jne	.L23
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	$3, %ecx
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movss	.LC1(%rip), %xmm2
	xorl	%eax, %eax
.L24:
	movss	0(%r13,%rax), %xmm0
	movaps	%xmm2, %xmm1
	mulss	%xmm0, %xmm0
	subss	%xmm0, %xmm1
	movss	%xmm1, (%rbx,%rax)
	addq	$4, %rax
	cmpq	$4096, %rax
	jne	.L24
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$4096, %edx
	movq	%rbx, %rsi
	movabsq	$4294967552, %r14
	movl	$7, %r12d
	call	cudaMemcpy@PLT
.L26:
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	movq	%r14, %rdx
	movl	$1, %ecx
	salq	$2, %rdi
	movl	$1024, %r8d
	movl	$1, %esi
	movq	%r14, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	32(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	%r12d, %ecx
	movq	%rdi, %rdx
	call	_Z32__device_stub__Z8backwardPfS_S_iPfS_S_i
.L25:
	call	cudaDeviceSynchronize@PLT
	subl	$1, %r12d
	jnb	.L26
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3849:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z8backwardPfS_S_i"
.LC3:
	.string	"_Z7forwardPfS_S_S_i"
.LC4:
	.string	"_Z10initializeP17curandStateXORWOWPfS1_i"
.LC5:
	.string	"precalc_xorwow_matrix"
.LC6:
	.string	"precalc_xorwow_offset_matrix"
.LC7:
	.string	"mrg32k3aM1"
.LC8:
	.string	"mrg32k3aM2"
.LC9:
	.string	"mrg32k3aM1SubSeq"
.LC10:
	.string	"mrg32k3aM2SubSeq"
.LC11:
	.string	"mrg32k3aM1Seq"
.LC12:
	.string	"mrg32k3aM2Seq"
.LC13:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3881:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8backwardPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7forwardPfS_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10initializeP17curandStateXORWOWPfS1_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3881:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	805306368
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

// Constants for the neural network
#define LAYERS 8
#define NEURONS 1024
#define THREADS_PER_BLOCK 256

// Kernel to initialize weights and biases
__global__ void initialize(hiprandState *state, float *weights, float *biases, int size) {
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    if (idx < size) {
        hiprandState localState = state[idx];
        weights[idx] = hiprand_normal(&localState) * 0.01f;
        biases[idx] = hiprand_normal(&localState) * 0.01f;
        state[idx] = localState;
    }
}

// Forward pass kernel
__global__ void forward(float *inputs, float *weights, float *biases, float *outputs, int layer) {
    extern __shared__ float sharedMem[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int neuronIdx = threadIdx.x;

    if (neuronIdx < NEURONS) {
        float sum = biases[layer * NEURONS + neuronIdx];
        for (int i = 0; i < NEURONS; i += blockDim.x) {
            int inputIdx = i + threadIdx.x;
            if (inputIdx < NEURONS) {
                sharedMem[threadIdx.x] = inputs[inputIdx];
                __syncthreads();
                sum += sharedMem[threadIdx.x] * weights[(layer * NEURONS + neuronIdx) * NEURONS + inputIdx];
                __syncthreads();
            }
        }
        outputs[neuronIdx] = tanhf(sum);
    }
}

// Backward pass kernel
__global__ void backward(float *deltas, float *weights, float *deltasPrev, int layer) {
    extern __shared__ float sharedMem[];
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int neuronIdx = threadIdx.x;

    if (neuronIdx < NEURONS) {
        float sum = 0.0f;
        for (int i = 0; i < NEURONS; i += blockDim.x) {
            int nextIdx = i + threadIdx.x;
            if (nextIdx < NEURONS) {
                sharedMem[threadIdx.x] = deltas[nextIdx] * weights[(layer * NEURONS + nextIdx) * NEURONS + neuronIdx];
                __syncthreads();
                sum += sharedMem[threadIdx.x];
                __syncthreads();
            }
        }
        deltasPrev[neuronIdx] = sum * (1.0f - deltasPrev[neuronIdx] * deltasPrev[neuronIdx]);
    }
}

// Main function to demonstrate the usage of the kernels
int main() {
    int size = LAYERS * NEURONS * NEURONS;
    int dataSize = NEURONS;

    // Allocate memory for weights, biases, inputs, outputs, and deltas
    float *h_weights, *h_biases, *h_inputs, *h_outputs, *h_deltas;
    float *d_weights, *d_biases, *d_inputs, *d_outputs, *d_deltas;
    hiprandState *d_state;

    h_weights = (float *)malloc(size * sizeof(float));
    h_biases = (float *)malloc(LAYERS * NEURONS * sizeof(float));
    h_inputs = (float *)malloc(dataSize * sizeof(float));
    h_outputs = (float *)malloc(dataSize * sizeof(float));
    h_deltas = (float *)malloc(dataSize * sizeof(float));

    hipMalloc((void **)&d_weights, size * sizeof(float));
    hipMalloc((void **)&d_biases, LAYERS * NEURONS * sizeof(float));
    hipMalloc((void **)&d_inputs, dataSize * sizeof(float));
    hipMalloc((void **)&d_outputs, dataSize * sizeof(float));
    hipMalloc((void **)&d_deltas, dataSize * sizeof(float));
    hipMalloc((void **)&d_state, dataSize * sizeof(hiprandState));

    // Initialize inputs
    for (int i = 0; i < dataSize; i++) {
        h_inputs[i] = static_cast<float>(rand()) / RAND_MAX;
    }

    // Initialize curand states
    int blocks = (dataSize + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK;
    initialize<<<blocks, THREADS_PER_BLOCK>>>(d_state, d_weights, d_biases, size);
    hipDeviceSynchronize();

    // Copy inputs to device
    hipMemcpy(d_inputs, h_inputs, dataSize * sizeof(float), hipMemcpyHostToDevice);

    // Forward pass
    for (int l = 0; l < LAYERS; l++) {
        forward<<<blocks, THREADS_PER_BLOCK, THREADS_PER_BLOCK * sizeof(float)>>>(
            (l == 0) ? d_inputs : d_outputs, d_weights, d_biases, d_outputs, l);
        hipDeviceSynchronize();
    }

    // Backward pass
    for (int l = LAYERS - 1; l >= 0; l--) {
        if (l == LAYERS - 1) {
            // Assume some loss derivative for the last layer
            hipMemcpy(d_deltas, d_outputs, dataSize * sizeof(float), hipMemcpyDeviceToDevice);
            for (int i = 0; i < dataSize; i++) {
                h_deltas[i] = 1.0f - h_outputs[i] * h_outputs[i]; // Derivative of tanh
            }
            hipMemcpy(d_deltas, h_deltas, dataSize * sizeof(float), hipMemcpyHostToDevice);
        }
        backward<<<blocks, THREADS_PER_BLOCK, THREADS_PER_BLOCK * sizeof(float)>>>(
            d_deltas, d_weights, (l == 0) ? d_deltas : d_deltas, l);
        hipDeviceSynchronize();
    }

    // Free memory
    free(h_weights);
    free(h_biases);
    free(h_inputs);
    free(h_outputs);
    free(h_deltas);
    hipFree(d_weights);
    hipFree(d_biases);
    hipFree(d_inputs);
    hipFree(d_outputs);
    hipFree(d_deltas);
    hipFree(d_state);

    return 0;
}
	.text
	.file	"cuda_code_035613.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__initializeP12hiprandStatePfS1_i # -- Begin function _Z25__device_stub__initializeP12hiprandStatePfS1_i
	.type	_Z25__device_stub__initializeP12hiprandStatePfS1_i,@function
_Z25__device_stub__initializeP12hiprandStatePfS1_i: # @_Z25__device_stub__initializeP12hiprandStatePfS1_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10initializeP12hiprandStatePfS1_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__initializeP12hiprandStatePfS1_i, .Lfunc_end0-_Z25__device_stub__initializeP12hiprandStatePfS1_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__forwardPfS_S_S_i # -- Begin function _Z22__device_stub__forwardPfS_S_S_i
	.type	_Z22__device_stub__forwardPfS_S_S_i,@function
_Z22__device_stub__forwardPfS_S_S_i:    # @_Z22__device_stub__forwardPfS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7forwardPfS_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__forwardPfS_S_S_i, .Lfunc_end1-_Z22__device_stub__forwardPfS_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__backwardPfS_S_i # -- Begin function _Z23__device_stub__backwardPfS_S_i
	.type	_Z23__device_stub__backwardPfS_S_i,@function
_Z23__device_stub__backwardPfS_S_i:     # @_Z23__device_stub__backwardPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8backwardPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__backwardPfS_S_i, .Lfunc_end2-_Z23__device_stub__backwardPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI3_1:
	.long	0x3f800000                      # float 1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %rbx
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r14
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r15
	leaq	16(%rsp), %rdi
	movl	$33554432, %esi                 # imm = 0x2000000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$32768, %esi                    # imm = 0x8000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$49152, %esi                    # imm = 0xC000
	callq	hipMalloc
	xorl	%r12d, %r12d
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI3_0(%rip), %xmm0
	movss	%xmm0, (%rbx,%r12,4)
	incq	%r12
	cmpq	$1024, %r12                     # imm = 0x400
	jne	.LBB3_1
# %bb.2:
	movabsq	$4294967300, %r12               # imm = 0x100000004
	leaq	252(%r12), %r13
	xorl	%ebp, %ebp
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	48(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdx
	movl	$8388608, %ecx                  # imm = 0x800000
	callq	_Z25__device_stub__initializeP12hiprandStatePfS1_i
.LBB3_4:
	callq	hipDeviceSynchronize
	movq	32(%rsp), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.LBB3_5:                                # =>This Inner Loop Header: Depth=1
	movl	$1024, %r8d                     # imm = 0x400
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.6:                                #   in Loop: Header=BB3_5 Depth=1
	movq	24(%rsp), %rcx
	movq	%rcx, %rdi
	testl	%ebp, %ebp
	jne	.LBB3_8
# %bb.7:                                #   in Loop: Header=BB3_5 Depth=1
	movq	32(%rsp), %rdi
.LBB3_8:                                #   in Loop: Header=BB3_5 Depth=1
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdx
	movl	%ebp, %r8d
	callq	_Z22__device_stub__forwardPfS_S_S_i
.LBB3_9:                                #   in Loop: Header=BB3_5 Depth=1
	callq	hipDeviceSynchronize
	incl	%ebp
	cmpl	$8, %ebp
	jne	.LBB3_5
# %bb.10:                               # %.preheader.preheader
	movl	$7, %ebp
.LBB3_11:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_13 Depth 2
	cmpl	$7, %ebp
	jne	.LBB3_15
# %bb.12:                               #   in Loop: Header=BB3_11 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movl	$3, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
	movss	.LCPI3_1(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
.LBB3_13:                               #   Parent Loop BB3_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r14,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	mulss	%xmm0, %xmm0
	movaps	%xmm2, %xmm1
	subss	%xmm0, %xmm1
	movss	%xmm1, (%r15,%rax,4)
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB3_13
# %bb.14:                               #   in Loop: Header=BB3_11 Depth=1
	movq	8(%rsp), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.LBB3_15:                               #   in Loop: Header=BB3_11 Depth=1
	movl	$1024, %r8d                     # imm = 0x400
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_17
# %bb.16:                               #   in Loop: Header=BB3_11 Depth=1
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	%rdi, %rdx
	movl	%ebp, %ecx
	callq	_Z23__device_stub__backwardPfS_S_i
.LBB3_17:                               #   in Loop: Header=BB3_11 Depth=1
	callq	hipDeviceSynchronize
	subl	$1, %ebp
	jae	.LBB3_11
# %bb.18:
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10initializeP12hiprandStatePfS1_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7forwardPfS_S_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8backwardPfS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10initializeP12hiprandStatePfS1_i,@object # @_Z10initializeP12hiprandStatePfS1_i
	.section	.rodata,"a",@progbits
	.globl	_Z10initializeP12hiprandStatePfS1_i
	.p2align	3, 0x0
_Z10initializeP12hiprandStatePfS1_i:
	.quad	_Z25__device_stub__initializeP12hiprandStatePfS1_i
	.size	_Z10initializeP12hiprandStatePfS1_i, 8

	.type	_Z7forwardPfS_S_S_i,@object     # @_Z7forwardPfS_S_S_i
	.globl	_Z7forwardPfS_S_S_i
	.p2align	3, 0x0
_Z7forwardPfS_S_S_i:
	.quad	_Z22__device_stub__forwardPfS_S_S_i
	.size	_Z7forwardPfS_S_S_i, 8

	.type	_Z8backwardPfS_S_i,@object      # @_Z8backwardPfS_S_i
	.globl	_Z8backwardPfS_S_i
	.p2align	3, 0x0
_Z8backwardPfS_S_i:
	.quad	_Z23__device_stub__backwardPfS_S_i
	.size	_Z8backwardPfS_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10initializeP12hiprandStatePfS1_i"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7forwardPfS_S_S_i"
	.size	.L__unnamed_2, 20

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8backwardPfS_S_i"
	.size	.L__unnamed_3, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__initializeP12hiprandStatePfS1_i
	.addrsig_sym _Z22__device_stub__forwardPfS_S_S_i
	.addrsig_sym _Z23__device_stub__backwardPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10initializeP12hiprandStatePfS1_i
	.addrsig_sym _Z7forwardPfS_S_S_i
	.addrsig_sym _Z8backwardPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10initializeP12hiprandStatePfS1_i ; -- Begin function _Z10initializeP12hiprandStatePfS1_i
	.globl	_Z10initializeP12hiprandStatePfS1_i
	.p2align	8
	.type	_Z10initializeP12hiprandStatePfS1_i,@function
_Z10initializeP12hiprandStatePfS1_i:    ; @_Z10initializeP12hiprandStatePfS1_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v14
	s_cbranch_execz .LBB0_6
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v15, 31, v14
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[8:9], null, v14, 48, s[4:5]
	s_clause 0x3
	global_load_b128 v[4:7], v[8:9], off
	global_load_b128 v[0:3], v[8:9], off offset:24
	global_load_b64 v[10:11], v[8:9], off offset:40
	global_load_b64 v[12:13], v[8:9], off offset:16
	s_waitcnt vmcnt(3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	v_cmp_eq_u32_e64 s0, 0, v5
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v16, v2 :: v_dual_mov_b32 v5, v7
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_lshrrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v5, v0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v5, 4, v10
	v_lshlrev_b32_e32 v7, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v7, v5
	v_xor3_b32 v5, v5, v0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v4, v5, 0x587c5
	v_add_nc_u32_e32 v4, 0xb0f8a, v4
	v_cvt_f32_u32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
	v_cmp_gt_f32_e64 s0, 0x800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 1.0, 0x4f800000, s0
	v_mul_f32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x3f317217, v0
	v_fma_f32 v16, 0x3f317217, v0, -v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v16, v0, 0x3377d1cf, v16
	v_add_f32_e32 v7, v7, v16
	v_cndmask_b32_e64 v16, 0, 0x41b17218, s0
	v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v7, s0
	v_lshrrev_b32_e32 v7, 2, v1
	v_xor_b32_e32 v1, v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v0, v0, v16 :: v_dual_lshlrev_b32 v7, 1, v1
	v_mul_f32_e32 v0, -2.0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, 0x4f800000, v0
	v_cmp_gt_f32_e64 s0, 0xf800000, v0
	v_cndmask_b32_e64 v0, v0, v16, s0
	v_lshlrev_b32_e32 v16, 4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v17, v0
	v_xor_b32_e32 v7, v7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_xor3_b32 v18, v7, v1, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v1, -1, v17
	v_add_nc_u32_e32 v16, 1, v17
	v_fma_f32 v19, -v1, v17, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v16, v17, v0
	v_cmp_ge_f32_e64 s1, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v17, v1, s1
	v_cmp_lt_f32_e64 s1, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v16, s1
	v_mul_f32_e32 v16, 0x37800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v16, s0
	v_cmp_class_f32_e64 s0, v0, 0x260
	v_cndmask_b32_e64 v19, v1, v0, s0
	v_mov_b32_e32 v1, v3
	v_mov_b32_e32 v3, v5
	v_add_nc_u32_e32 v7, v18, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v7, v7
	v_fmaak_f32 v7, 0x30c90fdb, v7, 0x30c90fdb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, 0.15915494, v7
	v_sin_f32_e32 v17, v7
	v_cos_f32_e32 v7, v7
	v_mov_b32_e32 v16, v10
	v_mov_b32_e32 v0, v2
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v10, v18 :: v_dual_mul_f32 v5, v19, v17
	v_mul_f32_e32 v7, v19, v7
.LBB0_3:                                ; %_Z14hiprand_normalI12hiprandStateEfPT_.exit
	s_or_b32 exec_lo, exec_lo, s4
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v20, 0x3c23d70a, v5 :: v_dual_mov_b32 v5, 0
	v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v17, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s0, s6, v14
	v_add_co_ci_u32_e64 v19, s0, s7, v15, s0
	global_store_b32 v[18:19], v20, off
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_lshrrev_b32_e32 v2, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v2, v0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v2, 4, v10
	v_lshlrev_b32_e32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v5, v2
	v_xor3_b32 v7, v2, v0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v4, v7, 0x587c5
	v_cvt_f32_u32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v2
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x3f317217, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0x3f317217, v0, -v2
	v_fmamk_f32 v5, v0, 0x3377d1cf, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v2, v5
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_lshrrev_b32_e32 v2, 2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v0, v0, v5
	v_xor_b32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, -2.0, v0
	v_dual_mul_f32 v5, 0x4f800000, v0 :: v_dual_lshlrev_b32 v2, 1, v1
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v0, v5 :: v_dual_lshlrev_b32 v5, 4, v7
	v_sqrt_f32_e32 v17, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v5
	v_xor3_b32 v18, v2, v1, v7
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v1, -1, v17
	v_add_nc_u32_e32 v5, 1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v1, v17, v0
	v_fma_f32 v20, -v5, v17, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v19
	v_cndmask_b32_e64 v1, v17, v1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v20
	v_cndmask_b32_e64 v1, v1, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0x37800000, v1
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 0xb0f8a, v4
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v5, 1 :: v_dual_cndmask_b32 v20, v1, v0
	v_dual_mov_b32 v1, v3 :: v_dual_add_nc_u32 v2, v18, v4
	v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, v2
	v_fmaak_f32 v2, 0x30c90fdb, v2, 0x30c90fdb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0.15915494, v2
	v_sin_f32_e32 v17, v2
	v_cos_f32_e32 v19, v2
	v_mov_b32_e32 v2, v10
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v10, v18 :: v_dual_mul_f32 v17, v20, v17
	v_mul_f32_e32 v7, v20, v19
.LBB0_5:                                ; %_Z14hiprand_normalI12hiprandStateEfPT_.exit15
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v16, 0x3c23d70a, v17
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	global_store_b32 v[14:15], v16, off
	global_store_b128 v[8:9], v[4:7], off
	s_waitcnt vmcnt(0)
	s_clause 0x2
	global_store_b64 v[8:9], v[12:13], off offset:16
	global_store_b128 v[8:9], v[0:3], off offset:24
	global_store_b64 v[8:9], v[10:11], off offset:40
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10initializeP12hiprandStatePfS1_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10initializeP12hiprandStatePfS1_i, .Lfunc_end0-_Z10initializeP12hiprandStatePfS1_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1232
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7forwardPfS_S_S_i     ; -- Begin function _Z7forwardPfS_S_S_i
	.globl	_Z7forwardPfS_S_S_i
	.p2align	8
	.type	_Z7forwardPfS_S_S_i,@function
_Z7forwardPfS_S_S_i:                    ; @_Z7forwardPfS_S_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	v_lshl_or_b32 v1, s2, 10, v0
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
	v_lshlrev_b32_e32 v1, 2, v0
	v_mul_u32_u24_e32 v2, 0x401, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 0, v1
	v_add_co_u32 v1, s1, s4, v1
	v_lshl_or_b32 v5, s2, 20, v2
	v_add_co_ci_u32_e64 v2, null, s5, 0, s1
	s_mov_b32 s1, 0
	s_lshl_b32 s2, s0, 2
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v6, s1, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x400, v6
	s_cbranch_execz .LBB1_3
; %bb.2:                                ;   in Loop: Header=BB1_1 Depth=1
	global_load_b32 v8, v[1:2], off
	v_add_nc_u32_e32 v6, s1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_b32 v6, v[6:7], off
	ds_load_b32 v7, v4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v3, v7, v6
.LBB1_3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_co_u32 v1, vcc_lo, v1, s2
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_add_i32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_gt_u32 s1, 0x3ff
	s_cbranch_scc0 .LBB1_1
; %bb.4:
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s0, 0x3f200000, |v3|
                                        ; implicit-def: $vgpr1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_add_f32_e64 v1, |v3|, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0x3fb8aa3b, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
	v_rndne_f32_e32 v4, v2
	v_fma_f32 v5, 0x3fb8aa3b, v1, -v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v2, v2, v4 :: v_dual_fmamk_f32 v5, v1, 0x32a5705f, v5
	v_cvt_i32_f32_e32 v4, v4
	v_add_f32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v2, v4
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7f800000, v2, vcc_lo
	v_add_f32_e32 v1, 1.0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v1, v1, -2.0, 1.0
.LBB1_6:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s0
; %bb.7:
	v_mul_f32_e32 v1, v3, v3
	s_mov_b32 s1, 0xbbbac73d
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fmaak_f32 v2, s1, v1, 0x3ca908c9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbd5c1c4e
	v_fmaak_f32 v2, v1, v2, 0x3e088382
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbeaaaa99
	v_mul_f32_e64 v2, |v3|, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v1, v1, v2, |v3|
; %bb.8:                                ; %_ZL5tanhff.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_bfi_b32 v1, 0x7fffffff, v1, v3
	v_lshlrev_b32_e32 v0, 2, v0
	global_store_b32 v0, v1, s[10:11]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7forwardPfS_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 12
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7forwardPfS_S_S_i, .Lfunc_end1-_Z7forwardPfS_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 596
; NumSgprs: 14
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 14
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8backwardPfS_S_i      ; -- Begin function _Z8backwardPfS_S_i
	.globl	_Z8backwardPfS_S_i
	.p2align	8
	.type	_Z8backwardPfS_S_i,@function
_Z8backwardPfS_S_i:                     ; @_Z8backwardPfS_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 2, v0
	v_mul_u32_u24_e32 v1, 0x401, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0, v2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	v_lshl_or_b32 v1, s3, 20, v1
	v_add_co_u32 v3, s3, s4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, null, s5, 0, s3
	s_mov_b32 s3, 0
	s_lshl_b32 s4, s2, 10
	s_lshl_b32 s5, s2, 2
.LBB2_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s3, v0
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x400, v2
	s_cbranch_execz .LBB2_3
; %bb.2:                                ;   in Loop: Header=BB2_1 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v2, v[3:4], off
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v2, v7
	ds_store_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_add_f32_e32 v5, v5, v2
.LBB2_3:                                ;   in Loop: Header=BB2_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_add_co_u32 v3, vcc_lo, v3, s5
	v_add_nc_u32_e32 v1, s4, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_gt_u32 s3, 0x3ff
	s_cbranch_scc0 .LBB2_1
; %bb.4:
	v_lshlrev_b32_e32 v0, 2, v0
	global_load_b32 v1, v0, s[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f32 v1, -v1, v1, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, v5, v1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8backwardPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 9
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8backwardPfS_S_i, .Lfunc_end2-_Z8backwardPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 11
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 11
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10initializeP12hiprandStatePfS1_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10initializeP12hiprandStatePfS1_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7forwardPfS_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     14
    .sgpr_spill_count: 0
    .symbol:         _Z7forwardPfS_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8backwardPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     11
    .sgpr_spill_count: 0
    .symbol:         _Z8backwardPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
